1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 2,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
39 def SDT_ARMBr2JT : SDTypeProfile<0, 3,
40 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
43 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
45 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
46 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
47 SDTCisVT<5, OtherVT>]>;
49 def SDT_ARMAnd : SDTypeProfile<1, 2,
50 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
53 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
55 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
56 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
58 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
59 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
61 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
62 def SDT_ARMEH_SJLJ_SetupDispatch: SDTypeProfile<0, 0, []>;
64 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
66 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
69 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
71 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def SDT_WIN__DBZCHK : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
76 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
79 SDTCisInt<0>, SDTCisVT<1, i32>]>;
81 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
82 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
89 def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>,
90 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
91 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >;
92 def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
93 def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>;
96 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
97 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
98 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntUnaryOp>;
100 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
101 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
102 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
103 [SDNPHasChain, SDNPSideEffect,
104 SDNPOptInGlue, SDNPOutGlue]>;
105 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
107 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
108 SDNPMayStore, SDNPMayLoad]>;
110 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
111 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
113 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
114 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
116 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
117 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
120 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
121 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
122 def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall,
123 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
124 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
127 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
128 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
130 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
132 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
135 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
138 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
141 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
144 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
145 [SDNPOutGlue, SDNPCommutative]>;
147 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
149 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
150 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
151 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
153 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
155 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
156 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
157 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
159 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
160 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
161 SDT_ARMEH_SJLJ_Setjmp,
162 [SDNPHasChain, SDNPSideEffect]>;
163 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
164 SDT_ARMEH_SJLJ_Longjmp,
165 [SDNPHasChain, SDNPSideEffect]>;
166 def ARMeh_sjlj_setup_dispatch: SDNode<"ARMISD::EH_SJLJ_SETUP_DISPATCH",
167 SDT_ARMEH_SJLJ_SetupDispatch,
168 [SDNPHasChain, SDNPSideEffect]>;
170 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
171 [SDNPHasChain, SDNPSideEffect]>;
172 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
173 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
175 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
177 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
178 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
180 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
182 //===----------------------------------------------------------------------===//
183 // ARM Instruction Predicate Definitions.
185 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
186 AssemblerPredicate<"HasV4TOps", "armv4t">;
187 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
188 def HasV5T : Predicate<"Subtarget->hasV5TOps()">,
189 AssemblerPredicate<"HasV5TOps", "armv5t">;
190 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
191 AssemblerPredicate<"HasV5TEOps", "armv5te">;
192 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
193 AssemblerPredicate<"HasV6Ops", "armv6">;
194 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
195 def HasV6M : Predicate<"Subtarget->hasV6MOps()">,
196 AssemblerPredicate<"HasV6MOps",
197 "armv6m or armv6t2">;
198 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
199 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
200 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
201 def HasV6K : Predicate<"Subtarget->hasV6KOps()">,
202 AssemblerPredicate<"HasV6KOps", "armv6k">;
203 def NoV6K : Predicate<"!Subtarget->hasV6KOps()">;
204 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
205 AssemblerPredicate<"HasV7Ops", "armv7">;
206 def HasV8 : Predicate<"Subtarget->hasV8Ops()">,
207 AssemblerPredicate<"HasV8Ops", "armv8">;
208 def PreV8 : Predicate<"!Subtarget->hasV8Ops()">,
209 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">;
210 def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">,
211 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">;
212 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
213 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
214 AssemblerPredicate<"FeatureVFP2", "VFP2">;
215 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
216 AssemblerPredicate<"FeatureVFP3", "VFP3">;
217 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
218 AssemblerPredicate<"FeatureVFP4", "VFP4">;
219 def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">,
220 AssemblerPredicate<"!FeatureVFPOnlySP",
221 "double precision VFP">;
222 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
223 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">;
224 def HasNEON : Predicate<"Subtarget->hasNEON()">,
225 AssemblerPredicate<"FeatureNEON", "NEON">;
226 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
227 AssemblerPredicate<"FeatureCrypto", "crypto">;
228 def HasCRC : Predicate<"Subtarget->hasCRC()">,
229 AssemblerPredicate<"FeatureCRC", "crc">;
230 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
231 AssemblerPredicate<"FeatureFP16","half-float">;
232 def HasDivide : Predicate<"Subtarget->hasDivide()">,
233 AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">;
234 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
235 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">;
236 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
237 AssemblerPredicate<"FeatureT2XtPk",
239 def HasDSP : Predicate<"Subtarget->hasDSP()">,
240 AssemblerPredicate<"FeatureDSP", "dsp">;
241 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
242 AssemblerPredicate<"FeatureDB",
244 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
245 AssemblerPredicate<"FeatureMP",
247 def HasVirtualization: Predicate<"false">,
248 AssemblerPredicate<"FeatureVirtualization",
249 "virtualization-extensions">;
250 def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
251 AssemblerPredicate<"FeatureTrustZone",
253 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
254 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
255 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
256 def IsThumb : Predicate<"Subtarget->isThumb()">,
257 AssemblerPredicate<"ModeThumb", "thumb">;
258 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
259 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
260 AssemblerPredicate<"ModeThumb,FeatureThumb2",
262 def IsMClass : Predicate<"Subtarget->isMClass()">,
263 AssemblerPredicate<"FeatureMClass", "armv*m">;
264 def IsNotMClass : Predicate<"!Subtarget->isMClass()">,
265 AssemblerPredicate<"!FeatureMClass",
267 def IsARM : Predicate<"!Subtarget->isThumb()">,
268 AssemblerPredicate<"!ModeThumb", "arm-mode">;
269 def IsMachO : Predicate<"Subtarget->isTargetMachO()">;
270 def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">;
271 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
272 def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
273 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
274 def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
276 // FIXME: Eventually this will be just "hasV6T2Ops".
277 def UseMovt : Predicate<"Subtarget->useMovt(*MF)">;
278 def DontUseMovt : Predicate<"!Subtarget->useMovt(*MF)">;
279 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
280 def UseMulOps : Predicate<"Subtarget->useMulOps()">;
282 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
283 // But only select them if more precision in FP computation is allowed.
284 // Do not use them for Darwin platforms.
285 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
286 " FPOpFusion::Fast && "
287 " Subtarget->hasVFP4()) && "
288 "!Subtarget->isTargetDarwin()">;
289 def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion =="
290 " FPOpFusion::Fast &&"
291 " Subtarget->hasVFP4()) || "
292 "Subtarget->isTargetDarwin()">;
294 // VGETLNi32 is microcoded on Swift - prefer VMOV.
295 def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
296 def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
298 // VDUP.32 is microcoded on Swift - prefer VMOV.
299 def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
300 def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
302 // Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as
303 // this allows more effective execution domain optimization. See
304 // setExecutionDomain().
305 def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;
306 def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;
308 def IsLE : Predicate<"MF->getDataLayout().isLittleEndian()">;
309 def IsBE : Predicate<"MF->getDataLayout().isBigEndian()">;
311 //===----------------------------------------------------------------------===//
312 // ARM Flag Definitions.
314 class RegConstraint<string C> {
315 string Constraints = C;
318 //===----------------------------------------------------------------------===//
319 // ARM specific transformation functions and pattern fragments.
322 // imm_neg_XFORM - Return the negation of an i32 immediate value.
323 def imm_neg_XFORM : SDNodeXForm<imm, [{
324 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), SDLoc(N), MVT::i32);
327 // imm_not_XFORM - Return the complement of a i32 immediate value.
328 def imm_not_XFORM : SDNodeXForm<imm, [{
329 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), SDLoc(N), MVT::i32);
332 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
333 def imm16_31 : ImmLeaf<i32, [{
334 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
337 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
338 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
339 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
342 /// Split a 32-bit immediate into two 16 bit parts.
343 def hi16 : SDNodeXForm<imm, [{
344 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, SDLoc(N),
348 def lo16AllZero : PatLeaf<(i32 imm), [{
349 // Returns true if all low 16-bits are 0.
350 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
353 class BinOpWithFlagFrag<dag res> :
354 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
355 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
356 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
358 // An 'and' node with a single use.
359 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
360 return N->hasOneUse();
363 // An 'xor' node with a single use.
364 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
365 return N->hasOneUse();
368 // An 'fmul' node with a single use.
369 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
370 return N->hasOneUse();
373 // An 'fadd' node which checks for single non-hazardous use.
374 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
375 return hasNoVMLxHazardUse(N);
378 // An 'fsub' node which checks for single non-hazardous use.
379 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
380 return hasNoVMLxHazardUse(N);
383 //===----------------------------------------------------------------------===//
384 // Operand Definitions.
387 // Immediate operands with a shared generic asm render method.
388 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
390 // Operands that are part of a memory addressing mode.
391 class MemOperand : Operand<i32> { let OperandType = "OPERAND_MEMORY"; }
394 // FIXME: rename brtarget to t2_brtarget
395 def brtarget : Operand<OtherVT> {
396 let EncoderMethod = "getBranchTargetOpValue";
397 let OperandType = "OPERAND_PCREL";
398 let DecoderMethod = "DecodeT2BROperand";
401 // FIXME: get rid of this one?
402 def uncondbrtarget : Operand<OtherVT> {
403 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
404 let OperandType = "OPERAND_PCREL";
407 // Branch target for ARM. Handles conditional/unconditional
408 def br_target : Operand<OtherVT> {
409 let EncoderMethod = "getARMBranchTargetOpValue";
410 let OperandType = "OPERAND_PCREL";
414 // FIXME: rename bltarget to t2_bl_target?
415 def bltarget : Operand<i32> {
416 // Encoded the same as branch targets.
417 let EncoderMethod = "getBranchTargetOpValue";
418 let OperandType = "OPERAND_PCREL";
421 // Call target for ARM. Handles conditional/unconditional
422 // FIXME: rename bl_target to t2_bltarget?
423 def bl_target : Operand<i32> {
424 let EncoderMethod = "getARMBLTargetOpValue";
425 let OperandType = "OPERAND_PCREL";
428 def blx_target : Operand<i32> {
429 let EncoderMethod = "getARMBLXTargetOpValue";
430 let OperandType = "OPERAND_PCREL";
433 // A list of registers separated by comma. Used by load/store multiple.
434 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
435 def reglist : Operand<i32> {
436 let EncoderMethod = "getRegisterListOpValue";
437 let ParserMatchClass = RegListAsmOperand;
438 let PrintMethod = "printRegisterList";
439 let DecoderMethod = "DecodeRegListOperand";
442 def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
444 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
445 def dpr_reglist : Operand<i32> {
446 let EncoderMethod = "getRegisterListOpValue";
447 let ParserMatchClass = DPRRegListAsmOperand;
448 let PrintMethod = "printRegisterList";
449 let DecoderMethod = "DecodeDPRRegListOperand";
452 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
453 def spr_reglist : Operand<i32> {
454 let EncoderMethod = "getRegisterListOpValue";
455 let ParserMatchClass = SPRRegListAsmOperand;
456 let PrintMethod = "printRegisterList";
457 let DecoderMethod = "DecodeSPRRegListOperand";
460 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
461 def cpinst_operand : Operand<i32> {
462 let PrintMethod = "printCPInstOperand";
466 def pclabel : Operand<i32> {
467 let PrintMethod = "printPCLabel";
470 // ADR instruction labels.
471 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
472 def adrlabel : Operand<i32> {
473 let EncoderMethod = "getAdrLabelOpValue";
474 let ParserMatchClass = AdrLabelAsmOperand;
475 let PrintMethod = "printAdrLabelOperand<0>";
478 def neon_vcvt_imm32 : Operand<i32> {
479 let EncoderMethod = "getNEONVcvtImm32OpValue";
480 let DecoderMethod = "DecodeVCVTImmOperand";
483 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
484 def rot_imm_XFORM: SDNodeXForm<imm, [{
485 switch (N->getZExtValue()){
486 default: llvm_unreachable(nullptr);
487 case 0: return CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
488 case 8: return CurDAG->getTargetConstant(1, SDLoc(N), MVT::i32);
489 case 16: return CurDAG->getTargetConstant(2, SDLoc(N), MVT::i32);
490 case 24: return CurDAG->getTargetConstant(3, SDLoc(N), MVT::i32);
493 def RotImmAsmOperand : AsmOperandClass {
495 let ParserMethod = "parseRotImm";
497 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
498 int32_t v = N->getZExtValue();
499 return v == 8 || v == 16 || v == 24; }],
501 let PrintMethod = "printRotImmOperand";
502 let ParserMatchClass = RotImmAsmOperand;
505 // shift_imm: An integer that encodes a shift amount and the type of shift
506 // (asr or lsl). The 6-bit immediate encodes as:
509 // {4-0} imm5 shift amount.
510 // asr #32 encoded as imm5 == 0.
511 def ShifterImmAsmOperand : AsmOperandClass {
512 let Name = "ShifterImm";
513 let ParserMethod = "parseShifterImm";
515 def shift_imm : Operand<i32> {
516 let PrintMethod = "printShiftImmOperand";
517 let ParserMatchClass = ShifterImmAsmOperand;
520 // shifter_operand operands: so_reg_reg, so_reg_imm, and mod_imm.
521 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
522 def so_reg_reg : Operand<i32>, // reg reg imm
523 ComplexPattern<i32, 3, "SelectRegShifterOperand",
524 [shl, srl, sra, rotr]> {
525 let EncoderMethod = "getSORegRegOpValue";
526 let PrintMethod = "printSORegRegOperand";
527 let DecoderMethod = "DecodeSORegRegOperand";
528 let ParserMatchClass = ShiftedRegAsmOperand;
529 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
532 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
533 def so_reg_imm : Operand<i32>, // reg imm
534 ComplexPattern<i32, 2, "SelectImmShifterOperand",
535 [shl, srl, sra, rotr]> {
536 let EncoderMethod = "getSORegImmOpValue";
537 let PrintMethod = "printSORegImmOperand";
538 let DecoderMethod = "DecodeSORegImmOperand";
539 let ParserMatchClass = ShiftedImmAsmOperand;
540 let MIOperandInfo = (ops GPR, i32imm);
543 // FIXME: Does this need to be distinct from so_reg?
544 def shift_so_reg_reg : Operand<i32>, // reg reg imm
545 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
546 [shl,srl,sra,rotr]> {
547 let EncoderMethod = "getSORegRegOpValue";
548 let PrintMethod = "printSORegRegOperand";
549 let DecoderMethod = "DecodeSORegRegOperand";
550 let ParserMatchClass = ShiftedRegAsmOperand;
551 let MIOperandInfo = (ops GPR, GPR, i32imm);
554 // FIXME: Does this need to be distinct from so_reg?
555 def shift_so_reg_imm : Operand<i32>, // reg reg imm
556 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
557 [shl,srl,sra,rotr]> {
558 let EncoderMethod = "getSORegImmOpValue";
559 let PrintMethod = "printSORegImmOperand";
560 let DecoderMethod = "DecodeSORegImmOperand";
561 let ParserMatchClass = ShiftedImmAsmOperand;
562 let MIOperandInfo = (ops GPR, i32imm);
565 // mod_imm: match a 32-bit immediate operand, which can be encoded into
566 // a 12-bit immediate; an 8-bit integer and a 4-bit rotator (See ARMARM
567 // - "Modified Immediate Constants"). Within the MC layer we keep this
568 // immediate in its encoded form.
569 def ModImmAsmOperand: AsmOperandClass {
571 let ParserMethod = "parseModImm";
573 def mod_imm : Operand<i32>, ImmLeaf<i32, [{
574 return ARM_AM::getSOImmVal(Imm) != -1;
576 let EncoderMethod = "getModImmOpValue";
577 let PrintMethod = "printModImmOperand";
578 let ParserMatchClass = ModImmAsmOperand;
581 // Note: the patterns mod_imm_not and mod_imm_neg do not require an encoder
582 // method and such, as they are only used on aliases (Pat<> and InstAlias<>).
583 // The actual parsing, encoding, decoding are handled by the destination
584 // instructions, which use mod_imm.
586 def ModImmNotAsmOperand : AsmOperandClass { let Name = "ModImmNot"; }
587 def mod_imm_not : Operand<i32>, PatLeaf<(imm), [{
588 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
590 let ParserMatchClass = ModImmNotAsmOperand;
593 def ModImmNegAsmOperand : AsmOperandClass { let Name = "ModImmNeg"; }
594 def mod_imm_neg : Operand<i32>, PatLeaf<(imm), [{
595 unsigned Value = -(unsigned)N->getZExtValue();
596 return Value && ARM_AM::getSOImmVal(Value) != -1;
598 let ParserMatchClass = ModImmNegAsmOperand;
601 /// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal()
602 def arm_i32imm : PatLeaf<(imm), [{
603 if (Subtarget->useMovt(*MF))
605 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
608 /// imm0_1 predicate - Immediate in the range [0,1].
609 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
610 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
612 /// imm0_3 predicate - Immediate in the range [0,3].
613 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
614 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
616 /// imm0_7 predicate - Immediate in the range [0,7].
617 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
618 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
619 return Imm >= 0 && Imm < 8;
621 let ParserMatchClass = Imm0_7AsmOperand;
624 /// imm8 predicate - Immediate is exactly 8.
625 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
626 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
627 let ParserMatchClass = Imm8AsmOperand;
630 /// imm16 predicate - Immediate is exactly 16.
631 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
632 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
633 let ParserMatchClass = Imm16AsmOperand;
636 /// imm32 predicate - Immediate is exactly 32.
637 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
638 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
639 let ParserMatchClass = Imm32AsmOperand;
642 def imm8_or_16 : ImmLeaf<i32, [{ return Imm == 8 || Imm == 16;}]>;
644 /// imm1_7 predicate - Immediate in the range [1,7].
645 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
646 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
647 let ParserMatchClass = Imm1_7AsmOperand;
650 /// imm1_15 predicate - Immediate in the range [1,15].
651 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
652 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
653 let ParserMatchClass = Imm1_15AsmOperand;
656 /// imm1_31 predicate - Immediate in the range [1,31].
657 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
658 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
659 let ParserMatchClass = Imm1_31AsmOperand;
662 /// imm0_15 predicate - Immediate in the range [0,15].
663 def Imm0_15AsmOperand: ImmAsmOperand {
664 let Name = "Imm0_15";
665 let DiagnosticType = "ImmRange0_15";
667 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
668 return Imm >= 0 && Imm < 16;
670 let ParserMatchClass = Imm0_15AsmOperand;
673 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
674 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
675 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
676 return Imm >= 0 && Imm < 32;
678 let ParserMatchClass = Imm0_31AsmOperand;
681 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
682 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
683 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
684 return Imm >= 0 && Imm < 32;
686 let ParserMatchClass = Imm0_32AsmOperand;
689 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
690 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
691 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
692 return Imm >= 0 && Imm < 64;
694 let ParserMatchClass = Imm0_63AsmOperand;
697 /// imm0_239 predicate - Immediate in the range [0,239].
698 def Imm0_239AsmOperand : ImmAsmOperand {
699 let Name = "Imm0_239";
700 let DiagnosticType = "ImmRange0_239";
702 def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> {
703 let ParserMatchClass = Imm0_239AsmOperand;
706 /// imm0_255 predicate - Immediate in the range [0,255].
707 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
708 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
709 let ParserMatchClass = Imm0_255AsmOperand;
712 /// imm0_65535 - An immediate is in the range [0.65535].
713 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
714 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
715 return Imm >= 0 && Imm < 65536;
717 let ParserMatchClass = Imm0_65535AsmOperand;
720 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
721 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
722 return -Imm >= 0 && -Imm < 65536;
725 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
726 // a relocatable expression.
728 // FIXME: This really needs a Thumb version separate from the ARM version.
729 // While the range is the same, and can thus use the same match class,
730 // the encoding is different so it should have a different encoder method.
731 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
732 def imm0_65535_expr : Operand<i32> {
733 let EncoderMethod = "getHiLo16ImmOpValue";
734 let ParserMatchClass = Imm0_65535ExprAsmOperand;
737 def Imm256_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm256_65535Expr"; }
738 def imm256_65535_expr : Operand<i32> {
739 let ParserMatchClass = Imm256_65535ExprAsmOperand;
742 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
743 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
744 def imm24b : Operand<i32>, ImmLeaf<i32, [{
745 return Imm >= 0 && Imm <= 0xffffff;
747 let ParserMatchClass = Imm24bitAsmOperand;
751 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
753 def BitfieldAsmOperand : AsmOperandClass {
754 let Name = "Bitfield";
755 let ParserMethod = "parseBitfield";
758 def bf_inv_mask_imm : Operand<i32>,
760 return ARM::isBitFieldInvertedMask(N->getZExtValue());
762 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
763 let PrintMethod = "printBitfieldInvMaskImmOperand";
764 let DecoderMethod = "DecodeBitfieldMaskOperand";
765 let ParserMatchClass = BitfieldAsmOperand;
768 def imm1_32_XFORM: SDNodeXForm<imm, [{
769 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N),
772 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
773 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
774 uint64_t Imm = N->getZExtValue();
775 return Imm > 0 && Imm <= 32;
778 let PrintMethod = "printImmPlusOneOperand";
779 let ParserMatchClass = Imm1_32AsmOperand;
782 def imm1_16_XFORM: SDNodeXForm<imm, [{
783 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N),
786 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
787 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
789 let PrintMethod = "printImmPlusOneOperand";
790 let ParserMatchClass = Imm1_16AsmOperand;
793 // Define ARM specific addressing modes.
794 // addrmode_imm12 := reg +/- imm12
796 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
797 class AddrMode_Imm12 : MemOperand,
798 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
799 // 12-bit immediate operand. Note that instructions using this encode
800 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
801 // immediate values are as normal.
803 let EncoderMethod = "getAddrModeImm12OpValue";
804 let DecoderMethod = "DecodeAddrModeImm12Operand";
805 let ParserMatchClass = MemImm12OffsetAsmOperand;
806 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
809 def addrmode_imm12 : AddrMode_Imm12 {
810 let PrintMethod = "printAddrModeImm12Operand<false>";
813 def addrmode_imm12_pre : AddrMode_Imm12 {
814 let PrintMethod = "printAddrModeImm12Operand<true>";
817 // ldst_so_reg := reg +/- reg shop imm
819 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
820 def ldst_so_reg : MemOperand,
821 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
822 let EncoderMethod = "getLdStSORegOpValue";
823 // FIXME: Simplify the printer
824 let PrintMethod = "printAddrMode2Operand";
825 let DecoderMethod = "DecodeSORegMemOperand";
826 let ParserMatchClass = MemRegOffsetAsmOperand;
827 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
830 // postidx_imm8 := +/- [0,255]
833 // {8} 1 is imm8 is non-negative. 0 otherwise.
834 // {7-0} [0,255] imm8 value.
835 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
836 def postidx_imm8 : MemOperand {
837 let PrintMethod = "printPostIdxImm8Operand";
838 let ParserMatchClass = PostIdxImm8AsmOperand;
839 let MIOperandInfo = (ops i32imm);
842 // postidx_imm8s4 := +/- [0,1020]
845 // {8} 1 is imm8 is non-negative. 0 otherwise.
846 // {7-0} [0,255] imm8 value, scaled by 4.
847 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
848 def postidx_imm8s4 : MemOperand {
849 let PrintMethod = "printPostIdxImm8s4Operand";
850 let ParserMatchClass = PostIdxImm8s4AsmOperand;
851 let MIOperandInfo = (ops i32imm);
855 // postidx_reg := +/- reg
857 def PostIdxRegAsmOperand : AsmOperandClass {
858 let Name = "PostIdxReg";
859 let ParserMethod = "parsePostIdxReg";
861 def postidx_reg : MemOperand {
862 let EncoderMethod = "getPostIdxRegOpValue";
863 let DecoderMethod = "DecodePostIdxReg";
864 let PrintMethod = "printPostIdxRegOperand";
865 let ParserMatchClass = PostIdxRegAsmOperand;
866 let MIOperandInfo = (ops GPRnopc, i32imm);
870 // addrmode2 := reg +/- imm12
871 // := reg +/- reg shop imm
873 // FIXME: addrmode2 should be refactored the rest of the way to always
874 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
875 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
876 def addrmode2 : MemOperand,
877 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
878 let EncoderMethod = "getAddrMode2OpValue";
879 let PrintMethod = "printAddrMode2Operand";
880 let ParserMatchClass = AddrMode2AsmOperand;
881 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
884 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
885 let Name = "PostIdxRegShifted";
886 let ParserMethod = "parsePostIdxReg";
888 def am2offset_reg : MemOperand,
889 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
890 [], [SDNPWantRoot]> {
891 let EncoderMethod = "getAddrMode2OffsetOpValue";
892 let PrintMethod = "printAddrMode2OffsetOperand";
893 // When using this for assembly, it's always as a post-index offset.
894 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
895 let MIOperandInfo = (ops GPRnopc, i32imm);
898 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
899 // the GPR is purely vestigal at this point.
900 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
901 def am2offset_imm : MemOperand,
902 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
903 [], [SDNPWantRoot]> {
904 let EncoderMethod = "getAddrMode2OffsetOpValue";
905 let PrintMethod = "printAddrMode2OffsetOperand";
906 let ParserMatchClass = AM2OffsetImmAsmOperand;
907 let MIOperandInfo = (ops GPRnopc, i32imm);
911 // addrmode3 := reg +/- reg
912 // addrmode3 := reg +/- imm8
914 // FIXME: split into imm vs. reg versions.
915 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
916 class AddrMode3 : MemOperand,
917 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
918 let EncoderMethod = "getAddrMode3OpValue";
919 let ParserMatchClass = AddrMode3AsmOperand;
920 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
923 def addrmode3 : AddrMode3
925 let PrintMethod = "printAddrMode3Operand<false>";
928 def addrmode3_pre : AddrMode3
930 let PrintMethod = "printAddrMode3Operand<true>";
933 // FIXME: split into imm vs. reg versions.
934 // FIXME: parser method to handle +/- register.
935 def AM3OffsetAsmOperand : AsmOperandClass {
936 let Name = "AM3Offset";
937 let ParserMethod = "parseAM3Offset";
939 def am3offset : MemOperand,
940 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
941 [], [SDNPWantRoot]> {
942 let EncoderMethod = "getAddrMode3OffsetOpValue";
943 let PrintMethod = "printAddrMode3OffsetOperand";
944 let ParserMatchClass = AM3OffsetAsmOperand;
945 let MIOperandInfo = (ops GPR, i32imm);
948 // ldstm_mode := {ia, ib, da, db}
950 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
951 let EncoderMethod = "getLdStmModeOpValue";
952 let PrintMethod = "printLdStmModeOperand";
955 // addrmode5 := reg +/- imm8*4
957 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
958 class AddrMode5 : MemOperand,
959 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
960 let EncoderMethod = "getAddrMode5OpValue";
961 let DecoderMethod = "DecodeAddrMode5Operand";
962 let ParserMatchClass = AddrMode5AsmOperand;
963 let MIOperandInfo = (ops GPR:$base, i32imm);
966 def addrmode5 : AddrMode5 {
967 let PrintMethod = "printAddrMode5Operand<false>";
970 def addrmode5_pre : AddrMode5 {
971 let PrintMethod = "printAddrMode5Operand<true>";
974 // addrmode6 := reg with optional alignment
976 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
977 def addrmode6 : MemOperand,
978 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
979 let PrintMethod = "printAddrMode6Operand";
980 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
981 let EncoderMethod = "getAddrMode6AddressOpValue";
982 let DecoderMethod = "DecodeAddrMode6Operand";
983 let ParserMatchClass = AddrMode6AsmOperand;
986 def am6offset : MemOperand,
987 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
988 [], [SDNPWantRoot]> {
989 let PrintMethod = "printAddrMode6OffsetOperand";
990 let MIOperandInfo = (ops GPR);
991 let EncoderMethod = "getAddrMode6OffsetOpValue";
992 let DecoderMethod = "DecodeGPRRegisterClass";
995 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
996 // (single element from one lane) for size 32.
997 def addrmode6oneL32 : MemOperand,
998 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
999 let PrintMethod = "printAddrMode6Operand";
1000 let MIOperandInfo = (ops GPR:$addr, i32imm);
1001 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
1004 // Base class for addrmode6 with specific alignment restrictions.
1005 class AddrMode6Align : MemOperand,
1006 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1007 let PrintMethod = "printAddrMode6Operand";
1008 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
1009 let EncoderMethod = "getAddrMode6AddressOpValue";
1010 let DecoderMethod = "DecodeAddrMode6Operand";
1013 // Special version of addrmode6 to handle no allowed alignment encoding for
1014 // VLD/VST instructions and checking the alignment is not specified.
1015 def AddrMode6AlignNoneAsmOperand : AsmOperandClass {
1016 let Name = "AlignedMemoryNone";
1017 let DiagnosticType = "AlignedMemoryRequiresNone";
1019 def addrmode6alignNone : AddrMode6Align {
1020 // The alignment specifier can only be omitted.
1021 let ParserMatchClass = AddrMode6AlignNoneAsmOperand;
1024 // Special version of addrmode6 to handle 16-bit alignment encoding for
1025 // VLD/VST instructions and checking the alignment value.
1026 def AddrMode6Align16AsmOperand : AsmOperandClass {
1027 let Name = "AlignedMemory16";
1028 let DiagnosticType = "AlignedMemoryRequires16";
1030 def addrmode6align16 : AddrMode6Align {
1031 // The alignment specifier can only be 16 or omitted.
1032 let ParserMatchClass = AddrMode6Align16AsmOperand;
1035 // Special version of addrmode6 to handle 32-bit alignment encoding for
1036 // VLD/VST instructions and checking the alignment value.
1037 def AddrMode6Align32AsmOperand : AsmOperandClass {
1038 let Name = "AlignedMemory32";
1039 let DiagnosticType = "AlignedMemoryRequires32";
1041 def addrmode6align32 : AddrMode6Align {
1042 // The alignment specifier can only be 32 or omitted.
1043 let ParserMatchClass = AddrMode6Align32AsmOperand;
1046 // Special version of addrmode6 to handle 64-bit alignment encoding for
1047 // VLD/VST instructions and checking the alignment value.
1048 def AddrMode6Align64AsmOperand : AsmOperandClass {
1049 let Name = "AlignedMemory64";
1050 let DiagnosticType = "AlignedMemoryRequires64";
1052 def addrmode6align64 : AddrMode6Align {
1053 // The alignment specifier can only be 64 or omitted.
1054 let ParserMatchClass = AddrMode6Align64AsmOperand;
1057 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1058 // for VLD/VST instructions and checking the alignment value.
1059 def AddrMode6Align64or128AsmOperand : AsmOperandClass {
1060 let Name = "AlignedMemory64or128";
1061 let DiagnosticType = "AlignedMemoryRequires64or128";
1063 def addrmode6align64or128 : AddrMode6Align {
1064 // The alignment specifier can only be 64, 128 or omitted.
1065 let ParserMatchClass = AddrMode6Align64or128AsmOperand;
1068 // Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment
1069 // encoding for VLD/VST instructions and checking the alignment value.
1070 def AddrMode6Align64or128or256AsmOperand : AsmOperandClass {
1071 let Name = "AlignedMemory64or128or256";
1072 let DiagnosticType = "AlignedMemoryRequires64or128or256";
1074 def addrmode6align64or128or256 : AddrMode6Align {
1075 // The alignment specifier can only be 64, 128, 256 or omitted.
1076 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand;
1079 // Special version of addrmode6 to handle alignment encoding for VLD-dup
1080 // instructions, specifically VLD4-dup.
1081 def addrmode6dup : MemOperand,
1082 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1083 let PrintMethod = "printAddrMode6Operand";
1084 let MIOperandInfo = (ops GPR:$addr, i32imm);
1085 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1086 // FIXME: This is close, but not quite right. The alignment specifier is
1088 let ParserMatchClass = AddrMode6AsmOperand;
1091 // Base class for addrmode6dup with specific alignment restrictions.
1092 class AddrMode6DupAlign : MemOperand,
1093 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1094 let PrintMethod = "printAddrMode6Operand";
1095 let MIOperandInfo = (ops GPR:$addr, i32imm);
1096 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1099 // Special version of addrmode6 to handle no allowed alignment encoding for
1100 // VLD-dup instruction and checking the alignment is not specified.
1101 def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass {
1102 let Name = "DupAlignedMemoryNone";
1103 let DiagnosticType = "DupAlignedMemoryRequiresNone";
1105 def addrmode6dupalignNone : AddrMode6DupAlign {
1106 // The alignment specifier can only be omitted.
1107 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand;
1110 // Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup
1111 // instruction and checking the alignment value.
1112 def AddrMode6dupAlign16AsmOperand : AsmOperandClass {
1113 let Name = "DupAlignedMemory16";
1114 let DiagnosticType = "DupAlignedMemoryRequires16";
1116 def addrmode6dupalign16 : AddrMode6DupAlign {
1117 // The alignment specifier can only be 16 or omitted.
1118 let ParserMatchClass = AddrMode6dupAlign16AsmOperand;
1121 // Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup
1122 // instruction and checking the alignment value.
1123 def AddrMode6dupAlign32AsmOperand : AsmOperandClass {
1124 let Name = "DupAlignedMemory32";
1125 let DiagnosticType = "DupAlignedMemoryRequires32";
1127 def addrmode6dupalign32 : AddrMode6DupAlign {
1128 // The alignment specifier can only be 32 or omitted.
1129 let ParserMatchClass = AddrMode6dupAlign32AsmOperand;
1132 // Special version of addrmode6 to handle 64-bit alignment encoding for VLD
1133 // instructions and checking the alignment value.
1134 def AddrMode6dupAlign64AsmOperand : AsmOperandClass {
1135 let Name = "DupAlignedMemory64";
1136 let DiagnosticType = "DupAlignedMemoryRequires64";
1138 def addrmode6dupalign64 : AddrMode6DupAlign {
1139 // The alignment specifier can only be 64 or omitted.
1140 let ParserMatchClass = AddrMode6dupAlign64AsmOperand;
1143 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1144 // for VLD instructions and checking the alignment value.
1145 def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass {
1146 let Name = "DupAlignedMemory64or128";
1147 let DiagnosticType = "DupAlignedMemoryRequires64or128";
1149 def addrmode6dupalign64or128 : AddrMode6DupAlign {
1150 // The alignment specifier can only be 64, 128 or omitted.
1151 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand;
1154 // addrmodepc := pc + reg
1156 def addrmodepc : MemOperand,
1157 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
1158 let PrintMethod = "printAddrModePCOperand";
1159 let MIOperandInfo = (ops GPR, i32imm);
1162 // addr_offset_none := reg
1164 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
1165 def addr_offset_none : MemOperand,
1166 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
1167 let PrintMethod = "printAddrMode7Operand";
1168 let DecoderMethod = "DecodeAddrMode7Operand";
1169 let ParserMatchClass = MemNoOffsetAsmOperand;
1170 let MIOperandInfo = (ops GPR:$base);
1173 def nohash_imm : Operand<i32> {
1174 let PrintMethod = "printNoHashImmediate";
1177 def CoprocNumAsmOperand : AsmOperandClass {
1178 let Name = "CoprocNum";
1179 let ParserMethod = "parseCoprocNumOperand";
1181 def p_imm : Operand<i32> {
1182 let PrintMethod = "printPImmediate";
1183 let ParserMatchClass = CoprocNumAsmOperand;
1184 let DecoderMethod = "DecodeCoprocessor";
1187 def CoprocRegAsmOperand : AsmOperandClass {
1188 let Name = "CoprocReg";
1189 let ParserMethod = "parseCoprocRegOperand";
1191 def c_imm : Operand<i32> {
1192 let PrintMethod = "printCImmediate";
1193 let ParserMatchClass = CoprocRegAsmOperand;
1195 def CoprocOptionAsmOperand : AsmOperandClass {
1196 let Name = "CoprocOption";
1197 let ParserMethod = "parseCoprocOptionOperand";
1199 def coproc_option_imm : Operand<i32> {
1200 let PrintMethod = "printCoprocOptionImm";
1201 let ParserMatchClass = CoprocOptionAsmOperand;
1204 //===----------------------------------------------------------------------===//
1206 include "ARMInstrFormats.td"
1208 //===----------------------------------------------------------------------===//
1209 // Multiclass helpers...
1212 /// AsI1_bin_irs - Defines a set of (op r, {mod_imm|r|so_reg}) patterns for a
1213 /// binop that produces a value.
1214 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1215 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
1216 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1217 PatFrag opnode, bit Commutable = 0> {
1218 // The register-immediate version is re-materializable. This is useful
1219 // in particular for taking the address of a local.
1220 let isReMaterializable = 1 in {
1221 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1222 iii, opc, "\t$Rd, $Rn, $imm",
1223 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
1224 Sched<[WriteALU, ReadALU]> {
1229 let Inst{19-16} = Rn;
1230 let Inst{15-12} = Rd;
1231 let Inst{11-0} = imm;
1234 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1235 iir, opc, "\t$Rd, $Rn, $Rm",
1236 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1237 Sched<[WriteALU, ReadALU, ReadALU]> {
1242 let isCommutable = Commutable;
1243 let Inst{19-16} = Rn;
1244 let Inst{15-12} = Rd;
1245 let Inst{11-4} = 0b00000000;
1249 def rsi : AsI1<opcod, (outs GPR:$Rd),
1250 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1251 iis, opc, "\t$Rd, $Rn, $shift",
1252 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1253 Sched<[WriteALUsi, ReadALU]> {
1258 let Inst{19-16} = Rn;
1259 let Inst{15-12} = Rd;
1260 let Inst{11-5} = shift{11-5};
1262 let Inst{3-0} = shift{3-0};
1265 def rsr : AsI1<opcod, (outs GPR:$Rd),
1266 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1267 iis, opc, "\t$Rd, $Rn, $shift",
1268 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1269 Sched<[WriteALUsr, ReadALUsr]> {
1274 let Inst{19-16} = Rn;
1275 let Inst{15-12} = Rd;
1276 let Inst{11-8} = shift{11-8};
1278 let Inst{6-5} = shift{6-5};
1280 let Inst{3-0} = shift{3-0};
1284 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1285 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1286 /// it is equivalent to the AsI1_bin_irs counterpart.
1287 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1288 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1289 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1290 PatFrag opnode, bit Commutable = 0> {
1291 // The register-immediate version is re-materializable. This is useful
1292 // in particular for taking the address of a local.
1293 let isReMaterializable = 1 in {
1294 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1295 iii, opc, "\t$Rd, $Rn, $imm",
1296 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>,
1297 Sched<[WriteALU, ReadALU]> {
1302 let Inst{19-16} = Rn;
1303 let Inst{15-12} = Rd;
1304 let Inst{11-0} = imm;
1307 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1308 iir, opc, "\t$Rd, $Rn, $Rm",
1309 [/* pattern left blank */]>,
1310 Sched<[WriteALU, ReadALU, ReadALU]> {
1314 let Inst{11-4} = 0b00000000;
1317 let Inst{15-12} = Rd;
1318 let Inst{19-16} = Rn;
1321 def rsi : AsI1<opcod, (outs GPR:$Rd),
1322 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1323 iis, opc, "\t$Rd, $Rn, $shift",
1324 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1325 Sched<[WriteALUsi, ReadALU]> {
1330 let Inst{19-16} = Rn;
1331 let Inst{15-12} = Rd;
1332 let Inst{11-5} = shift{11-5};
1334 let Inst{3-0} = shift{3-0};
1337 def rsr : AsI1<opcod, (outs GPR:$Rd),
1338 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1339 iis, opc, "\t$Rd, $Rn, $shift",
1340 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1341 Sched<[WriteALUsr, ReadALUsr]> {
1346 let Inst{19-16} = Rn;
1347 let Inst{15-12} = Rd;
1348 let Inst{11-8} = shift{11-8};
1350 let Inst{6-5} = shift{6-5};
1352 let Inst{3-0} = shift{3-0};
1356 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1358 /// These opcodes will be converted to the real non-S opcodes by
1359 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1360 let hasPostISelHook = 1, Defs = [CPSR] in {
1361 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1362 InstrItinClass iis, PatFrag opnode,
1363 bit Commutable = 0> {
1364 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1366 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>,
1367 Sched<[WriteALU, ReadALU]>;
1369 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1371 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1372 Sched<[WriteALU, ReadALU, ReadALU]> {
1373 let isCommutable = Commutable;
1375 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1376 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1378 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1379 so_reg_imm:$shift))]>,
1380 Sched<[WriteALUsi, ReadALU]>;
1382 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1383 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1385 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1386 so_reg_reg:$shift))]>,
1387 Sched<[WriteALUSsr, ReadALUsr]>;
1391 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1392 /// operands are reversed.
1393 let hasPostISelHook = 1, Defs = [CPSR] in {
1394 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1395 InstrItinClass iis, PatFrag opnode,
1396 bit Commutable = 0> {
1397 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1399 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>,
1400 Sched<[WriteALU, ReadALU]>;
1402 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1403 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1405 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1407 Sched<[WriteALUsi, ReadALU]>;
1409 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1410 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1412 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1414 Sched<[WriteALUSsr, ReadALUsr]>;
1418 /// AI1_cmp_irs - Defines a set of (op r, {mod_imm|r|so_reg}) cmp / test
1419 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1420 /// a explicit result, only implicitly set CPSR.
1421 let isCompare = 1, Defs = [CPSR] in {
1422 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1423 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1424 PatFrag opnode, bit Commutable = 0,
1425 string rrDecoderMethod = ""> {
1426 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii,
1428 [(opnode GPR:$Rn, mod_imm:$imm)]>,
1429 Sched<[WriteCMP, ReadALU]> {
1434 let Inst{19-16} = Rn;
1435 let Inst{15-12} = 0b0000;
1436 let Inst{11-0} = imm;
1438 let Unpredictable{15-12} = 0b1111;
1440 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1442 [(opnode GPR:$Rn, GPR:$Rm)]>,
1443 Sched<[WriteCMP, ReadALU, ReadALU]> {
1446 let isCommutable = Commutable;
1449 let Inst{19-16} = Rn;
1450 let Inst{15-12} = 0b0000;
1451 let Inst{11-4} = 0b00000000;
1453 let DecoderMethod = rrDecoderMethod;
1455 let Unpredictable{15-12} = 0b1111;
1457 def rsi : AI1<opcod, (outs),
1458 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1459 opc, "\t$Rn, $shift",
1460 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1461 Sched<[WriteCMPsi, ReadALU]> {
1466 let Inst{19-16} = Rn;
1467 let Inst{15-12} = 0b0000;
1468 let Inst{11-5} = shift{11-5};
1470 let Inst{3-0} = shift{3-0};
1472 let Unpredictable{15-12} = 0b1111;
1474 def rsr : AI1<opcod, (outs),
1475 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1476 opc, "\t$Rn, $shift",
1477 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
1478 Sched<[WriteCMPsr, ReadALU]> {
1483 let Inst{19-16} = Rn;
1484 let Inst{15-12} = 0b0000;
1485 let Inst{11-8} = shift{11-8};
1487 let Inst{6-5} = shift{6-5};
1489 let Inst{3-0} = shift{3-0};
1491 let Unpredictable{15-12} = 0b1111;
1497 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1498 /// register and one whose operand is a register rotated by 8/16/24.
1499 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1500 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1501 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1502 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1503 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1504 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1508 let Inst{19-16} = 0b1111;
1509 let Inst{15-12} = Rd;
1510 let Inst{11-10} = rot;
1514 class AI_ext_rrot_np<bits<8> opcod, string opc>
1515 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1516 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1517 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1519 let Inst{19-16} = 0b1111;
1520 let Inst{11-10} = rot;
1523 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1524 /// register and one whose operand is a register rotated by 8/16/24.
1525 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1526 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1527 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1528 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1529 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1530 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1535 let Inst{19-16} = Rn;
1536 let Inst{15-12} = Rd;
1537 let Inst{11-10} = rot;
1538 let Inst{9-4} = 0b000111;
1542 class AI_exta_rrot_np<bits<8> opcod, string opc>
1543 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1544 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1545 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1548 let Inst{19-16} = Rn;
1549 let Inst{11-10} = rot;
1552 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1553 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1554 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1555 bit Commutable = 0> {
1556 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1557 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1558 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1559 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>,
1561 Sched<[WriteALU, ReadALU]> {
1566 let Inst{15-12} = Rd;
1567 let Inst{19-16} = Rn;
1568 let Inst{11-0} = imm;
1570 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1571 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1572 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1574 Sched<[WriteALU, ReadALU, ReadALU]> {
1578 let Inst{11-4} = 0b00000000;
1580 let isCommutable = Commutable;
1582 let Inst{15-12} = Rd;
1583 let Inst{19-16} = Rn;
1585 def rsi : AsI1<opcod, (outs GPR:$Rd),
1586 (ins GPR:$Rn, so_reg_imm:$shift),
1587 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1588 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1590 Sched<[WriteALUsi, ReadALU]> {
1595 let Inst{19-16} = Rn;
1596 let Inst{15-12} = Rd;
1597 let Inst{11-5} = shift{11-5};
1599 let Inst{3-0} = shift{3-0};
1601 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1602 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1603 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1604 [(set GPRnopc:$Rd, CPSR,
1605 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1607 Sched<[WriteALUsr, ReadALUsr]> {
1612 let Inst{19-16} = Rn;
1613 let Inst{15-12} = Rd;
1614 let Inst{11-8} = shift{11-8};
1616 let Inst{6-5} = shift{6-5};
1618 let Inst{3-0} = shift{3-0};
1623 /// AI1_rsc_irs - Define instructions and patterns for rsc
1624 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1625 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1626 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1627 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1628 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1629 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>,
1631 Sched<[WriteALU, ReadALU]> {
1636 let Inst{15-12} = Rd;
1637 let Inst{19-16} = Rn;
1638 let Inst{11-0} = imm;
1640 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1641 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1642 [/* pattern left blank */]>,
1643 Sched<[WriteALU, ReadALU, ReadALU]> {
1647 let Inst{11-4} = 0b00000000;
1650 let Inst{15-12} = Rd;
1651 let Inst{19-16} = Rn;
1653 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1654 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1655 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1657 Sched<[WriteALUsi, ReadALU]> {
1662 let Inst{19-16} = Rn;
1663 let Inst{15-12} = Rd;
1664 let Inst{11-5} = shift{11-5};
1666 let Inst{3-0} = shift{3-0};
1668 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1669 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1670 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1672 Sched<[WriteALUsr, ReadALUsr]> {
1677 let Inst{19-16} = Rn;
1678 let Inst{15-12} = Rd;
1679 let Inst{11-8} = shift{11-8};
1681 let Inst{6-5} = shift{6-5};
1683 let Inst{3-0} = shift{3-0};
1688 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1689 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1690 InstrItinClass iir, PatFrag opnode> {
1691 // Note: We use the complex addrmode_imm12 rather than just an input
1692 // GPR and a constrained immediate so that we can use this to match
1693 // frame index references and avoid matching constant pool references.
1694 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1695 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1696 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1699 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1700 let Inst{19-16} = addr{16-13}; // Rn
1701 let Inst{15-12} = Rt;
1702 let Inst{11-0} = addr{11-0}; // imm12
1704 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1705 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1706 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1709 let shift{4} = 0; // Inst{4} = 0
1710 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1711 let Inst{19-16} = shift{16-13}; // Rn
1712 let Inst{15-12} = Rt;
1713 let Inst{11-0} = shift{11-0};
1718 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1719 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1720 InstrItinClass iir, PatFrag opnode> {
1721 // Note: We use the complex addrmode_imm12 rather than just an input
1722 // GPR and a constrained immediate so that we can use this to match
1723 // frame index references and avoid matching constant pool references.
1724 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1725 (ins addrmode_imm12:$addr),
1726 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1727 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1730 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1731 let Inst{19-16} = addr{16-13}; // Rn
1732 let Inst{15-12} = Rt;
1733 let Inst{11-0} = addr{11-0}; // imm12
1735 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1736 (ins ldst_so_reg:$shift),
1737 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1738 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1741 let shift{4} = 0; // Inst{4} = 0
1742 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1743 let Inst{19-16} = shift{16-13}; // Rn
1744 let Inst{15-12} = Rt;
1745 let Inst{11-0} = shift{11-0};
1751 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1752 InstrItinClass iir, PatFrag opnode> {
1753 // Note: We use the complex addrmode_imm12 rather than just an input
1754 // GPR and a constrained immediate so that we can use this to match
1755 // frame index references and avoid matching constant pool references.
1756 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1757 (ins GPR:$Rt, addrmode_imm12:$addr),
1758 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1759 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1762 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1763 let Inst{19-16} = addr{16-13}; // Rn
1764 let Inst{15-12} = Rt;
1765 let Inst{11-0} = addr{11-0}; // imm12
1767 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1768 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1769 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1772 let shift{4} = 0; // Inst{4} = 0
1773 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1774 let Inst{19-16} = shift{16-13}; // Rn
1775 let Inst{15-12} = Rt;
1776 let Inst{11-0} = shift{11-0};
1780 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1781 InstrItinClass iir, PatFrag opnode> {
1782 // Note: We use the complex addrmode_imm12 rather than just an input
1783 // GPR and a constrained immediate so that we can use this to match
1784 // frame index references and avoid matching constant pool references.
1785 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1786 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1787 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1788 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1791 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1792 let Inst{19-16} = addr{16-13}; // Rn
1793 let Inst{15-12} = Rt;
1794 let Inst{11-0} = addr{11-0}; // imm12
1796 def rs : AI2ldst<0b011, 0, isByte, (outs),
1797 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1798 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1799 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1802 let shift{4} = 0; // Inst{4} = 0
1803 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1804 let Inst{19-16} = shift{16-13}; // Rn
1805 let Inst{15-12} = Rt;
1806 let Inst{11-0} = shift{11-0};
1811 //===----------------------------------------------------------------------===//
1813 //===----------------------------------------------------------------------===//
1815 //===----------------------------------------------------------------------===//
1816 // Miscellaneous Instructions.
1819 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1820 /// the function. The first operand is the ID# for this instruction, the second
1821 /// is the index into the MachineConstantPool that this is, the third is the
1822 /// size in bytes of this constant pool entry.
1823 let hasSideEffects = 0, isNotDuplicable = 1 in
1824 def CONSTPOOL_ENTRY :
1825 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1826 i32imm:$size), NoItinerary, []>;
1828 /// A jumptable consisting of direct 32-bit addresses of the destination basic
1829 /// blocks (either absolute, or relative to the start of the jump-table in PIC
1830 /// mode). Used mostly in ARM and Thumb-1 modes.
1831 def JUMPTABLE_ADDRS :
1832 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1833 i32imm:$size), NoItinerary, []>;
1835 /// A jumptable consisting of 32-bit jump instructions. Used for Thumb-2 tables
1836 /// that cannot be optimised to use TBB or TBH.
1837 def JUMPTABLE_INSTS :
1838 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1839 i32imm:$size), NoItinerary, []>;
1841 /// A jumptable consisting of 8-bit unsigned integers representing offsets from
1842 /// a TBB instruction.
1844 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1845 i32imm:$size), NoItinerary, []>;
1847 /// A jumptable consisting of 16-bit unsigned integers representing offsets from
1848 /// a TBH instruction.
1850 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1851 i32imm:$size), NoItinerary, []>;
1854 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1855 // from removing one half of the matched pairs. That breaks PEI, which assumes
1856 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1857 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1858 def ADJCALLSTACKUP :
1859 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1860 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1862 def ADJCALLSTACKDOWN :
1863 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1864 [(ARMcallseq_start timm:$amt)]>;
1867 def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary,
1868 "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>,
1869 Requires<[IsARM, HasV6]> {
1871 let Inst{27-8} = 0b00110010000011110000;
1872 let Inst{7-0} = imm;
1875 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>;
1876 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>;
1877 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>;
1878 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>;
1879 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>;
1880 def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
1882 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1883 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1888 let Inst{15-12} = Rd;
1889 let Inst{19-16} = Rn;
1890 let Inst{27-20} = 0b01101000;
1891 let Inst{7-4} = 0b1011;
1892 let Inst{11-8} = 0b1111;
1893 let Unpredictable{11-8} = 0b1111;
1896 // The 16-bit operand $val can be used by a debugger to store more information
1897 // about the breakpoint.
1898 def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1899 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1901 let Inst{3-0} = val{3-0};
1902 let Inst{19-8} = val{15-4};
1903 let Inst{27-20} = 0b00010010;
1904 let Inst{31-28} = 0xe; // AL
1905 let Inst{7-4} = 0b0111;
1907 // default immediate for breakpoint mnemonic
1908 def : InstAlias<"bkpt", (BKPT 0)>, Requires<[IsARM]>;
1910 def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1911 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> {
1913 let Inst{3-0} = val{3-0};
1914 let Inst{19-8} = val{15-4};
1915 let Inst{27-20} = 0b00010000;
1916 let Inst{31-28} = 0xe; // AL
1917 let Inst{7-4} = 0b0111;
1920 // Change Processor State
1921 // FIXME: We should use InstAlias to handle the optional operands.
1922 class CPS<dag iops, string asm_ops>
1923 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1924 []>, Requires<[IsARM]> {
1930 let Inst{31-28} = 0b1111;
1931 let Inst{27-20} = 0b00010000;
1932 let Inst{19-18} = imod;
1933 let Inst{17} = M; // Enabled if mode is set;
1934 let Inst{16-9} = 0b00000000;
1935 let Inst{8-6} = iflags;
1937 let Inst{4-0} = mode;
1940 let DecoderMethod = "DecodeCPSInstruction" in {
1942 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1943 "$imod\t$iflags, $mode">;
1944 let mode = 0, M = 0 in
1945 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1947 let imod = 0, iflags = 0, M = 1 in
1948 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1951 // Preload signals the memory system of possible future data/instruction access.
1952 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1954 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm,
1955 IIC_Preload, !strconcat(opc, "\t$addr"),
1956 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>,
1957 Sched<[WritePreLd]> {
1960 let Inst{31-26} = 0b111101;
1961 let Inst{25} = 0; // 0 for immediate form
1962 let Inst{24} = data;
1963 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1964 let Inst{22} = read;
1965 let Inst{21-20} = 0b01;
1966 let Inst{19-16} = addr{16-13}; // Rn
1967 let Inst{15-12} = 0b1111;
1968 let Inst{11-0} = addr{11-0}; // imm12
1971 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1972 !strconcat(opc, "\t$shift"),
1973 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>,
1974 Sched<[WritePreLd]> {
1976 let Inst{31-26} = 0b111101;
1977 let Inst{25} = 1; // 1 for register form
1978 let Inst{24} = data;
1979 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1980 let Inst{22} = read;
1981 let Inst{21-20} = 0b01;
1982 let Inst{19-16} = shift{16-13}; // Rn
1983 let Inst{15-12} = 0b1111;
1984 let Inst{11-0} = shift{11-0};
1989 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1990 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1991 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1993 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1994 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> {
1996 let Inst{31-10} = 0b1111000100000001000000;
2001 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
2002 [(int_arm_dbg imm0_15:$opt)]>, Requires<[IsARM, HasV7]> {
2004 let Inst{27-4} = 0b001100100000111100001111;
2005 let Inst{3-0} = opt;
2008 // A8.8.247 UDF - Undefined (Encoding A1)
2009 def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary,
2010 "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> {
2012 let Inst{31-28} = 0b1110; // AL
2013 let Inst{27-25} = 0b011;
2014 let Inst{24-20} = 0b11111;
2015 let Inst{19-8} = imm16{15-4};
2016 let Inst{7-4} = 0b1111;
2017 let Inst{3-0} = imm16{3-0};
2021 * A5.4 Permanently UNDEFINED instructions.
2023 * For most targets use UDF #65006, for which the OS will generate SIGTRAP.
2024 * Other UDF encodings generate SIGILL.
2026 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
2028 * 1110 0111 1111 iiii iiii iiii 1111 iiii
2030 * 1101 1110 iiii iiii
2031 * It uses the following encoding:
2032 * 1110 0111 1111 1110 1101 1110 1111 0000
2033 * - In ARM: UDF #60896;
2034 * - In Thumb: UDF #254 followed by a branch-to-self.
2036 let isBarrier = 1, isTerminator = 1 in
2037 def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
2039 Requires<[IsARM,UseNaClTrap]> {
2040 let Inst = 0xe7fedef0;
2042 let isBarrier = 1, isTerminator = 1 in
2043 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
2045 Requires<[IsARM,DontUseNaClTrap]> {
2046 let Inst = 0xe7ffdefe;
2049 // Address computation and loads and stores in PIC mode.
2050 let isNotDuplicable = 1 in {
2051 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
2053 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
2054 Sched<[WriteALU, ReadALU]>;
2056 let AddedComplexity = 10 in {
2057 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
2059 [(set GPR:$dst, (load addrmodepc:$addr))]>;
2061 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2063 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
2065 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2067 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
2069 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2071 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
2073 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2075 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
2077 let AddedComplexity = 10 in {
2078 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2079 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
2081 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2082 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
2083 addrmodepc:$addr)]>;
2085 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2086 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
2088 } // isNotDuplicable = 1
2091 // LEApcrel - Load a pc-relative address into a register without offending the
2093 let hasSideEffects = 0, isReMaterializable = 1 in
2094 // The 'adr' mnemonic encodes differently if the label is before or after
2095 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
2096 // know until then which form of the instruction will be used.
2097 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
2098 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
2099 Sched<[WriteALU, ReadALU]> {
2102 let Inst{27-25} = 0b001;
2104 let Inst{23-22} = label{13-12};
2107 let Inst{19-16} = 0b1111;
2108 let Inst{15-12} = Rd;
2109 let Inst{11-0} = label{11-0};
2112 let hasSideEffects = 1 in {
2113 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
2114 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
2116 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
2117 (ins i32imm:$label, pred:$p),
2118 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
2121 //===----------------------------------------------------------------------===//
2122 // Control Flow Instructions.
2125 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
2127 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
2128 "bx", "\tlr", [(ARMretflag)]>,
2129 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2130 let Inst{27-0} = 0b0001001011111111111100011110;
2134 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
2135 "mov", "\tpc, lr", [(ARMretflag)]>,
2136 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> {
2137 let Inst{27-0} = 0b0001101000001111000000001110;
2140 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets
2141 // the user-space one).
2142 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p),
2144 [(ARMintretflag imm:$offset)]>;
2147 // Indirect branches
2148 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
2150 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
2151 [(brind GPR:$dst)]>,
2152 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2154 let Inst{31-4} = 0b1110000100101111111111110001;
2155 let Inst{3-0} = dst;
2158 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
2159 "bx", "\t$dst", [/* pattern left blank */]>,
2160 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2162 let Inst{27-4} = 0b000100101111111111110001;
2163 let Inst{3-0} = dst;
2167 // SP is marked as a use to prevent stack-pointer assignments that appear
2168 // immediately before calls from potentially appearing dead.
2170 // FIXME: Do we really need a non-predicated version? If so, it should
2171 // at least be a pseudo instruction expanding to the predicated version
2172 // at MC lowering time.
2173 Defs = [LR], Uses = [SP] in {
2174 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
2175 IIC_Br, "bl\t$func",
2176 [(ARMcall tglobaladdr:$func)]>,
2177 Requires<[IsARM]>, Sched<[WriteBrL]> {
2178 let Inst{31-28} = 0b1110;
2180 let Inst{23-0} = func;
2181 let DecoderMethod = "DecodeBranchImmInstruction";
2184 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
2185 IIC_Br, "bl", "\t$func",
2186 [(ARMcall_pred tglobaladdr:$func)]>,
2187 Requires<[IsARM]>, Sched<[WriteBrL]> {
2189 let Inst{23-0} = func;
2190 let DecoderMethod = "DecodeBranchImmInstruction";
2194 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
2195 IIC_Br, "blx\t$func",
2196 [(ARMcall GPR:$func)]>,
2197 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2199 let Inst{31-4} = 0b1110000100101111111111110011;
2200 let Inst{3-0} = func;
2203 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
2204 IIC_Br, "blx", "\t$func",
2205 [(ARMcall_pred GPR:$func)]>,
2206 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2208 let Inst{27-4} = 0b000100101111111111110011;
2209 let Inst{3-0} = func;
2213 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
2214 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2215 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2216 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>;
2219 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2220 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2221 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
2223 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
2224 // return stack predictor.
2225 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
2226 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
2227 Requires<[IsARM]>, Sched<[WriteBr]>;
2230 let isBranch = 1, isTerminator = 1 in {
2231 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2232 // a two-value operand where a dag node expects two operands. :(
2233 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2234 IIC_Br, "b", "\t$target",
2235 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>,
2238 let Inst{23-0} = target;
2239 let DecoderMethod = "DecodeBranchImmInstruction";
2242 let isBarrier = 1 in {
2243 // B is "predicable" since it's just a Bcc with an 'always' condition.
2244 let isPredicable = 1 in
2245 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2246 // should be sufficient.
2247 // FIXME: Is B really a Barrier? That doesn't seem right.
2248 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2249 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>,
2252 let Size = 4, isNotDuplicable = 1, isIndirectBranch = 1 in {
2253 def BR_JTr : ARMPseudoInst<(outs),
2254 (ins GPR:$target, i32imm:$jt),
2256 [(ARMbrjt GPR:$target, tjumptable:$jt)]>,
2258 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2259 // into i12 and rs suffixed versions.
2260 def BR_JTm : ARMPseudoInst<(outs),
2261 (ins addrmode2:$target, i32imm:$jt),
2263 [(ARMbrjt (i32 (load addrmode2:$target)),
2264 tjumptable:$jt)]>, Sched<[WriteBrTbl]>;
2265 def BR_JTadd : ARMPseudoInst<(outs),
2266 (ins GPR:$target, GPR:$idx, i32imm:$jt),
2268 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt)]>,
2269 Sched<[WriteBrTbl]>;
2270 } // isNotDuplicable = 1, isIndirectBranch = 1
2276 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2277 "blx\t$target", []>,
2278 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2279 let Inst{31-25} = 0b1111101;
2281 let Inst{23-0} = target{24-1};
2282 let Inst{24} = target{0};
2286 // Branch and Exchange Jazelle
2287 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2288 [/* pattern left blank */]>, Sched<[WriteBr]> {
2290 let Inst{23-20} = 0b0010;
2291 let Inst{19-8} = 0xfff;
2292 let Inst{7-4} = 0b0010;
2293 let Inst{3-0} = func;
2299 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
2300 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>,
2303 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>,
2306 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
2308 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2309 Requires<[IsARM]>, Sched<[WriteBr]>;
2311 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
2313 (BX GPR:$dst)>, Sched<[WriteBr]>,
2317 // Secure Monitor Call is a system instruction.
2318 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2319 []>, Requires<[IsARM, HasTrustZone]> {
2321 let Inst{23-4} = 0b01100000000000000111;
2322 let Inst{3-0} = opt;
2325 // Supervisor Call (Software Interrupt)
2326 let isCall = 1, Uses = [SP] in {
2327 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>,
2330 let Inst{23-0} = svc;
2334 // Store Return State
2335 class SRSI<bit wb, string asm>
2336 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2337 NoItinerary, asm, "", []> {
2339 let Inst{31-28} = 0b1111;
2340 let Inst{27-25} = 0b100;
2344 let Inst{19-16} = 0b1101; // SP
2345 let Inst{15-5} = 0b00000101000;
2346 let Inst{4-0} = mode;
2349 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2350 let Inst{24-23} = 0;
2352 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2353 let Inst{24-23} = 0;
2355 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2356 let Inst{24-23} = 0b10;
2358 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2359 let Inst{24-23} = 0b10;
2361 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2362 let Inst{24-23} = 0b01;
2364 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2365 let Inst{24-23} = 0b01;
2367 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2368 let Inst{24-23} = 0b11;
2370 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2371 let Inst{24-23} = 0b11;
2374 def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
2375 def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
2377 def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
2378 def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
2380 def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
2381 def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
2383 def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
2384 def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
2386 // Return From Exception
2387 class RFEI<bit wb, string asm>
2388 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2389 NoItinerary, asm, "", []> {
2391 let Inst{31-28} = 0b1111;
2392 let Inst{27-25} = 0b100;
2396 let Inst{19-16} = Rn;
2397 let Inst{15-0} = 0xa00;
2400 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2401 let Inst{24-23} = 0;
2403 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2404 let Inst{24-23} = 0;
2406 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2407 let Inst{24-23} = 0b10;
2409 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2410 let Inst{24-23} = 0b10;
2412 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2413 let Inst{24-23} = 0b01;
2415 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2416 let Inst{24-23} = 0b01;
2418 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2419 let Inst{24-23} = 0b11;
2421 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2422 let Inst{24-23} = 0b11;
2425 // Hypervisor Call is a system instruction
2427 def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary,
2428 "hvc", "\t$imm", []>,
2429 Requires<[IsARM, HasVirtualization]> {
2432 // Even though HVC isn't predicable, it's encoding includes a condition field.
2433 // The instruction is undefined if the condition field is 0xf otherwise it is
2434 // unpredictable if it isn't condition AL (0xe).
2435 let Inst{31-28} = 0b1110;
2436 let Unpredictable{31-28} = 0b1111;
2437 let Inst{27-24} = 0b0001;
2438 let Inst{23-20} = 0b0100;
2439 let Inst{19-8} = imm{15-4};
2440 let Inst{7-4} = 0b0111;
2441 let Inst{3-0} = imm{3-0};
2445 // Return from exception in Hypervisor mode.
2446 let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in
2447 def ERET : ABI<0b0001, (outs), (ins), NoItinerary, "eret", "", []>,
2448 Requires<[IsARM, HasVirtualization]> {
2449 let Inst{23-0} = 0b011000000000000001101110;
2452 //===----------------------------------------------------------------------===//
2453 // Load / Store Instructions.
2459 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2460 UnOpFrag<(load node:$Src)>>;
2461 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2462 UnOpFrag<(zextloadi8 node:$Src)>>;
2463 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2464 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2465 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2466 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2468 // Special LDR for loads from non-pc-relative constpools.
2469 let canFoldAsLoad = 1, mayLoad = 1, hasSideEffects = 0,
2470 isReMaterializable = 1, isCodeGenOnly = 1 in
2471 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2472 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2476 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2477 let Inst{19-16} = 0b1111;
2478 let Inst{15-12} = Rt;
2479 let Inst{11-0} = addr{11-0}; // imm12
2482 // Loads with zero extension
2483 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2484 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2485 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2487 // Loads with sign extension
2488 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2489 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2490 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2492 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2493 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2494 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2496 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
2498 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
2499 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>,
2500 Requires<[IsARM, HasV5TE]>;
2503 def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2504 NoItinerary, "lda", "\t$Rt, $addr", []>;
2505 def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2506 NoItinerary, "ldab", "\t$Rt, $addr", []>;
2507 def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2508 NoItinerary, "ldah", "\t$Rt, $addr", []>;
2511 multiclass AI2_ldridx<bit isByte, string opc,
2512 InstrItinClass iii, InstrItinClass iir> {
2513 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2514 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii,
2515 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2518 let Inst{23} = addr{12};
2519 let Inst{19-16} = addr{16-13};
2520 let Inst{11-0} = addr{11-0};
2521 let DecoderMethod = "DecodeLDRPreImm";
2524 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2525 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2526 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2529 let Inst{23} = addr{12};
2530 let Inst{19-16} = addr{16-13};
2531 let Inst{11-0} = addr{11-0};
2533 let DecoderMethod = "DecodeLDRPreReg";
2536 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2537 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2538 IndexModePost, LdFrm, iir,
2539 opc, "\t$Rt, $addr, $offset",
2540 "$addr.base = $Rn_wb", []> {
2546 let Inst{23} = offset{12};
2547 let Inst{19-16} = addr;
2548 let Inst{11-0} = offset{11-0};
2551 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2554 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2555 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2556 IndexModePost, LdFrm, iii,
2557 opc, "\t$Rt, $addr, $offset",
2558 "$addr.base = $Rn_wb", []> {
2564 let Inst{23} = offset{12};
2565 let Inst{19-16} = addr;
2566 let Inst{11-0} = offset{11-0};
2568 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2573 let mayLoad = 1, hasSideEffects = 0 in {
2574 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2575 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2576 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2577 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2580 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2581 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2582 (ins addrmode3_pre:$addr), IndexModePre,
2584 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2586 let Inst{23} = addr{8}; // U bit
2587 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2588 let Inst{19-16} = addr{12-9}; // Rn
2589 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2590 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2591 let DecoderMethod = "DecodeAddrMode3Instruction";
2593 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2594 (ins addr_offset_none:$addr, am3offset:$offset),
2595 IndexModePost, LdMiscFrm, itin,
2596 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2600 let Inst{23} = offset{8}; // U bit
2601 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2602 let Inst{19-16} = addr;
2603 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2604 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2605 let DecoderMethod = "DecodeAddrMode3Instruction";
2609 let mayLoad = 1, hasSideEffects = 0 in {
2610 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2611 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2612 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2613 let hasExtraDefRegAllocReq = 1 in {
2614 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2615 (ins addrmode3_pre:$addr), IndexModePre,
2616 LdMiscFrm, IIC_iLoad_d_ru,
2617 "ldrd", "\t$Rt, $Rt2, $addr!",
2618 "$addr.base = $Rn_wb", []> {
2620 let Inst{23} = addr{8}; // U bit
2621 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2622 let Inst{19-16} = addr{12-9}; // Rn
2623 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2624 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2625 let DecoderMethod = "DecodeAddrMode3Instruction";
2627 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2628 (ins addr_offset_none:$addr, am3offset:$offset),
2629 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2630 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2631 "$addr.base = $Rn_wb", []> {
2634 let Inst{23} = offset{8}; // U bit
2635 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2636 let Inst{19-16} = addr;
2637 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2638 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2639 let DecoderMethod = "DecodeAddrMode3Instruction";
2641 } // hasExtraDefRegAllocReq = 1
2642 } // mayLoad = 1, hasSideEffects = 0
2644 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2645 let mayLoad = 1, hasSideEffects = 0 in {
2646 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2647 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2648 IndexModePost, LdFrm, IIC_iLoad_ru,
2649 "ldrt", "\t$Rt, $addr, $offset",
2650 "$addr.base = $Rn_wb", []> {
2656 let Inst{23} = offset{12};
2657 let Inst{21} = 1; // overwrite
2658 let Inst{19-16} = addr;
2659 let Inst{11-5} = offset{11-5};
2661 let Inst{3-0} = offset{3-0};
2662 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2666 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2667 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2668 IndexModePost, LdFrm, IIC_iLoad_ru,
2669 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2675 let Inst{23} = offset{12};
2676 let Inst{21} = 1; // overwrite
2677 let Inst{19-16} = addr;
2678 let Inst{11-0} = offset{11-0};
2679 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2682 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2683 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2684 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2685 "ldrbt", "\t$Rt, $addr, $offset",
2686 "$addr.base = $Rn_wb", []> {
2692 let Inst{23} = offset{12};
2693 let Inst{21} = 1; // overwrite
2694 let Inst{19-16} = addr;
2695 let Inst{11-5} = offset{11-5};
2697 let Inst{3-0} = offset{3-0};
2698 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2702 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2703 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2704 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2705 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2711 let Inst{23} = offset{12};
2712 let Inst{21} = 1; // overwrite
2713 let Inst{19-16} = addr;
2714 let Inst{11-0} = offset{11-0};
2715 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2718 multiclass AI3ldrT<bits<4> op, string opc> {
2719 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2720 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2721 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2722 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2724 let Inst{23} = offset{8};
2726 let Inst{11-8} = offset{7-4};
2727 let Inst{3-0} = offset{3-0};
2729 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2730 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2731 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2732 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2734 let Inst{23} = Rm{4};
2737 let Unpredictable{11-8} = 0b1111;
2738 let Inst{3-0} = Rm{3-0};
2739 let DecoderMethod = "DecodeLDR";
2743 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2744 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2745 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2749 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2753 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2758 // Stores with truncate
2759 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2760 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2761 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2764 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
2765 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2766 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>,
2767 Requires<[IsARM, HasV5TE]> {
2773 multiclass AI2_stridx<bit isByte, string opc,
2774 InstrItinClass iii, InstrItinClass iir> {
2775 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2776 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
2778 opc, "\t$Rt, $addr!",
2779 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2782 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2783 let Inst{19-16} = addr{16-13}; // Rn
2784 let Inst{11-0} = addr{11-0}; // imm12
2785 let DecoderMethod = "DecodeSTRPreImm";
2788 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2789 (ins GPR:$Rt, ldst_so_reg:$addr),
2790 IndexModePre, StFrm, iir,
2791 opc, "\t$Rt, $addr!",
2792 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2795 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2796 let Inst{19-16} = addr{16-13}; // Rn
2797 let Inst{11-0} = addr{11-0};
2798 let Inst{4} = 0; // Inst{4} = 0
2799 let DecoderMethod = "DecodeSTRPreReg";
2801 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2802 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2803 IndexModePost, StFrm, iir,
2804 opc, "\t$Rt, $addr, $offset",
2805 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2811 let Inst{23} = offset{12};
2812 let Inst{19-16} = addr;
2813 let Inst{11-0} = offset{11-0};
2816 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2819 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2820 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2821 IndexModePost, StFrm, iii,
2822 opc, "\t$Rt, $addr, $offset",
2823 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2829 let Inst{23} = offset{12};
2830 let Inst{19-16} = addr;
2831 let Inst{11-0} = offset{11-0};
2833 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2837 let mayStore = 1, hasSideEffects = 0 in {
2838 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2839 // IIC_iStore_siu depending on whether it the offset register is shifted.
2840 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2841 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2844 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2845 am2offset_reg:$offset),
2846 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2847 am2offset_reg:$offset)>;
2848 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2849 am2offset_imm:$offset),
2850 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2851 am2offset_imm:$offset)>;
2852 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2853 am2offset_reg:$offset),
2854 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2855 am2offset_reg:$offset)>;
2856 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2857 am2offset_imm:$offset),
2858 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2859 am2offset_imm:$offset)>;
2861 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2862 // put the patterns on the instruction definitions directly as ISel wants
2863 // the address base and offset to be separate operands, not a single
2864 // complex operand like we represent the instructions themselves. The
2865 // pseudos map between the two.
2866 let usesCustomInserter = 1,
2867 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2868 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2869 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2872 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2873 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2874 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2877 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2878 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2879 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2882 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2883 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2884 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2887 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2888 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2889 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2892 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2897 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2898 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
2899 StMiscFrm, IIC_iStore_bh_ru,
2900 "strh", "\t$Rt, $addr!",
2901 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2903 let Inst{23} = addr{8}; // U bit
2904 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2905 let Inst{19-16} = addr{12-9}; // Rn
2906 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2907 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2908 let DecoderMethod = "DecodeAddrMode3Instruction";
2911 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2912 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2913 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2914 "strh", "\t$Rt, $addr, $offset",
2915 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb",
2916 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2917 addr_offset_none:$addr,
2918 am3offset:$offset))]> {
2921 let Inst{23} = offset{8}; // U bit
2922 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2923 let Inst{19-16} = addr;
2924 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2925 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2926 let DecoderMethod = "DecodeAddrMode3Instruction";
2929 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
2930 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2931 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
2932 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2933 "strd", "\t$Rt, $Rt2, $addr!",
2934 "$addr.base = $Rn_wb", []> {
2936 let Inst{23} = addr{8}; // U bit
2937 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2938 let Inst{19-16} = addr{12-9}; // Rn
2939 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2940 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2941 let DecoderMethod = "DecodeAddrMode3Instruction";
2944 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2945 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2947 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2948 "strd", "\t$Rt, $Rt2, $addr, $offset",
2949 "$addr.base = $Rn_wb", []> {
2952 let Inst{23} = offset{8}; // U bit
2953 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2954 let Inst{19-16} = addr;
2955 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2956 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2957 let DecoderMethod = "DecodeAddrMode3Instruction";
2959 } // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1
2961 // STRT, STRBT, and STRHT
2963 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2964 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2965 IndexModePost, StFrm, IIC_iStore_bh_ru,
2966 "strbt", "\t$Rt, $addr, $offset",
2967 "$addr.base = $Rn_wb", []> {
2973 let Inst{23} = offset{12};
2974 let Inst{21} = 1; // overwrite
2975 let Inst{19-16} = addr;
2976 let Inst{11-5} = offset{11-5};
2978 let Inst{3-0} = offset{3-0};
2979 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2983 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2984 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2985 IndexModePost, StFrm, IIC_iStore_bh_ru,
2986 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2992 let Inst{23} = offset{12};
2993 let Inst{21} = 1; // overwrite
2994 let Inst{19-16} = addr;
2995 let Inst{11-0} = offset{11-0};
2996 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3000 : ARMAsmPseudo<"strbt${q} $Rt, $addr",
3001 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3003 let mayStore = 1, hasSideEffects = 0 in {
3004 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
3005 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
3006 IndexModePost, StFrm, IIC_iStore_ru,
3007 "strt", "\t$Rt, $addr, $offset",
3008 "$addr.base = $Rn_wb", []> {
3014 let Inst{23} = offset{12};
3015 let Inst{21} = 1; // overwrite
3016 let Inst{19-16} = addr;
3017 let Inst{11-5} = offset{11-5};
3019 let Inst{3-0} = offset{3-0};
3020 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3024 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
3025 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
3026 IndexModePost, StFrm, IIC_iStore_ru,
3027 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
3033 let Inst{23} = offset{12};
3034 let Inst{21} = 1; // overwrite
3035 let Inst{19-16} = addr;
3036 let Inst{11-0} = offset{11-0};
3037 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3042 : ARMAsmPseudo<"strt${q} $Rt, $addr",
3043 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3045 multiclass AI3strT<bits<4> op, string opc> {
3046 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3047 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
3048 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
3049 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
3051 let Inst{23} = offset{8};
3053 let Inst{11-8} = offset{7-4};
3054 let Inst{3-0} = offset{3-0};
3056 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3057 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
3058 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
3059 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
3061 let Inst{23} = Rm{4};
3064 let Inst{3-0} = Rm{3-0};
3069 defm STRHT : AI3strT<0b1011, "strht">;
3071 def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3072 NoItinerary, "stl", "\t$Rt, $addr", []>;
3073 def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3074 NoItinerary, "stlb", "\t$Rt, $addr", []>;
3075 def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3076 NoItinerary, "stlh", "\t$Rt, $addr", []>;
3078 //===----------------------------------------------------------------------===//
3079 // Load / store multiple Instructions.
3082 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
3083 InstrItinClass itin, InstrItinClass itin_upd> {
3084 // IA is the default, so no need for an explicit suffix on the
3085 // mnemonic here. Without it is the canonical spelling.
3087 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3088 IndexModeNone, f, itin,
3089 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
3090 let Inst{24-23} = 0b01; // Increment After
3091 let Inst{22} = P_bit;
3092 let Inst{21} = 0; // No writeback
3093 let Inst{20} = L_bit;
3096 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3097 IndexModeUpd, f, itin_upd,
3098 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3099 let Inst{24-23} = 0b01; // Increment After
3100 let Inst{22} = P_bit;
3101 let Inst{21} = 1; // Writeback
3102 let Inst{20} = L_bit;
3104 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3107 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3108 IndexModeNone, f, itin,
3109 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
3110 let Inst{24-23} = 0b00; // Decrement After
3111 let Inst{22} = P_bit;
3112 let Inst{21} = 0; // No writeback
3113 let Inst{20} = L_bit;
3116 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3117 IndexModeUpd, f, itin_upd,
3118 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3119 let Inst{24-23} = 0b00; // Decrement After
3120 let Inst{22} = P_bit;
3121 let Inst{21} = 1; // Writeback
3122 let Inst{20} = L_bit;
3124 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3127 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3128 IndexModeNone, f, itin,
3129 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
3130 let Inst{24-23} = 0b10; // Decrement Before
3131 let Inst{22} = P_bit;
3132 let Inst{21} = 0; // No writeback
3133 let Inst{20} = L_bit;
3136 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3137 IndexModeUpd, f, itin_upd,
3138 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3139 let Inst{24-23} = 0b10; // Decrement Before
3140 let Inst{22} = P_bit;
3141 let Inst{21} = 1; // Writeback
3142 let Inst{20} = L_bit;
3144 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3147 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3148 IndexModeNone, f, itin,
3149 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
3150 let Inst{24-23} = 0b11; // Increment Before
3151 let Inst{22} = P_bit;
3152 let Inst{21} = 0; // No writeback
3153 let Inst{20} = L_bit;
3156 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3157 IndexModeUpd, f, itin_upd,
3158 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3159 let Inst{24-23} = 0b11; // Increment Before
3160 let Inst{22} = P_bit;
3161 let Inst{21} = 1; // Writeback
3162 let Inst{20} = L_bit;
3164 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3168 let hasSideEffects = 0 in {
3170 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3171 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
3172 IIC_iLoad_mu>, ComplexDeprecationPredicate<"ARMLoad">;
3174 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3175 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
3177 ComplexDeprecationPredicate<"ARMStore">;
3181 // FIXME: remove when we have a way to marking a MI with these properties.
3182 // FIXME: Should pc be an implicit operand like PICADD, etc?
3183 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3184 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3185 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3186 reglist:$regs, variable_ops),
3187 4, IIC_iLoad_mBr, [],
3188 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3189 RegConstraint<"$Rn = $wb">;
3191 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3192 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
3195 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3196 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
3201 //===----------------------------------------------------------------------===//
3202 // Move Instructions.
3205 let hasSideEffects = 0 in
3206 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
3207 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3211 let Inst{19-16} = 0b0000;
3212 let Inst{11-4} = 0b00000000;
3215 let Inst{15-12} = Rd;
3218 // A version for the smaller set of tail call registers.
3219 let hasSideEffects = 0 in
3220 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
3221 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3225 let Inst{11-4} = 0b00000000;
3228 let Inst{15-12} = Rd;
3231 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
3232 DPSoRegRegFrm, IIC_iMOVsr,
3233 "mov", "\t$Rd, $src",
3234 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
3238 let Inst{15-12} = Rd;
3239 let Inst{19-16} = 0b0000;
3240 let Inst{11-8} = src{11-8};
3242 let Inst{6-5} = src{6-5};
3244 let Inst{3-0} = src{3-0};
3248 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3249 DPSoRegImmFrm, IIC_iMOVsr,
3250 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
3251 UnaryDP, Sched<[WriteALU]> {
3254 let Inst{15-12} = Rd;
3255 let Inst{19-16} = 0b0000;
3256 let Inst{11-5} = src{11-5};
3258 let Inst{3-0} = src{3-0};
3262 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3263 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi,
3264 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP,
3269 let Inst{15-12} = Rd;
3270 let Inst{19-16} = 0b0000;
3271 let Inst{11-0} = imm;
3274 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3275 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3277 "movw", "\t$Rd, $imm",
3278 [(set GPR:$Rd, imm0_65535:$imm)]>,
3279 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
3282 let Inst{15-12} = Rd;
3283 let Inst{11-0} = imm{11-0};
3284 let Inst{19-16} = imm{15-12};
3287 let DecoderMethod = "DecodeArmMOVTWInstruction";
3290 def : InstAlias<"mov${p} $Rd, $imm",
3291 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3294 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3295 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3298 let Constraints = "$src = $Rd" in {
3299 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3300 (ins GPR:$src, imm0_65535_expr:$imm),
3302 "movt", "\t$Rd, $imm",
3304 (or (and GPR:$src, 0xffff),
3305 lo16AllZero:$imm))]>, UnaryDP,
3306 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
3309 let Inst{15-12} = Rd;
3310 let Inst{11-0} = imm{11-0};
3311 let Inst{19-16} = imm{15-12};
3314 let DecoderMethod = "DecodeArmMOVTWInstruction";
3317 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3318 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3323 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3324 Requires<[IsARM, HasV6T2]>;
3326 let Uses = [CPSR] in
3327 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3328 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3329 Requires<[IsARM]>, Sched<[WriteALU]>;
3331 // These aren't really mov instructions, but we have to define them this way
3332 // due to flag operands.
3334 let Defs = [CPSR] in {
3335 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3336 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3337 Sched<[WriteALU]>, Requires<[IsARM]>;
3338 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3339 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3340 Sched<[WriteALU]>, Requires<[IsARM]>;
3343 //===----------------------------------------------------------------------===//
3344 // Extend Instructions.
3349 def SXTB : AI_ext_rrot<0b01101010,
3350 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3351 def SXTH : AI_ext_rrot<0b01101011,
3352 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3354 def SXTAB : AI_exta_rrot<0b01101010,
3355 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3356 def SXTAH : AI_exta_rrot<0b01101011,
3357 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3359 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3361 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3365 let AddedComplexity = 16 in {
3366 def UXTB : AI_ext_rrot<0b01101110,
3367 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3368 def UXTH : AI_ext_rrot<0b01101111,
3369 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3370 def UXTB16 : AI_ext_rrot<0b01101100,
3371 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3373 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3374 // The transformation should probably be done as a combiner action
3375 // instead so we can include a check for masking back in the upper
3376 // eight bits of the source into the lower eight bits of the result.
3377 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3378 // (UXTB16r_rot GPR:$Src, 3)>;
3379 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3380 (UXTB16 GPR:$Src, 1)>;
3382 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3383 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3384 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3385 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3388 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3389 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3392 def SBFX : I<(outs GPRnopc:$Rd),
3393 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3394 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3395 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3396 Requires<[IsARM, HasV6T2]> {
3401 let Inst{27-21} = 0b0111101;
3402 let Inst{6-4} = 0b101;
3403 let Inst{20-16} = width;
3404 let Inst{15-12} = Rd;
3405 let Inst{11-7} = lsb;
3409 def UBFX : I<(outs GPRnopc:$Rd),
3410 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3411 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3412 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3413 Requires<[IsARM, HasV6T2]> {
3418 let Inst{27-21} = 0b0111111;
3419 let Inst{6-4} = 0b101;
3420 let Inst{20-16} = width;
3421 let Inst{15-12} = Rd;
3422 let Inst{11-7} = lsb;
3426 //===----------------------------------------------------------------------===//
3427 // Arithmetic Instructions.
3430 defm ADD : AsI1_bin_irs<0b0100, "add",
3431 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3432 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3433 defm SUB : AsI1_bin_irs<0b0010, "sub",
3434 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3435 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3437 // ADD and SUB with 's' bit set.
3439 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3440 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3441 // AdjustInstrPostInstrSelection where we determine whether or not to
3442 // set the "s" bit based on CPSR liveness.
3444 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3445 // support for an optional CPSR definition that corresponds to the DAG
3446 // node's second value. We can then eliminate the implicit def of CPSR.
3447 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3448 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3449 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3450 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3452 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3453 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3454 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3455 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3457 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3458 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3459 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3461 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3462 // CPSR and the implicit def of CPSR is not needed.
3463 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3464 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3466 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3467 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3469 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3470 // The assume-no-carry-in form uses the negation of the input since add/sub
3471 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3472 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3474 def : ARMPat<(add GPR:$src, mod_imm_neg:$imm),
3475 (SUBri GPR:$src, mod_imm_neg:$imm)>;
3476 def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm),
3477 (SUBSri GPR:$src, mod_imm_neg:$imm)>;
3479 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3480 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3481 Requires<[IsARM, HasV6T2]>;
3482 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3483 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3484 Requires<[IsARM, HasV6T2]>;
3486 // The with-carry-in form matches bitwise not instead of the negation.
3487 // Effectively, the inverse interpretation of the carry flag already accounts
3488 // for part of the negation.
3489 def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR),
3490 (SBCri GPR:$src, mod_imm_not:$imm)>;
3491 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3492 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>,
3493 Requires<[IsARM, HasV6T2]>;
3495 // Note: These are implemented in C++ code, because they have to generate
3496 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3498 // (mul X, 2^n+1) -> (add (X << n), X)
3499 // (mul X, 2^n-1) -> (rsb X, (X << n))
3501 // ARM Arithmetic Instruction
3502 // GPR:$dst = GPR:$a op GPR:$b
3503 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3504 list<dag> pattern = [],
3505 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3506 string asm = "\t$Rd, $Rn, $Rm">
3507 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
3508 Sched<[WriteALU, ReadALU, ReadALU]> {
3512 let Inst{27-20} = op27_20;
3513 let Inst{11-4} = op11_4;
3514 let Inst{19-16} = Rn;
3515 let Inst{15-12} = Rd;
3518 let Unpredictable{11-8} = 0b1111;
3521 // Saturating add/subtract
3523 let DecoderMethod = "DecodeQADDInstruction" in
3524 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3525 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3526 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3528 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3529 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3530 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3531 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3532 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3534 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3535 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3538 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3539 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3540 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3541 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3542 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3543 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3544 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3545 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3546 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3547 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3548 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3549 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3551 // Signed/Unsigned add/subtract
3553 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3554 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3555 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3556 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3557 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3558 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3559 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3560 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3561 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3562 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3563 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3564 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3566 // Signed/Unsigned halving add/subtract
3568 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3569 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3570 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3571 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3572 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3573 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3574 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3575 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3576 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3577 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3578 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3579 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3581 // Unsigned Sum of Absolute Differences [and Accumulate].
3583 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3584 MulFrm /* for convenience */, NoItinerary, "usad8",
3585 "\t$Rd, $Rn, $Rm", []>,
3586 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
3590 let Inst{27-20} = 0b01111000;
3591 let Inst{15-12} = 0b1111;
3592 let Inst{7-4} = 0b0001;
3593 let Inst{19-16} = Rd;
3594 let Inst{11-8} = Rm;
3597 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3598 MulFrm /* for convenience */, NoItinerary, "usada8",
3599 "\t$Rd, $Rn, $Rm, $Ra", []>,
3600 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
3605 let Inst{27-20} = 0b01111000;
3606 let Inst{7-4} = 0b0001;
3607 let Inst{19-16} = Rd;
3608 let Inst{15-12} = Ra;
3609 let Inst{11-8} = Rm;
3613 // Signed/Unsigned saturate
3615 def SSAT : AI<(outs GPRnopc:$Rd),
3616 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3617 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3622 let Inst{27-21} = 0b0110101;
3623 let Inst{5-4} = 0b01;
3624 let Inst{20-16} = sat_imm;
3625 let Inst{15-12} = Rd;
3626 let Inst{11-7} = sh{4-0};
3627 let Inst{6} = sh{5};
3631 def SSAT16 : AI<(outs GPRnopc:$Rd),
3632 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3633 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3637 let Inst{27-20} = 0b01101010;
3638 let Inst{11-4} = 0b11110011;
3639 let Inst{15-12} = Rd;
3640 let Inst{19-16} = sat_imm;
3644 def USAT : AI<(outs GPRnopc:$Rd),
3645 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3646 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3651 let Inst{27-21} = 0b0110111;
3652 let Inst{5-4} = 0b01;
3653 let Inst{15-12} = Rd;
3654 let Inst{11-7} = sh{4-0};
3655 let Inst{6} = sh{5};
3656 let Inst{20-16} = sat_imm;
3660 def USAT16 : AI<(outs GPRnopc:$Rd),
3661 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3662 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3666 let Inst{27-20} = 0b01101110;
3667 let Inst{11-4} = 0b11110011;
3668 let Inst{15-12} = Rd;
3669 let Inst{19-16} = sat_imm;
3673 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3674 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3675 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3676 (USAT imm:$pos, GPRnopc:$a, 0)>;
3678 //===----------------------------------------------------------------------===//
3679 // Bitwise Instructions.
3682 defm AND : AsI1_bin_irs<0b0000, "and",
3683 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3684 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3685 defm ORR : AsI1_bin_irs<0b1100, "orr",
3686 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3687 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3688 defm EOR : AsI1_bin_irs<0b0001, "eor",
3689 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3690 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3691 defm BIC : AsI1_bin_irs<0b1110, "bic",
3692 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3693 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3695 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3696 // like in the actual instruction encoding. The complexity of mapping the mask
3697 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3698 // instruction description.
3699 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3700 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3701 "bfc", "\t$Rd, $imm", "$src = $Rd",
3702 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3703 Requires<[IsARM, HasV6T2]> {
3706 let Inst{27-21} = 0b0111110;
3707 let Inst{6-0} = 0b0011111;
3708 let Inst{15-12} = Rd;
3709 let Inst{11-7} = imm{4-0}; // lsb
3710 let Inst{20-16} = imm{9-5}; // msb
3713 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3714 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3715 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3716 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3717 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3718 bf_inv_mask_imm:$imm))]>,
3719 Requires<[IsARM, HasV6T2]> {
3723 let Inst{27-21} = 0b0111110;
3724 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3725 let Inst{15-12} = Rd;
3726 let Inst{11-7} = imm{4-0}; // lsb
3727 let Inst{20-16} = imm{9-5}; // width
3731 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3732 "mvn", "\t$Rd, $Rm",
3733 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
3737 let Inst{19-16} = 0b0000;
3738 let Inst{11-4} = 0b00000000;
3739 let Inst{15-12} = Rd;
3742 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3743 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3744 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
3749 let Inst{19-16} = 0b0000;
3750 let Inst{15-12} = Rd;
3751 let Inst{11-5} = shift{11-5};
3753 let Inst{3-0} = shift{3-0};
3755 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3756 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3757 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
3762 let Inst{19-16} = 0b0000;
3763 let Inst{15-12} = Rd;
3764 let Inst{11-8} = shift{11-8};
3766 let Inst{6-5} = shift{6-5};
3768 let Inst{3-0} = shift{3-0};
3770 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3771 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm,
3772 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3773 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
3777 let Inst{19-16} = 0b0000;
3778 let Inst{15-12} = Rd;
3779 let Inst{11-0} = imm;
3782 def : ARMPat<(and GPR:$src, mod_imm_not:$imm),
3783 (BICri GPR:$src, mod_imm_not:$imm)>;
3785 //===----------------------------------------------------------------------===//
3786 // Multiply Instructions.
3788 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3789 string opc, string asm, list<dag> pattern>
3790 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3794 let Inst{19-16} = Rd;
3795 let Inst{11-8} = Rm;
3798 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3799 string opc, string asm, list<dag> pattern>
3800 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3805 let Inst{19-16} = RdHi;
3806 let Inst{15-12} = RdLo;
3807 let Inst{11-8} = Rm;
3810 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3811 string opc, string asm, list<dag> pattern>
3812 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3817 let Inst{19-16} = RdHi;
3818 let Inst{15-12} = RdLo;
3819 let Inst{11-8} = Rm;
3823 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3824 // property. Remove them when it's possible to add those properties
3825 // on an individual MachineInstr, not just an instruction description.
3826 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3827 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3828 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3829 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3830 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3831 Requires<[IsARM, HasV6]> {
3832 let Inst{15-12} = 0b0000;
3833 let Unpredictable{15-12} = 0b1111;
3836 let Constraints = "@earlyclobber $Rd" in
3837 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3838 pred:$p, cc_out:$s),
3840 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3841 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3842 Requires<[IsARM, NoV6, UseMulOps]>;
3845 def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd),
3846 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra),
3847 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3848 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>,
3849 Requires<[IsARM, HasV6, UseMulOps]> {
3851 let Inst{15-12} = Ra;
3854 let Constraints = "@earlyclobber $Rd" in
3855 def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd),
3856 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
3857 pred:$p, cc_out:$s), 4, IIC_iMAC32,
3858 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))],
3859 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>,
3860 Requires<[IsARM, NoV6]>;
3862 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3863 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3864 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3865 Requires<[IsARM, HasV6T2, UseMulOps]> {
3870 let Inst{19-16} = Rd;
3871 let Inst{15-12} = Ra;
3872 let Inst{11-8} = Rm;
3876 // Extra precision multiplies with low / high results
3877 let hasSideEffects = 0 in {
3878 let isCommutable = 1 in {
3879 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3880 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3881 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3882 Requires<[IsARM, HasV6]>;
3884 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3885 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3886 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3887 Requires<[IsARM, HasV6]>;
3889 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3890 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3891 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3893 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3894 Requires<[IsARM, NoV6]>;
3896 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3897 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3899 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3900 Requires<[IsARM, NoV6]>;
3904 // Multiply + accumulate
3905 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3906 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3907 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3908 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3909 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3910 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3911 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3912 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3914 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3915 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3916 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3917 Requires<[IsARM, HasV6]> {
3922 let Inst{19-16} = RdHi;
3923 let Inst{15-12} = RdLo;
3924 let Inst{11-8} = Rm;
3929 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in {
3930 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3931 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3933 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3934 pred:$p, cc_out:$s)>,
3935 Requires<[IsARM, NoV6]>;
3936 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3937 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3939 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3940 pred:$p, cc_out:$s)>,
3941 Requires<[IsARM, NoV6]>;
3946 // Most significant word multiply
3947 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3948 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3949 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3950 Requires<[IsARM, HasV6]> {
3951 let Inst{15-12} = 0b1111;
3954 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3955 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3956 Requires<[IsARM, HasV6]> {
3957 let Inst{15-12} = 0b1111;
3960 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3961 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3962 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3963 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3964 Requires<[IsARM, HasV6, UseMulOps]>;
3966 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3967 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3968 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3969 Requires<[IsARM, HasV6]>;
3971 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3972 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3973 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3974 Requires<[IsARM, HasV6, UseMulOps]>;
3976 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3977 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3978 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3979 Requires<[IsARM, HasV6]>;
3981 multiclass AI_smul<string opc, PatFrag opnode> {
3982 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3983 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3984 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3985 (sext_inreg GPR:$Rm, i16)))]>,
3986 Requires<[IsARM, HasV5TE]>;
3988 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3989 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3990 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3991 (sra GPR:$Rm, (i32 16))))]>,
3992 Requires<[IsARM, HasV5TE]>;
3994 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3995 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3996 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3997 (sext_inreg GPR:$Rm, i16)))]>,
3998 Requires<[IsARM, HasV5TE]>;
4000 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4001 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
4002 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
4003 (sra GPR:$Rm, (i32 16))))]>,
4004 Requires<[IsARM, HasV5TE]>;
4006 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4007 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
4009 Requires<[IsARM, HasV5TE]>;
4011 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4012 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
4014 Requires<[IsARM, HasV5TE]>;
4018 multiclass AI_smla<string opc, PatFrag opnode> {
4019 let DecoderMethod = "DecodeSMLAInstruction" in {
4020 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
4021 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4022 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
4023 [(set GPRnopc:$Rd, (add GPR:$Ra,
4024 (opnode (sext_inreg GPRnopc:$Rn, i16),
4025 (sext_inreg GPRnopc:$Rm, i16))))]>,
4026 Requires<[IsARM, HasV5TE, UseMulOps]>;
4028 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
4029 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4030 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
4032 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
4033 (sra GPRnopc:$Rm, (i32 16)))))]>,
4034 Requires<[IsARM, HasV5TE, UseMulOps]>;
4036 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
4037 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4038 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
4040 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
4041 (sext_inreg GPRnopc:$Rm, i16))))]>,
4042 Requires<[IsARM, HasV5TE, UseMulOps]>;
4044 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
4045 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4046 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
4048 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
4049 (sra GPRnopc:$Rm, (i32 16)))))]>,
4050 Requires<[IsARM, HasV5TE, UseMulOps]>;
4052 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
4053 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4054 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
4056 Requires<[IsARM, HasV5TE, UseMulOps]>;
4058 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
4059 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4060 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
4062 Requires<[IsARM, HasV5TE, UseMulOps]>;
4066 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
4067 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
4069 // Halfword multiply accumulate long: SMLAL<x><y>.
4070 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4071 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4072 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4073 Requires<[IsARM, HasV5TE]>;
4075 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4076 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4077 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4078 Requires<[IsARM, HasV5TE]>;
4080 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4081 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4082 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4083 Requires<[IsARM, HasV5TE]>;
4085 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4086 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4087 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4088 Requires<[IsARM, HasV5TE]>;
4090 // Helper class for AI_smld.
4091 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
4092 InstrItinClass itin, string opc, string asm>
4093 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
4096 let Inst{27-23} = 0b01110;
4097 let Inst{22} = long;
4098 let Inst{21-20} = 0b00;
4099 let Inst{11-8} = Rm;
4106 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
4107 InstrItinClass itin, string opc, string asm>
4108 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4110 let Inst{15-12} = 0b1111;
4111 let Inst{19-16} = Rd;
4113 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
4114 InstrItinClass itin, string opc, string asm>
4115 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4118 let Inst{19-16} = Rd;
4119 let Inst{15-12} = Ra;
4121 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
4122 InstrItinClass itin, string opc, string asm>
4123 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4126 let Inst{19-16} = RdHi;
4127 let Inst{15-12} = RdLo;
4130 multiclass AI_smld<bit sub, string opc> {
4132 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
4133 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4134 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
4136 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
4137 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4138 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
4140 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4141 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4142 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
4144 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4145 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4146 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
4150 defm SMLA : AI_smld<0, "smla">;
4151 defm SMLS : AI_smld<1, "smls">;
4153 multiclass AI_sdml<bit sub, string opc> {
4155 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
4156 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
4157 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
4158 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
4161 defm SMUA : AI_sdml<0, "smua">;
4162 defm SMUS : AI_sdml<1, "smus">;
4164 //===----------------------------------------------------------------------===//
4165 // Division Instructions (ARMv7-A with virtualization extension)
4167 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4168 "sdiv", "\t$Rd, $Rn, $Rm",
4169 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
4170 Requires<[IsARM, HasDivideInARM]>;
4172 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4173 "udiv", "\t$Rd, $Rn, $Rm",
4174 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
4175 Requires<[IsARM, HasDivideInARM]>;
4177 //===----------------------------------------------------------------------===//
4178 // Misc. Arithmetic Instructions.
4181 def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
4182 IIC_iUNAr, "clz", "\t$Rd, $Rm",
4183 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
4186 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4187 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
4188 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
4189 Requires<[IsARM, HasV6T2]>,
4192 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4193 IIC_iUNAr, "rev", "\t$Rd, $Rm",
4194 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
4197 let AddedComplexity = 5 in
4198 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4199 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
4200 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
4201 Requires<[IsARM, HasV6]>,
4204 def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)),
4205 (REV16 (LDRH addrmode3:$addr))>;
4206 def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr),
4207 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>;
4209 let AddedComplexity = 5 in
4210 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4211 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
4212 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
4213 Requires<[IsARM, HasV6]>,
4216 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
4217 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
4220 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
4221 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
4222 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
4223 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
4224 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
4226 Requires<[IsARM, HasV6]>,
4227 Sched<[WriteALUsi, ReadALU]>;
4229 // Alternate cases for PKHBT where identities eliminate some nodes.
4230 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
4231 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
4232 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
4233 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
4235 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
4236 // will match the pattern below.
4237 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
4238 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
4239 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
4240 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
4241 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
4243 Requires<[IsARM, HasV6]>,
4244 Sched<[WriteALUsi, ReadALU]>;
4246 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
4247 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
4248 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
4249 // pkhtb src1, src2, asr (17..31).
4250 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4251 (srl GPRnopc:$src2, imm16:$sh)),
4252 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>;
4253 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4254 (sra GPRnopc:$src2, imm16_31:$sh)),
4255 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
4256 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4257 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
4258 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
4260 //===----------------------------------------------------------------------===//
4264 // + CRC32{B,H,W} 0x04C11DB7
4265 // + CRC32C{B,H,W} 0x1EDC6F41
4268 class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
4269 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary,
4270 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
4271 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>,
4272 Requires<[IsARM, HasV8, HasCRC]> {
4277 let Inst{31-28} = 0b1110;
4278 let Inst{27-23} = 0b00010;
4279 let Inst{22-21} = sz;
4281 let Inst{19-16} = Rn;
4282 let Inst{15-12} = Rd;
4283 let Inst{11-10} = 0b00;
4286 let Inst{7-4} = 0b0100;
4289 let Unpredictable{11-8} = 0b1101;
4292 def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>;
4293 def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>;
4294 def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>;
4295 def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>;
4296 def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>;
4297 def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>;
4299 //===----------------------------------------------------------------------===//
4300 // ARMv8.1a Privilege Access Never extension
4304 def SETPAN : AInoP<(outs), (ins imm0_1:$imm), MiscFrm, NoItinerary, "setpan",
4305 "\t$imm", []>, Requires<[IsARM, HasV8, HasV8_1a]> {
4308 let Inst{31-28} = 0b1111;
4309 let Inst{27-20} = 0b00010001;
4310 let Inst{19-16} = 0b0000;
4311 let Inst{15-10} = 0b000000;
4314 let Inst{7-4} = 0b0000;
4315 let Inst{3-0} = 0b0000;
4317 let Unpredictable{19-16} = 0b1111;
4318 let Unpredictable{15-10} = 0b111111;
4319 let Unpredictable{8} = 0b1;
4320 let Unpredictable{3-0} = 0b1111;
4323 //===----------------------------------------------------------------------===//
4324 // Comparison Instructions...
4327 defm CMP : AI1_cmp_irs<0b1010, "cmp",
4328 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
4329 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
4331 // ARMcmpZ can re-use the above instruction definitions.
4332 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm),
4333 (CMPri GPR:$src, mod_imm:$imm)>;
4334 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4335 (CMPrr GPR:$src, GPR:$rhs)>;
4336 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4337 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4338 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4339 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4341 // CMN register-integer
4342 let isCompare = 1, Defs = [CPSR] in {
4343 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi,
4344 "cmn", "\t$Rn, $imm",
4345 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>,
4346 Sched<[WriteCMP, ReadALU]> {
4351 let Inst{19-16} = Rn;
4352 let Inst{15-12} = 0b0000;
4353 let Inst{11-0} = imm;
4355 let Unpredictable{15-12} = 0b1111;
4358 // CMN register-register/shift
4359 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4360 "cmn", "\t$Rn, $Rm",
4361 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4362 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4365 let isCommutable = 1;
4368 let Inst{19-16} = Rn;
4369 let Inst{15-12} = 0b0000;
4370 let Inst{11-4} = 0b00000000;
4373 let Unpredictable{15-12} = 0b1111;
4376 def CMNzrsi : AI1<0b1011, (outs),
4377 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4378 "cmn", "\t$Rn, $shift",
4379 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4380 GPR:$Rn, so_reg_imm:$shift)]>,
4381 Sched<[WriteCMPsi, ReadALU]> {
4386 let Inst{19-16} = Rn;
4387 let Inst{15-12} = 0b0000;
4388 let Inst{11-5} = shift{11-5};
4390 let Inst{3-0} = shift{3-0};
4392 let Unpredictable{15-12} = 0b1111;
4395 def CMNzrsr : AI1<0b1011, (outs),
4396 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4397 "cmn", "\t$Rn, $shift",
4398 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4399 GPRnopc:$Rn, so_reg_reg:$shift)]>,
4400 Sched<[WriteCMPsr, ReadALU]> {
4405 let Inst{19-16} = Rn;
4406 let Inst{15-12} = 0b0000;
4407 let Inst{11-8} = shift{11-8};
4409 let Inst{6-5} = shift{6-5};
4411 let Inst{3-0} = shift{3-0};
4413 let Unpredictable{15-12} = 0b1111;
4418 def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm),
4419 (CMNri GPR:$src, mod_imm_neg:$imm)>;
4421 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm),
4422 (CMNri GPR:$src, mod_imm_neg:$imm)>;
4424 // Note that TST/TEQ don't set all the same flags that CMP does!
4425 defm TST : AI1_cmp_irs<0b1000, "tst",
4426 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4427 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1,
4428 "DecodeTSTInstruction">;
4429 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4430 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4431 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4433 // Pseudo i64 compares for some floating point compares.
4434 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4436 def BCCi64 : PseudoInst<(outs),
4437 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4439 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
4442 def BCCZi64 : PseudoInst<(outs),
4443 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4444 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
4446 } // usesCustomInserter
4449 // Conditional moves
4450 let hasSideEffects = 0 in {
4452 let isCommutable = 1, isSelect = 1 in
4453 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
4454 (ins GPR:$false, GPR:$Rm, cmovpred:$p),
4456 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
4458 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4460 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4461 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p),
4464 (ARMcmov GPR:$false, so_reg_imm:$shift,
4466 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4467 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4468 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p),
4470 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4472 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4475 let isMoveImm = 1 in
4477 : ARMPseudoInst<(outs GPR:$Rd),
4478 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
4480 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm,
4482 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
4485 let isMoveImm = 1 in
4486 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4487 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
4489 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm,
4491 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4493 // Two instruction predicate mov immediate.
4494 let isMoveImm = 1 in
4496 : ARMPseudoInst<(outs GPR:$Rd),
4497 (ins GPR:$false, i32imm:$src, cmovpred:$p),
4499 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
4501 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4503 let isMoveImm = 1 in
4504 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4505 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
4507 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm,
4509 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4514 //===----------------------------------------------------------------------===//
4515 // Atomic operations intrinsics
4518 def MemBarrierOptOperand : AsmOperandClass {
4519 let Name = "MemBarrierOpt";
4520 let ParserMethod = "parseMemBarrierOptOperand";
4522 def memb_opt : Operand<i32> {
4523 let PrintMethod = "printMemBOption";
4524 let ParserMatchClass = MemBarrierOptOperand;
4525 let DecoderMethod = "DecodeMemBarrierOption";
4528 def InstSyncBarrierOptOperand : AsmOperandClass {
4529 let Name = "InstSyncBarrierOpt";
4530 let ParserMethod = "parseInstSyncBarrierOptOperand";
4532 def instsyncb_opt : Operand<i32> {
4533 let PrintMethod = "printInstSyncBOption";
4534 let ParserMatchClass = InstSyncBarrierOptOperand;
4535 let DecoderMethod = "DecodeInstSyncBarrierOption";
4538 // Memory barriers protect the atomic sequences
4539 let hasSideEffects = 1 in {
4540 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4541 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>,
4542 Requires<[IsARM, HasDB]> {
4544 let Inst{31-4} = 0xf57ff05;
4545 let Inst{3-0} = opt;
4548 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4549 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>,
4550 Requires<[IsARM, HasDB]> {
4552 let Inst{31-4} = 0xf57ff04;
4553 let Inst{3-0} = opt;
4556 // ISB has only full system option
4557 def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary,
4558 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>,
4559 Requires<[IsARM, HasDB]> {
4561 let Inst{31-4} = 0xf57ff06;
4562 let Inst{3-0} = opt;
4566 let usesCustomInserter = 1, Defs = [CPSR] in {
4568 // Pseudo instruction that combines movs + predicated rsbmi
4569 // to implement integer ABS
4570 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4573 let usesCustomInserter = 1 in {
4574 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4575 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4577 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4580 def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4581 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4584 def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4585 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4588 def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4589 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4592 def strex_1 : PatFrag<(ops node:$val, node:$ptr),
4593 (int_arm_strex node:$val, node:$ptr), [{
4594 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4597 def strex_2 : PatFrag<(ops node:$val, node:$ptr),
4598 (int_arm_strex node:$val, node:$ptr), [{
4599 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4602 def strex_4 : PatFrag<(ops node:$val, node:$ptr),
4603 (int_arm_strex node:$val, node:$ptr), [{
4604 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4607 def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4608 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4611 def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4612 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4615 def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4616 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4619 def stlex_1 : PatFrag<(ops node:$val, node:$ptr),
4620 (int_arm_stlex node:$val, node:$ptr), [{
4621 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4624 def stlex_2 : PatFrag<(ops node:$val, node:$ptr),
4625 (int_arm_stlex node:$val, node:$ptr), [{
4626 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4629 def stlex_4 : PatFrag<(ops node:$val, node:$ptr),
4630 (int_arm_stlex node:$val, node:$ptr), [{
4631 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4634 let mayLoad = 1 in {
4635 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4636 NoItinerary, "ldrexb", "\t$Rt, $addr",
4637 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
4638 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4639 NoItinerary, "ldrexh", "\t$Rt, $addr",
4640 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
4641 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4642 NoItinerary, "ldrex", "\t$Rt, $addr",
4643 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>;
4644 let hasExtraDefRegAllocReq = 1 in
4645 def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4646 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
4647 let DecoderMethod = "DecodeDoubleRegLoad";
4650 def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4651 NoItinerary, "ldaexb", "\t$Rt, $addr",
4652 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>;
4653 def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4654 NoItinerary, "ldaexh", "\t$Rt, $addr",
4655 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>;
4656 def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4657 NoItinerary, "ldaex", "\t$Rt, $addr",
4658 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>;
4659 let hasExtraDefRegAllocReq = 1 in
4660 def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4661 NoItinerary, "ldaexd", "\t$Rt, $addr", []> {
4662 let DecoderMethod = "DecodeDoubleRegLoad";
4666 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4667 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4668 NoItinerary, "strexb", "\t$Rd, $Rt, $addr",
4669 [(set GPR:$Rd, (strex_1 GPR:$Rt,
4670 addr_offset_none:$addr))]>;
4671 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4672 NoItinerary, "strexh", "\t$Rd, $Rt, $addr",
4673 [(set GPR:$Rd, (strex_2 GPR:$Rt,
4674 addr_offset_none:$addr))]>;
4675 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4676 NoItinerary, "strex", "\t$Rd, $Rt, $addr",
4677 [(set GPR:$Rd, (strex_4 GPR:$Rt,
4678 addr_offset_none:$addr))]>;
4679 let hasExtraSrcRegAllocReq = 1 in
4680 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4681 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4682 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4683 let DecoderMethod = "DecodeDoubleRegStore";
4685 def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4686 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr",
4688 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>;
4689 def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4690 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr",
4692 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>;
4693 def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4694 NoItinerary, "stlex", "\t$Rd, $Rt, $addr",
4696 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>;
4697 let hasExtraSrcRegAllocReq = 1 in
4698 def STLEXD : AIstlex<0b01, (outs GPR:$Rd),
4699 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4700 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> {
4701 let DecoderMethod = "DecodeDoubleRegStore";
4705 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
4707 Requires<[IsARM, HasV7]> {
4708 let Inst{31-0} = 0b11110101011111111111000000011111;
4711 def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4712 (STREXB GPR:$Rt, addr_offset_none:$addr)>;
4713 def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4714 (STREXH GPR:$Rt, addr_offset_none:$addr)>;
4716 def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4717 (STLEXB GPR:$Rt, addr_offset_none:$addr)>;
4718 def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4719 (STLEXH GPR:$Rt, addr_offset_none:$addr)>;
4721 class acquiring_load<PatFrag base>
4722 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
4723 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4724 return isAtLeastAcquire(Ordering);
4727 def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
4728 def atomic_load_acquire_16 : acquiring_load<atomic_load_16>;
4729 def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
4731 class releasing_store<PatFrag base>
4732 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
4733 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4734 return isAtLeastRelease(Ordering);
4737 def atomic_store_release_8 : releasing_store<atomic_store_8>;
4738 def atomic_store_release_16 : releasing_store<atomic_store_16>;
4739 def atomic_store_release_32 : releasing_store<atomic_store_32>;
4741 let AddedComplexity = 8 in {
4742 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>;
4743 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>;
4744 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>;
4745 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>;
4746 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>;
4747 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>;
4750 // SWP/SWPB are deprecated in V6/V7.
4751 let mayLoad = 1, mayStore = 1 in {
4752 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4753 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>,
4755 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4756 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>,
4760 //===----------------------------------------------------------------------===//
4761 // Coprocessor Instructions.
4764 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4765 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4766 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4767 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4768 imm:$CRm, imm:$opc2)]>,
4777 let Inst{3-0} = CRm;
4779 let Inst{7-5} = opc2;
4780 let Inst{11-8} = cop;
4781 let Inst{15-12} = CRd;
4782 let Inst{19-16} = CRn;
4783 let Inst{23-20} = opc1;
4786 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4787 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4788 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4789 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4790 imm:$CRm, imm:$opc2)]>,
4792 let Inst{31-28} = 0b1111;
4800 let Inst{3-0} = CRm;
4802 let Inst{7-5} = opc2;
4803 let Inst{11-8} = cop;
4804 let Inst{15-12} = CRd;
4805 let Inst{19-16} = CRn;
4806 let Inst{23-20} = opc1;
4809 class ACI<dag oops, dag iops, string opc, string asm,
4810 IndexMode im = IndexModeNone>
4811 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4813 let Inst{27-25} = 0b110;
4815 class ACInoP<dag oops, dag iops, string opc, string asm,
4816 IndexMode im = IndexModeNone>
4817 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4819 let Inst{31-28} = 0b1111;
4820 let Inst{27-25} = 0b110;
4822 multiclass LdStCop<bit load, bit Dbit, string asm> {
4823 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4824 asm, "\t$cop, $CRd, $addr"> {
4828 let Inst{24} = 1; // P = 1
4829 let Inst{23} = addr{8};
4830 let Inst{22} = Dbit;
4831 let Inst{21} = 0; // W = 0
4832 let Inst{20} = load;
4833 let Inst{19-16} = addr{12-9};
4834 let Inst{15-12} = CRd;
4835 let Inst{11-8} = cop;
4836 let Inst{7-0} = addr{7-0};
4837 let DecoderMethod = "DecodeCopMemInstruction";
4839 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4840 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4844 let Inst{24} = 1; // P = 1
4845 let Inst{23} = addr{8};
4846 let Inst{22} = Dbit;
4847 let Inst{21} = 1; // W = 1
4848 let Inst{20} = load;
4849 let Inst{19-16} = addr{12-9};
4850 let Inst{15-12} = CRd;
4851 let Inst{11-8} = cop;
4852 let Inst{7-0} = addr{7-0};
4853 let DecoderMethod = "DecodeCopMemInstruction";
4855 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4856 postidx_imm8s4:$offset),
4857 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4862 let Inst{24} = 0; // P = 0
4863 let Inst{23} = offset{8};
4864 let Inst{22} = Dbit;
4865 let Inst{21} = 1; // W = 1
4866 let Inst{20} = load;
4867 let Inst{19-16} = addr;
4868 let Inst{15-12} = CRd;
4869 let Inst{11-8} = cop;
4870 let Inst{7-0} = offset{7-0};
4871 let DecoderMethod = "DecodeCopMemInstruction";
4873 def _OPTION : ACI<(outs),
4874 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4875 coproc_option_imm:$option),
4876 asm, "\t$cop, $CRd, $addr, $option"> {
4881 let Inst{24} = 0; // P = 0
4882 let Inst{23} = 1; // U = 1
4883 let Inst{22} = Dbit;
4884 let Inst{21} = 0; // W = 0
4885 let Inst{20} = load;
4886 let Inst{19-16} = addr;
4887 let Inst{15-12} = CRd;
4888 let Inst{11-8} = cop;
4889 let Inst{7-0} = option;
4890 let DecoderMethod = "DecodeCopMemInstruction";
4893 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4894 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4895 asm, "\t$cop, $CRd, $addr"> {
4899 let Inst{24} = 1; // P = 1
4900 let Inst{23} = addr{8};
4901 let Inst{22} = Dbit;
4902 let Inst{21} = 0; // W = 0
4903 let Inst{20} = load;
4904 let Inst{19-16} = addr{12-9};
4905 let Inst{15-12} = CRd;
4906 let Inst{11-8} = cop;
4907 let Inst{7-0} = addr{7-0};
4908 let DecoderMethod = "DecodeCopMemInstruction";
4910 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4911 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4915 let Inst{24} = 1; // P = 1
4916 let Inst{23} = addr{8};
4917 let Inst{22} = Dbit;
4918 let Inst{21} = 1; // W = 1
4919 let Inst{20} = load;
4920 let Inst{19-16} = addr{12-9};
4921 let Inst{15-12} = CRd;
4922 let Inst{11-8} = cop;
4923 let Inst{7-0} = addr{7-0};
4924 let DecoderMethod = "DecodeCopMemInstruction";
4926 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4927 postidx_imm8s4:$offset),
4928 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4933 let Inst{24} = 0; // P = 0
4934 let Inst{23} = offset{8};
4935 let Inst{22} = Dbit;
4936 let Inst{21} = 1; // W = 1
4937 let Inst{20} = load;
4938 let Inst{19-16} = addr;
4939 let Inst{15-12} = CRd;
4940 let Inst{11-8} = cop;
4941 let Inst{7-0} = offset{7-0};
4942 let DecoderMethod = "DecodeCopMemInstruction";
4944 def _OPTION : ACInoP<(outs),
4945 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4946 coproc_option_imm:$option),
4947 asm, "\t$cop, $CRd, $addr, $option"> {
4952 let Inst{24} = 0; // P = 0
4953 let Inst{23} = 1; // U = 1
4954 let Inst{22} = Dbit;
4955 let Inst{21} = 0; // W = 0
4956 let Inst{20} = load;
4957 let Inst{19-16} = addr;
4958 let Inst{15-12} = CRd;
4959 let Inst{11-8} = cop;
4960 let Inst{7-0} = option;
4961 let DecoderMethod = "DecodeCopMemInstruction";
4965 defm LDC : LdStCop <1, 0, "ldc">;
4966 defm LDCL : LdStCop <1, 1, "ldcl">;
4967 defm STC : LdStCop <0, 0, "stc">;
4968 defm STCL : LdStCop <0, 1, "stcl">;
4969 defm LDC2 : LdSt2Cop<1, 0, "ldc2">, Requires<[PreV8]>;
4970 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">, Requires<[PreV8]>;
4971 defm STC2 : LdSt2Cop<0, 0, "stc2">, Requires<[PreV8]>;
4972 defm STC2L : LdSt2Cop<0, 1, "stc2l">, Requires<[PreV8]>;
4974 //===----------------------------------------------------------------------===//
4975 // Move between coprocessor and ARM core register.
4978 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4980 : ABI<0b1110, oops, iops, NoItinerary, opc,
4981 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4982 let Inst{20} = direction;
4992 let Inst{15-12} = Rt;
4993 let Inst{11-8} = cop;
4994 let Inst{23-21} = opc1;
4995 let Inst{7-5} = opc2;
4996 let Inst{3-0} = CRm;
4997 let Inst{19-16} = CRn;
5000 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
5002 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5003 c_imm:$CRm, imm0_7:$opc2),
5004 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
5005 imm:$CRm, imm:$opc2)]>,
5006 ComplexDeprecationPredicate<"MCR">;
5007 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
5008 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5009 c_imm:$CRm, 0, pred:$p)>;
5010 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
5011 (outs GPRwithAPSR:$Rt),
5012 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
5014 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
5015 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
5016 c_imm:$CRm, 0, pred:$p)>;
5018 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
5019 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
5021 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
5023 : ABXI<0b1110, oops, iops, NoItinerary,
5024 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
5025 let Inst{31-24} = 0b11111110;
5026 let Inst{20} = direction;
5036 let Inst{15-12} = Rt;
5037 let Inst{11-8} = cop;
5038 let Inst{23-21} = opc1;
5039 let Inst{7-5} = opc2;
5040 let Inst{3-0} = CRm;
5041 let Inst{19-16} = CRn;
5044 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
5046 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5047 c_imm:$CRm, imm0_7:$opc2),
5048 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
5049 imm:$CRm, imm:$opc2)]>,
5051 def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm",
5052 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5054 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
5055 (outs GPRwithAPSR:$Rt),
5056 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
5059 def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm",
5060 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
5063 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
5064 imm:$CRm, imm:$opc2),
5065 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
5067 class MovRRCopro<string opc, bit direction, dag oops, dag iops, list<dag>
5069 : ABI<0b1100, oops, iops, NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm",
5072 let Inst{23-21} = 0b010;
5073 let Inst{20} = direction;
5081 let Inst{15-12} = Rt;
5082 let Inst{19-16} = Rt2;
5083 let Inst{11-8} = cop;
5084 let Inst{7-4} = opc1;
5085 let Inst{3-0} = CRm;
5088 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
5089 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt,
5090 GPRnopc:$Rt2, c_imm:$CRm),
5091 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
5092 GPRnopc:$Rt2, imm:$CRm)]>;
5093 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */,
5094 (outs GPRnopc:$Rt, GPRnopc:$Rt2),
5095 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>;
5097 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
5098 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5099 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
5100 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>,
5102 let Inst{31-28} = 0b1111;
5103 let Inst{23-21} = 0b010;
5104 let Inst{20} = direction;
5112 let Inst{15-12} = Rt;
5113 let Inst{19-16} = Rt2;
5114 let Inst{11-8} = cop;
5115 let Inst{7-4} = opc1;
5116 let Inst{3-0} = CRm;
5118 let DecoderMethod = "DecodeMRRC2";
5121 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
5122 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
5123 GPRnopc:$Rt2, imm:$CRm)]>;
5124 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
5126 //===----------------------------------------------------------------------===//
5127 // Move between special register and ARM core register
5130 // Move to ARM core register from Special Register
5131 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5132 "mrs", "\t$Rd, apsr", []> {
5134 let Inst{23-16} = 0b00001111;
5135 let Unpredictable{19-17} = 0b111;
5137 let Inst{15-12} = Rd;
5139 let Inst{11-0} = 0b000000000000;
5140 let Unpredictable{11-0} = 0b110100001111;
5143 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
5146 // The MRSsys instruction is the MRS instruction from the ARM ARM,
5147 // section B9.3.9, with the R bit set to 1.
5148 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5149 "mrs", "\t$Rd, spsr", []> {
5151 let Inst{23-16} = 0b01001111;
5152 let Unpredictable{19-16} = 0b1111;
5154 let Inst{15-12} = Rd;
5156 let Inst{11-0} = 0b000000000000;
5157 let Unpredictable{11-0} = 0b110100001111;
5160 // However, the MRS (banked register) system instruction (ARMv7VE) *does* have a
5161 // separate encoding (distinguished by bit 5.
5162 def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked),
5163 NoItinerary, "mrs", "\t$Rd, $banked", []>,
5164 Requires<[IsARM, HasVirtualization]> {
5169 let Inst{22} = banked{5}; // R bit
5170 let Inst{21-20} = 0b00;
5171 let Inst{19-16} = banked{3-0};
5172 let Inst{15-12} = Rd;
5173 let Inst{11-9} = 0b001;
5174 let Inst{8} = banked{4};
5175 let Inst{7-0} = 0b00000000;
5178 // Move from ARM core register to Special Register
5180 // No need to have both system and application versions of MSR (immediate) or
5181 // MSR (register), the encodings are the same and the assembly parser has no way
5182 // to distinguish between them. The mask operand contains the special register
5183 // (R Bit) in bit 4 and bits 3-0 contains the mask with the fields to be
5184 // accessed in the special register.
5185 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
5186 "msr", "\t$mask, $Rn", []> {
5191 let Inst{22} = mask{4}; // R bit
5192 let Inst{21-20} = 0b10;
5193 let Inst{19-16} = mask{3-0};
5194 let Inst{15-12} = 0b1111;
5195 let Inst{11-4} = 0b00000000;
5199 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary,
5200 "msr", "\t$mask, $imm", []> {
5205 let Inst{22} = mask{4}; // R bit
5206 let Inst{21-20} = 0b10;
5207 let Inst{19-16} = mask{3-0};
5208 let Inst{15-12} = 0b1111;
5209 let Inst{11-0} = imm;
5212 // However, the MSR (banked register) system instruction (ARMv7VE) *does* have a
5213 // separate encoding (distinguished by bit 5.
5214 def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn),
5215 NoItinerary, "msr", "\t$banked, $Rn", []>,
5216 Requires<[IsARM, HasVirtualization]> {
5221 let Inst{22} = banked{5}; // R bit
5222 let Inst{21-20} = 0b10;
5223 let Inst{19-16} = banked{3-0};
5224 let Inst{15-12} = 0b1111;
5225 let Inst{11-9} = 0b001;
5226 let Inst{8} = banked{4};
5227 let Inst{7-4} = 0b0000;
5231 // Dynamic stack allocation yields a _chkstk for Windows targets. These calls
5232 // are needed to probe the stack when allocating more than
5233 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
5234 // ensure that the guard pages used by the OS virtual memory manager are
5235 // allocated in correct sequence.
5236 // The main point of having separate instruction are extra unmodelled effects
5237 // (compared to ordinary calls) like stack pointer change.
5239 def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone,
5240 [SDNPHasChain, SDNPSideEffect]>;
5241 let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP] in
5242 def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>;
5244 def win__dbzchk : SDNode<"ARMISD::WIN__DBZCHK", SDT_WIN__DBZCHK,
5245 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
5246 let usesCustomInserter = 1, Defs = [CPSR] in
5247 def WIN__DBZCHK : PseudoInst<(outs), (ins GPR:$divisor), NoItinerary,
5248 [(win__dbzchk GPR:$divisor)]>;
5250 //===----------------------------------------------------------------------===//
5254 // __aeabi_read_tp preserves the registers r1-r3.
5255 // This is a pseudo inst so that we can get the encoding right,
5256 // complete with fixup for the aeabi_read_tp function.
5257 // TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern
5258 // is defined in "ARMInstrThumb.td".
5260 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
5261 def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br,
5262 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
5265 //===----------------------------------------------------------------------===//
5266 // SJLJ Exception handling intrinsics
5267 // eh_sjlj_setjmp() is an instruction sequence to store the return
5268 // address and save #0 in R0 for the non-longjmp case.
5269 // Since by its nature we may be coming from some other function to get
5270 // here, and we're using the stack frame for the containing function to
5271 // save/restore registers, we can't keep anything live in regs across
5272 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
5273 // when we get here from a longjmp(). We force everything out of registers
5274 // except for our own input by listing the relevant registers in Defs. By
5275 // doing so, we also cause the prologue/epilogue code to actively preserve
5276 // all of the callee-saved resgisters, which is exactly what we want.
5277 // A constant value is passed in $val, and we use the location as a scratch.
5279 // These are pseudo-instructions and are lowered to individual MC-insts, so
5280 // no encoding information is necessary.
5282 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
5283 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
5284 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5285 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5287 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5288 Requires<[IsARM, HasVFP2]>;
5292 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
5293 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5294 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5296 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5297 Requires<[IsARM, NoVFP]>;
5300 // FIXME: Non-IOS version(s)
5301 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
5302 Defs = [ R7, LR, SP ] in {
5303 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
5305 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
5309 let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1 in
5310 def Int_eh_sjlj_setup_dispatch : PseudoInst<(outs), (ins), NoItinerary,
5311 [(ARMeh_sjlj_setup_dispatch)]>;
5313 // eh.sjlj.dispatchsetup pseudo-instruction.
5314 // This pseudo is used for both ARM and Thumb. Any differences are handled when
5315 // the pseudo is expanded (which happens before any passes that need the
5316 // instruction size).
5317 let isBarrier = 1 in
5318 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
5321 //===----------------------------------------------------------------------===//
5322 // Non-Instruction Patterns
5325 // ARMv4 indirect branch using (MOVr PC, dst)
5326 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
5327 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
5328 4, IIC_Br, [(brind GPR:$dst)],
5329 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
5330 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
5332 // Large immediate handling.
5334 // 32-bit immediate using two piece mod_imms or movw + movt.
5335 // This is a single pseudo instruction, the benefit is that it can be remat'd
5336 // as a single unit instead of having to handle reg inputs.
5337 // FIXME: Remove this when we can do generalized remat.
5338 let isReMaterializable = 1, isMoveImm = 1 in
5339 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
5340 [(set GPR:$dst, (arm_i32imm:$src))]>,
5343 def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i,
5344 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>,
5345 Requires<[IsARM, DontUseMovt]>;
5347 // Pseudo instruction that combines movw + movt + add pc (if PIC).
5348 // It also makes it possible to rematerialize the instructions.
5349 // FIXME: Remove this when we can do generalized remat and when machine licm
5350 // can properly the instructions.
5351 let isReMaterializable = 1 in {
5352 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5354 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
5355 Requires<[IsARM, UseMovt]>;
5357 def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5360 (ARMWrapperPIC tglobaladdr:$addr))]>,
5361 Requires<[IsARM, DontUseMovt]>;
5363 let AddedComplexity = 10 in
5364 def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5367 (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5368 Requires<[IsARM, DontUseMovt]>;
5370 let AddedComplexity = 10 in
5371 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5373 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5374 Requires<[IsARM, UseMovt]>;
5375 } // isReMaterializable
5377 // ConstantPool, GlobalAddress, and JumpTable
5378 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
5379 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
5380 Requires<[IsARM, UseMovt]>;
5381 def : ARMPat<(ARMWrapperJT tjumptable:$dst),
5382 (LEApcrelJT tjumptable:$dst)>;
5384 // TODO: add,sub,and, 3-instr forms?
5386 // Tail calls. These patterns also apply to Thumb mode.
5387 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
5388 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
5389 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
5392 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
5393 def : ARMPat<(ARMcall_nolink texternalsym:$func),
5394 (BMOVPCB_CALL texternalsym:$func)>;
5396 // zextload i1 -> zextload i8
5397 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5398 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5400 // extload -> zextload
5401 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5402 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5403 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5404 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5406 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
5408 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
5409 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
5412 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5413 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5414 (SMULBB GPR:$a, GPR:$b)>;
5415 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
5416 (SMULBB GPR:$a, GPR:$b)>;
5417 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5418 (sra GPR:$b, (i32 16))),
5419 (SMULBT GPR:$a, GPR:$b)>;
5420 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
5421 (SMULBT GPR:$a, GPR:$b)>;
5422 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
5423 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5424 (SMULTB GPR:$a, GPR:$b)>;
5425 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
5426 (SMULTB GPR:$a, GPR:$b)>;
5428 def : ARMV5MOPat<(add GPR:$acc,
5429 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5430 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5431 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5432 def : ARMV5MOPat<(add GPR:$acc,
5433 (mul sext_16_node:$a, sext_16_node:$b)),
5434 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5435 def : ARMV5MOPat<(add GPR:$acc,
5436 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5437 (sra GPR:$b, (i32 16)))),
5438 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5439 def : ARMV5MOPat<(add GPR:$acc,
5440 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
5441 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5442 def : ARMV5MOPat<(add GPR:$acc,
5443 (mul (sra GPR:$a, (i32 16)),
5444 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5445 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5446 def : ARMV5MOPat<(add GPR:$acc,
5447 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
5448 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5451 // Pre-v7 uses MCR for synchronization barriers.
5452 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
5453 Requires<[IsARM, HasV6]>;
5455 // SXT/UXT with no rotate
5456 let AddedComplexity = 16 in {
5457 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5458 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
5459 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
5460 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
5461 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
5462 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
5463 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5466 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5467 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5469 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5470 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5471 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5472 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5474 // Atomic load/store patterns
5475 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
5476 (LDRBrs ldst_so_reg:$src)>;
5477 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
5478 (LDRBi12 addrmode_imm12:$src)>;
5479 def : ARMPat<(atomic_load_16 addrmode3:$src),
5480 (LDRH addrmode3:$src)>;
5481 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5482 (LDRrs ldst_so_reg:$src)>;
5483 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5484 (LDRi12 addrmode_imm12:$src)>;
5485 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5486 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5487 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5488 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5489 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5490 (STRH GPR:$val, addrmode3:$ptr)>;
5491 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5492 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5493 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5494 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5497 //===----------------------------------------------------------------------===//
5501 include "ARMInstrThumb.td"
5503 //===----------------------------------------------------------------------===//
5507 include "ARMInstrThumb2.td"
5509 //===----------------------------------------------------------------------===//
5510 // Floating Point Support
5513 include "ARMInstrVFP.td"
5515 //===----------------------------------------------------------------------===//
5516 // Advanced SIMD (NEON) Support
5519 include "ARMInstrNEON.td"
5521 //===----------------------------------------------------------------------===//
5522 // Assembler aliases
5526 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5527 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5528 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5530 // System instructions
5531 def : MnemonicAlias<"swi", "svc">;
5533 // Load / Store Multiple
5534 def : MnemonicAlias<"ldmfd", "ldm">;
5535 def : MnemonicAlias<"ldmia", "ldm">;
5536 def : MnemonicAlias<"ldmea", "ldmdb">;
5537 def : MnemonicAlias<"stmfd", "stmdb">;
5538 def : MnemonicAlias<"stmia", "stm">;
5539 def : MnemonicAlias<"stmea", "stm">;
5541 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5542 // shift amount is zero (i.e., unspecified).
5543 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5544 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5545 Requires<[IsARM, HasV6]>;
5546 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5547 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5548 Requires<[IsARM, HasV6]>;
5550 // PUSH/POP aliases for STM/LDM
5551 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5552 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5554 // SSAT/USAT optional shift operand.
5555 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5556 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5557 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5558 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5561 // Extend instruction optional rotate operand.
5562 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5563 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5564 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5565 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5566 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5567 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5568 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5569 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5570 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5571 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5572 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5573 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5575 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5576 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5577 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5578 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5579 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5580 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5581 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5582 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5583 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5584 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5585 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5586 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5590 def : MnemonicAlias<"rfefa", "rfeda">;
5591 def : MnemonicAlias<"rfeea", "rfedb">;
5592 def : MnemonicAlias<"rfefd", "rfeia">;
5593 def : MnemonicAlias<"rfeed", "rfeib">;
5594 def : MnemonicAlias<"rfe", "rfeia">;
5597 def : MnemonicAlias<"srsfa", "srsib">;
5598 def : MnemonicAlias<"srsea", "srsia">;
5599 def : MnemonicAlias<"srsfd", "srsdb">;
5600 def : MnemonicAlias<"srsed", "srsda">;
5601 def : MnemonicAlias<"srs", "srsia">;
5604 def : MnemonicAlias<"qsubaddx", "qsax">;
5606 def : MnemonicAlias<"saddsubx", "sasx">;
5607 // SHASX == SHADDSUBX
5608 def : MnemonicAlias<"shaddsubx", "shasx">;
5609 // SHSAX == SHSUBADDX
5610 def : MnemonicAlias<"shsubaddx", "shsax">;
5612 def : MnemonicAlias<"ssubaddx", "ssax">;
5614 def : MnemonicAlias<"uaddsubx", "uasx">;
5615 // UHASX == UHADDSUBX
5616 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5617 // UHSAX == UHSUBADDX
5618 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5619 // UQASX == UQADDSUBX
5620 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5621 // UQSAX == UQSUBADDX
5622 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5624 def : MnemonicAlias<"usubaddx", "usax">;
5626 // "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like
5628 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5629 (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
5630 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5631 (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
5632 // Same for AND <--> BIC
5633 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5634 (ANDri rGPR:$Rd, rGPR:$Rn, mod_imm_not:$imm,
5635 pred:$p, cc_out:$s)>;
5636 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5637 (ANDri rGPR:$Rdn, rGPR:$Rdn, mod_imm_not:$imm,
5638 pred:$p, cc_out:$s)>;
5639 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5640 (BICri rGPR:$Rd, rGPR:$Rn, mod_imm_not:$imm,
5641 pred:$p, cc_out:$s)>;
5642 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5643 (BICri rGPR:$Rdn, rGPR:$Rdn, mod_imm_not:$imm,
5644 pred:$p, cc_out:$s)>;
5646 // Likewise, "add Rd, mod_imm_neg" -> sub
5647 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5648 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5649 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5650 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5651 // Same for CMP <--> CMN via mod_imm_neg
5652 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5653 (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
5654 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5655 (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
5657 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5658 // LSR, ROR, and RRX instructions.
5659 // FIXME: We need C++ parser hooks to map the alias to the MOV
5660 // encoding. It seems we should be able to do that sort of thing
5661 // in tblgen, but it could get ugly.
5662 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5663 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5664 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5666 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5667 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5669 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5670 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5672 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5673 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5676 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5677 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
5678 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5679 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5680 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5682 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5683 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5685 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5686 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5688 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5689 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5693 // "neg" is and alias for "rsb rd, rn, #0"
5694 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5695 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5697 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5698 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5699 Requires<[IsARM, NoV6]>;
5701 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
5702 // the instruction definitions need difference constraints pre-v6.
5703 // Use these aliases for the assembly parsing on pre-v6.
5704 def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm",
5705 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
5706 Requires<[IsARM, NoV6]>;
5707 def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra",
5708 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
5709 pred:$p, cc_out:$s)>,
5710 Requires<[IsARM, NoV6]>;
5711 def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5712 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5713 Requires<[IsARM, NoV6]>;
5714 def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5715 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5716 Requires<[IsARM, NoV6]>;
5717 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5718 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5719 Requires<[IsARM, NoV6]>;
5720 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5721 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5722 Requires<[IsARM, NoV6]>;
5724 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5726 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>,
5727 ComplexDeprecationPredicate<"IT">;
5729 let mayLoad = 1, mayStore =1, hasSideEffects = 1 in
5730 def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn),
5732 [(set GPR:$Rd, (int_arm_space imm:$size, GPR:$Rn))]>;