1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file describes the ARM instructions in TableGen format.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // ARM specific DAG Nodes.
20 def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
39 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
40 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
42 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
45 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
46 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
48 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq,
49 [SDNPHasChain, SDNPOutFlag]>;
50 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq,
51 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
53 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
54 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
55 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
56 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
57 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
58 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
60 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTRet,
61 [SDNPHasChain, SDNPOptInFlag]>;
63 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
65 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
68 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
69 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
71 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
74 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
77 def ARMcmpNZ : SDNode<"ARMISD::CMPNZ", SDT_ARMCmp,
80 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
82 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
83 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
84 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
86 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
88 //===----------------------------------------------------------------------===//
89 // ARM Instruction Predicate Definitions.
91 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
92 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
93 def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
94 def IsThumb : Predicate<"Subtarget->isThumb()">;
95 def IsARM : Predicate<"!Subtarget->isThumb()">;
97 //===----------------------------------------------------------------------===//
98 // ARM Flag Definitions.
100 class RegConstraint<string C> {
101 string Constraints = C;
104 //===----------------------------------------------------------------------===//
105 // ARM specific transformation functions and pattern fragments.
108 // so_imm_XFORM - Return a so_imm value packed into the format described for
110 def so_imm_XFORM : SDNodeXForm<imm, [{
111 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(N->getValue()),
115 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
116 // so_imm_neg def below.
117 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
118 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(-(int)N->getValue()),
122 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
123 // so_imm_not def below.
124 def so_imm_not_XFORM : SDNodeXForm<imm, [{
125 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(~(int)N->getValue()),
129 // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
130 def rot_imm : PatLeaf<(i32 imm), [{
131 int32_t v = (int32_t)N->getValue();
132 return v == 8 || v == 16 || v == 24;
135 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
136 def imm1_15 : PatLeaf<(i32 imm), [{
137 return (int32_t)N->getValue() >= 1 && (int32_t)N->getValue() < 16;
140 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
141 def imm16_31 : PatLeaf<(i32 imm), [{
142 return (int32_t)N->getValue() >= 16 && (int32_t)N->getValue() < 32;
146 PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(-(int)N->getValue()) != -1; }],
150 PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(~(int)N->getValue()) != -1; }],
153 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
154 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
155 return CurDAG->ComputeNumSignBits(SDOperand(N,0)) >= 17;
160 //===----------------------------------------------------------------------===//
161 // Operand Definitions.
165 def brtarget : Operand<OtherVT>;
167 // A list of registers separated by comma. Used by load/store multiple.
168 def reglist : Operand<i32> {
169 let PrintMethod = "printRegisterList";
172 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
173 def cpinst_operand : Operand<i32> {
174 let PrintMethod = "printCPInstOperand";
177 def jtblock_operand : Operand<i32> {
178 let PrintMethod = "printJTBlockOperand";
182 def pclabel : Operand<i32> {
183 let PrintMethod = "printPCLabel";
186 // shifter_operand operands: so_reg and so_imm.
187 def so_reg : Operand<i32>, // reg reg imm
188 ComplexPattern<i32, 3, "SelectShifterOperandReg",
189 [shl,srl,sra,rotr]> {
190 let PrintMethod = "printSORegOperand";
191 let MIOperandInfo = (ops GPR, GPR, i32imm);
194 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
195 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
196 // represented in the imm field in the same 12-bit form that they are encoded
197 // into so_imm instructions: the 8-bit immediate is the least significant bits
198 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
199 def so_imm : Operand<i32>,
201 [{ return ARM_AM::getSOImmVal(N->getValue()) != -1; }],
203 let PrintMethod = "printSOImmOperand";
206 // Break so_imm's up into two pieces. This handles immediates with up to 16
207 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
208 // get the first/second pieces.
209 def so_imm2part : Operand<i32>,
211 [{ return ARM_AM::isSOImmTwoPartVal((unsigned)N->getValue()); }]> {
212 let PrintMethod = "printSOImm2PartOperand";
215 def so_imm2part_1 : SDNodeXForm<imm, [{
216 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getValue());
217 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
220 def so_imm2part_2 : SDNodeXForm<imm, [{
221 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getValue());
222 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
226 // Define ARM specific addressing modes.
228 // addrmode2 := reg +/- reg shop imm
229 // addrmode2 := reg +/- imm12
231 def addrmode2 : Operand<i32>,
232 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
233 let PrintMethod = "printAddrMode2Operand";
234 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
237 def am2offset : Operand<i32>,
238 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
239 let PrintMethod = "printAddrMode2OffsetOperand";
240 let MIOperandInfo = (ops GPR, i32imm);
243 // addrmode3 := reg +/- reg
244 // addrmode3 := reg +/- imm8
246 def addrmode3 : Operand<i32>,
247 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
248 let PrintMethod = "printAddrMode3Operand";
249 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
252 def am3offset : Operand<i32>,
253 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
254 let PrintMethod = "printAddrMode3OffsetOperand";
255 let MIOperandInfo = (ops GPR, i32imm);
258 // addrmode4 := reg, <mode|W>
260 def addrmode4 : Operand<i32>,
261 ComplexPattern<i32, 2, "", []> {
262 let PrintMethod = "printAddrMode4Operand";
263 let MIOperandInfo = (ops GPR, i32imm);
266 // addrmode5 := reg +/- imm8*4
268 def addrmode5 : Operand<i32>,
269 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
270 let PrintMethod = "printAddrMode5Operand";
271 let MIOperandInfo = (ops GPR, i32imm);
274 // addrmodepc := pc + reg
276 def addrmodepc : Operand<i32>,
277 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
278 let PrintMethod = "printAddrModePCOperand";
279 let MIOperandInfo = (ops GPR, i32imm);
282 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
283 // register whose default is 0 (no register).
284 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
285 (ops (i32 14), (i32 zero_reg))> {
286 let PrintMethod = "printPredicateOperand";
289 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
291 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
292 let PrintMethod = "printSBitModifierOperand";
295 //===----------------------------------------------------------------------===//
296 // ARM Instruction flags. These need to match ARMInstrInfo.h.
300 class AddrMode<bits<4> val> {
303 def AddrModeNone : AddrMode<0>;
304 def AddrMode1 : AddrMode<1>;
305 def AddrMode2 : AddrMode<2>;
306 def AddrMode3 : AddrMode<3>;
307 def AddrMode4 : AddrMode<4>;
308 def AddrMode5 : AddrMode<5>;
309 def AddrModeT1 : AddrMode<6>;
310 def AddrModeT2 : AddrMode<7>;
311 def AddrModeT4 : AddrMode<8>;
312 def AddrModeTs : AddrMode<9>;
315 class SizeFlagVal<bits<3> val> {
318 def SizeInvalid : SizeFlagVal<0>; // Unset.
319 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
320 def Size8Bytes : SizeFlagVal<2>;
321 def Size4Bytes : SizeFlagVal<3>;
322 def Size2Bytes : SizeFlagVal<4>;
324 // Load / store index mode.
325 class IndexMode<bits<2> val> {
328 def IndexModeNone : IndexMode<0>;
329 def IndexModePre : IndexMode<1>;
330 def IndexModePost : IndexMode<2>;
332 //===----------------------------------------------------------------------===//
333 // ARM Instruction templates.
336 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
337 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
338 list<Predicate> Predicates = [IsARM];
340 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
341 list<Predicate> Predicates = [IsARM, HasV5TE];
343 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
344 list<Predicate> Predicates = [IsARM, HasV6];
347 class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im,
350 let Namespace = "ARM";
352 bits<4> Opcode = opcod;
354 bits<4> AddrModeBits = AM.Value;
357 bits<3> SizeFlag = SZ.Value;
360 bits<2> IndexModeBits = IM.Value;
362 let Constraints = cstr;
365 class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern>
366 : InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, ""> {
367 let OutOperandList = oops;
368 let InOperandList = iops;
370 let Pattern = pattern;
373 // Almost all ARM instructions are predicable.
374 class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, IndexMode im,
375 string opc, string asm, string cstr, list<dag> pattern>
376 // FIXME: Set all opcodes to 0 for now.
377 : InstARM<0, am, sz, im, cstr> {
378 let OutOperandList = oops;
379 let InOperandList = !con(iops, (ops pred:$p));
380 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
381 let Pattern = pattern;
382 list<Predicate> Predicates = [IsARM];
385 // Same as I except it can optionally modify CPSR. Note it's modeled as
386 // an input operand since by default it's a zero register. It will
387 // become an implicit def once it's "flipped".
388 class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, IndexMode im,
389 string opc, string asm, string cstr, list<dag> pattern>
390 // FIXME: Set all opcodes to 0 for now.
391 : InstARM<0, am, sz, im, cstr> {
392 let OutOperandList = oops;
393 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
394 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
395 let Pattern = pattern;
396 list<Predicate> Predicates = [IsARM];
399 class AI<dag oops, dag iops, string opc, string asm, list<dag> pattern>
400 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, opc, asm,"",pattern>;
401 class AsI<dag oops, dag iops, string opc, string asm, list<dag> pattern>
402 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, opc,asm,"",pattern>;
403 class AI1<dag oops, dag iops, string opc, string asm, list<dag> pattern>
404 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
405 class AsI1<dag oops, dag iops, string opc, string asm, list<dag> pattern>
406 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
407 class AI2<dag oops, dag iops, string opc, string asm, list<dag> pattern>
408 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
409 class AI3<dag oops, dag iops, string opc, string asm, list<dag> pattern>
410 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
411 class AI4<dag oops, dag iops, string opc, string asm, list<dag> pattern>
412 : I<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
413 class AI1x2<dag oops, dag iops, string opc, string asm, list<dag> pattern>
414 : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, opc, asm, "", pattern>;
417 class AI2pr<dag oops, dag iops, string opc, string asm, string cstr,
419 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, opc, asm, cstr, pattern>;
420 class AI3pr<dag oops, dag iops, string opc, string asm, string cstr,
422 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, opc, asm, cstr, pattern>;
425 class AI2po<dag oops, dag iops, string opc, string asm, string cstr,
427 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, opc, asm, cstr,pattern>;
428 class AI3po<dag oops, dag iops, string opc, string asm, string cstr,
430 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, opc, asm, cstr,pattern>;
433 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
434 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
437 /// AI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
438 /// binop that produces a value.
439 multiclass AsI1_bin_irs<string opc, PatFrag opnode> {
440 def ri : AsI1<(outs GPR:$dst), (ins GPR:$a, so_imm:$b),
441 opc, " $dst, $a, $b",
442 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
443 def rr : AsI1<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
444 opc, " $dst, $a, $b",
445 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
446 def rs : AsI1<(outs GPR:$dst), (ins GPR:$a, so_reg:$b),
447 opc, " $dst, $a, $b",
448 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
451 /// ASI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
452 /// instruction modifies the CSPR register.
453 multiclass ASI1_bin_s_irs<string opc, PatFrag opnode> {
454 def ri : AI1<(outs GPR:$dst), (ins GPR:$a, so_imm:$b),
455 opc, "s $dst, $a, $b",
456 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>, Imp<[], [CPSR]>;
457 def rr : AI1<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
458 opc, "s $dst, $a, $b",
459 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>, Imp<[], [CPSR]>;
460 def rs : AI1<(outs GPR:$dst), (ins GPR:$a, so_reg:$b),
461 opc, "s $dst, $a, $b",
462 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>, Imp<[], [CPSR]>;
465 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
466 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
467 /// a explicit result, only implicitly set CPSR.
468 multiclass AI1_cmp_irs<string opc, PatFrag opnode> {
469 def ri : AI1<(outs), (ins GPR:$a, so_imm:$b),
471 [(opnode GPR:$a, so_imm:$b)]>, Imp<[], [CPSR]>;
472 def rr : AI1<(outs), (ins GPR:$a, GPR:$b),
474 [(opnode GPR:$a, GPR:$b)]>, Imp<[], [CPSR]>;
475 def rs : AI1<(outs), (ins GPR:$a, so_reg:$b),
477 [(opnode GPR:$a, so_reg:$b)]>, Imp<[], [CPSR]>;
480 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
481 /// register and one whose operand is a register rotated by 8/16/24.
482 multiclass AI_unary_rrot<string opc, PatFrag opnode> {
483 def r : AI<(outs GPR:$dst), (ins GPR:$Src),
485 [(set GPR:$dst, (opnode GPR:$Src))]>, Requires<[IsARM, HasV6]>;
486 def r_rot : AI<(outs GPR:$dst), (ins GPR:$Src, i32imm:$rot),
487 opc, " $dst, $Src, ror $rot",
488 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>,
489 Requires<[IsARM, HasV6]>;
492 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
493 /// register and one whose operand is a register rotated by 8/16/24.
494 multiclass AI_bin_rrot<string opc, PatFrag opnode> {
495 def rr : AI<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
496 opc, " $dst, $LHS, $RHS",
497 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
498 Requires<[IsARM, HasV6]>;
499 def rr_rot : AI<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
500 opc, " $dst, $LHS, $RHS, ror $rot",
501 [(set GPR:$dst, (opnode GPR:$LHS,
502 (rotr GPR:$RHS, rot_imm:$rot)))]>,
503 Requires<[IsARM, HasV6]>;
507 class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, IndexMode im,
508 string asm, string cstr, list<dag> pattern>
509 // FIXME: Set all opcodes to 0 for now.
510 : InstARM<0, am, sz, im, cstr> {
511 let OutOperandList = oops;
512 let InOperandList = iops;
514 let Pattern = pattern;
515 list<Predicate> Predicates = [IsARM];
518 class AXI<dag oops, dag iops, string asm, list<dag> pattern>
519 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, asm, "", pattern>;
520 class AXI1<dag oops, dag iops, string asm, list<dag> pattern>
521 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, asm, "", pattern>;
522 class AXI2<dag oops, dag iops, string asm, list<dag> pattern>
523 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, asm, "", pattern>;
524 class AXI3<dag oops, dag iops, string asm, list<dag> pattern>
525 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, asm, "", pattern>;
526 class AXI4<dag oops, dag iops, string asm, list<dag> pattern>
527 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, asm, "", pattern>;
529 class AXIx2<dag oops, dag iops, string asm, list<dag> pattern>
530 : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, asm, "", pattern>;
532 // BR_JT instructions
533 class JTI<dag oops, dag iops, string asm, list<dag> pattern>
534 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, asm, "", pattern>;
535 class JTI1<dag oops, dag iops, string asm, list<dag> pattern>
536 : XI<oops, iops, AddrMode1, SizeSpecial, IndexModeNone, asm, "", pattern>;
537 class JTI2<dag oops, dag iops, string asm, list<dag> pattern>
538 : XI<oops, iops, AddrMode2, SizeSpecial, IndexModeNone, asm, "", pattern>;
540 /// AsXI1_bin_c_irs - Same as AsI1_bin_irs but without the predicate operand and
541 /// setting carry bit. But it can optionally set CPSR.
542 multiclass AsXI1_bin_c_irs<string opc, PatFrag opnode> {
543 def ri : AXI1<(outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
544 !strconcat(opc, "${s} $dst, $a, $b"),
545 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>, Imp<[CPSR], []>;
546 def rr : AXI1<(outs GPR:$dst), (ins GPR:$a, GPR:$b, cc_out:$s),
547 !strconcat(opc, "${s} $dst, $a, $b"),
548 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>, Imp<[CPSR], []>;
549 def rs : AXI1<(outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
550 !strconcat(opc, "${s} $dst, $a, $b"),
551 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>, Imp<[CPSR], []>;
554 //===----------------------------------------------------------------------===//
556 //===----------------------------------------------------------------------===//
558 //===----------------------------------------------------------------------===//
559 // Miscellaneous Instructions.
561 def IMPLICIT_DEF_GPR :
562 PseudoInst<(outs GPR:$rD), (ins pred:$p),
563 "@ IMPLICIT_DEF_GPR $rD",
564 [(set GPR:$rD, (undef))]>;
567 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
568 /// the function. The first operand is the ID# for this instruction, the second
569 /// is the index into the MachineConstantPool that this is, the third is the
570 /// size in bytes of this constant pool entry.
571 let isNotDuplicable = 1 in
572 def CONSTPOOL_ENTRY :
573 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
575 "${instid:label} ${cpidx:cpentry}", []>;
578 PseudoInst<(outs), (ins i32imm:$amt, pred:$p),
579 "@ ADJCALLSTACKUP $amt",
580 [(ARMcallseq_end imm:$amt)]>, Imp<[SP],[SP]>;
582 def ADJCALLSTACKDOWN :
583 PseudoInst<(outs), (ins i32imm:$amt, pred:$p),
584 "@ ADJCALLSTACKDOWN $amt",
585 [(ARMcallseq_start imm:$amt)]>, Imp<[SP],[SP]>;
588 PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
589 ".loc $file, $line, $col",
590 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
592 let isNotDuplicable = 1 in {
593 def PICADD : AXI1<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
594 "$cp:\n\tadd$p $dst, pc, $a",
595 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
597 let isLoad = 1, AddedComplexity = 10 in {
598 def PICLD : AXI2<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
599 "${addr:label}:\n\tldr$p $dst, $addr",
600 [(set GPR:$dst, (load addrmodepc:$addr))]>;
602 def PICLDZH : AXI3<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
603 "${addr:label}:\n\tldr${p}h $dst, $addr",
604 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
606 def PICLDZB : AXI2<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
607 "${addr:label}:\n\tldr${p}b $dst, $addr",
608 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
610 def PICLDH : AXI3<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
611 "${addr:label}:\n\tldr${p}h $dst, $addr",
612 [(set GPR:$dst, (extloadi16 addrmodepc:$addr))]>;
614 def PICLDB : AXI2<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
615 "${addr:label}:\n\tldr${p}b $dst, $addr",
616 [(set GPR:$dst, (extloadi8 addrmodepc:$addr))]>;
618 def PICLDSH : AXI3<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
619 "${addr:label}:\n\tldr${p}sh $dst, $addr",
620 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
622 def PICLDSB : AXI3<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
623 "${addr:label}:\n\tldr${p}sb $dst, $addr",
624 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
626 let isStore = 1, AddedComplexity = 10 in {
627 def PICSTR : AXI2<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
628 "${addr:label}:\n\tstr$p $src, $addr",
629 [(store GPR:$src, addrmodepc:$addr)]>;
631 def PICSTRH : AXI3<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
632 "${addr:label}:\n\tstr${p}h $src, $addr",
633 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
635 def PICSTRB : AXI2<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
636 "${addr:label}:\n\tstr${p}b $src, $addr",
637 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
641 //===----------------------------------------------------------------------===//
642 // Control Flow Instructions.
645 let isReturn = 1, isTerminator = 1 in
646 def BX_RET : AI<(outs), (ins), "bx", " lr", [(ARMretflag)]>;
648 // FIXME: remove when we have a way to marking a MI with these properties.
649 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
651 let isLoad = 1, isReturn = 1, isTerminator = 1 in
652 def LDM_RET : AXI4<(outs),
653 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
654 "ldm${p}${addr:submode} $addr, $dst1",
658 Defs = [R0, R1, R2, R3, R12, LR,
659 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
660 def BL : AXI<(outs), (ins i32imm:$func, variable_ops),
662 [(ARMcall tglobaladdr:$func)]>;
664 def BL_pred : AI<(outs), (ins i32imm:$func, variable_ops),
665 "bl", " ${func:call}",
666 [(ARMcall_pred tglobaladdr:$func)]>;
669 def BLX : AXI<(outs), (ins GPR:$func, variable_ops),
671 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T]>;
674 def BX : AXIx2<(outs), (ins GPR:$func, variable_ops),
675 "mov lr, pc\n\tbx $func",
676 [(ARMcall_nolink GPR:$func)]>;
680 let isBranch = 1, isTerminator = 1 in {
681 // B is "predicable" since it can be xformed into a Bcc.
682 let isBarrier = 1 in {
683 let isPredicable = 1 in
684 def B : AXI<(outs), (ins brtarget:$target), "b $target",
687 let isNotDuplicable = 1 in {
688 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
689 "mov pc, $target \n$jt",
690 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
691 def BR_JTm : JTI2<(outs), (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
692 "ldr pc, $target \n$jt",
693 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
695 def BR_JTadd : JTI1<(outs), (ins GPR:$target, GPR:$idx, jtblock_operand:$jt,
697 "add pc, $target, $idx \n$jt",
698 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
703 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
704 // a two-value operand where a dag node expects two operands. :(
705 def Bcc : AI<(outs), (ins brtarget:$target), "b", " $target",
706 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
709 //===----------------------------------------------------------------------===//
710 // Load / store Instructions.
715 def LDR : AI2<(outs GPR:$dst), (ins addrmode2:$addr),
716 "ldr", " $dst, $addr",
717 [(set GPR:$dst, (load addrmode2:$addr))]>;
719 // Special LDR for loads from non-pc-relative constpools.
720 let isReMaterializable = 1 in
721 def LDRcp : AI2<(outs GPR:$dst), (ins addrmode2:$addr),
722 "ldr", " $dst, $addr", []>;
724 // Loads with zero extension
725 def LDRH : AI3<(outs GPR:$dst), (ins addrmode3:$addr),
726 "ldr", "h $dst, $addr",
727 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
729 def LDRB : AI2<(outs GPR:$dst), (ins addrmode2:$addr),
730 "ldr", "b $dst, $addr",
731 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
733 // Loads with sign extension
734 def LDRSH : AI3<(outs GPR:$dst), (ins addrmode3:$addr),
735 "ldr", "sh $dst, $addr",
736 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
738 def LDRSB : AI3<(outs GPR:$dst), (ins addrmode3:$addr),
739 "ldr", "sb $dst, $addr",
740 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
743 def LDRD : AI3<(outs GPR:$dst), (ins addrmode3:$addr),
744 "ldr", "d $dst, $addr",
745 []>, Requires<[IsARM, HasV5T]>;
748 def LDR_PRE : AI2pr<(outs GPR:$dst, GPR:$base_wb), (ins addrmode2:$addr),
749 "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>;
751 def LDR_POST : AI2po<(outs GPR:$dst, GPR:$base_wb), (ins GPR:$base, am2offset:$offset),
752 "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>;
754 def LDRH_PRE : AI3pr<(outs GPR:$dst, GPR:$base_wb), (ins addrmode3:$addr),
755 "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>;
757 def LDRH_POST : AI3po<(outs GPR:$dst, GPR:$base_wb), (ins GPR:$base,am3offset:$offset),
758 "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>;
760 def LDRB_PRE : AI2pr<(outs GPR:$dst, GPR:$base_wb), (ins addrmode2:$addr),
761 "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>;
763 def LDRB_POST : AI2po<(outs GPR:$dst, GPR:$base_wb), (ins GPR:$base,am2offset:$offset),
764 "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>;
766 def LDRSH_PRE : AI3pr<(outs GPR:$dst, GPR:$base_wb), (ins addrmode3:$addr),
767 "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>;
769 def LDRSH_POST: AI3po<(outs GPR:$dst, GPR:$base_wb), (ins GPR:$base,am3offset:$offset),
770 "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>;
772 def LDRSB_PRE : AI3pr<(outs GPR:$dst, GPR:$base_wb), (ins addrmode3:$addr),
773 "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>;
775 def LDRSB_POST: AI3po<(outs GPR:$dst, GPR:$base_wb), (ins GPR:$base,am3offset:$offset),
776 "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
781 def STR : AI2<(outs), (ins GPR:$src, addrmode2:$addr),
782 "str", " $src, $addr",
783 [(store GPR:$src, addrmode2:$addr)]>;
785 // Stores with truncate
786 def STRH : AI3<(outs), (ins GPR:$src, addrmode3:$addr),
787 "str", "h $src, $addr",
788 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
790 def STRB : AI2<(outs), (ins GPR:$src, addrmode2:$addr),
791 "str", "b $src, $addr",
792 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
795 def STRD : AI3<(outs), (ins GPR:$src, addrmode3:$addr),
796 "str", "d $src, $addr",
797 []>, Requires<[IsARM, HasV5T]>;
800 def STR_PRE : AI2pr<(outs GPR:$base_wb),
801 (ins GPR:$src, GPR:$base, am2offset:$offset),
802 "str", " $src, [$base, $offset]!", "$base = $base_wb",
804 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
806 def STR_POST : AI2po<(outs GPR:$base_wb),
807 (ins GPR:$src, GPR:$base,am2offset:$offset),
808 "str", " $src, [$base], $offset", "$base = $base_wb",
810 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
812 def STRH_PRE : AI3pr<(outs GPR:$base_wb),
813 (ins GPR:$src, GPR:$base,am3offset:$offset),
814 "str", "h $src, [$base, $offset]!", "$base = $base_wb",
816 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
818 def STRH_POST: AI3po<(outs GPR:$base_wb),
819 (ins GPR:$src, GPR:$base,am3offset:$offset),
820 "str", "h $src, [$base], $offset", "$base = $base_wb",
821 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
822 GPR:$base, am3offset:$offset))]>;
824 def STRB_PRE : AI2pr<(outs GPR:$base_wb),
825 (ins GPR:$src, GPR:$base,am2offset:$offset),
826 "str", "b $src, [$base, $offset]!", "$base = $base_wb",
827 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
828 GPR:$base, am2offset:$offset))]>;
830 def STRB_POST: AI2po<(outs GPR:$base_wb),
831 (ins GPR:$src, GPR:$base,am2offset:$offset),
832 "str", "b $src, [$base], $offset", "$base = $base_wb",
833 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
834 GPR:$base, am2offset:$offset))]>;
837 //===----------------------------------------------------------------------===//
838 // Load / store multiple Instructions.
841 // FIXME: $dst1 should be a def.
843 def LDM : AXI4<(outs),
844 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
845 "ldm${p}${addr:submode} $addr, $dst1",
849 def STM : AXI4<(outs),
850 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
851 "stm${p}${addr:submode} $addr, $src1",
854 //===----------------------------------------------------------------------===//
855 // Move Instructions.
858 def MOVr : AsI1<(outs GPR:$dst), (ins GPR:$src),
859 "mov", " $dst, $src", []>;
860 def MOVs : AsI1<(outs GPR:$dst), (ins so_reg:$src),
861 "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>;
863 let isReMaterializable = 1 in
864 def MOVi : AsI1<(outs GPR:$dst), (ins so_imm:$src),
865 "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>;
867 def MOVrx : AsI1<(outs GPR:$dst), (ins GPR:$src),
868 "mov", " $dst, $src, rrx",
869 [(set GPR:$dst, (ARMrrx GPR:$src))]>;
871 // These aren't really mov instructions, but we have to define them this way
872 // due to flag operands.
874 def MOVsrl_flag : AI1<(outs GPR:$dst), (ins GPR:$src),
875 "mov", "s $dst, $src, lsr #1",
876 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, Imp<[], [CPSR]>;
877 def MOVsra_flag : AI1<(outs GPR:$dst), (ins GPR:$src),
878 "mov", "s $dst, $src, asr #1",
879 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, Imp<[], [CPSR]>;
881 //===----------------------------------------------------------------------===//
882 // Extend Instructions.
887 defm SXTB : AI_unary_rrot<"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
888 defm SXTH : AI_unary_rrot<"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
890 defm SXTAB : AI_bin_rrot<"sxtab",
891 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
892 defm SXTAH : AI_bin_rrot<"sxtah",
893 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
895 // TODO: SXT(A){B|H}16
899 let AddedComplexity = 16 in {
900 defm UXTB : AI_unary_rrot<"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
901 defm UXTH : AI_unary_rrot<"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
902 defm UXTB16 : AI_unary_rrot<"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
904 def : ARMV6Pat<(and (shl GPR:$Src, 8), 0xFF00FF),
905 (UXTB16r_rot GPR:$Src, 24)>;
906 def : ARMV6Pat<(and (srl GPR:$Src, 8), 0xFF00FF),
907 (UXTB16r_rot GPR:$Src, 8)>;
909 defm UXTAB : AI_bin_rrot<"uxtab",
910 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
911 defm UXTAH : AI_bin_rrot<"uxtah",
912 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
915 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
916 //defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
918 // TODO: UXT(A){B|H}16
920 //===----------------------------------------------------------------------===//
921 // Arithmetic Instructions.
924 defm ADD : AsI1_bin_irs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>>;
925 defm SUB : AsI1_bin_irs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
927 // ADD and SUB with 's' bit set.
928 defm ADDS : ASI1_bin_s_irs<"add", BinOpFrag<(addc node:$LHS, node:$RHS)>>;
929 defm SUBS : ASI1_bin_s_irs<"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
931 // FIXME: Do not allow ADC / SBC to be predicated for now.
932 defm ADC : AsXI1_bin_c_irs<"adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>;
933 defm SBC : AsXI1_bin_c_irs<"sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
935 // These don't define reg/reg forms, because they are handled above.
936 def RSBri : AsI1<(outs GPR:$dst), (ins GPR:$a, so_imm:$b),
937 "rsb", " $dst, $a, $b",
938 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>;
940 def RSBrs : AsI1<(outs GPR:$dst), (ins GPR:$a, so_reg:$b),
941 "rsb", " $dst, $a, $b",
942 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>;
944 // RSB with 's' bit set.
945 def RSBSri : AI1<(outs GPR:$dst), (ins GPR:$a, so_imm:$b),
946 "rsb", "s $dst, $a, $b",
947 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>, Imp<[], [CPSR]>;
948 def RSBSrs : AI1<(outs GPR:$dst), (ins GPR:$a, so_reg:$b),
949 "rsb", "s $dst, $a, $b",
950 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>, Imp<[], [CPSR]>;
952 // FIXME: Do not allow RSC to be predicated for now. But they can set CPSR.
953 def RSCri : AXI1<(outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
954 "rsc${s} $dst, $a, $b",
955 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>, Imp<[CPSR], []>;
956 def RSCrs : AXI1<(outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
957 "rsc${s} $dst, $a, $b",
958 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>, Imp<[CPSR], []>;
960 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
961 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
962 (SUBri GPR:$src, so_imm_neg:$imm)>;
964 //def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
965 // (SUBSri GPR:$src, so_imm_neg:$imm)>;
966 //def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
967 // (SBCri GPR:$src, so_imm_neg:$imm)>;
969 // Note: These are implemented in C++ code, because they have to generate
970 // ADD/SUBrs instructions, which use a complex pattern that a xform function
972 // (mul X, 2^n+1) -> (add (X << n), X)
973 // (mul X, 2^n-1) -> (rsb X, (X << n))
976 //===----------------------------------------------------------------------===//
977 // Bitwise Instructions.
980 defm AND : AsI1_bin_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>>;
981 defm ORR : AsI1_bin_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>>;
982 defm EOR : AsI1_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>;
983 defm BIC : AsI1_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
985 def MVNr : AsI<(outs GPR:$dst), (ins GPR:$src),
986 "mvn", " $dst, $src", [(set GPR:$dst, (not GPR:$src))]>;
987 def MVNs : AsI<(outs GPR:$dst), (ins so_reg:$src),
988 "mvn", " $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>;
989 let isReMaterializable = 1 in
990 def MVNi : AsI<(outs GPR:$dst), (ins so_imm:$imm),
991 "mvn", " $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>;
993 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
994 (BICri GPR:$src, so_imm_not:$imm)>;
996 //===----------------------------------------------------------------------===//
997 // Multiply Instructions.
1000 def MUL : AsI<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
1001 "mul", " $dst, $a, $b",
1002 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
1004 def MLA : AsI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1005 "mla", " $dst, $a, $b, $c",
1006 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
1008 // Extra precision multiplies with low / high results
1009 def SMULL : AsI<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
1010 "smull", " $ldst, $hdst, $a, $b", []>;
1012 def UMULL : AsI<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
1013 "umull", " $ldst, $hdst, $a, $b", []>;
1015 // Multiply + accumulate
1016 def SMLAL : AsI<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
1017 "smlal", " $ldst, $hdst, $a, $b", []>;
1019 def UMLAL : AsI<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
1020 "umlal", " $ldst, $hdst, $a, $b", []>;
1022 def UMAAL : AI<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
1023 "umaal", " $ldst, $hdst, $a, $b", []>,
1024 Requires<[IsARM, HasV6]>;
1026 // Most significant word multiply
1027 def SMMUL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
1028 "smmul", " $dst, $a, $b",
1029 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
1030 Requires<[IsARM, HasV6]>;
1032 def SMMLA : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1033 "smmla", " $dst, $a, $b, $c",
1034 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
1035 Requires<[IsARM, HasV6]>;
1038 def SMMLS : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1039 "smmls", " $dst, $a, $b, $c",
1040 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
1041 Requires<[IsARM, HasV6]>;
1043 multiclass AI_smul<string opc, PatFrag opnode> {
1044 def BB : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
1045 !strconcat(opc, "bb"), " $dst, $a, $b",
1046 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1047 (sext_inreg GPR:$b, i16)))]>,
1048 Requires<[IsARM, HasV5TE]>;
1049 def BT : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
1050 !strconcat(opc, "bt"), " $dst, $a, $b",
1051 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1052 (sra GPR:$b, 16)))]>,
1053 Requires<[IsARM, HasV5TE]>;
1054 def TB : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
1055 !strconcat(opc, "tb"), " $dst, $a, $b",
1056 [(set GPR:$dst, (opnode (sra GPR:$a, 16),
1057 (sext_inreg GPR:$b, i16)))]>,
1058 Requires<[IsARM, HasV5TE]>;
1059 def TT : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
1060 !strconcat(opc, "tt"), " $dst, $a, $b",
1061 [(set GPR:$dst, (opnode (sra GPR:$a, 16),
1062 (sra GPR:$b, 16)))]>,
1063 Requires<[IsARM, HasV5TE]>;
1064 def WB : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
1065 !strconcat(opc, "wb"), " $dst, $a, $b",
1066 [(set GPR:$dst, (sra (opnode GPR:$a,
1067 (sext_inreg GPR:$b, i16)), 16))]>,
1068 Requires<[IsARM, HasV5TE]>;
1069 def WT : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
1070 !strconcat(opc, "wt"), " $dst, $a, $b",
1071 [(set GPR:$dst, (sra (opnode GPR:$a,
1072 (sra GPR:$b, 16)), 16))]>,
1073 Requires<[IsARM, HasV5TE]>;
1076 multiclass AI_smla<string opc, PatFrag opnode> {
1077 def BB : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1078 !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
1079 [(set GPR:$dst, (add GPR:$acc,
1080 (opnode (sext_inreg GPR:$a, i16),
1081 (sext_inreg GPR:$b, i16))))]>,
1082 Requires<[IsARM, HasV5TE]>;
1083 def BT : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1084 !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
1085 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1086 (sra GPR:$b, 16))))]>,
1087 Requires<[IsARM, HasV5TE]>;
1088 def TB : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1089 !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
1090 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
1091 (sext_inreg GPR:$b, i16))))]>,
1092 Requires<[IsARM, HasV5TE]>;
1093 def TT : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1094 !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
1095 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
1096 (sra GPR:$b, 16))))]>,
1097 Requires<[IsARM, HasV5TE]>;
1099 def WB : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1100 !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
1101 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1102 (sext_inreg GPR:$b, i16)), 16)))]>,
1103 Requires<[IsARM, HasV5TE]>;
1104 def WT : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1105 !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
1106 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1107 (sra GPR:$b, 16)), 16)))]>,
1108 Requires<[IsARM, HasV5TE]>;
1111 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1112 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1114 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
1115 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1117 //===----------------------------------------------------------------------===//
1118 // Misc. Arithmetic Instructions.
1121 def CLZ : AI<(outs GPR:$dst), (ins GPR:$src),
1122 "clz", " $dst, $src",
1123 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]>;
1125 def REV : AI<(outs GPR:$dst), (ins GPR:$src),
1126 "rev", " $dst, $src",
1127 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]>;
1129 def REV16 : AI<(outs GPR:$dst), (ins GPR:$src),
1130 "rev16", " $dst, $src",
1132 (or (and (srl GPR:$src, 8), 0xFF),
1133 (or (and (shl GPR:$src, 8), 0xFF00),
1134 (or (and (srl GPR:$src, 8), 0xFF0000),
1135 (and (shl GPR:$src, 8), 0xFF000000)))))]>,
1136 Requires<[IsARM, HasV6]>;
1138 def REVSH : AI<(outs GPR:$dst), (ins GPR:$src),
1139 "revsh", " $dst, $src",
1142 (or (srl (and GPR:$src, 0xFF00), 8),
1143 (shl GPR:$src, 8)), i16))]>,
1144 Requires<[IsARM, HasV6]>;
1146 def PKHBT : AI<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1147 "pkhbt", " $dst, $src1, $src2, LSL $shamt",
1148 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1149 (and (shl GPR:$src2, (i32 imm:$shamt)),
1151 Requires<[IsARM, HasV6]>;
1153 // Alternate cases for PKHBT where identities eliminate some nodes.
1154 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1155 (PKHBT GPR:$src1, GPR:$src2, 0)>;
1156 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1157 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1160 def PKHTB : AI<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1161 "pkhtb", " $dst, $src1, $src2, ASR $shamt",
1162 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1163 (and (sra GPR:$src2, imm16_31:$shamt),
1164 0xFFFF)))]>, Requires<[IsARM, HasV6]>;
1166 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
1167 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1168 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, 16)),
1169 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1170 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1171 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1172 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1175 //===----------------------------------------------------------------------===//
1176 // Comparison Instructions...
1179 defm CMP : AI1_cmp_irs<"cmp", BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1180 defm CMN : AI1_cmp_irs<"cmn", BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1182 // Note that TST/TEQ don't set all the same flags that CMP does!
1183 defm TST : AI1_cmp_irs<"tst", BinOpFrag<(ARMcmpNZ (and node:$LHS, node:$RHS), 0)>>;
1184 defm TEQ : AI1_cmp_irs<"teq", BinOpFrag<(ARMcmpNZ (xor node:$LHS, node:$RHS), 0)>>;
1186 defm CMPnz : AI1_cmp_irs<"cmp", BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>;
1187 defm CMNnz : AI1_cmp_irs<"cmn", BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>;
1189 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1190 (CMNri GPR:$src, so_imm_neg:$imm)>;
1192 def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm),
1193 (CMNri GPR:$src, so_imm_neg:$imm)>;
1196 // Conditional moves
1197 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1198 // a two-value operand where a dag node expects two operands. :(
1199 def MOVCCr : AI<(outs GPR:$dst), (ins GPR:$false, GPR:$true),
1200 "mov", " $dst, $true",
1201 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1202 RegConstraint<"$false = $dst">;
1204 def MOVCCs : AI<(outs GPR:$dst), (ins GPR:$false, so_reg:$true),
1205 "mov", " $dst, $true",
1206 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
1207 RegConstraint<"$false = $dst">;
1209 def MOVCCi : AI<(outs GPR:$dst), (ins GPR:$false, so_imm:$true),
1210 "mov", " $dst, $true",
1211 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1212 RegConstraint<"$false = $dst">;
1215 // LEApcrel - Load a pc-relative address into a register without offending the
1217 def LEApcrel : AXI1<(outs GPR:$dst), (ins i32imm:$label, pred:$p),
1218 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
1219 "${:private}PCRELL${:uid}+8))\n"),
1220 !strconcat("${:private}PCRELL${:uid}:\n\t",
1221 "add$p $dst, pc, #PCRELV${:uid}")),
1224 def LEApcrelJT : AXI1<(outs GPR:$dst), (ins i32imm:$label, i32imm:$id, pred:$p),
1225 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
1226 "${:private}PCRELL${:uid}+8))\n"),
1227 !strconcat("${:private}PCRELL${:uid}:\n\t",
1228 "add$p $dst, pc, #PCRELV${:uid}")),
1231 //===----------------------------------------------------------------------===//
1235 // __aeabi_read_tp preserves the registers r1-r3.
1237 Defs = [R0, R12, LR, CPSR] in {
1238 def TPsoft : AXI<(outs), (ins),
1239 "bl __aeabi_read_tp",
1240 [(set R0, ARMthread_pointer)]>;
1243 //===----------------------------------------------------------------------===//
1244 // Non-Instruction Patterns
1247 // ConstantPool, GlobalAddress, and JumpTable
1248 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>;
1249 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
1250 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1251 (LEApcrelJT tjumptable:$dst, imm:$id)>;
1253 // Large immediate handling.
1255 // Two piece so_imms.
1256 let isReMaterializable = 1 in
1257 def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src),
1258 "mov", " $dst, $src",
1259 [(set GPR:$dst, so_imm2part:$src)]>;
1261 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
1262 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1263 (so_imm2part_2 imm:$RHS))>;
1264 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
1265 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1266 (so_imm2part_2 imm:$RHS))>;
1268 // TODO: add,sub,and, 3-instr forms?
1272 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
1274 // zextload i1 -> zextload i8
1275 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1277 // extload -> zextload
1278 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1279 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1280 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
1282 // truncstore i1 -> truncstore i8
1283 def : ARMPat<(truncstorei1 GPR:$src, addrmode2:$dst),
1284 (STRB GPR:$src, addrmode2:$dst)>;
1285 def : ARMPat<(pre_truncsti1 GPR:$src, GPR:$base, am2offset:$offset),
1286 (STRB_PRE GPR:$src, GPR:$base, am2offset:$offset)>;
1287 def : ARMPat<(post_truncsti1 GPR:$src, GPR:$base, am2offset:$offset),
1288 (STRB_POST GPR:$src, GPR:$base, am2offset:$offset)>;
1291 def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra (shl GPR:$b, 16), 16)),
1292 (SMULBB GPR:$a, GPR:$b)>;
1293 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
1294 (SMULBB GPR:$a, GPR:$b)>;
1295 def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16)),
1296 (SMULBT GPR:$a, GPR:$b)>;
1297 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, 16)),
1298 (SMULBT GPR:$a, GPR:$b)>;
1299 def : ARMV5TEPat<(mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16)),
1300 (SMULTB GPR:$a, GPR:$b)>;
1301 def : ARMV5TEPat<(mul (sra GPR:$a, 16), sext_16_node:$b),
1302 (SMULTB GPR:$a, GPR:$b)>;
1303 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16),
1304 (SMULWB GPR:$a, GPR:$b)>;
1305 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), 16),
1306 (SMULWB GPR:$a, GPR:$b)>;
1308 def : ARMV5TEPat<(add GPR:$acc,
1309 (mul (sra (shl GPR:$a, 16), 16),
1310 (sra (shl GPR:$b, 16), 16))),
1311 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1312 def : ARMV5TEPat<(add GPR:$acc,
1313 (mul sext_16_node:$a, sext_16_node:$b)),
1314 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1315 def : ARMV5TEPat<(add GPR:$acc,
1316 (mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16))),
1317 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1318 def : ARMV5TEPat<(add GPR:$acc,
1319 (mul sext_16_node:$a, (sra GPR:$b, 16))),
1320 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1321 def : ARMV5TEPat<(add GPR:$acc,
1322 (mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16))),
1323 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1324 def : ARMV5TEPat<(add GPR:$acc,
1325 (mul (sra GPR:$a, 16), sext_16_node:$b)),
1326 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1327 def : ARMV5TEPat<(add GPR:$acc,
1328 (sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16)),
1329 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1330 def : ARMV5TEPat<(add GPR:$acc,
1331 (sra (mul GPR:$a, sext_16_node:$b), 16)),
1332 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1334 //===----------------------------------------------------------------------===//
1338 include "ARMInstrThumb.td"
1340 //===----------------------------------------------------------------------===//
1341 // Floating Point Support
1344 include "ARMInstrVFP.td"