1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisInt<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
68 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
70 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
71 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
75 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
76 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
77 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
79 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
80 [SDNPHasChain, SDNPOutGlue]>;
81 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
82 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
84 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
85 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
87 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
88 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
90 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
91 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
94 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
95 [SDNPHasChain, SDNPOptInGlue]>;
97 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
100 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
101 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
103 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
105 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
108 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
111 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
114 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
115 [SDNPOutGlue, SDNPCommutative]>;
117 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
119 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
120 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
121 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
123 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
124 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
125 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
126 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
127 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
128 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
129 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
132 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
134 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
136 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
137 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
139 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
141 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
142 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
145 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
147 //===----------------------------------------------------------------------===//
148 // ARM Instruction Predicate Definitions.
150 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
151 AssemblerPredicate<"HasV4TOps">;
152 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
153 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
154 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
155 AssemblerPredicate<"HasV5TEOps">;
156 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
157 AssemblerPredicate<"HasV6Ops">;
158 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
159 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
160 AssemblerPredicate<"HasV6T2Ops">;
161 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
162 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
163 AssemblerPredicate<"HasV7Ops">;
164 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
165 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
166 AssemblerPredicate<"FeatureVFP2">;
167 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
168 AssemblerPredicate<"FeatureVFP3">;
169 def HasNEON : Predicate<"Subtarget->hasNEON()">,
170 AssemblerPredicate<"FeatureNEON">;
171 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
172 AssemblerPredicate<"FeatureFP16">;
173 def HasDivide : Predicate<"Subtarget->hasDivide()">,
174 AssemblerPredicate<"FeatureHWDiv">;
175 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
176 AssemblerPredicate<"FeatureT2XtPk">;
177 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
178 AssemblerPredicate<"FeatureDSPThumb2">;
179 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
180 AssemblerPredicate<"FeatureDB">;
181 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
182 AssemblerPredicate<"FeatureMP">;
183 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
184 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
185 def IsThumb : Predicate<"Subtarget->isThumb()">,
186 AssemblerPredicate<"ModeThumb">;
187 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
188 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
189 AssemblerPredicate<"ModeThumb,FeatureThumb2">;
190 def IsARM : Predicate<"!Subtarget->isThumb()">,
191 AssemblerPredicate<"!ModeThumb">;
192 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
193 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
195 // FIXME: Eventually this will be just "hasV6T2Ops".
196 def UseMovt : Predicate<"Subtarget->useMovt()">;
197 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
198 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
200 //===----------------------------------------------------------------------===//
201 // ARM Flag Definitions.
203 class RegConstraint<string C> {
204 string Constraints = C;
207 //===----------------------------------------------------------------------===//
208 // ARM specific transformation functions and pattern fragments.
211 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
212 // so_imm_neg def below.
213 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
214 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
217 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
218 // so_imm_not def below.
219 def so_imm_not_XFORM : SDNodeXForm<imm, [{
220 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
223 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
224 def imm1_15 : ImmLeaf<i32, [{
225 return (int32_t)Imm >= 1 && (int32_t)Imm < 16;
228 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
229 def imm16_31 : ImmLeaf<i32, [{
230 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
235 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
236 }], so_imm_neg_XFORM>;
240 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
241 }], so_imm_not_XFORM>;
243 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
244 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
245 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
248 /// Split a 32-bit immediate into two 16 bit parts.
249 def hi16 : SDNodeXForm<imm, [{
250 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
253 def lo16AllZero : PatLeaf<(i32 imm), [{
254 // Returns true if all low 16-bits are 0.
255 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
258 /// imm0_65535 - An immediate is in the range [0.65535].
259 def Imm0_65535AsmOperand: AsmOperandClass { let Name = "Imm0_65535"; }
260 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
261 return Imm >= 0 && Imm < 65536;
263 let ParserMatchClass = Imm0_65535AsmOperand;
266 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
267 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
269 /// adde and sube predicates - True based on whether the carry flag output
270 /// will be needed or not.
271 def adde_dead_carry :
272 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
273 [{return !N->hasAnyUseOfValue(1);}]>;
274 def sube_dead_carry :
275 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
276 [{return !N->hasAnyUseOfValue(1);}]>;
277 def adde_live_carry :
278 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
279 [{return N->hasAnyUseOfValue(1);}]>;
280 def sube_live_carry :
281 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
282 [{return N->hasAnyUseOfValue(1);}]>;
284 // An 'and' node with a single use.
285 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
286 return N->hasOneUse();
289 // An 'xor' node with a single use.
290 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
291 return N->hasOneUse();
294 // An 'fmul' node with a single use.
295 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
296 return N->hasOneUse();
299 // An 'fadd' node which checks for single non-hazardous use.
300 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
301 return hasNoVMLxHazardUse(N);
304 // An 'fsub' node which checks for single non-hazardous use.
305 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
306 return hasNoVMLxHazardUse(N);
309 //===----------------------------------------------------------------------===//
310 // Operand Definitions.
314 // FIXME: rename brtarget to t2_brtarget
315 def brtarget : Operand<OtherVT> {
316 let EncoderMethod = "getBranchTargetOpValue";
317 let OperandType = "OPERAND_PCREL";
320 // FIXME: get rid of this one?
321 def uncondbrtarget : Operand<OtherVT> {
322 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
323 let OperandType = "OPERAND_PCREL";
326 // Branch target for ARM. Handles conditional/unconditional
327 def br_target : Operand<OtherVT> {
328 let EncoderMethod = "getARMBranchTargetOpValue";
329 let OperandType = "OPERAND_PCREL";
333 // FIXME: rename bltarget to t2_bl_target?
334 def bltarget : Operand<i32> {
335 // Encoded the same as branch targets.
336 let EncoderMethod = "getBranchTargetOpValue";
337 let OperandType = "OPERAND_PCREL";
340 // Call target for ARM. Handles conditional/unconditional
341 // FIXME: rename bl_target to t2_bltarget?
342 def bl_target : Operand<i32> {
343 // Encoded the same as branch targets.
344 let EncoderMethod = "getARMBranchTargetOpValue";
345 let OperandType = "OPERAND_PCREL";
349 // A list of registers separated by comma. Used by load/store multiple.
350 def RegListAsmOperand : AsmOperandClass {
351 let Name = "RegList";
352 let SuperClasses = [];
355 def DPRRegListAsmOperand : AsmOperandClass {
356 let Name = "DPRRegList";
357 let SuperClasses = [];
360 def SPRRegListAsmOperand : AsmOperandClass {
361 let Name = "SPRRegList";
362 let SuperClasses = [];
365 def reglist : Operand<i32> {
366 let EncoderMethod = "getRegisterListOpValue";
367 let ParserMatchClass = RegListAsmOperand;
368 let PrintMethod = "printRegisterList";
371 def dpr_reglist : Operand<i32> {
372 let EncoderMethod = "getRegisterListOpValue";
373 let ParserMatchClass = DPRRegListAsmOperand;
374 let PrintMethod = "printRegisterList";
377 def spr_reglist : Operand<i32> {
378 let EncoderMethod = "getRegisterListOpValue";
379 let ParserMatchClass = SPRRegListAsmOperand;
380 let PrintMethod = "printRegisterList";
383 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
384 def cpinst_operand : Operand<i32> {
385 let PrintMethod = "printCPInstOperand";
389 def pclabel : Operand<i32> {
390 let PrintMethod = "printPCLabel";
393 // ADR instruction labels.
394 def adrlabel : Operand<i32> {
395 let EncoderMethod = "getAdrLabelOpValue";
398 def neon_vcvt_imm32 : Operand<i32> {
399 let EncoderMethod = "getNEONVcvtImm32OpValue";
402 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
403 def rot_imm : Operand<i32>, ImmLeaf<i32, [{
404 int32_t v = (int32_t)Imm;
405 return v == 8 || v == 16 || v == 24; }]> {
406 let EncoderMethod = "getRotImmOpValue";
409 def ShifterAsmOperand : AsmOperandClass {
410 let Name = "Shifter";
411 let SuperClasses = [];
414 // shift_imm: An integer that encodes a shift amount and the type of shift
415 // (currently either asr or lsl) using the same encoding used for the
416 // immediates in so_reg operands.
417 def shift_imm : Operand<i32> {
418 let PrintMethod = "printShiftImmOperand";
419 let ParserMatchClass = ShifterAsmOperand;
422 def ShiftedRegAsmOperand : AsmOperandClass {
423 let Name = "ShiftedReg";
426 def ShiftedImmAsmOperand : AsmOperandClass {
427 let Name = "ShiftedImm";
430 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
431 def so_reg_reg : Operand<i32>, // reg reg imm
432 ComplexPattern<i32, 3, "SelectRegShifterOperand",
433 [shl, srl, sra, rotr]> {
434 let EncoderMethod = "getSORegOpValue";
435 let PrintMethod = "printSORegOperand";
436 let ParserMatchClass = ShiftedRegAsmOperand;
437 let MIOperandInfo = (ops GPR, GPR, shift_imm);
440 def so_reg_imm : Operand<i32>, // reg imm
441 ComplexPattern<i32, 3, "SelectImmShifterOperand",
442 [shl, srl, sra, rotr]> {
443 let EncoderMethod = "getSORegOpValue";
444 let PrintMethod = "printSORegOperand";
445 let ParserMatchClass = ShiftedImmAsmOperand;
446 let MIOperandInfo = (ops GPR, GPR, shift_imm);
449 // FIXME: Does this need to be distinct from so_reg?
450 def shift_so_reg : Operand<i32>, // reg reg imm
451 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
452 [shl,srl,sra,rotr]> {
453 let EncoderMethod = "getSORegOpValue";
454 let PrintMethod = "printSORegOperand";
455 let MIOperandInfo = (ops GPR, GPR, shift_imm);
458 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
459 // 8-bit immediate rotated by an arbitrary number of bits.
460 def SOImmAsmOperand: AsmOperandClass { let Name = "ARMSOImm"; }
461 def so_imm : Operand<i32>, ImmLeaf<i32, [{
462 return ARM_AM::getSOImmVal(Imm) != -1;
464 let EncoderMethod = "getSOImmOpValue";
465 let ParserMatchClass = SOImmAsmOperand;
468 // Break so_imm's up into two pieces. This handles immediates with up to 16
469 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
470 // get the first/second pieces.
471 def so_imm2part : PatLeaf<(imm), [{
472 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
475 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
477 def arm_i32imm : PatLeaf<(imm), [{
478 if (Subtarget->hasV6T2Ops())
480 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
483 /// imm0_7 predicate - Immediate in the range [0,31].
484 def Imm0_7AsmOperand: AsmOperandClass { let Name = "Imm0_7"; }
485 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
486 return Imm >= 0 && Imm < 8;
488 let ParserMatchClass = Imm0_7AsmOperand;
491 /// imm0_15 predicate - Immediate in the range [0,31].
492 def Imm0_15AsmOperand: AsmOperandClass { let Name = "Imm0_15"; }
493 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
494 return Imm >= 0 && Imm < 16;
496 let ParserMatchClass = Imm0_15AsmOperand;
499 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
500 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
501 return Imm >= 0 && Imm < 32;
504 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
505 def imm0_31_m1 : Operand<i32>, ImmLeaf<i32, [{
506 return Imm >= 0 && Imm < 32;
508 let EncoderMethod = "getImmMinusOneOpValue";
511 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
512 // a relocatable expression.
514 // FIXME: This really needs a Thumb version separate from the ARM version.
515 // While the range is the same, and can thus use the same match class,
516 // the encoding is different so it should have a different encoder method.
517 def Imm0_65535ExprAsmOperand: AsmOperandClass { let Name = "Imm0_65535Expr"; }
518 def imm0_65535_expr : Operand<i32> {
519 let EncoderMethod = "getHiLo16ImmOpValue";
520 let ParserMatchClass = Imm0_65535ExprAsmOperand;
523 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
525 def bf_inv_mask_imm : Operand<i32>,
527 return ARM::isBitFieldInvertedMask(N->getZExtValue());
529 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
530 let PrintMethod = "printBitfieldInvMaskImmOperand";
533 /// lsb_pos_imm - position of the lsb bit, used by BFI4p and t2BFI4p
534 def lsb_pos_imm : Operand<i32>, ImmLeaf<i32, [{
535 return isInt<5>(Imm);
538 /// width_imm - number of bits to be copied, used by BFI4p and t2BFI4p
539 def width_imm : Operand<i32>, ImmLeaf<i32, [{
540 return Imm > 0 && Imm <= 32;
542 let EncoderMethod = "getMsbOpValue";
545 def ssat_imm : Operand<i32>, ImmLeaf<i32, [{
546 return Imm > 0 && Imm <= 32;
548 let EncoderMethod = "getSsatBitPosValue";
551 // Define ARM specific addressing modes.
553 def MemMode2AsmOperand : AsmOperandClass {
554 let Name = "MemMode2";
555 let SuperClasses = [];
556 let ParserMethod = "tryParseMemMode2Operand";
559 def MemMode3AsmOperand : AsmOperandClass {
560 let Name = "MemMode3";
561 let SuperClasses = [];
562 let ParserMethod = "tryParseMemMode3Operand";
565 // addrmode_imm12 := reg +/- imm12
567 def addrmode_imm12 : Operand<i32>,
568 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
569 // 12-bit immediate operand. Note that instructions using this encode
570 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
571 // immediate values are as normal.
573 let EncoderMethod = "getAddrModeImm12OpValue";
574 let PrintMethod = "printAddrModeImm12Operand";
575 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
577 // ldst_so_reg := reg +/- reg shop imm
579 def ldst_so_reg : Operand<i32>,
580 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
581 let EncoderMethod = "getLdStSORegOpValue";
582 // FIXME: Simplify the printer
583 let PrintMethod = "printAddrMode2Operand";
584 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
587 // addrmode2 := reg +/- imm12
588 // := reg +/- reg shop imm
590 def addrmode2 : Operand<i32>,
591 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
592 let EncoderMethod = "getAddrMode2OpValue";
593 let PrintMethod = "printAddrMode2Operand";
594 let ParserMatchClass = MemMode2AsmOperand;
595 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
598 def am2offset : Operand<i32>,
599 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
600 [], [SDNPWantRoot]> {
601 let EncoderMethod = "getAddrMode2OffsetOpValue";
602 let PrintMethod = "printAddrMode2OffsetOperand";
603 let MIOperandInfo = (ops GPR, i32imm);
606 // addrmode3 := reg +/- reg
607 // addrmode3 := reg +/- imm8
609 def addrmode3 : Operand<i32>,
610 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
611 let EncoderMethod = "getAddrMode3OpValue";
612 let PrintMethod = "printAddrMode3Operand";
613 let ParserMatchClass = MemMode3AsmOperand;
614 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
617 def am3offset : Operand<i32>,
618 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
619 [], [SDNPWantRoot]> {
620 let EncoderMethod = "getAddrMode3OffsetOpValue";
621 let PrintMethod = "printAddrMode3OffsetOperand";
622 let MIOperandInfo = (ops GPR, i32imm);
625 // ldstm_mode := {ia, ib, da, db}
627 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
628 let EncoderMethod = "getLdStmModeOpValue";
629 let PrintMethod = "printLdStmModeOperand";
632 def MemMode5AsmOperand : AsmOperandClass {
633 let Name = "MemMode5";
634 let SuperClasses = [];
637 // addrmode5 := reg +/- imm8*4
639 def addrmode5 : Operand<i32>,
640 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
641 let PrintMethod = "printAddrMode5Operand";
642 let MIOperandInfo = (ops GPR:$base, i32imm);
643 let ParserMatchClass = MemMode5AsmOperand;
644 let EncoderMethod = "getAddrMode5OpValue";
647 // addrmode6 := reg with optional alignment
649 def addrmode6 : Operand<i32>,
650 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
651 let PrintMethod = "printAddrMode6Operand";
652 let MIOperandInfo = (ops GPR:$addr, i32imm);
653 let EncoderMethod = "getAddrMode6AddressOpValue";
656 def am6offset : Operand<i32>,
657 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
658 [], [SDNPWantRoot]> {
659 let PrintMethod = "printAddrMode6OffsetOperand";
660 let MIOperandInfo = (ops GPR);
661 let EncoderMethod = "getAddrMode6OffsetOpValue";
664 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
665 // (single element from one lane) for size 32.
666 def addrmode6oneL32 : Operand<i32>,
667 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
668 let PrintMethod = "printAddrMode6Operand";
669 let MIOperandInfo = (ops GPR:$addr, i32imm);
670 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
673 // Special version of addrmode6 to handle alignment encoding for VLD-dup
674 // instructions, specifically VLD4-dup.
675 def addrmode6dup : Operand<i32>,
676 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
677 let PrintMethod = "printAddrMode6Operand";
678 let MIOperandInfo = (ops GPR:$addr, i32imm);
679 let EncoderMethod = "getAddrMode6DupAddressOpValue";
682 // addrmodepc := pc + reg
684 def addrmodepc : Operand<i32>,
685 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
686 let PrintMethod = "printAddrModePCOperand";
687 let MIOperandInfo = (ops GPR, i32imm);
690 def MemMode7AsmOperand : AsmOperandClass {
691 let Name = "MemMode7";
692 let SuperClasses = [];
696 // Used by load/store exclusive instructions. Useful to enable right assembly
697 // parsing and printing. Not used for any codegen matching.
699 def addrmode7 : Operand<i32> {
700 let PrintMethod = "printAddrMode7Operand";
701 let MIOperandInfo = (ops GPR);
702 let ParserMatchClass = MemMode7AsmOperand;
705 def nohash_imm : Operand<i32> {
706 let PrintMethod = "printNoHashImmediate";
709 def CoprocNumAsmOperand : AsmOperandClass {
710 let Name = "CoprocNum";
711 let SuperClasses = [];
712 let ParserMethod = "tryParseCoprocNumOperand";
715 def CoprocRegAsmOperand : AsmOperandClass {
716 let Name = "CoprocReg";
717 let SuperClasses = [];
718 let ParserMethod = "tryParseCoprocRegOperand";
721 def p_imm : Operand<i32> {
722 let PrintMethod = "printPImmediate";
723 let ParserMatchClass = CoprocNumAsmOperand;
726 def c_imm : Operand<i32> {
727 let PrintMethod = "printCImmediate";
728 let ParserMatchClass = CoprocRegAsmOperand;
731 //===----------------------------------------------------------------------===//
733 include "ARMInstrFormats.td"
735 //===----------------------------------------------------------------------===//
736 // Multiclass helpers...
739 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
740 /// binop that produces a value.
741 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
742 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
743 PatFrag opnode, string baseOpc, bit Commutable = 0> {
744 // The register-immediate version is re-materializable. This is useful
745 // in particular for taking the address of a local.
746 let isReMaterializable = 1 in {
747 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
748 iii, opc, "\t$Rd, $Rn, $imm",
749 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
754 let Inst{19-16} = Rn;
755 let Inst{15-12} = Rd;
756 let Inst{11-0} = imm;
759 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
760 iir, opc, "\t$Rd, $Rn, $Rm",
761 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
766 let isCommutable = Commutable;
767 let Inst{19-16} = Rn;
768 let Inst{15-12} = Rd;
769 let Inst{11-4} = 0b00000000;
773 def rsi : AsI1<opcod, (outs GPR:$Rd),
774 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegFrm,
775 iis, opc, "\t$Rd, $Rn, $shift",
776 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
781 let Inst{19-16} = Rn;
782 let Inst{15-12} = Rd;
783 let Inst{11-5} = shift{11-5};
785 let Inst{3-0} = shift{3-0};
788 def rsr : AsI1<opcod, (outs GPR:$Rd),
789 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegFrm,
790 iis, opc, "\t$Rd, $Rn, $shift",
791 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
796 let Inst{19-16} = Rn;
797 let Inst{15-12} = Rd;
798 let Inst{11-8} = shift{11-8};
800 let Inst{6-5} = shift{6-5};
802 let Inst{3-0} = shift{3-0};
805 // Assembly aliases for optional destination operand when it's the same
806 // as the source operand.
807 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
808 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
809 so_imm:$imm, pred:$p,
812 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
813 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
817 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
818 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
819 so_reg_imm:$shift, pred:$p,
822 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
823 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
824 so_reg_reg:$shift, pred:$p,
830 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
831 /// instruction modifies the CPSR register.
832 let isCodeGenOnly = 1, Defs = [CPSR] in {
833 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
834 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
835 PatFrag opnode, bit Commutable = 0> {
836 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
837 iii, opc, "\t$Rd, $Rn, $imm",
838 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
844 let Inst{19-16} = Rn;
845 let Inst{15-12} = Rd;
846 let Inst{11-0} = imm;
848 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
849 iir, opc, "\t$Rd, $Rn, $Rm",
850 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
854 let isCommutable = Commutable;
857 let Inst{19-16} = Rn;
858 let Inst{15-12} = Rd;
859 let Inst{11-4} = 0b00000000;
862 def rsi : AI1<opcod, (outs GPR:$Rd),
863 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegFrm,
864 iis, opc, "\t$Rd, $Rn, $shift",
865 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
871 let Inst{19-16} = Rn;
872 let Inst{15-12} = Rd;
873 let Inst{11-5} = shift{11-5};
875 let Inst{3-0} = shift{3-0};
878 def rsr : AI1<opcod, (outs GPR:$Rd),
879 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegFrm,
880 iis, opc, "\t$Rd, $Rn, $shift",
881 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
887 let Inst{19-16} = Rn;
888 let Inst{15-12} = Rd;
889 let Inst{11-8} = shift{11-8};
891 let Inst{6-5} = shift{6-5};
893 let Inst{3-0} = shift{3-0};
898 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
899 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
900 /// a explicit result, only implicitly set CPSR.
901 let isCompare = 1, Defs = [CPSR] in {
902 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
903 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
904 PatFrag opnode, bit Commutable = 0> {
905 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
907 [(opnode GPR:$Rn, so_imm:$imm)]> {
912 let Inst{19-16} = Rn;
913 let Inst{15-12} = 0b0000;
914 let Inst{11-0} = imm;
916 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
918 [(opnode GPR:$Rn, GPR:$Rm)]> {
921 let isCommutable = Commutable;
924 let Inst{19-16} = Rn;
925 let Inst{15-12} = 0b0000;
926 let Inst{11-4} = 0b00000000;
929 def rsi : AI1<opcod, (outs),
930 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegFrm, iis,
931 opc, "\t$Rn, $shift",
932 [(opnode GPR:$Rn, so_reg_imm:$shift)]> {
937 let Inst{19-16} = Rn;
938 let Inst{15-12} = 0b0000;
939 let Inst{11-5} = shift{11-5};
941 let Inst{3-0} = shift{3-0};
943 def rsr : AI1<opcod, (outs),
944 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegFrm, iis,
945 opc, "\t$Rn, $shift",
946 [(opnode GPR:$Rn, so_reg_reg:$shift)]> {
951 let Inst{19-16} = Rn;
952 let Inst{15-12} = 0b0000;
953 let Inst{11-8} = shift{11-8};
955 let Inst{6-5} = shift{6-5};
957 let Inst{3-0} = shift{3-0};
963 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
964 /// register and one whose operand is a register rotated by 8/16/24.
965 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
966 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
967 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
968 IIC_iEXTr, opc, "\t$Rd, $Rm",
969 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
970 Requires<[IsARM, HasV6]> {
973 let Inst{19-16} = 0b1111;
974 let Inst{15-12} = Rd;
975 let Inst{11-10} = 0b00;
978 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
979 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
980 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
981 Requires<[IsARM, HasV6]> {
985 let Inst{19-16} = 0b1111;
986 let Inst{15-12} = Rd;
987 let Inst{11-10} = rot;
992 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
993 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
994 IIC_iEXTr, opc, "\t$Rd, $Rm",
995 [/* For disassembly only; pattern left blank */]>,
996 Requires<[IsARM, HasV6]> {
997 let Inst{19-16} = 0b1111;
998 let Inst{11-10} = 0b00;
1000 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
1001 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
1002 [/* For disassembly only; pattern left blank */]>,
1003 Requires<[IsARM, HasV6]> {
1005 let Inst{19-16} = 0b1111;
1006 let Inst{11-10} = rot;
1010 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1011 /// register and one whose operand is a register rotated by 8/16/24.
1012 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
1013 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1014 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
1015 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1016 Requires<[IsARM, HasV6]> {
1020 let Inst{19-16} = Rn;
1021 let Inst{15-12} = Rd;
1022 let Inst{11-10} = 0b00;
1023 let Inst{9-4} = 0b000111;
1026 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
1028 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
1029 [(set GPR:$Rd, (opnode GPR:$Rn,
1030 (rotr GPR:$Rm, rot_imm:$rot)))]>,
1031 Requires<[IsARM, HasV6]> {
1036 let Inst{19-16} = Rn;
1037 let Inst{15-12} = Rd;
1038 let Inst{11-10} = rot;
1039 let Inst{9-4} = 0b000111;
1044 // For disassembly only.
1045 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
1046 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1047 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
1048 [/* For disassembly only; pattern left blank */]>,
1049 Requires<[IsARM, HasV6]> {
1050 let Inst{11-10} = 0b00;
1052 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
1054 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
1055 [/* For disassembly only; pattern left blank */]>,
1056 Requires<[IsARM, HasV6]> {
1059 let Inst{19-16} = Rn;
1060 let Inst{11-10} = rot;
1064 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1065 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1066 string baseOpc, bit Commutable = 0> {
1067 let Uses = [CPSR] in {
1068 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1069 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1070 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
1076 let Inst{15-12} = Rd;
1077 let Inst{19-16} = Rn;
1078 let Inst{11-0} = imm;
1080 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1081 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1082 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1087 let Inst{11-4} = 0b00000000;
1089 let isCommutable = Commutable;
1091 let Inst{15-12} = Rd;
1092 let Inst{19-16} = Rn;
1094 def rsi : AsI1<opcod, (outs GPR:$Rd),
1095 (ins GPR:$Rn, so_reg_imm:$shift),
1096 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1097 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1103 let Inst{19-16} = Rn;
1104 let Inst{15-12} = Rd;
1105 let Inst{11-5} = shift{11-5};
1107 let Inst{3-0} = shift{3-0};
1109 def rsr : AsI1<opcod, (outs GPR:$Rd),
1110 (ins GPR:$Rn, so_reg_reg:$shift),
1111 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1112 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1118 let Inst{19-16} = Rn;
1119 let Inst{15-12} = Rd;
1120 let Inst{11-8} = shift{11-8};
1122 let Inst{6-5} = shift{6-5};
1124 let Inst{3-0} = shift{3-0};
1127 // Assembly aliases for optional destination operand when it's the same
1128 // as the source operand.
1129 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1130 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1131 so_imm:$imm, pred:$p,
1134 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1135 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1139 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1140 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1141 so_reg_imm:$shift, pred:$p,
1144 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1145 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1146 so_reg_reg:$shift, pred:$p,
1151 // Carry setting variants
1152 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
1153 let usesCustomInserter = 1 in {
1154 multiclass AI1_adde_sube_s_irs<PatFrag opnode, bit Commutable = 0> {
1155 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1157 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>;
1158 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1160 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
1161 let isCommutable = Commutable;
1163 def rsi : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1165 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>;
1166 def rsr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1168 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>;
1172 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1173 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1174 InstrItinClass iir, PatFrag opnode> {
1175 // Note: We use the complex addrmode_imm12 rather than just an input
1176 // GPR and a constrained immediate so that we can use this to match
1177 // frame index references and avoid matching constant pool references.
1178 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1179 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1180 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1183 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1184 let Inst{19-16} = addr{16-13}; // Rn
1185 let Inst{15-12} = Rt;
1186 let Inst{11-0} = addr{11-0}; // imm12
1188 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1189 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1190 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1193 let shift{4} = 0; // Inst{4} = 0
1194 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1195 let Inst{19-16} = shift{16-13}; // Rn
1196 let Inst{15-12} = Rt;
1197 let Inst{11-0} = shift{11-0};
1202 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1203 InstrItinClass iir, PatFrag opnode> {
1204 // Note: We use the complex addrmode_imm12 rather than just an input
1205 // GPR and a constrained immediate so that we can use this to match
1206 // frame index references and avoid matching constant pool references.
1207 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1208 (ins GPR:$Rt, addrmode_imm12:$addr),
1209 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1210 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1213 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1214 let Inst{19-16} = addr{16-13}; // Rn
1215 let Inst{15-12} = Rt;
1216 let Inst{11-0} = addr{11-0}; // imm12
1218 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1219 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1220 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1223 let shift{4} = 0; // Inst{4} = 0
1224 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1225 let Inst{19-16} = shift{16-13}; // Rn
1226 let Inst{15-12} = Rt;
1227 let Inst{11-0} = shift{11-0};
1230 //===----------------------------------------------------------------------===//
1232 //===----------------------------------------------------------------------===//
1234 //===----------------------------------------------------------------------===//
1235 // Miscellaneous Instructions.
1238 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1239 /// the function. The first operand is the ID# for this instruction, the second
1240 /// is the index into the MachineConstantPool that this is, the third is the
1241 /// size in bytes of this constant pool entry.
1242 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1243 def CONSTPOOL_ENTRY :
1244 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1245 i32imm:$size), NoItinerary, []>;
1247 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1248 // from removing one half of the matched pairs. That breaks PEI, which assumes
1249 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1250 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1251 def ADJCALLSTACKUP :
1252 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1253 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1255 def ADJCALLSTACKDOWN :
1256 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1257 [(ARMcallseq_start timm:$amt)]>;
1260 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
1261 [/* For disassembly only; pattern left blank */]>,
1262 Requires<[IsARM, HasV6T2]> {
1263 let Inst{27-16} = 0b001100100000;
1264 let Inst{15-8} = 0b11110000;
1265 let Inst{7-0} = 0b00000000;
1268 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
1269 [/* For disassembly only; pattern left blank */]>,
1270 Requires<[IsARM, HasV6T2]> {
1271 let Inst{27-16} = 0b001100100000;
1272 let Inst{15-8} = 0b11110000;
1273 let Inst{7-0} = 0b00000001;
1276 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
1277 [/* For disassembly only; pattern left blank */]>,
1278 Requires<[IsARM, HasV6T2]> {
1279 let Inst{27-16} = 0b001100100000;
1280 let Inst{15-8} = 0b11110000;
1281 let Inst{7-0} = 0b00000010;
1284 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
1285 [/* For disassembly only; pattern left blank */]>,
1286 Requires<[IsARM, HasV6T2]> {
1287 let Inst{27-16} = 0b001100100000;
1288 let Inst{15-8} = 0b11110000;
1289 let Inst{7-0} = 0b00000011;
1292 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
1294 [/* For disassembly only; pattern left blank */]>,
1295 Requires<[IsARM, HasV6]> {
1300 let Inst{15-12} = Rd;
1301 let Inst{19-16} = Rn;
1302 let Inst{27-20} = 0b01101000;
1303 let Inst{7-4} = 0b1011;
1304 let Inst{11-8} = 0b1111;
1307 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1308 [/* For disassembly only; pattern left blank */]>,
1309 Requires<[IsARM, HasV6T2]> {
1310 let Inst{27-16} = 0b001100100000;
1311 let Inst{15-8} = 0b11110000;
1312 let Inst{7-0} = 0b00000100;
1315 // The i32imm operand $val can be used by a debugger to store more information
1316 // about the breakpoint.
1317 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1318 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1320 let Inst{3-0} = val{3-0};
1321 let Inst{19-8} = val{15-4};
1322 let Inst{27-20} = 0b00010010;
1323 let Inst{7-4} = 0b0111;
1326 // Change Processor State is a system instruction -- for disassembly and
1328 // FIXME: Since the asm parser has currently no clean way to handle optional
1329 // operands, create 3 versions of the same instruction. Once there's a clean
1330 // framework to represent optional operands, change this behavior.
1331 class CPS<dag iops, string asm_ops>
1332 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1333 [/* For disassembly only; pattern left blank */]>, Requires<[IsARM]> {
1339 let Inst{31-28} = 0b1111;
1340 let Inst{27-20} = 0b00010000;
1341 let Inst{19-18} = imod;
1342 let Inst{17} = M; // Enabled if mode is set;
1344 let Inst{8-6} = iflags;
1346 let Inst{4-0} = mode;
1350 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
1351 "$imod\t$iflags, $mode">;
1352 let mode = 0, M = 0 in
1353 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1355 let imod = 0, iflags = 0, M = 1 in
1356 def CPS1p : CPS<(ins i32imm:$mode), "\t$mode">;
1358 // Preload signals the memory system of possible future data/instruction access.
1359 // These are for disassembly only.
1360 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1362 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1363 !strconcat(opc, "\t$addr"),
1364 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1367 let Inst{31-26} = 0b111101;
1368 let Inst{25} = 0; // 0 for immediate form
1369 let Inst{24} = data;
1370 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1371 let Inst{22} = read;
1372 let Inst{21-20} = 0b01;
1373 let Inst{19-16} = addr{16-13}; // Rn
1374 let Inst{15-12} = 0b1111;
1375 let Inst{11-0} = addr{11-0}; // imm12
1378 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1379 !strconcat(opc, "\t$shift"),
1380 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1382 let Inst{31-26} = 0b111101;
1383 let Inst{25} = 1; // 1 for register form
1384 let Inst{24} = data;
1385 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1386 let Inst{22} = read;
1387 let Inst{21-20} = 0b01;
1388 let Inst{19-16} = shift{16-13}; // Rn
1389 let Inst{15-12} = 0b1111;
1390 let Inst{11-0} = shift{11-0};
1394 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1395 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1396 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1398 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1400 [/* For disassembly only; pattern left blank */]>,
1403 let Inst{31-10} = 0b1111000100000001000000;
1408 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1409 []>, Requires<[IsARM, HasV7]> {
1411 let Inst{27-4} = 0b001100100000111100001111;
1412 let Inst{3-0} = opt;
1415 // A5.4 Permanently UNDEFINED instructions.
1416 let isBarrier = 1, isTerminator = 1 in
1417 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1420 let Inst = 0xe7ffdefe;
1423 // Address computation and loads and stores in PIC mode.
1424 let isNotDuplicable = 1 in {
1425 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1427 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1429 let AddedComplexity = 10 in {
1430 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1432 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1434 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1436 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1438 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1440 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1442 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1444 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1446 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1448 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1450 let AddedComplexity = 10 in {
1451 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1452 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1454 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1455 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1456 addrmodepc:$addr)]>;
1458 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1459 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1461 } // isNotDuplicable = 1
1464 // LEApcrel - Load a pc-relative address into a register without offending the
1466 let neverHasSideEffects = 1, isReMaterializable = 1 in
1467 // The 'adr' mnemonic encodes differently if the label is before or after
1468 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1469 // know until then which form of the instruction will be used.
1470 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1471 MiscFrm, IIC_iALUi, "adr", "\t$Rd, #$label", []> {
1474 let Inst{27-25} = 0b001;
1476 let Inst{19-16} = 0b1111;
1477 let Inst{15-12} = Rd;
1478 let Inst{11-0} = label;
1480 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1483 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1484 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1487 //===----------------------------------------------------------------------===//
1488 // Control Flow Instructions.
1491 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1493 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1494 "bx", "\tlr", [(ARMretflag)]>,
1495 Requires<[IsARM, HasV4T]> {
1496 let Inst{27-0} = 0b0001001011111111111100011110;
1500 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1501 "mov", "\tpc, lr", [(ARMretflag)]>,
1502 Requires<[IsARM, NoV4T]> {
1503 let Inst{27-0} = 0b0001101000001111000000001110;
1507 // Indirect branches
1508 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1510 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1511 [(brind GPR:$dst)]>,
1512 Requires<[IsARM, HasV4T]> {
1514 let Inst{31-4} = 0b1110000100101111111111110001;
1515 let Inst{3-0} = dst;
1518 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1519 "bx", "\t$dst", [/* pattern left blank */]>,
1520 Requires<[IsARM, HasV4T]> {
1522 let Inst{27-4} = 0b000100101111111111110001;
1523 let Inst{3-0} = dst;
1527 // All calls clobber the non-callee saved registers. SP is marked as
1528 // a use to prevent stack-pointer assignments that appear immediately
1529 // before calls from potentially appearing dead.
1531 // On non-Darwin platforms R9 is callee-saved.
1532 // FIXME: Do we really need a non-predicated version? If so, it should
1533 // at least be a pseudo instruction expanding to the predicated version
1534 // at MC lowering time.
1535 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1537 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1538 IIC_Br, "bl\t$func",
1539 [(ARMcall tglobaladdr:$func)]>,
1540 Requires<[IsARM, IsNotDarwin]> {
1541 let Inst{31-28} = 0b1110;
1543 let Inst{23-0} = func;
1546 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1547 IIC_Br, "bl", "\t$func",
1548 [(ARMcall_pred tglobaladdr:$func)]>,
1549 Requires<[IsARM, IsNotDarwin]> {
1551 let Inst{23-0} = func;
1555 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1556 IIC_Br, "blx\t$func",
1557 [(ARMcall GPR:$func)]>,
1558 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1560 let Inst{31-4} = 0b1110000100101111111111110011;
1561 let Inst{3-0} = func;
1564 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1565 IIC_Br, "blx", "\t$func",
1566 [(ARMcall_pred GPR:$func)]>,
1567 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1569 let Inst{27-4} = 0b000100101111111111110011;
1570 let Inst{3-0} = func;
1574 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1575 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1576 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1577 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1580 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1581 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1582 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1586 // On Darwin R9 is call-clobbered.
1587 // R7 is marked as a use to prevent frame-pointer assignments from being
1588 // moved above / below calls.
1589 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1590 Uses = [R7, SP] in {
1591 def BLr9 : ARMPseudoExpand<(outs), (ins bl_target:$func, variable_ops),
1593 [(ARMcall tglobaladdr:$func)], (BL bl_target:$func)>,
1594 Requires<[IsARM, IsDarwin]>;
1596 def BLr9_pred : ARMPseudoExpand<(outs),
1597 (ins bl_target:$func, pred:$p, variable_ops),
1599 [(ARMcall_pred tglobaladdr:$func)],
1600 (BL_pred bl_target:$func, pred:$p)>,
1601 Requires<[IsARM, IsDarwin]>;
1604 def BLXr9 : ARMPseudoExpand<(outs), (ins GPR:$func, variable_ops),
1606 [(ARMcall GPR:$func)],
1608 Requires<[IsARM, HasV5T, IsDarwin]>;
1610 def BLXr9_pred: ARMPseudoExpand<(outs), (ins GPR:$func, pred:$p,variable_ops),
1612 [(ARMcall_pred GPR:$func)],
1613 (BLX_pred GPR:$func, pred:$p)>,
1614 Requires<[IsARM, HasV5T, IsDarwin]>;
1617 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1618 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1619 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1620 Requires<[IsARM, HasV4T, IsDarwin]>;
1623 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1624 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1625 Requires<[IsARM, NoV4T, IsDarwin]>;
1628 let isBranch = 1, isTerminator = 1 in {
1629 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1630 // a two-value operand where a dag node expects two operands. :(
1631 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1632 IIC_Br, "b", "\t$target",
1633 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1635 let Inst{23-0} = target;
1638 let isBarrier = 1 in {
1639 // B is "predicable" since it's just a Bcc with an 'always' condition.
1640 let isPredicable = 1 in
1641 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1642 // should be sufficient.
1643 // FIXME: Is B really a Barrier? That doesn't seem right.
1644 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
1645 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
1647 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1648 def BR_JTr : ARMPseudoInst<(outs),
1649 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1651 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1652 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1653 // into i12 and rs suffixed versions.
1654 def BR_JTm : ARMPseudoInst<(outs),
1655 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1657 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1659 def BR_JTadd : ARMPseudoInst<(outs),
1660 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1662 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1664 } // isNotDuplicable = 1, isIndirectBranch = 1
1669 // BLX (immediate) -- for disassembly only
1670 def BLXi : AXI<(outs), (ins br_target:$target), BrMiscFrm, NoItinerary,
1671 "blx\t$target", [/* pattern left blank */]>,
1672 Requires<[IsARM, HasV5T]> {
1673 let Inst{31-25} = 0b1111101;
1675 let Inst{23-0} = target{24-1};
1676 let Inst{24} = target{0};
1679 // Branch and Exchange Jazelle
1680 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1681 [/* pattern left blank */]> {
1683 let Inst{23-20} = 0b0010;
1684 let Inst{19-8} = 0xfff;
1685 let Inst{7-4} = 0b0010;
1686 let Inst{3-0} = func;
1691 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1693 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
1695 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1696 IIC_Br, []>, Requires<[IsDarwin]>;
1698 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1699 IIC_Br, []>, Requires<[IsDarwin]>;
1701 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst, variable_ops),
1703 (Bcc br_target:$dst, (ops 14, zero_reg))>,
1704 Requires<[IsARM, IsDarwin]>;
1706 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
1709 Requires<[IsARM, IsDarwin]>;
1713 // Non-Darwin versions (the difference is R9).
1714 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
1716 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1717 IIC_Br, []>, Requires<[IsNotDarwin]>;
1719 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1720 IIC_Br, []>, Requires<[IsNotDarwin]>;
1722 def TAILJMPdND : ARMPseudoExpand<(outs), (ins brtarget:$dst, variable_ops),
1724 (Bcc br_target:$dst, (ops 14, zero_reg))>,
1725 Requires<[IsARM, IsNotDarwin]>;
1727 def TAILJMPrND : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
1730 Requires<[IsARM, IsNotDarwin]>;
1738 // Secure Monitor Call is a system instruction -- for disassembly only
1739 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1740 [/* For disassembly only; pattern left blank */]> {
1742 let Inst{23-4} = 0b01100000000000000111;
1743 let Inst{3-0} = opt;
1746 // Supervisor Call (Software Interrupt) -- for disassembly only
1747 let isCall = 1, Uses = [SP] in {
1748 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1749 [/* For disassembly only; pattern left blank */]> {
1751 let Inst{23-0} = svc;
1755 // Store Return State is a system instruction -- for disassembly only
1756 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1757 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1758 NoItinerary, "srs${amode}\tsp!, $mode",
1759 [/* For disassembly only; pattern left blank */]> {
1760 let Inst{31-28} = 0b1111;
1761 let Inst{22-20} = 0b110; // W = 1
1762 let Inst{19-8} = 0xd05;
1763 let Inst{7-5} = 0b000;
1766 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1767 NoItinerary, "srs${amode}\tsp, $mode",
1768 [/* For disassembly only; pattern left blank */]> {
1769 let Inst{31-28} = 0b1111;
1770 let Inst{22-20} = 0b100; // W = 0
1771 let Inst{19-8} = 0xd05;
1772 let Inst{7-5} = 0b000;
1775 // Return From Exception is a system instruction -- for disassembly only
1776 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1777 NoItinerary, "rfe${amode}\t$base!",
1778 [/* For disassembly only; pattern left blank */]> {
1779 let Inst{31-28} = 0b1111;
1780 let Inst{22-20} = 0b011; // W = 1
1781 let Inst{15-0} = 0x0a00;
1784 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1785 NoItinerary, "rfe${amode}\t$base",
1786 [/* For disassembly only; pattern left blank */]> {
1787 let Inst{31-28} = 0b1111;
1788 let Inst{22-20} = 0b001; // W = 0
1789 let Inst{15-0} = 0x0a00;
1791 } // isCodeGenOnly = 1
1793 //===----------------------------------------------------------------------===//
1794 // Load / store Instructions.
1800 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1801 UnOpFrag<(load node:$Src)>>;
1802 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1803 UnOpFrag<(zextloadi8 node:$Src)>>;
1804 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1805 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1806 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1807 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1809 // Special LDR for loads from non-pc-relative constpools.
1810 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1811 isReMaterializable = 1 in
1812 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1813 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
1817 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1818 let Inst{19-16} = 0b1111;
1819 let Inst{15-12} = Rt;
1820 let Inst{11-0} = addr{11-0}; // imm12
1823 // Loads with zero extension
1824 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1825 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
1826 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
1828 // Loads with sign extension
1829 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1830 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
1831 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
1833 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1834 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
1835 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
1837 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1839 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
1840 (ins addrmode3:$addr), LdMiscFrm,
1841 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
1842 []>, Requires<[IsARM, HasV5TE]>;
1846 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
1847 def _PRE : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1848 (ins addrmode2:$addr), IndexModePre, LdFrm, itin,
1849 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1851 // {13} 1 == Rm, 0 == imm12
1855 let Inst{25} = addr{13};
1856 let Inst{23} = addr{12};
1857 let Inst{19-16} = addr{17-14};
1858 let Inst{11-0} = addr{11-0};
1859 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1861 def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1862 (ins GPR:$Rn, am2offset:$offset),
1863 IndexModePost, LdFrm, itin,
1864 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1865 // {13} 1 == Rm, 0 == imm12
1870 let Inst{25} = offset{13};
1871 let Inst{23} = offset{12};
1872 let Inst{19-16} = Rn;
1873 let Inst{11-0} = offset{11-0};
1877 let mayLoad = 1, neverHasSideEffects = 1 in {
1878 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
1879 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
1882 multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
1883 def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1884 (ins addrmode3:$addr), IndexModePre,
1886 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1888 let Inst{23} = addr{8}; // U bit
1889 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1890 let Inst{19-16} = addr{12-9}; // Rn
1891 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1892 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1894 def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1895 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1897 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1900 let Inst{23} = offset{8}; // U bit
1901 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1902 let Inst{19-16} = Rn;
1903 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1904 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1908 let mayLoad = 1, neverHasSideEffects = 1 in {
1909 defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
1910 defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
1911 defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
1912 let hasExtraDefRegAllocReq = 1 in {
1913 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
1914 (ins addrmode3:$addr), IndexModePre,
1915 LdMiscFrm, IIC_iLoad_d_ru,
1916 "ldrd", "\t$Rt, $Rt2, $addr!",
1917 "$addr.base = $Rn_wb", []> {
1919 let Inst{23} = addr{8}; // U bit
1920 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1921 let Inst{19-16} = addr{12-9}; // Rn
1922 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1923 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1925 def LDRD_POST: AI3ldstidx<0b1101, 0, 1, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
1926 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1927 LdMiscFrm, IIC_iLoad_d_ru,
1928 "ldrd", "\t$Rt, $Rt2, [$Rn], $offset",
1929 "$Rn = $Rn_wb", []> {
1932 let Inst{23} = offset{8}; // U bit
1933 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1934 let Inst{19-16} = Rn;
1935 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1936 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1938 } // hasExtraDefRegAllocReq = 1
1939 } // mayLoad = 1, neverHasSideEffects = 1
1941 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1942 let mayLoad = 1, neverHasSideEffects = 1 in {
1943 def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$base_wb),
1944 (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_ru,
1945 "ldrt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1947 // {13} 1 == Rm, 0 == imm12
1951 let Inst{25} = addr{13};
1952 let Inst{23} = addr{12};
1953 let Inst{21} = 1; // overwrite
1954 let Inst{19-16} = addr{17-14};
1955 let Inst{11-0} = addr{11-0};
1956 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1958 def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1959 (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_bh_ru,
1960 "ldrbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1962 // {13} 1 == Rm, 0 == imm12
1966 let Inst{25} = addr{13};
1967 let Inst{23} = addr{12};
1968 let Inst{21} = 1; // overwrite
1969 let Inst{19-16} = addr{17-14};
1970 let Inst{11-0} = addr{11-0};
1971 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1973 def LDRSBT : AI3ldstidxT<0b1101, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1974 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1975 "ldrsbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1976 let Inst{21} = 1; // overwrite
1978 def LDRHT : AI3ldstidxT<0b1011, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1979 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1980 "ldrht", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1981 let Inst{21} = 1; // overwrite
1983 def LDRSHT : AI3ldstidxT<0b1111, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1984 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1985 "ldrsht", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1986 let Inst{21} = 1; // overwrite
1992 // Stores with truncate
1993 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
1994 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
1995 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
1998 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1999 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2000 StMiscFrm, IIC_iStore_d_r,
2001 "strd", "\t$Rt, $src2, $addr", []>, Requires<[IsARM, HasV5TE]>;
2004 def STR_PRE : AI2stridx<0, 1, (outs GPR:$Rn_wb),
2005 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
2006 IndexModePre, StFrm, IIC_iStore_ru,
2007 "str", "\t$Rt, [$Rn, $offset]!",
2008 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
2010 (pre_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
2012 def STR_POST : AI2stridx<0, 0, (outs GPR:$Rn_wb),
2013 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
2014 IndexModePost, StFrm, IIC_iStore_ru,
2015 "str", "\t$Rt, [$Rn], $offset",
2016 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
2018 (post_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
2020 def STRB_PRE : AI2stridx<1, 1, (outs GPR:$Rn_wb),
2021 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
2022 IndexModePre, StFrm, IIC_iStore_bh_ru,
2023 "strb", "\t$Rt, [$Rn, $offset]!",
2024 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
2025 [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
2026 GPR:$Rn, am2offset:$offset))]>;
2027 def STRB_POST: AI2stridx<1, 0, (outs GPR:$Rn_wb),
2028 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
2029 IndexModePost, StFrm, IIC_iStore_bh_ru,
2030 "strb", "\t$Rt, [$Rn], $offset",
2031 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
2032 [(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
2033 GPR:$Rn, am2offset:$offset))]>;
2035 def STRH_PRE : AI3stridx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2036 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
2037 IndexModePre, StMiscFrm, IIC_iStore_ru,
2038 "strh", "\t$Rt, [$Rn, $offset]!",
2039 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
2041 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2043 def STRH_POST: AI3stridx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2044 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
2045 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2046 "strh", "\t$Rt, [$Rn], $offset",
2047 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
2048 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2049 GPR:$Rn, am3offset:$offset))]>;
2051 // For disassembly only
2052 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2053 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
2054 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
2055 StMiscFrm, IIC_iStore_d_ru,
2056 "strd", "\t$src1, $src2, [$base, $offset]!",
2057 "$base = $base_wb", []>;
2059 // For disassembly only
2060 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
2061 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
2062 StMiscFrm, IIC_iStore_d_ru,
2063 "strd", "\t$src1, $src2, [$base], $offset",
2064 "$base = $base_wb", []>;
2065 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2067 // STRT, STRBT, and STRHT are for disassembly only.
2069 def STRT : AI2stridxT<0, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
2070 IndexModePost, StFrm, IIC_iStore_ru,
2071 "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
2072 [/* For disassembly only; pattern left blank */]> {
2073 let Inst{21} = 1; // overwrite
2074 let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
2077 def STRBT : AI2stridxT<1, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
2078 IndexModePost, StFrm, IIC_iStore_bh_ru,
2079 "strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
2080 [/* For disassembly only; pattern left blank */]> {
2081 let Inst{21} = 1; // overwrite
2082 let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
2085 def STRHT: AI3sthpo<(outs GPR:$base_wb), (ins GPR:$Rt, addrmode3:$addr),
2086 StMiscFrm, IIC_iStore_bh_ru,
2087 "strht", "\t$Rt, $addr", "$addr.base = $base_wb",
2088 [/* For disassembly only; pattern left blank */]> {
2089 let Inst{21} = 1; // overwrite
2090 let AsmMatchConverter = "CvtStWriteBackRegAddrMode3";
2093 //===----------------------------------------------------------------------===//
2094 // Load / store multiple Instructions.
2097 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
2098 InstrItinClass itin, InstrItinClass itin_upd> {
2099 // IA is the default, so no need for an explicit suffix on the
2100 // mnemonic here. Without it is the cannonical spelling.
2102 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2103 IndexModeNone, f, itin,
2104 !strconcat(asm, "${p}\t$Rn, $regs"), "", []> {
2105 let Inst{24-23} = 0b01; // Increment After
2106 let Inst{21} = 0; // No writeback
2107 let Inst{20} = L_bit;
2110 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2111 IndexModeUpd, f, itin_upd,
2112 !strconcat(asm, "${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2113 let Inst{24-23} = 0b01; // Increment After
2114 let Inst{21} = 1; // Writeback
2115 let Inst{20} = L_bit;
2118 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2119 IndexModeNone, f, itin,
2120 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
2121 let Inst{24-23} = 0b00; // Decrement After
2122 let Inst{21} = 0; // No writeback
2123 let Inst{20} = L_bit;
2126 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2127 IndexModeUpd, f, itin_upd,
2128 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2129 let Inst{24-23} = 0b00; // Decrement After
2130 let Inst{21} = 1; // Writeback
2131 let Inst{20} = L_bit;
2134 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2135 IndexModeNone, f, itin,
2136 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
2137 let Inst{24-23} = 0b10; // Decrement Before
2138 let Inst{21} = 0; // No writeback
2139 let Inst{20} = L_bit;
2142 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2143 IndexModeUpd, f, itin_upd,
2144 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2145 let Inst{24-23} = 0b10; // Decrement Before
2146 let Inst{21} = 1; // Writeback
2147 let Inst{20} = L_bit;
2150 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2151 IndexModeNone, f, itin,
2152 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
2153 let Inst{24-23} = 0b11; // Increment Before
2154 let Inst{21} = 0; // No writeback
2155 let Inst{20} = L_bit;
2158 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2159 IndexModeUpd, f, itin_upd,
2160 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2161 let Inst{24-23} = 0b11; // Increment Before
2162 let Inst{21} = 1; // Writeback
2163 let Inst{20} = L_bit;
2167 let neverHasSideEffects = 1 in {
2169 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2170 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
2172 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2173 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
2175 } // neverHasSideEffects
2177 // FIXME: remove when we have a way to marking a MI with these properties.
2178 // FIXME: Should pc be an implicit operand like PICADD, etc?
2179 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2180 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2181 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2182 reglist:$regs, variable_ops),
2183 4, IIC_iLoad_mBr, [],
2184 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2185 RegConstraint<"$Rn = $wb">;
2187 //===----------------------------------------------------------------------===//
2188 // Move Instructions.
2191 let neverHasSideEffects = 1 in
2192 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2193 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2197 let Inst{19-16} = 0b0000;
2198 let Inst{11-4} = 0b00000000;
2201 let Inst{15-12} = Rd;
2204 // A version for the smaller set of tail call registers.
2205 let neverHasSideEffects = 1 in
2206 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2207 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2211 let Inst{11-4} = 0b00000000;
2214 let Inst{15-12} = Rd;
2217 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
2218 DPSoRegFrm, IIC_iMOVsr,
2219 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
2223 let Inst{15-12} = Rd;
2224 let Inst{19-16} = 0b0000;
2225 let Inst{11-0} = src;
2229 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2230 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2231 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2235 let Inst{15-12} = Rd;
2236 let Inst{19-16} = 0b0000;
2237 let Inst{11-0} = imm;
2240 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2241 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
2243 "movw", "\t$Rd, $imm",
2244 [(set GPR:$Rd, imm0_65535:$imm)]>,
2245 Requires<[IsARM, HasV6T2]>, UnaryDP {
2248 let Inst{15-12} = Rd;
2249 let Inst{11-0} = imm{11-0};
2250 let Inst{19-16} = imm{15-12};
2255 def : InstAlias<"mov${p} $Rd, $imm",
2256 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
2259 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2260 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2262 let Constraints = "$src = $Rd" in {
2263 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, imm0_65535_expr:$imm),
2265 "movt", "\t$Rd, $imm",
2267 (or (and GPR:$src, 0xffff),
2268 lo16AllZero:$imm))]>, UnaryDP,
2269 Requires<[IsARM, HasV6T2]> {
2272 let Inst{15-12} = Rd;
2273 let Inst{11-0} = imm{11-0};
2274 let Inst{19-16} = imm{15-12};
2279 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2280 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2284 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2285 Requires<[IsARM, HasV6T2]>;
2287 let Uses = [CPSR] in
2288 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2289 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2292 // These aren't really mov instructions, but we have to define them this way
2293 // due to flag operands.
2295 let Defs = [CPSR] in {
2296 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2297 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2299 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2300 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2304 //===----------------------------------------------------------------------===//
2305 // Extend Instructions.
2310 defm SXTB : AI_ext_rrot<0b01101010,
2311 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2312 defm SXTH : AI_ext_rrot<0b01101011,
2313 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2315 defm SXTAB : AI_exta_rrot<0b01101010,
2316 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2317 defm SXTAH : AI_exta_rrot<0b01101011,
2318 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2320 // For disassembly only
2321 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2323 // For disassembly only
2324 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2328 let AddedComplexity = 16 in {
2329 defm UXTB : AI_ext_rrot<0b01101110,
2330 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2331 defm UXTH : AI_ext_rrot<0b01101111,
2332 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2333 defm UXTB16 : AI_ext_rrot<0b01101100,
2334 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2336 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2337 // The transformation should probably be done as a combiner action
2338 // instead so we can include a check for masking back in the upper
2339 // eight bits of the source into the lower eight bits of the result.
2340 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2341 // (UXTB16r_rot GPR:$Src, 24)>;
2342 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2343 (UXTB16r_rot GPR:$Src, 8)>;
2345 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2346 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2347 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2348 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2351 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2352 // For disassembly only
2353 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2356 def SBFX : I<(outs GPR:$Rd),
2357 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2358 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
2359 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2360 Requires<[IsARM, HasV6T2]> {
2365 let Inst{27-21} = 0b0111101;
2366 let Inst{6-4} = 0b101;
2367 let Inst{20-16} = width;
2368 let Inst{15-12} = Rd;
2369 let Inst{11-7} = lsb;
2373 def UBFX : I<(outs GPR:$Rd),
2374 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2375 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
2376 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2377 Requires<[IsARM, HasV6T2]> {
2382 let Inst{27-21} = 0b0111111;
2383 let Inst{6-4} = 0b101;
2384 let Inst{20-16} = width;
2385 let Inst{15-12} = Rd;
2386 let Inst{11-7} = lsb;
2390 //===----------------------------------------------------------------------===//
2391 // Arithmetic Instructions.
2394 defm ADD : AsI1_bin_irs<0b0100, "add",
2395 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2396 BinOpFrag<(add node:$LHS, node:$RHS)>, "ADD", 1>;
2397 defm SUB : AsI1_bin_irs<0b0010, "sub",
2398 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2399 BinOpFrag<(sub node:$LHS, node:$RHS)>, "SUB">;
2401 // ADD and SUB with 's' bit set.
2402 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
2403 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2404 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
2405 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
2406 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2407 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
2409 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
2410 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>,
2412 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
2413 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>,
2416 // ADC and SUBC with 's' bit set.
2417 let usesCustomInserter = 1 in {
2418 defm ADCS : AI1_adde_sube_s_irs<
2419 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
2420 defm SBCS : AI1_adde_sube_s_irs<
2421 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
2424 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2425 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
2426 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
2431 let Inst{15-12} = Rd;
2432 let Inst{19-16} = Rn;
2433 let Inst{11-0} = imm;
2436 // The reg/reg form is only defined for the disassembler; for codegen it is
2437 // equivalent to SUBrr.
2438 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2439 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
2440 [/* For disassembly only; pattern left blank */]> {
2444 let Inst{11-4} = 0b00000000;
2447 let Inst{15-12} = Rd;
2448 let Inst{19-16} = Rn;
2451 def RSBrsi : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
2452 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2453 [(set GPR:$Rd, (sub so_reg_imm:$shift, GPR:$Rn))]> {
2458 let Inst{19-16} = Rn;
2459 let Inst{15-12} = Rd;
2460 let Inst{11-5} = shift{11-5};
2462 let Inst{3-0} = shift{3-0};
2465 def RSBrsr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
2466 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2467 [(set GPR:$Rd, (sub so_reg_reg:$shift, GPR:$Rn))]> {
2472 let Inst{19-16} = Rn;
2473 let Inst{15-12} = Rd;
2474 let Inst{11-8} = shift{11-8};
2476 let Inst{6-5} = shift{6-5};
2478 let Inst{3-0} = shift{3-0};
2481 // RSB with 's' bit set.
2482 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
2483 let usesCustomInserter = 1 in {
2484 def RSBSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2486 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]>;
2487 def RSBSrr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2489 [/* For disassembly only; pattern left blank */]>;
2490 def RSBSrsi : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
2492 [(set GPR:$Rd, (subc so_reg_imm:$shift, GPR:$Rn))]>;
2493 def RSBSrsr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
2495 [(set GPR:$Rd, (subc so_reg_reg:$shift, GPR:$Rn))]>;
2498 let Uses = [CPSR] in {
2499 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2500 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2501 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2507 let Inst{15-12} = Rd;
2508 let Inst{19-16} = Rn;
2509 let Inst{11-0} = imm;
2511 // The reg/reg form is only defined for the disassembler; for codegen it is
2512 // equivalent to SUBrr.
2513 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2514 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2515 [/* For disassembly only; pattern left blank */]> {
2519 let Inst{11-4} = 0b00000000;
2522 let Inst{15-12} = Rd;
2523 let Inst{19-16} = Rn;
2525 def RSCrsi : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
2526 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2527 [(set GPR:$Rd, (sube_dead_carry so_reg_imm:$shift, GPR:$Rn))]>,
2533 let Inst{19-16} = Rn;
2534 let Inst{15-12} = Rd;
2535 let Inst{11-5} = shift{11-5};
2537 let Inst{3-0} = shift{3-0};
2539 def RSCrsr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
2540 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2541 [(set GPR:$Rd, (sube_dead_carry so_reg_reg:$shift, GPR:$Rn))]>,
2547 let Inst{19-16} = Rn;
2548 let Inst{15-12} = Rd;
2549 let Inst{11-8} = shift{11-8};
2551 let Inst{6-5} = shift{6-5};
2553 let Inst{3-0} = shift{3-0};
2558 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
2559 let usesCustomInserter = 1, Uses = [CPSR] in {
2560 def RSCSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2562 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>;
2563 def RSCSrsi : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
2565 [(set GPR:$Rd, (sube_dead_carry so_reg_imm:$shift, GPR:$Rn))]>;
2566 def RSCSrsr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
2568 [(set GPR:$Rd, (sube_dead_carry so_reg_reg:$shift, GPR:$Rn))]>;
2571 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2572 // The assume-no-carry-in form uses the negation of the input since add/sub
2573 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2574 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2576 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2577 (SUBri GPR:$src, so_imm_neg:$imm)>;
2578 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2579 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2580 // The with-carry-in form matches bitwise not instead of the negation.
2581 // Effectively, the inverse interpretation of the carry flag already accounts
2582 // for part of the negation.
2583 def : ARMPat<(adde_dead_carry GPR:$src, so_imm_not:$imm),
2584 (SBCri GPR:$src, so_imm_not:$imm)>;
2585 def : ARMPat<(adde_live_carry GPR:$src, so_imm_not:$imm),
2586 (SBCSri GPR:$src, so_imm_not:$imm)>;
2588 // Note: These are implemented in C++ code, because they have to generate
2589 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2591 // (mul X, 2^n+1) -> (add (X << n), X)
2592 // (mul X, 2^n-1) -> (rsb X, (X << n))
2594 // ARM Arithmetic Instruction -- for disassembly only
2595 // GPR:$dst = GPR:$a op GPR:$b
2596 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2597 list<dag> pattern = [/* For disassembly only; pattern left blank */],
2598 dag iops = (ins GPR:$Rn, GPR:$Rm), string asm = "\t$Rd, $Rn, $Rm">
2599 : AI<(outs GPR:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
2603 let Inst{27-20} = op27_20;
2604 let Inst{11-4} = op11_4;
2605 let Inst{19-16} = Rn;
2606 let Inst{15-12} = Rd;
2610 // Saturating add/subtract -- for disassembly only
2612 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2613 [(set GPR:$Rd, (int_arm_qadd GPR:$Rm, GPR:$Rn))],
2614 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2615 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2616 [(set GPR:$Rd, (int_arm_qsub GPR:$Rm, GPR:$Rn))],
2617 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2618 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [], (ins GPR:$Rm, GPR:$Rn),
2620 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [], (ins GPR:$Rm, GPR:$Rn),
2623 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2624 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2625 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2626 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2627 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2628 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2629 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2630 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2631 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2632 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2633 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2634 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2636 // Signed/Unsigned add/subtract -- for disassembly only
2638 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2639 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2640 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2641 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2642 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2643 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2644 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2645 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2646 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2647 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2648 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2649 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2651 // Signed/Unsigned halving add/subtract -- for disassembly only
2653 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2654 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2655 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2656 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2657 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2658 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2659 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2660 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2661 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2662 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2663 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2664 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2666 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2668 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2669 MulFrm /* for convenience */, NoItinerary, "usad8",
2670 "\t$Rd, $Rn, $Rm", []>,
2671 Requires<[IsARM, HasV6]> {
2675 let Inst{27-20} = 0b01111000;
2676 let Inst{15-12} = 0b1111;
2677 let Inst{7-4} = 0b0001;
2678 let Inst{19-16} = Rd;
2679 let Inst{11-8} = Rm;
2682 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2683 MulFrm /* for convenience */, NoItinerary, "usada8",
2684 "\t$Rd, $Rn, $Rm, $Ra", []>,
2685 Requires<[IsARM, HasV6]> {
2690 let Inst{27-20} = 0b01111000;
2691 let Inst{7-4} = 0b0001;
2692 let Inst{19-16} = Rd;
2693 let Inst{15-12} = Ra;
2694 let Inst{11-8} = Rm;
2698 // Signed/Unsigned saturate -- for disassembly only
2700 def SSAT : AI<(outs GPR:$Rd), (ins ssat_imm:$sat_imm, GPR:$a, shift_imm:$sh),
2701 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2702 [/* For disassembly only; pattern left blank */]> {
2707 let Inst{27-21} = 0b0110101;
2708 let Inst{5-4} = 0b01;
2709 let Inst{20-16} = sat_imm;
2710 let Inst{15-12} = Rd;
2711 let Inst{11-7} = sh{7-3};
2712 let Inst{6} = sh{0};
2716 def SSAT16 : AI<(outs GPR:$Rd), (ins ssat_imm:$sat_imm, GPR:$Rn), SatFrm,
2717 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2718 [/* For disassembly only; pattern left blank */]> {
2722 let Inst{27-20} = 0b01101010;
2723 let Inst{11-4} = 0b11110011;
2724 let Inst{15-12} = Rd;
2725 let Inst{19-16} = sat_imm;
2729 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2730 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2731 [/* For disassembly only; pattern left blank */]> {
2736 let Inst{27-21} = 0b0110111;
2737 let Inst{5-4} = 0b01;
2738 let Inst{15-12} = Rd;
2739 let Inst{11-7} = sh{7-3};
2740 let Inst{6} = sh{0};
2741 let Inst{20-16} = sat_imm;
2745 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2746 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2747 [/* For disassembly only; pattern left blank */]> {
2751 let Inst{27-20} = 0b01101110;
2752 let Inst{11-4} = 0b11110011;
2753 let Inst{15-12} = Rd;
2754 let Inst{19-16} = sat_imm;
2758 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2759 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2761 //===----------------------------------------------------------------------===//
2762 // Bitwise Instructions.
2765 defm AND : AsI1_bin_irs<0b0000, "and",
2766 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2767 BinOpFrag<(and node:$LHS, node:$RHS)>, "AND", 1>;
2768 defm ORR : AsI1_bin_irs<0b1100, "orr",
2769 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2770 BinOpFrag<(or node:$LHS, node:$RHS)>, "ORR", 1>;
2771 defm EOR : AsI1_bin_irs<0b0001, "eor",
2772 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2773 BinOpFrag<(xor node:$LHS, node:$RHS)>, "EOR", 1>;
2774 defm BIC : AsI1_bin_irs<0b1110, "bic",
2775 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2776 BinOpFrag<(and node:$LHS, (not node:$RHS))>, "BIC">;
2778 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2779 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
2780 "bfc", "\t$Rd, $imm", "$src = $Rd",
2781 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2782 Requires<[IsARM, HasV6T2]> {
2785 let Inst{27-21} = 0b0111110;
2786 let Inst{6-0} = 0b0011111;
2787 let Inst{15-12} = Rd;
2788 let Inst{11-7} = imm{4-0}; // lsb
2789 let Inst{20-16} = imm{9-5}; // width
2792 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2793 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2794 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
2795 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2796 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2797 bf_inv_mask_imm:$imm))]>,
2798 Requires<[IsARM, HasV6T2]> {
2802 let Inst{27-21} = 0b0111110;
2803 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2804 let Inst{15-12} = Rd;
2805 let Inst{11-7} = imm{4-0}; // lsb
2806 let Inst{20-16} = imm{9-5}; // width
2810 // GNU as only supports this form of bfi (w/ 4 arguments)
2811 let isAsmParserOnly = 1 in
2812 def BFI4p : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn,
2813 lsb_pos_imm:$lsb, width_imm:$width),
2814 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
2815 "bfi", "\t$Rd, $Rn, $lsb, $width", "$src = $Rd",
2816 []>, Requires<[IsARM, HasV6T2]> {
2821 let Inst{27-21} = 0b0111110;
2822 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2823 let Inst{15-12} = Rd;
2824 let Inst{11-7} = lsb;
2825 let Inst{20-16} = width; // Custom encoder => lsb+width-1
2829 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2830 "mvn", "\t$Rd, $Rm",
2831 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2835 let Inst{19-16} = 0b0000;
2836 let Inst{11-4} = 0b00000000;
2837 let Inst{15-12} = Rd;
2840 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift), DPSoRegFrm,
2841 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2842 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
2846 let Inst{19-16} = 0b0000;
2847 let Inst{15-12} = Rd;
2848 let Inst{11-5} = shift{11-5};
2850 let Inst{3-0} = shift{3-0};
2852 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift), DPSoRegFrm,
2853 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2854 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
2858 let Inst{19-16} = 0b0000;
2859 let Inst{15-12} = Rd;
2860 let Inst{11-8} = shift{11-8};
2862 let Inst{6-5} = shift{6-5};
2864 let Inst{3-0} = shift{3-0};
2866 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2867 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2868 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2869 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2873 let Inst{19-16} = 0b0000;
2874 let Inst{15-12} = Rd;
2875 let Inst{11-0} = imm;
2878 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2879 (BICri GPR:$src, so_imm_not:$imm)>;
2881 //===----------------------------------------------------------------------===//
2882 // Multiply Instructions.
2884 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2885 string opc, string asm, list<dag> pattern>
2886 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2890 let Inst{19-16} = Rd;
2891 let Inst{11-8} = Rm;
2894 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2895 string opc, string asm, list<dag> pattern>
2896 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2901 let Inst{19-16} = RdHi;
2902 let Inst{15-12} = RdLo;
2903 let Inst{11-8} = Rm;
2907 // FIXME: The v5 pseudos are only necessary for the additional Constraint
2908 // property. Remove them when it's possible to add those properties
2909 // on an individual MachineInstr, not just an instuction description.
2910 let isCommutable = 1 in {
2911 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2912 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2913 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2914 Requires<[IsARM, HasV6]> {
2915 let Inst{15-12} = 0b0000;
2918 let Constraints = "@earlyclobber $Rd" in
2919 def MULv5: ARMPseudoExpand<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
2920 pred:$p, cc_out:$s),
2922 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))],
2923 (MUL GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
2924 Requires<[IsARM, NoV6]>;
2927 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2928 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2929 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2930 Requires<[IsARM, HasV6]> {
2932 let Inst{15-12} = Ra;
2935 let Constraints = "@earlyclobber $Rd" in
2936 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
2937 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
2939 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
2940 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
2941 Requires<[IsARM, NoV6]>;
2943 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2944 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
2945 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
2946 Requires<[IsARM, HasV6T2]> {
2951 let Inst{19-16} = Rd;
2952 let Inst{15-12} = Ra;
2953 let Inst{11-8} = Rm;
2957 // Extra precision multiplies with low / high results
2958 let neverHasSideEffects = 1 in {
2959 let isCommutable = 1 in {
2960 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2961 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2962 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2963 Requires<[IsARM, HasV6]>;
2965 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2966 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2967 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2968 Requires<[IsARM, HasV6]>;
2970 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2971 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
2972 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2974 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
2975 Requires<[IsARM, NoV6]>;
2977 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
2978 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2980 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
2981 Requires<[IsARM, NoV6]>;
2985 // Multiply + accumulate
2986 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2987 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2988 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2989 Requires<[IsARM, HasV6]>;
2990 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2991 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2992 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2993 Requires<[IsARM, HasV6]>;
2995 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2996 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2997 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2998 Requires<[IsARM, HasV6]> {
3003 let Inst{19-16} = RdLo;
3004 let Inst{15-12} = RdHi;
3005 let Inst{11-8} = Rm;
3009 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3010 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3011 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3013 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3014 Requires<[IsARM, NoV6]>;
3015 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3016 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3018 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3019 Requires<[IsARM, NoV6]>;
3020 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3021 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3023 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3024 Requires<[IsARM, NoV6]>;
3027 } // neverHasSideEffects
3029 // Most significant word multiply
3030 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3031 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3032 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3033 Requires<[IsARM, HasV6]> {
3034 let Inst{15-12} = 0b1111;
3037 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3038 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
3039 [/* For disassembly only; pattern left blank */]>,
3040 Requires<[IsARM, HasV6]> {
3041 let Inst{15-12} = 0b1111;
3044 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3045 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3046 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3047 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3048 Requires<[IsARM, HasV6]>;
3050 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3051 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3052 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
3053 [/* For disassembly only; pattern left blank */]>,
3054 Requires<[IsARM, HasV6]>;
3056 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3057 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3058 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
3059 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
3060 Requires<[IsARM, HasV6]>;
3062 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3063 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3064 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
3065 [/* For disassembly only; pattern left blank */]>,
3066 Requires<[IsARM, HasV6]>;
3068 multiclass AI_smul<string opc, PatFrag opnode> {
3069 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3070 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3071 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3072 (sext_inreg GPR:$Rm, i16)))]>,
3073 Requires<[IsARM, HasV5TE]>;
3075 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3076 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3077 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3078 (sra GPR:$Rm, (i32 16))))]>,
3079 Requires<[IsARM, HasV5TE]>;
3081 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3082 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3083 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3084 (sext_inreg GPR:$Rm, i16)))]>,
3085 Requires<[IsARM, HasV5TE]>;
3087 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3088 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3089 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3090 (sra GPR:$Rm, (i32 16))))]>,
3091 Requires<[IsARM, HasV5TE]>;
3093 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3094 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3095 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3096 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3097 Requires<[IsARM, HasV5TE]>;
3099 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3100 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3101 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3102 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3103 Requires<[IsARM, HasV5TE]>;
3107 multiclass AI_smla<string opc, PatFrag opnode> {
3108 def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
3109 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3110 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3111 [(set GPR:$Rd, (add GPR:$Ra,
3112 (opnode (sext_inreg GPR:$Rn, i16),
3113 (sext_inreg GPR:$Rm, i16))))]>,
3114 Requires<[IsARM, HasV5TE]>;
3116 def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd),
3117 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3118 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3119 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
3120 (sra GPR:$Rm, (i32 16)))))]>,
3121 Requires<[IsARM, HasV5TE]>;
3123 def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd),
3124 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3125 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3126 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
3127 (sext_inreg GPR:$Rm, i16))))]>,
3128 Requires<[IsARM, HasV5TE]>;
3130 def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
3131 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3132 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3133 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
3134 (sra GPR:$Rm, (i32 16)))))]>,
3135 Requires<[IsARM, HasV5TE]>;
3137 def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd),
3138 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3139 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3140 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
3141 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
3142 Requires<[IsARM, HasV5TE]>;
3144 def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd),
3145 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3146 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3147 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
3148 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
3149 Requires<[IsARM, HasV5TE]>;
3152 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3153 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3155 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
3156 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
3157 (ins GPR:$Rn, GPR:$Rm),
3158 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
3159 [/* For disassembly only; pattern left blank */]>,
3160 Requires<[IsARM, HasV5TE]>;
3162 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
3163 (ins GPR:$Rn, GPR:$Rm),
3164 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
3165 [/* For disassembly only; pattern left blank */]>,
3166 Requires<[IsARM, HasV5TE]>;
3168 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
3169 (ins GPR:$Rn, GPR:$Rm),
3170 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
3171 [/* For disassembly only; pattern left blank */]>,
3172 Requires<[IsARM, HasV5TE]>;
3174 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
3175 (ins GPR:$Rn, GPR:$Rm),
3176 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
3177 [/* For disassembly only; pattern left blank */]>,
3178 Requires<[IsARM, HasV5TE]>;
3180 // Helper class for AI_smld -- for disassembly only
3181 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3182 InstrItinClass itin, string opc, string asm>
3183 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3190 let Inst{21-20} = 0b00;
3191 let Inst{22} = long;
3192 let Inst{27-23} = 0b01110;
3193 let Inst{11-8} = Rm;
3196 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3197 InstrItinClass itin, string opc, string asm>
3198 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3200 let Inst{15-12} = 0b1111;
3201 let Inst{19-16} = Rd;
3203 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3204 InstrItinClass itin, string opc, string asm>
3205 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3207 let Inst{15-12} = Ra;
3209 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3210 InstrItinClass itin, string opc, string asm>
3211 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3214 let Inst{19-16} = RdHi;
3215 let Inst{15-12} = RdLo;
3218 multiclass AI_smld<bit sub, string opc> {
3220 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3221 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3223 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3224 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3226 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
3227 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
3228 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3230 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
3231 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
3232 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3236 defm SMLA : AI_smld<0, "smla">;
3237 defm SMLS : AI_smld<1, "smls">;
3239 multiclass AI_sdml<bit sub, string opc> {
3241 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3242 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3243 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3244 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3247 defm SMUA : AI_sdml<0, "smua">;
3248 defm SMUS : AI_sdml<1, "smus">;
3250 //===----------------------------------------------------------------------===//
3251 // Misc. Arithmetic Instructions.
3254 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3255 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3256 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3258 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3259 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3260 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3261 Requires<[IsARM, HasV6T2]>;
3263 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3264 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3265 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3267 let AddedComplexity = 5 in
3268 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3269 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3270 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3271 Requires<[IsARM, HasV6]>;
3273 let AddedComplexity = 5 in
3274 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3275 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3276 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3277 Requires<[IsARM, HasV6]>;
3279 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3280 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3283 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
3284 (ins GPR:$Rn, GPR:$Rm, pkh_lsl_amt:$sh),
3285 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3286 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
3287 (and (shl GPR:$Rm, pkh_lsl_amt:$sh),
3289 Requires<[IsARM, HasV6]>;
3291 // Alternate cases for PKHBT where identities eliminate some nodes.
3292 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
3293 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
3294 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
3295 (PKHBT GPR:$Rn, GPR:$Rm, imm16_31:$sh)>;
3297 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3298 // will match the pattern below.
3299 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
3300 (ins GPR:$Rn, GPR:$Rm, pkh_asr_amt:$sh),
3301 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3302 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
3303 (and (sra GPR:$Rm, pkh_asr_amt:$sh),
3305 Requires<[IsARM, HasV6]>;
3307 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3308 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3309 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
3310 (PKHTB GPR:$src1, GPR:$src2, imm16_31:$sh)>;
3311 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
3312 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
3313 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$sh)>;
3315 //===----------------------------------------------------------------------===//
3316 // Comparison Instructions...
3319 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3320 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3321 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3323 // ARMcmpZ can re-use the above instruction definitions.
3324 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3325 (CMPri GPR:$src, so_imm:$imm)>;
3326 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3327 (CMPrr GPR:$src, GPR:$rhs)>;
3328 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
3329 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
3330 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
3331 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
3333 // FIXME: We have to be careful when using the CMN instruction and comparison
3334 // with 0. One would expect these two pieces of code should give identical
3350 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3351 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3352 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3353 // value of r0 and the carry bit (because the "carry bit" parameter to
3354 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3355 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3356 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3357 // parameter to AddWithCarry is defined as 0).
3359 // When x is 0 and unsigned:
3363 // ~x + 1 = 0x1 0000 0000
3364 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3366 // Therefore, we should disable CMN when comparing against zero, until we can
3367 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3368 // when it's a comparison which doesn't look at the 'carry' flag).
3370 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3372 // This is related to <rdar://problem/7569620>.
3374 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3375 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3377 // Note that TST/TEQ don't set all the same flags that CMP does!
3378 defm TST : AI1_cmp_irs<0b1000, "tst",
3379 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3380 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3381 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3382 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3383 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3385 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
3386 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3387 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
3389 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3390 // (CMNri GPR:$src, so_imm_neg:$imm)>;
3392 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3393 (CMNzri GPR:$src, so_imm_neg:$imm)>;
3395 // Pseudo i64 compares for some floating point compares.
3396 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3398 def BCCi64 : PseudoInst<(outs),
3399 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3401 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3403 def BCCZi64 : PseudoInst<(outs),
3404 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3405 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3406 } // usesCustomInserter
3409 // Conditional moves
3410 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3411 // a two-value operand where a dag node expects two operands. :(
3412 let neverHasSideEffects = 1 in {
3413 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3415 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3416 RegConstraint<"$false = $Rd">;
3417 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
3418 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
3420 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift, imm:$cc, CCR:$ccr))*/]>,
3421 RegConstraint<"$false = $Rd">;
3422 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
3423 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
3425 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
3426 RegConstraint<"$false = $Rd">;
3429 let isMoveImm = 1 in
3430 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3431 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
3434 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3436 let isMoveImm = 1 in
3437 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3438 (ins GPR:$false, so_imm:$imm, pred:$p),
3440 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3441 RegConstraint<"$false = $Rd">;
3443 // Two instruction predicate mov immediate.
3444 let isMoveImm = 1 in
3445 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
3446 (ins GPR:$false, i32imm:$src, pred:$p),
3447 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3449 let isMoveImm = 1 in
3450 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
3451 (ins GPR:$false, so_imm:$imm, pred:$p),
3453 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3454 RegConstraint<"$false = $Rd">;
3455 } // neverHasSideEffects
3457 //===----------------------------------------------------------------------===//
3458 // Atomic operations intrinsics
3461 def memb_opt : Operand<i32> {
3462 let PrintMethod = "printMemBOption";
3463 let ParserMatchClass = MemBarrierOptOperand;
3466 // memory barriers protect the atomic sequences
3467 let hasSideEffects = 1 in {
3468 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3469 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3470 Requires<[IsARM, HasDB]> {
3472 let Inst{31-4} = 0xf57ff05;
3473 let Inst{3-0} = opt;
3477 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3478 "dsb", "\t$opt", []>,
3479 Requires<[IsARM, HasDB]> {
3481 let Inst{31-4} = 0xf57ff04;
3482 let Inst{3-0} = opt;
3485 // ISB has only full system option
3486 def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3487 "isb", "\t$opt", []>,
3488 Requires<[IsARM, HasDB]> {
3490 let Inst{31-4} = 0xf57ff06;
3491 let Inst{3-0} = opt;
3494 let usesCustomInserter = 1 in {
3495 let Uses = [CPSR] in {
3496 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
3497 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3498 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
3499 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
3500 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3501 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
3502 def ATOMIC_LOAD_AND_I8 : PseudoInst<
3503 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3504 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
3505 def ATOMIC_LOAD_OR_I8 : PseudoInst<
3506 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3507 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
3508 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
3509 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3510 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
3511 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
3512 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3513 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
3514 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
3515 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3516 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
3517 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
3518 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3519 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
3520 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
3521 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3522 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
3523 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
3524 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3525 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
3526 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
3527 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3528 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
3529 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
3530 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3531 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
3532 def ATOMIC_LOAD_AND_I16 : PseudoInst<
3533 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3534 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
3535 def ATOMIC_LOAD_OR_I16 : PseudoInst<
3536 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3537 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
3538 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
3539 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3540 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
3541 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
3542 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3543 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
3544 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
3545 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3546 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
3547 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
3548 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3549 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
3550 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
3551 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3552 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
3553 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
3554 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3555 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
3556 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
3557 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3558 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
3559 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
3560 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3561 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
3562 def ATOMIC_LOAD_AND_I32 : PseudoInst<
3563 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3564 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
3565 def ATOMIC_LOAD_OR_I32 : PseudoInst<
3566 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3567 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
3568 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
3569 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3570 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
3571 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
3572 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3573 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
3574 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
3575 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3576 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
3577 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
3578 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3579 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
3580 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
3581 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3582 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
3583 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
3584 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3585 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
3587 def ATOMIC_SWAP_I8 : PseudoInst<
3588 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3589 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3590 def ATOMIC_SWAP_I16 : PseudoInst<
3591 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3592 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3593 def ATOMIC_SWAP_I32 : PseudoInst<
3594 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3595 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3597 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3598 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3599 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3600 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3601 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3602 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3603 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3604 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3605 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3609 let mayLoad = 1 in {
3610 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3611 "ldrexb", "\t$Rt, $addr", []>;
3612 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3613 "ldrexh", "\t$Rt, $addr", []>;
3614 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3615 "ldrex", "\t$Rt, $addr", []>;
3616 let hasExtraDefRegAllocReq = 1 in
3617 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode7:$addr),
3618 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []>;
3621 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3622 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3623 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
3624 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3625 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
3626 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3627 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
3630 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
3631 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3632 (ins GPR:$Rt, GPR:$Rt2, addrmode7:$addr),
3633 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []>;
3635 // Clear-Exclusive is for disassembly only.
3636 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3637 [/* For disassembly only; pattern left blank */]>,
3638 Requires<[IsARM, HasV7]> {
3639 let Inst{31-0} = 0b11110101011111111111000000011111;
3642 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3643 let mayLoad = 1 in {
3644 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3645 [/* For disassembly only; pattern left blank */]>;
3646 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3647 [/* For disassembly only; pattern left blank */]>;
3650 //===----------------------------------------------------------------------===//
3651 // Coprocessor Instructions.
3654 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3655 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3656 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3657 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3658 imm:$CRm, imm:$opc2)]> {
3666 let Inst{3-0} = CRm;
3668 let Inst{7-5} = opc2;
3669 let Inst{11-8} = cop;
3670 let Inst{15-12} = CRd;
3671 let Inst{19-16} = CRn;
3672 let Inst{23-20} = opc1;
3675 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3676 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3677 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3678 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3679 imm:$CRm, imm:$opc2)]> {
3680 let Inst{31-28} = 0b1111;
3688 let Inst{3-0} = CRm;
3690 let Inst{7-5} = opc2;
3691 let Inst{11-8} = cop;
3692 let Inst{15-12} = CRd;
3693 let Inst{19-16} = CRn;
3694 let Inst{23-20} = opc1;
3697 class ACI<dag oops, dag iops, string opc, string asm,
3698 IndexMode im = IndexModeNone>
3699 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
3700 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3701 let Inst{27-25} = 0b110;
3704 multiclass LdStCop<bits<4> op31_28, bit load, dag ops, string opc, string cond>{
3706 def _OFFSET : ACI<(outs),
3707 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3708 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr"> {
3709 let Inst{31-28} = op31_28;
3710 let Inst{24} = 1; // P = 1
3711 let Inst{21} = 0; // W = 0
3712 let Inst{22} = 0; // D = 0
3713 let Inst{20} = load;
3716 def _PRE : ACI<(outs),
3717 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3718 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr!", IndexModePre> {
3719 let Inst{31-28} = op31_28;
3720 let Inst{24} = 1; // P = 1
3721 let Inst{21} = 1; // W = 1
3722 let Inst{22} = 0; // D = 0
3723 let Inst{20} = load;
3726 def _POST : ACI<(outs),
3727 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3728 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr", IndexModePost> {
3729 let Inst{31-28} = op31_28;
3730 let Inst{24} = 0; // P = 0
3731 let Inst{21} = 1; // W = 1
3732 let Inst{22} = 0; // D = 0
3733 let Inst{20} = load;
3736 def _OPTION : ACI<(outs),
3737 !con((ins nohash_imm:$cop,nohash_imm:$CRd,GPR:$base, nohash_imm:$option),
3739 !strconcat(opc, cond), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3740 let Inst{31-28} = op31_28;
3741 let Inst{24} = 0; // P = 0
3742 let Inst{23} = 1; // U = 1
3743 let Inst{21} = 0; // W = 0
3744 let Inst{22} = 0; // D = 0
3745 let Inst{20} = load;
3748 def L_OFFSET : ACI<(outs),
3749 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3750 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr"> {
3751 let Inst{31-28} = op31_28;
3752 let Inst{24} = 1; // P = 1
3753 let Inst{21} = 0; // W = 0
3754 let Inst{22} = 1; // D = 1
3755 let Inst{20} = load;
3758 def L_PRE : ACI<(outs),
3759 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3760 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr!",
3762 let Inst{31-28} = op31_28;
3763 let Inst{24} = 1; // P = 1
3764 let Inst{21} = 1; // W = 1
3765 let Inst{22} = 1; // D = 1
3766 let Inst{20} = load;
3769 def L_POST : ACI<(outs),
3770 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3771 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr",
3773 let Inst{31-28} = op31_28;
3774 let Inst{24} = 0; // P = 0
3775 let Inst{21} = 1; // W = 1
3776 let Inst{22} = 1; // D = 1
3777 let Inst{20} = load;
3780 def L_OPTION : ACI<(outs),
3781 !con((ins nohash_imm:$cop, nohash_imm:$CRd,GPR:$base,nohash_imm:$option),
3783 !strconcat(!strconcat(opc, "l"), cond),
3784 "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3785 let Inst{31-28} = op31_28;
3786 let Inst{24} = 0; // P = 0
3787 let Inst{23} = 1; // U = 1
3788 let Inst{21} = 0; // W = 0
3789 let Inst{22} = 1; // D = 1
3790 let Inst{20} = load;
3794 defm LDC : LdStCop<{?,?,?,?}, 1, (ins pred:$p), "ldc", "${p}">;
3795 defm LDC2 : LdStCop<0b1111, 1, (ins), "ldc2", "">;
3796 defm STC : LdStCop<{?,?,?,?}, 0, (ins pred:$p), "stc", "${p}">;
3797 defm STC2 : LdStCop<0b1111, 0, (ins), "stc2", "">;
3799 //===----------------------------------------------------------------------===//
3800 // Move between coprocessor and ARM core register -- for disassembly only
3803 class MovRCopro<string opc, bit direction, dag oops, dag iops,
3805 : ABI<0b1110, oops, iops, NoItinerary, opc,
3806 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
3807 let Inst{20} = direction;
3817 let Inst{15-12} = Rt;
3818 let Inst{11-8} = cop;
3819 let Inst{23-21} = opc1;
3820 let Inst{7-5} = opc2;
3821 let Inst{3-0} = CRm;
3822 let Inst{19-16} = CRn;
3825 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
3827 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3828 c_imm:$CRm, imm0_7:$opc2),
3829 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3830 imm:$CRm, imm:$opc2)]>;
3831 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
3833 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
3836 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3837 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3839 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
3841 : ABXI<0b1110, oops, iops, NoItinerary,
3842 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
3843 let Inst{31-28} = 0b1111;
3844 let Inst{20} = direction;
3854 let Inst{15-12} = Rt;
3855 let Inst{11-8} = cop;
3856 let Inst{23-21} = opc1;
3857 let Inst{7-5} = opc2;
3858 let Inst{3-0} = CRm;
3859 let Inst{19-16} = CRn;
3862 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
3864 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3865 c_imm:$CRm, imm0_7:$opc2),
3866 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3867 imm:$CRm, imm:$opc2)]>;
3868 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
3870 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
3873 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
3874 imm:$CRm, imm:$opc2),
3875 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3877 class MovRRCopro<string opc, bit direction,
3878 list<dag> pattern = [/* For disassembly only */]>
3879 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3880 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3881 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
3882 let Inst{23-21} = 0b010;
3883 let Inst{20} = direction;
3891 let Inst{15-12} = Rt;
3892 let Inst{19-16} = Rt2;
3893 let Inst{11-8} = cop;
3894 let Inst{7-4} = opc1;
3895 let Inst{3-0} = CRm;
3898 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
3899 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3901 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
3903 class MovRRCopro2<string opc, bit direction,
3904 list<dag> pattern = [/* For disassembly only */]>
3905 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3906 GPR:$Rt, GPR:$Rt2, c_imm:$CRm), NoItinerary,
3907 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3908 let Inst{31-28} = 0b1111;
3909 let Inst{23-21} = 0b010;
3910 let Inst{20} = direction;
3918 let Inst{15-12} = Rt;
3919 let Inst{19-16} = Rt2;
3920 let Inst{11-8} = cop;
3921 let Inst{7-4} = opc1;
3922 let Inst{3-0} = CRm;
3925 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
3926 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3928 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
3930 //===----------------------------------------------------------------------===//
3931 // Move between special register and ARM core register
3934 // Move to ARM core register from Special Register
3935 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
3936 "mrs", "\t$Rd, apsr", []> {
3938 let Inst{23-16} = 0b00001111;
3939 let Inst{15-12} = Rd;
3940 let Inst{7-4} = 0b0000;
3943 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPR:$Rd, pred:$p)>, Requires<[IsARM]>;
3945 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
3946 "mrs", "\t$Rd, spsr", []> {
3948 let Inst{23-16} = 0b01001111;
3949 let Inst{15-12} = Rd;
3950 let Inst{7-4} = 0b0000;
3953 // Move from ARM core register to Special Register
3955 // No need to have both system and application versions, the encodings are the
3956 // same and the assembly parser has no way to distinguish between them. The mask
3957 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3958 // the mask with the fields to be accessed in the special register.
3959 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
3960 "msr", "\t$mask, $Rn", []> {
3965 let Inst{22} = mask{4}; // R bit
3966 let Inst{21-20} = 0b10;
3967 let Inst{19-16} = mask{3-0};
3968 let Inst{15-12} = 0b1111;
3969 let Inst{11-4} = 0b00000000;
3973 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
3974 "msr", "\t$mask, $a", []> {
3979 let Inst{22} = mask{4}; // R bit
3980 let Inst{21-20} = 0b10;
3981 let Inst{19-16} = mask{3-0};
3982 let Inst{15-12} = 0b1111;
3986 //===----------------------------------------------------------------------===//
3990 // __aeabi_read_tp preserves the registers r1-r3.
3991 // This is a pseudo inst so that we can get the encoding right,
3992 // complete with fixup for the aeabi_read_tp function.
3994 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
3995 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
3996 [(set R0, ARMthread_pointer)]>;
3999 //===----------------------------------------------------------------------===//
4000 // SJLJ Exception handling intrinsics
4001 // eh_sjlj_setjmp() is an instruction sequence to store the return
4002 // address and save #0 in R0 for the non-longjmp case.
4003 // Since by its nature we may be coming from some other function to get
4004 // here, and we're using the stack frame for the containing function to
4005 // save/restore registers, we can't keep anything live in regs across
4006 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4007 // when we get here from a longjmp(). We force everything out of registers
4008 // except for our own input by listing the relevant registers in Defs. By
4009 // doing so, we also cause the prologue/epilogue code to actively preserve
4010 // all of the callee-saved resgisters, which is exactly what we want.
4011 // A constant value is passed in $val, and we use the location as a scratch.
4013 // These are pseudo-instructions and are lowered to individual MC-insts, so
4014 // no encoding information is necessary.
4016 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4017 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ], hasSideEffects = 1, isBarrier = 1 in {
4018 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4020 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4021 Requires<[IsARM, HasVFP2]>;
4025 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4026 hasSideEffects = 1, isBarrier = 1 in {
4027 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4029 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4030 Requires<[IsARM, NoVFP]>;
4033 // FIXME: Non-Darwin version(s)
4034 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4035 Defs = [ R7, LR, SP ] in {
4036 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4038 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4039 Requires<[IsARM, IsDarwin]>;
4042 // eh.sjlj.dispatchsetup pseudo-instruction.
4043 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
4044 // handled when the pseudo is expanded (which happens before any passes
4045 // that need the instruction size).
4046 let isBarrier = 1, hasSideEffects = 1 in
4047 def Int_eh_sjlj_dispatchsetup :
4048 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
4049 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
4050 Requires<[IsDarwin]>;
4052 //===----------------------------------------------------------------------===//
4053 // Non-Instruction Patterns
4056 // ARMv4 indirect branch using (MOVr PC, dst)
4057 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4058 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4059 4, IIC_Br, [(brind GPR:$dst)],
4060 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4061 Requires<[IsARM, NoV4T]>;
4063 // Large immediate handling.
4065 // 32-bit immediate using two piece so_imms or movw + movt.
4066 // This is a single pseudo instruction, the benefit is that it can be remat'd
4067 // as a single unit instead of having to handle reg inputs.
4068 // FIXME: Remove this when we can do generalized remat.
4069 let isReMaterializable = 1, isMoveImm = 1 in
4070 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4071 [(set GPR:$dst, (arm_i32imm:$src))]>,
4074 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4075 // It also makes it possible to rematerialize the instructions.
4076 // FIXME: Remove this when we can do generalized remat and when machine licm
4077 // can properly the instructions.
4078 let isReMaterializable = 1 in {
4079 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4081 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4082 Requires<[IsARM, UseMovt]>;
4084 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4086 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4087 Requires<[IsARM, UseMovt]>;
4089 let AddedComplexity = 10 in
4090 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4092 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4093 Requires<[IsARM, UseMovt]>;
4094 } // isReMaterializable
4096 // ConstantPool, GlobalAddress, and JumpTable
4097 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4098 Requires<[IsARM, DontUseMovt]>;
4099 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4100 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4101 Requires<[IsARM, UseMovt]>;
4102 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4103 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4105 // TODO: add,sub,and, 3-instr forms?
4108 def : ARMPat<(ARMtcret tcGPR:$dst),
4109 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
4111 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
4112 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
4114 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
4115 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
4117 def : ARMPat<(ARMtcret tcGPR:$dst),
4118 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
4120 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
4121 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
4123 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
4124 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
4127 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
4128 Requires<[IsARM, IsNotDarwin]>;
4129 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
4130 Requires<[IsARM, IsDarwin]>;
4132 // zextload i1 -> zextload i8
4133 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4134 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4136 // extload -> zextload
4137 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4138 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4139 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4140 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4142 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4144 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4145 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4148 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4149 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4150 (SMULBB GPR:$a, GPR:$b)>;
4151 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4152 (SMULBB GPR:$a, GPR:$b)>;
4153 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4154 (sra GPR:$b, (i32 16))),
4155 (SMULBT GPR:$a, GPR:$b)>;
4156 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
4157 (SMULBT GPR:$a, GPR:$b)>;
4158 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4159 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4160 (SMULTB GPR:$a, GPR:$b)>;
4161 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
4162 (SMULTB GPR:$a, GPR:$b)>;
4163 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4165 (SMULWB GPR:$a, GPR:$b)>;
4166 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
4167 (SMULWB GPR:$a, GPR:$b)>;
4169 def : ARMV5TEPat<(add GPR:$acc,
4170 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4171 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4172 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4173 def : ARMV5TEPat<(add GPR:$acc,
4174 (mul sext_16_node:$a, sext_16_node:$b)),
4175 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4176 def : ARMV5TEPat<(add GPR:$acc,
4177 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4178 (sra GPR:$b, (i32 16)))),
4179 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4180 def : ARMV5TEPat<(add GPR:$acc,
4181 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
4182 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4183 def : ARMV5TEPat<(add GPR:$acc,
4184 (mul (sra GPR:$a, (i32 16)),
4185 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4186 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4187 def : ARMV5TEPat<(add GPR:$acc,
4188 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
4189 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4190 def : ARMV5TEPat<(add GPR:$acc,
4191 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4193 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4194 def : ARMV5TEPat<(add GPR:$acc,
4195 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
4196 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4199 // Pre-v7 uses MCR for synchronization barriers.
4200 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
4201 Requires<[IsARM, HasV6]>;
4204 //===----------------------------------------------------------------------===//
4208 include "ARMInstrThumb.td"
4210 //===----------------------------------------------------------------------===//
4214 include "ARMInstrThumb2.td"
4216 //===----------------------------------------------------------------------===//
4217 // Floating Point Support
4220 include "ARMInstrVFP.td"
4222 //===----------------------------------------------------------------------===//
4223 // Advanced SIMD (NEON) Support
4226 include "ARMInstrNEON.td"
4228 //===----------------------------------------------------------------------===//
4229 // Assembler aliases
4233 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
4234 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
4235 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
4237 // System instructions
4238 def : MnemonicAlias<"swi", "svc">;
4240 // Load / Store Multiple
4241 def : MnemonicAlias<"ldmfd", "ldm">;
4242 def : MnemonicAlias<"ldmia", "ldm">;
4243 def : MnemonicAlias<"stmfd", "stmdb">;
4244 def : MnemonicAlias<"stmia", "stm">;
4245 def : MnemonicAlias<"stmea", "stm">;
4247 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4248 // shift amount is zero (i.e., unspecified).
4249 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4250 (PKHBT GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>;
4251 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4252 (PKHBT GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>;
4254 // PUSH/POP aliases for STM/LDM
4255 def : InstAlias<"push${p} $regs",
4256 (STMDB_UPD SP, pred:$p, reglist:$regs)>;
4257 def : InstAlias<"pop${p} $regs",
4258 (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4260 // RSB two-operand forms (optional explicit destination operand)
4261 def : InstAlias<"rsb${s}${p} $Rdn, $imm",
4262 (RSBri GPR:$Rdn, GPR:$Rdn, so_imm:$imm, pred:$p, cc_out:$s)>,
4264 def : InstAlias<"rsb${s}${p} $Rdn, $Rm",
4265 (RSBrr GPR:$Rdn, GPR:$Rdn, GPR:$Rm, pred:$p, cc_out:$s)>,
4267 def : InstAlias<"rsb${s}${p} $Rdn, $shift",
4268 (RSBrsi GPR:$Rdn, GPR:$Rdn, so_reg_imm:$shift, pred:$p,
4269 cc_out:$s)>, Requires<[IsARM]>;
4270 def : InstAlias<"rsb${s}${p} $Rdn, $shift",
4271 (RSBrsr GPR:$Rdn, GPR:$Rdn, so_reg_reg:$shift, pred:$p,
4272 cc_out:$s)>, Requires<[IsARM]>;