1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
67 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
68 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
72 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
74 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
75 [SDNPHasChain, SDNPOutFlag]>;
76 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
77 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
79 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
80 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
82 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
83 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
85 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
86 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
89 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
90 [SDNPHasChain, SDNPOptInFlag]>;
92 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
94 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
97 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
98 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
100 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
102 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
105 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
108 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
111 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
112 [SDNPOutFlag, SDNPCommutative]>;
114 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
116 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
117 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
118 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
120 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
121 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
122 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
123 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
124 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
125 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
126 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
129 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
131 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
134 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
136 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
137 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
140 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
142 //===----------------------------------------------------------------------===//
143 // ARM Instruction Predicate Definitions.
145 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
146 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
147 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
148 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
149 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
150 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
151 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
152 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
153 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
154 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
155 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
156 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
157 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
158 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
160 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
162 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
163 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
164 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
165 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
166 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
167 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
168 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
169 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
171 // FIXME: Eventually this will be just "hasV6T2Ops".
172 def UseMovt : Predicate<"Subtarget->useMovt()">;
173 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
174 def UseVMLx : Predicate<"Subtarget->useVMLx()">;
176 //===----------------------------------------------------------------------===//
177 // ARM Flag Definitions.
179 class RegConstraint<string C> {
180 string Constraints = C;
183 //===----------------------------------------------------------------------===//
184 // ARM specific transformation functions and pattern fragments.
187 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
188 // so_imm_neg def below.
189 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
190 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
193 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
194 // so_imm_not def below.
195 def so_imm_not_XFORM : SDNodeXForm<imm, [{
196 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
199 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
200 def imm1_15 : PatLeaf<(i32 imm), [{
201 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
204 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
205 def imm16_31 : PatLeaf<(i32 imm), [{
206 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
211 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
212 }], so_imm_neg_XFORM>;
216 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
217 }], so_imm_not_XFORM>;
219 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
220 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
221 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
224 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
226 def bf_inv_mask_imm : Operand<i32>,
228 return ARM::isBitFieldInvertedMask(N->getZExtValue());
230 string EncoderMethod = "getBitfieldInvertedMaskOpValue";
231 let PrintMethod = "printBitfieldInvMaskImmOperand";
234 /// Split a 32-bit immediate into two 16 bit parts.
235 def hi16 : SDNodeXForm<imm, [{
236 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
239 def lo16AllZero : PatLeaf<(i32 imm), [{
240 // Returns true if all low 16-bits are 0.
241 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
244 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
246 def imm0_65535 : PatLeaf<(i32 imm), [{
247 return (uint32_t)N->getZExtValue() < 65536;
250 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
251 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
253 /// adde and sube predicates - True based on whether the carry flag output
254 /// will be needed or not.
255 def adde_dead_carry :
256 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
257 [{return !N->hasAnyUseOfValue(1);}]>;
258 def sube_dead_carry :
259 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
260 [{return !N->hasAnyUseOfValue(1);}]>;
261 def adde_live_carry :
262 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
263 [{return N->hasAnyUseOfValue(1);}]>;
264 def sube_live_carry :
265 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
266 [{return N->hasAnyUseOfValue(1);}]>;
268 //===----------------------------------------------------------------------===//
269 // Operand Definitions.
273 def brtarget : Operand<OtherVT>;
275 // A list of registers separated by comma. Used by load/store multiple.
276 def reglist : Operand<i32> {
277 string EncoderMethod = "getRegisterListOpValue";
278 let PrintMethod = "printRegisterList";
281 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
282 def cpinst_operand : Operand<i32> {
283 let PrintMethod = "printCPInstOperand";
286 def jtblock_operand : Operand<i32> {
287 let PrintMethod = "printJTBlockOperand";
289 def jt2block_operand : Operand<i32> {
290 let PrintMethod = "printJT2BlockOperand";
294 def pclabel : Operand<i32> {
295 let PrintMethod = "printPCLabel";
298 def neon_vcvt_imm32 : Operand<i32> {
299 string EncoderMethod = "getNEONVcvtImm32OpValue";
302 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
303 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
304 int32_t v = (int32_t)N->getZExtValue();
305 return v == 8 || v == 16 || v == 24; }]> {
306 string EncoderMethod = "getRotImmOpValue";
309 // shift_imm: An integer that encodes a shift amount and the type of shift
310 // (currently either asr or lsl) using the same encoding used for the
311 // immediates in so_reg operands.
312 def shift_imm : Operand<i32> {
313 let PrintMethod = "printShiftImmOperand";
316 // shifter_operand operands: so_reg and so_imm.
317 def so_reg : Operand<i32>, // reg reg imm
318 ComplexPattern<i32, 3, "SelectShifterOperandReg",
319 [shl,srl,sra,rotr]> {
320 string EncoderMethod = "getSORegOpValue";
321 let PrintMethod = "printSORegOperand";
322 let MIOperandInfo = (ops GPR, GPR, i32imm);
324 def shift_so_reg : Operand<i32>, // reg reg imm
325 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
326 [shl,srl,sra,rotr]> {
327 string EncoderMethod = "getSORegOpValue";
328 let PrintMethod = "printSORegOperand";
329 let MIOperandInfo = (ops GPR, GPR, i32imm);
332 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
333 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
334 // represented in the imm field in the same 12-bit form that they are encoded
335 // into so_imm instructions: the 8-bit immediate is the least significant bits
336 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
337 def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> {
338 string EncoderMethod = "getSOImmOpValue";
339 let PrintMethod = "printSOImmOperand";
342 // Break so_imm's up into two pieces. This handles immediates with up to 16
343 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
344 // get the first/second pieces.
345 def so_imm2part : Operand<i32>,
347 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
349 let PrintMethod = "printSOImm2PartOperand";
352 def so_imm2part_1 : SDNodeXForm<imm, [{
353 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
354 return CurDAG->getTargetConstant(V, MVT::i32);
357 def so_imm2part_2 : SDNodeXForm<imm, [{
358 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
359 return CurDAG->getTargetConstant(V, MVT::i32);
362 def so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
363 return ARM_AM::isSOImmTwoPartVal(-(int)N->getZExtValue());
365 let PrintMethod = "printSOImm2PartOperand";
368 def so_neg_imm2part_1 : SDNodeXForm<imm, [{
369 unsigned V = ARM_AM::getSOImmTwoPartFirst(-(int)N->getZExtValue());
370 return CurDAG->getTargetConstant(V, MVT::i32);
373 def so_neg_imm2part_2 : SDNodeXForm<imm, [{
374 unsigned V = ARM_AM::getSOImmTwoPartSecond(-(int)N->getZExtValue());
375 return CurDAG->getTargetConstant(V, MVT::i32);
378 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
379 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
380 return (int32_t)N->getZExtValue() < 32;
383 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
384 def imm0_31_m1 : Operand<i32>, PatLeaf<(imm), [{
385 return (int32_t)N->getZExtValue() < 32;
387 string EncoderMethod = "getImmMinusOneOpValue";
390 // Define ARM specific addressing modes.
393 // addrmode_imm12 := reg +/- imm12
395 def addrmode_imm12 : Operand<i32>,
396 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
397 // 12-bit immediate operand. Note that instructions using this encode
398 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
399 // immediate values are as normal.
401 string EncoderMethod = "getAddrModeImmOpValue";
402 let PrintMethod = "printAddrModeImm12Operand";
403 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
405 // ldst_so_reg := reg +/- reg shop imm
407 def ldst_so_reg : Operand<i32>,
408 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
409 // FIXME: Simplify the printer
410 // FIXME: Add EncoderMethod for this addressing mode
411 let PrintMethod = "printAddrMode2Operand";
412 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
415 // addrmode2 := reg +/- imm12
416 // := reg +/- reg shop imm
418 def addrmode2 : Operand<i32>,
419 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
420 let PrintMethod = "printAddrMode2Operand";
421 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
424 def am2offset : Operand<i32>,
425 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
426 [], [SDNPWantRoot]> {
427 let PrintMethod = "printAddrMode2OffsetOperand";
428 let MIOperandInfo = (ops GPR, i32imm);
431 // addrmode3 := reg +/- reg
432 // addrmode3 := reg +/- imm8
434 def addrmode3 : Operand<i32>,
435 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
436 let PrintMethod = "printAddrMode3Operand";
437 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
440 def am3offset : Operand<i32>,
441 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
442 [], [SDNPWantRoot]> {
443 let PrintMethod = "printAddrMode3OffsetOperand";
444 let MIOperandInfo = (ops GPR, i32imm);
447 // addrmode4 := reg, <mode|W>
449 def addrmode4 : Operand<i32>,
450 ComplexPattern<i32, 2, "SelectAddrMode4", []> {
451 let PrintMethod = "printAddrMode4Operand";
452 let MIOperandInfo = (ops GPR:$addr, i32imm);
455 def ARMMemMode5AsmOperand : AsmOperandClass {
456 let Name = "MemMode5";
457 let SuperClasses = [];
460 // addrmode5 := reg +/- imm8*4
462 def addrmode5 : Operand<i32>,
463 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
464 let PrintMethod = "printAddrMode5Operand";
465 let MIOperandInfo = (ops GPR:$base, i32imm);
466 let ParserMatchClass = ARMMemMode5AsmOperand;
467 string EncoderMethod = "getAddrModeImmOpValue";
470 // addrmode6 := reg with optional writeback
472 def addrmode6 : Operand<i32>,
473 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
474 let PrintMethod = "printAddrMode6Operand";
475 let MIOperandInfo = (ops GPR:$addr, i32imm);
476 string EncoderMethod = "getAddrMode6AddressOpValue";
479 def am6offset : Operand<i32> {
480 let PrintMethod = "printAddrMode6OffsetOperand";
481 let MIOperandInfo = (ops GPR);
482 string EncoderMethod = "getAddrMode6OffsetOpValue";
485 // addrmodepc := pc + reg
487 def addrmodepc : Operand<i32>,
488 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
489 let PrintMethod = "printAddrModePCOperand";
490 let MIOperandInfo = (ops GPR, i32imm);
493 def nohash_imm : Operand<i32> {
494 let PrintMethod = "printNoHashImmediate";
497 //===----------------------------------------------------------------------===//
499 include "ARMInstrFormats.td"
501 //===----------------------------------------------------------------------===//
502 // Multiclass helpers...
505 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
506 /// binop that produces a value.
507 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
508 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
509 PatFrag opnode, bit Commutable = 0> {
510 // The register-immediate version is re-materializable. This is useful
511 // in particular for taking the address of a local.
512 let isReMaterializable = 1 in {
513 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
514 iii, opc, "\t$Rd, $Rn, $imm",
515 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
520 let Inst{19-16} = Rn;
521 let Inst{15-12} = Rd;
522 let Inst{11-0} = imm;
525 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
526 iir, opc, "\t$Rd, $Rn, $Rm",
527 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
532 let isCommutable = Commutable;
533 let Inst{19-16} = Rn;
534 let Inst{15-12} = Rd;
535 let Inst{11-4} = 0b00000000;
538 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
539 iis, opc, "\t$Rd, $Rn, $shift",
540 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
545 let Inst{19-16} = Rn;
546 let Inst{15-12} = Rd;
547 let Inst{11-0} = shift;
551 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
552 /// instruction modifies the CPSR register.
553 let Defs = [CPSR] in {
554 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
555 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
556 PatFrag opnode, bit Commutable = 0> {
557 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
558 iii, opc, "\t$Rd, $Rn, $imm",
559 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
565 let Inst{19-16} = Rn;
566 let Inst{15-12} = Rd;
567 let Inst{11-0} = imm;
569 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
570 iir, opc, "\t$Rd, $Rn, $Rm",
571 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
575 let isCommutable = Commutable;
578 let Inst{19-16} = Rn;
579 let Inst{15-12} = Rd;
580 let Inst{11-4} = 0b00000000;
583 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
584 iis, opc, "\t$Rd, $Rn, $shift",
585 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
591 let Inst{19-16} = Rn;
592 let Inst{15-12} = Rd;
593 let Inst{11-0} = shift;
598 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
599 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
600 /// a explicit result, only implicitly set CPSR.
601 let isCompare = 1, Defs = [CPSR] in {
602 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
603 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
604 PatFrag opnode, bit Commutable = 0> {
605 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
607 [(opnode GPR:$Rn, so_imm:$imm)]> {
612 let Inst{19-16} = Rn;
613 let Inst{15-12} = 0b0000;
614 let Inst{11-0} = imm;
616 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
618 [(opnode GPR:$Rn, GPR:$Rm)]> {
621 let isCommutable = Commutable;
624 let Inst{19-16} = Rn;
625 let Inst{15-12} = 0b0000;
626 let Inst{11-4} = 0b00000000;
629 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
630 opc, "\t$Rn, $shift",
631 [(opnode GPR:$Rn, so_reg:$shift)]> {
636 let Inst{19-16} = Rn;
637 let Inst{15-12} = 0b0000;
638 let Inst{11-0} = shift;
643 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
644 /// register and one whose operand is a register rotated by 8/16/24.
645 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
646 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
647 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
648 IIC_iEXTr, opc, "\t$Rd, $Rm",
649 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
650 Requires<[IsARM, HasV6]> {
653 let Inst{19-16} = 0b1111;
654 let Inst{15-12} = Rd;
655 let Inst{11-10} = 0b00;
658 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
659 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
660 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
661 Requires<[IsARM, HasV6]> {
665 let Inst{19-16} = 0b1111;
666 let Inst{15-12} = Rd;
667 let Inst{11-10} = rot;
672 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
673 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
674 IIC_iEXTr, opc, "\t$Rd, $Rm",
675 [/* For disassembly only; pattern left blank */]>,
676 Requires<[IsARM, HasV6]> {
677 let Inst{19-16} = 0b1111;
678 let Inst{11-10} = 0b00;
680 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
681 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
682 [/* For disassembly only; pattern left blank */]>,
683 Requires<[IsARM, HasV6]> {
685 let Inst{19-16} = 0b1111;
686 let Inst{11-10} = rot;
690 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
691 /// register and one whose operand is a register rotated by 8/16/24.
692 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
693 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
694 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
695 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
696 Requires<[IsARM, HasV6]> {
697 let Inst{11-10} = 0b00;
699 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
701 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
702 [(set GPR:$Rd, (opnode GPR:$Rn,
703 (rotr GPR:$Rm, rot_imm:$rot)))]>,
704 Requires<[IsARM, HasV6]> {
707 let Inst{19-16} = Rn;
708 let Inst{11-10} = rot;
712 // For disassembly only.
713 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
714 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
715 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
716 [/* For disassembly only; pattern left blank */]>,
717 Requires<[IsARM, HasV6]> {
718 let Inst{11-10} = 0b00;
720 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
722 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
723 [/* For disassembly only; pattern left blank */]>,
724 Requires<[IsARM, HasV6]> {
727 let Inst{19-16} = Rn;
728 let Inst{11-10} = rot;
732 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
733 let Uses = [CPSR] in {
734 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
735 bit Commutable = 0> {
736 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
737 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
738 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
744 let Inst{15-12} = Rd;
745 let Inst{19-16} = Rn;
746 let Inst{11-0} = imm;
748 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
749 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
750 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
755 let Inst{11-4} = 0b00000000;
757 let isCommutable = Commutable;
759 let Inst{15-12} = Rd;
760 let Inst{19-16} = Rn;
762 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
763 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
764 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
770 let Inst{11-0} = shift;
771 let Inst{15-12} = Rd;
772 let Inst{19-16} = Rn;
775 // Carry setting variants
776 let Defs = [CPSR] in {
777 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
778 bit Commutable = 0> {
779 def Sri : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
780 DPFrm, IIC_iALUi, !strconcat(opc, "\t$Rd, $Rn, $imm"),
781 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
786 let Inst{15-12} = Rd;
787 let Inst{19-16} = Rn;
788 let Inst{11-0} = imm;
792 def Srr : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
793 DPFrm, IIC_iALUr, !strconcat(opc, "\t$Rd, $Rn, $Rm"),
794 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
799 let Inst{11-4} = 0b00000000;
800 let isCommutable = Commutable;
802 let Inst{15-12} = Rd;
803 let Inst{19-16} = Rn;
807 def Srs : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
808 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$Rd, $Rn, $shift"),
809 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
814 let Inst{11-0} = shift;
815 let Inst{15-12} = Rd;
816 let Inst{19-16} = Rn;
824 let canFoldAsLoad = 1, isReMaterializable = 1 in {
825 multiclass AI_ldr1<bit opc22, string opc, InstrItinClass iii,
826 InstrItinClass iir, PatFrag opnode> {
827 // Note: We use the complex addrmode_imm12 rather than just an input
828 // GPR and a constrained immediate so that we can use this to match
829 // frame index references and avoid matching constant pool references.
830 def i12 : AIldst1<0b010, opc22, 1, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
831 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
832 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
835 let Inst{23} = addr{16}; // U (add = ('U' == 1))
836 let Inst{19-16} = addr{20-17}; // Rn
837 let Inst{15-12} = Rt;
838 let Inst{11-0} = addr{11-0}; // imm12
840 def rs : AIldst1<0b011, opc22, 1, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
841 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
842 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
845 let Inst{23} = shift{16}; // U (add = ('U' == 1))
846 let Inst{19-16} = shift{20-17}; // Rn
847 let Inst{11-0} = shift{11-0};
852 multiclass AI_str1<bit opc22, string opc, InstrItinClass iii,
853 InstrItinClass iir, PatFrag opnode> {
854 // Note: We use the complex addrmode_imm12 rather than just an input
855 // GPR and a constrained immediate so that we can use this to match
856 // frame index references and avoid matching constant pool references.
857 def i12 : AIldst1<0b010, opc22, 0, (outs),
858 (ins GPR:$Rt, addrmode_imm12:$addr),
859 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
860 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
863 let Inst{23} = addr{12}; // U (add = ('U' == 1))
864 let Inst{19-16} = addr{16-13}; // Rn
865 let Inst{15-12} = Rt;
866 let Inst{11-0} = addr{11-0}; // imm12
868 def rs : AIldst1<0b011, opc22, 0, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
869 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
870 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
873 let Inst{23} = shift{12}; // U (add = ('U' == 1))
874 let Inst{19-16} = shift{16-13}; // Rn
875 let Inst{11-0} = shift{11-0};
878 //===----------------------------------------------------------------------===//
880 //===----------------------------------------------------------------------===//
882 //===----------------------------------------------------------------------===//
883 // Miscellaneous Instructions.
886 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
887 /// the function. The first operand is the ID# for this instruction, the second
888 /// is the index into the MachineConstantPool that this is, the third is the
889 /// size in bytes of this constant pool entry.
890 let neverHasSideEffects = 1, isNotDuplicable = 1 in
891 def CONSTPOOL_ENTRY :
892 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
893 i32imm:$size), NoItinerary, "", []>;
895 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
896 // from removing one half of the matched pairs. That breaks PEI, which assumes
897 // these will always be in pairs, and asserts if it finds otherwise. Better way?
898 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
900 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary, "",
901 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
903 def ADJCALLSTACKDOWN :
904 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary, "",
905 [(ARMcallseq_start timm:$amt)]>;
908 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
909 [/* For disassembly only; pattern left blank */]>,
910 Requires<[IsARM, HasV6T2]> {
911 let Inst{27-16} = 0b001100100000;
912 let Inst{15-8} = 0b11110000;
913 let Inst{7-0} = 0b00000000;
916 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
917 [/* For disassembly only; pattern left blank */]>,
918 Requires<[IsARM, HasV6T2]> {
919 let Inst{27-16} = 0b001100100000;
920 let Inst{15-8} = 0b11110000;
921 let Inst{7-0} = 0b00000001;
924 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
925 [/* For disassembly only; pattern left blank */]>,
926 Requires<[IsARM, HasV6T2]> {
927 let Inst{27-16} = 0b001100100000;
928 let Inst{15-8} = 0b11110000;
929 let Inst{7-0} = 0b00000010;
932 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
933 [/* For disassembly only; pattern left blank */]>,
934 Requires<[IsARM, HasV6T2]> {
935 let Inst{27-16} = 0b001100100000;
936 let Inst{15-8} = 0b11110000;
937 let Inst{7-0} = 0b00000011;
940 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
942 [/* For disassembly only; pattern left blank */]>,
943 Requires<[IsARM, HasV6]> {
948 let Inst{15-12} = Rd;
949 let Inst{19-16} = Rn;
950 let Inst{27-20} = 0b01101000;
951 let Inst{7-4} = 0b1011;
952 let Inst{11-8} = 0b1111;
955 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
956 [/* For disassembly only; pattern left blank */]>,
957 Requires<[IsARM, HasV6T2]> {
958 let Inst{27-16} = 0b001100100000;
959 let Inst{15-8} = 0b11110000;
960 let Inst{7-0} = 0b00000100;
963 // The i32imm operand $val can be used by a debugger to store more information
964 // about the breakpoint.
965 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
966 [/* For disassembly only; pattern left blank */]>,
969 let Inst{3-0} = val{3-0};
970 let Inst{19-8} = val{15-4};
971 let Inst{27-20} = 0b00010010;
972 let Inst{7-4} = 0b0111;
975 // Change Processor State is a system instruction -- for disassembly only.
976 // The singleton $opt operand contains the following information:
977 // opt{4-0} = mode from Inst{4-0}
978 // opt{5} = changemode from Inst{17}
979 // opt{8-6} = AIF from Inst{8-6}
980 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
981 // FIXME: Integrated assembler will need these split out.
982 def CPS : AXI<(outs), (ins cps_opt:$opt), MiscFrm, NoItinerary, "cps$opt",
983 [/* For disassembly only; pattern left blank */]>,
985 let Inst{31-28} = 0b1111;
986 let Inst{27-20} = 0b00010000;
991 // Preload signals the memory system of possible future data/instruction access.
992 // These are for disassembly only.
994 // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
995 // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
996 multiclass APreLoad<bit data, bit read, string opc> {
998 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, NoItinerary,
999 !strconcat(opc, "\t$addr"), []> {
1002 let Inst{31-26} = 0b111101;
1003 let Inst{25} = 0; // 0 for immediate form
1004 let Inst{24} = data;
1005 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1006 let Inst{22} = read;
1007 let Inst{21-20} = 0b01;
1008 let Inst{19-16} = addr{16-13}; // Rn
1009 let Inst{15-12} = Rt;
1010 let Inst{11-0} = addr{11-0}; // imm12
1013 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, NoItinerary,
1014 !strconcat(opc, "\t$shift"), []> {
1017 let Inst{31-26} = 0b111101;
1018 let Inst{25} = 1; // 1 for register form
1019 let Inst{24} = data;
1020 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1021 let Inst{22} = read;
1022 let Inst{21-20} = 0b01;
1023 let Inst{19-16} = shift{16-13}; // Rn
1024 let Inst{11-0} = shift{11-0};
1028 defm PLD : APreLoad<1, 1, "pld">;
1029 defm PLDW : APreLoad<1, 0, "pldw">;
1030 defm PLI : APreLoad<0, 1, "pli">;
1032 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1034 [/* For disassembly only; pattern left blank */]>,
1037 let Inst{31-10} = 0b1111000100000001000000;
1042 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1043 [/* For disassembly only; pattern left blank */]>,
1044 Requires<[IsARM, HasV7]> {
1046 let Inst{27-4} = 0b001100100000111100001111;
1047 let Inst{3-0} = opt;
1050 // A5.4 Permanently UNDEFINED instructions.
1051 let isBarrier = 1, isTerminator = 1 in
1052 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1055 let Inst{27-25} = 0b011;
1056 let Inst{24-20} = 0b11111;
1057 let Inst{7-5} = 0b111;
1061 // Address computation and loads and stores in PIC mode.
1062 // FIXME: These PIC insn patterns are pseudos, but derive from the normal insn
1063 // classes (AXI1, et.al.) and so have encoding information and such,
1064 // which is suboptimal. Once the rest of the code emitter (including
1065 // JIT) is MC-ized we should look at refactoring these into true
1066 // pseudos. As is, the encoding information ends up being ignored,
1067 // as these instructions are lowered to individual MC-insts.
1068 let isNotDuplicable = 1 in {
1069 def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1070 Pseudo, IIC_iALUr, "",
1071 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1073 let AddedComplexity = 10 in {
1074 def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1075 Pseudo, IIC_iLoad_r, "",
1076 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1078 def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1079 Pseudo, IIC_iLoad_bh_r, "",
1080 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
1082 def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1083 Pseudo, IIC_iLoad_bh_r, "",
1084 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
1086 def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1087 Pseudo, IIC_iLoad_bh_r, "",
1088 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
1090 def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1091 Pseudo, IIC_iLoad_bh_r, "",
1092 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
1094 let AddedComplexity = 10 in {
1095 def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1096 Pseudo, IIC_iStore_r, "",
1097 [(store GPR:$src, addrmodepc:$addr)]>;
1099 def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1100 Pseudo, IIC_iStore_bh_r, "",
1101 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
1103 def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1104 Pseudo, IIC_iStore_bh_r, "",
1105 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1107 } // isNotDuplicable = 1
1110 // LEApcrel - Load a pc-relative address into a register without offending the
1112 // FIXME: These are marked as pseudos, but they're really not(?). They're just
1113 // the ADR instruction. Is this the right way to handle that? They need
1114 // encoding information regardless.
1115 let neverHasSideEffects = 1 in {
1116 let isReMaterializable = 1 in
1117 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
1119 "adr$p\t$dst, #$label", []>;
1121 } // neverHasSideEffects
1122 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
1123 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1125 "adr$p\t$dst, #${label}_${id}", []> {
1129 //===----------------------------------------------------------------------===//
1130 // Control Flow Instructions.
1133 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1135 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1136 "bx", "\tlr", [(ARMretflag)]>,
1137 Requires<[IsARM, HasV4T]> {
1138 let Inst{27-0} = 0b0001001011111111111100011110;
1142 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1143 "mov", "\tpc, lr", [(ARMretflag)]>,
1144 Requires<[IsARM, NoV4T]> {
1145 let Inst{27-0} = 0b0001101000001111000000001110;
1149 // Indirect branches
1150 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1152 def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1153 [(brind GPR:$dst)]>,
1154 Requires<[IsARM, HasV4T]> {
1156 let Inst{31-4} = 0b1110000100101111111111110001;
1157 let Inst{3-0} = dst;
1161 def MOVPCRX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "mov\tpc, $dst",
1162 [(brind GPR:$dst)]>,
1163 Requires<[IsARM, NoV4T]> {
1165 let Inst{31-4} = 0b1110000110100000111100000000;
1166 let Inst{3-0} = dst;
1170 // FIXME: remove when we have a way to marking a MI with these properties.
1171 // FIXME: Should pc be an implicit operand like PICADD, etc?
1172 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1173 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1174 def LDM_RET : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1175 reglist:$dsts, variable_ops),
1176 IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr,
1177 "ldm${addr:submode}${p}\t$addr!, $dsts",
1178 "$addr.addr = $wb", []>;
1180 // On non-Darwin platforms R9 is callee-saved.
1182 Defs = [R0, R1, R2, R3, R12, LR,
1183 D0, D1, D2, D3, D4, D5, D6, D7,
1184 D16, D17, D18, D19, D20, D21, D22, D23,
1185 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
1186 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
1187 IIC_Br, "bl\t$func",
1188 [(ARMcall tglobaladdr:$func)]>,
1189 Requires<[IsARM, IsNotDarwin]> {
1190 let Inst{31-28} = 0b1110;
1191 // FIXME: Encoding info for $func. Needs fixups bits.
1194 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
1195 IIC_Br, "bl", "\t$func",
1196 [(ARMcall_pred tglobaladdr:$func)]>,
1197 Requires<[IsARM, IsNotDarwin]>;
1200 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1201 IIC_Br, "blx\t$func",
1202 [(ARMcall GPR:$func)]>,
1203 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1205 let Inst{27-4} = 0b000100101111111111110011;
1206 let Inst{3-0} = func;
1210 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1211 def BX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1212 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
1213 [(ARMcall_nolink tGPR:$func)]>,
1214 Requires<[IsARM, HasV4T, IsNotDarwin]> {
1216 let Inst{27-4} = 0b000100101111111111110001;
1217 let Inst{3-0} = func;
1221 def BMOVPCRX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1222 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
1223 [(ARMcall_nolink tGPR:$func)]>,
1224 Requires<[IsARM, NoV4T, IsNotDarwin]> {
1226 let Inst{27-4} = 0b000110100000111100000000;
1227 let Inst{3-0} = func;
1231 // On Darwin R9 is call-clobbered.
1233 Defs = [R0, R1, R2, R3, R9, R12, LR,
1234 D0, D1, D2, D3, D4, D5, D6, D7,
1235 D16, D17, D18, D19, D20, D21, D22, D23,
1236 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
1237 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
1238 IIC_Br, "bl\t$func",
1239 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
1240 let Inst{31-28} = 0b1110;
1241 // FIXME: Encoding info for $func. Needs fixups bits.
1244 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
1245 IIC_Br, "bl", "\t$func",
1246 [(ARMcall_pred tglobaladdr:$func)]>,
1247 Requires<[IsARM, IsDarwin]>;
1250 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1251 IIC_Br, "blx\t$func",
1252 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
1254 let Inst{27-4} = 0b000100101111111111110011;
1255 let Inst{3-0} = func;
1259 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1260 def BXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1261 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
1262 [(ARMcall_nolink tGPR:$func)]>,
1263 Requires<[IsARM, HasV4T, IsDarwin]> {
1265 let Inst{27-4} = 0b000100101111111111110001;
1266 let Inst{3-0} = func;
1270 def BMOVPCRXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1271 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
1272 [(ARMcall_nolink tGPR:$func)]>,
1273 Requires<[IsARM, NoV4T, IsDarwin]> {
1275 let Inst{27-4} = 0b000110100000111100000000;
1276 let Inst{3-0} = func;
1282 // FIXME: These should probably be xformed into the non-TC versions of the
1283 // instructions as part of MC lowering.
1284 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1286 let Defs = [R0, R1, R2, R3, R9, R12,
1287 D0, D1, D2, D3, D4, D5, D6, D7,
1288 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1289 D27, D28, D29, D30, D31, PC],
1291 def TCRETURNdi : AInoP<(outs), (ins i32imm:$dst, variable_ops),
1293 "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
1295 def TCRETURNri : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
1297 "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
1299 def TAILJMPd : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1300 IIC_Br, "b\t$dst @ TAILCALL",
1301 []>, Requires<[IsDarwin]>;
1303 def TAILJMPdt: ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1304 IIC_Br, "b.w\t$dst @ TAILCALL",
1305 []>, Requires<[IsDarwin]>;
1307 def TAILJMPr : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1308 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1309 []>, Requires<[IsDarwin]> {
1311 let Inst{31-4} = 0b1110000100101111111111110001;
1312 let Inst{3-0} = dst;
1316 // Non-Darwin versions (the difference is R9).
1317 let Defs = [R0, R1, R2, R3, R12,
1318 D0, D1, D2, D3, D4, D5, D6, D7,
1319 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1320 D27, D28, D29, D30, D31, PC],
1322 def TCRETURNdiND : AInoP<(outs), (ins i32imm:$dst, variable_ops),
1324 "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
1326 def TCRETURNriND : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
1328 "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
1330 def TAILJMPdND : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1331 IIC_Br, "b\t$dst @ TAILCALL",
1332 []>, Requires<[IsARM, IsNotDarwin]>;
1334 def TAILJMPdNDt : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1335 IIC_Br, "b.w\t$dst @ TAILCALL",
1336 []>, Requires<[IsThumb, IsNotDarwin]>;
1338 def TAILJMPrND : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1339 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1340 []>, Requires<[IsNotDarwin]> {
1342 let Inst{31-4} = 0b1110000100101111111111110001;
1343 let Inst{3-0} = dst;
1348 let isBranch = 1, isTerminator = 1 in {
1349 // B is "predicable" since it can be xformed into a Bcc.
1350 let isBarrier = 1 in {
1351 let isPredicable = 1 in
1352 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
1353 "b\t$target", [(br bb:$target)]>;
1355 let isNotDuplicable = 1, isIndirectBranch = 1,
1356 // FIXME: $imm field is not specified by asm string. Mark as cgonly.
1357 isCodeGenOnly = 1 in {
1358 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
1359 IIC_Br, "mov\tpc, $target$jt",
1360 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
1361 let Inst{11-4} = 0b00000000;
1362 let Inst{15-12} = 0b1111;
1363 let Inst{20} = 0; // S Bit
1364 let Inst{24-21} = 0b1101;
1365 let Inst{27-25} = 0b000;
1367 def BR_JTm : JTI<(outs),
1368 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
1369 IIC_Br, "ldr\tpc, $target$jt",
1370 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1372 let Inst{15-12} = 0b1111;
1373 let Inst{20} = 1; // L bit
1374 let Inst{21} = 0; // W bit
1375 let Inst{22} = 0; // B bit
1376 let Inst{24} = 1; // P bit
1377 let Inst{27-25} = 0b011;
1379 def BR_JTadd : JTI<(outs),
1380 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
1381 IIC_Br, "add\tpc, $target, $idx$jt",
1382 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1384 let Inst{15-12} = 0b1111;
1385 let Inst{20} = 0; // S bit
1386 let Inst{24-21} = 0b0100;
1387 let Inst{27-25} = 0b000;
1389 } // isNotDuplicable = 1, isIndirectBranch = 1
1392 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1393 // a two-value operand where a dag node expects two operands. :(
1394 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
1395 IIC_Br, "b", "\t$target",
1396 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
1399 // Branch and Exchange Jazelle -- for disassembly only
1400 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1401 [/* For disassembly only; pattern left blank */]> {
1402 let Inst{23-20} = 0b0010;
1403 //let Inst{19-8} = 0xfff;
1404 let Inst{7-4} = 0b0010;
1407 // Secure Monitor Call is a system instruction -- for disassembly only
1408 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1409 [/* For disassembly only; pattern left blank */]> {
1411 let Inst{23-4} = 0b01100000000000000111;
1412 let Inst{3-0} = opt;
1415 // Supervisor Call (Software Interrupt) -- for disassembly only
1417 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1418 [/* For disassembly only; pattern left blank */]> {
1420 let Inst{23-0} = svc;
1424 // Store Return State is a system instruction -- for disassembly only
1425 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1426 def SRSW : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, i32imm:$mode),
1427 NoItinerary, "srs${addr:submode}\tsp!, $mode",
1428 [/* For disassembly only; pattern left blank */]> {
1429 let Inst{31-28} = 0b1111;
1430 let Inst{22-20} = 0b110; // W = 1
1433 def SRS : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, i32imm:$mode),
1434 NoItinerary, "srs${addr:submode}\tsp, $mode",
1435 [/* For disassembly only; pattern left blank */]> {
1436 let Inst{31-28} = 0b1111;
1437 let Inst{22-20} = 0b100; // W = 0
1440 // Return From Exception is a system instruction -- for disassembly only
1441 def RFEW : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, GPR:$base),
1442 NoItinerary, "rfe${addr:submode}\t$base!",
1443 [/* For disassembly only; pattern left blank */]> {
1444 let Inst{31-28} = 0b1111;
1445 let Inst{22-20} = 0b011; // W = 1
1448 def RFE : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, GPR:$base),
1449 NoItinerary, "rfe${addr:submode}\t$base",
1450 [/* For disassembly only; pattern left blank */]> {
1451 let Inst{31-28} = 0b1111;
1452 let Inst{22-20} = 0b001; // W = 0
1454 } // isCodeGenOnly = 1
1456 //===----------------------------------------------------------------------===//
1457 // Load / store Instructions.
1463 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1464 UnOpFrag<(load node:$Src)>>;
1465 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1466 UnOpFrag<(zextloadi8 node:$Src)>>;
1467 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1468 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1469 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1470 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1472 // Special LDR for loads from non-pc-relative constpools.
1473 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1474 isReMaterializable = 1 in
1475 def LDRcp : AIldst1<0b010, 0, 1, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1476 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr", []> {
1479 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1480 let Inst{19-16} = 0b1111;
1481 let Inst{15-12} = Rt;
1482 let Inst{11-0} = addr{11-0}; // imm12
1485 // Loads with zero extension
1486 def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1487 IIC_iLoad_bh_r, "ldrh", "\t$dst, $addr",
1488 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
1490 // Loads with sign extension
1491 def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1492 IIC_iLoad_bh_r, "ldrsh", "\t$dst, $addr",
1493 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
1495 def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1496 IIC_iLoad_bh_r, "ldrsb", "\t$dst, $addr",
1497 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
1499 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
1500 isCodeGenOnly = 1 in { // $dst2 doesn't exist in asmstring?
1502 def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
1503 IIC_iLoad_d_r, "ldrd", "\t$dst1, $addr",
1504 []>, Requires<[IsARM, HasV5TE]>;
1507 def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
1508 (ins addrmode2:$addr), LdFrm, IIC_iLoad_ru,
1509 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1511 def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
1512 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoad_ru,
1513 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1515 def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
1516 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru,
1517 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1519 def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
1520 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1521 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1523 def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
1524 (ins addrmode2:$addr), LdFrm, IIC_iLoad_bh_ru,
1525 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1527 def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
1528 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru,
1529 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1531 def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
1532 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru,
1533 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1535 def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
1536 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1537 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1539 def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
1540 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru,
1541 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1543 def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
1544 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_ru,
1545 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1547 // For disassembly only
1548 def LDRD_PRE : AI3lddpr<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
1549 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_d_ru,
1550 "ldrd", "\t$dst1, $dst2, $addr!", "$addr.base = $base_wb", []>,
1551 Requires<[IsARM, HasV5TE]>;
1553 // For disassembly only
1554 def LDRD_POST : AI3lddpo<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
1555 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_d_ru,
1556 "ldrd", "\t$dst1, $dst2, [$base], $offset", "$base = $base_wb", []>,
1557 Requires<[IsARM, HasV5TE]>;
1559 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1561 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1563 def LDRT : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
1564 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoad_ru,
1565 "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1566 let Inst{21} = 1; // overwrite
1569 def LDRBT : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
1570 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru,
1571 "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1572 let Inst{21} = 1; // overwrite
1575 def LDRSBT : AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
1576 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1577 "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1578 let Inst{21} = 1; // overwrite
1581 def LDRHT : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
1582 (ins GPR:$base, am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1583 "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1584 let Inst{21} = 1; // overwrite
1587 def LDRSHT : AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
1588 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1589 "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1590 let Inst{21} = 1; // overwrite
1595 // Stores with truncate
1596 def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm,
1597 IIC_iStore_bh_r, "strh", "\t$src, $addr",
1598 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
1601 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
1602 isCodeGenOnly = 1 in // $src2 doesn't exist in asm string
1603 def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
1604 StMiscFrm, IIC_iStore_d_r,
1605 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
1608 def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
1609 (ins GPR:$src, GPR:$base, am2offset:$offset),
1610 StFrm, IIC_iStore_ru,
1611 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
1613 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
1615 def STR_POST : AI2stwpo<(outs GPR:$base_wb),
1616 (ins GPR:$src, GPR:$base,am2offset:$offset),
1617 StFrm, IIC_iStore_ru,
1618 "str", "\t$src, [$base], $offset", "$base = $base_wb",
1620 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
1622 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
1623 (ins GPR:$src, GPR:$base,am3offset:$offset),
1624 StMiscFrm, IIC_iStore_ru,
1625 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
1627 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
1629 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
1630 (ins GPR:$src, GPR:$base,am3offset:$offset),
1631 StMiscFrm, IIC_iStore_bh_ru,
1632 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
1633 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
1634 GPR:$base, am3offset:$offset))]>;
1636 def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
1637 (ins GPR:$src, GPR:$base,am2offset:$offset),
1638 StFrm, IIC_iStore_bh_ru,
1639 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
1640 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
1641 GPR:$base, am2offset:$offset))]>;
1643 def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
1644 (ins GPR:$src, GPR:$base,am2offset:$offset),
1645 StFrm, IIC_iStore_bh_ru,
1646 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
1647 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
1648 GPR:$base, am2offset:$offset))]>;
1650 // For disassembly only
1651 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1652 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1653 StMiscFrm, IIC_iStore_d_ru,
1654 "strd", "\t$src1, $src2, [$base, $offset]!",
1655 "$base = $base_wb", []>;
1657 // For disassembly only
1658 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1659 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1660 StMiscFrm, IIC_iStore_d_ru,
1661 "strd", "\t$src1, $src2, [$base], $offset",
1662 "$base = $base_wb", []>;
1664 // STRT, STRBT, and STRHT are for disassembly only.
1666 def STRT : AI2stwpo<(outs GPR:$base_wb),
1667 (ins GPR:$src, GPR:$base,am2offset:$offset),
1668 StFrm, IIC_iStore_ru,
1669 "strt", "\t$src, [$base], $offset", "$base = $base_wb",
1670 [/* For disassembly only; pattern left blank */]> {
1671 let Inst{21} = 1; // overwrite
1674 def STRBT : AI2stbpo<(outs GPR:$base_wb),
1675 (ins GPR:$src, GPR:$base,am2offset:$offset),
1676 StFrm, IIC_iStore_bh_ru,
1677 "strbt", "\t$src, [$base], $offset", "$base = $base_wb",
1678 [/* For disassembly only; pattern left blank */]> {
1679 let Inst{21} = 1; // overwrite
1682 def STRHT: AI3sthpo<(outs GPR:$base_wb),
1683 (ins GPR:$src, GPR:$base,am3offset:$offset),
1684 StMiscFrm, IIC_iStore_bh_ru,
1685 "strht", "\t$src, [$base], $offset", "$base = $base_wb",
1686 [/* For disassembly only; pattern left blank */]> {
1687 let Inst{21} = 1; // overwrite
1690 //===----------------------------------------------------------------------===//
1691 // Load / store multiple Instructions.
1694 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
1695 isCodeGenOnly = 1 in {
1696 def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p,
1697 reglist:$dsts, variable_ops),
1698 IndexModeNone, LdStMulFrm, IIC_iLoad_m,
1699 "ldm${addr:submode}${p}\t$addr, $dsts", "", []>;
1701 def LDM_UPD : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1702 reglist:$dsts, variable_ops),
1703 IndexModeUpd, LdStMulFrm, IIC_iLoad_mu,
1704 "ldm${addr:submode}${p}\t$addr!, $dsts",
1705 "$addr.addr = $wb", []>;
1706 } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
1708 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
1709 isCodeGenOnly = 1 in {
1710 def STM : AXI4st<(outs), (ins addrmode4:$addr, pred:$p,
1711 reglist:$srcs, variable_ops),
1712 IndexModeNone, LdStMulFrm, IIC_iStore_m,
1713 "stm${addr:submode}${p}\t$addr, $srcs", "", []>;
1715 def STM_UPD : AXI4st<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1716 reglist:$srcs, variable_ops),
1717 IndexModeUpd, LdStMulFrm, IIC_iStore_mu,
1718 "stm${addr:submode}${p}\t$addr!, $srcs",
1719 "$addr.addr = $wb", []>;
1720 } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
1722 //===----------------------------------------------------------------------===//
1723 // Move Instructions.
1726 let neverHasSideEffects = 1 in
1727 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
1728 "mov", "\t$Rd, $Rm", []>, UnaryDP {
1732 let Inst{11-4} = 0b00000000;
1735 let Inst{15-12} = Rd;
1738 // A version for the smaller set of tail call registers.
1739 let neverHasSideEffects = 1 in
1740 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
1741 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
1745 let Inst{11-4} = 0b00000000;
1748 let Inst{15-12} = Rd;
1751 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
1752 DPSoRegFrm, IIC_iMOVsr,
1753 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
1757 let Inst{15-12} = Rd;
1758 let Inst{11-0} = src;
1762 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1763 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
1764 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
1768 let Inst{15-12} = Rd;
1769 let Inst{19-16} = 0b0000;
1770 let Inst{11-0} = imm;
1773 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1774 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins i32imm:$imm),
1776 "movw", "\t$Rd, $imm",
1777 [(set GPR:$Rd, imm0_65535:$imm)]>,
1778 Requires<[IsARM, HasV6T2]>, UnaryDP {
1781 let Inst{15-12} = Rd;
1782 let Inst{11-0} = imm{11-0};
1783 let Inst{19-16} = imm{15-12};
1788 let Constraints = "$src = $Rd" in
1789 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, i32imm:$imm),
1791 "movt", "\t$Rd, $imm",
1793 (or (and GPR:$src, 0xffff),
1794 lo16AllZero:$imm))]>, UnaryDP,
1795 Requires<[IsARM, HasV6T2]> {
1798 let Inst{15-12} = Rd;
1799 let Inst{11-0} = imm{11-0};
1800 let Inst{19-16} = imm{15-12};
1805 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
1806 Requires<[IsARM, HasV6T2]>;
1808 let Uses = [CPSR] in
1809 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi, "",
1810 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
1813 // These aren't really mov instructions, but we have to define them this way
1814 // due to flag operands.
1816 let Defs = [CPSR] in {
1817 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, "",
1818 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
1820 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, "",
1821 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
1825 //===----------------------------------------------------------------------===//
1826 // Extend Instructions.
1831 defm SXTB : AI_ext_rrot<0b01101010,
1832 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
1833 defm SXTH : AI_ext_rrot<0b01101011,
1834 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
1836 defm SXTAB : AI_exta_rrot<0b01101010,
1837 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1838 defm SXTAH : AI_exta_rrot<0b01101011,
1839 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1841 // For disassembly only
1842 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
1844 // For disassembly only
1845 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
1849 let AddedComplexity = 16 in {
1850 defm UXTB : AI_ext_rrot<0b01101110,
1851 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
1852 defm UXTH : AI_ext_rrot<0b01101111,
1853 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1854 defm UXTB16 : AI_ext_rrot<0b01101100,
1855 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1857 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1858 // The transformation should probably be done as a combiner action
1859 // instead so we can include a check for masking back in the upper
1860 // eight bits of the source into the lower eight bits of the result.
1861 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1862 // (UXTB16r_rot GPR:$Src, 24)>;
1863 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1864 (UXTB16r_rot GPR:$Src, 8)>;
1866 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
1867 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1868 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
1869 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1872 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
1873 // For disassembly only
1874 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
1877 def SBFX : I<(outs GPR:$Rd),
1878 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
1879 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
1880 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
1881 Requires<[IsARM, HasV6T2]> {
1886 let Inst{27-21} = 0b0111101;
1887 let Inst{6-4} = 0b101;
1888 let Inst{20-16} = width;
1889 let Inst{15-12} = Rd;
1890 let Inst{11-7} = lsb;
1894 def UBFX : I<(outs GPR:$Rd),
1895 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
1896 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
1897 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
1898 Requires<[IsARM, HasV6T2]> {
1903 let Inst{27-21} = 0b0111111;
1904 let Inst{6-4} = 0b101;
1905 let Inst{20-16} = width;
1906 let Inst{15-12} = Rd;
1907 let Inst{11-7} = lsb;
1911 //===----------------------------------------------------------------------===//
1912 // Arithmetic Instructions.
1915 defm ADD : AsI1_bin_irs<0b0100, "add",
1916 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
1917 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1918 defm SUB : AsI1_bin_irs<0b0010, "sub",
1919 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
1920 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1922 // ADD and SUB with 's' bit set.
1923 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
1924 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
1925 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1926 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
1927 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
1928 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1930 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
1931 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1932 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
1933 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1934 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
1935 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
1936 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
1937 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
1939 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1940 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
1941 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
1946 let Inst{15-12} = Rd;
1947 let Inst{19-16} = Rn;
1948 let Inst{11-0} = imm;
1951 // The reg/reg form is only defined for the disassembler; for codegen it is
1952 // equivalent to SUBrr.
1953 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1954 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
1955 [/* For disassembly only; pattern left blank */]> {
1959 let Inst{11-4} = 0b00000000;
1962 let Inst{15-12} = Rd;
1963 let Inst{19-16} = Rn;
1966 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
1967 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
1968 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
1973 let Inst{11-0} = shift;
1974 let Inst{15-12} = Rd;
1975 let Inst{19-16} = Rn;
1978 // RSB with 's' bit set.
1979 let Defs = [CPSR] in {
1980 def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1981 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
1982 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
1988 let Inst{15-12} = Rd;
1989 let Inst{19-16} = Rn;
1990 let Inst{11-0} = imm;
1992 def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
1993 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
1994 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
2000 let Inst{11-0} = shift;
2001 let Inst{15-12} = Rd;
2002 let Inst{19-16} = Rn;
2006 let Uses = [CPSR] in {
2007 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2008 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2009 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2015 let Inst{15-12} = Rd;
2016 let Inst{19-16} = Rn;
2017 let Inst{11-0} = imm;
2019 // The reg/reg form is only defined for the disassembler; for codegen it is
2020 // equivalent to SUBrr.
2021 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2022 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2023 [/* For disassembly only; pattern left blank */]> {
2027 let Inst{11-4} = 0b00000000;
2030 let Inst{15-12} = Rd;
2031 let Inst{19-16} = Rn;
2033 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2034 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2035 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2041 let Inst{11-0} = shift;
2042 let Inst{15-12} = Rd;
2043 let Inst{19-16} = Rn;
2047 // FIXME: Allow these to be predicated.
2048 let Defs = [CPSR], Uses = [CPSR] in {
2049 def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2050 DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
2051 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2058 let Inst{15-12} = Rd;
2059 let Inst{19-16} = Rn;
2060 let Inst{11-0} = imm;
2062 def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2063 DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
2064 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2071 let Inst{11-0} = shift;
2072 let Inst{15-12} = Rd;
2073 let Inst{19-16} = Rn;
2077 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2078 // The assume-no-carry-in form uses the negation of the input since add/sub
2079 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2080 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2082 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2083 (SUBri GPR:$src, so_imm_neg:$imm)>;
2084 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2085 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2086 // The with-carry-in form matches bitwise not instead of the negation.
2087 // Effectively, the inverse interpretation of the carry flag already accounts
2088 // for part of the negation.
2089 def : ARMPat<(adde GPR:$src, so_imm_not:$imm),
2090 (SBCri GPR:$src, so_imm_not:$imm)>;
2092 // Note: These are implemented in C++ code, because they have to generate
2093 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2095 // (mul X, 2^n+1) -> (add (X << n), X)
2096 // (mul X, 2^n-1) -> (rsb X, (X << n))
2098 // ARM Arithmetic Instruction -- for disassembly only
2099 // GPR:$dst = GPR:$a op GPR:$b
2100 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2101 list<dag> pattern = [/* For disassembly only; pattern left blank */]>
2102 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iALUr,
2103 opc, "\t$Rd, $Rn, $Rm", pattern> {
2107 let Inst{27-20} = op27_20;
2108 let Inst{11-4} = op11_4;
2109 let Inst{19-16} = Rn;
2110 let Inst{15-12} = Rd;
2114 // Saturating add/subtract -- for disassembly only
2116 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2117 [(set GPR:$Rd, (int_arm_qadd GPR:$Rn, GPR:$Rm))]>;
2118 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2119 [(set GPR:$Rd, (int_arm_qsub GPR:$Rn, GPR:$Rm))]>;
2120 def QDADD : AAI<0b00010100, 0b00000101, "qdadd">;
2121 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub">;
2123 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2124 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2125 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2126 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2127 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2128 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2129 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2130 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2131 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2132 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2133 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2134 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2136 // Signed/Unsigned add/subtract -- for disassembly only
2138 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2139 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2140 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2141 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2142 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2143 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2144 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2145 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2146 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2147 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2148 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2149 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2151 // Signed/Unsigned halving add/subtract -- for disassembly only
2153 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2154 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2155 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2156 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2157 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2158 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2159 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2160 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2161 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2162 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2163 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2164 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2166 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2168 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2169 MulFrm /* for convenience */, NoItinerary, "usad8",
2170 "\t$Rd, $Rn, $Rm", []>,
2171 Requires<[IsARM, HasV6]> {
2175 let Inst{27-20} = 0b01111000;
2176 let Inst{15-12} = 0b1111;
2177 let Inst{7-4} = 0b0001;
2178 let Inst{19-16} = Rd;
2179 let Inst{11-8} = Rm;
2182 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2183 MulFrm /* for convenience */, NoItinerary, "usada8",
2184 "\t$Rd, $Rn, $Rm, $Ra", []>,
2185 Requires<[IsARM, HasV6]> {
2190 let Inst{27-20} = 0b01111000;
2191 let Inst{7-4} = 0b0001;
2192 let Inst{19-16} = Rd;
2193 let Inst{15-12} = Ra;
2194 let Inst{11-8} = Rm;
2198 // Signed/Unsigned saturate -- for disassembly only
2200 def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2201 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2202 [/* For disassembly only; pattern left blank */]> {
2207 let Inst{27-21} = 0b0110101;
2208 let Inst{5-4} = 0b01;
2209 let Inst{20-16} = sat_imm;
2210 let Inst{15-12} = Rd;
2211 let Inst{11-7} = sh{7-3};
2212 let Inst{6} = sh{0};
2216 def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm,
2217 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2218 [/* For disassembly only; pattern left blank */]> {
2222 let Inst{27-20} = 0b01101010;
2223 let Inst{11-4} = 0b11110011;
2224 let Inst{15-12} = Rd;
2225 let Inst{19-16} = sat_imm;
2229 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2230 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2231 [/* For disassembly only; pattern left blank */]> {
2236 let Inst{27-21} = 0b0110111;
2237 let Inst{5-4} = 0b01;
2238 let Inst{15-12} = Rd;
2239 let Inst{11-7} = sh{7-3};
2240 let Inst{6} = sh{0};
2241 let Inst{20-16} = sat_imm;
2245 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2246 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2247 [/* For disassembly only; pattern left blank */]> {
2251 let Inst{27-20} = 0b01101110;
2252 let Inst{11-4} = 0b11110011;
2253 let Inst{15-12} = Rd;
2254 let Inst{19-16} = sat_imm;
2258 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2259 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2261 //===----------------------------------------------------------------------===//
2262 // Bitwise Instructions.
2265 defm AND : AsI1_bin_irs<0b0000, "and",
2266 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2267 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2268 defm ORR : AsI1_bin_irs<0b1100, "orr",
2269 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2270 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2271 defm EOR : AsI1_bin_irs<0b0001, "eor",
2272 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2273 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2274 defm BIC : AsI1_bin_irs<0b1110, "bic",
2275 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2276 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2278 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2279 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2280 "bfc", "\t$Rd, $imm", "$src = $Rd",
2281 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2282 Requires<[IsARM, HasV6T2]> {
2285 let Inst{27-21} = 0b0111110;
2286 let Inst{6-0} = 0b0011111;
2287 let Inst{15-12} = Rd;
2288 let Inst{11-7} = imm{4-0}; // lsb
2289 let Inst{20-16} = imm{9-5}; // width
2292 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2293 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2294 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2295 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2296 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2297 bf_inv_mask_imm:$imm))]>,
2298 Requires<[IsARM, HasV6T2]> {
2302 let Inst{27-21} = 0b0111110;
2303 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2304 let Inst{15-12} = Rd;
2305 let Inst{11-7} = imm{4-0}; // lsb
2306 let Inst{20-16} = imm{9-5}; // width
2310 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2311 "mvn", "\t$Rd, $Rm",
2312 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2316 let Inst{19-16} = 0b0000;
2317 let Inst{11-4} = 0b00000000;
2318 let Inst{15-12} = Rd;
2321 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2322 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2323 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2328 let Inst{19-16} = 0b0000;
2329 let Inst{15-12} = Rd;
2330 let Inst{11-0} = shift;
2332 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
2333 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2334 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2335 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2340 let Inst{19-16} = 0b0000;
2341 let Inst{15-12} = Rd;
2342 let Inst{11-0} = imm;
2345 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2346 (BICri GPR:$src, so_imm_not:$imm)>;
2348 //===----------------------------------------------------------------------===//
2349 // Multiply Instructions.
2351 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2352 string opc, string asm, list<dag> pattern>
2353 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2357 let Inst{19-16} = Rd;
2358 let Inst{11-8} = Rm;
2361 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2362 string opc, string asm, list<dag> pattern>
2363 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2368 let Inst{19-16} = RdHi;
2369 let Inst{15-12} = RdLo;
2370 let Inst{11-8} = Rm;
2374 let isCommutable = 1 in
2375 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2376 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2377 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>;
2379 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2380 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2381 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]> {
2383 let Inst{15-12} = Ra;
2386 def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
2387 IIC_iMAC32, "mls", "\t$dst, $a, $b, $c",
2388 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
2389 Requires<[IsARM, HasV6T2]> {
2393 let Inst{19-16} = Rd;
2394 let Inst{11-8} = Rm;
2398 // Extra precision multiplies with low / high results
2400 let neverHasSideEffects = 1 in {
2401 let isCommutable = 1 in {
2402 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2403 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2404 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2406 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2407 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2408 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2411 // Multiply + accumulate
2412 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2413 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2414 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2416 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2417 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2418 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2420 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2421 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2422 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2423 Requires<[IsARM, HasV6]> {
2428 let Inst{19-16} = RdLo;
2429 let Inst{15-12} = RdHi;
2430 let Inst{11-8} = Rm;
2433 } // neverHasSideEffects
2435 // Most significant word multiply
2436 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2437 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2438 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2439 Requires<[IsARM, HasV6]> {
2440 let Inst{15-12} = 0b1111;
2443 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2444 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2445 [/* For disassembly only; pattern left blank */]>,
2446 Requires<[IsARM, HasV6]> {
2447 let Inst{15-12} = 0b1111;
2450 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2451 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2452 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2453 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2454 Requires<[IsARM, HasV6]>;
2456 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2457 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2458 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2459 [/* For disassembly only; pattern left blank */]>,
2460 Requires<[IsARM, HasV6]>;
2462 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2463 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2464 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2465 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2466 Requires<[IsARM, HasV6]>;
2468 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2469 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2470 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2471 [/* For disassembly only; pattern left blank */]>,
2472 Requires<[IsARM, HasV6]>;
2474 multiclass AI_smul<string opc, PatFrag opnode> {
2475 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2476 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2477 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2478 (sext_inreg GPR:$Rm, i16)))]>,
2479 Requires<[IsARM, HasV5TE]>;
2481 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2482 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2483 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2484 (sra GPR:$Rm, (i32 16))))]>,
2485 Requires<[IsARM, HasV5TE]>;
2487 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2488 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2489 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2490 (sext_inreg GPR:$Rm, i16)))]>,
2491 Requires<[IsARM, HasV5TE]>;
2493 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2494 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2495 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2496 (sra GPR:$Rm, (i32 16))))]>,
2497 Requires<[IsARM, HasV5TE]>;
2499 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2500 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2501 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2502 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2503 Requires<[IsARM, HasV5TE]>;
2505 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2506 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2507 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2508 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2509 Requires<[IsARM, HasV5TE]>;
2513 multiclass AI_smla<string opc, PatFrag opnode> {
2514 def BB : AMulxyI<0b0001000, 0b00, (outs GPR:$Rd),
2515 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2516 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2517 [(set GPR:$Rd, (add GPR:$Ra,
2518 (opnode (sext_inreg GPR:$Rn, i16),
2519 (sext_inreg GPR:$Rm, i16))))]>,
2520 Requires<[IsARM, HasV5TE]>;
2522 def BT : AMulxyI<0b0001000, 0b10, (outs GPR:$Rd),
2523 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2524 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2525 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2526 (sra GPR:$Rm, (i32 16)))))]>,
2527 Requires<[IsARM, HasV5TE]>;
2529 def TB : AMulxyI<0b0001000, 0b01, (outs GPR:$Rd),
2530 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2531 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2532 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2533 (sext_inreg GPR:$Rm, i16))))]>,
2534 Requires<[IsARM, HasV5TE]>;
2536 def TT : AMulxyI<0b0001000, 0b11, (outs GPR:$Rd),
2537 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2538 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2539 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2540 (sra GPR:$Rm, (i32 16)))))]>,
2541 Requires<[IsARM, HasV5TE]>;
2543 def WB : AMulxyI<0b0001001, 0b00, (outs GPR:$Rd),
2544 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2545 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2546 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2547 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2548 Requires<[IsARM, HasV5TE]>;
2550 def WT : AMulxyI<0b0001001, 0b10, (outs GPR:$Rd),
2551 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2552 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2553 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2554 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2555 Requires<[IsARM, HasV5TE]>;
2558 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2559 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2561 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2562 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2563 (ins GPR:$Rn, GPR:$Rm),
2564 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2565 [/* For disassembly only; pattern left blank */]>,
2566 Requires<[IsARM, HasV5TE]>;
2568 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2569 (ins GPR:$Rn, GPR:$Rm),
2570 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2571 [/* For disassembly only; pattern left blank */]>,
2572 Requires<[IsARM, HasV5TE]>;
2574 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2575 (ins GPR:$Rn, GPR:$Rm),
2576 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2577 [/* For disassembly only; pattern left blank */]>,
2578 Requires<[IsARM, HasV5TE]>;
2580 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2581 (ins GPR:$Rn, GPR:$Rm),
2582 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2583 [/* For disassembly only; pattern left blank */]>,
2584 Requires<[IsARM, HasV5TE]>;
2586 // Helper class for AI_smld -- for disassembly only
2587 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2588 InstrItinClass itin, string opc, string asm>
2589 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2596 let Inst{21-20} = 0b00;
2597 let Inst{22} = long;
2598 let Inst{27-23} = 0b01110;
2599 let Inst{11-8} = Rm;
2602 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2603 InstrItinClass itin, string opc, string asm>
2604 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2606 let Inst{15-12} = 0b1111;
2607 let Inst{19-16} = Rd;
2609 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2610 InstrItinClass itin, string opc, string asm>
2611 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2613 let Inst{15-12} = Ra;
2615 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2616 InstrItinClass itin, string opc, string asm>
2617 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2620 let Inst{19-16} = RdHi;
2621 let Inst{15-12} = RdLo;
2624 multiclass AI_smld<bit sub, string opc> {
2626 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2627 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
2629 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2630 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
2632 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
2633 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2634 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
2636 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
2637 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2638 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
2642 defm SMLA : AI_smld<0, "smla">;
2643 defm SMLS : AI_smld<1, "smls">;
2645 multiclass AI_sdml<bit sub, string opc> {
2647 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2648 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
2649 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2650 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
2653 defm SMUA : AI_sdml<0, "smua">;
2654 defm SMUS : AI_sdml<1, "smus">;
2656 //===----------------------------------------------------------------------===//
2657 // Misc. Arithmetic Instructions.
2660 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
2661 IIC_iUNAr, "clz", "\t$Rd, $Rm",
2662 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
2664 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2665 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
2666 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
2667 Requires<[IsARM, HasV6T2]>;
2669 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2670 IIC_iUNAr, "rev", "\t$Rd, $Rm",
2671 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
2673 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2674 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
2676 (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
2677 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
2678 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
2679 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
2680 Requires<[IsARM, HasV6]>;
2682 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2683 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
2686 (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
2687 (shl GPR:$Rm, (i32 8))), i16))]>,
2688 Requires<[IsARM, HasV6]>;
2690 def lsl_shift_imm : SDNodeXForm<imm, [{
2691 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
2692 return CurDAG->getTargetConstant(Sh, MVT::i32);
2695 def lsl_amt : PatLeaf<(i32 imm), [{
2696 return (N->getZExtValue() < 32);
2699 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
2700 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2701 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2702 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
2703 (and (shl GPR:$Rm, lsl_amt:$sh),
2705 Requires<[IsARM, HasV6]>;
2707 // Alternate cases for PKHBT where identities eliminate some nodes.
2708 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
2709 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
2710 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
2711 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
2713 def asr_shift_imm : SDNodeXForm<imm, [{
2714 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
2715 return CurDAG->getTargetConstant(Sh, MVT::i32);
2718 def asr_amt : PatLeaf<(i32 imm), [{
2719 return (N->getZExtValue() <= 32);
2722 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2723 // will match the pattern below.
2724 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
2725 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2726 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2727 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
2728 (and (sra GPR:$Rm, asr_amt:$sh),
2730 Requires<[IsARM, HasV6]>;
2732 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2733 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2734 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
2735 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
2736 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
2737 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
2738 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
2740 //===----------------------------------------------------------------------===//
2741 // Comparison Instructions...
2744 defm CMP : AI1_cmp_irs<0b1010, "cmp",
2745 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2746 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2748 // FIXME: We have to be careful when using the CMN instruction and comparison
2749 // with 0. One would expect these two pieces of code should give identical
2765 // However, the CMN gives the *opposite* result when r1 is 0. This is because
2766 // the carry flag is set in the CMP case but not in the CMN case. In short, the
2767 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
2768 // value of r0 and the carry bit (because the "carry bit" parameter to
2769 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
2770 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
2771 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
2772 // parameter to AddWithCarry is defined as 0).
2774 // When x is 0 and unsigned:
2778 // ~x + 1 = 0x1 0000 0000
2779 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
2781 // Therefore, we should disable CMN when comparing against zero, until we can
2782 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
2783 // when it's a comparison which doesn't look at the 'carry' flag).
2785 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
2787 // This is related to <rdar://problem/7569620>.
2789 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
2790 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2792 // Note that TST/TEQ don't set all the same flags that CMP does!
2793 defm TST : AI1_cmp_irs<0b1000, "tst",
2794 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2795 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>, 1>;
2796 defm TEQ : AI1_cmp_irs<0b1001, "teq",
2797 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2798 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>, 1>;
2800 defm CMPz : AI1_cmp_irs<0b1010, "cmp",
2801 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2802 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
2803 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
2804 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2805 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2807 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
2808 // (CMNri GPR:$src, so_imm_neg:$imm)>;
2810 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
2811 (CMNzri GPR:$src, so_imm_neg:$imm)>;
2813 // Pseudo i64 compares for some floating point compares.
2814 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
2816 def BCCi64 : PseudoInst<(outs),
2817 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
2819 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
2821 def BCCZi64 : PseudoInst<(outs),
2822 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br, "",
2823 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
2824 } // usesCustomInserter
2827 // Conditional moves
2828 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2829 // a two-value operand where a dag node expects two operands. :(
2830 // FIXME: These should all be pseudo-instructions that get expanded to
2831 // the normal MOV instructions. That would fix the dependency on
2832 // special casing them in tblgen.
2833 let neverHasSideEffects = 1 in {
2834 def MOVCCr : AI1<0b1101, (outs GPR:$Rd), (ins GPR:$false, GPR:$Rm), DPFrm,
2835 IIC_iCMOVr, "mov", "\t$Rd, $Rm",
2836 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2837 RegConstraint<"$false = $Rd">, UnaryDP {
2842 let Inst{15-12} = Rd;
2843 let Inst{11-4} = 0b00000000;
2847 def MOVCCs : AI1<0b1101, (outs GPR:$Rd),
2848 (ins GPR:$false, so_reg:$shift), DPSoRegFrm, IIC_iCMOVsr,
2849 "mov", "\t$Rd, $shift",
2850 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
2851 RegConstraint<"$false = $Rd">, UnaryDP {
2857 let Inst{19-16} = Rn;
2858 let Inst{15-12} = Rd;
2859 let Inst{11-0} = shift;
2862 def MOVCCi16 : AI1<0b1000, (outs GPR:$Rd), (ins GPR:$false, i32imm:$imm),
2864 "movw", "\t$Rd, $imm",
2866 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
2872 let Inst{19-16} = imm{15-12};
2873 let Inst{15-12} = Rd;
2874 let Inst{11-0} = imm{11-0};
2877 def MOVCCi : AI1<0b1101, (outs GPR:$Rd),
2878 (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi,
2879 "mov", "\t$Rd, $imm",
2880 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2881 RegConstraint<"$false = $Rd">, UnaryDP {
2886 let Inst{19-16} = 0b0000;
2887 let Inst{15-12} = Rd;
2888 let Inst{11-0} = imm;
2890 } // neverHasSideEffects
2892 //===----------------------------------------------------------------------===//
2893 // Atomic operations intrinsics
2896 def memb_opt : Operand<i32> {
2897 let PrintMethod = "printMemBOption";
2900 // memory barriers protect the atomic sequences
2901 let hasSideEffects = 1 in {
2902 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
2903 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2904 Requires<[IsARM, HasDB]> {
2906 let Inst{31-4} = 0xf57ff05;
2907 let Inst{3-0} = opt;
2910 def DMB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary,
2911 "mcr", "\tp15, 0, $zero, c7, c10, 5",
2912 [(ARMMemBarrierMCR GPR:$zero)]>,
2913 Requires<[IsARM, HasV6]> {
2914 // FIXME: add encoding
2918 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
2920 [/* For disassembly only; pattern left blank */]>,
2921 Requires<[IsARM, HasDB]> {
2923 let Inst{31-4} = 0xf57ff04;
2924 let Inst{3-0} = opt;
2927 // ISB has only full system option -- for disassembly only
2928 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
2929 Requires<[IsARM, HasDB]> {
2930 let Inst{31-4} = 0xf57ff06;
2931 let Inst{3-0} = 0b1111;
2934 let usesCustomInserter = 1 in {
2935 let Uses = [CPSR] in {
2936 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
2937 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2938 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
2939 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
2940 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2941 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
2942 def ATOMIC_LOAD_AND_I8 : PseudoInst<
2943 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2944 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
2945 def ATOMIC_LOAD_OR_I8 : PseudoInst<
2946 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2947 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
2948 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
2949 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2950 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
2951 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
2952 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2953 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
2954 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
2955 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2956 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
2957 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
2958 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2959 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
2960 def ATOMIC_LOAD_AND_I16 : PseudoInst<
2961 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2962 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
2963 def ATOMIC_LOAD_OR_I16 : PseudoInst<
2964 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2965 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
2966 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
2967 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2968 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
2969 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
2970 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2971 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
2972 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
2973 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2974 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
2975 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
2976 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2977 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
2978 def ATOMIC_LOAD_AND_I32 : PseudoInst<
2979 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2980 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
2981 def ATOMIC_LOAD_OR_I32 : PseudoInst<
2982 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2983 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
2984 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
2985 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2986 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
2987 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
2988 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2989 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
2991 def ATOMIC_SWAP_I8 : PseudoInst<
2992 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, "",
2993 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
2994 def ATOMIC_SWAP_I16 : PseudoInst<
2995 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, "",
2996 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
2997 def ATOMIC_SWAP_I32 : PseudoInst<
2998 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, "",
2999 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3001 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3002 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, "",
3003 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3004 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3005 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, "",
3006 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3007 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3008 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, "",
3009 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3013 let mayLoad = 1 in {
3014 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3015 "ldrexb", "\t$Rt, [$Rn]",
3017 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3018 "ldrexh", "\t$Rt, [$Rn]",
3020 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3021 "ldrex", "\t$Rt, [$Rn]",
3023 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins GPR:$Rn),
3025 "ldrexd", "\t$Rt, $Rt2, [$Rn]",
3029 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3030 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$src, GPR:$Rn),
3032 "strexb", "\t$Rd, $src, [$Rn]",
3034 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3036 "strexh", "\t$Rd, $Rt, [$Rn]",
3038 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3040 "strex", "\t$Rd, $Rt, [$Rn]",
3042 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3043 (ins GPR:$Rt, GPR:$Rt2, GPR:$Rn),
3045 "strexd", "\t$Rd, $Rt, $Rt2, [$Rn]",
3049 // Clear-Exclusive is for disassembly only.
3050 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3051 [/* For disassembly only; pattern left blank */]>,
3052 Requires<[IsARM, HasV7]> {
3053 let Inst{31-0} = 0b11110101011111111111000000011111;
3056 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3057 let mayLoad = 1 in {
3058 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3059 [/* For disassembly only; pattern left blank */]>;
3060 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3061 [/* For disassembly only; pattern left blank */]>;
3064 //===----------------------------------------------------------------------===//
3068 // __aeabi_read_tp preserves the registers r1-r3.
3069 // FIXME: This needs to be a pseudo of some sort so that we can get the
3070 // encoding right, complete with fixup for the aeabi_read_tp function.
3072 Defs = [R0, R12, LR, CPSR] in {
3073 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
3074 "bl\t__aeabi_read_tp",
3075 [(set R0, ARMthread_pointer)]>;
3078 //===----------------------------------------------------------------------===//
3079 // SJLJ Exception handling intrinsics
3080 // eh_sjlj_setjmp() is an instruction sequence to store the return
3081 // address and save #0 in R0 for the non-longjmp case.
3082 // Since by its nature we may be coming from some other function to get
3083 // here, and we're using the stack frame for the containing function to
3084 // save/restore registers, we can't keep anything live in regs across
3085 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3086 // when we get here from a longjmp(). We force everthing out of registers
3087 // except for our own input by listing the relevant registers in Defs. By
3088 // doing so, we also cause the prologue/epilogue code to actively preserve
3089 // all of the callee-saved resgisters, which is exactly what we want.
3090 // A constant value is passed in $val, and we use the location as a scratch.
3092 // These are pseudo-instructions and are lowered to individual MC-insts, so
3093 // no encoding information is necessary.
3095 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
3096 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
3097 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
3098 D31 ], hasSideEffects = 1, isBarrier = 1 in {
3099 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src, GPR:$val),
3100 AddrModeNone, SizeSpecial, IndexModeNone,
3101 Pseudo, NoItinerary, "", "",
3102 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3103 Requires<[IsARM, HasVFP2]>;
3107 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
3108 hasSideEffects = 1, isBarrier = 1 in {
3109 def Int_eh_sjlj_setjmp_nofp : XI<(outs), (ins GPR:$src, GPR:$val),
3110 AddrModeNone, SizeSpecial, IndexModeNone,
3111 Pseudo, NoItinerary, "", "",
3112 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3113 Requires<[IsARM, NoVFP]>;
3116 // FIXME: Non-Darwin version(s)
3117 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3118 Defs = [ R7, LR, SP ] in {
3119 def Int_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
3120 AddrModeNone, SizeSpecial, IndexModeNone,
3121 Pseudo, NoItinerary, "", "",
3122 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3123 Requires<[IsARM, IsDarwin]>;
3126 // eh.sjlj.dispatchsetup pseudo-instruction.
3127 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3128 // handled when the pseudo is expanded (which happens before any passes
3129 // that need the instruction size).
3130 let isBarrier = 1, hasSideEffects = 1 in
3131 def Int_eh_sjlj_dispatchsetup :
3132 PseudoInst<(outs), (ins GPR:$src), NoItinerary, "",
3133 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
3134 Requires<[IsDarwin]>;
3136 //===----------------------------------------------------------------------===//
3137 // Non-Instruction Patterns
3140 // Large immediate handling.
3142 // Two piece so_imms.
3143 // FIXME: Remove this when we can do generalized remat.
3144 let isReMaterializable = 1 in
3145 def MOVi2pieces : PseudoInst<(outs GPR:$dst), (ins so_imm2part:$src),
3147 [(set GPR:$dst, (so_imm2part:$src))]>,
3148 Requires<[IsARM, NoV6T2]>;
3150 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
3151 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
3152 (so_imm2part_2 imm:$RHS))>;
3153 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
3154 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
3155 (so_imm2part_2 imm:$RHS))>;
3156 def : ARMPat<(add GPR:$LHS, so_imm2part:$RHS),
3157 (ADDri (ADDri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
3158 (so_imm2part_2 imm:$RHS))>;
3159 def : ARMPat<(add GPR:$LHS, so_neg_imm2part:$RHS),
3160 (SUBri (SUBri GPR:$LHS, (so_neg_imm2part_1 imm:$RHS)),
3161 (so_neg_imm2part_2 imm:$RHS))>;
3163 // 32-bit immediate using movw + movt.
3164 // This is a single pseudo instruction, the benefit is that it can be remat'd
3165 // as a single unit instead of having to handle reg inputs.
3166 // FIXME: Remove this when we can do generalized remat.
3167 let isReMaterializable = 1 in
3168 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, "",
3169 [(set GPR:$dst, (i32 imm:$src))]>,
3170 Requires<[IsARM, HasV6T2]>;
3172 // ConstantPool, GlobalAddress, and JumpTable
3173 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3174 Requires<[IsARM, DontUseMovt]>;
3175 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3176 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3177 Requires<[IsARM, UseMovt]>;
3178 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3179 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3181 // TODO: add,sub,and, 3-instr forms?
3184 def : ARMPat<(ARMtcret tcGPR:$dst),
3185 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3187 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3188 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3190 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3191 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3193 def : ARMPat<(ARMtcret tcGPR:$dst),
3194 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3196 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3197 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3199 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3200 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3203 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3204 Requires<[IsARM, IsNotDarwin]>;
3205 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3206 Requires<[IsARM, IsDarwin]>;
3208 // zextload i1 -> zextload i8
3209 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3210 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3212 // extload -> zextload
3213 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3214 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3215 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3216 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3218 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3220 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3221 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3224 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3225 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3226 (SMULBB GPR:$a, GPR:$b)>;
3227 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3228 (SMULBB GPR:$a, GPR:$b)>;
3229 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3230 (sra GPR:$b, (i32 16))),
3231 (SMULBT GPR:$a, GPR:$b)>;
3232 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3233 (SMULBT GPR:$a, GPR:$b)>;
3234 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3235 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3236 (SMULTB GPR:$a, GPR:$b)>;
3237 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3238 (SMULTB GPR:$a, GPR:$b)>;
3239 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3241 (SMULWB GPR:$a, GPR:$b)>;
3242 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3243 (SMULWB GPR:$a, GPR:$b)>;
3245 def : ARMV5TEPat<(add GPR:$acc,
3246 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3247 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3248 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3249 def : ARMV5TEPat<(add GPR:$acc,
3250 (mul sext_16_node:$a, sext_16_node:$b)),
3251 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3252 def : ARMV5TEPat<(add GPR:$acc,
3253 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3254 (sra GPR:$b, (i32 16)))),
3255 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3256 def : ARMV5TEPat<(add GPR:$acc,
3257 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3258 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3259 def : ARMV5TEPat<(add GPR:$acc,
3260 (mul (sra GPR:$a, (i32 16)),
3261 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3262 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3263 def : ARMV5TEPat<(add GPR:$acc,
3264 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3265 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3266 def : ARMV5TEPat<(add GPR:$acc,
3267 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3269 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3270 def : ARMV5TEPat<(add GPR:$acc,
3271 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3272 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3274 //===----------------------------------------------------------------------===//
3278 include "ARMInstrThumb.td"
3280 //===----------------------------------------------------------------------===//
3284 include "ARMInstrThumb2.td"
3286 //===----------------------------------------------------------------------===//
3287 // Floating Point Support
3290 include "ARMInstrVFP.td"
3292 //===----------------------------------------------------------------------===//
3293 // Advanced SIMD (NEON) Support
3296 include "ARMInstrNEON.td"
3298 //===----------------------------------------------------------------------===//
3299 // Coprocessor Instructions. For disassembly only.
3302 def CDP : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3303 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3304 NoItinerary, "cdp", "\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3305 [/* For disassembly only; pattern left blank */]> {
3309 def CDP2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3310 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3311 NoItinerary, "cdp2\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3312 [/* For disassembly only; pattern left blank */]> {
3313 let Inst{31-28} = 0b1111;
3317 class ACI<dag oops, dag iops, string opc, string asm>
3318 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
3319 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3320 let Inst{27-25} = 0b110;
3323 multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
3325 def _OFFSET : ACI<(outs),
3326 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3327 opc, "\tp$cop, cr$CRd, $addr"> {
3328 let Inst{31-28} = op31_28;
3329 let Inst{24} = 1; // P = 1
3330 let Inst{21} = 0; // W = 0
3331 let Inst{22} = 0; // D = 0
3332 let Inst{20} = load;
3335 def _PRE : ACI<(outs),
3336 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3337 opc, "\tp$cop, cr$CRd, $addr!"> {
3338 let Inst{31-28} = op31_28;
3339 let Inst{24} = 1; // P = 1
3340 let Inst{21} = 1; // W = 1
3341 let Inst{22} = 0; // D = 0
3342 let Inst{20} = load;
3345 def _POST : ACI<(outs),
3346 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3347 opc, "\tp$cop, cr$CRd, [$base], $offset"> {
3348 let Inst{31-28} = op31_28;
3349 let Inst{24} = 0; // P = 0
3350 let Inst{21} = 1; // W = 1
3351 let Inst{22} = 0; // D = 0
3352 let Inst{20} = load;
3355 def _OPTION : ACI<(outs),
3356 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option),
3357 opc, "\tp$cop, cr$CRd, [$base], $option"> {
3358 let Inst{31-28} = op31_28;
3359 let Inst{24} = 0; // P = 0
3360 let Inst{23} = 1; // U = 1
3361 let Inst{21} = 0; // W = 0
3362 let Inst{22} = 0; // D = 0
3363 let Inst{20} = load;
3366 def L_OFFSET : ACI<(outs),
3367 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3368 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
3369 let Inst{31-28} = op31_28;
3370 let Inst{24} = 1; // P = 1
3371 let Inst{21} = 0; // W = 0
3372 let Inst{22} = 1; // D = 1
3373 let Inst{20} = load;
3376 def L_PRE : ACI<(outs),
3377 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3378 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
3379 let Inst{31-28} = op31_28;
3380 let Inst{24} = 1; // P = 1
3381 let Inst{21} = 1; // W = 1
3382 let Inst{22} = 1; // D = 1
3383 let Inst{20} = load;
3386 def L_POST : ACI<(outs),
3387 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3388 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $offset"> {
3389 let Inst{31-28} = op31_28;
3390 let Inst{24} = 0; // P = 0
3391 let Inst{21} = 1; // W = 1
3392 let Inst{22} = 1; // D = 1
3393 let Inst{20} = load;
3396 def L_OPTION : ACI<(outs),
3397 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
3398 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $option"> {
3399 let Inst{31-28} = op31_28;
3400 let Inst{24} = 0; // P = 0
3401 let Inst{23} = 1; // U = 1
3402 let Inst{21} = 0; // W = 0
3403 let Inst{22} = 1; // D = 1
3404 let Inst{20} = load;
3408 defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">;
3409 defm LDC2 : LdStCop<0b1111, 1, "ldc2">;
3410 defm STC : LdStCop<{?,?,?,?}, 0, "stc">;
3411 defm STC2 : LdStCop<0b1111, 0, "stc2">;
3413 def MCR : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3414 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3415 NoItinerary, "mcr", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3416 [/* For disassembly only; pattern left blank */]> {
3421 def MCR2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3422 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3423 NoItinerary, "mcr2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3424 [/* For disassembly only; pattern left blank */]> {
3425 let Inst{31-28} = 0b1111;
3430 def MRC : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3431 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3432 NoItinerary, "mrc", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3433 [/* For disassembly only; pattern left blank */]> {
3438 def MRC2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3439 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3440 NoItinerary, "mrc2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3441 [/* For disassembly only; pattern left blank */]> {
3442 let Inst{31-28} = 0b1111;
3447 def MCRR : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3448 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3449 NoItinerary, "mcrr", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3450 [/* For disassembly only; pattern left blank */]> {
3451 let Inst{23-20} = 0b0100;
3454 def MCRR2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3455 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3456 NoItinerary, "mcrr2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3457 [/* For disassembly only; pattern left blank */]> {
3458 let Inst{31-28} = 0b1111;
3459 let Inst{23-20} = 0b0100;
3462 def MRRC : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3463 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3464 NoItinerary, "mrrc", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3465 [/* For disassembly only; pattern left blank */]> {
3466 let Inst{23-20} = 0b0101;
3469 def MRRC2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3470 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3471 NoItinerary, "mrrc2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3472 [/* For disassembly only; pattern left blank */]> {
3473 let Inst{31-28} = 0b1111;
3474 let Inst{23-20} = 0b0101;
3477 //===----------------------------------------------------------------------===//
3478 // Move between special register and ARM core register -- for disassembly only
3481 def MRS : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary, "mrs", "\t$dst, cpsr",
3482 [/* For disassembly only; pattern left blank */]> {
3483 let Inst{23-20} = 0b0000;
3484 let Inst{7-4} = 0b0000;
3487 def MRSsys : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary,"mrs","\t$dst, spsr",
3488 [/* For disassembly only; pattern left blank */]> {
3489 let Inst{23-20} = 0b0100;
3490 let Inst{7-4} = 0b0000;
3493 def MSR : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3494 "msr", "\tcpsr$mask, $src",
3495 [/* For disassembly only; pattern left blank */]> {
3496 let Inst{23-20} = 0b0010;
3497 let Inst{7-4} = 0b0000;
3500 def MSRi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3501 "msr", "\tcpsr$mask, $a",
3502 [/* For disassembly only; pattern left blank */]> {
3503 let Inst{23-20} = 0b0010;
3504 let Inst{7-4} = 0b0000;
3507 def MSRsys : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3508 "msr", "\tspsr$mask, $src",
3509 [/* For disassembly only; pattern left blank */]> {
3510 let Inst{23-20} = 0b0110;
3511 let Inst{7-4} = 0b0000;
3514 def MSRsysi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3515 "msr", "\tspsr$mask, $a",
3516 [/* For disassembly only; pattern left blank */]> {
3517 let Inst{23-20} = 0b0110;
3518 let Inst{7-4} = 0b0000;