1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
67 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
68 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
72 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
73 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
74 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
76 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
77 [SDNPHasChain, SDNPOutGlue]>;
78 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
79 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
81 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
82 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
84 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
85 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
87 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
88 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
91 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
92 [SDNPHasChain, SDNPOptInGlue]>;
94 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
97 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
98 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
100 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
102 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
105 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
108 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
111 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
112 [SDNPOutGlue, SDNPCommutative]>;
114 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
116 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
117 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
118 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
120 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
121 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
122 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
123 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
124 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
125 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
126 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
129 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
131 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
133 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDTPrefetch,
134 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
136 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
138 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
139 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
142 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
144 //===----------------------------------------------------------------------===//
145 // ARM Instruction Predicate Definitions.
147 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
148 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
149 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
150 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
151 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
152 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
153 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
154 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
155 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
156 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
157 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
158 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
159 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
160 def HasFP16 : Predicate<"Subtarget->hasFP16()">, AssemblerPredicate;
161 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
162 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
164 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
166 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
168 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
169 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
170 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
171 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
172 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
173 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
174 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
175 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
177 // FIXME: Eventually this will be just "hasV6T2Ops".
178 def UseMovt : Predicate<"Subtarget->useMovt()">;
179 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
180 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
182 //===----------------------------------------------------------------------===//
183 // ARM Flag Definitions.
185 class RegConstraint<string C> {
186 string Constraints = C;
189 //===----------------------------------------------------------------------===//
190 // ARM specific transformation functions and pattern fragments.
193 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
194 // so_imm_neg def below.
195 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
196 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
199 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
200 // so_imm_not def below.
201 def so_imm_not_XFORM : SDNodeXForm<imm, [{
202 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
205 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
206 def imm1_15 : PatLeaf<(i32 imm), [{
207 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
210 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
211 def imm16_31 : PatLeaf<(i32 imm), [{
212 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
217 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
218 }], so_imm_neg_XFORM>;
222 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
223 }], so_imm_not_XFORM>;
225 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
226 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
227 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
230 /// Split a 32-bit immediate into two 16 bit parts.
231 def hi16 : SDNodeXForm<imm, [{
232 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
235 def lo16AllZero : PatLeaf<(i32 imm), [{
236 // Returns true if all low 16-bits are 0.
237 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
240 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
242 def imm0_65535 : PatLeaf<(i32 imm), [{
243 return (uint32_t)N->getZExtValue() < 65536;
246 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
247 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
249 /// adde and sube predicates - True based on whether the carry flag output
250 /// will be needed or not.
251 def adde_dead_carry :
252 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
253 [{return !N->hasAnyUseOfValue(1);}]>;
254 def sube_dead_carry :
255 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
256 [{return !N->hasAnyUseOfValue(1);}]>;
257 def adde_live_carry :
258 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
259 [{return N->hasAnyUseOfValue(1);}]>;
260 def sube_live_carry :
261 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
262 [{return N->hasAnyUseOfValue(1);}]>;
264 // An 'and' node with a single use.
265 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
266 return N->hasOneUse();
269 // An 'xor' node with a single use.
270 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
271 return N->hasOneUse();
274 // An 'fmul' node with a single use.
275 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
276 return N->hasOneUse();
279 // An 'fadd' node which checks for single non-hazardous use.
280 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
281 return hasNoVMLxHazardUse(N);
284 // An 'fsub' node which checks for single non-hazardous use.
285 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
286 return hasNoVMLxHazardUse(N);
289 //===----------------------------------------------------------------------===//
290 // Operand Definitions.
294 // FIXME: rename brtarget to t2_brtarget
295 def brtarget : Operand<OtherVT> {
296 let EncoderMethod = "getBranchTargetOpValue";
299 // FIXME: get rid of this one?
300 def uncondbrtarget : Operand<OtherVT> {
301 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
304 // Branch target for ARM. Handles conditional/unconditional
305 def br_target : Operand<OtherVT> {
306 let EncoderMethod = "getARMBranchTargetOpValue";
310 // FIXME: rename bltarget to t2_bl_target?
311 def bltarget : Operand<i32> {
312 // Encoded the same as branch targets.
313 let EncoderMethod = "getBranchTargetOpValue";
316 // Call target for ARM. Handles conditional/unconditional
317 // FIXME: rename bl_target to t2_bltarget?
318 def bl_target : Operand<i32> {
319 // Encoded the same as branch targets.
320 let EncoderMethod = "getARMBranchTargetOpValue";
324 // A list of registers separated by comma. Used by load/store multiple.
325 def RegListAsmOperand : AsmOperandClass {
326 let Name = "RegList";
327 let SuperClasses = [];
330 def DPRRegListAsmOperand : AsmOperandClass {
331 let Name = "DPRRegList";
332 let SuperClasses = [];
335 def SPRRegListAsmOperand : AsmOperandClass {
336 let Name = "SPRRegList";
337 let SuperClasses = [];
340 def reglist : Operand<i32> {
341 let EncoderMethod = "getRegisterListOpValue";
342 let ParserMatchClass = RegListAsmOperand;
343 let PrintMethod = "printRegisterList";
346 def dpr_reglist : Operand<i32> {
347 let EncoderMethod = "getRegisterListOpValue";
348 let ParserMatchClass = DPRRegListAsmOperand;
349 let PrintMethod = "printRegisterList";
352 def spr_reglist : Operand<i32> {
353 let EncoderMethod = "getRegisterListOpValue";
354 let ParserMatchClass = SPRRegListAsmOperand;
355 let PrintMethod = "printRegisterList";
358 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
359 def cpinst_operand : Operand<i32> {
360 let PrintMethod = "printCPInstOperand";
364 def pclabel : Operand<i32> {
365 let PrintMethod = "printPCLabel";
368 // ADR instruction labels.
369 def adrlabel : Operand<i32> {
370 let EncoderMethod = "getAdrLabelOpValue";
373 def neon_vcvt_imm32 : Operand<i32> {
374 let EncoderMethod = "getNEONVcvtImm32OpValue";
377 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
378 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
379 int32_t v = (int32_t)N->getZExtValue();
380 return v == 8 || v == 16 || v == 24; }]> {
381 let EncoderMethod = "getRotImmOpValue";
384 def ShifterAsmOperand : AsmOperandClass {
385 let Name = "Shifter";
386 let SuperClasses = [];
389 // shift_imm: An integer that encodes a shift amount and the type of shift
390 // (currently either asr or lsl) using the same encoding used for the
391 // immediates in so_reg operands.
392 def shift_imm : Operand<i32> {
393 let PrintMethod = "printShiftImmOperand";
394 let ParserMatchClass = ShifterAsmOperand;
397 // shifter_operand operands: so_reg and so_imm.
398 def so_reg : Operand<i32>, // reg reg imm
399 ComplexPattern<i32, 3, "SelectShifterOperandReg",
400 [shl,srl,sra,rotr]> {
401 let EncoderMethod = "getSORegOpValue";
402 let PrintMethod = "printSORegOperand";
403 let MIOperandInfo = (ops GPR, GPR, shift_imm);
405 def shift_so_reg : Operand<i32>, // reg reg imm
406 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
407 [shl,srl,sra,rotr]> {
408 let EncoderMethod = "getSORegOpValue";
409 let PrintMethod = "printSORegOperand";
410 let MIOperandInfo = (ops GPR, GPR, shift_imm);
413 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
414 // 8-bit immediate rotated by an arbitrary number of bits.
415 def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> {
416 let EncoderMethod = "getSOImmOpValue";
417 let PrintMethod = "printSOImmOperand";
420 // Break so_imm's up into two pieces. This handles immediates with up to 16
421 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
422 // get the first/second pieces.
423 def so_imm2part : PatLeaf<(imm), [{
424 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
427 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
429 def arm_i32imm : PatLeaf<(imm), [{
430 if (Subtarget->hasV6T2Ops())
432 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
435 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
436 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
437 return (int32_t)N->getZExtValue() < 32;
440 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
441 def imm0_31_m1 : Operand<i32>, PatLeaf<(imm), [{
442 return (int32_t)N->getZExtValue() < 32;
444 let EncoderMethod = "getImmMinusOneOpValue";
447 // i32imm_hilo16 - For movt/movw - sets the MC Encoder method.
448 // The imm is split into imm{15-12}, imm{11-0}
450 def i32imm_hilo16 : Operand<i32> {
451 let EncoderMethod = "getHiLo16ImmOpValue";
454 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
456 def bf_inv_mask_imm : Operand<i32>,
458 return ARM::isBitFieldInvertedMask(N->getZExtValue());
460 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
461 let PrintMethod = "printBitfieldInvMaskImmOperand";
464 /// lsb_pos_imm - position of the lsb bit, used by BFI4p and t2BFI4p
465 def lsb_pos_imm : Operand<i32>, PatLeaf<(imm), [{
466 return isInt<5>(N->getSExtValue());
469 /// width_imm - number of bits to be copied, used by BFI4p and t2BFI4p
470 def width_imm : Operand<i32>, PatLeaf<(imm), [{
471 return N->getSExtValue() > 0 && N->getSExtValue() <= 32;
473 let EncoderMethod = "getMsbOpValue";
476 // Define ARM specific addressing modes.
479 // addrmode_imm12 := reg +/- imm12
481 def addrmode_imm12 : Operand<i32>,
482 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
483 // 12-bit immediate operand. Note that instructions using this encode
484 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
485 // immediate values are as normal.
487 let EncoderMethod = "getAddrModeImm12OpValue";
488 let PrintMethod = "printAddrModeImm12Operand";
489 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
491 // ldst_so_reg := reg +/- reg shop imm
493 def ldst_so_reg : Operand<i32>,
494 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
495 let EncoderMethod = "getLdStSORegOpValue";
496 // FIXME: Simplify the printer
497 let PrintMethod = "printAddrMode2Operand";
498 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
501 // addrmode2 := reg +/- imm12
502 // := reg +/- reg shop imm
504 def addrmode2 : Operand<i32>,
505 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
506 let EncoderMethod = "getAddrMode2OpValue";
507 let PrintMethod = "printAddrMode2Operand";
508 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
511 def am2offset : Operand<i32>,
512 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
513 [], [SDNPWantRoot]> {
514 let EncoderMethod = "getAddrMode2OffsetOpValue";
515 let PrintMethod = "printAddrMode2OffsetOperand";
516 let MIOperandInfo = (ops GPR, i32imm);
519 // addrmode3 := reg +/- reg
520 // addrmode3 := reg +/- imm8
522 def addrmode3 : Operand<i32>,
523 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
524 let EncoderMethod = "getAddrMode3OpValue";
525 let PrintMethod = "printAddrMode3Operand";
526 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
529 def am3offset : Operand<i32>,
530 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
531 [], [SDNPWantRoot]> {
532 let EncoderMethod = "getAddrMode3OffsetOpValue";
533 let PrintMethod = "printAddrMode3OffsetOperand";
534 let MIOperandInfo = (ops GPR, i32imm);
537 // ldstm_mode := {ia, ib, da, db}
539 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
540 let EncoderMethod = "getLdStmModeOpValue";
541 let PrintMethod = "printLdStmModeOperand";
544 def MemMode5AsmOperand : AsmOperandClass {
545 let Name = "MemMode5";
546 let SuperClasses = [];
549 // addrmode5 := reg +/- imm8*4
551 def addrmode5 : Operand<i32>,
552 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
553 let PrintMethod = "printAddrMode5Operand";
554 let MIOperandInfo = (ops GPR:$base, i32imm);
555 let ParserMatchClass = MemMode5AsmOperand;
556 let EncoderMethod = "getAddrMode5OpValue";
559 // addrmode6 := reg with optional alignment
561 def addrmode6 : Operand<i32>,
562 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
563 let PrintMethod = "printAddrMode6Operand";
564 let MIOperandInfo = (ops GPR:$addr, i32imm);
565 let EncoderMethod = "getAddrMode6AddressOpValue";
568 def am6offset : Operand<i32>,
569 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
570 [], [SDNPWantRoot]> {
571 let PrintMethod = "printAddrMode6OffsetOperand";
572 let MIOperandInfo = (ops GPR);
573 let EncoderMethod = "getAddrMode6OffsetOpValue";
576 // Special version of addrmode6 to handle alignment encoding for VLD-dup
577 // instructions, specifically VLD4-dup.
578 def addrmode6dup : Operand<i32>,
579 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
580 let PrintMethod = "printAddrMode6Operand";
581 let MIOperandInfo = (ops GPR:$addr, i32imm);
582 let EncoderMethod = "getAddrMode6DupAddressOpValue";
585 // addrmodepc := pc + reg
587 def addrmodepc : Operand<i32>,
588 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
589 let PrintMethod = "printAddrModePCOperand";
590 let MIOperandInfo = (ops GPR, i32imm);
593 def MemMode7AsmOperand : AsmOperandClass {
594 let Name = "MemMode7";
595 let SuperClasses = [];
599 // Used by load/store exclusive instructions. Useful to enable right assembly
600 // parsing and printing. Not used for any codegen matching.
602 def addrmode7 : Operand<i32> {
603 let PrintMethod = "printAddrMode7Operand";
604 let MIOperandInfo = (ops GPR);
605 let ParserMatchClass = MemMode7AsmOperand;
608 def nohash_imm : Operand<i32> {
609 let PrintMethod = "printNoHashImmediate";
612 def CoprocNumAsmOperand : AsmOperandClass {
613 let Name = "CoprocNum";
614 let SuperClasses = [];
615 let ParserMethod = "tryParseCoprocNumOperand";
618 def CoprocRegAsmOperand : AsmOperandClass {
619 let Name = "CoprocReg";
620 let SuperClasses = [];
621 let ParserMethod = "tryParseCoprocRegOperand";
624 def p_imm : Operand<i32> {
625 let PrintMethod = "printPImmediate";
626 let ParserMatchClass = CoprocNumAsmOperand;
629 def c_imm : Operand<i32> {
630 let PrintMethod = "printCImmediate";
631 let ParserMatchClass = CoprocRegAsmOperand;
634 //===----------------------------------------------------------------------===//
636 include "ARMInstrFormats.td"
638 //===----------------------------------------------------------------------===//
639 // Multiclass helpers...
642 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
643 /// binop that produces a value.
644 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
645 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
646 PatFrag opnode, bit Commutable = 0> {
647 // The register-immediate version is re-materializable. This is useful
648 // in particular for taking the address of a local.
649 let isReMaterializable = 1 in {
650 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
651 iii, opc, "\t$Rd, $Rn, $imm",
652 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
657 let Inst{19-16} = Rn;
658 let Inst{15-12} = Rd;
659 let Inst{11-0} = imm;
662 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
663 iir, opc, "\t$Rd, $Rn, $Rm",
664 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
669 let isCommutable = Commutable;
670 let Inst{19-16} = Rn;
671 let Inst{15-12} = Rd;
672 let Inst{11-4} = 0b00000000;
675 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
676 iis, opc, "\t$Rd, $Rn, $shift",
677 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
682 let Inst{19-16} = Rn;
683 let Inst{15-12} = Rd;
684 let Inst{11-0} = shift;
688 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
689 /// instruction modifies the CPSR register.
690 let isCodeGenOnly = 1, Defs = [CPSR] in {
691 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
692 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
693 PatFrag opnode, bit Commutable = 0> {
694 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
695 iii, opc, "\t$Rd, $Rn, $imm",
696 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
702 let Inst{19-16} = Rn;
703 let Inst{15-12} = Rd;
704 let Inst{11-0} = imm;
706 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
707 iir, opc, "\t$Rd, $Rn, $Rm",
708 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
712 let isCommutable = Commutable;
715 let Inst{19-16} = Rn;
716 let Inst{15-12} = Rd;
717 let Inst{11-4} = 0b00000000;
720 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
721 iis, opc, "\t$Rd, $Rn, $shift",
722 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
728 let Inst{19-16} = Rn;
729 let Inst{15-12} = Rd;
730 let Inst{11-0} = shift;
735 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
736 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
737 /// a explicit result, only implicitly set CPSR.
738 let isCompare = 1, Defs = [CPSR] in {
739 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
740 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
741 PatFrag opnode, bit Commutable = 0> {
742 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
744 [(opnode GPR:$Rn, so_imm:$imm)]> {
749 let Inst{19-16} = Rn;
750 let Inst{15-12} = 0b0000;
751 let Inst{11-0} = imm;
753 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
755 [(opnode GPR:$Rn, GPR:$Rm)]> {
758 let isCommutable = Commutable;
761 let Inst{19-16} = Rn;
762 let Inst{15-12} = 0b0000;
763 let Inst{11-4} = 0b00000000;
766 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
767 opc, "\t$Rn, $shift",
768 [(opnode GPR:$Rn, so_reg:$shift)]> {
773 let Inst{19-16} = Rn;
774 let Inst{15-12} = 0b0000;
775 let Inst{11-0} = shift;
780 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
781 /// register and one whose operand is a register rotated by 8/16/24.
782 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
783 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
784 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
785 IIC_iEXTr, opc, "\t$Rd, $Rm",
786 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
787 Requires<[IsARM, HasV6]> {
790 let Inst{19-16} = 0b1111;
791 let Inst{15-12} = Rd;
792 let Inst{11-10} = 0b00;
795 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
796 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
797 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
798 Requires<[IsARM, HasV6]> {
802 let Inst{19-16} = 0b1111;
803 let Inst{15-12} = Rd;
804 let Inst{11-10} = rot;
809 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
810 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
811 IIC_iEXTr, opc, "\t$Rd, $Rm",
812 [/* For disassembly only; pattern left blank */]>,
813 Requires<[IsARM, HasV6]> {
814 let Inst{19-16} = 0b1111;
815 let Inst{11-10} = 0b00;
817 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
818 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
819 [/* For disassembly only; pattern left blank */]>,
820 Requires<[IsARM, HasV6]> {
822 let Inst{19-16} = 0b1111;
823 let Inst{11-10} = rot;
827 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
828 /// register and one whose operand is a register rotated by 8/16/24.
829 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
830 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
831 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
832 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
833 Requires<[IsARM, HasV6]> {
837 let Inst{19-16} = Rn;
838 let Inst{15-12} = Rd;
839 let Inst{11-10} = 0b00;
840 let Inst{9-4} = 0b000111;
843 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
845 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
846 [(set GPR:$Rd, (opnode GPR:$Rn,
847 (rotr GPR:$Rm, rot_imm:$rot)))]>,
848 Requires<[IsARM, HasV6]> {
853 let Inst{19-16} = Rn;
854 let Inst{15-12} = Rd;
855 let Inst{11-10} = rot;
856 let Inst{9-4} = 0b000111;
861 // For disassembly only.
862 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
863 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
864 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
865 [/* For disassembly only; pattern left blank */]>,
866 Requires<[IsARM, HasV6]> {
867 let Inst{11-10} = 0b00;
869 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
871 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
872 [/* For disassembly only; pattern left blank */]>,
873 Requires<[IsARM, HasV6]> {
876 let Inst{19-16} = Rn;
877 let Inst{11-10} = rot;
881 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
882 let Uses = [CPSR] in {
883 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
884 bit Commutable = 0> {
885 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
886 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
887 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
893 let Inst{15-12} = Rd;
894 let Inst{19-16} = Rn;
895 let Inst{11-0} = imm;
897 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
898 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
899 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
904 let Inst{11-4} = 0b00000000;
906 let isCommutable = Commutable;
908 let Inst{15-12} = Rd;
909 let Inst{19-16} = Rn;
911 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
912 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
913 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
919 let Inst{11-0} = shift;
920 let Inst{15-12} = Rd;
921 let Inst{19-16} = Rn;
924 // Carry setting variants
925 let isCodeGenOnly = 1, Defs = [CPSR] in {
926 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
927 bit Commutable = 0> {
928 def Sri : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
929 DPFrm, IIC_iALUi, !strconcat(opc, "\t$Rd, $Rn, $imm"),
930 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
935 let Inst{15-12} = Rd;
936 let Inst{19-16} = Rn;
937 let Inst{11-0} = imm;
941 def Srr : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
942 DPFrm, IIC_iALUr, !strconcat(opc, "\t$Rd, $Rn, $Rm"),
943 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
948 let Inst{11-4} = 0b00000000;
949 let isCommutable = Commutable;
951 let Inst{15-12} = Rd;
952 let Inst{19-16} = Rn;
956 def Srs : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
957 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$Rd, $Rn, $shift"),
958 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
963 let Inst{11-0} = shift;
964 let Inst{15-12} = Rd;
965 let Inst{19-16} = Rn;
973 let canFoldAsLoad = 1, isReMaterializable = 1 in {
974 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
975 InstrItinClass iir, PatFrag opnode> {
976 // Note: We use the complex addrmode_imm12 rather than just an input
977 // GPR and a constrained immediate so that we can use this to match
978 // frame index references and avoid matching constant pool references.
979 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
980 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
981 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
984 let Inst{23} = addr{12}; // U (add = ('U' == 1))
985 let Inst{19-16} = addr{16-13}; // Rn
986 let Inst{15-12} = Rt;
987 let Inst{11-0} = addr{11-0}; // imm12
989 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
990 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
991 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
994 let shift{4} = 0; // Inst{4} = 0
995 let Inst{23} = shift{12}; // U (add = ('U' == 1))
996 let Inst{19-16} = shift{16-13}; // Rn
997 let Inst{15-12} = Rt;
998 let Inst{11-0} = shift{11-0};
1003 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1004 InstrItinClass iir, PatFrag opnode> {
1005 // Note: We use the complex addrmode_imm12 rather than just an input
1006 // GPR and a constrained immediate so that we can use this to match
1007 // frame index references and avoid matching constant pool references.
1008 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1009 (ins GPR:$Rt, addrmode_imm12:$addr),
1010 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1011 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1014 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1015 let Inst{19-16} = addr{16-13}; // Rn
1016 let Inst{15-12} = Rt;
1017 let Inst{11-0} = addr{11-0}; // imm12
1019 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1020 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1021 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1024 let shift{4} = 0; // Inst{4} = 0
1025 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1026 let Inst{19-16} = shift{16-13}; // Rn
1027 let Inst{15-12} = Rt;
1028 let Inst{11-0} = shift{11-0};
1031 //===----------------------------------------------------------------------===//
1033 //===----------------------------------------------------------------------===//
1035 //===----------------------------------------------------------------------===//
1036 // Miscellaneous Instructions.
1039 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1040 /// the function. The first operand is the ID# for this instruction, the second
1041 /// is the index into the MachineConstantPool that this is, the third is the
1042 /// size in bytes of this constant pool entry.
1043 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1044 def CONSTPOOL_ENTRY :
1045 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1046 i32imm:$size), NoItinerary, []>;
1048 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1049 // from removing one half of the matched pairs. That breaks PEI, which assumes
1050 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1051 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1052 def ADJCALLSTACKUP :
1053 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1054 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1056 def ADJCALLSTACKDOWN :
1057 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1058 [(ARMcallseq_start timm:$amt)]>;
1061 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
1062 [/* For disassembly only; pattern left blank */]>,
1063 Requires<[IsARM, HasV6T2]> {
1064 let Inst{27-16} = 0b001100100000;
1065 let Inst{15-8} = 0b11110000;
1066 let Inst{7-0} = 0b00000000;
1069 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
1070 [/* For disassembly only; pattern left blank */]>,
1071 Requires<[IsARM, HasV6T2]> {
1072 let Inst{27-16} = 0b001100100000;
1073 let Inst{15-8} = 0b11110000;
1074 let Inst{7-0} = 0b00000001;
1077 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
1078 [/* For disassembly only; pattern left blank */]>,
1079 Requires<[IsARM, HasV6T2]> {
1080 let Inst{27-16} = 0b001100100000;
1081 let Inst{15-8} = 0b11110000;
1082 let Inst{7-0} = 0b00000010;
1085 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
1086 [/* For disassembly only; pattern left blank */]>,
1087 Requires<[IsARM, HasV6T2]> {
1088 let Inst{27-16} = 0b001100100000;
1089 let Inst{15-8} = 0b11110000;
1090 let Inst{7-0} = 0b00000011;
1093 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
1095 [/* For disassembly only; pattern left blank */]>,
1096 Requires<[IsARM, HasV6]> {
1101 let Inst{15-12} = Rd;
1102 let Inst{19-16} = Rn;
1103 let Inst{27-20} = 0b01101000;
1104 let Inst{7-4} = 0b1011;
1105 let Inst{11-8} = 0b1111;
1108 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1109 [/* For disassembly only; pattern left blank */]>,
1110 Requires<[IsARM, HasV6T2]> {
1111 let Inst{27-16} = 0b001100100000;
1112 let Inst{15-8} = 0b11110000;
1113 let Inst{7-0} = 0b00000100;
1116 // The i32imm operand $val can be used by a debugger to store more information
1117 // about the breakpoint.
1118 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
1119 [/* For disassembly only; pattern left blank */]>,
1122 let Inst{3-0} = val{3-0};
1123 let Inst{19-8} = val{15-4};
1124 let Inst{27-20} = 0b00010010;
1125 let Inst{7-4} = 0b0111;
1128 // Change Processor State is a system instruction -- for disassembly and
1130 // FIXME: Since the asm parser has currently no clean way to handle optional
1131 // operands, create 3 versions of the same instruction. Once there's a clean
1132 // framework to represent optional operands, change this behavior.
1133 class CPS<dag iops, string asm_ops>
1134 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1135 [/* For disassembly only; pattern left blank */]>, Requires<[IsARM]> {
1141 let Inst{31-28} = 0b1111;
1142 let Inst{27-20} = 0b00010000;
1143 let Inst{19-18} = imod;
1144 let Inst{17} = M; // Enabled if mode is set;
1146 let Inst{8-6} = iflags;
1148 let Inst{4-0} = mode;
1152 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
1153 "$imod\t$iflags, $mode">;
1154 let mode = 0, M = 0 in
1155 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1157 let imod = 0, iflags = 0, M = 1 in
1158 def CPS1p : CPS<(ins i32imm:$mode), "\t$mode">;
1160 // Preload signals the memory system of possible future data/instruction access.
1161 // These are for disassembly only.
1162 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1164 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1165 !strconcat(opc, "\t$addr"),
1166 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1169 let Inst{31-26} = 0b111101;
1170 let Inst{25} = 0; // 0 for immediate form
1171 let Inst{24} = data;
1172 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1173 let Inst{22} = read;
1174 let Inst{21-20} = 0b01;
1175 let Inst{19-16} = addr{16-13}; // Rn
1176 let Inst{15-12} = 0b1111;
1177 let Inst{11-0} = addr{11-0}; // imm12
1180 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1181 !strconcat(opc, "\t$shift"),
1182 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1184 let Inst{31-26} = 0b111101;
1185 let Inst{25} = 1; // 1 for register form
1186 let Inst{24} = data;
1187 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1188 let Inst{22} = read;
1189 let Inst{21-20} = 0b01;
1190 let Inst{19-16} = shift{16-13}; // Rn
1191 let Inst{15-12} = 0b1111;
1192 let Inst{11-0} = shift{11-0};
1196 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1197 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1198 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1200 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1202 [/* For disassembly only; pattern left blank */]>,
1205 let Inst{31-10} = 0b1111000100000001000000;
1210 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1211 [/* For disassembly only; pattern left blank */]>,
1212 Requires<[IsARM, HasV7]> {
1214 let Inst{27-4} = 0b001100100000111100001111;
1215 let Inst{3-0} = opt;
1218 // A5.4 Permanently UNDEFINED instructions.
1219 let isBarrier = 1, isTerminator = 1 in
1220 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1223 let Inst = 0xe7ffdefe;
1226 // Address computation and loads and stores in PIC mode.
1227 let isNotDuplicable = 1 in {
1228 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1229 Size4Bytes, IIC_iALUr,
1230 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1232 let AddedComplexity = 10 in {
1233 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1234 Size4Bytes, IIC_iLoad_r,
1235 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1237 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1238 Size4Bytes, IIC_iLoad_bh_r,
1239 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1241 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1242 Size4Bytes, IIC_iLoad_bh_r,
1243 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1245 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1246 Size4Bytes, IIC_iLoad_bh_r,
1247 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1249 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1250 Size4Bytes, IIC_iLoad_bh_r,
1251 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1253 let AddedComplexity = 10 in {
1254 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1255 Size4Bytes, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1257 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1258 Size4Bytes, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1259 addrmodepc:$addr)]>;
1261 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1262 Size4Bytes, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1264 } // isNotDuplicable = 1
1267 // LEApcrel - Load a pc-relative address into a register without offending the
1269 let neverHasSideEffects = 1, isReMaterializable = 1 in
1270 // The 'adr' mnemonic encodes differently if the label is before or after
1271 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1272 // know until then which form of the instruction will be used.
1273 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1274 MiscFrm, IIC_iALUi, "adr", "\t$Rd, #$label", []> {
1277 let Inst{27-25} = 0b001;
1279 let Inst{19-16} = 0b1111;
1280 let Inst{15-12} = Rd;
1281 let Inst{11-0} = label;
1283 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1284 Size4Bytes, IIC_iALUi, []>;
1286 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1287 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1288 Size4Bytes, IIC_iALUi, []>;
1290 //===----------------------------------------------------------------------===//
1291 // Control Flow Instructions.
1294 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1296 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1297 "bx", "\tlr", [(ARMretflag)]>,
1298 Requires<[IsARM, HasV4T]> {
1299 let Inst{27-0} = 0b0001001011111111111100011110;
1303 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1304 "mov", "\tpc, lr", [(ARMretflag)]>,
1305 Requires<[IsARM, NoV4T]> {
1306 let Inst{27-0} = 0b0001101000001111000000001110;
1310 // Indirect branches
1311 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1313 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1314 [(brind GPR:$dst)]>,
1315 Requires<[IsARM, HasV4T]> {
1317 let Inst{31-4} = 0b1110000100101111111111110001;
1318 let Inst{3-0} = dst;
1322 // FIXME: We would really like to define this as a vanilla ARMPat like:
1323 // ARMPat<(brind GPR:$dst), (MOVr PC, GPR:$dst)>
1324 // With that, however, we can't set isBranch, isTerminator, etc..
1325 def MOVPCRX : ARMPseudoInst<(outs), (ins GPR:$dst),
1326 Size4Bytes, IIC_Br, [(brind GPR:$dst)]>,
1327 Requires<[IsARM, NoV4T]>;
1330 // All calls clobber the non-callee saved registers. SP is marked as
1331 // a use to prevent stack-pointer assignments that appear immediately
1332 // before calls from potentially appearing dead.
1334 // On non-Darwin platforms R9 is callee-saved.
1335 // FIXME: Do we really need a non-predicated version? If so, it should
1336 // at least be a pseudo instruction expanding to the predicated version
1337 // at MC lowering time.
1338 Defs = [R0, R1, R2, R3, R12, LR,
1339 D0, D1, D2, D3, D4, D5, D6, D7,
1340 D16, D17, D18, D19, D20, D21, D22, D23,
1341 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1343 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1344 IIC_Br, "bl\t$func",
1345 [(ARMcall tglobaladdr:$func)]>,
1346 Requires<[IsARM, IsNotDarwin]> {
1347 let Inst{31-28} = 0b1110;
1349 let Inst{23-0} = func;
1352 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1353 IIC_Br, "bl", "\t$func",
1354 [(ARMcall_pred tglobaladdr:$func)]>,
1355 Requires<[IsARM, IsNotDarwin]> {
1357 let Inst{23-0} = func;
1361 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1362 IIC_Br, "blx\t$func",
1363 [(ARMcall GPR:$func)]>,
1364 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1366 let Inst{31-4} = 0b1110000100101111111111110011;
1367 let Inst{3-0} = func;
1370 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1371 IIC_Br, "blx", "\t$func",
1372 [(ARMcall_pred GPR:$func)]>,
1373 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1375 let Inst{27-4} = 0b000100101111111111110011;
1376 let Inst{3-0} = func;
1380 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1381 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1382 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1383 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1386 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1387 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1388 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1392 // On Darwin R9 is call-clobbered.
1393 // R7 is marked as a use to prevent frame-pointer assignments from being
1394 // moved above / below calls.
1395 Defs = [R0, R1, R2, R3, R9, R12, LR,
1396 D0, D1, D2, D3, D4, D5, D6, D7,
1397 D16, D17, D18, D19, D20, D21, D22, D23,
1398 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1399 Uses = [R7, SP] in {
1400 def BLr9 : ARMPseudoInst<(outs), (ins bltarget:$func, variable_ops),
1402 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]>;
1404 def BLr9_pred : ARMPseudoInst<(outs),
1405 (ins bltarget:$func, pred:$p, variable_ops),
1407 [(ARMcall_pred tglobaladdr:$func)]>,
1408 Requires<[IsARM, IsDarwin]>;
1411 def BLXr9 : ARMPseudoInst<(outs), (ins GPR:$func, variable_ops),
1413 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]>;
1415 def BLXr9_pred: ARMPseudoInst<(outs), (ins GPR:$func, pred:$p, variable_ops),
1417 [(ARMcall_pred GPR:$func)]>,
1418 Requires<[IsARM, HasV5T, IsDarwin]>;
1421 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1422 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1423 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1424 Requires<[IsARM, HasV4T, IsDarwin]>;
1427 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1428 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1429 Requires<[IsARM, NoV4T, IsDarwin]>;
1434 // FIXME: The Thumb versions of these should live in ARMInstrThumb.td
1435 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1437 let Defs = [R0, R1, R2, R3, R9, R12,
1438 D0, D1, D2, D3, D4, D5, D6, D7,
1439 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1440 D27, D28, D29, D30, D31, PC],
1442 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1443 IIC_Br, []>, Requires<[IsDarwin]>;
1445 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1446 IIC_Br, []>, Requires<[IsDarwin]>;
1448 def TAILJMPd : ARMPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1450 []>, Requires<[IsARM, IsDarwin]>;
1452 def tTAILJMPd: tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1454 []>, Requires<[IsThumb, IsDarwin]>;
1456 def TAILJMPr : ARMPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1458 []>, Requires<[IsARM, IsDarwin]>;
1460 def tTAILJMPr : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1462 []>, Requires<[IsThumb, IsDarwin]>;
1465 // Non-Darwin versions (the difference is R9).
1466 let Defs = [R0, R1, R2, R3, R12,
1467 D0, D1, D2, D3, D4, D5, D6, D7,
1468 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1469 D27, D28, D29, D30, D31, PC],
1471 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1472 IIC_Br, []>, Requires<[IsNotDarwin]>;
1474 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1475 IIC_Br, []>, Requires<[IsNotDarwin]>;
1477 def TAILJMPdND : ARMPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1479 []>, Requires<[IsARM, IsNotDarwin]>;
1481 def tTAILJMPdND : tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1483 []>, Requires<[IsThumb, IsNotDarwin]>;
1485 def TAILJMPrND : ARMPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1487 []>, Requires<[IsARM, IsNotDarwin]>;
1488 def tTAILJMPrND : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1490 []>, Requires<[IsThumb, IsNotDarwin]>;
1494 let isBranch = 1, isTerminator = 1 in {
1495 // B is "predicable" since it's just a Bcc with an 'always' condition.
1496 let isBarrier = 1 in {
1497 let isPredicable = 1 in
1498 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1499 // should be sufficient.
1500 def B : ARMPseudoInst<(outs), (ins brtarget:$target), Size4Bytes, IIC_Br,
1503 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1504 def BR_JTr : ARMPseudoInst<(outs),
1505 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1506 SizeSpecial, IIC_Br,
1507 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1508 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1509 // into i12 and rs suffixed versions.
1510 def BR_JTm : ARMPseudoInst<(outs),
1511 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1512 SizeSpecial, IIC_Br,
1513 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1515 def BR_JTadd : ARMPseudoInst<(outs),
1516 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1517 SizeSpecial, IIC_Br,
1518 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1520 } // isNotDuplicable = 1, isIndirectBranch = 1
1523 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1524 // a two-value operand where a dag node expects two operands. :(
1525 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1526 IIC_Br, "b", "\t$target",
1527 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1529 let Inst{23-0} = target;
1533 // BLX (immediate) -- for disassembly only
1534 def BLXi : AXI<(outs), (ins br_target:$target), BrMiscFrm, NoItinerary,
1535 "blx\t$target", [/* pattern left blank */]>,
1536 Requires<[IsARM, HasV5T]> {
1537 let Inst{31-25} = 0b1111101;
1539 let Inst{23-0} = target{24-1};
1540 let Inst{24} = target{0};
1543 // Branch and Exchange Jazelle -- for disassembly only
1544 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1545 [/* For disassembly only; pattern left blank */]> {
1546 let Inst{23-20} = 0b0010;
1547 //let Inst{19-8} = 0xfff;
1548 let Inst{7-4} = 0b0010;
1551 // Secure Monitor Call is a system instruction -- for disassembly only
1552 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1553 [/* For disassembly only; pattern left blank */]> {
1555 let Inst{23-4} = 0b01100000000000000111;
1556 let Inst{3-0} = opt;
1559 // Supervisor Call (Software Interrupt) -- for disassembly only
1560 let isCall = 1, Uses = [SP] in {
1561 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1562 [/* For disassembly only; pattern left blank */]> {
1564 let Inst{23-0} = svc;
1567 def : MnemonicAlias<"swi", "svc">;
1569 // Store Return State is a system instruction -- for disassembly only
1570 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1571 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1572 NoItinerary, "srs${amode}\tsp!, $mode",
1573 [/* For disassembly only; pattern left blank */]> {
1574 let Inst{31-28} = 0b1111;
1575 let Inst{22-20} = 0b110; // W = 1
1578 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1579 NoItinerary, "srs${amode}\tsp, $mode",
1580 [/* For disassembly only; pattern left blank */]> {
1581 let Inst{31-28} = 0b1111;
1582 let Inst{22-20} = 0b100; // W = 0
1585 // Return From Exception is a system instruction -- for disassembly only
1586 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1587 NoItinerary, "rfe${amode}\t$base!",
1588 [/* For disassembly only; pattern left blank */]> {
1589 let Inst{31-28} = 0b1111;
1590 let Inst{22-20} = 0b011; // W = 1
1593 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1594 NoItinerary, "rfe${amode}\t$base",
1595 [/* For disassembly only; pattern left blank */]> {
1596 let Inst{31-28} = 0b1111;
1597 let Inst{22-20} = 0b001; // W = 0
1599 } // isCodeGenOnly = 1
1601 //===----------------------------------------------------------------------===//
1602 // Load / store Instructions.
1608 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1609 UnOpFrag<(load node:$Src)>>;
1610 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1611 UnOpFrag<(zextloadi8 node:$Src)>>;
1612 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1613 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1614 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1615 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1617 // Special LDR for loads from non-pc-relative constpools.
1618 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1619 isReMaterializable = 1 in
1620 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1621 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
1625 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1626 let Inst{19-16} = 0b1111;
1627 let Inst{15-12} = Rt;
1628 let Inst{11-0} = addr{11-0}; // imm12
1631 // Loads with zero extension
1632 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1633 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
1634 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
1636 // Loads with sign extension
1637 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1638 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
1639 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
1641 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1642 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
1643 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
1645 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
1646 isCodeGenOnly = 1 in { // $dst2 doesn't exist in asmstring?
1647 // FIXME: $dst2 isn't in the asm string as it's implied by $Rd (dst2 = Rd+1)
1648 // how to represent that such that tblgen is happy and we don't
1649 // mark this codegen only?
1651 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
1652 (ins addrmode3:$addr), LdMiscFrm,
1653 IIC_iLoad_d_r, "ldrd", "\t$Rd, $addr",
1654 []>, Requires<[IsARM, HasV5TE]>;
1658 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
1659 def _PRE : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1660 (ins addrmode2:$addr), IndexModePre, LdFrm, itin,
1661 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1663 // {13} 1 == Rm, 0 == imm12
1667 let Inst{25} = addr{13};
1668 let Inst{23} = addr{12};
1669 let Inst{19-16} = addr{17-14};
1670 let Inst{11-0} = addr{11-0};
1672 def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1673 (ins GPR:$Rn, am2offset:$offset),
1674 IndexModePost, LdFrm, itin,
1675 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1676 // {13} 1 == Rm, 0 == imm12
1681 let Inst{25} = offset{13};
1682 let Inst{23} = offset{12};
1683 let Inst{19-16} = Rn;
1684 let Inst{11-0} = offset{11-0};
1688 let mayLoad = 1, neverHasSideEffects = 1 in {
1689 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
1690 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
1693 multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
1694 def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1695 (ins addrmode3:$addr), IndexModePre,
1697 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1699 let Inst{23} = addr{8}; // U bit
1700 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1701 let Inst{19-16} = addr{12-9}; // Rn
1702 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1703 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1705 def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1706 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1708 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1711 let Inst{23} = offset{8}; // U bit
1712 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1713 let Inst{19-16} = Rn;
1714 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1715 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1719 let mayLoad = 1, neverHasSideEffects = 1 in {
1720 defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
1721 defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
1722 defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
1723 let hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1724 defm LDRD : AI3_ldridx<0b1101, 0, "ldrd", IIC_iLoad_d_ru>;
1725 } // mayLoad = 1, neverHasSideEffects = 1
1727 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1728 let mayLoad = 1, neverHasSideEffects = 1 in {
1729 def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$dst, GPR:$base_wb),
1730 (ins GPR:$base, am2offset:$offset), IndexModePost,
1731 LdFrm, IIC_iLoad_ru,
1732 "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1733 let Inst{21} = 1; // overwrite
1735 def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1736 (ins GPR:$base, am2offset:$offset), IndexModePost,
1737 LdFrm, IIC_iLoad_bh_ru,
1738 "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1739 let Inst{21} = 1; // overwrite
1741 def LDRSBT : AI3ldstidx<0b1101, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1742 (ins GPR:$base, am3offset:$offset), IndexModePost,
1743 LdMiscFrm, IIC_iLoad_bh_ru,
1744 "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1745 let Inst{21} = 1; // overwrite
1747 def LDRHT : AI3ldstidx<0b1011, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1748 (ins GPR:$base, am3offset:$offset), IndexModePost,
1749 LdMiscFrm, IIC_iLoad_bh_ru,
1750 "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1751 let Inst{21} = 1; // overwrite
1753 def LDRSHT : AI3ldstidx<0b1111, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1754 (ins GPR:$base, am3offset:$offset), IndexModePost,
1755 LdMiscFrm, IIC_iLoad_bh_ru,
1756 "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1757 let Inst{21} = 1; // overwrite
1763 // Stores with truncate
1764 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
1765 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
1766 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
1769 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
1770 isCodeGenOnly = 1 in // $src2 doesn't exist in asm string
1771 def STRD : AI3str<0b1111, (outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
1772 StMiscFrm, IIC_iStore_d_r,
1773 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
1776 def STR_PRE : AI2stridx<0, 1, (outs GPR:$Rn_wb),
1777 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1778 IndexModePre, StFrm, IIC_iStore_ru,
1779 "str", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1781 (pre_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1783 def STR_POST : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1784 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1785 IndexModePost, StFrm, IIC_iStore_ru,
1786 "str", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1788 (post_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1790 def STRB_PRE : AI2stridx<1, 1, (outs GPR:$Rn_wb),
1791 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1792 IndexModePre, StFrm, IIC_iStore_bh_ru,
1793 "strb", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1794 [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
1795 GPR:$Rn, am2offset:$offset))]>;
1796 def STRB_POST: AI2stridx<1, 0, (outs GPR:$Rn_wb),
1797 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1798 IndexModePost, StFrm, IIC_iStore_bh_ru,
1799 "strb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1800 [(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
1801 GPR:$Rn, am2offset:$offset))]>;
1803 def STRH_PRE : AI3stridx<0b1011, 0, 1, (outs GPR:$Rn_wb),
1804 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1805 IndexModePre, StMiscFrm, IIC_iStore_ru,
1806 "strh", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1808 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
1810 def STRH_POST: AI3stridx<0b1011, 0, 0, (outs GPR:$Rn_wb),
1811 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1812 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
1813 "strh", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1814 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
1815 GPR:$Rn, am3offset:$offset))]>;
1817 // For disassembly only
1818 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1819 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1820 StMiscFrm, IIC_iStore_d_ru,
1821 "strd", "\t$src1, $src2, [$base, $offset]!",
1822 "$base = $base_wb", []>;
1824 // For disassembly only
1825 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1826 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1827 StMiscFrm, IIC_iStore_d_ru,
1828 "strd", "\t$src1, $src2, [$base], $offset",
1829 "$base = $base_wb", []>;
1831 // STRT, STRBT, and STRHT are for disassembly only.
1833 def STRT : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1834 (ins GPR:$Rt, GPR:$Rn,am2offset:$offset),
1835 IndexModePost, StFrm, IIC_iStore_ru,
1836 "strt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1837 [/* For disassembly only; pattern left blank */]> {
1838 let Inst{21} = 1; // overwrite
1841 def STRBT : AI2stridx<1, 0, (outs GPR:$Rn_wb),
1842 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1843 IndexModePost, StFrm, IIC_iStore_bh_ru,
1844 "strbt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1845 [/* For disassembly only; pattern left blank */]> {
1846 let Inst{21} = 1; // overwrite
1849 def STRHT: AI3sthpo<(outs GPR:$base_wb),
1850 (ins GPR:$src, GPR:$base,am3offset:$offset),
1851 StMiscFrm, IIC_iStore_bh_ru,
1852 "strht", "\t$src, [$base], $offset", "$base = $base_wb",
1853 [/* For disassembly only; pattern left blank */]> {
1854 let Inst{21} = 1; // overwrite
1857 //===----------------------------------------------------------------------===//
1858 // Load / store multiple Instructions.
1861 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
1862 InstrItinClass itin, InstrItinClass itin_upd> {
1864 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1865 IndexModeNone, f, itin,
1866 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
1867 let Inst{24-23} = 0b01; // Increment After
1868 let Inst{21} = 0; // No writeback
1869 let Inst{20} = L_bit;
1872 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1873 IndexModeUpd, f, itin_upd,
1874 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1875 let Inst{24-23} = 0b01; // Increment After
1876 let Inst{21} = 1; // Writeback
1877 let Inst{20} = L_bit;
1880 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1881 IndexModeNone, f, itin,
1882 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
1883 let Inst{24-23} = 0b00; // Decrement After
1884 let Inst{21} = 0; // No writeback
1885 let Inst{20} = L_bit;
1888 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1889 IndexModeUpd, f, itin_upd,
1890 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1891 let Inst{24-23} = 0b00; // Decrement After
1892 let Inst{21} = 1; // Writeback
1893 let Inst{20} = L_bit;
1896 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1897 IndexModeNone, f, itin,
1898 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
1899 let Inst{24-23} = 0b10; // Decrement Before
1900 let Inst{21} = 0; // No writeback
1901 let Inst{20} = L_bit;
1904 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1905 IndexModeUpd, f, itin_upd,
1906 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1907 let Inst{24-23} = 0b10; // Decrement Before
1908 let Inst{21} = 1; // Writeback
1909 let Inst{20} = L_bit;
1912 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1913 IndexModeNone, f, itin,
1914 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
1915 let Inst{24-23} = 0b11; // Increment Before
1916 let Inst{21} = 0; // No writeback
1917 let Inst{20} = L_bit;
1920 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1921 IndexModeUpd, f, itin_upd,
1922 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1923 let Inst{24-23} = 0b11; // Increment Before
1924 let Inst{21} = 1; // Writeback
1925 let Inst{20} = L_bit;
1929 let neverHasSideEffects = 1 in {
1931 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1932 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
1934 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1935 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
1937 } // neverHasSideEffects
1939 // Load / Store Multiple Mnemonic Aliases
1940 def : MnemonicAlias<"ldm", "ldmia">;
1941 def : MnemonicAlias<"stm", "stmia">;
1943 // FIXME: remove when we have a way to marking a MI with these properties.
1944 // FIXME: Should pc be an implicit operand like PICADD, etc?
1945 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1946 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1947 def LDMIA_RET : ARMPseudoInst<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
1948 reglist:$regs, variable_ops),
1949 Size4Bytes, IIC_iLoad_mBr, []>,
1950 RegConstraint<"$Rn = $wb">;
1952 //===----------------------------------------------------------------------===//
1953 // Move Instructions.
1956 let neverHasSideEffects = 1 in
1957 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
1958 "mov", "\t$Rd, $Rm", []>, UnaryDP {
1962 let Inst{11-4} = 0b00000000;
1965 let Inst{15-12} = Rd;
1968 // A version for the smaller set of tail call registers.
1969 let neverHasSideEffects = 1 in
1970 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
1971 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
1975 let Inst{11-4} = 0b00000000;
1978 let Inst{15-12} = Rd;
1981 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
1982 DPSoRegFrm, IIC_iMOVsr,
1983 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
1987 let Inst{15-12} = Rd;
1988 let Inst{11-0} = src;
1992 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1993 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
1994 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
1998 let Inst{15-12} = Rd;
1999 let Inst{19-16} = 0b0000;
2000 let Inst{11-0} = imm;
2003 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2004 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins i32imm_hilo16:$imm),
2006 "movw", "\t$Rd, $imm",
2007 [(set GPR:$Rd, imm0_65535:$imm)]>,
2008 Requires<[IsARM, HasV6T2]>, UnaryDP {
2011 let Inst{15-12} = Rd;
2012 let Inst{11-0} = imm{11-0};
2013 let Inst{19-16} = imm{15-12};
2018 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2019 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2021 let Constraints = "$src = $Rd" in {
2022 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, i32imm_hilo16:$imm),
2024 "movt", "\t$Rd, $imm",
2026 (or (and GPR:$src, 0xffff),
2027 lo16AllZero:$imm))]>, UnaryDP,
2028 Requires<[IsARM, HasV6T2]> {
2031 let Inst{15-12} = Rd;
2032 let Inst{11-0} = imm{11-0};
2033 let Inst{19-16} = imm{15-12};
2038 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2039 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2043 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2044 Requires<[IsARM, HasV6T2]>;
2046 let Uses = [CPSR] in
2047 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2048 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2051 // These aren't really mov instructions, but we have to define them this way
2052 // due to flag operands.
2054 let Defs = [CPSR] in {
2055 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2056 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2058 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2059 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2063 //===----------------------------------------------------------------------===//
2064 // Extend Instructions.
2069 defm SXTB : AI_ext_rrot<0b01101010,
2070 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2071 defm SXTH : AI_ext_rrot<0b01101011,
2072 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2074 defm SXTAB : AI_exta_rrot<0b01101010,
2075 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2076 defm SXTAH : AI_exta_rrot<0b01101011,
2077 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2079 // For disassembly only
2080 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2082 // For disassembly only
2083 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2087 let AddedComplexity = 16 in {
2088 defm UXTB : AI_ext_rrot<0b01101110,
2089 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2090 defm UXTH : AI_ext_rrot<0b01101111,
2091 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2092 defm UXTB16 : AI_ext_rrot<0b01101100,
2093 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2095 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2096 // The transformation should probably be done as a combiner action
2097 // instead so we can include a check for masking back in the upper
2098 // eight bits of the source into the lower eight bits of the result.
2099 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2100 // (UXTB16r_rot GPR:$Src, 24)>;
2101 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2102 (UXTB16r_rot GPR:$Src, 8)>;
2104 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2105 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2106 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2107 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2110 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2111 // For disassembly only
2112 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2115 def SBFX : I<(outs GPR:$Rd),
2116 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2117 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2118 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2119 Requires<[IsARM, HasV6T2]> {
2124 let Inst{27-21} = 0b0111101;
2125 let Inst{6-4} = 0b101;
2126 let Inst{20-16} = width;
2127 let Inst{15-12} = Rd;
2128 let Inst{11-7} = lsb;
2132 def UBFX : I<(outs GPR:$Rd),
2133 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2134 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2135 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2136 Requires<[IsARM, HasV6T2]> {
2141 let Inst{27-21} = 0b0111111;
2142 let Inst{6-4} = 0b101;
2143 let Inst{20-16} = width;
2144 let Inst{15-12} = Rd;
2145 let Inst{11-7} = lsb;
2149 //===----------------------------------------------------------------------===//
2150 // Arithmetic Instructions.
2153 defm ADD : AsI1_bin_irs<0b0100, "add",
2154 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2155 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
2156 defm SUB : AsI1_bin_irs<0b0010, "sub",
2157 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2158 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
2160 // ADD and SUB with 's' bit set.
2161 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
2162 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2163 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
2164 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
2165 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2166 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
2168 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
2169 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
2170 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
2171 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
2173 // ADC and SUBC with 's' bit set.
2174 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
2175 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
2176 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
2177 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
2179 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2180 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
2181 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
2186 let Inst{15-12} = Rd;
2187 let Inst{19-16} = Rn;
2188 let Inst{11-0} = imm;
2191 // The reg/reg form is only defined for the disassembler; for codegen it is
2192 // equivalent to SUBrr.
2193 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2194 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
2195 [/* For disassembly only; pattern left blank */]> {
2199 let Inst{11-4} = 0b00000000;
2202 let Inst{15-12} = Rd;
2203 let Inst{19-16} = Rn;
2206 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2207 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2208 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
2213 let Inst{11-0} = shift;
2214 let Inst{15-12} = Rd;
2215 let Inst{19-16} = Rn;
2218 // RSB with 's' bit set.
2219 let isCodeGenOnly = 1, Defs = [CPSR] in {
2220 def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2221 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
2222 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
2228 let Inst{15-12} = Rd;
2229 let Inst{19-16} = Rn;
2230 let Inst{11-0} = imm;
2232 def RSBSrr : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2233 IIC_iALUr, "rsbs", "\t$Rd, $Rn, $Rm",
2234 [/* For disassembly only; pattern left blank */]> {
2238 let Inst{11-4} = 0b00000000;
2242 let Inst{15-12} = Rd;
2243 let Inst{19-16} = Rn;
2245 def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2246 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
2247 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
2253 let Inst{11-0} = shift;
2254 let Inst{15-12} = Rd;
2255 let Inst{19-16} = Rn;
2259 let Uses = [CPSR] in {
2260 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2261 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2262 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2268 let Inst{15-12} = Rd;
2269 let Inst{19-16} = Rn;
2270 let Inst{11-0} = imm;
2272 // The reg/reg form is only defined for the disassembler; for codegen it is
2273 // equivalent to SUBrr.
2274 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2275 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2276 [/* For disassembly only; pattern left blank */]> {
2280 let Inst{11-4} = 0b00000000;
2283 let Inst{15-12} = Rd;
2284 let Inst{19-16} = Rn;
2286 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2287 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2288 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2294 let Inst{11-0} = shift;
2295 let Inst{15-12} = Rd;
2296 let Inst{19-16} = Rn;
2300 // FIXME: Allow these to be predicated.
2301 let isCodeGenOnly = 1, Defs = [CPSR], Uses = [CPSR] in {
2302 def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2303 DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
2304 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2311 let Inst{15-12} = Rd;
2312 let Inst{19-16} = Rn;
2313 let Inst{11-0} = imm;
2315 def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2316 DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
2317 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2324 let Inst{11-0} = shift;
2325 let Inst{15-12} = Rd;
2326 let Inst{19-16} = Rn;
2330 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2331 // The assume-no-carry-in form uses the negation of the input since add/sub
2332 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2333 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2335 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2336 (SUBri GPR:$src, so_imm_neg:$imm)>;
2337 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2338 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2339 // The with-carry-in form matches bitwise not instead of the negation.
2340 // Effectively, the inverse interpretation of the carry flag already accounts
2341 // for part of the negation.
2342 def : ARMPat<(adde GPR:$src, so_imm_not:$imm),
2343 (SBCri GPR:$src, so_imm_not:$imm)>;
2345 // Note: These are implemented in C++ code, because they have to generate
2346 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2348 // (mul X, 2^n+1) -> (add (X << n), X)
2349 // (mul X, 2^n-1) -> (rsb X, (X << n))
2351 // ARM Arithmetic Instruction -- for disassembly only
2352 // GPR:$dst = GPR:$a op GPR:$b
2353 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2354 list<dag> pattern = [/* For disassembly only; pattern left blank */],
2355 dag iops = (ins GPR:$Rn, GPR:$Rm), string asm = "\t$Rd, $Rn, $Rm">
2356 : AI<(outs GPR:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
2360 let Inst{27-20} = op27_20;
2361 let Inst{11-4} = op11_4;
2362 let Inst{19-16} = Rn;
2363 let Inst{15-12} = Rd;
2367 // Saturating add/subtract -- for disassembly only
2369 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2370 [(set GPR:$Rd, (int_arm_qadd GPR:$Rm, GPR:$Rn))],
2371 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2372 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2373 [(set GPR:$Rd, (int_arm_qsub GPR:$Rm, GPR:$Rn))],
2374 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2375 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [], (ins GPR:$Rm, GPR:$Rn),
2377 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [], (ins GPR:$Rm, GPR:$Rn),
2380 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2381 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2382 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2383 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2384 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2385 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2386 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2387 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2388 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2389 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2390 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2391 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2393 // Signed/Unsigned add/subtract -- for disassembly only
2395 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2396 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2397 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2398 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2399 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2400 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2401 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2402 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2403 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2404 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2405 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2406 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2408 // Signed/Unsigned halving add/subtract -- for disassembly only
2410 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2411 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2412 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2413 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2414 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2415 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2416 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2417 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2418 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2419 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2420 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2421 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2423 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2425 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2426 MulFrm /* for convenience */, NoItinerary, "usad8",
2427 "\t$Rd, $Rn, $Rm", []>,
2428 Requires<[IsARM, HasV6]> {
2432 let Inst{27-20} = 0b01111000;
2433 let Inst{15-12} = 0b1111;
2434 let Inst{7-4} = 0b0001;
2435 let Inst{19-16} = Rd;
2436 let Inst{11-8} = Rm;
2439 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2440 MulFrm /* for convenience */, NoItinerary, "usada8",
2441 "\t$Rd, $Rn, $Rm, $Ra", []>,
2442 Requires<[IsARM, HasV6]> {
2447 let Inst{27-20} = 0b01111000;
2448 let Inst{7-4} = 0b0001;
2449 let Inst{19-16} = Rd;
2450 let Inst{15-12} = Ra;
2451 let Inst{11-8} = Rm;
2455 // Signed/Unsigned saturate -- for disassembly only
2457 def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2458 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2459 [/* For disassembly only; pattern left blank */]> {
2464 let Inst{27-21} = 0b0110101;
2465 let Inst{5-4} = 0b01;
2466 let Inst{20-16} = sat_imm;
2467 let Inst{15-12} = Rd;
2468 let Inst{11-7} = sh{7-3};
2469 let Inst{6} = sh{0};
2473 def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm,
2474 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2475 [/* For disassembly only; pattern left blank */]> {
2479 let Inst{27-20} = 0b01101010;
2480 let Inst{11-4} = 0b11110011;
2481 let Inst{15-12} = Rd;
2482 let Inst{19-16} = sat_imm;
2486 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2487 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2488 [/* For disassembly only; pattern left blank */]> {
2493 let Inst{27-21} = 0b0110111;
2494 let Inst{5-4} = 0b01;
2495 let Inst{15-12} = Rd;
2496 let Inst{11-7} = sh{7-3};
2497 let Inst{6} = sh{0};
2498 let Inst{20-16} = sat_imm;
2502 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2503 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2504 [/* For disassembly only; pattern left blank */]> {
2508 let Inst{27-20} = 0b01101110;
2509 let Inst{11-4} = 0b11110011;
2510 let Inst{15-12} = Rd;
2511 let Inst{19-16} = sat_imm;
2515 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2516 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2518 //===----------------------------------------------------------------------===//
2519 // Bitwise Instructions.
2522 defm AND : AsI1_bin_irs<0b0000, "and",
2523 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2524 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2525 defm ORR : AsI1_bin_irs<0b1100, "orr",
2526 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2527 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2528 defm EOR : AsI1_bin_irs<0b0001, "eor",
2529 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2530 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2531 defm BIC : AsI1_bin_irs<0b1110, "bic",
2532 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2533 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2535 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2536 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2537 "bfc", "\t$Rd, $imm", "$src = $Rd",
2538 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2539 Requires<[IsARM, HasV6T2]> {
2542 let Inst{27-21} = 0b0111110;
2543 let Inst{6-0} = 0b0011111;
2544 let Inst{15-12} = Rd;
2545 let Inst{11-7} = imm{4-0}; // lsb
2546 let Inst{20-16} = imm{9-5}; // width
2549 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2550 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2551 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2552 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2553 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2554 bf_inv_mask_imm:$imm))]>,
2555 Requires<[IsARM, HasV6T2]> {
2559 let Inst{27-21} = 0b0111110;
2560 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2561 let Inst{15-12} = Rd;
2562 let Inst{11-7} = imm{4-0}; // lsb
2563 let Inst{20-16} = imm{9-5}; // width
2567 // GNU as only supports this form of bfi (w/ 4 arguments)
2568 let isAsmParserOnly = 1 in
2569 def BFI4p : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn,
2570 lsb_pos_imm:$lsb, width_imm:$width),
2571 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2572 "bfi", "\t$Rd, $Rn, $lsb, $width", "$src = $Rd",
2573 []>, Requires<[IsARM, HasV6T2]> {
2578 let Inst{27-21} = 0b0111110;
2579 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2580 let Inst{15-12} = Rd;
2581 let Inst{11-7} = lsb;
2582 let Inst{20-16} = width; // Custom encoder => lsb+width-1
2586 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2587 "mvn", "\t$Rd, $Rm",
2588 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2592 let Inst{19-16} = 0b0000;
2593 let Inst{11-4} = 0b00000000;
2594 let Inst{15-12} = Rd;
2597 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2598 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2599 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2603 let Inst{19-16} = 0b0000;
2604 let Inst{15-12} = Rd;
2605 let Inst{11-0} = shift;
2607 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2608 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2609 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2610 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2614 let Inst{19-16} = 0b0000;
2615 let Inst{15-12} = Rd;
2616 let Inst{11-0} = imm;
2619 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2620 (BICri GPR:$src, so_imm_not:$imm)>;
2622 //===----------------------------------------------------------------------===//
2623 // Multiply Instructions.
2625 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2626 string opc, string asm, list<dag> pattern>
2627 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2631 let Inst{19-16} = Rd;
2632 let Inst{11-8} = Rm;
2635 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2636 string opc, string asm, list<dag> pattern>
2637 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2642 let Inst{19-16} = RdHi;
2643 let Inst{15-12} = RdLo;
2644 let Inst{11-8} = Rm;
2648 let isCommutable = 1 in {
2649 let Constraints = "@earlyclobber $Rd" in
2650 def MULv5: ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
2651 pred:$p, cc_out:$s),
2652 Size4Bytes, IIC_iMUL32,
2653 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2654 Requires<[IsARM, NoV6]>;
2656 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2657 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2658 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2659 Requires<[IsARM, HasV6]>;
2662 let Constraints = "@earlyclobber $Rd" in
2663 def MLAv5: ARMPseudoInst<(outs GPR:$Rd),
2664 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
2665 Size4Bytes, IIC_iMAC32,
2666 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2667 Requires<[IsARM, NoV6]> {
2669 let Inst{15-12} = Ra;
2671 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2672 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2673 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2674 Requires<[IsARM, HasV6]> {
2676 let Inst{15-12} = Ra;
2679 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2680 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
2681 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
2682 Requires<[IsARM, HasV6T2]> {
2687 let Inst{19-16} = Rd;
2688 let Inst{15-12} = Ra;
2689 let Inst{11-8} = Rm;
2693 // Extra precision multiplies with low / high results
2695 let neverHasSideEffects = 1 in {
2696 let isCommutable = 1 in {
2697 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2698 def SMULLv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2699 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2700 Size4Bytes, IIC_iMUL64, []>,
2701 Requires<[IsARM, NoV6]>;
2703 def UMULLv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2704 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2705 Size4Bytes, IIC_iMUL64, []>,
2706 Requires<[IsARM, NoV6]>;
2709 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2710 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2711 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2712 Requires<[IsARM, HasV6]>;
2714 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2715 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2716 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2717 Requires<[IsARM, HasV6]>;
2720 // Multiply + accumulate
2721 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2722 def SMLALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2723 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2724 Size4Bytes, IIC_iMAC64, []>,
2725 Requires<[IsARM, NoV6]>;
2726 def UMLALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2727 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2728 Size4Bytes, IIC_iMAC64, []>,
2729 Requires<[IsARM, NoV6]>;
2730 def UMAALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2731 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2732 Size4Bytes, IIC_iMAC64, []>,
2733 Requires<[IsARM, NoV6]>;
2737 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2738 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2739 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2740 Requires<[IsARM, HasV6]>;
2741 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2742 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2743 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2744 Requires<[IsARM, HasV6]>;
2746 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2747 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2748 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2749 Requires<[IsARM, HasV6]> {
2754 let Inst{19-16} = RdLo;
2755 let Inst{15-12} = RdHi;
2756 let Inst{11-8} = Rm;
2759 } // neverHasSideEffects
2761 // Most significant word multiply
2762 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2763 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2764 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2765 Requires<[IsARM, HasV6]> {
2766 let Inst{15-12} = 0b1111;
2769 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2770 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2771 [/* For disassembly only; pattern left blank */]>,
2772 Requires<[IsARM, HasV6]> {
2773 let Inst{15-12} = 0b1111;
2776 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2777 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2778 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2779 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2780 Requires<[IsARM, HasV6]>;
2782 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2783 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2784 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2785 [/* For disassembly only; pattern left blank */]>,
2786 Requires<[IsARM, HasV6]>;
2788 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2789 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2790 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2791 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2792 Requires<[IsARM, HasV6]>;
2794 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2795 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2796 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2797 [/* For disassembly only; pattern left blank */]>,
2798 Requires<[IsARM, HasV6]>;
2800 multiclass AI_smul<string opc, PatFrag opnode> {
2801 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2802 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2803 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2804 (sext_inreg GPR:$Rm, i16)))]>,
2805 Requires<[IsARM, HasV5TE]>;
2807 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2808 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2809 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2810 (sra GPR:$Rm, (i32 16))))]>,
2811 Requires<[IsARM, HasV5TE]>;
2813 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2814 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2815 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2816 (sext_inreg GPR:$Rm, i16)))]>,
2817 Requires<[IsARM, HasV5TE]>;
2819 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2820 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2821 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2822 (sra GPR:$Rm, (i32 16))))]>,
2823 Requires<[IsARM, HasV5TE]>;
2825 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2826 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2827 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2828 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2829 Requires<[IsARM, HasV5TE]>;
2831 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2832 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2833 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2834 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2835 Requires<[IsARM, HasV5TE]>;
2839 multiclass AI_smla<string opc, PatFrag opnode> {
2840 def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
2841 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2842 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2843 [(set GPR:$Rd, (add GPR:$Ra,
2844 (opnode (sext_inreg GPR:$Rn, i16),
2845 (sext_inreg GPR:$Rm, i16))))]>,
2846 Requires<[IsARM, HasV5TE]>;
2848 def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd),
2849 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2850 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2851 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2852 (sra GPR:$Rm, (i32 16)))))]>,
2853 Requires<[IsARM, HasV5TE]>;
2855 def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd),
2856 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2857 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2858 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2859 (sext_inreg GPR:$Rm, i16))))]>,
2860 Requires<[IsARM, HasV5TE]>;
2862 def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
2863 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2864 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2865 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2866 (sra GPR:$Rm, (i32 16)))))]>,
2867 Requires<[IsARM, HasV5TE]>;
2869 def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd),
2870 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2871 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2872 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2873 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2874 Requires<[IsARM, HasV5TE]>;
2876 def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd),
2877 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2878 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2879 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2880 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2881 Requires<[IsARM, HasV5TE]>;
2884 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2885 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2887 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2888 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2889 (ins GPR:$Rn, GPR:$Rm),
2890 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2891 [/* For disassembly only; pattern left blank */]>,
2892 Requires<[IsARM, HasV5TE]>;
2894 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2895 (ins GPR:$Rn, GPR:$Rm),
2896 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2897 [/* For disassembly only; pattern left blank */]>,
2898 Requires<[IsARM, HasV5TE]>;
2900 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2901 (ins GPR:$Rn, GPR:$Rm),
2902 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2903 [/* For disassembly only; pattern left blank */]>,
2904 Requires<[IsARM, HasV5TE]>;
2906 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2907 (ins GPR:$Rn, GPR:$Rm),
2908 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2909 [/* For disassembly only; pattern left blank */]>,
2910 Requires<[IsARM, HasV5TE]>;
2912 // Helper class for AI_smld -- for disassembly only
2913 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2914 InstrItinClass itin, string opc, string asm>
2915 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2922 let Inst{21-20} = 0b00;
2923 let Inst{22} = long;
2924 let Inst{27-23} = 0b01110;
2925 let Inst{11-8} = Rm;
2928 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2929 InstrItinClass itin, string opc, string asm>
2930 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2932 let Inst{15-12} = 0b1111;
2933 let Inst{19-16} = Rd;
2935 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2936 InstrItinClass itin, string opc, string asm>
2937 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2939 let Inst{15-12} = Ra;
2941 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2942 InstrItinClass itin, string opc, string asm>
2943 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2946 let Inst{19-16} = RdHi;
2947 let Inst{15-12} = RdLo;
2950 multiclass AI_smld<bit sub, string opc> {
2952 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2953 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
2955 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2956 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
2958 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
2959 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2960 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
2962 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
2963 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2964 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
2968 defm SMLA : AI_smld<0, "smla">;
2969 defm SMLS : AI_smld<1, "smls">;
2971 multiclass AI_sdml<bit sub, string opc> {
2973 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2974 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
2975 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2976 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
2979 defm SMUA : AI_sdml<0, "smua">;
2980 defm SMUS : AI_sdml<1, "smus">;
2982 //===----------------------------------------------------------------------===//
2983 // Misc. Arithmetic Instructions.
2986 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
2987 IIC_iUNAr, "clz", "\t$Rd, $Rm",
2988 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
2990 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2991 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
2992 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
2993 Requires<[IsARM, HasV6T2]>;
2995 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2996 IIC_iUNAr, "rev", "\t$Rd, $Rm",
2997 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
2999 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3000 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3002 (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
3003 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
3004 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
3005 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
3006 Requires<[IsARM, HasV6]>;
3008 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3009 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3012 (or (srl GPR:$Rm, (i32 8)),
3013 (shl GPR:$Rm, (i32 8))), i16))]>,
3014 Requires<[IsARM, HasV6]>;
3016 def : ARMV6Pat<(sext_inreg (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
3017 (shl GPR:$Rm, (i32 8))), i16),
3020 // Need the AddedComplexity or else MOVs + REV would be chosen.
3021 let AddedComplexity = 5 in
3022 def : ARMV6Pat<(sra (bswap GPR:$Rm), (i32 16)), (REVSH GPR:$Rm)>;
3024 def lsl_shift_imm : SDNodeXForm<imm, [{
3025 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
3026 return CurDAG->getTargetConstant(Sh, MVT::i32);
3029 def lsl_amt : PatLeaf<(i32 imm), [{
3030 return (N->getZExtValue() < 32);
3033 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
3034 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3035 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3036 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
3037 (and (shl GPR:$Rm, lsl_amt:$sh),
3039 Requires<[IsARM, HasV6]>;
3041 // Alternate cases for PKHBT where identities eliminate some nodes.
3042 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
3043 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
3044 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
3045 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
3047 def asr_shift_imm : SDNodeXForm<imm, [{
3048 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
3049 return CurDAG->getTargetConstant(Sh, MVT::i32);
3052 def asr_amt : PatLeaf<(i32 imm), [{
3053 return (N->getZExtValue() <= 32);
3056 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3057 // will match the pattern below.
3058 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
3059 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3060 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3061 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
3062 (and (sra GPR:$Rm, asr_amt:$sh),
3064 Requires<[IsARM, HasV6]>;
3066 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3067 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3068 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
3069 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
3070 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
3071 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
3072 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
3074 //===----------------------------------------------------------------------===//
3075 // Comparison Instructions...
3078 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3079 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3080 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3082 // ARMcmpZ can re-use the above instruction definitions.
3083 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3084 (CMPri GPR:$src, so_imm:$imm)>;
3085 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3086 (CMPrr GPR:$src, GPR:$rhs)>;
3087 def : ARMPat<(ARMcmpZ GPR:$src, so_reg:$rhs),
3088 (CMPrs GPR:$src, so_reg:$rhs)>;
3090 // FIXME: We have to be careful when using the CMN instruction and comparison
3091 // with 0. One would expect these two pieces of code should give identical
3107 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3108 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3109 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3110 // value of r0 and the carry bit (because the "carry bit" parameter to
3111 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3112 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3113 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3114 // parameter to AddWithCarry is defined as 0).
3116 // When x is 0 and unsigned:
3120 // ~x + 1 = 0x1 0000 0000
3121 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3123 // Therefore, we should disable CMN when comparing against zero, until we can
3124 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3125 // when it's a comparison which doesn't look at the 'carry' flag).
3127 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3129 // This is related to <rdar://problem/7569620>.
3131 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3132 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3134 // Note that TST/TEQ don't set all the same flags that CMP does!
3135 defm TST : AI1_cmp_irs<0b1000, "tst",
3136 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3137 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3138 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3139 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3140 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3142 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
3143 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3144 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
3146 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3147 // (CMNri GPR:$src, so_imm_neg:$imm)>;
3149 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3150 (CMNzri GPR:$src, so_imm_neg:$imm)>;
3152 // Pseudo i64 compares for some floating point compares.
3153 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3155 def BCCi64 : PseudoInst<(outs),
3156 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3158 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3160 def BCCZi64 : PseudoInst<(outs),
3161 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3162 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3163 } // usesCustomInserter
3166 // Conditional moves
3167 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3168 // a two-value operand where a dag node expects two operands. :(
3169 let neverHasSideEffects = 1 in {
3170 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3171 Size4Bytes, IIC_iCMOVr,
3172 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3173 RegConstraint<"$false = $Rd">;
3174 def MOVCCs : ARMPseudoInst<(outs GPR:$Rd),
3175 (ins GPR:$false, so_reg:$shift, pred:$p),
3176 Size4Bytes, IIC_iCMOVsr,
3177 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
3178 RegConstraint<"$false = $Rd">;
3180 let isMoveImm = 1 in
3181 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3182 (ins GPR:$false, i32imm_hilo16:$imm, pred:$p),
3183 Size4Bytes, IIC_iMOVi,
3185 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3187 let isMoveImm = 1 in
3188 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3189 (ins GPR:$false, so_imm:$imm, pred:$p),
3190 Size4Bytes, IIC_iCMOVi,
3191 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3192 RegConstraint<"$false = $Rd">;
3194 // Two instruction predicate mov immediate.
3195 let isMoveImm = 1 in
3196 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
3197 (ins GPR:$false, i32imm:$src, pred:$p),
3198 Size8Bytes, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3200 let isMoveImm = 1 in
3201 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
3202 (ins GPR:$false, so_imm:$imm, pred:$p),
3203 Size4Bytes, IIC_iCMOVi,
3204 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3205 RegConstraint<"$false = $Rd">;
3206 } // neverHasSideEffects
3208 //===----------------------------------------------------------------------===//
3209 // Atomic operations intrinsics
3212 def memb_opt : Operand<i32> {
3213 let PrintMethod = "printMemBOption";
3214 let ParserMatchClass = MemBarrierOptOperand;
3217 // memory barriers protect the atomic sequences
3218 let hasSideEffects = 1 in {
3219 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3220 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3221 Requires<[IsARM, HasDB]> {
3223 let Inst{31-4} = 0xf57ff05;
3224 let Inst{3-0} = opt;
3228 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3230 [/* For disassembly only; pattern left blank */]>,
3231 Requires<[IsARM, HasDB]> {
3233 let Inst{31-4} = 0xf57ff04;
3234 let Inst{3-0} = opt;
3237 // ISB has only full system option -- for disassembly only
3238 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
3239 Requires<[IsARM, HasDB]> {
3240 let Inst{31-4} = 0xf57ff06;
3241 let Inst{3-0} = 0b1111;
3244 let usesCustomInserter = 1 in {
3245 let Uses = [CPSR] in {
3246 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
3247 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3248 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
3249 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
3250 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3251 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
3252 def ATOMIC_LOAD_AND_I8 : PseudoInst<
3253 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3254 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
3255 def ATOMIC_LOAD_OR_I8 : PseudoInst<
3256 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3257 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
3258 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
3259 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3260 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
3261 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
3262 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3263 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
3264 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
3265 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3266 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
3267 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
3268 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3269 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
3270 def ATOMIC_LOAD_AND_I16 : PseudoInst<
3271 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3272 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
3273 def ATOMIC_LOAD_OR_I16 : PseudoInst<
3274 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3275 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
3276 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
3277 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3278 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
3279 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
3280 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3281 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
3282 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
3283 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3284 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
3285 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
3286 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3287 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
3288 def ATOMIC_LOAD_AND_I32 : PseudoInst<
3289 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3290 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
3291 def ATOMIC_LOAD_OR_I32 : PseudoInst<
3292 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3293 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
3294 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
3295 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3296 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
3297 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
3298 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3299 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
3301 def ATOMIC_SWAP_I8 : PseudoInst<
3302 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3303 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3304 def ATOMIC_SWAP_I16 : PseudoInst<
3305 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3306 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3307 def ATOMIC_SWAP_I32 : PseudoInst<
3308 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3309 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3311 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3312 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3313 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3314 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3315 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3316 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3317 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3318 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3319 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3323 let mayLoad = 1 in {
3324 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3325 "ldrexb", "\t$Rt, $addr", []>;
3326 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3327 "ldrexh", "\t$Rt, $addr", []>;
3328 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3329 "ldrex", "\t$Rt, $addr", []>;
3330 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode7:$addr),
3331 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []>;
3334 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3335 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3336 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
3337 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3338 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
3339 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3340 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
3341 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3342 (ins GPR:$Rt, GPR:$Rt2, addrmode7:$addr),
3343 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []>;
3346 // Clear-Exclusive is for disassembly only.
3347 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3348 [/* For disassembly only; pattern left blank */]>,
3349 Requires<[IsARM, HasV7]> {
3350 let Inst{31-0} = 0b11110101011111111111000000011111;
3353 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3354 let mayLoad = 1 in {
3355 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3356 [/* For disassembly only; pattern left blank */]>;
3357 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3358 [/* For disassembly only; pattern left blank */]>;
3361 //===----------------------------------------------------------------------===//
3362 // Coprocessor Instructions.
3365 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3366 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3367 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3368 [/* For disassembly only; pattern left blank */]> {
3376 let Inst{3-0} = CRm;
3378 let Inst{7-5} = opc2;
3379 let Inst{11-8} = cop;
3380 let Inst{15-12} = CRd;
3381 let Inst{19-16} = CRn;
3382 let Inst{23-20} = opc1;
3385 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3386 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3387 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3388 [/* For disassembly only; pattern left blank */]> {
3389 let Inst{31-28} = 0b1111;
3397 let Inst{3-0} = CRm;
3399 let Inst{7-5} = opc2;
3400 let Inst{11-8} = cop;
3401 let Inst{15-12} = CRd;
3402 let Inst{19-16} = CRn;
3403 let Inst{23-20} = opc1;
3406 class ACI<dag oops, dag iops, string opc, string asm>
3407 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
3408 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3409 let Inst{27-25} = 0b110;
3412 multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
3414 def _OFFSET : ACI<(outs),
3415 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3416 opc, "\tp$cop, cr$CRd, $addr"> {
3417 let Inst{31-28} = op31_28;
3418 let Inst{24} = 1; // P = 1
3419 let Inst{21} = 0; // W = 0
3420 let Inst{22} = 0; // D = 0
3421 let Inst{20} = load;
3424 def _PRE : ACI<(outs),
3425 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3426 opc, "\tp$cop, cr$CRd, $addr!"> {
3427 let Inst{31-28} = op31_28;
3428 let Inst{24} = 1; // P = 1
3429 let Inst{21} = 1; // W = 1
3430 let Inst{22} = 0; // D = 0
3431 let Inst{20} = load;
3434 def _POST : ACI<(outs),
3435 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3436 opc, "\tp$cop, cr$CRd, [$base], $offset"> {
3437 let Inst{31-28} = op31_28;
3438 let Inst{24} = 0; // P = 0
3439 let Inst{21} = 1; // W = 1
3440 let Inst{22} = 0; // D = 0
3441 let Inst{20} = load;
3444 def _OPTION : ACI<(outs),
3445 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
3446 opc, "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3447 let Inst{31-28} = op31_28;
3448 let Inst{24} = 0; // P = 0
3449 let Inst{23} = 1; // U = 1
3450 let Inst{21} = 0; // W = 0
3451 let Inst{22} = 0; // D = 0
3452 let Inst{20} = load;
3455 def L_OFFSET : ACI<(outs),
3456 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3457 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
3458 let Inst{31-28} = op31_28;
3459 let Inst{24} = 1; // P = 1
3460 let Inst{21} = 0; // W = 0
3461 let Inst{22} = 1; // D = 1
3462 let Inst{20} = load;
3465 def L_PRE : ACI<(outs),
3466 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3467 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
3468 let Inst{31-28} = op31_28;
3469 let Inst{24} = 1; // P = 1
3470 let Inst{21} = 1; // W = 1
3471 let Inst{22} = 1; // D = 1
3472 let Inst{20} = load;
3475 def L_POST : ACI<(outs),
3476 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3477 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $offset"> {
3478 let Inst{31-28} = op31_28;
3479 let Inst{24} = 0; // P = 0
3480 let Inst{21} = 1; // W = 1
3481 let Inst{22} = 1; // D = 1
3482 let Inst{20} = load;
3485 def L_OPTION : ACI<(outs),
3486 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
3487 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3488 let Inst{31-28} = op31_28;
3489 let Inst{24} = 0; // P = 0
3490 let Inst{23} = 1; // U = 1
3491 let Inst{21} = 0; // W = 0
3492 let Inst{22} = 1; // D = 1
3493 let Inst{20} = load;
3497 defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">;
3498 defm LDC2 : LdStCop<0b1111, 1, "ldc2">;
3499 defm STC : LdStCop<{?,?,?,?}, 0, "stc">;
3500 defm STC2 : LdStCop<0b1111, 0, "stc2">;
3502 //===----------------------------------------------------------------------===//
3503 // Move between coprocessor and ARM core register -- for disassembly only
3506 class MovRCopro<string opc, bit direction, dag oops, dag iops>
3507 : ABI<0b1110, oops, iops, NoItinerary, opc,
3508 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
3509 [/* For disassembly only; pattern left blank */]> {
3510 let Inst{20} = direction;
3520 let Inst{15-12} = Rt;
3521 let Inst{11-8} = cop;
3522 let Inst{23-21} = opc1;
3523 let Inst{7-5} = opc2;
3524 let Inst{3-0} = CRm;
3525 let Inst{19-16} = CRn;
3528 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
3529 (outs), (ins p_imm:$cop, i32imm:$opc1,
3530 GPR:$Rt, c_imm:$CRn, c_imm:$CRm,
3532 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
3533 (outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1,
3534 c_imm:$CRn, c_imm:$CRm, i32imm:$opc2)>;
3536 class MovRCopro2<string opc, bit direction, dag oops, dag iops>
3537 : ABXI<0b1110, oops, iops, NoItinerary,
3538 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3539 [/* For disassembly only; pattern left blank */]> {
3540 let Inst{31-28} = 0b1111;
3541 let Inst{20} = direction;
3551 let Inst{15-12} = Rt;
3552 let Inst{11-8} = cop;
3553 let Inst{23-21} = opc1;
3554 let Inst{7-5} = opc2;
3555 let Inst{3-0} = CRm;
3556 let Inst{19-16} = CRn;
3559 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
3560 (outs), (ins p_imm:$cop, i32imm:$opc1,
3561 GPR:$Rt, c_imm:$CRn, c_imm:$CRm,
3563 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
3564 (outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1,
3565 c_imm:$CRn, c_imm:$CRm,
3568 class MovRRCopro<string opc, bit direction>
3569 : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
3570 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3571 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm",
3572 [/* For disassembly only; pattern left blank */]> {
3573 let Inst{23-21} = 0b010;
3574 let Inst{20} = direction;
3582 let Inst{15-12} = Rt;
3583 let Inst{19-16} = Rt2;
3584 let Inst{11-8} = cop;
3585 let Inst{7-4} = opc1;
3586 let Inst{3-0} = CRm;
3589 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */>;
3590 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
3592 class MovRRCopro2<string opc, bit direction>
3593 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
3594 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3595 NoItinerary, !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"),
3596 [/* For disassembly only; pattern left blank */]> {
3597 let Inst{31-28} = 0b1111;
3598 let Inst{23-21} = 0b010;
3599 let Inst{20} = direction;
3607 let Inst{15-12} = Rt;
3608 let Inst{19-16} = Rt2;
3609 let Inst{11-8} = cop;
3610 let Inst{7-4} = opc1;
3611 let Inst{3-0} = CRm;
3614 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */>;
3615 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
3617 //===----------------------------------------------------------------------===//
3618 // Move between special register and ARM core register -- for disassembly only
3621 // Move to ARM core register from Special Register
3622 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3623 [/* For disassembly only; pattern left blank */]> {
3625 let Inst{23-16} = 0b00001111;
3626 let Inst{15-12} = Rd;
3627 let Inst{7-4} = 0b0000;
3630 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,"mrs","\t$Rd, spsr",
3631 [/* For disassembly only; pattern left blank */]> {
3633 let Inst{23-16} = 0b01001111;
3634 let Inst{15-12} = Rd;
3635 let Inst{7-4} = 0b0000;
3638 // Move from ARM core register to Special Register
3640 // No need to have both system and application versions, the encodings are the
3641 // same and the assembly parser has no way to distinguish between them. The mask
3642 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3643 // the mask with the fields to be accessed in the special register.
3644 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
3645 "msr", "\t$mask, $Rn",
3646 [/* For disassembly only; pattern left blank */]> {
3651 let Inst{22} = mask{4}; // R bit
3652 let Inst{21-20} = 0b10;
3653 let Inst{19-16} = mask{3-0};
3654 let Inst{15-12} = 0b1111;
3655 let Inst{11-4} = 0b00000000;
3659 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
3660 "msr", "\t$mask, $a",
3661 [/* For disassembly only; pattern left blank */]> {
3666 let Inst{22} = mask{4}; // R bit
3667 let Inst{21-20} = 0b10;
3668 let Inst{19-16} = mask{3-0};
3669 let Inst{15-12} = 0b1111;
3673 //===----------------------------------------------------------------------===//
3677 // __aeabi_read_tp preserves the registers r1-r3.
3678 // This is a pseudo inst so that we can get the encoding right,
3679 // complete with fixup for the aeabi_read_tp function.
3681 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
3682 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
3683 [(set R0, ARMthread_pointer)]>;
3686 //===----------------------------------------------------------------------===//
3687 // SJLJ Exception handling intrinsics
3688 // eh_sjlj_setjmp() is an instruction sequence to store the return
3689 // address and save #0 in R0 for the non-longjmp case.
3690 // Since by its nature we may be coming from some other function to get
3691 // here, and we're using the stack frame for the containing function to
3692 // save/restore registers, we can't keep anything live in regs across
3693 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3694 // when we get here from a longjmp(). We force everthing out of registers
3695 // except for our own input by listing the relevant registers in Defs. By
3696 // doing so, we also cause the prologue/epilogue code to actively preserve
3697 // all of the callee-saved resgisters, which is exactly what we want.
3698 // A constant value is passed in $val, and we use the location as a scratch.
3700 // These are pseudo-instructions and are lowered to individual MC-insts, so
3701 // no encoding information is necessary.
3703 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
3704 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
3705 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
3706 D31 ], hasSideEffects = 1, isBarrier = 1 in {
3707 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3709 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3710 Requires<[IsARM, HasVFP2]>;
3714 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
3715 hasSideEffects = 1, isBarrier = 1 in {
3716 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3718 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3719 Requires<[IsARM, NoVFP]>;
3722 // FIXME: Non-Darwin version(s)
3723 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3724 Defs = [ R7, LR, SP ] in {
3725 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
3727 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3728 Requires<[IsARM, IsDarwin]>;
3731 // eh.sjlj.dispatchsetup pseudo-instruction.
3732 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3733 // handled when the pseudo is expanded (which happens before any passes
3734 // that need the instruction size).
3735 let isBarrier = 1, hasSideEffects = 1 in
3736 def Int_eh_sjlj_dispatchsetup :
3737 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
3738 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
3739 Requires<[IsDarwin]>;
3741 //===----------------------------------------------------------------------===//
3742 // Non-Instruction Patterns
3745 // Large immediate handling.
3747 // 32-bit immediate using two piece so_imms or movw + movt.
3748 // This is a single pseudo instruction, the benefit is that it can be remat'd
3749 // as a single unit instead of having to handle reg inputs.
3750 // FIXME: Remove this when we can do generalized remat.
3751 let isReMaterializable = 1, isMoveImm = 1 in
3752 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3753 [(set GPR:$dst, (arm_i32imm:$src))]>,
3756 // Pseudo instruction that combines movw + movt + add pc (if PIC).
3757 // It also makes it possible to rematerialize the instructions.
3758 // FIXME: Remove this when we can do generalized remat and when machine licm
3759 // can properly the instructions.
3760 let isReMaterializable = 1 in {
3761 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3763 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3764 Requires<[IsARM, UseMovt]>;
3766 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3768 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3769 Requires<[IsARM, UseMovt]>;
3771 let AddedComplexity = 10 in
3772 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3774 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
3775 Requires<[IsARM, UseMovt]>;
3776 } // isReMaterializable
3778 // ConstantPool, GlobalAddress, and JumpTable
3779 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3780 Requires<[IsARM, DontUseMovt]>;
3781 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3782 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3783 Requires<[IsARM, UseMovt]>;
3784 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3785 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3787 // TODO: add,sub,and, 3-instr forms?
3790 def : ARMPat<(ARMtcret tcGPR:$dst),
3791 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3793 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3794 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3796 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3797 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3799 def : ARMPat<(ARMtcret tcGPR:$dst),
3800 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3802 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3803 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3805 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3806 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3809 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3810 Requires<[IsARM, IsNotDarwin]>;
3811 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3812 Requires<[IsARM, IsDarwin]>;
3814 // zextload i1 -> zextload i8
3815 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3816 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3818 // extload -> zextload
3819 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3820 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3821 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3822 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3824 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3826 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3827 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3830 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3831 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3832 (SMULBB GPR:$a, GPR:$b)>;
3833 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3834 (SMULBB GPR:$a, GPR:$b)>;
3835 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3836 (sra GPR:$b, (i32 16))),
3837 (SMULBT GPR:$a, GPR:$b)>;
3838 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3839 (SMULBT GPR:$a, GPR:$b)>;
3840 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3841 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3842 (SMULTB GPR:$a, GPR:$b)>;
3843 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3844 (SMULTB GPR:$a, GPR:$b)>;
3845 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3847 (SMULWB GPR:$a, GPR:$b)>;
3848 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3849 (SMULWB GPR:$a, GPR:$b)>;
3851 def : ARMV5TEPat<(add GPR:$acc,
3852 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3853 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3854 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3855 def : ARMV5TEPat<(add GPR:$acc,
3856 (mul sext_16_node:$a, sext_16_node:$b)),
3857 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3858 def : ARMV5TEPat<(add GPR:$acc,
3859 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3860 (sra GPR:$b, (i32 16)))),
3861 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3862 def : ARMV5TEPat<(add GPR:$acc,
3863 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3864 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3865 def : ARMV5TEPat<(add GPR:$acc,
3866 (mul (sra GPR:$a, (i32 16)),
3867 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3868 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3869 def : ARMV5TEPat<(add GPR:$acc,
3870 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3871 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3872 def : ARMV5TEPat<(add GPR:$acc,
3873 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3875 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3876 def : ARMV5TEPat<(add GPR:$acc,
3877 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3878 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3881 // Pre-v7 uses MCR for synchronization barriers.
3882 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
3883 Requires<[IsARM, HasV6]>;
3886 //===----------------------------------------------------------------------===//
3890 include "ARMInstrThumb.td"
3892 //===----------------------------------------------------------------------===//
3896 include "ARMInstrThumb2.td"
3898 //===----------------------------------------------------------------------===//
3899 // Floating Point Support
3902 include "ARMInstrVFP.td"
3904 //===----------------------------------------------------------------------===//
3905 // Advanced SIMD (NEON) Support
3908 include "ARMInstrNEON.td"