1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
67 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
68 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
72 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
74 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
75 [SDNPHasChain, SDNPOutFlag]>;
76 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
77 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
79 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
80 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
82 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
83 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
85 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
86 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
89 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
90 [SDNPHasChain, SDNPOptInFlag]>;
92 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
94 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
97 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
98 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
100 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
102 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
105 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
108 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
111 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
112 [SDNPOutFlag, SDNPCommutative]>;
114 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
116 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
117 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
118 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
120 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
121 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
122 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
123 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
124 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
125 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
126 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
129 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
131 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
133 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDTPrefetch,
134 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
136 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
138 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
139 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
142 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
144 //===----------------------------------------------------------------------===//
145 // ARM Instruction Predicate Definitions.
147 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
148 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
149 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
150 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
151 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
152 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
153 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
154 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
155 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
156 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
157 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
158 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
159 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
160 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
162 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
164 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
166 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
167 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
168 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
169 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
170 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
171 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
172 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
173 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
175 // FIXME: Eventually this will be just "hasV6T2Ops".
176 def UseMovt : Predicate<"Subtarget->useMovt()">;
177 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
178 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
180 //===----------------------------------------------------------------------===//
181 // ARM Flag Definitions.
183 class RegConstraint<string C> {
184 string Constraints = C;
187 //===----------------------------------------------------------------------===//
188 // ARM specific transformation functions and pattern fragments.
191 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
192 // so_imm_neg def below.
193 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
194 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
197 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
198 // so_imm_not def below.
199 def so_imm_not_XFORM : SDNodeXForm<imm, [{
200 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
203 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
204 def imm1_15 : PatLeaf<(i32 imm), [{
205 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
208 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
209 def imm16_31 : PatLeaf<(i32 imm), [{
210 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
215 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
216 }], so_imm_neg_XFORM>;
220 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
221 }], so_imm_not_XFORM>;
223 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
224 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
225 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
228 /// Split a 32-bit immediate into two 16 bit parts.
229 def hi16 : SDNodeXForm<imm, [{
230 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
233 def lo16AllZero : PatLeaf<(i32 imm), [{
234 // Returns true if all low 16-bits are 0.
235 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
238 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
240 def imm0_65535 : PatLeaf<(i32 imm), [{
241 return (uint32_t)N->getZExtValue() < 65536;
244 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
245 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
247 /// adde and sube predicates - True based on whether the carry flag output
248 /// will be needed or not.
249 def adde_dead_carry :
250 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
251 [{return !N->hasAnyUseOfValue(1);}]>;
252 def sube_dead_carry :
253 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
254 [{return !N->hasAnyUseOfValue(1);}]>;
255 def adde_live_carry :
256 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
257 [{return N->hasAnyUseOfValue(1);}]>;
258 def sube_live_carry :
259 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
260 [{return N->hasAnyUseOfValue(1);}]>;
262 // An 'and' node with a single use.
263 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
264 return N->hasOneUse();
267 // An 'xor' node with a single use.
268 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
269 return N->hasOneUse();
272 // An 'fmul' node with a single use.
273 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
274 return N->hasOneUse();
277 // An 'fadd' node which checks for single non-hazardous use.
278 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
279 return hasNoVMLxHazardUse(N);
282 // An 'fsub' node which checks for single non-hazardous use.
283 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
284 return hasNoVMLxHazardUse(N);
287 //===----------------------------------------------------------------------===//
288 // Operand Definitions.
292 def brtarget : Operand<OtherVT> {
293 let EncoderMethod = "getBranchTargetOpValue";
296 def uncondbrtarget : Operand<OtherVT> {
297 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
301 def bltarget : Operand<i32> {
302 // Encoded the same as branch targets.
303 let EncoderMethod = "getBranchTargetOpValue";
306 // A list of registers separated by comma. Used by load/store multiple.
307 def RegListAsmOperand : AsmOperandClass {
308 let Name = "RegList";
309 let SuperClasses = [];
312 def DPRRegListAsmOperand : AsmOperandClass {
313 let Name = "DPRRegList";
314 let SuperClasses = [];
317 def SPRRegListAsmOperand : AsmOperandClass {
318 let Name = "SPRRegList";
319 let SuperClasses = [];
322 def reglist : Operand<i32> {
323 let EncoderMethod = "getRegisterListOpValue";
324 let ParserMatchClass = RegListAsmOperand;
325 let PrintMethod = "printRegisterList";
328 def dpr_reglist : Operand<i32> {
329 let EncoderMethod = "getRegisterListOpValue";
330 let ParserMatchClass = DPRRegListAsmOperand;
331 let PrintMethod = "printRegisterList";
334 def spr_reglist : Operand<i32> {
335 let EncoderMethod = "getRegisterListOpValue";
336 let ParserMatchClass = SPRRegListAsmOperand;
337 let PrintMethod = "printRegisterList";
340 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
341 def cpinst_operand : Operand<i32> {
342 let PrintMethod = "printCPInstOperand";
346 def pclabel : Operand<i32> {
347 let PrintMethod = "printPCLabel";
350 // ADR instruction labels.
351 def adrlabel : Operand<i32> {
352 let EncoderMethod = "getAdrLabelOpValue";
355 def neon_vcvt_imm32 : Operand<i32> {
356 let EncoderMethod = "getNEONVcvtImm32OpValue";
359 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
360 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
361 int32_t v = (int32_t)N->getZExtValue();
362 return v == 8 || v == 16 || v == 24; }]> {
363 let EncoderMethod = "getRotImmOpValue";
366 // shift_imm: An integer that encodes a shift amount and the type of shift
367 // (currently either asr or lsl) using the same encoding used for the
368 // immediates in so_reg operands.
369 def shift_imm : Operand<i32> {
370 let PrintMethod = "printShiftImmOperand";
373 // shifter_operand operands: so_reg and so_imm.
374 def so_reg : Operand<i32>, // reg reg imm
375 ComplexPattern<i32, 3, "SelectShifterOperandReg",
376 [shl,srl,sra,rotr]> {
377 let EncoderMethod = "getSORegOpValue";
378 let PrintMethod = "printSORegOperand";
379 let MIOperandInfo = (ops GPR, GPR, i32imm);
381 def shift_so_reg : Operand<i32>, // reg reg imm
382 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
383 [shl,srl,sra,rotr]> {
384 let EncoderMethod = "getSORegOpValue";
385 let PrintMethod = "printSORegOperand";
386 let MIOperandInfo = (ops GPR, GPR, i32imm);
389 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
390 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
391 // represented in the imm field in the same 12-bit form that they are encoded
392 // into so_imm instructions: the 8-bit immediate is the least significant bits
393 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
394 def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> {
395 let EncoderMethod = "getSOImmOpValue";
396 let PrintMethod = "printSOImmOperand";
399 // Break so_imm's up into two pieces. This handles immediates with up to 16
400 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
401 // get the first/second pieces.
402 def so_imm2part : PatLeaf<(imm), [{
403 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
406 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
408 def arm_i32imm : PatLeaf<(imm), [{
409 if (Subtarget->hasV6T2Ops())
411 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
414 def so_imm2part_1 : SDNodeXForm<imm, [{
415 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
416 return CurDAG->getTargetConstant(V, MVT::i32);
419 def so_imm2part_2 : SDNodeXForm<imm, [{
420 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
421 return CurDAG->getTargetConstant(V, MVT::i32);
424 def so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
425 return ARM_AM::isSOImmTwoPartVal(-(int)N->getZExtValue());
427 let PrintMethod = "printSOImm2PartOperand";
430 def so_neg_imm2part_1 : SDNodeXForm<imm, [{
431 unsigned V = ARM_AM::getSOImmTwoPartFirst(-(int)N->getZExtValue());
432 return CurDAG->getTargetConstant(V, MVT::i32);
435 def so_neg_imm2part_2 : SDNodeXForm<imm, [{
436 unsigned V = ARM_AM::getSOImmTwoPartSecond(-(int)N->getZExtValue());
437 return CurDAG->getTargetConstant(V, MVT::i32);
440 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
441 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
442 return (int32_t)N->getZExtValue() < 32;
445 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
446 def imm0_31_m1 : Operand<i32>, PatLeaf<(imm), [{
447 return (int32_t)N->getZExtValue() < 32;
449 let EncoderMethod = "getImmMinusOneOpValue";
452 // For movt/movw - sets the MC Encoder method.
453 // The imm is split into imm{15-12}, imm{11-0}
455 def movt_imm : Operand<i32> {
456 let EncoderMethod = "getMovtImmOpValue";
459 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
461 def bf_inv_mask_imm : Operand<i32>,
463 return ARM::isBitFieldInvertedMask(N->getZExtValue());
465 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
466 let PrintMethod = "printBitfieldInvMaskImmOperand";
469 // Define ARM specific addressing modes.
472 // addrmode_imm12 := reg +/- imm12
474 def addrmode_imm12 : Operand<i32>,
475 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
476 // 12-bit immediate operand. Note that instructions using this encode
477 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
478 // immediate values are as normal.
480 let EncoderMethod = "getAddrModeImm12OpValue";
481 let PrintMethod = "printAddrModeImm12Operand";
482 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
484 // ldst_so_reg := reg +/- reg shop imm
486 def ldst_so_reg : Operand<i32>,
487 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
488 let EncoderMethod = "getLdStSORegOpValue";
489 // FIXME: Simplify the printer
490 let PrintMethod = "printAddrMode2Operand";
491 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
494 // addrmode2 := reg +/- imm12
495 // := reg +/- reg shop imm
497 def addrmode2 : Operand<i32>,
498 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
499 let EncoderMethod = "getAddrMode2OpValue";
500 let PrintMethod = "printAddrMode2Operand";
501 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
504 def am2offset : Operand<i32>,
505 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
506 [], [SDNPWantRoot]> {
507 let EncoderMethod = "getAddrMode2OffsetOpValue";
508 let PrintMethod = "printAddrMode2OffsetOperand";
509 let MIOperandInfo = (ops GPR, i32imm);
512 // addrmode3 := reg +/- reg
513 // addrmode3 := reg +/- imm8
515 def addrmode3 : Operand<i32>,
516 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
517 let EncoderMethod = "getAddrMode3OpValue";
518 let PrintMethod = "printAddrMode3Operand";
519 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
522 def am3offset : Operand<i32>,
523 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
524 [], [SDNPWantRoot]> {
525 let EncoderMethod = "getAddrMode3OffsetOpValue";
526 let PrintMethod = "printAddrMode3OffsetOperand";
527 let MIOperandInfo = (ops GPR, i32imm);
530 // ldstm_mode := {ia, ib, da, db}
532 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
533 let EncoderMethod = "getLdStmModeOpValue";
534 let PrintMethod = "printLdStmModeOperand";
537 def MemMode5AsmOperand : AsmOperandClass {
538 let Name = "MemMode5";
539 let SuperClasses = [];
542 // addrmode5 := reg +/- imm8*4
544 def addrmode5 : Operand<i32>,
545 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
546 let PrintMethod = "printAddrMode5Operand";
547 let MIOperandInfo = (ops GPR:$base, i32imm);
548 let ParserMatchClass = MemMode5AsmOperand;
549 let EncoderMethod = "getAddrMode5OpValue";
552 // addrmode6 := reg with optional writeback
554 def addrmode6 : Operand<i32>,
555 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
556 let PrintMethod = "printAddrMode6Operand";
557 let MIOperandInfo = (ops GPR:$addr, i32imm);
558 let EncoderMethod = "getAddrMode6AddressOpValue";
561 def am6offset : Operand<i32> {
562 let PrintMethod = "printAddrMode6OffsetOperand";
563 let MIOperandInfo = (ops GPR);
564 let EncoderMethod = "getAddrMode6OffsetOpValue";
567 // Special version of addrmode6 to handle alignment encoding for VLD-dup
568 // instructions, specifically VLD4-dup.
569 def addrmode6dup : Operand<i32>,
570 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
571 let PrintMethod = "printAddrMode6Operand";
572 let MIOperandInfo = (ops GPR:$addr, i32imm);
573 let EncoderMethod = "getAddrMode6DupAddressOpValue";
576 // addrmodepc := pc + reg
578 def addrmodepc : Operand<i32>,
579 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
580 let PrintMethod = "printAddrModePCOperand";
581 let MIOperandInfo = (ops GPR, i32imm);
584 def nohash_imm : Operand<i32> {
585 let PrintMethod = "printNoHashImmediate";
588 //===----------------------------------------------------------------------===//
590 include "ARMInstrFormats.td"
592 //===----------------------------------------------------------------------===//
593 // Multiclass helpers...
596 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
597 /// binop that produces a value.
598 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
599 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
600 PatFrag opnode, bit Commutable = 0> {
601 // The register-immediate version is re-materializable. This is useful
602 // in particular for taking the address of a local.
603 let isReMaterializable = 1 in {
604 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
605 iii, opc, "\t$Rd, $Rn, $imm",
606 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
611 let Inst{19-16} = Rn;
612 let Inst{15-12} = Rd;
613 let Inst{11-0} = imm;
616 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
617 iir, opc, "\t$Rd, $Rn, $Rm",
618 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
623 let isCommutable = Commutable;
624 let Inst{19-16} = Rn;
625 let Inst{15-12} = Rd;
626 let Inst{11-4} = 0b00000000;
629 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
630 iis, opc, "\t$Rd, $Rn, $shift",
631 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
636 let Inst{19-16} = Rn;
637 let Inst{15-12} = Rd;
638 let Inst{11-0} = shift;
642 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
643 /// instruction modifies the CPSR register.
644 let Defs = [CPSR] in {
645 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
646 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
647 PatFrag opnode, bit Commutable = 0> {
648 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
649 iii, opc, "\t$Rd, $Rn, $imm",
650 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
656 let Inst{19-16} = Rn;
657 let Inst{15-12} = Rd;
658 let Inst{11-0} = imm;
660 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
661 iir, opc, "\t$Rd, $Rn, $Rm",
662 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
666 let isCommutable = Commutable;
669 let Inst{19-16} = Rn;
670 let Inst{15-12} = Rd;
671 let Inst{11-4} = 0b00000000;
674 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
675 iis, opc, "\t$Rd, $Rn, $shift",
676 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
682 let Inst{19-16} = Rn;
683 let Inst{15-12} = Rd;
684 let Inst{11-0} = shift;
689 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
690 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
691 /// a explicit result, only implicitly set CPSR.
692 let isCompare = 1, Defs = [CPSR] in {
693 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
694 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
695 PatFrag opnode, bit Commutable = 0> {
696 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
698 [(opnode GPR:$Rn, so_imm:$imm)]> {
703 let Inst{19-16} = Rn;
704 let Inst{15-12} = 0b0000;
705 let Inst{11-0} = imm;
707 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
709 [(opnode GPR:$Rn, GPR:$Rm)]> {
712 let isCommutable = Commutable;
715 let Inst{19-16} = Rn;
716 let Inst{15-12} = 0b0000;
717 let Inst{11-4} = 0b00000000;
720 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
721 opc, "\t$Rn, $shift",
722 [(opnode GPR:$Rn, so_reg:$shift)]> {
727 let Inst{19-16} = Rn;
728 let Inst{15-12} = 0b0000;
729 let Inst{11-0} = shift;
734 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
735 /// register and one whose operand is a register rotated by 8/16/24.
736 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
737 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
738 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
739 IIC_iEXTr, opc, "\t$Rd, $Rm",
740 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
741 Requires<[IsARM, HasV6]> {
744 let Inst{19-16} = 0b1111;
745 let Inst{15-12} = Rd;
746 let Inst{11-10} = 0b00;
749 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
750 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
751 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
752 Requires<[IsARM, HasV6]> {
756 let Inst{19-16} = 0b1111;
757 let Inst{15-12} = Rd;
758 let Inst{11-10} = rot;
763 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
764 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
765 IIC_iEXTr, opc, "\t$Rd, $Rm",
766 [/* For disassembly only; pattern left blank */]>,
767 Requires<[IsARM, HasV6]> {
768 let Inst{19-16} = 0b1111;
769 let Inst{11-10} = 0b00;
771 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
772 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
773 [/* For disassembly only; pattern left blank */]>,
774 Requires<[IsARM, HasV6]> {
776 let Inst{19-16} = 0b1111;
777 let Inst{11-10} = rot;
781 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
782 /// register and one whose operand is a register rotated by 8/16/24.
783 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
784 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
785 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
786 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
787 Requires<[IsARM, HasV6]> {
791 let Inst{19-16} = Rn;
792 let Inst{15-12} = Rd;
793 let Inst{11-10} = 0b00;
794 let Inst{9-4} = 0b000111;
797 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
799 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
800 [(set GPR:$Rd, (opnode GPR:$Rn,
801 (rotr GPR:$Rm, rot_imm:$rot)))]>,
802 Requires<[IsARM, HasV6]> {
807 let Inst{19-16} = Rn;
808 let Inst{15-12} = Rd;
809 let Inst{11-10} = rot;
810 let Inst{9-4} = 0b000111;
815 // For disassembly only.
816 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
817 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
818 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
819 [/* For disassembly only; pattern left blank */]>,
820 Requires<[IsARM, HasV6]> {
821 let Inst{11-10} = 0b00;
823 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
825 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
826 [/* For disassembly only; pattern left blank */]>,
827 Requires<[IsARM, HasV6]> {
830 let Inst{19-16} = Rn;
831 let Inst{11-10} = rot;
835 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
836 let Uses = [CPSR] in {
837 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
838 bit Commutable = 0> {
839 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
840 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
841 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
847 let Inst{15-12} = Rd;
848 let Inst{19-16} = Rn;
849 let Inst{11-0} = imm;
851 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
852 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
853 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
858 let Inst{11-4} = 0b00000000;
860 let isCommutable = Commutable;
862 let Inst{15-12} = Rd;
863 let Inst{19-16} = Rn;
865 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
866 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
867 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
873 let Inst{11-0} = shift;
874 let Inst{15-12} = Rd;
875 let Inst{19-16} = Rn;
878 // Carry setting variants
879 let Defs = [CPSR] in {
880 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
881 bit Commutable = 0> {
882 def Sri : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
883 DPFrm, IIC_iALUi, !strconcat(opc, "\t$Rd, $Rn, $imm"),
884 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
889 let Inst{15-12} = Rd;
890 let Inst{19-16} = Rn;
891 let Inst{11-0} = imm;
895 def Srr : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
896 DPFrm, IIC_iALUr, !strconcat(opc, "\t$Rd, $Rn, $Rm"),
897 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
902 let Inst{11-4} = 0b00000000;
903 let isCommutable = Commutable;
905 let Inst{15-12} = Rd;
906 let Inst{19-16} = Rn;
910 def Srs : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
911 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$Rd, $Rn, $shift"),
912 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
917 let Inst{11-0} = shift;
918 let Inst{15-12} = Rd;
919 let Inst{19-16} = Rn;
927 let canFoldAsLoad = 1, isReMaterializable = 1 in {
928 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
929 InstrItinClass iir, PatFrag opnode> {
930 // Note: We use the complex addrmode_imm12 rather than just an input
931 // GPR and a constrained immediate so that we can use this to match
932 // frame index references and avoid matching constant pool references.
933 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
934 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
935 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
938 let Inst{23} = addr{12}; // U (add = ('U' == 1))
939 let Inst{19-16} = addr{16-13}; // Rn
940 let Inst{15-12} = Rt;
941 let Inst{11-0} = addr{11-0}; // imm12
943 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
944 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
945 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
948 let Inst{23} = shift{12}; // U (add = ('U' == 1))
949 let Inst{19-16} = shift{16-13}; // Rn
950 let Inst{15-12} = Rt;
951 let Inst{11-0} = shift{11-0};
956 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
957 InstrItinClass iir, PatFrag opnode> {
958 // Note: We use the complex addrmode_imm12 rather than just an input
959 // GPR and a constrained immediate so that we can use this to match
960 // frame index references and avoid matching constant pool references.
961 def i12 : AI2ldst<0b010, 0, isByte, (outs),
962 (ins GPR:$Rt, addrmode_imm12:$addr),
963 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
964 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
967 let Inst{23} = addr{12}; // U (add = ('U' == 1))
968 let Inst{19-16} = addr{16-13}; // Rn
969 let Inst{15-12} = Rt;
970 let Inst{11-0} = addr{11-0}; // imm12
972 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
973 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
974 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
977 let Inst{23} = shift{12}; // U (add = ('U' == 1))
978 let Inst{19-16} = shift{16-13}; // Rn
979 let Inst{15-12} = Rt;
980 let Inst{11-0} = shift{11-0};
983 //===----------------------------------------------------------------------===//
985 //===----------------------------------------------------------------------===//
987 //===----------------------------------------------------------------------===//
988 // Miscellaneous Instructions.
991 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
992 /// the function. The first operand is the ID# for this instruction, the second
993 /// is the index into the MachineConstantPool that this is, the third is the
994 /// size in bytes of this constant pool entry.
995 let neverHasSideEffects = 1, isNotDuplicable = 1 in
996 def CONSTPOOL_ENTRY :
997 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
998 i32imm:$size), NoItinerary, []>;
1000 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1001 // from removing one half of the matched pairs. That breaks PEI, which assumes
1002 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1003 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1004 def ADJCALLSTACKUP :
1005 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1006 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1008 def ADJCALLSTACKDOWN :
1009 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1010 [(ARMcallseq_start timm:$amt)]>;
1013 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
1014 [/* For disassembly only; pattern left blank */]>,
1015 Requires<[IsARM, HasV6T2]> {
1016 let Inst{27-16} = 0b001100100000;
1017 let Inst{15-8} = 0b11110000;
1018 let Inst{7-0} = 0b00000000;
1021 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
1022 [/* For disassembly only; pattern left blank */]>,
1023 Requires<[IsARM, HasV6T2]> {
1024 let Inst{27-16} = 0b001100100000;
1025 let Inst{15-8} = 0b11110000;
1026 let Inst{7-0} = 0b00000001;
1029 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
1030 [/* For disassembly only; pattern left blank */]>,
1031 Requires<[IsARM, HasV6T2]> {
1032 let Inst{27-16} = 0b001100100000;
1033 let Inst{15-8} = 0b11110000;
1034 let Inst{7-0} = 0b00000010;
1037 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
1038 [/* For disassembly only; pattern left blank */]>,
1039 Requires<[IsARM, HasV6T2]> {
1040 let Inst{27-16} = 0b001100100000;
1041 let Inst{15-8} = 0b11110000;
1042 let Inst{7-0} = 0b00000011;
1045 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
1047 [/* For disassembly only; pattern left blank */]>,
1048 Requires<[IsARM, HasV6]> {
1053 let Inst{15-12} = Rd;
1054 let Inst{19-16} = Rn;
1055 let Inst{27-20} = 0b01101000;
1056 let Inst{7-4} = 0b1011;
1057 let Inst{11-8} = 0b1111;
1060 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1061 [/* For disassembly only; pattern left blank */]>,
1062 Requires<[IsARM, HasV6T2]> {
1063 let Inst{27-16} = 0b001100100000;
1064 let Inst{15-8} = 0b11110000;
1065 let Inst{7-0} = 0b00000100;
1068 // The i32imm operand $val can be used by a debugger to store more information
1069 // about the breakpoint.
1070 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
1071 [/* For disassembly only; pattern left blank */]>,
1074 let Inst{3-0} = val{3-0};
1075 let Inst{19-8} = val{15-4};
1076 let Inst{27-20} = 0b00010010;
1077 let Inst{7-4} = 0b0111;
1080 // Change Processor State is a system instruction -- for disassembly only.
1081 // The singleton $opt operand contains the following information:
1082 // opt{4-0} = mode from Inst{4-0}
1083 // opt{5} = changemode from Inst{17}
1084 // opt{8-6} = AIF from Inst{8-6}
1085 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
1086 // FIXME: Integrated assembler will need these split out.
1087 def CPS : AXI<(outs), (ins cps_opt:$opt), MiscFrm, NoItinerary, "cps$opt",
1088 [/* For disassembly only; pattern left blank */]>,
1090 let Inst{31-28} = 0b1111;
1091 let Inst{27-20} = 0b00010000;
1096 // Preload signals the memory system of possible future data/instruction access.
1097 // These are for disassembly only.
1098 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1100 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1101 !strconcat(opc, "\t$addr"),
1102 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1105 let Inst{31-26} = 0b111101;
1106 let Inst{25} = 0; // 0 for immediate form
1107 let Inst{24} = data;
1108 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1109 let Inst{22} = read;
1110 let Inst{21-20} = 0b01;
1111 let Inst{19-16} = addr{16-13}; // Rn
1112 let Inst{15-12} = Rt;
1113 let Inst{11-0} = addr{11-0}; // imm12
1116 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1117 !strconcat(opc, "\t$shift"),
1118 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1121 let Inst{31-26} = 0b111101;
1122 let Inst{25} = 1; // 1 for register form
1123 let Inst{24} = data;
1124 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1125 let Inst{22} = read;
1126 let Inst{21-20} = 0b01;
1127 let Inst{19-16} = shift{16-13}; // Rn
1128 let Inst{11-0} = shift{11-0};
1132 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1133 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1134 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1136 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1138 [/* For disassembly only; pattern left blank */]>,
1141 let Inst{31-10} = 0b1111000100000001000000;
1146 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1147 [/* For disassembly only; pattern left blank */]>,
1148 Requires<[IsARM, HasV7]> {
1150 let Inst{27-4} = 0b001100100000111100001111;
1151 let Inst{3-0} = opt;
1154 // A5.4 Permanently UNDEFINED instructions.
1155 let isBarrier = 1, isTerminator = 1 in
1156 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1159 let Inst = 0xe7ffdefe;
1162 // Address computation and loads and stores in PIC mode.
1163 let isNotDuplicable = 1 in {
1164 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1165 Size4Bytes, IIC_iALUr,
1166 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1168 let AddedComplexity = 10 in {
1169 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1170 Size4Bytes, IIC_iLoad_r,
1171 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1173 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1174 Size4Bytes, IIC_iLoad_bh_r,
1175 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1177 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1178 Size4Bytes, IIC_iLoad_bh_r,
1179 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1181 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1182 Size4Bytes, IIC_iLoad_bh_r,
1183 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1185 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1186 Size4Bytes, IIC_iLoad_bh_r,
1187 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1189 let AddedComplexity = 10 in {
1190 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1191 Size4Bytes, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1193 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1194 Size4Bytes, IIC_iStore_bh_r, [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
1196 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1197 Size4Bytes, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1199 } // isNotDuplicable = 1
1202 // LEApcrel - Load a pc-relative address into a register without offending the
1204 let neverHasSideEffects = 1, isReMaterializable = 1 in
1205 // The 'adr' mnemonic encodes differently if the label is before or after
1206 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1207 // know until then which form of the instruction will be used.
1208 def ADR : AI1<0, (outs GPR:$Rd), (ins adrlabel:$label),
1209 MiscFrm, IIC_iALUi, "adr", "\t$Rd, #$label", []> {
1212 let Inst{27-25} = 0b001;
1214 let Inst{19-16} = 0b1111;
1215 let Inst{15-12} = Rd;
1216 let Inst{11-0} = label;
1218 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1219 Size4Bytes, IIC_iALUi, []>;
1221 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1222 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1223 Size4Bytes, IIC_iALUi, []>;
1225 //===----------------------------------------------------------------------===//
1226 // Control Flow Instructions.
1229 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1231 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1232 "bx", "\tlr", [(ARMretflag)]>,
1233 Requires<[IsARM, HasV4T]> {
1234 let Inst{27-0} = 0b0001001011111111111100011110;
1238 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1239 "mov", "\tpc, lr", [(ARMretflag)]>,
1240 Requires<[IsARM, NoV4T]> {
1241 let Inst{27-0} = 0b0001101000001111000000001110;
1245 // Indirect branches
1246 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1248 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1249 [(brind GPR:$dst)]>,
1250 Requires<[IsARM, HasV4T]> {
1252 let Inst{31-4} = 0b1110000100101111111111110001;
1253 let Inst{3-0} = dst;
1257 // FIXME: We would really like to define this as a vanilla ARMPat like:
1258 // ARMPat<(brind GPR:$dst), (MOVr PC, GPR:$dst)>
1259 // With that, however, we can't set isBranch, isTerminator, etc..
1260 def MOVPCRX : ARMPseudoInst<(outs), (ins GPR:$dst),
1261 Size4Bytes, IIC_Br, [(brind GPR:$dst)]>,
1262 Requires<[IsARM, NoV4T]>;
1265 // All calls clobber the non-callee saved registers. SP is marked as
1266 // a use to prevent stack-pointer assignments that appear immediately
1267 // before calls from potentially appearing dead.
1269 // On non-Darwin platforms R9 is callee-saved.
1270 Defs = [R0, R1, R2, R3, R12, LR,
1271 D0, D1, D2, D3, D4, D5, D6, D7,
1272 D16, D17, D18, D19, D20, D21, D22, D23,
1273 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1275 def BL : ABXI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1276 IIC_Br, "bl\t$func",
1277 [(ARMcall tglobaladdr:$func)]>,
1278 Requires<[IsARM, IsNotDarwin]> {
1279 let Inst{31-28} = 0b1110;
1281 let Inst{23-0} = func;
1284 def BL_pred : ABI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1285 IIC_Br, "bl", "\t$func",
1286 [(ARMcall_pred tglobaladdr:$func)]>,
1287 Requires<[IsARM, IsNotDarwin]> {
1289 let Inst{23-0} = func;
1293 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1294 IIC_Br, "blx\t$func",
1295 [(ARMcall GPR:$func)]>,
1296 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1298 let Inst{31-4} = 0b1110000100101111111111110011;
1299 let Inst{3-0} = func;
1303 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1304 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1305 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1306 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1309 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1310 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1311 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1315 // On Darwin R9 is call-clobbered.
1316 // R7 is marked as a use to prevent frame-pointer assignments from being
1317 // moved above / below calls.
1318 Defs = [R0, R1, R2, R3, R9, R12, LR,
1319 D0, D1, D2, D3, D4, D5, D6, D7,
1320 D16, D17, D18, D19, D20, D21, D22, D23,
1321 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1322 Uses = [R7, SP] in {
1323 def BLr9 : ABXI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1324 IIC_Br, "bl\t$func",
1325 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
1326 let Inst{31-28} = 0b1110;
1328 let Inst{23-0} = func;
1331 def BLr9_pred : ABI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1332 IIC_Br, "bl", "\t$func",
1333 [(ARMcall_pred tglobaladdr:$func)]>,
1334 Requires<[IsARM, IsDarwin]> {
1336 let Inst{23-0} = func;
1340 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1341 IIC_Br, "blx\t$func",
1342 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
1344 let Inst{31-4} = 0b1110000100101111111111110011;
1345 let Inst{3-0} = func;
1349 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1350 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1351 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1352 Requires<[IsARM, HasV4T, IsDarwin]>;
1355 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1356 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1357 Requires<[IsARM, NoV4T, IsDarwin]>;
1362 // FIXME: These should probably be xformed into the non-TC versions of the
1363 // instructions as part of MC lowering.
1364 // FIXME: These seem to be used for both Thumb and ARM instruction selection.
1365 // Thumb should have its own version since the instruction is actually
1366 // different, even though the mnemonic is the same.
1367 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1369 let Defs = [R0, R1, R2, R3, R9, R12,
1370 D0, D1, D2, D3, D4, D5, D6, D7,
1371 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1372 D27, D28, D29, D30, D31, PC],
1374 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1375 IIC_Br, []>, Requires<[IsDarwin]>;
1377 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1378 IIC_Br, []>, Requires<[IsDarwin]>;
1380 def TAILJMPd : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1381 IIC_Br, "b\t$dst @ TAILCALL",
1382 []>, Requires<[IsARM, IsDarwin]>;
1384 def TAILJMPdt: ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1385 IIC_Br, "b.w\t$dst @ TAILCALL",
1386 []>, Requires<[IsThumb, IsDarwin]>;
1388 def TAILJMPr : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1389 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1390 []>, Requires<[IsDarwin]> {
1392 let Inst{31-4} = 0b1110000100101111111111110001;
1393 let Inst{3-0} = dst;
1397 // Non-Darwin versions (the difference is R9).
1398 let Defs = [R0, R1, R2, R3, R12,
1399 D0, D1, D2, D3, D4, D5, D6, D7,
1400 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1401 D27, D28, D29, D30, D31, PC],
1403 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1404 IIC_Br, []>, Requires<[IsNotDarwin]>;
1406 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1407 IIC_Br, []>, Requires<[IsNotDarwin]>;
1409 def TAILJMPdND : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1410 IIC_Br, "b\t$dst @ TAILCALL",
1411 []>, Requires<[IsARM, IsNotDarwin]>;
1413 def TAILJMPdNDt : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1414 IIC_Br, "b.w\t$dst @ TAILCALL",
1415 []>, Requires<[IsThumb, IsNotDarwin]>;
1417 def TAILJMPrND : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1418 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1419 []>, Requires<[IsNotDarwin]> {
1421 let Inst{31-4} = 0b1110000100101111111111110001;
1422 let Inst{3-0} = dst;
1427 let isBranch = 1, isTerminator = 1 in {
1428 // B is "predicable" since it can be xformed into a Bcc.
1429 let isBarrier = 1 in {
1430 let isPredicable = 1 in
1431 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
1432 "b\t$target", [(br bb:$target)]> {
1434 let Inst{31-28} = 0b1110;
1435 let Inst{23-0} = target;
1438 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1439 def BR_JTr : ARMPseudoInst<(outs),
1440 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1441 SizeSpecial, IIC_Br,
1442 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1443 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1444 // into i12 and rs suffixed versions.
1445 def BR_JTm : ARMPseudoInst<(outs),
1446 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1447 SizeSpecial, IIC_Br,
1448 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1450 def BR_JTadd : ARMPseudoInst<(outs),
1451 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1452 SizeSpecial, IIC_Br,
1453 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1455 } // isNotDuplicable = 1, isIndirectBranch = 1
1458 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1459 // a two-value operand where a dag node expects two operands. :(
1460 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
1461 IIC_Br, "b", "\t$target",
1462 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1464 let Inst{23-0} = target;
1468 // Branch and Exchange Jazelle -- for disassembly only
1469 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1470 [/* For disassembly only; pattern left blank */]> {
1471 let Inst{23-20} = 0b0010;
1472 //let Inst{19-8} = 0xfff;
1473 let Inst{7-4} = 0b0010;
1476 // Secure Monitor Call is a system instruction -- for disassembly only
1477 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1478 [/* For disassembly only; pattern left blank */]> {
1480 let Inst{23-4} = 0b01100000000000000111;
1481 let Inst{3-0} = opt;
1484 // Supervisor Call (Software Interrupt) -- for disassembly only
1485 let isCall = 1, Uses = [SP] in {
1486 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1487 [/* For disassembly only; pattern left blank */]> {
1489 let Inst{23-0} = svc;
1493 // Store Return State is a system instruction -- for disassembly only
1494 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1495 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1496 NoItinerary, "srs${amode}\tsp!, $mode",
1497 [/* For disassembly only; pattern left blank */]> {
1498 let Inst{31-28} = 0b1111;
1499 let Inst{22-20} = 0b110; // W = 1
1502 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1503 NoItinerary, "srs${amode}\tsp, $mode",
1504 [/* For disassembly only; pattern left blank */]> {
1505 let Inst{31-28} = 0b1111;
1506 let Inst{22-20} = 0b100; // W = 0
1509 // Return From Exception is a system instruction -- for disassembly only
1510 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1511 NoItinerary, "rfe${amode}\t$base!",
1512 [/* For disassembly only; pattern left blank */]> {
1513 let Inst{31-28} = 0b1111;
1514 let Inst{22-20} = 0b011; // W = 1
1517 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1518 NoItinerary, "rfe${amode}\t$base",
1519 [/* For disassembly only; pattern left blank */]> {
1520 let Inst{31-28} = 0b1111;
1521 let Inst{22-20} = 0b001; // W = 0
1523 } // isCodeGenOnly = 1
1525 //===----------------------------------------------------------------------===//
1526 // Load / store Instructions.
1532 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1533 UnOpFrag<(load node:$Src)>>;
1534 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1535 UnOpFrag<(zextloadi8 node:$Src)>>;
1536 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1537 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1538 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1539 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1541 // Special LDR for loads from non-pc-relative constpools.
1542 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1543 isReMaterializable = 1 in
1544 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1545 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
1549 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1550 let Inst{19-16} = 0b1111;
1551 let Inst{15-12} = Rt;
1552 let Inst{11-0} = addr{11-0}; // imm12
1555 // Loads with zero extension
1556 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1557 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
1558 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
1560 // Loads with sign extension
1561 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1562 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
1563 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
1565 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1566 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
1567 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
1569 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
1570 isCodeGenOnly = 1 in { // $dst2 doesn't exist in asmstring?
1571 // FIXME: $dst2 isn't in the asm string as it's implied by $Rd (dst2 = Rd+1)
1572 // how to represent that such that tblgen is happy and we don't
1573 // mark this codegen only?
1575 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
1576 (ins addrmode3:$addr), LdMiscFrm,
1577 IIC_iLoad_d_r, "ldrd", "\t$Rd, $addr",
1578 []>, Requires<[IsARM, HasV5TE]>;
1582 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
1583 def _PRE : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1584 (ins addrmode2:$addr), IndexModePre, LdFrm, itin,
1585 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1587 // {13} 1 == Rm, 0 == imm12
1591 let Inst{25} = addr{13};
1592 let Inst{23} = addr{12};
1593 let Inst{19-16} = addr{17-14};
1594 let Inst{11-0} = addr{11-0};
1596 def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1597 (ins GPR:$Rn, am2offset:$offset),
1598 IndexModePost, LdFrm, itin,
1599 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1600 // {13} 1 == Rm, 0 == imm12
1605 let Inst{25} = offset{13};
1606 let Inst{23} = offset{12};
1607 let Inst{19-16} = Rn;
1608 let Inst{11-0} = offset{11-0};
1612 let mayLoad = 1, neverHasSideEffects = 1 in {
1613 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
1614 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
1617 multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
1618 def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1619 (ins addrmode3:$addr), IndexModePre,
1621 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1623 let Inst{23} = addr{8}; // U bit
1624 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1625 let Inst{19-16} = addr{12-9}; // Rn
1626 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1627 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1629 def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1630 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1632 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1635 let Inst{23} = offset{8}; // U bit
1636 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1637 let Inst{19-16} = Rn;
1638 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1639 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1643 let mayLoad = 1, neverHasSideEffects = 1 in {
1644 defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
1645 defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
1646 defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
1647 let hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1648 defm LDRD : AI3_ldridx<0b1101, 0, "ldrd", IIC_iLoad_d_ru>;
1649 } // mayLoad = 1, neverHasSideEffects = 1
1651 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1652 let mayLoad = 1, neverHasSideEffects = 1 in {
1653 def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$dst, GPR:$base_wb),
1654 (ins GPR:$base, am2offset:$offset), IndexModeNone,
1655 LdFrm, IIC_iLoad_ru,
1656 "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1657 let Inst{21} = 1; // overwrite
1659 def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1660 (ins GPR:$base, am2offset:$offset), IndexModeNone,
1661 LdFrm, IIC_iLoad_bh_ru,
1662 "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1663 let Inst{21} = 1; // overwrite
1665 def LDRSBT : AI3ldstidx<0b1101, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1666 (ins GPR:$base, am3offset:$offset), IndexModePost,
1667 LdMiscFrm, IIC_iLoad_bh_ru,
1668 "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1669 let Inst{21} = 1; // overwrite
1671 def LDRHT : AI3ldstidx<0b1011, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1672 (ins GPR:$base, am3offset:$offset), IndexModePost,
1673 LdMiscFrm, IIC_iLoad_bh_ru,
1674 "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1675 let Inst{21} = 1; // overwrite
1677 def LDRSHT : AI3ldstidx<0b1111, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1678 (ins GPR:$base, am3offset:$offset), IndexModePost,
1679 LdMiscFrm, IIC_iLoad_bh_ru,
1680 "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1681 let Inst{21} = 1; // overwrite
1687 // Stores with truncate
1688 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
1689 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
1690 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
1693 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
1694 isCodeGenOnly = 1 in // $src2 doesn't exist in asm string
1695 def STRD : AI3str<0b1111, (outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
1696 StMiscFrm, IIC_iStore_d_r,
1697 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
1700 def STR_PRE : AI2stridx<0, 1, (outs GPR:$Rn_wb),
1701 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1702 IndexModePre, StFrm, IIC_iStore_ru,
1703 "str", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1705 (pre_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1707 def STR_POST : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1708 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1709 IndexModePost, StFrm, IIC_iStore_ru,
1710 "str", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1712 (post_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1714 def STRB_PRE : AI2stridx<1, 1, (outs GPR:$Rn_wb),
1715 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1716 IndexModePre, StFrm, IIC_iStore_bh_ru,
1717 "strb", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1718 [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
1719 GPR:$Rn, am2offset:$offset))]>;
1720 def STRB_POST: AI2stridx<1, 0, (outs GPR:$Rn_wb),
1721 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1722 IndexModePost, StFrm, IIC_iStore_bh_ru,
1723 "strb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1724 [(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
1725 GPR:$Rn, am2offset:$offset))]>;
1727 def STRH_PRE : AI3stridx<0b1011, 0, 1, (outs GPR:$Rn_wb),
1728 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1729 IndexModePre, StMiscFrm, IIC_iStore_ru,
1730 "strh", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1732 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
1734 def STRH_POST: AI3stridx<0b1011, 0, 0, (outs GPR:$Rn_wb),
1735 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1736 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
1737 "strh", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1738 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
1739 GPR:$Rn, am3offset:$offset))]>;
1741 // For disassembly only
1742 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1743 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1744 StMiscFrm, IIC_iStore_d_ru,
1745 "strd", "\t$src1, $src2, [$base, $offset]!",
1746 "$base = $base_wb", []>;
1748 // For disassembly only
1749 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1750 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1751 StMiscFrm, IIC_iStore_d_ru,
1752 "strd", "\t$src1, $src2, [$base], $offset",
1753 "$base = $base_wb", []>;
1755 // STRT, STRBT, and STRHT are for disassembly only.
1757 def STRT : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1758 (ins GPR:$Rt, GPR:$Rn,am2offset:$offset),
1759 IndexModeNone, StFrm, IIC_iStore_ru,
1760 "strt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1761 [/* For disassembly only; pattern left blank */]> {
1762 let Inst{21} = 1; // overwrite
1765 def STRBT : AI2stridx<1, 0, (outs GPR:$Rn_wb),
1766 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1767 IndexModeNone, StFrm, IIC_iStore_bh_ru,
1768 "strbt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1769 [/* For disassembly only; pattern left blank */]> {
1770 let Inst{21} = 1; // overwrite
1773 def STRHT: AI3sthpo<(outs GPR:$base_wb),
1774 (ins GPR:$src, GPR:$base,am3offset:$offset),
1775 StMiscFrm, IIC_iStore_bh_ru,
1776 "strht", "\t$src, [$base], $offset", "$base = $base_wb",
1777 [/* For disassembly only; pattern left blank */]> {
1778 let Inst{21} = 1; // overwrite
1781 //===----------------------------------------------------------------------===//
1782 // Load / store multiple Instructions.
1785 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
1786 InstrItinClass itin, InstrItinClass itin_upd> {
1788 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1789 IndexModeNone, f, itin,
1790 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
1791 let Inst{24-23} = 0b01; // Increment After
1792 let Inst{21} = 0; // No writeback
1793 let Inst{20} = L_bit;
1796 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1797 IndexModeUpd, f, itin_upd,
1798 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1799 let Inst{24-23} = 0b01; // Increment After
1800 let Inst{21} = 1; // Writeback
1801 let Inst{20} = L_bit;
1804 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1805 IndexModeNone, f, itin,
1806 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
1807 let Inst{24-23} = 0b00; // Decrement After
1808 let Inst{21} = 0; // No writeback
1809 let Inst{20} = L_bit;
1812 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1813 IndexModeUpd, f, itin_upd,
1814 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1815 let Inst{24-23} = 0b00; // Decrement After
1816 let Inst{21} = 1; // Writeback
1817 let Inst{20} = L_bit;
1820 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1821 IndexModeNone, f, itin,
1822 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
1823 let Inst{24-23} = 0b10; // Decrement Before
1824 let Inst{21} = 0; // No writeback
1825 let Inst{20} = L_bit;
1828 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1829 IndexModeUpd, f, itin_upd,
1830 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1831 let Inst{24-23} = 0b10; // Decrement Before
1832 let Inst{21} = 1; // Writeback
1833 let Inst{20} = L_bit;
1836 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1837 IndexModeNone, f, itin,
1838 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
1839 let Inst{24-23} = 0b11; // Increment Before
1840 let Inst{21} = 0; // No writeback
1841 let Inst{20} = L_bit;
1844 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1845 IndexModeUpd, f, itin_upd,
1846 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1847 let Inst{24-23} = 0b11; // Increment Before
1848 let Inst{21} = 1; // Writeback
1849 let Inst{20} = L_bit;
1853 let neverHasSideEffects = 1 in {
1855 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1856 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
1858 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1859 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
1861 } // neverHasSideEffects
1863 // Load / Store Multiple Mnemnoic Aliases
1864 def : MnemonicAlias<"ldm", "ldmia">;
1865 def : MnemonicAlias<"stm", "stmia">;
1867 // FIXME: remove when we have a way to marking a MI with these properties.
1868 // FIXME: Should pc be an implicit operand like PICADD, etc?
1869 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1870 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1871 // FIXME: Should be a pseudo-instruction.
1872 def LDMIA_RET : AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
1873 reglist:$regs, variable_ops),
1874 IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr,
1875 "ldmia${p}\t$Rn!, $regs",
1877 let Inst{24-23} = 0b01; // Increment After
1878 let Inst{21} = 1; // Writeback
1879 let Inst{20} = 1; // Load
1882 //===----------------------------------------------------------------------===//
1883 // Move Instructions.
1886 let neverHasSideEffects = 1 in
1887 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
1888 "mov", "\t$Rd, $Rm", []>, UnaryDP {
1892 let Inst{11-4} = 0b00000000;
1895 let Inst{15-12} = Rd;
1898 // A version for the smaller set of tail call registers.
1899 let neverHasSideEffects = 1 in
1900 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
1901 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
1905 let Inst{11-4} = 0b00000000;
1908 let Inst{15-12} = Rd;
1911 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
1912 DPSoRegFrm, IIC_iMOVsr,
1913 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
1917 let Inst{15-12} = Rd;
1918 let Inst{11-0} = src;
1922 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1923 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
1924 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
1928 let Inst{15-12} = Rd;
1929 let Inst{19-16} = 0b0000;
1930 let Inst{11-0} = imm;
1933 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1934 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins movt_imm:$imm),
1936 "movw", "\t$Rd, $imm",
1937 [(set GPR:$Rd, imm0_65535:$imm)]>,
1938 Requires<[IsARM, HasV6T2]>, UnaryDP {
1941 let Inst{15-12} = Rd;
1942 let Inst{11-0} = imm{11-0};
1943 let Inst{19-16} = imm{15-12};
1948 let Constraints = "$src = $Rd" in
1949 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, movt_imm:$imm),
1951 "movt", "\t$Rd, $imm",
1953 (or (and GPR:$src, 0xffff),
1954 lo16AllZero:$imm))]>, UnaryDP,
1955 Requires<[IsARM, HasV6T2]> {
1958 let Inst{15-12} = Rd;
1959 let Inst{11-0} = imm{11-0};
1960 let Inst{19-16} = imm{15-12};
1965 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
1966 Requires<[IsARM, HasV6T2]>;
1968 let Uses = [CPSR] in
1969 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
1970 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
1973 // These aren't really mov instructions, but we have to define them this way
1974 // due to flag operands.
1976 let Defs = [CPSR] in {
1977 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1978 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
1980 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1981 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
1985 //===----------------------------------------------------------------------===//
1986 // Extend Instructions.
1991 defm SXTB : AI_ext_rrot<0b01101010,
1992 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
1993 defm SXTH : AI_ext_rrot<0b01101011,
1994 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
1996 defm SXTAB : AI_exta_rrot<0b01101010,
1997 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1998 defm SXTAH : AI_exta_rrot<0b01101011,
1999 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2001 // For disassembly only
2002 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2004 // For disassembly only
2005 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2009 let AddedComplexity = 16 in {
2010 defm UXTB : AI_ext_rrot<0b01101110,
2011 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2012 defm UXTH : AI_ext_rrot<0b01101111,
2013 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2014 defm UXTB16 : AI_ext_rrot<0b01101100,
2015 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2017 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2018 // The transformation should probably be done as a combiner action
2019 // instead so we can include a check for masking back in the upper
2020 // eight bits of the source into the lower eight bits of the result.
2021 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2022 // (UXTB16r_rot GPR:$Src, 24)>;
2023 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2024 (UXTB16r_rot GPR:$Src, 8)>;
2026 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2027 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2028 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2029 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2032 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2033 // For disassembly only
2034 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2037 def SBFX : I<(outs GPR:$Rd),
2038 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2039 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2040 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2041 Requires<[IsARM, HasV6T2]> {
2046 let Inst{27-21} = 0b0111101;
2047 let Inst{6-4} = 0b101;
2048 let Inst{20-16} = width;
2049 let Inst{15-12} = Rd;
2050 let Inst{11-7} = lsb;
2054 def UBFX : I<(outs GPR:$Rd),
2055 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2056 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2057 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2058 Requires<[IsARM, HasV6T2]> {
2063 let Inst{27-21} = 0b0111111;
2064 let Inst{6-4} = 0b101;
2065 let Inst{20-16} = width;
2066 let Inst{15-12} = Rd;
2067 let Inst{11-7} = lsb;
2071 //===----------------------------------------------------------------------===//
2072 // Arithmetic Instructions.
2075 defm ADD : AsI1_bin_irs<0b0100, "add",
2076 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2077 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
2078 defm SUB : AsI1_bin_irs<0b0010, "sub",
2079 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2080 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
2082 // ADD and SUB with 's' bit set.
2083 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
2084 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2085 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
2086 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
2087 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2088 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
2090 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
2091 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
2092 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
2093 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
2094 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
2095 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
2096 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
2097 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
2099 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2100 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
2101 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
2106 let Inst{15-12} = Rd;
2107 let Inst{19-16} = Rn;
2108 let Inst{11-0} = imm;
2111 // The reg/reg form is only defined for the disassembler; for codegen it is
2112 // equivalent to SUBrr.
2113 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2114 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
2115 [/* For disassembly only; pattern left blank */]> {
2119 let Inst{11-4} = 0b00000000;
2122 let Inst{15-12} = Rd;
2123 let Inst{19-16} = Rn;
2126 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2127 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2128 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
2133 let Inst{11-0} = shift;
2134 let Inst{15-12} = Rd;
2135 let Inst{19-16} = Rn;
2138 // RSB with 's' bit set.
2139 let Defs = [CPSR] in {
2140 def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2141 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
2142 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
2148 let Inst{15-12} = Rd;
2149 let Inst{19-16} = Rn;
2150 let Inst{11-0} = imm;
2152 def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2153 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
2154 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
2160 let Inst{11-0} = shift;
2161 let Inst{15-12} = Rd;
2162 let Inst{19-16} = Rn;
2166 let Uses = [CPSR] in {
2167 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2168 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2169 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2175 let Inst{15-12} = Rd;
2176 let Inst{19-16} = Rn;
2177 let Inst{11-0} = imm;
2179 // The reg/reg form is only defined for the disassembler; for codegen it is
2180 // equivalent to SUBrr.
2181 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2182 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2183 [/* For disassembly only; pattern left blank */]> {
2187 let Inst{11-4} = 0b00000000;
2190 let Inst{15-12} = Rd;
2191 let Inst{19-16} = Rn;
2193 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2194 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2195 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2201 let Inst{11-0} = shift;
2202 let Inst{15-12} = Rd;
2203 let Inst{19-16} = Rn;
2207 // FIXME: Allow these to be predicated.
2208 let Defs = [CPSR], Uses = [CPSR] in {
2209 def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2210 DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
2211 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2218 let Inst{15-12} = Rd;
2219 let Inst{19-16} = Rn;
2220 let Inst{11-0} = imm;
2222 def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2223 DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
2224 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2231 let Inst{11-0} = shift;
2232 let Inst{15-12} = Rd;
2233 let Inst{19-16} = Rn;
2237 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2238 // The assume-no-carry-in form uses the negation of the input since add/sub
2239 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2240 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2242 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2243 (SUBri GPR:$src, so_imm_neg:$imm)>;
2244 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2245 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2246 // The with-carry-in form matches bitwise not instead of the negation.
2247 // Effectively, the inverse interpretation of the carry flag already accounts
2248 // for part of the negation.
2249 def : ARMPat<(adde GPR:$src, so_imm_not:$imm),
2250 (SBCri GPR:$src, so_imm_not:$imm)>;
2252 // Note: These are implemented in C++ code, because they have to generate
2253 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2255 // (mul X, 2^n+1) -> (add (X << n), X)
2256 // (mul X, 2^n-1) -> (rsb X, (X << n))
2258 // ARM Arithmetic Instruction -- for disassembly only
2259 // GPR:$dst = GPR:$a op GPR:$b
2260 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2261 list<dag> pattern = [/* For disassembly only; pattern left blank */]>
2262 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iALUr,
2263 opc, "\t$Rd, $Rn, $Rm", pattern> {
2267 let Inst{27-20} = op27_20;
2268 let Inst{11-4} = op11_4;
2269 let Inst{19-16} = Rn;
2270 let Inst{15-12} = Rd;
2274 // Saturating add/subtract -- for disassembly only
2276 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2277 [(set GPR:$Rd, (int_arm_qadd GPR:$Rn, GPR:$Rm))]>;
2278 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2279 [(set GPR:$Rd, (int_arm_qsub GPR:$Rn, GPR:$Rm))]>;
2280 def QDADD : AAI<0b00010100, 0b00000101, "qdadd">;
2281 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub">;
2283 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2284 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2285 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2286 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2287 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2288 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2289 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2290 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2291 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2292 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2293 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2294 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2296 // Signed/Unsigned add/subtract -- for disassembly only
2298 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2299 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2300 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2301 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2302 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2303 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2304 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2305 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2306 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2307 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2308 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2309 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2311 // Signed/Unsigned halving add/subtract -- for disassembly only
2313 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2314 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2315 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2316 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2317 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2318 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2319 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2320 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2321 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2322 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2323 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2324 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2326 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2328 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2329 MulFrm /* for convenience */, NoItinerary, "usad8",
2330 "\t$Rd, $Rn, $Rm", []>,
2331 Requires<[IsARM, HasV6]> {
2335 let Inst{27-20} = 0b01111000;
2336 let Inst{15-12} = 0b1111;
2337 let Inst{7-4} = 0b0001;
2338 let Inst{19-16} = Rd;
2339 let Inst{11-8} = Rm;
2342 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2343 MulFrm /* for convenience */, NoItinerary, "usada8",
2344 "\t$Rd, $Rn, $Rm, $Ra", []>,
2345 Requires<[IsARM, HasV6]> {
2350 let Inst{27-20} = 0b01111000;
2351 let Inst{7-4} = 0b0001;
2352 let Inst{19-16} = Rd;
2353 let Inst{15-12} = Ra;
2354 let Inst{11-8} = Rm;
2358 // Signed/Unsigned saturate -- for disassembly only
2360 def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2361 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2362 [/* For disassembly only; pattern left blank */]> {
2367 let Inst{27-21} = 0b0110101;
2368 let Inst{5-4} = 0b01;
2369 let Inst{20-16} = sat_imm;
2370 let Inst{15-12} = Rd;
2371 let Inst{11-7} = sh{7-3};
2372 let Inst{6} = sh{0};
2376 def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm,
2377 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2378 [/* For disassembly only; pattern left blank */]> {
2382 let Inst{27-20} = 0b01101010;
2383 let Inst{11-4} = 0b11110011;
2384 let Inst{15-12} = Rd;
2385 let Inst{19-16} = sat_imm;
2389 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2390 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2391 [/* For disassembly only; pattern left blank */]> {
2396 let Inst{27-21} = 0b0110111;
2397 let Inst{5-4} = 0b01;
2398 let Inst{15-12} = Rd;
2399 let Inst{11-7} = sh{7-3};
2400 let Inst{6} = sh{0};
2401 let Inst{20-16} = sat_imm;
2405 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2406 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2407 [/* For disassembly only; pattern left blank */]> {
2411 let Inst{27-20} = 0b01101110;
2412 let Inst{11-4} = 0b11110011;
2413 let Inst{15-12} = Rd;
2414 let Inst{19-16} = sat_imm;
2418 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2419 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2421 //===----------------------------------------------------------------------===//
2422 // Bitwise Instructions.
2425 defm AND : AsI1_bin_irs<0b0000, "and",
2426 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2427 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2428 defm ORR : AsI1_bin_irs<0b1100, "orr",
2429 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2430 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2431 defm EOR : AsI1_bin_irs<0b0001, "eor",
2432 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2433 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2434 defm BIC : AsI1_bin_irs<0b1110, "bic",
2435 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2436 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2438 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2439 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2440 "bfc", "\t$Rd, $imm", "$src = $Rd",
2441 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2442 Requires<[IsARM, HasV6T2]> {
2445 let Inst{27-21} = 0b0111110;
2446 let Inst{6-0} = 0b0011111;
2447 let Inst{15-12} = Rd;
2448 let Inst{11-7} = imm{4-0}; // lsb
2449 let Inst{20-16} = imm{9-5}; // width
2452 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2453 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2454 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2455 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2456 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2457 bf_inv_mask_imm:$imm))]>,
2458 Requires<[IsARM, HasV6T2]> {
2462 let Inst{27-21} = 0b0111110;
2463 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2464 let Inst{15-12} = Rd;
2465 let Inst{11-7} = imm{4-0}; // lsb
2466 let Inst{20-16} = imm{9-5}; // width
2470 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2471 "mvn", "\t$Rd, $Rm",
2472 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2476 let Inst{19-16} = 0b0000;
2477 let Inst{11-4} = 0b00000000;
2478 let Inst{15-12} = Rd;
2481 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2482 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2483 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2487 let Inst{19-16} = 0b0000;
2488 let Inst{15-12} = Rd;
2489 let Inst{11-0} = shift;
2491 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2492 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2493 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2494 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2498 let Inst{19-16} = 0b0000;
2499 let Inst{15-12} = Rd;
2500 let Inst{11-0} = imm;
2503 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2504 (BICri GPR:$src, so_imm_not:$imm)>;
2506 //===----------------------------------------------------------------------===//
2507 // Multiply Instructions.
2509 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2510 string opc, string asm, list<dag> pattern>
2511 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2515 let Inst{19-16} = Rd;
2516 let Inst{11-8} = Rm;
2519 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2520 string opc, string asm, list<dag> pattern>
2521 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2526 let Inst{19-16} = RdHi;
2527 let Inst{15-12} = RdLo;
2528 let Inst{11-8} = Rm;
2532 let isCommutable = 1 in
2533 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2534 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2535 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>;
2537 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2538 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2539 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]> {
2541 let Inst{15-12} = Ra;
2544 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2545 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
2546 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
2547 Requires<[IsARM, HasV6T2]> {
2552 let Inst{19-16} = Rd;
2553 let Inst{15-12} = Ra;
2554 let Inst{11-8} = Rm;
2558 // Extra precision multiplies with low / high results
2560 let neverHasSideEffects = 1 in {
2561 let isCommutable = 1 in {
2562 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2563 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2564 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2566 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2567 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2568 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2571 // Multiply + accumulate
2572 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2573 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2574 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2576 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2577 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2578 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2580 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2581 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2582 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2583 Requires<[IsARM, HasV6]> {
2588 let Inst{19-16} = RdLo;
2589 let Inst{15-12} = RdHi;
2590 let Inst{11-8} = Rm;
2593 } // neverHasSideEffects
2595 // Most significant word multiply
2596 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2597 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2598 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2599 Requires<[IsARM, HasV6]> {
2600 let Inst{15-12} = 0b1111;
2603 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2604 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2605 [/* For disassembly only; pattern left blank */]>,
2606 Requires<[IsARM, HasV6]> {
2607 let Inst{15-12} = 0b1111;
2610 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2611 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2612 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2613 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2614 Requires<[IsARM, HasV6]>;
2616 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2617 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2618 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2619 [/* For disassembly only; pattern left blank */]>,
2620 Requires<[IsARM, HasV6]>;
2622 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2623 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2624 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2625 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2626 Requires<[IsARM, HasV6]>;
2628 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2629 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2630 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2631 [/* For disassembly only; pattern left blank */]>,
2632 Requires<[IsARM, HasV6]>;
2634 multiclass AI_smul<string opc, PatFrag opnode> {
2635 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2636 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2637 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2638 (sext_inreg GPR:$Rm, i16)))]>,
2639 Requires<[IsARM, HasV5TE]>;
2641 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2642 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2643 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2644 (sra GPR:$Rm, (i32 16))))]>,
2645 Requires<[IsARM, HasV5TE]>;
2647 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2648 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2649 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2650 (sext_inreg GPR:$Rm, i16)))]>,
2651 Requires<[IsARM, HasV5TE]>;
2653 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2654 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2655 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2656 (sra GPR:$Rm, (i32 16))))]>,
2657 Requires<[IsARM, HasV5TE]>;
2659 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2660 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2661 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2662 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2663 Requires<[IsARM, HasV5TE]>;
2665 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2666 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2667 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2668 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2669 Requires<[IsARM, HasV5TE]>;
2673 multiclass AI_smla<string opc, PatFrag opnode> {
2674 def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
2675 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2676 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2677 [(set GPR:$Rd, (add GPR:$Ra,
2678 (opnode (sext_inreg GPR:$Rn, i16),
2679 (sext_inreg GPR:$Rm, i16))))]>,
2680 Requires<[IsARM, HasV5TE]>;
2682 def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd),
2683 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2684 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2685 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2686 (sra GPR:$Rm, (i32 16)))))]>,
2687 Requires<[IsARM, HasV5TE]>;
2689 def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd),
2690 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2691 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2692 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2693 (sext_inreg GPR:$Rm, i16))))]>,
2694 Requires<[IsARM, HasV5TE]>;
2696 def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
2697 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2698 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2699 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2700 (sra GPR:$Rm, (i32 16)))))]>,
2701 Requires<[IsARM, HasV5TE]>;
2703 def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd),
2704 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2705 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2706 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2707 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2708 Requires<[IsARM, HasV5TE]>;
2710 def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd),
2711 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2712 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2713 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2714 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2715 Requires<[IsARM, HasV5TE]>;
2718 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2719 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2721 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2722 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2723 (ins GPR:$Rn, GPR:$Rm),
2724 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2725 [/* For disassembly only; pattern left blank */]>,
2726 Requires<[IsARM, HasV5TE]>;
2728 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2729 (ins GPR:$Rn, GPR:$Rm),
2730 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2731 [/* For disassembly only; pattern left blank */]>,
2732 Requires<[IsARM, HasV5TE]>;
2734 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2735 (ins GPR:$Rn, GPR:$Rm),
2736 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2737 [/* For disassembly only; pattern left blank */]>,
2738 Requires<[IsARM, HasV5TE]>;
2740 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2741 (ins GPR:$Rn, GPR:$Rm),
2742 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2743 [/* For disassembly only; pattern left blank */]>,
2744 Requires<[IsARM, HasV5TE]>;
2746 // Helper class for AI_smld -- for disassembly only
2747 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2748 InstrItinClass itin, string opc, string asm>
2749 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2756 let Inst{21-20} = 0b00;
2757 let Inst{22} = long;
2758 let Inst{27-23} = 0b01110;
2759 let Inst{11-8} = Rm;
2762 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2763 InstrItinClass itin, string opc, string asm>
2764 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2766 let Inst{15-12} = 0b1111;
2767 let Inst{19-16} = Rd;
2769 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2770 InstrItinClass itin, string opc, string asm>
2771 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2773 let Inst{15-12} = Ra;
2775 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2776 InstrItinClass itin, string opc, string asm>
2777 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2780 let Inst{19-16} = RdHi;
2781 let Inst{15-12} = RdLo;
2784 multiclass AI_smld<bit sub, string opc> {
2786 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2787 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
2789 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2790 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
2792 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
2793 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2794 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
2796 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
2797 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2798 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
2802 defm SMLA : AI_smld<0, "smla">;
2803 defm SMLS : AI_smld<1, "smls">;
2805 multiclass AI_sdml<bit sub, string opc> {
2807 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2808 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
2809 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2810 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
2813 defm SMUA : AI_sdml<0, "smua">;
2814 defm SMUS : AI_sdml<1, "smus">;
2816 //===----------------------------------------------------------------------===//
2817 // Misc. Arithmetic Instructions.
2820 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
2821 IIC_iUNAr, "clz", "\t$Rd, $Rm",
2822 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
2824 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2825 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
2826 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
2827 Requires<[IsARM, HasV6T2]>;
2829 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2830 IIC_iUNAr, "rev", "\t$Rd, $Rm",
2831 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
2833 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2834 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
2836 (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
2837 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
2838 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
2839 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
2840 Requires<[IsARM, HasV6]>;
2842 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2843 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
2846 (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
2847 (shl GPR:$Rm, (i32 8))), i16))]>,
2848 Requires<[IsARM, HasV6]>;
2850 def lsl_shift_imm : SDNodeXForm<imm, [{
2851 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
2852 return CurDAG->getTargetConstant(Sh, MVT::i32);
2855 def lsl_amt : PatLeaf<(i32 imm), [{
2856 return (N->getZExtValue() < 32);
2859 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
2860 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2861 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2862 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
2863 (and (shl GPR:$Rm, lsl_amt:$sh),
2865 Requires<[IsARM, HasV6]>;
2867 // Alternate cases for PKHBT where identities eliminate some nodes.
2868 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
2869 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
2870 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
2871 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
2873 def asr_shift_imm : SDNodeXForm<imm, [{
2874 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
2875 return CurDAG->getTargetConstant(Sh, MVT::i32);
2878 def asr_amt : PatLeaf<(i32 imm), [{
2879 return (N->getZExtValue() <= 32);
2882 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2883 // will match the pattern below.
2884 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
2885 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2886 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2887 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
2888 (and (sra GPR:$Rm, asr_amt:$sh),
2890 Requires<[IsARM, HasV6]>;
2892 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2893 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2894 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
2895 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
2896 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
2897 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
2898 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
2900 //===----------------------------------------------------------------------===//
2901 // Comparison Instructions...
2904 defm CMP : AI1_cmp_irs<0b1010, "cmp",
2905 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2906 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2908 // ARMcmpZ can re-use the above instruction definitions.
2909 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
2910 (CMPri GPR:$src, so_imm:$imm)>;
2911 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
2912 (CMPrr GPR:$src, GPR:$rhs)>;
2913 def : ARMPat<(ARMcmpZ GPR:$src, so_reg:$rhs),
2914 (CMPrs GPR:$src, so_reg:$rhs)>;
2916 // FIXME: We have to be careful when using the CMN instruction and comparison
2917 // with 0. One would expect these two pieces of code should give identical
2933 // However, the CMN gives the *opposite* result when r1 is 0. This is because
2934 // the carry flag is set in the CMP case but not in the CMN case. In short, the
2935 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
2936 // value of r0 and the carry bit (because the "carry bit" parameter to
2937 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
2938 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
2939 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
2940 // parameter to AddWithCarry is defined as 0).
2942 // When x is 0 and unsigned:
2946 // ~x + 1 = 0x1 0000 0000
2947 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
2949 // Therefore, we should disable CMN when comparing against zero, until we can
2950 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
2951 // when it's a comparison which doesn't look at the 'carry' flag).
2953 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
2955 // This is related to <rdar://problem/7569620>.
2957 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
2958 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2960 // Note that TST/TEQ don't set all the same flags that CMP does!
2961 defm TST : AI1_cmp_irs<0b1000, "tst",
2962 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2963 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
2964 defm TEQ : AI1_cmp_irs<0b1001, "teq",
2965 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2966 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
2968 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
2969 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2970 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2972 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
2973 // (CMNri GPR:$src, so_imm_neg:$imm)>;
2975 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
2976 (CMNzri GPR:$src, so_imm_neg:$imm)>;
2978 // Pseudo i64 compares for some floating point compares.
2979 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
2981 def BCCi64 : PseudoInst<(outs),
2982 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
2984 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
2986 def BCCZi64 : PseudoInst<(outs),
2987 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
2988 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
2989 } // usesCustomInserter
2992 // Conditional moves
2993 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2994 // a two-value operand where a dag node expects two operands. :(
2995 // FIXME: These should all be pseudo-instructions that get expanded to
2996 // the normal MOV instructions. That would fix the dependency on
2997 // special casing them in tblgen.
2998 let neverHasSideEffects = 1 in {
2999 def MOVCCr : AI1<0b1101, (outs GPR:$Rd), (ins GPR:$false, GPR:$Rm), DPFrm,
3000 IIC_iCMOVr, "mov", "\t$Rd, $Rm",
3001 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3002 RegConstraint<"$false = $Rd">, UnaryDP {
3007 let Inst{15-12} = Rd;
3008 let Inst{11-4} = 0b00000000;
3012 def MOVCCs : AI1<0b1101, (outs GPR:$Rd),
3013 (ins GPR:$false, so_reg:$shift), DPSoRegFrm, IIC_iCMOVsr,
3014 "mov", "\t$Rd, $shift",
3015 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
3016 RegConstraint<"$false = $Rd">, UnaryDP {
3021 let Inst{19-16} = 0;
3022 let Inst{15-12} = Rd;
3023 let Inst{11-0} = shift;
3026 let isMoveImm = 1 in
3027 def MOVCCi16 : AI1<0b1000, (outs GPR:$Rd), (ins GPR:$false, movt_imm:$imm),
3029 "movw", "\t$Rd, $imm",
3031 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
3037 let Inst{19-16} = imm{15-12};
3038 let Inst{15-12} = Rd;
3039 let Inst{11-0} = imm{11-0};
3042 let isMoveImm = 1 in
3043 def MOVCCi : AI1<0b1101, (outs GPR:$Rd),
3044 (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi,
3045 "mov", "\t$Rd, $imm",
3046 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3047 RegConstraint<"$false = $Rd">, UnaryDP {
3052 let Inst{19-16} = 0b0000;
3053 let Inst{15-12} = Rd;
3054 let Inst{11-0} = imm;
3057 // Two instruction predicate mov immediate.
3058 let isMoveImm = 1 in
3059 def MOVCCi32imm : PseudoInst<(outs GPR:$Rd),
3060 (ins GPR:$false, i32imm:$src, pred:$p),
3061 IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3063 let isMoveImm = 1 in
3064 def MVNCCi : AI1<0b1111, (outs GPR:$Rd),
3065 (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi,
3066 "mvn", "\t$Rd, $imm",
3067 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3068 RegConstraint<"$false = $Rd">, UnaryDP {
3073 let Inst{19-16} = 0b0000;
3074 let Inst{15-12} = Rd;
3075 let Inst{11-0} = imm;
3077 } // neverHasSideEffects
3079 //===----------------------------------------------------------------------===//
3080 // Atomic operations intrinsics
3083 def memb_opt : Operand<i32> {
3084 let PrintMethod = "printMemBOption";
3087 // memory barriers protect the atomic sequences
3088 let hasSideEffects = 1 in {
3089 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3090 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3091 Requires<[IsARM, HasDB]> {
3093 let Inst{31-4} = 0xf57ff05;
3094 let Inst{3-0} = opt;
3097 def DMB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary,
3098 "mcr", "\tp15, 0, $zero, c7, c10, 5",
3099 [(ARMMemBarrierMCR GPR:$zero)]>,
3100 Requires<[IsARM, HasV6]> {
3101 // FIXME: add encoding
3105 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3107 [/* For disassembly only; pattern left blank */]>,
3108 Requires<[IsARM, HasDB]> {
3110 let Inst{31-4} = 0xf57ff04;
3111 let Inst{3-0} = opt;
3114 // ISB has only full system option -- for disassembly only
3115 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
3116 Requires<[IsARM, HasDB]> {
3117 let Inst{31-4} = 0xf57ff06;
3118 let Inst{3-0} = 0b1111;
3121 let usesCustomInserter = 1 in {
3122 let Uses = [CPSR] in {
3123 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
3124 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3125 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
3126 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
3127 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3128 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
3129 def ATOMIC_LOAD_AND_I8 : PseudoInst<
3130 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3131 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
3132 def ATOMIC_LOAD_OR_I8 : PseudoInst<
3133 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3134 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
3135 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
3136 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3137 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
3138 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
3139 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3140 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
3141 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
3142 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3143 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
3144 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
3145 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3146 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
3147 def ATOMIC_LOAD_AND_I16 : PseudoInst<
3148 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3149 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
3150 def ATOMIC_LOAD_OR_I16 : PseudoInst<
3151 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3152 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
3153 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
3154 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3155 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
3156 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
3157 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3158 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
3159 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
3160 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3161 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
3162 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
3163 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3164 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
3165 def ATOMIC_LOAD_AND_I32 : PseudoInst<
3166 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3167 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
3168 def ATOMIC_LOAD_OR_I32 : PseudoInst<
3169 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3170 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
3171 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
3172 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3173 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
3174 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
3175 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3176 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
3178 def ATOMIC_SWAP_I8 : PseudoInst<
3179 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3180 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3181 def ATOMIC_SWAP_I16 : PseudoInst<
3182 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3183 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3184 def ATOMIC_SWAP_I32 : PseudoInst<
3185 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3186 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3188 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3189 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3190 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3191 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3192 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3193 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3194 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3195 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3196 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3200 let mayLoad = 1 in {
3201 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3202 "ldrexb", "\t$Rt, [$Rn]",
3204 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3205 "ldrexh", "\t$Rt, [$Rn]",
3207 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3208 "ldrex", "\t$Rt, [$Rn]",
3210 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins GPR:$Rn),
3212 "ldrexd", "\t$Rt, $Rt2, [$Rn]",
3216 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3217 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$src, GPR:$Rn),
3219 "strexb", "\t$Rd, $src, [$Rn]",
3221 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3223 "strexh", "\t$Rd, $Rt, [$Rn]",
3225 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3227 "strex", "\t$Rd, $Rt, [$Rn]",
3229 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3230 (ins GPR:$Rt, GPR:$Rt2, GPR:$Rn),
3232 "strexd", "\t$Rd, $Rt, $Rt2, [$Rn]",
3236 // Clear-Exclusive is for disassembly only.
3237 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3238 [/* For disassembly only; pattern left blank */]>,
3239 Requires<[IsARM, HasV7]> {
3240 let Inst{31-0} = 0b11110101011111111111000000011111;
3243 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3244 let mayLoad = 1 in {
3245 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3246 [/* For disassembly only; pattern left blank */]>;
3247 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3248 [/* For disassembly only; pattern left blank */]>;
3251 //===----------------------------------------------------------------------===//
3255 // __aeabi_read_tp preserves the registers r1-r3.
3256 // This is a pseudo inst so that we can get the encoding right,
3257 // complete with fixup for the aeabi_read_tp function.
3259 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
3260 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
3261 [(set R0, ARMthread_pointer)]>;
3264 //===----------------------------------------------------------------------===//
3265 // SJLJ Exception handling intrinsics
3266 // eh_sjlj_setjmp() is an instruction sequence to store the return
3267 // address and save #0 in R0 for the non-longjmp case.
3268 // Since by its nature we may be coming from some other function to get
3269 // here, and we're using the stack frame for the containing function to
3270 // save/restore registers, we can't keep anything live in regs across
3271 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3272 // when we get here from a longjmp(). We force everthing out of registers
3273 // except for our own input by listing the relevant registers in Defs. By
3274 // doing so, we also cause the prologue/epilogue code to actively preserve
3275 // all of the callee-saved resgisters, which is exactly what we want.
3276 // A constant value is passed in $val, and we use the location as a scratch.
3278 // These are pseudo-instructions and are lowered to individual MC-insts, so
3279 // no encoding information is necessary.
3281 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
3282 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
3283 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
3284 D31 ], hasSideEffects = 1, isBarrier = 1 in {
3285 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3287 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3288 Requires<[IsARM, HasVFP2]>;
3292 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
3293 hasSideEffects = 1, isBarrier = 1 in {
3294 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3296 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3297 Requires<[IsARM, NoVFP]>;
3300 // FIXME: Non-Darwin version(s)
3301 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3302 Defs = [ R7, LR, SP ] in {
3303 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
3305 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3306 Requires<[IsARM, IsDarwin]>;
3309 // eh.sjlj.dispatchsetup pseudo-instruction.
3310 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3311 // handled when the pseudo is expanded (which happens before any passes
3312 // that need the instruction size).
3313 let isBarrier = 1, hasSideEffects = 1 in
3314 def Int_eh_sjlj_dispatchsetup :
3315 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
3316 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
3317 Requires<[IsDarwin]>;
3319 //===----------------------------------------------------------------------===//
3320 // Non-Instruction Patterns
3323 // Large immediate handling.
3325 // 32-bit immediate using two piece so_imms or movw + movt.
3326 // This is a single pseudo instruction, the benefit is that it can be remat'd
3327 // as a single unit instead of having to handle reg inputs.
3328 // FIXME: Remove this when we can do generalized remat.
3329 let isReMaterializable = 1, isMoveImm = 1 in
3330 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3331 [(set GPR:$dst, (arm_i32imm:$src))]>,
3334 // ConstantPool, GlobalAddress, and JumpTable
3335 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3336 Requires<[IsARM, DontUseMovt]>;
3337 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3338 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3339 Requires<[IsARM, UseMovt]>;
3340 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3341 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3343 // TODO: add,sub,and, 3-instr forms?
3346 def : ARMPat<(ARMtcret tcGPR:$dst),
3347 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3349 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3350 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3352 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3353 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3355 def : ARMPat<(ARMtcret tcGPR:$dst),
3356 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3358 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3359 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3361 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3362 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3365 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3366 Requires<[IsARM, IsNotDarwin]>;
3367 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3368 Requires<[IsARM, IsDarwin]>;
3370 // zextload i1 -> zextload i8
3371 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3372 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3374 // extload -> zextload
3375 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3376 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3377 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3378 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3380 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3382 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3383 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3386 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3387 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3388 (SMULBB GPR:$a, GPR:$b)>;
3389 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3390 (SMULBB GPR:$a, GPR:$b)>;
3391 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3392 (sra GPR:$b, (i32 16))),
3393 (SMULBT GPR:$a, GPR:$b)>;
3394 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3395 (SMULBT GPR:$a, GPR:$b)>;
3396 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3397 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3398 (SMULTB GPR:$a, GPR:$b)>;
3399 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3400 (SMULTB GPR:$a, GPR:$b)>;
3401 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3403 (SMULWB GPR:$a, GPR:$b)>;
3404 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3405 (SMULWB GPR:$a, GPR:$b)>;
3407 def : ARMV5TEPat<(add GPR:$acc,
3408 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3409 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3410 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3411 def : ARMV5TEPat<(add GPR:$acc,
3412 (mul sext_16_node:$a, sext_16_node:$b)),
3413 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3414 def : ARMV5TEPat<(add GPR:$acc,
3415 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3416 (sra GPR:$b, (i32 16)))),
3417 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3418 def : ARMV5TEPat<(add GPR:$acc,
3419 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3420 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3421 def : ARMV5TEPat<(add GPR:$acc,
3422 (mul (sra GPR:$a, (i32 16)),
3423 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3424 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3425 def : ARMV5TEPat<(add GPR:$acc,
3426 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3427 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3428 def : ARMV5TEPat<(add GPR:$acc,
3429 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3431 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3432 def : ARMV5TEPat<(add GPR:$acc,
3433 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3434 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3436 //===----------------------------------------------------------------------===//
3440 include "ARMInstrThumb.td"
3442 //===----------------------------------------------------------------------===//
3446 include "ARMInstrThumb2.td"
3448 //===----------------------------------------------------------------------===//
3449 // Floating Point Support
3452 include "ARMInstrVFP.td"
3454 //===----------------------------------------------------------------------===//
3455 // Advanced SIMD (NEON) Support
3458 include "ARMInstrNEON.td"
3460 //===----------------------------------------------------------------------===//
3461 // Coprocessor Instructions. For disassembly only.
3464 def CDP : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3465 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3466 NoItinerary, "cdp", "\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3467 [/* For disassembly only; pattern left blank */]> {
3471 def CDP2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3472 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3473 NoItinerary, "cdp2\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3474 [/* For disassembly only; pattern left blank */]> {
3475 let Inst{31-28} = 0b1111;
3479 class ACI<dag oops, dag iops, string opc, string asm>
3480 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
3481 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3482 let Inst{27-25} = 0b110;
3485 multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
3487 def _OFFSET : ACI<(outs),
3488 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3489 opc, "\tp$cop, cr$CRd, $addr"> {
3490 let Inst{31-28} = op31_28;
3491 let Inst{24} = 1; // P = 1
3492 let Inst{21} = 0; // W = 0
3493 let Inst{22} = 0; // D = 0
3494 let Inst{20} = load;
3497 def _PRE : ACI<(outs),
3498 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3499 opc, "\tp$cop, cr$CRd, $addr!"> {
3500 let Inst{31-28} = op31_28;
3501 let Inst{24} = 1; // P = 1
3502 let Inst{21} = 1; // W = 1
3503 let Inst{22} = 0; // D = 0
3504 let Inst{20} = load;
3507 def _POST : ACI<(outs),
3508 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3509 opc, "\tp$cop, cr$CRd, [$base], $offset"> {
3510 let Inst{31-28} = op31_28;
3511 let Inst{24} = 0; // P = 0
3512 let Inst{21} = 1; // W = 1
3513 let Inst{22} = 0; // D = 0
3514 let Inst{20} = load;
3517 def _OPTION : ACI<(outs),
3518 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option),
3519 opc, "\tp$cop, cr$CRd, [$base], $option"> {
3520 let Inst{31-28} = op31_28;
3521 let Inst{24} = 0; // P = 0
3522 let Inst{23} = 1; // U = 1
3523 let Inst{21} = 0; // W = 0
3524 let Inst{22} = 0; // D = 0
3525 let Inst{20} = load;
3528 def L_OFFSET : ACI<(outs),
3529 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3530 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
3531 let Inst{31-28} = op31_28;
3532 let Inst{24} = 1; // P = 1
3533 let Inst{21} = 0; // W = 0
3534 let Inst{22} = 1; // D = 1
3535 let Inst{20} = load;
3538 def L_PRE : ACI<(outs),
3539 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3540 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
3541 let Inst{31-28} = op31_28;
3542 let Inst{24} = 1; // P = 1
3543 let Inst{21} = 1; // W = 1
3544 let Inst{22} = 1; // D = 1
3545 let Inst{20} = load;
3548 def L_POST : ACI<(outs),
3549 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3550 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $offset"> {
3551 let Inst{31-28} = op31_28;
3552 let Inst{24} = 0; // P = 0
3553 let Inst{21} = 1; // W = 1
3554 let Inst{22} = 1; // D = 1
3555 let Inst{20} = load;
3558 def L_OPTION : ACI<(outs),
3559 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
3560 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $option"> {
3561 let Inst{31-28} = op31_28;
3562 let Inst{24} = 0; // P = 0
3563 let Inst{23} = 1; // U = 1
3564 let Inst{21} = 0; // W = 0
3565 let Inst{22} = 1; // D = 1
3566 let Inst{20} = load;
3570 defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">;
3571 defm LDC2 : LdStCop<0b1111, 1, "ldc2">;
3572 defm STC : LdStCop<{?,?,?,?}, 0, "stc">;
3573 defm STC2 : LdStCop<0b1111, 0, "stc2">;
3575 def MCR : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3576 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3577 NoItinerary, "mcr", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3578 [/* For disassembly only; pattern left blank */]> {
3583 def MCR2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3584 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3585 NoItinerary, "mcr2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3586 [/* For disassembly only; pattern left blank */]> {
3587 let Inst{31-28} = 0b1111;
3592 def MRC : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3593 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3594 NoItinerary, "mrc", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3595 [/* For disassembly only; pattern left blank */]> {
3600 def MRC2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3601 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3602 NoItinerary, "mrc2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3603 [/* For disassembly only; pattern left blank */]> {
3604 let Inst{31-28} = 0b1111;
3609 def MCRR : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3610 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3611 NoItinerary, "mcrr", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3612 [/* For disassembly only; pattern left blank */]> {
3613 let Inst{23-20} = 0b0100;
3616 def MCRR2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3617 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3618 NoItinerary, "mcrr2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3619 [/* For disassembly only; pattern left blank */]> {
3620 let Inst{31-28} = 0b1111;
3621 let Inst{23-20} = 0b0100;
3624 def MRRC : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3625 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3626 NoItinerary, "mrrc", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3627 [/* For disassembly only; pattern left blank */]> {
3628 let Inst{23-20} = 0b0101;
3631 def MRRC2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3632 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3633 NoItinerary, "mrrc2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3634 [/* For disassembly only; pattern left blank */]> {
3635 let Inst{31-28} = 0b1111;
3636 let Inst{23-20} = 0b0101;
3639 //===----------------------------------------------------------------------===//
3640 // Move between special register and ARM core register -- for disassembly only
3643 def MRS : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary, "mrs", "\t$dst, cpsr",
3644 [/* For disassembly only; pattern left blank */]> {
3645 let Inst{23-20} = 0b0000;
3646 let Inst{7-4} = 0b0000;
3649 def MRSsys : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary,"mrs","\t$dst, spsr",
3650 [/* For disassembly only; pattern left blank */]> {
3651 let Inst{23-20} = 0b0100;
3652 let Inst{7-4} = 0b0000;
3655 def MSR : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3656 "msr", "\tcpsr$mask, $src",
3657 [/* For disassembly only; pattern left blank */]> {
3658 let Inst{23-20} = 0b0010;
3659 let Inst{7-4} = 0b0000;
3662 def MSRi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3663 "msr", "\tcpsr$mask, $a",
3664 [/* For disassembly only; pattern left blank */]> {
3665 let Inst{23-20} = 0b0010;
3666 let Inst{7-4} = 0b0000;
3669 def MSRsys : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3670 "msr", "\tspsr$mask, $src",
3671 [/* For disassembly only; pattern left blank */]> {
3672 let Inst{23-20} = 0b0110;
3673 let Inst{7-4} = 0b0000;
3676 def MSRsysi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3677 "msr", "\tspsr$mask, $a",
3678 [/* For disassembly only; pattern left blank */]> {
3679 let Inst{23-20} = 0b0110;
3680 let Inst{7-4} = 0b0000;