1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisInt<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
68 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
70 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
71 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
73 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
76 SDTCisInt<0>, SDTCisVT<1, i32>]>;
78 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
79 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
86 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
87 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
88 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
89 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
91 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
92 [SDNPHasChain, SDNPOutGlue]>;
93 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
94 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
96 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
97 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
99 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
100 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
102 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
103 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
106 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
107 [SDNPHasChain, SDNPOptInGlue]>;
109 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
112 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
113 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
115 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
117 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
120 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
123 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
126 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
127 [SDNPOutGlue, SDNPCommutative]>;
129 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
131 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
132 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
133 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
135 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
137 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
138 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
139 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
141 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
142 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
143 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
144 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
145 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
146 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
147 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
150 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
152 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
154 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
155 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
157 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
159 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
160 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
163 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
165 //===----------------------------------------------------------------------===//
166 // ARM Instruction Predicate Definitions.
168 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
169 AssemblerPredicate<"HasV4TOps">;
170 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
171 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
172 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
173 AssemblerPredicate<"HasV5TEOps">;
174 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
175 AssemblerPredicate<"HasV6Ops">;
176 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
177 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
178 AssemblerPredicate<"HasV6T2Ops">;
179 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
180 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
181 AssemblerPredicate<"HasV7Ops">;
182 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
183 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
184 AssemblerPredicate<"FeatureVFP2">;
185 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
186 AssemblerPredicate<"FeatureVFP3">;
187 def HasNEON : Predicate<"Subtarget->hasNEON()">,
188 AssemblerPredicate<"FeatureNEON">;
189 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
190 AssemblerPredicate<"FeatureFP16">;
191 def HasDivide : Predicate<"Subtarget->hasDivide()">,
192 AssemblerPredicate<"FeatureHWDiv">;
193 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
194 AssemblerPredicate<"FeatureT2XtPk">;
195 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
196 AssemblerPredicate<"FeatureDSPThumb2">;
197 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
198 AssemblerPredicate<"FeatureDB">;
199 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
200 AssemblerPredicate<"FeatureMP">;
201 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
202 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
203 def IsThumb : Predicate<"Subtarget->isThumb()">,
204 AssemblerPredicate<"ModeThumb">;
205 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
206 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
207 AssemblerPredicate<"ModeThumb,FeatureThumb2">;
208 def IsMClass : Predicate<"Subtarget->isMClass()">,
209 AssemblerPredicate<"FeatureMClass">;
210 def IsARClass : Predicate<"!Subtarget->isMClass()">,
211 AssemblerPredicate<"!FeatureMClass">;
212 def IsARM : Predicate<"!Subtarget->isThumb()">,
213 AssemblerPredicate<"!ModeThumb">;
214 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
215 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
216 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
218 // FIXME: Eventually this will be just "hasV6T2Ops".
219 def UseMovt : Predicate<"Subtarget->useMovt()">;
220 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
221 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
223 //===----------------------------------------------------------------------===//
224 // ARM Flag Definitions.
226 class RegConstraint<string C> {
227 string Constraints = C;
230 //===----------------------------------------------------------------------===//
231 // ARM specific transformation functions and pattern fragments.
234 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
235 // so_imm_neg def below.
236 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
237 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
240 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
241 // so_imm_not def below.
242 def so_imm_not_XFORM : SDNodeXForm<imm, [{
243 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
246 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
247 def imm1_15 : ImmLeaf<i32, [{
248 return (int32_t)Imm >= 1 && (int32_t)Imm < 16;
251 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
252 def imm16_31 : ImmLeaf<i32, [{
253 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
258 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
259 }], so_imm_neg_XFORM>;
261 // Note: this pattern doesn't require an encoder method and such, as it's
262 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
263 // is handled by the destination instructions, which use t2_so_imm.
264 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
266 Operand<i32>, PatLeaf<(imm), [{
267 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
268 }], so_imm_not_XFORM> {
269 let ParserMatchClass = so_imm_not_asmoperand;
272 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
273 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
274 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
277 /// Split a 32-bit immediate into two 16 bit parts.
278 def hi16 : SDNodeXForm<imm, [{
279 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
282 def lo16AllZero : PatLeaf<(i32 imm), [{
283 // Returns true if all low 16-bits are 0.
284 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
287 /// imm0_65535 - An immediate is in the range [0.65535].
288 def Imm0_65535AsmOperand: AsmOperandClass { let Name = "Imm0_65535"; }
289 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
290 return Imm >= 0 && Imm < 65536;
292 let ParserMatchClass = Imm0_65535AsmOperand;
295 class BinOpWithFlagFrag<dag res> :
296 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
297 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
298 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
300 // An 'and' node with a single use.
301 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
302 return N->hasOneUse();
305 // An 'xor' node with a single use.
306 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
307 return N->hasOneUse();
310 // An 'fmul' node with a single use.
311 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
312 return N->hasOneUse();
315 // An 'fadd' node which checks for single non-hazardous use.
316 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
317 return hasNoVMLxHazardUse(N);
320 // An 'fsub' node which checks for single non-hazardous use.
321 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
322 return hasNoVMLxHazardUse(N);
325 //===----------------------------------------------------------------------===//
326 // Operand Definitions.
330 // FIXME: rename brtarget to t2_brtarget
331 def brtarget : Operand<OtherVT> {
332 let EncoderMethod = "getBranchTargetOpValue";
333 let OperandType = "OPERAND_PCREL";
334 let DecoderMethod = "DecodeT2BROperand";
337 // FIXME: get rid of this one?
338 def uncondbrtarget : Operand<OtherVT> {
339 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
340 let OperandType = "OPERAND_PCREL";
343 // Branch target for ARM. Handles conditional/unconditional
344 def br_target : Operand<OtherVT> {
345 let EncoderMethod = "getARMBranchTargetOpValue";
346 let OperandType = "OPERAND_PCREL";
350 // FIXME: rename bltarget to t2_bl_target?
351 def bltarget : Operand<i32> {
352 // Encoded the same as branch targets.
353 let EncoderMethod = "getBranchTargetOpValue";
354 let OperandType = "OPERAND_PCREL";
357 // Call target for ARM. Handles conditional/unconditional
358 // FIXME: rename bl_target to t2_bltarget?
359 def bl_target : Operand<i32> {
360 // Encoded the same as branch targets.
361 let EncoderMethod = "getARMBranchTargetOpValue";
362 let OperandType = "OPERAND_PCREL";
365 def blx_target : Operand<i32> {
366 // Encoded the same as branch targets.
367 let EncoderMethod = "getARMBLXTargetOpValue";
368 let OperandType = "OPERAND_PCREL";
371 // A list of registers separated by comma. Used by load/store multiple.
372 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
373 def reglist : Operand<i32> {
374 let EncoderMethod = "getRegisterListOpValue";
375 let ParserMatchClass = RegListAsmOperand;
376 let PrintMethod = "printRegisterList";
377 let DecoderMethod = "DecodeRegListOperand";
380 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
381 def dpr_reglist : Operand<i32> {
382 let EncoderMethod = "getRegisterListOpValue";
383 let ParserMatchClass = DPRRegListAsmOperand;
384 let PrintMethod = "printRegisterList";
385 let DecoderMethod = "DecodeDPRRegListOperand";
388 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
389 def spr_reglist : Operand<i32> {
390 let EncoderMethod = "getRegisterListOpValue";
391 let ParserMatchClass = SPRRegListAsmOperand;
392 let PrintMethod = "printRegisterList";
393 let DecoderMethod = "DecodeSPRRegListOperand";
396 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
397 def cpinst_operand : Operand<i32> {
398 let PrintMethod = "printCPInstOperand";
402 def pclabel : Operand<i32> {
403 let PrintMethod = "printPCLabel";
406 // ADR instruction labels.
407 def adrlabel : Operand<i32> {
408 let EncoderMethod = "getAdrLabelOpValue";
411 def neon_vcvt_imm32 : Operand<i32> {
412 let EncoderMethod = "getNEONVcvtImm32OpValue";
413 let DecoderMethod = "DecodeVCVTImmOperand";
416 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
417 def rot_imm_XFORM: SDNodeXForm<imm, [{
418 switch (N->getZExtValue()){
420 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
421 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
422 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
423 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
426 def RotImmAsmOperand : AsmOperandClass {
428 let ParserMethod = "parseRotImm";
430 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
431 int32_t v = N->getZExtValue();
432 return v == 8 || v == 16 || v == 24; }],
434 let PrintMethod = "printRotImmOperand";
435 let ParserMatchClass = RotImmAsmOperand;
438 // shift_imm: An integer that encodes a shift amount and the type of shift
439 // (asr or lsl). The 6-bit immediate encodes as:
442 // {4-0} imm5 shift amount.
443 // asr #32 encoded as imm5 == 0.
444 def ShifterImmAsmOperand : AsmOperandClass {
445 let Name = "ShifterImm";
446 let ParserMethod = "parseShifterImm";
448 def shift_imm : Operand<i32> {
449 let PrintMethod = "printShiftImmOperand";
450 let ParserMatchClass = ShifterImmAsmOperand;
453 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
454 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
455 def so_reg_reg : Operand<i32>, // reg reg imm
456 ComplexPattern<i32, 3, "SelectRegShifterOperand",
457 [shl, srl, sra, rotr]> {
458 let EncoderMethod = "getSORegRegOpValue";
459 let PrintMethod = "printSORegRegOperand";
460 let DecoderMethod = "DecodeSORegRegOperand";
461 let ParserMatchClass = ShiftedRegAsmOperand;
462 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
465 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
466 def so_reg_imm : Operand<i32>, // reg imm
467 ComplexPattern<i32, 2, "SelectImmShifterOperand",
468 [shl, srl, sra, rotr]> {
469 let EncoderMethod = "getSORegImmOpValue";
470 let PrintMethod = "printSORegImmOperand";
471 let DecoderMethod = "DecodeSORegImmOperand";
472 let ParserMatchClass = ShiftedImmAsmOperand;
473 let MIOperandInfo = (ops GPR, i32imm);
476 // FIXME: Does this need to be distinct from so_reg?
477 def shift_so_reg_reg : Operand<i32>, // reg reg imm
478 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
479 [shl,srl,sra,rotr]> {
480 let EncoderMethod = "getSORegRegOpValue";
481 let PrintMethod = "printSORegRegOperand";
482 let DecoderMethod = "DecodeSORegRegOperand";
483 let MIOperandInfo = (ops GPR, GPR, i32imm);
486 // FIXME: Does this need to be distinct from so_reg?
487 def shift_so_reg_imm : Operand<i32>, // reg reg imm
488 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
489 [shl,srl,sra,rotr]> {
490 let EncoderMethod = "getSORegImmOpValue";
491 let PrintMethod = "printSORegImmOperand";
492 let DecoderMethod = "DecodeSORegImmOperand";
493 let MIOperandInfo = (ops GPR, i32imm);
497 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
498 // 8-bit immediate rotated by an arbitrary number of bits.
499 def SOImmAsmOperand: AsmOperandClass { let Name = "ARMSOImm"; }
500 def so_imm : Operand<i32>, ImmLeaf<i32, [{
501 return ARM_AM::getSOImmVal(Imm) != -1;
503 let EncoderMethod = "getSOImmOpValue";
504 let ParserMatchClass = SOImmAsmOperand;
505 let DecoderMethod = "DecodeSOImmOperand";
508 // Break so_imm's up into two pieces. This handles immediates with up to 16
509 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
510 // get the first/second pieces.
511 def so_imm2part : PatLeaf<(imm), [{
512 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
515 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
517 def arm_i32imm : PatLeaf<(imm), [{
518 if (Subtarget->hasV6T2Ops())
520 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
523 /// imm0_7 predicate - Immediate in the range [0,7].
524 def Imm0_7AsmOperand: AsmOperandClass { let Name = "Imm0_7"; }
525 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
526 return Imm >= 0 && Imm < 8;
528 let ParserMatchClass = Imm0_7AsmOperand;
531 /// imm0_15 predicate - Immediate in the range [0,15].
532 def Imm0_15AsmOperand: AsmOperandClass { let Name = "Imm0_15"; }
533 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
534 return Imm >= 0 && Imm < 16;
536 let ParserMatchClass = Imm0_15AsmOperand;
539 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
540 def Imm0_31AsmOperand: AsmOperandClass { let Name = "Imm0_31"; }
541 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
542 return Imm >= 0 && Imm < 32;
544 let ParserMatchClass = Imm0_31AsmOperand;
547 /// imm0_255 predicate - Immediate in the range [0,255].
548 def Imm0_255AsmOperand : AsmOperandClass { let Name = "Imm0_255"; }
549 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
550 let ParserMatchClass = Imm0_255AsmOperand;
553 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
554 // a relocatable expression.
556 // FIXME: This really needs a Thumb version separate from the ARM version.
557 // While the range is the same, and can thus use the same match class,
558 // the encoding is different so it should have a different encoder method.
559 def Imm0_65535ExprAsmOperand: AsmOperandClass { let Name = "Imm0_65535Expr"; }
560 def imm0_65535_expr : Operand<i32> {
561 let EncoderMethod = "getHiLo16ImmOpValue";
562 let ParserMatchClass = Imm0_65535ExprAsmOperand;
565 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
566 def Imm24bitAsmOperand: AsmOperandClass { let Name = "Imm24bit"; }
567 def imm24b : Operand<i32>, ImmLeaf<i32, [{
568 return Imm >= 0 && Imm <= 0xffffff;
570 let ParserMatchClass = Imm24bitAsmOperand;
574 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
576 def BitfieldAsmOperand : AsmOperandClass {
577 let Name = "Bitfield";
578 let ParserMethod = "parseBitfield";
580 def bf_inv_mask_imm : Operand<i32>,
582 return ARM::isBitFieldInvertedMask(N->getZExtValue());
584 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
585 let PrintMethod = "printBitfieldInvMaskImmOperand";
586 let DecoderMethod = "DecodeBitfieldMaskOperand";
587 let ParserMatchClass = BitfieldAsmOperand;
590 def imm1_32_XFORM: SDNodeXForm<imm, [{
591 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
593 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
594 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
595 uint64_t Imm = N->getZExtValue();
596 return Imm > 0 && Imm <= 32;
599 let PrintMethod = "printImmPlusOneOperand";
600 let ParserMatchClass = Imm1_32AsmOperand;
603 def imm1_16_XFORM: SDNodeXForm<imm, [{
604 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
606 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
607 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
609 let PrintMethod = "printImmPlusOneOperand";
610 let ParserMatchClass = Imm1_16AsmOperand;
613 // Define ARM specific addressing modes.
614 // addrmode_imm12 := reg +/- imm12
616 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
617 def addrmode_imm12 : Operand<i32>,
618 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
619 // 12-bit immediate operand. Note that instructions using this encode
620 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
621 // immediate values are as normal.
623 let EncoderMethod = "getAddrModeImm12OpValue";
624 let PrintMethod = "printAddrModeImm12Operand";
625 let DecoderMethod = "DecodeAddrModeImm12Operand";
626 let ParserMatchClass = MemImm12OffsetAsmOperand;
627 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
629 // ldst_so_reg := reg +/- reg shop imm
631 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
632 def ldst_so_reg : Operand<i32>,
633 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
634 let EncoderMethod = "getLdStSORegOpValue";
635 // FIXME: Simplify the printer
636 let PrintMethod = "printAddrMode2Operand";
637 let DecoderMethod = "DecodeSORegMemOperand";
638 let ParserMatchClass = MemRegOffsetAsmOperand;
639 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
642 // postidx_imm8 := +/- [0,255]
645 // {8} 1 is imm8 is non-negative. 0 otherwise.
646 // {7-0} [0,255] imm8 value.
647 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
648 def postidx_imm8 : Operand<i32> {
649 let PrintMethod = "printPostIdxImm8Operand";
650 let ParserMatchClass = PostIdxImm8AsmOperand;
651 let MIOperandInfo = (ops i32imm);
654 // postidx_imm8s4 := +/- [0,1020]
657 // {8} 1 is imm8 is non-negative. 0 otherwise.
658 // {7-0} [0,255] imm8 value, scaled by 4.
659 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
660 def postidx_imm8s4 : Operand<i32> {
661 let PrintMethod = "printPostIdxImm8s4Operand";
662 let ParserMatchClass = PostIdxImm8s4AsmOperand;
663 let MIOperandInfo = (ops i32imm);
667 // postidx_reg := +/- reg
669 def PostIdxRegAsmOperand : AsmOperandClass {
670 let Name = "PostIdxReg";
671 let ParserMethod = "parsePostIdxReg";
673 def postidx_reg : Operand<i32> {
674 let EncoderMethod = "getPostIdxRegOpValue";
675 let DecoderMethod = "DecodePostIdxReg";
676 let PrintMethod = "printPostIdxRegOperand";
677 let ParserMatchClass = PostIdxRegAsmOperand;
678 let MIOperandInfo = (ops GPR, i32imm);
682 // addrmode2 := reg +/- imm12
683 // := reg +/- reg shop imm
685 // FIXME: addrmode2 should be refactored the rest of the way to always
686 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
687 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
688 def addrmode2 : Operand<i32>,
689 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
690 let EncoderMethod = "getAddrMode2OpValue";
691 let PrintMethod = "printAddrMode2Operand";
692 let ParserMatchClass = AddrMode2AsmOperand;
693 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
696 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
697 let Name = "PostIdxRegShifted";
698 let ParserMethod = "parsePostIdxReg";
700 def am2offset_reg : Operand<i32>,
701 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
702 [], [SDNPWantRoot]> {
703 let EncoderMethod = "getAddrMode2OffsetOpValue";
704 let PrintMethod = "printAddrMode2OffsetOperand";
705 // When using this for assembly, it's always as a post-index offset.
706 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
707 let MIOperandInfo = (ops GPR, i32imm);
710 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
711 // the GPR is purely vestigal at this point.
712 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
713 def am2offset_imm : Operand<i32>,
714 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
715 [], [SDNPWantRoot]> {
716 let EncoderMethod = "getAddrMode2OffsetOpValue";
717 let PrintMethod = "printAddrMode2OffsetOperand";
718 let ParserMatchClass = AM2OffsetImmAsmOperand;
719 let MIOperandInfo = (ops GPR, i32imm);
723 // addrmode3 := reg +/- reg
724 // addrmode3 := reg +/- imm8
726 // FIXME: split into imm vs. reg versions.
727 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
728 def addrmode3 : Operand<i32>,
729 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
730 let EncoderMethod = "getAddrMode3OpValue";
731 let PrintMethod = "printAddrMode3Operand";
732 let ParserMatchClass = AddrMode3AsmOperand;
733 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
736 // FIXME: split into imm vs. reg versions.
737 // FIXME: parser method to handle +/- register.
738 def AM3OffsetAsmOperand : AsmOperandClass {
739 let Name = "AM3Offset";
740 let ParserMethod = "parseAM3Offset";
742 def am3offset : Operand<i32>,
743 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
744 [], [SDNPWantRoot]> {
745 let EncoderMethod = "getAddrMode3OffsetOpValue";
746 let PrintMethod = "printAddrMode3OffsetOperand";
747 let ParserMatchClass = AM3OffsetAsmOperand;
748 let MIOperandInfo = (ops GPR, i32imm);
751 // ldstm_mode := {ia, ib, da, db}
753 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
754 let EncoderMethod = "getLdStmModeOpValue";
755 let PrintMethod = "printLdStmModeOperand";
758 // addrmode5 := reg +/- imm8*4
760 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
761 def addrmode5 : Operand<i32>,
762 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
763 let PrintMethod = "printAddrMode5Operand";
764 let EncoderMethod = "getAddrMode5OpValue";
765 let DecoderMethod = "DecodeAddrMode5Operand";
766 let ParserMatchClass = AddrMode5AsmOperand;
767 let MIOperandInfo = (ops GPR:$base, i32imm);
770 // addrmode6 := reg with optional alignment
772 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
773 def addrmode6 : Operand<i32>,
774 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
775 let PrintMethod = "printAddrMode6Operand";
776 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
777 let EncoderMethod = "getAddrMode6AddressOpValue";
778 let DecoderMethod = "DecodeAddrMode6Operand";
779 let ParserMatchClass = AddrMode6AsmOperand;
782 def am6offset : Operand<i32>,
783 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
784 [], [SDNPWantRoot]> {
785 let PrintMethod = "printAddrMode6OffsetOperand";
786 let MIOperandInfo = (ops GPR);
787 let EncoderMethod = "getAddrMode6OffsetOpValue";
788 let DecoderMethod = "DecodeGPRRegisterClass";
791 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
792 // (single element from one lane) for size 32.
793 def addrmode6oneL32 : Operand<i32>,
794 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
795 let PrintMethod = "printAddrMode6Operand";
796 let MIOperandInfo = (ops GPR:$addr, i32imm);
797 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
800 // Special version of addrmode6 to handle alignment encoding for VLD-dup
801 // instructions, specifically VLD4-dup.
802 def addrmode6dup : Operand<i32>,
803 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
804 let PrintMethod = "printAddrMode6Operand";
805 let MIOperandInfo = (ops GPR:$addr, i32imm);
806 let EncoderMethod = "getAddrMode6DupAddressOpValue";
809 // addrmodepc := pc + reg
811 def addrmodepc : Operand<i32>,
812 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
813 let PrintMethod = "printAddrModePCOperand";
814 let MIOperandInfo = (ops GPR, i32imm);
817 // addr_offset_none := reg
819 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
820 def addr_offset_none : Operand<i32>,
821 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
822 let PrintMethod = "printAddrMode7Operand";
823 let DecoderMethod = "DecodeAddrMode7Operand";
824 let ParserMatchClass = MemNoOffsetAsmOperand;
825 let MIOperandInfo = (ops GPR:$base);
828 def nohash_imm : Operand<i32> {
829 let PrintMethod = "printNoHashImmediate";
832 def CoprocNumAsmOperand : AsmOperandClass {
833 let Name = "CoprocNum";
834 let ParserMethod = "parseCoprocNumOperand";
836 def p_imm : Operand<i32> {
837 let PrintMethod = "printPImmediate";
838 let ParserMatchClass = CoprocNumAsmOperand;
839 let DecoderMethod = "DecodeCoprocessor";
842 def CoprocRegAsmOperand : AsmOperandClass {
843 let Name = "CoprocReg";
844 let ParserMethod = "parseCoprocRegOperand";
846 def c_imm : Operand<i32> {
847 let PrintMethod = "printCImmediate";
848 let ParserMatchClass = CoprocRegAsmOperand;
850 def CoprocOptionAsmOperand : AsmOperandClass {
851 let Name = "CoprocOption";
852 let ParserMethod = "parseCoprocOptionOperand";
854 def coproc_option_imm : Operand<i32> {
855 let PrintMethod = "printCoprocOptionImm";
856 let ParserMatchClass = CoprocOptionAsmOperand;
859 //===----------------------------------------------------------------------===//
861 include "ARMInstrFormats.td"
863 //===----------------------------------------------------------------------===//
864 // Multiclass helpers...
867 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
868 /// binop that produces a value.
869 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
870 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
871 PatFrag opnode, string baseOpc, bit Commutable = 0> {
872 // The register-immediate version is re-materializable. This is useful
873 // in particular for taking the address of a local.
874 let isReMaterializable = 1 in {
875 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
876 iii, opc, "\t$Rd, $Rn, $imm",
877 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
882 let Inst{19-16} = Rn;
883 let Inst{15-12} = Rd;
884 let Inst{11-0} = imm;
887 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
888 iir, opc, "\t$Rd, $Rn, $Rm",
889 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
894 let isCommutable = Commutable;
895 let Inst{19-16} = Rn;
896 let Inst{15-12} = Rd;
897 let Inst{11-4} = 0b00000000;
901 def rsi : AsI1<opcod, (outs GPR:$Rd),
902 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
903 iis, opc, "\t$Rd, $Rn, $shift",
904 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
909 let Inst{19-16} = Rn;
910 let Inst{15-12} = Rd;
911 let Inst{11-5} = shift{11-5};
913 let Inst{3-0} = shift{3-0};
916 def rsr : AsI1<opcod, (outs GPR:$Rd),
917 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
918 iis, opc, "\t$Rd, $Rn, $shift",
919 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
924 let Inst{19-16} = Rn;
925 let Inst{15-12} = Rd;
926 let Inst{11-8} = shift{11-8};
928 let Inst{6-5} = shift{6-5};
930 let Inst{3-0} = shift{3-0};
933 // Assembly aliases for optional destination operand when it's the same
934 // as the source operand.
935 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
936 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
937 so_imm:$imm, pred:$p,
940 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
941 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
945 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
946 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
947 so_reg_imm:$shift, pred:$p,
950 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
951 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
952 so_reg_reg:$shift, pred:$p,
958 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
959 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
960 /// it is equivalent to the AsI1_bin_irs counterpart.
961 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
962 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
963 PatFrag opnode, string baseOpc, bit Commutable = 0> {
964 // The register-immediate version is re-materializable. This is useful
965 // in particular for taking the address of a local.
966 let isReMaterializable = 1 in {
967 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
968 iii, opc, "\t$Rd, $Rn, $imm",
969 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]> {
974 let Inst{19-16} = Rn;
975 let Inst{15-12} = Rd;
976 let Inst{11-0} = imm;
979 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
980 iir, opc, "\t$Rd, $Rn, $Rm",
981 [/* pattern left blank */]> {
985 let Inst{11-4} = 0b00000000;
988 let Inst{15-12} = Rd;
989 let Inst{19-16} = Rn;
992 def rsi : AsI1<opcod, (outs GPR:$Rd),
993 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
994 iis, opc, "\t$Rd, $Rn, $shift",
995 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]> {
1000 let Inst{19-16} = Rn;
1001 let Inst{15-12} = Rd;
1002 let Inst{11-5} = shift{11-5};
1004 let Inst{3-0} = shift{3-0};
1007 def rsr : AsI1<opcod, (outs GPR:$Rd),
1008 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1009 iis, opc, "\t$Rd, $Rn, $shift",
1010 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]> {
1015 let Inst{19-16} = Rn;
1016 let Inst{15-12} = Rd;
1017 let Inst{11-8} = shift{11-8};
1019 let Inst{6-5} = shift{6-5};
1021 let Inst{3-0} = shift{3-0};
1024 // Assembly aliases for optional destination operand when it's the same
1025 // as the source operand.
1026 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1027 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1028 so_imm:$imm, pred:$p,
1031 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1032 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1036 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1037 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1038 so_reg_imm:$shift, pred:$p,
1041 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1042 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1043 so_reg_reg:$shift, pred:$p,
1049 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1051 /// These opcodes will be converted to the real non-S opcodes by
1052 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1053 let hasPostISelHook = 1, Defs = [CPSR] in {
1054 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1055 InstrItinClass iis, PatFrag opnode,
1056 bit Commutable = 0> {
1057 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1059 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>;
1061 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1063 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> {
1064 let isCommutable = Commutable;
1066 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1067 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1069 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1070 so_reg_imm:$shift))]>;
1072 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1073 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1075 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1076 so_reg_reg:$shift))]>;
1080 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1081 /// operands are reversed.
1082 let hasPostISelHook = 1, Defs = [CPSR] in {
1083 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1084 InstrItinClass iis, PatFrag opnode,
1085 bit Commutable = 0> {
1086 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1088 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>;
1090 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1091 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1093 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1096 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1097 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1099 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1104 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1105 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1106 /// a explicit result, only implicitly set CPSR.
1107 let isCompare = 1, Defs = [CPSR] in {
1108 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1109 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1110 PatFrag opnode, bit Commutable = 0> {
1111 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1113 [(opnode GPR:$Rn, so_imm:$imm)]> {
1118 let Inst{19-16} = Rn;
1119 let Inst{15-12} = 0b0000;
1120 let Inst{11-0} = imm;
1122 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1124 [(opnode GPR:$Rn, GPR:$Rm)]> {
1127 let isCommutable = Commutable;
1130 let Inst{19-16} = Rn;
1131 let Inst{15-12} = 0b0000;
1132 let Inst{11-4} = 0b00000000;
1135 def rsi : AI1<opcod, (outs),
1136 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1137 opc, "\t$Rn, $shift",
1138 [(opnode GPR:$Rn, so_reg_imm:$shift)]> {
1143 let Inst{19-16} = Rn;
1144 let Inst{15-12} = 0b0000;
1145 let Inst{11-5} = shift{11-5};
1147 let Inst{3-0} = shift{3-0};
1149 def rsr : AI1<opcod, (outs),
1150 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1151 opc, "\t$Rn, $shift",
1152 [(opnode GPR:$Rn, so_reg_reg:$shift)]> {
1157 let Inst{19-16} = Rn;
1158 let Inst{15-12} = 0b0000;
1159 let Inst{11-8} = shift{11-8};
1161 let Inst{6-5} = shift{6-5};
1163 let Inst{3-0} = shift{3-0};
1169 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1170 /// register and one whose operand is a register rotated by 8/16/24.
1171 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1172 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1173 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1174 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1175 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1176 Requires<[IsARM, HasV6]> {
1180 let Inst{19-16} = 0b1111;
1181 let Inst{15-12} = Rd;
1182 let Inst{11-10} = rot;
1186 class AI_ext_rrot_np<bits<8> opcod, string opc>
1187 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1188 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1189 Requires<[IsARM, HasV6]> {
1191 let Inst{19-16} = 0b1111;
1192 let Inst{11-10} = rot;
1195 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1196 /// register and one whose operand is a register rotated by 8/16/24.
1197 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1198 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1199 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1200 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1201 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1202 Requires<[IsARM, HasV6]> {
1207 let Inst{19-16} = Rn;
1208 let Inst{15-12} = Rd;
1209 let Inst{11-10} = rot;
1210 let Inst{9-4} = 0b000111;
1214 class AI_exta_rrot_np<bits<8> opcod, string opc>
1215 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1216 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1217 Requires<[IsARM, HasV6]> {
1220 let Inst{19-16} = Rn;
1221 let Inst{11-10} = rot;
1224 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1225 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1226 string baseOpc, bit Commutable = 0> {
1227 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1228 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1229 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1230 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1236 let Inst{15-12} = Rd;
1237 let Inst{19-16} = Rn;
1238 let Inst{11-0} = imm;
1240 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1241 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1242 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1247 let Inst{11-4} = 0b00000000;
1249 let isCommutable = Commutable;
1251 let Inst{15-12} = Rd;
1252 let Inst{19-16} = Rn;
1254 def rsi : AsI1<opcod, (outs GPR:$Rd),
1255 (ins GPR:$Rn, so_reg_imm:$shift),
1256 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1257 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1263 let Inst{19-16} = Rn;
1264 let Inst{15-12} = Rd;
1265 let Inst{11-5} = shift{11-5};
1267 let Inst{3-0} = shift{3-0};
1269 def rsr : AsI1<opcod, (outs GPR:$Rd),
1270 (ins GPR:$Rn, so_reg_reg:$shift),
1271 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1272 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_reg:$shift, CPSR))]>,
1278 let Inst{19-16} = Rn;
1279 let Inst{15-12} = Rd;
1280 let Inst{11-8} = shift{11-8};
1282 let Inst{6-5} = shift{6-5};
1284 let Inst{3-0} = shift{3-0};
1288 // Assembly aliases for optional destination operand when it's the same
1289 // as the source operand.
1290 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1291 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1292 so_imm:$imm, pred:$p,
1295 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1296 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1300 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1301 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1302 so_reg_imm:$shift, pred:$p,
1305 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1306 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1307 so_reg_reg:$shift, pred:$p,
1312 /// AI1_rsc_irs - Define instructions and patterns for rsc
1313 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode,
1315 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1316 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1317 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1318 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1324 let Inst{15-12} = Rd;
1325 let Inst{19-16} = Rn;
1326 let Inst{11-0} = imm;
1328 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1329 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1330 [/* pattern left blank */]> {
1334 let Inst{11-4} = 0b00000000;
1337 let Inst{15-12} = Rd;
1338 let Inst{19-16} = Rn;
1340 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1341 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1342 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1348 let Inst{19-16} = Rn;
1349 let Inst{15-12} = Rd;
1350 let Inst{11-5} = shift{11-5};
1352 let Inst{3-0} = shift{3-0};
1354 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1355 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1356 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1362 let Inst{19-16} = Rn;
1363 let Inst{15-12} = Rd;
1364 let Inst{11-8} = shift{11-8};
1366 let Inst{6-5} = shift{6-5};
1368 let Inst{3-0} = shift{3-0};
1372 // Assembly aliases for optional destination operand when it's the same
1373 // as the source operand.
1374 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1375 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1376 so_imm:$imm, pred:$p,
1379 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1380 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1384 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1385 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1386 so_reg_imm:$shift, pred:$p,
1389 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1390 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1391 so_reg_reg:$shift, pred:$p,
1396 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1397 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1398 InstrItinClass iir, PatFrag opnode> {
1399 // Note: We use the complex addrmode_imm12 rather than just an input
1400 // GPR and a constrained immediate so that we can use this to match
1401 // frame index references and avoid matching constant pool references.
1402 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1403 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1404 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1407 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1408 let Inst{19-16} = addr{16-13}; // Rn
1409 let Inst{15-12} = Rt;
1410 let Inst{11-0} = addr{11-0}; // imm12
1412 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1413 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1414 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1417 let shift{4} = 0; // Inst{4} = 0
1418 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1419 let Inst{19-16} = shift{16-13}; // Rn
1420 let Inst{15-12} = Rt;
1421 let Inst{11-0} = shift{11-0};
1426 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1427 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1428 InstrItinClass iir, PatFrag opnode> {
1429 // Note: We use the complex addrmode_imm12 rather than just an input
1430 // GPR and a constrained immediate so that we can use this to match
1431 // frame index references and avoid matching constant pool references.
1432 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), (ins addrmode_imm12:$addr),
1433 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1434 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1437 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1438 let Inst{19-16} = addr{16-13}; // Rn
1439 let Inst{15-12} = Rt;
1440 let Inst{11-0} = addr{11-0}; // imm12
1442 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), (ins ldst_so_reg:$shift),
1443 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1444 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1447 let shift{4} = 0; // Inst{4} = 0
1448 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1449 let Inst{19-16} = shift{16-13}; // Rn
1450 let Inst{15-12} = Rt;
1451 let Inst{11-0} = shift{11-0};
1457 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1458 InstrItinClass iir, PatFrag opnode> {
1459 // Note: We use the complex addrmode_imm12 rather than just an input
1460 // GPR and a constrained immediate so that we can use this to match
1461 // frame index references and avoid matching constant pool references.
1462 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1463 (ins GPR:$Rt, addrmode_imm12:$addr),
1464 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1465 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1468 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1469 let Inst{19-16} = addr{16-13}; // Rn
1470 let Inst{15-12} = Rt;
1471 let Inst{11-0} = addr{11-0}; // imm12
1473 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1474 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1475 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1478 let shift{4} = 0; // Inst{4} = 0
1479 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1480 let Inst{19-16} = shift{16-13}; // Rn
1481 let Inst{15-12} = Rt;
1482 let Inst{11-0} = shift{11-0};
1486 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1487 InstrItinClass iir, PatFrag opnode> {
1488 // Note: We use the complex addrmode_imm12 rather than just an input
1489 // GPR and a constrained immediate so that we can use this to match
1490 // frame index references and avoid matching constant pool references.
1491 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1492 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1493 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1494 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1497 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1498 let Inst{19-16} = addr{16-13}; // Rn
1499 let Inst{15-12} = Rt;
1500 let Inst{11-0} = addr{11-0}; // imm12
1502 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1503 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1504 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1507 let shift{4} = 0; // Inst{4} = 0
1508 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1509 let Inst{19-16} = shift{16-13}; // Rn
1510 let Inst{15-12} = Rt;
1511 let Inst{11-0} = shift{11-0};
1516 //===----------------------------------------------------------------------===//
1518 //===----------------------------------------------------------------------===//
1520 //===----------------------------------------------------------------------===//
1521 // Miscellaneous Instructions.
1524 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1525 /// the function. The first operand is the ID# for this instruction, the second
1526 /// is the index into the MachineConstantPool that this is, the third is the
1527 /// size in bytes of this constant pool entry.
1528 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1529 def CONSTPOOL_ENTRY :
1530 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1531 i32imm:$size), NoItinerary, []>;
1533 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1534 // from removing one half of the matched pairs. That breaks PEI, which assumes
1535 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1536 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1537 def ADJCALLSTACKUP :
1538 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1539 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1541 def ADJCALLSTACKDOWN :
1542 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1543 [(ARMcallseq_start timm:$amt)]>;
1546 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1547 // (These psuedos use a hand-written selection code).
1548 let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
1549 def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1550 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1552 def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1553 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1555 def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1556 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1558 def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1559 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1561 def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1562 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1564 def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1565 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1567 def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1568 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1570 def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1571 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
1572 GPR:$set1, GPR:$set2),
1576 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "", []>,
1577 Requires<[IsARM, HasV6T2]> {
1578 let Inst{27-16} = 0b001100100000;
1579 let Inst{15-8} = 0b11110000;
1580 let Inst{7-0} = 0b00000000;
1583 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "", []>,
1584 Requires<[IsARM, HasV6T2]> {
1585 let Inst{27-16} = 0b001100100000;
1586 let Inst{15-8} = 0b11110000;
1587 let Inst{7-0} = 0b00000001;
1590 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "", []>,
1591 Requires<[IsARM, HasV6T2]> {
1592 let Inst{27-16} = 0b001100100000;
1593 let Inst{15-8} = 0b11110000;
1594 let Inst{7-0} = 0b00000010;
1597 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "", []>,
1598 Requires<[IsARM, HasV6T2]> {
1599 let Inst{27-16} = 0b001100100000;
1600 let Inst{15-8} = 0b11110000;
1601 let Inst{7-0} = 0b00000011;
1604 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1605 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1610 let Inst{15-12} = Rd;
1611 let Inst{19-16} = Rn;
1612 let Inst{27-20} = 0b01101000;
1613 let Inst{7-4} = 0b1011;
1614 let Inst{11-8} = 0b1111;
1617 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1618 []>, Requires<[IsARM, HasV6T2]> {
1619 let Inst{27-16} = 0b001100100000;
1620 let Inst{15-8} = 0b11110000;
1621 let Inst{7-0} = 0b00000100;
1624 // The i32imm operand $val can be used by a debugger to store more information
1625 // about the breakpoint.
1626 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1627 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1629 let Inst{3-0} = val{3-0};
1630 let Inst{19-8} = val{15-4};
1631 let Inst{27-20} = 0b00010010;
1632 let Inst{7-4} = 0b0111;
1635 // Change Processor State
1636 // FIXME: We should use InstAlias to handle the optional operands.
1637 class CPS<dag iops, string asm_ops>
1638 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1639 []>, Requires<[IsARM]> {
1645 let Inst{31-28} = 0b1111;
1646 let Inst{27-20} = 0b00010000;
1647 let Inst{19-18} = imod;
1648 let Inst{17} = M; // Enabled if mode is set;
1649 let Inst{16-9} = 0b00000000;
1650 let Inst{8-6} = iflags;
1652 let Inst{4-0} = mode;
1655 let DecoderMethod = "DecodeCPSInstruction" in {
1657 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1658 "$imod\t$iflags, $mode">;
1659 let mode = 0, M = 0 in
1660 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1662 let imod = 0, iflags = 0, M = 1 in
1663 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1666 // Preload signals the memory system of possible future data/instruction access.
1667 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1669 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1670 !strconcat(opc, "\t$addr"),
1671 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1674 let Inst{31-26} = 0b111101;
1675 let Inst{25} = 0; // 0 for immediate form
1676 let Inst{24} = data;
1677 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1678 let Inst{22} = read;
1679 let Inst{21-20} = 0b01;
1680 let Inst{19-16} = addr{16-13}; // Rn
1681 let Inst{15-12} = 0b1111;
1682 let Inst{11-0} = addr{11-0}; // imm12
1685 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1686 !strconcat(opc, "\t$shift"),
1687 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1689 let Inst{31-26} = 0b111101;
1690 let Inst{25} = 1; // 1 for register form
1691 let Inst{24} = data;
1692 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1693 let Inst{22} = read;
1694 let Inst{21-20} = 0b01;
1695 let Inst{19-16} = shift{16-13}; // Rn
1696 let Inst{15-12} = 0b1111;
1697 let Inst{11-0} = shift{11-0};
1702 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1703 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1704 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1706 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1707 "setend\t$end", []>, Requires<[IsARM]> {
1709 let Inst{31-10} = 0b1111000100000001000000;
1714 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1715 []>, Requires<[IsARM, HasV7]> {
1717 let Inst{27-4} = 0b001100100000111100001111;
1718 let Inst{3-0} = opt;
1721 // A5.4 Permanently UNDEFINED instructions.
1722 let isBarrier = 1, isTerminator = 1 in
1723 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1726 let Inst = 0xe7ffdefe;
1729 // Address computation and loads and stores in PIC mode.
1730 let isNotDuplicable = 1 in {
1731 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1733 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1735 let AddedComplexity = 10 in {
1736 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1738 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1740 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1742 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1744 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1746 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1748 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1750 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1752 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1754 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1756 let AddedComplexity = 10 in {
1757 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1758 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1760 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1761 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1762 addrmodepc:$addr)]>;
1764 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1765 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1767 } // isNotDuplicable = 1
1770 // LEApcrel - Load a pc-relative address into a register without offending the
1772 let neverHasSideEffects = 1, isReMaterializable = 1 in
1773 // The 'adr' mnemonic encodes differently if the label is before or after
1774 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1775 // know until then which form of the instruction will be used.
1776 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1777 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []> {
1780 let Inst{27-25} = 0b001;
1782 let Inst{23-22} = label{13-12};
1785 let Inst{19-16} = 0b1111;
1786 let Inst{15-12} = Rd;
1787 let Inst{11-0} = label{11-0};
1789 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1792 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1793 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1796 //===----------------------------------------------------------------------===//
1797 // Control Flow Instructions.
1800 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1802 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1803 "bx", "\tlr", [(ARMretflag)]>,
1804 Requires<[IsARM, HasV4T]> {
1805 let Inst{27-0} = 0b0001001011111111111100011110;
1809 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1810 "mov", "\tpc, lr", [(ARMretflag)]>,
1811 Requires<[IsARM, NoV4T]> {
1812 let Inst{27-0} = 0b0001101000001111000000001110;
1816 // Indirect branches
1817 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1819 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1820 [(brind GPR:$dst)]>,
1821 Requires<[IsARM, HasV4T]> {
1823 let Inst{31-4} = 0b1110000100101111111111110001;
1824 let Inst{3-0} = dst;
1827 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1828 "bx", "\t$dst", [/* pattern left blank */]>,
1829 Requires<[IsARM, HasV4T]> {
1831 let Inst{27-4} = 0b000100101111111111110001;
1832 let Inst{3-0} = dst;
1836 // All calls clobber the non-callee saved registers. SP is marked as
1837 // a use to prevent stack-pointer assignments that appear immediately
1838 // before calls from potentially appearing dead.
1840 // On non-Darwin platforms R9 is callee-saved.
1841 // FIXME: Do we really need a non-predicated version? If so, it should
1842 // at least be a pseudo instruction expanding to the predicated version
1843 // at MC lowering time.
1844 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1846 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1847 IIC_Br, "bl\t$func",
1848 [(ARMcall tglobaladdr:$func)]>,
1849 Requires<[IsARM, IsNotDarwin]> {
1850 let Inst{31-28} = 0b1110;
1852 let Inst{23-0} = func;
1853 let DecoderMethod = "DecodeBranchImmInstruction";
1856 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1857 IIC_Br, "bl", "\t$func",
1858 [(ARMcall_pred tglobaladdr:$func)]>,
1859 Requires<[IsARM, IsNotDarwin]> {
1861 let Inst{23-0} = func;
1862 let DecoderMethod = "DecodeBranchImmInstruction";
1866 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1867 IIC_Br, "blx\t$func",
1868 [(ARMcall GPR:$func)]>,
1869 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1871 let Inst{31-4} = 0b1110000100101111111111110011;
1872 let Inst{3-0} = func;
1875 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1876 IIC_Br, "blx", "\t$func",
1877 [(ARMcall_pred GPR:$func)]>,
1878 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1880 let Inst{27-4} = 0b000100101111111111110011;
1881 let Inst{3-0} = func;
1885 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1886 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1887 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1888 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1891 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1892 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1893 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1897 // On Darwin R9 is call-clobbered.
1898 // R7 is marked as a use to prevent frame-pointer assignments from being
1899 // moved above / below calls.
1900 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1901 Uses = [R7, SP] in {
1902 def BLr9 : ARMPseudoExpand<(outs), (ins bl_target:$func, variable_ops),
1904 [(ARMcall tglobaladdr:$func)], (BL bl_target:$func)>,
1905 Requires<[IsARM, IsDarwin]>;
1907 def BLr9_pred : ARMPseudoExpand<(outs),
1908 (ins bl_target:$func, pred:$p, variable_ops),
1910 [(ARMcall_pred tglobaladdr:$func)],
1911 (BL_pred bl_target:$func, pred:$p)>,
1912 Requires<[IsARM, IsDarwin]>;
1915 def BLXr9 : ARMPseudoExpand<(outs), (ins GPR:$func, variable_ops),
1917 [(ARMcall GPR:$func)],
1919 Requires<[IsARM, HasV5T, IsDarwin]>;
1921 def BLXr9_pred: ARMPseudoExpand<(outs), (ins GPR:$func, pred:$p,variable_ops),
1923 [(ARMcall_pred GPR:$func)],
1924 (BLX_pred GPR:$func, pred:$p)>,
1925 Requires<[IsARM, HasV5T, IsDarwin]>;
1928 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1929 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1930 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1931 Requires<[IsARM, HasV4T, IsDarwin]>;
1934 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1935 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1936 Requires<[IsARM, NoV4T, IsDarwin]>;
1939 let isBranch = 1, isTerminator = 1 in {
1940 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1941 // a two-value operand where a dag node expects two operands. :(
1942 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1943 IIC_Br, "b", "\t$target",
1944 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1946 let Inst{23-0} = target;
1947 let DecoderMethod = "DecodeBranchImmInstruction";
1950 let isBarrier = 1 in {
1951 // B is "predicable" since it's just a Bcc with an 'always' condition.
1952 let isPredicable = 1 in
1953 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1954 // should be sufficient.
1955 // FIXME: Is B really a Barrier? That doesn't seem right.
1956 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
1957 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
1959 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1960 def BR_JTr : ARMPseudoInst<(outs),
1961 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1963 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1964 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1965 // into i12 and rs suffixed versions.
1966 def BR_JTm : ARMPseudoInst<(outs),
1967 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1969 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1971 def BR_JTadd : ARMPseudoInst<(outs),
1972 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1974 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1976 } // isNotDuplicable = 1, isIndirectBranch = 1
1982 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
1983 "blx\t$target", []>,
1984 Requires<[IsARM, HasV5T]> {
1985 let Inst{31-25} = 0b1111101;
1987 let Inst{23-0} = target{24-1};
1988 let Inst{24} = target{0};
1991 // Branch and Exchange Jazelle
1992 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1993 [/* pattern left blank */]> {
1995 let Inst{23-20} = 0b0010;
1996 let Inst{19-8} = 0xfff;
1997 let Inst{7-4} = 0b0010;
1998 let Inst{3-0} = func;
2003 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
2005 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
2007 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
2008 IIC_Br, []>, Requires<[IsDarwin]>;
2010 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
2011 IIC_Br, []>, Requires<[IsDarwin]>;
2013 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst, variable_ops),
2015 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2016 Requires<[IsARM, IsDarwin]>;
2018 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
2021 Requires<[IsARM, IsDarwin]>;
2025 // Non-Darwin versions (the difference is R9).
2026 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
2028 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
2029 IIC_Br, []>, Requires<[IsNotDarwin]>;
2031 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
2032 IIC_Br, []>, Requires<[IsNotDarwin]>;
2034 def TAILJMPdND : ARMPseudoExpand<(outs), (ins brtarget:$dst, variable_ops),
2036 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2037 Requires<[IsARM, IsNotDarwin]>;
2039 def TAILJMPrND : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
2042 Requires<[IsARM, IsNotDarwin]>;
2046 // Secure Monitor Call is a system instruction.
2047 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2050 let Inst{23-4} = 0b01100000000000000111;
2051 let Inst{3-0} = opt;
2054 // Supervisor Call (Software Interrupt)
2055 let isCall = 1, Uses = [SP] in {
2056 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
2058 let Inst{23-0} = svc;
2062 // Store Return State
2063 class SRSI<bit wb, string asm>
2064 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2065 NoItinerary, asm, "", []> {
2067 let Inst{31-28} = 0b1111;
2068 let Inst{27-25} = 0b100;
2072 let Inst{19-16} = 0b1101; // SP
2073 let Inst{15-5} = 0b00000101000;
2074 let Inst{4-0} = mode;
2077 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2078 let Inst{24-23} = 0;
2080 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2081 let Inst{24-23} = 0;
2083 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2084 let Inst{24-23} = 0b10;
2086 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2087 let Inst{24-23} = 0b10;
2089 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2090 let Inst{24-23} = 0b01;
2092 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2093 let Inst{24-23} = 0b01;
2095 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2096 let Inst{24-23} = 0b11;
2098 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2099 let Inst{24-23} = 0b11;
2102 // Return From Exception
2103 class RFEI<bit wb, string asm>
2104 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2105 NoItinerary, asm, "", []> {
2107 let Inst{31-28} = 0b1111;
2108 let Inst{27-25} = 0b100;
2112 let Inst{19-16} = Rn;
2113 let Inst{15-0} = 0xa00;
2116 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2117 let Inst{24-23} = 0;
2119 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2120 let Inst{24-23} = 0;
2122 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2123 let Inst{24-23} = 0b10;
2125 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2126 let Inst{24-23} = 0b10;
2128 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2129 let Inst{24-23} = 0b01;
2131 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2132 let Inst{24-23} = 0b01;
2134 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2135 let Inst{24-23} = 0b11;
2137 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2138 let Inst{24-23} = 0b11;
2141 //===----------------------------------------------------------------------===//
2142 // Load / Store Instructions.
2148 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2149 UnOpFrag<(load node:$Src)>>;
2150 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2151 UnOpFrag<(zextloadi8 node:$Src)>>;
2152 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2153 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2154 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2155 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2157 // Special LDR for loads from non-pc-relative constpools.
2158 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2159 isReMaterializable = 1, isCodeGenOnly = 1 in
2160 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2161 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2165 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2166 let Inst{19-16} = 0b1111;
2167 let Inst{15-12} = Rt;
2168 let Inst{11-0} = addr{11-0}; // imm12
2171 // Loads with zero extension
2172 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2173 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2174 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2176 // Loads with sign extension
2177 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2178 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2179 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2181 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2182 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2183 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2185 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2187 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2188 (ins addrmode3:$addr), LdMiscFrm,
2189 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2190 []>, Requires<[IsARM, HasV5TE]>;
2194 multiclass AI2_ldridx<bit isByte, string opc,
2195 InstrItinClass iii, InstrItinClass iir> {
2196 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2197 (ins addrmode_imm12:$addr), IndexModePre, LdFrm, iii,
2198 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2201 let Inst{23} = addr{12};
2202 let Inst{19-16} = addr{16-13};
2203 let Inst{11-0} = addr{11-0};
2204 let DecoderMethod = "DecodeLDRPreImm";
2205 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
2208 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2209 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2210 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2213 let Inst{23} = addr{12};
2214 let Inst{19-16} = addr{16-13};
2215 let Inst{11-0} = addr{11-0};
2217 let DecoderMethod = "DecodeLDRPreReg";
2218 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2221 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2222 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2223 IndexModePost, LdFrm, iir,
2224 opc, "\t$Rt, $addr, $offset",
2225 "$addr.base = $Rn_wb", []> {
2231 let Inst{23} = offset{12};
2232 let Inst{19-16} = addr;
2233 let Inst{11-0} = offset{11-0};
2235 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2238 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2239 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2240 IndexModePost, LdFrm, iii,
2241 opc, "\t$Rt, $addr, $offset",
2242 "$addr.base = $Rn_wb", []> {
2248 let Inst{23} = offset{12};
2249 let Inst{19-16} = addr;
2250 let Inst{11-0} = offset{11-0};
2252 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2257 let mayLoad = 1, neverHasSideEffects = 1 in {
2258 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2259 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2260 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2261 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2264 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2265 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2266 (ins addrmode3:$addr), IndexModePre,
2268 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2270 let Inst{23} = addr{8}; // U bit
2271 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2272 let Inst{19-16} = addr{12-9}; // Rn
2273 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2274 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2275 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
2276 let DecoderMethod = "DecodeAddrMode3Instruction";
2278 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2279 (ins addr_offset_none:$addr, am3offset:$offset),
2280 IndexModePost, LdMiscFrm, itin,
2281 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2285 let Inst{23} = offset{8}; // U bit
2286 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2287 let Inst{19-16} = addr;
2288 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2289 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2290 let DecoderMethod = "DecodeAddrMode3Instruction";
2294 let mayLoad = 1, neverHasSideEffects = 1 in {
2295 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2296 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2297 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2298 let hasExtraDefRegAllocReq = 1 in {
2299 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2300 (ins addrmode3:$addr), IndexModePre,
2301 LdMiscFrm, IIC_iLoad_d_ru,
2302 "ldrd", "\t$Rt, $Rt2, $addr!",
2303 "$addr.base = $Rn_wb", []> {
2305 let Inst{23} = addr{8}; // U bit
2306 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2307 let Inst{19-16} = addr{12-9}; // Rn
2308 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2309 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2310 let DecoderMethod = "DecodeAddrMode3Instruction";
2311 let AsmMatchConverter = "cvtLdrdPre";
2313 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2314 (ins addr_offset_none:$addr, am3offset:$offset),
2315 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2316 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2317 "$addr.base = $Rn_wb", []> {
2320 let Inst{23} = offset{8}; // U bit
2321 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2322 let Inst{19-16} = addr;
2323 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2324 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2325 let DecoderMethod = "DecodeAddrMode3Instruction";
2327 } // hasExtraDefRegAllocReq = 1
2328 } // mayLoad = 1, neverHasSideEffects = 1
2330 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2331 let mayLoad = 1, neverHasSideEffects = 1 in {
2332 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2333 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2334 IndexModePost, LdFrm, IIC_iLoad_ru,
2335 "ldrt", "\t$Rt, $addr, $offset",
2336 "$addr.base = $Rn_wb", []> {
2342 let Inst{23} = offset{12};
2343 let Inst{21} = 1; // overwrite
2344 let Inst{19-16} = addr;
2345 let Inst{11-5} = offset{11-5};
2347 let Inst{3-0} = offset{3-0};
2348 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2351 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2352 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2353 IndexModePost, LdFrm, IIC_iLoad_ru,
2354 "ldrt", "\t$Rt, $addr, $offset",
2355 "$addr.base = $Rn_wb", []> {
2361 let Inst{23} = offset{12};
2362 let Inst{21} = 1; // overwrite
2363 let Inst{19-16} = addr;
2364 let Inst{11-0} = offset{11-0};
2365 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2368 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2369 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2370 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2371 "ldrbt", "\t$Rt, $addr, $offset",
2372 "$addr.base = $Rn_wb", []> {
2378 let Inst{23} = offset{12};
2379 let Inst{21} = 1; // overwrite
2380 let Inst{19-16} = addr;
2381 let Inst{11-5} = offset{11-5};
2383 let Inst{3-0} = offset{3-0};
2384 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2387 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2388 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2389 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2390 "ldrbt", "\t$Rt, $addr, $offset",
2391 "$addr.base = $Rn_wb", []> {
2397 let Inst{23} = offset{12};
2398 let Inst{21} = 1; // overwrite
2399 let Inst{19-16} = addr;
2400 let Inst{11-0} = offset{11-0};
2401 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2404 multiclass AI3ldrT<bits<4> op, string opc> {
2405 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2406 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2407 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2408 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2410 let Inst{23} = offset{8};
2412 let Inst{11-8} = offset{7-4};
2413 let Inst{3-0} = offset{3-0};
2414 let AsmMatchConverter = "cvtLdExtTWriteBackImm";
2416 def r : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2417 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2418 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2419 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2421 let Inst{23} = Rm{4};
2424 let Inst{3-0} = Rm{3-0};
2425 let AsmMatchConverter = "cvtLdExtTWriteBackReg";
2429 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2430 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2431 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2436 // Stores with truncate
2437 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2438 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2439 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2442 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2443 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2444 StMiscFrm, IIC_iStore_d_r,
2445 "strd", "\t$Rt, $src2, $addr", []>,
2446 Requires<[IsARM, HasV5TE]> {
2451 multiclass AI2_stridx<bit isByte, string opc,
2452 InstrItinClass iii, InstrItinClass iir> {
2453 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2454 (ins GPR:$Rt, addrmode_imm12:$addr), IndexModePre,
2456 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2459 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2460 let Inst{19-16} = addr{16-13}; // Rn
2461 let Inst{11-0} = addr{11-0}; // imm12
2462 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
2463 let DecoderMethod = "DecodeSTRPreImm";
2466 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2467 (ins GPR:$Rt, ldst_so_reg:$addr),
2468 IndexModePre, StFrm, iir,
2469 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2472 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2473 let Inst{19-16} = addr{16-13}; // Rn
2474 let Inst{11-0} = addr{11-0};
2475 let Inst{4} = 0; // Inst{4} = 0
2476 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2477 let DecoderMethod = "DecodeSTRPreReg";
2479 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2480 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2481 IndexModePost, StFrm, iir,
2482 opc, "\t$Rt, $addr, $offset",
2483 "$addr.base = $Rn_wb", []> {
2489 let Inst{23} = offset{12};
2490 let Inst{19-16} = addr;
2491 let Inst{11-0} = offset{11-0};
2493 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2496 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2497 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2498 IndexModePost, StFrm, iii,
2499 opc, "\t$Rt, $addr, $offset",
2500 "$addr.base = $Rn_wb", []> {
2506 let Inst{23} = offset{12};
2507 let Inst{19-16} = addr;
2508 let Inst{11-0} = offset{11-0};
2510 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2514 let mayStore = 1, neverHasSideEffects = 1 in {
2515 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2516 // IIC_iStore_siu depending on whether it the offset register is shifted.
2517 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2518 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2521 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2522 am2offset_reg:$offset),
2523 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2524 am2offset_reg:$offset)>;
2525 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2526 am2offset_imm:$offset),
2527 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2528 am2offset_imm:$offset)>;
2529 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2530 am2offset_reg:$offset),
2531 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2532 am2offset_reg:$offset)>;
2533 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2534 am2offset_imm:$offset),
2535 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2536 am2offset_imm:$offset)>;
2538 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2539 // put the patterns on the instruction definitions directly as ISel wants
2540 // the address base and offset to be separate operands, not a single
2541 // complex operand like we represent the instructions themselves. The
2542 // pseudos map between the two.
2543 let usesCustomInserter = 1,
2544 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2545 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2546 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2549 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2550 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2551 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2554 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2555 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2556 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2559 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2560 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2561 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2564 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2565 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2566 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2569 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2574 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2575 (ins GPR:$Rt, addrmode3:$addr), IndexModePre,
2576 StMiscFrm, IIC_iStore_bh_ru,
2577 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2579 let Inst{23} = addr{8}; // U bit
2580 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2581 let Inst{19-16} = addr{12-9}; // Rn
2582 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2583 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2584 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
2585 let DecoderMethod = "DecodeAddrMode3Instruction";
2588 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2589 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2590 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2591 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2592 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2593 addr_offset_none:$addr,
2594 am3offset:$offset))]> {
2597 let Inst{23} = offset{8}; // U bit
2598 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2599 let Inst{19-16} = addr;
2600 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2601 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2602 let DecoderMethod = "DecodeAddrMode3Instruction";
2605 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2606 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2607 (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2608 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2609 "strd", "\t$Rt, $Rt2, $addr!",
2610 "$addr.base = $Rn_wb", []> {
2612 let Inst{23} = addr{8}; // U bit
2613 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2614 let Inst{19-16} = addr{12-9}; // Rn
2615 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2616 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2617 let DecoderMethod = "DecodeAddrMode3Instruction";
2618 let AsmMatchConverter = "cvtStrdPre";
2621 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2622 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2624 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2625 "strd", "\t$Rt, $Rt2, $addr, $offset",
2626 "$addr.base = $Rn_wb", []> {
2629 let Inst{23} = offset{8}; // U bit
2630 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2631 let Inst{19-16} = addr;
2632 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2633 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2634 let DecoderMethod = "DecodeAddrMode3Instruction";
2636 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2638 // STRT, STRBT, and STRHT
2640 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2641 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2642 IndexModePost, StFrm, IIC_iStore_bh_ru,
2643 "strbt", "\t$Rt, $addr, $offset",
2644 "$addr.base = $Rn_wb", []> {
2650 let Inst{23} = offset{12};
2651 let Inst{21} = 1; // overwrite
2652 let Inst{19-16} = addr;
2653 let Inst{11-5} = offset{11-5};
2655 let Inst{3-0} = offset{3-0};
2656 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2659 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2660 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2661 IndexModePost, StFrm, IIC_iStore_bh_ru,
2662 "strbt", "\t$Rt, $addr, $offset",
2663 "$addr.base = $Rn_wb", []> {
2669 let Inst{23} = offset{12};
2670 let Inst{21} = 1; // overwrite
2671 let Inst{19-16} = addr;
2672 let Inst{11-0} = offset{11-0};
2673 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2676 let mayStore = 1, neverHasSideEffects = 1 in {
2677 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2678 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2679 IndexModePost, StFrm, IIC_iStore_ru,
2680 "strt", "\t$Rt, $addr, $offset",
2681 "$addr.base = $Rn_wb", []> {
2687 let Inst{23} = offset{12};
2688 let Inst{21} = 1; // overwrite
2689 let Inst{19-16} = addr;
2690 let Inst{11-5} = offset{11-5};
2692 let Inst{3-0} = offset{3-0};
2693 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2696 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2697 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2698 IndexModePost, StFrm, IIC_iStore_ru,
2699 "strt", "\t$Rt, $addr, $offset",
2700 "$addr.base = $Rn_wb", []> {
2706 let Inst{23} = offset{12};
2707 let Inst{21} = 1; // overwrite
2708 let Inst{19-16} = addr;
2709 let Inst{11-0} = offset{11-0};
2710 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2715 multiclass AI3strT<bits<4> op, string opc> {
2716 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2717 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2718 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2719 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2721 let Inst{23} = offset{8};
2723 let Inst{11-8} = offset{7-4};
2724 let Inst{3-0} = offset{3-0};
2725 let AsmMatchConverter = "cvtStExtTWriteBackImm";
2727 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2728 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2729 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2730 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2732 let Inst{23} = Rm{4};
2735 let Inst{3-0} = Rm{3-0};
2736 let AsmMatchConverter = "cvtStExtTWriteBackReg";
2741 defm STRHT : AI3strT<0b1011, "strht">;
2744 //===----------------------------------------------------------------------===//
2745 // Load / store multiple Instructions.
2748 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
2749 InstrItinClass itin, InstrItinClass itin_upd> {
2750 // IA is the default, so no need for an explicit suffix on the
2751 // mnemonic here. Without it is the cannonical spelling.
2753 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2754 IndexModeNone, f, itin,
2755 !strconcat(asm, "${p}\t$Rn, $regs"), "", []> {
2756 let Inst{24-23} = 0b01; // Increment After
2757 let Inst{21} = 0; // No writeback
2758 let Inst{20} = L_bit;
2761 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2762 IndexModeUpd, f, itin_upd,
2763 !strconcat(asm, "${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2764 let Inst{24-23} = 0b01; // Increment After
2765 let Inst{21} = 1; // Writeback
2766 let Inst{20} = L_bit;
2768 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2771 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2772 IndexModeNone, f, itin,
2773 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
2774 let Inst{24-23} = 0b00; // Decrement After
2775 let Inst{21} = 0; // No writeback
2776 let Inst{20} = L_bit;
2779 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2780 IndexModeUpd, f, itin_upd,
2781 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2782 let Inst{24-23} = 0b00; // Decrement After
2783 let Inst{21} = 1; // Writeback
2784 let Inst{20} = L_bit;
2786 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2789 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2790 IndexModeNone, f, itin,
2791 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
2792 let Inst{24-23} = 0b10; // Decrement Before
2793 let Inst{21} = 0; // No writeback
2794 let Inst{20} = L_bit;
2797 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2798 IndexModeUpd, f, itin_upd,
2799 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2800 let Inst{24-23} = 0b10; // Decrement Before
2801 let Inst{21} = 1; // Writeback
2802 let Inst{20} = L_bit;
2804 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2807 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2808 IndexModeNone, f, itin,
2809 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
2810 let Inst{24-23} = 0b11; // Increment Before
2811 let Inst{21} = 0; // No writeback
2812 let Inst{20} = L_bit;
2815 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2816 IndexModeUpd, f, itin_upd,
2817 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2818 let Inst{24-23} = 0b11; // Increment Before
2819 let Inst{21} = 1; // Writeback
2820 let Inst{20} = L_bit;
2822 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2826 let neverHasSideEffects = 1 in {
2828 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2829 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
2831 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2832 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
2834 } // neverHasSideEffects
2836 // FIXME: remove when we have a way to marking a MI with these properties.
2837 // FIXME: Should pc be an implicit operand like PICADD, etc?
2838 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2839 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2840 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2841 reglist:$regs, variable_ops),
2842 4, IIC_iLoad_mBr, [],
2843 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2844 RegConstraint<"$Rn = $wb">;
2846 //===----------------------------------------------------------------------===//
2847 // Move Instructions.
2850 let neverHasSideEffects = 1 in
2851 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2852 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2856 let Inst{19-16} = 0b0000;
2857 let Inst{11-4} = 0b00000000;
2860 let Inst{15-12} = Rd;
2863 def : ARMInstAlias<"movs${p} $Rd, $Rm",
2864 (MOVr GPR:$Rd, GPR:$Rm, pred:$p, CPSR)>;
2866 // A version for the smaller set of tail call registers.
2867 let neverHasSideEffects = 1 in
2868 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2869 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2873 let Inst{11-4} = 0b00000000;
2876 let Inst{15-12} = Rd;
2879 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2880 DPSoRegRegFrm, IIC_iMOVsr,
2881 "mov", "\t$Rd, $src",
2882 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP {
2885 let Inst{15-12} = Rd;
2886 let Inst{19-16} = 0b0000;
2887 let Inst{11-8} = src{11-8};
2889 let Inst{6-5} = src{6-5};
2891 let Inst{3-0} = src{3-0};
2895 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
2896 DPSoRegImmFrm, IIC_iMOVsr,
2897 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
2901 let Inst{15-12} = Rd;
2902 let Inst{19-16} = 0b0000;
2903 let Inst{11-5} = src{11-5};
2905 let Inst{3-0} = src{3-0};
2909 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2910 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2911 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2915 let Inst{15-12} = Rd;
2916 let Inst{19-16} = 0b0000;
2917 let Inst{11-0} = imm;
2920 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2921 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
2923 "movw", "\t$Rd, $imm",
2924 [(set GPR:$Rd, imm0_65535:$imm)]>,
2925 Requires<[IsARM, HasV6T2]>, UnaryDP {
2928 let Inst{15-12} = Rd;
2929 let Inst{11-0} = imm{11-0};
2930 let Inst{19-16} = imm{15-12};
2933 let DecoderMethod = "DecodeArmMOVTWInstruction";
2936 def : InstAlias<"mov${p} $Rd, $imm",
2937 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
2940 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2941 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2943 let Constraints = "$src = $Rd" in {
2944 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
2945 (ins GPR:$src, imm0_65535_expr:$imm),
2947 "movt", "\t$Rd, $imm",
2949 (or (and GPR:$src, 0xffff),
2950 lo16AllZero:$imm))]>, UnaryDP,
2951 Requires<[IsARM, HasV6T2]> {
2954 let Inst{15-12} = Rd;
2955 let Inst{11-0} = imm{11-0};
2956 let Inst{19-16} = imm{15-12};
2959 let DecoderMethod = "DecodeArmMOVTWInstruction";
2962 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2963 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2967 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2968 Requires<[IsARM, HasV6T2]>;
2970 let Uses = [CPSR] in
2971 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2972 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2975 // These aren't really mov instructions, but we have to define them this way
2976 // due to flag operands.
2978 let Defs = [CPSR] in {
2979 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2980 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2982 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2983 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2987 //===----------------------------------------------------------------------===//
2988 // Extend Instructions.
2993 def SXTB : AI_ext_rrot<0b01101010,
2994 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2995 def SXTH : AI_ext_rrot<0b01101011,
2996 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2998 def SXTAB : AI_exta_rrot<0b01101010,
2999 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3000 def SXTAH : AI_exta_rrot<0b01101011,
3001 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3003 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3005 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3009 let AddedComplexity = 16 in {
3010 def UXTB : AI_ext_rrot<0b01101110,
3011 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3012 def UXTH : AI_ext_rrot<0b01101111,
3013 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3014 def UXTB16 : AI_ext_rrot<0b01101100,
3015 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3017 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3018 // The transformation should probably be done as a combiner action
3019 // instead so we can include a check for masking back in the upper
3020 // eight bits of the source into the lower eight bits of the result.
3021 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3022 // (UXTB16r_rot GPR:$Src, 3)>;
3023 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3024 (UXTB16 GPR:$Src, 1)>;
3026 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3027 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3028 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3029 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3032 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3033 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3036 def SBFX : I<(outs GPRnopc:$Rd),
3037 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3038 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3039 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3040 Requires<[IsARM, HasV6T2]> {
3045 let Inst{27-21} = 0b0111101;
3046 let Inst{6-4} = 0b101;
3047 let Inst{20-16} = width;
3048 let Inst{15-12} = Rd;
3049 let Inst{11-7} = lsb;
3053 def UBFX : I<(outs GPR:$Rd),
3054 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3055 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3056 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3057 Requires<[IsARM, HasV6T2]> {
3062 let Inst{27-21} = 0b0111111;
3063 let Inst{6-4} = 0b101;
3064 let Inst{20-16} = width;
3065 let Inst{15-12} = Rd;
3066 let Inst{11-7} = lsb;
3070 //===----------------------------------------------------------------------===//
3071 // Arithmetic Instructions.
3074 defm ADD : AsI1_bin_irs<0b0100, "add",
3075 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3076 BinOpFrag<(add node:$LHS, node:$RHS)>, "ADD", 1>;
3077 defm SUB : AsI1_bin_irs<0b0010, "sub",
3078 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3079 BinOpFrag<(sub node:$LHS, node:$RHS)>, "SUB">;
3081 // ADD and SUB with 's' bit set.
3083 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3084 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3085 // AdjustInstrPostInstrSelection where we determine whether or not to
3086 // set the "s" bit based on CPSR liveness.
3088 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3089 // support for an optional CPSR definition that corresponds to the DAG
3090 // node's second value. We can then eliminate the implicit def of CPSR.
3091 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3092 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3093 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3094 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3096 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3097 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>,
3099 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3100 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3103 defm RSB : AsI1_rbin_irs <0b0011, "rsb",
3104 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3105 BinOpFrag<(sub node:$LHS, node:$RHS)>, "RSB">;
3107 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3108 // CPSR and the implicit def of CPSR is not needed.
3109 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3110 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3112 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3113 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3116 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3117 // The assume-no-carry-in form uses the negation of the input since add/sub
3118 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3119 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3121 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3122 (SUBri GPR:$src, so_imm_neg:$imm)>;
3123 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3124 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3126 // The with-carry-in form matches bitwise not instead of the negation.
3127 // Effectively, the inverse interpretation of the carry flag already accounts
3128 // for part of the negation.
3129 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3130 (SBCri GPR:$src, so_imm_not:$imm)>;
3132 // Note: These are implemented in C++ code, because they have to generate
3133 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3135 // (mul X, 2^n+1) -> (add (X << n), X)
3136 // (mul X, 2^n-1) -> (rsb X, (X << n))
3138 // ARM Arithmetic Instruction
3139 // GPR:$dst = GPR:$a op GPR:$b
3140 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3141 list<dag> pattern = [],
3142 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3143 string asm = "\t$Rd, $Rn, $Rm">
3144 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
3148 let Inst{27-20} = op27_20;
3149 let Inst{11-4} = op11_4;
3150 let Inst{19-16} = Rn;
3151 let Inst{15-12} = Rd;
3155 // Saturating add/subtract
3157 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3158 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3159 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3160 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3161 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3162 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3163 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3164 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3166 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3167 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3170 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3171 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3172 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3173 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3174 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3175 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3176 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3177 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3178 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3179 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3180 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3181 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3183 // Signed/Unsigned add/subtract
3185 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3186 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3187 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3188 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3189 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3190 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3191 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3192 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3193 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3194 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3195 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3196 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3198 // Signed/Unsigned halving add/subtract
3200 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3201 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3202 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3203 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3204 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3205 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3206 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3207 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3208 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3209 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3210 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3211 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3213 // Unsigned Sum of Absolute Differences [and Accumulate].
3215 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3216 MulFrm /* for convenience */, NoItinerary, "usad8",
3217 "\t$Rd, $Rn, $Rm", []>,
3218 Requires<[IsARM, HasV6]> {
3222 let Inst{27-20} = 0b01111000;
3223 let Inst{15-12} = 0b1111;
3224 let Inst{7-4} = 0b0001;
3225 let Inst{19-16} = Rd;
3226 let Inst{11-8} = Rm;
3229 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3230 MulFrm /* for convenience */, NoItinerary, "usada8",
3231 "\t$Rd, $Rn, $Rm, $Ra", []>,
3232 Requires<[IsARM, HasV6]> {
3237 let Inst{27-20} = 0b01111000;
3238 let Inst{7-4} = 0b0001;
3239 let Inst{19-16} = Rd;
3240 let Inst{15-12} = Ra;
3241 let Inst{11-8} = Rm;
3245 // Signed/Unsigned saturate
3247 def SSAT : AI<(outs GPRnopc:$Rd),
3248 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3249 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3254 let Inst{27-21} = 0b0110101;
3255 let Inst{5-4} = 0b01;
3256 let Inst{20-16} = sat_imm;
3257 let Inst{15-12} = Rd;
3258 let Inst{11-7} = sh{4-0};
3259 let Inst{6} = sh{5};
3263 def SSAT16 : AI<(outs GPRnopc:$Rd),
3264 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3265 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3269 let Inst{27-20} = 0b01101010;
3270 let Inst{11-4} = 0b11110011;
3271 let Inst{15-12} = Rd;
3272 let Inst{19-16} = sat_imm;
3276 def USAT : AI<(outs GPRnopc:$Rd),
3277 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3278 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3283 let Inst{27-21} = 0b0110111;
3284 let Inst{5-4} = 0b01;
3285 let Inst{15-12} = Rd;
3286 let Inst{11-7} = sh{4-0};
3287 let Inst{6} = sh{5};
3288 let Inst{20-16} = sat_imm;
3292 def USAT16 : AI<(outs GPRnopc:$Rd),
3293 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3294 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3298 let Inst{27-20} = 0b01101110;
3299 let Inst{11-4} = 0b11110011;
3300 let Inst{15-12} = Rd;
3301 let Inst{19-16} = sat_imm;
3305 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3306 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3307 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3308 (USAT imm:$pos, GPRnopc:$a, 0)>;
3310 //===----------------------------------------------------------------------===//
3311 // Bitwise Instructions.
3314 defm AND : AsI1_bin_irs<0b0000, "and",
3315 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3316 BinOpFrag<(and node:$LHS, node:$RHS)>, "AND", 1>;
3317 defm ORR : AsI1_bin_irs<0b1100, "orr",
3318 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3319 BinOpFrag<(or node:$LHS, node:$RHS)>, "ORR", 1>;
3320 defm EOR : AsI1_bin_irs<0b0001, "eor",
3321 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3322 BinOpFrag<(xor node:$LHS, node:$RHS)>, "EOR", 1>;
3323 defm BIC : AsI1_bin_irs<0b1110, "bic",
3324 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3325 BinOpFrag<(and node:$LHS, (not node:$RHS))>, "BIC">;
3327 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3328 // like in the actual instruction encoding. The complexity of mapping the mask
3329 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3330 // instruction description.
3331 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3332 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3333 "bfc", "\t$Rd, $imm", "$src = $Rd",
3334 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3335 Requires<[IsARM, HasV6T2]> {
3338 let Inst{27-21} = 0b0111110;
3339 let Inst{6-0} = 0b0011111;
3340 let Inst{15-12} = Rd;
3341 let Inst{11-7} = imm{4-0}; // lsb
3342 let Inst{20-16} = imm{9-5}; // msb
3345 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3346 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3347 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3348 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3349 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3350 bf_inv_mask_imm:$imm))]>,
3351 Requires<[IsARM, HasV6T2]> {
3355 let Inst{27-21} = 0b0111110;
3356 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3357 let Inst{15-12} = Rd;
3358 let Inst{11-7} = imm{4-0}; // lsb
3359 let Inst{20-16} = imm{9-5}; // width
3363 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3364 "mvn", "\t$Rd, $Rm",
3365 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
3369 let Inst{19-16} = 0b0000;
3370 let Inst{11-4} = 0b00000000;
3371 let Inst{15-12} = Rd;
3374 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3375 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3376 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
3380 let Inst{19-16} = 0b0000;
3381 let Inst{15-12} = Rd;
3382 let Inst{11-5} = shift{11-5};
3384 let Inst{3-0} = shift{3-0};
3386 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3387 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3388 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
3392 let Inst{19-16} = 0b0000;
3393 let Inst{15-12} = Rd;
3394 let Inst{11-8} = shift{11-8};
3396 let Inst{6-5} = shift{6-5};
3398 let Inst{3-0} = shift{3-0};
3400 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3401 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3402 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3403 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
3407 let Inst{19-16} = 0b0000;
3408 let Inst{15-12} = Rd;
3409 let Inst{11-0} = imm;
3412 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3413 (BICri GPR:$src, so_imm_not:$imm)>;
3415 //===----------------------------------------------------------------------===//
3416 // Multiply Instructions.
3418 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3419 string opc, string asm, list<dag> pattern>
3420 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3424 let Inst{19-16} = Rd;
3425 let Inst{11-8} = Rm;
3428 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3429 string opc, string asm, list<dag> pattern>
3430 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3435 let Inst{19-16} = RdHi;
3436 let Inst{15-12} = RdLo;
3437 let Inst{11-8} = Rm;
3441 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3442 // property. Remove them when it's possible to add those properties
3443 // on an individual MachineInstr, not just an instuction description.
3444 let isCommutable = 1 in {
3445 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3446 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3447 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
3448 Requires<[IsARM, HasV6]> {
3449 let Inst{15-12} = 0b0000;
3452 let Constraints = "@earlyclobber $Rd" in
3453 def MULv5: ARMPseudoExpand<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
3454 pred:$p, cc_out:$s),
3456 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))],
3457 (MUL GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3458 Requires<[IsARM, NoV6]>;
3461 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3462 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3463 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3464 Requires<[IsARM, HasV6]> {
3466 let Inst{15-12} = Ra;
3469 let Constraints = "@earlyclobber $Rd" in
3470 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3471 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3473 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3474 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3475 Requires<[IsARM, NoV6]>;
3477 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3478 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3479 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3480 Requires<[IsARM, HasV6T2]> {
3485 let Inst{19-16} = Rd;
3486 let Inst{15-12} = Ra;
3487 let Inst{11-8} = Rm;
3491 // Extra precision multiplies with low / high results
3492 let neverHasSideEffects = 1 in {
3493 let isCommutable = 1 in {
3494 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3495 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3496 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3497 Requires<[IsARM, HasV6]>;
3499 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3500 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3501 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3502 Requires<[IsARM, HasV6]>;
3504 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3505 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3506 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3508 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3509 Requires<[IsARM, NoV6]>;
3511 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3512 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3514 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3515 Requires<[IsARM, NoV6]>;
3519 // Multiply + accumulate
3520 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3521 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3522 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3523 Requires<[IsARM, HasV6]>;
3524 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3525 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3526 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3527 Requires<[IsARM, HasV6]>;
3529 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3530 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3531 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3532 Requires<[IsARM, HasV6]> {
3537 let Inst{19-16} = RdHi;
3538 let Inst{15-12} = RdLo;
3539 let Inst{11-8} = Rm;
3543 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3544 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3545 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3547 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3548 Requires<[IsARM, NoV6]>;
3549 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3550 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3552 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3553 Requires<[IsARM, NoV6]>;
3554 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3555 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3557 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3558 Requires<[IsARM, NoV6]>;
3561 } // neverHasSideEffects
3563 // Most significant word multiply
3564 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3565 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3566 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3567 Requires<[IsARM, HasV6]> {
3568 let Inst{15-12} = 0b1111;
3571 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3572 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3573 Requires<[IsARM, HasV6]> {
3574 let Inst{15-12} = 0b1111;
3577 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3578 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3579 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3580 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3581 Requires<[IsARM, HasV6]>;
3583 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3584 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3585 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3586 Requires<[IsARM, HasV6]>;
3588 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3589 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3590 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
3591 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
3592 Requires<[IsARM, HasV6]>;
3594 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3595 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3596 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3597 Requires<[IsARM, HasV6]>;
3599 multiclass AI_smul<string opc, PatFrag opnode> {
3600 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3601 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3602 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3603 (sext_inreg GPR:$Rm, i16)))]>,
3604 Requires<[IsARM, HasV5TE]>;
3606 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3607 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3608 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3609 (sra GPR:$Rm, (i32 16))))]>,
3610 Requires<[IsARM, HasV5TE]>;
3612 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3613 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3614 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3615 (sext_inreg GPR:$Rm, i16)))]>,
3616 Requires<[IsARM, HasV5TE]>;
3618 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3619 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3620 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3621 (sra GPR:$Rm, (i32 16))))]>,
3622 Requires<[IsARM, HasV5TE]>;
3624 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3625 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3626 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3627 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3628 Requires<[IsARM, HasV5TE]>;
3630 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3631 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3632 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3633 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3634 Requires<[IsARM, HasV5TE]>;
3638 multiclass AI_smla<string opc, PatFrag opnode> {
3639 let DecoderMethod = "DecodeSMLAInstruction" in {
3640 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3641 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3642 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3643 [(set GPRnopc:$Rd, (add GPR:$Ra,
3644 (opnode (sext_inreg GPRnopc:$Rn, i16),
3645 (sext_inreg GPRnopc:$Rm, i16))))]>,
3646 Requires<[IsARM, HasV5TE]>;
3648 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3649 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3650 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3652 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3653 (sra GPRnopc:$Rm, (i32 16)))))]>,
3654 Requires<[IsARM, HasV5TE]>;
3656 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3657 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3658 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3660 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3661 (sext_inreg GPRnopc:$Rm, i16))))]>,
3662 Requires<[IsARM, HasV5TE]>;
3664 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3665 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3666 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3668 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3669 (sra GPRnopc:$Rm, (i32 16)))))]>,
3670 Requires<[IsARM, HasV5TE]>;
3672 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3673 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3674 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3676 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3677 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3678 Requires<[IsARM, HasV5TE]>;
3680 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3681 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3682 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3684 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3685 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3686 Requires<[IsARM, HasV5TE]>;
3690 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3691 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3693 // Halfword multiply accumulate long: SMLAL<x><y>.
3694 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3695 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3696 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3697 Requires<[IsARM, HasV5TE]>;
3699 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3700 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3701 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3702 Requires<[IsARM, HasV5TE]>;
3704 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3705 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3706 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3707 Requires<[IsARM, HasV5TE]>;
3709 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3710 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3711 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3712 Requires<[IsARM, HasV5TE]>;
3714 // Helper class for AI_smld.
3715 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3716 InstrItinClass itin, string opc, string asm>
3717 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3720 let Inst{27-23} = 0b01110;
3721 let Inst{22} = long;
3722 let Inst{21-20} = 0b00;
3723 let Inst{11-8} = Rm;
3730 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3731 InstrItinClass itin, string opc, string asm>
3732 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3734 let Inst{15-12} = 0b1111;
3735 let Inst{19-16} = Rd;
3737 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3738 InstrItinClass itin, string opc, string asm>
3739 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3742 let Inst{19-16} = Rd;
3743 let Inst{15-12} = Ra;
3745 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3746 InstrItinClass itin, string opc, string asm>
3747 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3750 let Inst{19-16} = RdHi;
3751 let Inst{15-12} = RdLo;
3754 multiclass AI_smld<bit sub, string opc> {
3756 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3757 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3758 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3760 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3761 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3762 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3764 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3765 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3766 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3768 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3769 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3770 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3774 defm SMLA : AI_smld<0, "smla">;
3775 defm SMLS : AI_smld<1, "smls">;
3777 multiclass AI_sdml<bit sub, string opc> {
3779 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3780 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3781 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3782 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3785 defm SMUA : AI_sdml<0, "smua">;
3786 defm SMUS : AI_sdml<1, "smus">;
3788 //===----------------------------------------------------------------------===//
3789 // Misc. Arithmetic Instructions.
3792 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3793 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3794 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3796 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3797 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3798 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3799 Requires<[IsARM, HasV6T2]>;
3801 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3802 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3803 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3805 let AddedComplexity = 5 in
3806 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3807 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3808 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3809 Requires<[IsARM, HasV6]>;
3811 let AddedComplexity = 5 in
3812 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3813 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3814 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3815 Requires<[IsARM, HasV6]>;
3817 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3818 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3821 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3822 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3823 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3824 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3825 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3827 Requires<[IsARM, HasV6]>;
3829 // Alternate cases for PKHBT where identities eliminate some nodes.
3830 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3831 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
3832 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
3833 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
3835 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3836 // will match the pattern below.
3837 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
3838 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
3839 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3840 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
3841 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
3843 Requires<[IsARM, HasV6]>;
3845 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3846 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3847 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3848 (srl GPRnopc:$src2, imm16_31:$sh)),
3849 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
3850 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3851 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
3852 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
3854 //===----------------------------------------------------------------------===//
3855 // Comparison Instructions...
3858 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3859 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3860 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3862 // ARMcmpZ can re-use the above instruction definitions.
3863 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3864 (CMPri GPR:$src, so_imm:$imm)>;
3865 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3866 (CMPrr GPR:$src, GPR:$rhs)>;
3867 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
3868 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
3869 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
3870 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
3872 // FIXME: We have to be careful when using the CMN instruction and comparison
3873 // with 0. One would expect these two pieces of code should give identical
3889 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3890 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3891 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3892 // value of r0 and the carry bit (because the "carry bit" parameter to
3893 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3894 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3895 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3896 // parameter to AddWithCarry is defined as 0).
3898 // When x is 0 and unsigned:
3902 // ~x + 1 = 0x1 0000 0000
3903 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3905 // Therefore, we should disable CMN when comparing against zero, until we can
3906 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3907 // when it's a comparison which doesn't look at the 'carry' flag).
3909 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3911 // This is related to <rdar://problem/7569620>.
3913 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3914 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3916 // Note that TST/TEQ don't set all the same flags that CMP does!
3917 defm TST : AI1_cmp_irs<0b1000, "tst",
3918 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3919 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3920 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3921 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3922 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3924 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
3925 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3926 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
3928 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3929 // (CMNri GPR:$src, so_imm_neg:$imm)>;
3931 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3932 (CMNzri GPR:$src, so_imm_neg:$imm)>;
3934 // Pseudo i64 compares for some floating point compares.
3935 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3937 def BCCi64 : PseudoInst<(outs),
3938 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3940 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3942 def BCCZi64 : PseudoInst<(outs),
3943 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3944 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3945 } // usesCustomInserter
3948 // Conditional moves
3949 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3950 // a two-value operand where a dag node expects two operands. :(
3951 let neverHasSideEffects = 1 in {
3952 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3954 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3955 RegConstraint<"$false = $Rd">;
3956 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
3957 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
3959 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
3960 imm:$cc, CCR:$ccr))*/]>,
3961 RegConstraint<"$false = $Rd">;
3962 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
3963 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
3965 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
3966 imm:$cc, CCR:$ccr))*/]>,
3967 RegConstraint<"$false = $Rd">;
3970 let isMoveImm = 1 in
3971 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3972 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
3975 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3977 let isMoveImm = 1 in
3978 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3979 (ins GPR:$false, so_imm:$imm, pred:$p),
3981 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3982 RegConstraint<"$false = $Rd">;
3984 // Two instruction predicate mov immediate.
3985 let isMoveImm = 1 in
3986 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
3987 (ins GPR:$false, i32imm:$src, pred:$p),
3988 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3990 let isMoveImm = 1 in
3991 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
3992 (ins GPR:$false, so_imm:$imm, pred:$p),
3994 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3995 RegConstraint<"$false = $Rd">;
3996 } // neverHasSideEffects
3998 //===----------------------------------------------------------------------===//
3999 // Atomic operations intrinsics
4002 def MemBarrierOptOperand : AsmOperandClass {
4003 let Name = "MemBarrierOpt";
4004 let ParserMethod = "parseMemBarrierOptOperand";
4006 def memb_opt : Operand<i32> {
4007 let PrintMethod = "printMemBOption";
4008 let ParserMatchClass = MemBarrierOptOperand;
4009 let DecoderMethod = "DecodeMemBarrierOption";
4012 // memory barriers protect the atomic sequences
4013 let hasSideEffects = 1 in {
4014 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4015 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
4016 Requires<[IsARM, HasDB]> {
4018 let Inst{31-4} = 0xf57ff05;
4019 let Inst{3-0} = opt;
4023 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4024 "dsb", "\t$opt", []>,
4025 Requires<[IsARM, HasDB]> {
4027 let Inst{31-4} = 0xf57ff04;
4028 let Inst{3-0} = opt;
4031 // ISB has only full system option
4032 def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4033 "isb", "\t$opt", []>,
4034 Requires<[IsARM, HasDB]> {
4036 let Inst{31-4} = 0xf57ff06;
4037 let Inst{3-0} = opt;
4040 // Pseudo isntruction that combines movs + predicated rsbmi
4041 // to implement integer ABS
4042 let usesCustomInserter = 1, Defs = [CPSR] in {
4043 def ABS : ARMPseudoInst<
4044 (outs GPR:$dst), (ins GPR:$src),
4045 8, NoItinerary, []>;
4048 let usesCustomInserter = 1 in {
4049 let Defs = [CPSR] in {
4050 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4051 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4052 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
4053 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4054 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4055 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
4056 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4057 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4058 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
4059 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4060 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4061 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4062 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4063 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4064 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4065 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4066 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4067 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4068 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4069 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4070 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4071 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4072 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4073 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4074 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4075 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4076 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4077 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4078 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4079 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4080 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4081 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4082 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4083 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4084 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4085 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4086 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4087 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4088 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4089 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4090 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4091 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4092 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4093 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4094 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4095 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4096 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4097 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4098 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4099 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4100 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4101 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4102 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4103 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4104 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4105 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4106 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4107 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4108 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4109 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4110 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4111 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4112 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4113 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4114 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4115 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4116 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4117 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4118 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4119 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4120 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4121 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4122 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4123 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4124 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4125 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4126 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4127 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4128 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4129 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4130 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4131 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4132 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4133 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4134 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4135 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4136 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4137 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4138 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4139 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4141 def ATOMIC_SWAP_I8 : PseudoInst<
4142 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4143 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4144 def ATOMIC_SWAP_I16 : PseudoInst<
4145 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4146 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4147 def ATOMIC_SWAP_I32 : PseudoInst<
4148 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4149 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4151 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4152 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4153 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4154 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4155 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4156 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4157 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4158 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4159 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4163 let mayLoad = 1 in {
4164 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4166 "ldrexb", "\t$Rt, $addr", []>;
4167 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4168 NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
4169 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4170 NoItinerary, "ldrex", "\t$Rt, $addr", []>;
4171 let hasExtraDefRegAllocReq = 1 in
4172 def LDREXD: AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2),(ins addr_offset_none:$addr),
4173 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []> {
4174 let DecoderMethod = "DecodeDoubleRegLoad";
4178 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4179 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4180 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
4181 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4182 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
4183 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4184 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
4187 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
4188 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4189 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr),
4190 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []> {
4191 let DecoderMethod = "DecodeDoubleRegStore";
4194 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
4195 Requires<[IsARM, HasV7]> {
4196 let Inst{31-0} = 0b11110101011111111111000000011111;
4199 // SWP/SWPB are deprecated in V6/V7.
4200 let mayLoad = 1, mayStore = 1 in {
4201 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
4203 def SWPB: AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
4207 //===----------------------------------------------------------------------===//
4208 // Coprocessor Instructions.
4211 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4212 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4213 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4214 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4215 imm:$CRm, imm:$opc2)]> {
4223 let Inst{3-0} = CRm;
4225 let Inst{7-5} = opc2;
4226 let Inst{11-8} = cop;
4227 let Inst{15-12} = CRd;
4228 let Inst{19-16} = CRn;
4229 let Inst{23-20} = opc1;
4232 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4233 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4234 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4235 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4236 imm:$CRm, imm:$opc2)]> {
4237 let Inst{31-28} = 0b1111;
4245 let Inst{3-0} = CRm;
4247 let Inst{7-5} = opc2;
4248 let Inst{11-8} = cop;
4249 let Inst{15-12} = CRd;
4250 let Inst{19-16} = CRn;
4251 let Inst{23-20} = opc1;
4254 class ACI<dag oops, dag iops, string opc, string asm,
4255 IndexMode im = IndexModeNone>
4256 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4258 let Inst{27-25} = 0b110;
4260 class ACInoP<dag oops, dag iops, string opc, string asm,
4261 IndexMode im = IndexModeNone>
4262 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4264 let Inst{31-28} = 0b1111;
4265 let Inst{27-25} = 0b110;
4267 multiclass LdStCop<bit load, bit Dbit, string asm> {
4268 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4269 asm, "\t$cop, $CRd, $addr"> {
4273 let Inst{24} = 1; // P = 1
4274 let Inst{23} = addr{8};
4275 let Inst{22} = Dbit;
4276 let Inst{21} = 0; // W = 0
4277 let Inst{20} = load;
4278 let Inst{19-16} = addr{12-9};
4279 let Inst{15-12} = CRd;
4280 let Inst{11-8} = cop;
4281 let Inst{7-0} = addr{7-0};
4282 let DecoderMethod = "DecodeCopMemInstruction";
4284 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4285 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4289 let Inst{24} = 1; // P = 1
4290 let Inst{23} = addr{8};
4291 let Inst{22} = Dbit;
4292 let Inst{21} = 1; // W = 1
4293 let Inst{20} = load;
4294 let Inst{19-16} = addr{12-9};
4295 let Inst{15-12} = CRd;
4296 let Inst{11-8} = cop;
4297 let Inst{7-0} = addr{7-0};
4298 let DecoderMethod = "DecodeCopMemInstruction";
4300 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4301 postidx_imm8s4:$offset),
4302 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4307 let Inst{24} = 0; // P = 0
4308 let Inst{23} = offset{8};
4309 let Inst{22} = Dbit;
4310 let Inst{21} = 1; // W = 1
4311 let Inst{20} = load;
4312 let Inst{19-16} = addr;
4313 let Inst{15-12} = CRd;
4314 let Inst{11-8} = cop;
4315 let Inst{7-0} = offset{7-0};
4316 let DecoderMethod = "DecodeCopMemInstruction";
4318 def _OPTION : ACI<(outs),
4319 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4320 coproc_option_imm:$option),
4321 asm, "\t$cop, $CRd, $addr, $option"> {
4326 let Inst{24} = 0; // P = 0
4327 let Inst{23} = 1; // U = 1
4328 let Inst{22} = Dbit;
4329 let Inst{21} = 0; // W = 0
4330 let Inst{20} = load;
4331 let Inst{19-16} = addr;
4332 let Inst{15-12} = CRd;
4333 let Inst{11-8} = cop;
4334 let Inst{7-0} = option;
4335 let DecoderMethod = "DecodeCopMemInstruction";
4338 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4339 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4340 asm, "\t$cop, $CRd, $addr"> {
4344 let Inst{24} = 1; // P = 1
4345 let Inst{23} = addr{8};
4346 let Inst{22} = Dbit;
4347 let Inst{21} = 0; // W = 0
4348 let Inst{20} = load;
4349 let Inst{19-16} = addr{12-9};
4350 let Inst{15-12} = CRd;
4351 let Inst{11-8} = cop;
4352 let Inst{7-0} = addr{7-0};
4353 let DecoderMethod = "DecodeCopMemInstruction";
4355 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4356 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4360 let Inst{24} = 1; // P = 1
4361 let Inst{23} = addr{8};
4362 let Inst{22} = Dbit;
4363 let Inst{21} = 1; // W = 1
4364 let Inst{20} = load;
4365 let Inst{19-16} = addr{12-9};
4366 let Inst{15-12} = CRd;
4367 let Inst{11-8} = cop;
4368 let Inst{7-0} = addr{7-0};
4369 let DecoderMethod = "DecodeCopMemInstruction";
4371 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4372 postidx_imm8s4:$offset),
4373 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4378 let Inst{24} = 0; // P = 0
4379 let Inst{23} = offset{8};
4380 let Inst{22} = Dbit;
4381 let Inst{21} = 1; // W = 1
4382 let Inst{20} = load;
4383 let Inst{19-16} = addr;
4384 let Inst{15-12} = CRd;
4385 let Inst{11-8} = cop;
4386 let Inst{7-0} = offset{7-0};
4387 let DecoderMethod = "DecodeCopMemInstruction";
4389 def _OPTION : ACInoP<(outs),
4390 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4391 coproc_option_imm:$option),
4392 asm, "\t$cop, $CRd, $addr, $option"> {
4397 let Inst{24} = 0; // P = 0
4398 let Inst{23} = 1; // U = 1
4399 let Inst{22} = Dbit;
4400 let Inst{21} = 0; // W = 0
4401 let Inst{20} = load;
4402 let Inst{19-16} = addr;
4403 let Inst{15-12} = CRd;
4404 let Inst{11-8} = cop;
4405 let Inst{7-0} = option;
4406 let DecoderMethod = "DecodeCopMemInstruction";
4410 defm LDC : LdStCop <1, 0, "ldc">;
4411 defm LDCL : LdStCop <1, 1, "ldcl">;
4412 defm STC : LdStCop <0, 0, "stc">;
4413 defm STCL : LdStCop <0, 1, "stcl">;
4414 defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
4415 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
4416 defm STC2 : LdSt2Cop<0, 0, "stc2">;
4417 defm STC2L : LdSt2Cop<0, 1, "stc2l">;
4419 //===----------------------------------------------------------------------===//
4420 // Move between coprocessor and ARM core register.
4423 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4425 : ABI<0b1110, oops, iops, NoItinerary, opc,
4426 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4427 let Inst{20} = direction;
4437 let Inst{15-12} = Rt;
4438 let Inst{11-8} = cop;
4439 let Inst{23-21} = opc1;
4440 let Inst{7-5} = opc2;
4441 let Inst{3-0} = CRm;
4442 let Inst{19-16} = CRn;
4445 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4447 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4448 c_imm:$CRm, imm0_7:$opc2),
4449 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4450 imm:$CRm, imm:$opc2)]>;
4451 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4453 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4456 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4457 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4459 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4461 : ABXI<0b1110, oops, iops, NoItinerary,
4462 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4463 let Inst{31-28} = 0b1111;
4464 let Inst{20} = direction;
4474 let Inst{15-12} = Rt;
4475 let Inst{11-8} = cop;
4476 let Inst{23-21} = opc1;
4477 let Inst{7-5} = opc2;
4478 let Inst{3-0} = CRm;
4479 let Inst{19-16} = CRn;
4482 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4484 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4485 c_imm:$CRm, imm0_7:$opc2),
4486 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4487 imm:$CRm, imm:$opc2)]>;
4488 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4490 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4493 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4494 imm:$CRm, imm:$opc2),
4495 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4497 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4498 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4499 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
4500 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4501 let Inst{23-21} = 0b010;
4502 let Inst{20} = direction;
4510 let Inst{15-12} = Rt;
4511 let Inst{19-16} = Rt2;
4512 let Inst{11-8} = cop;
4513 let Inst{7-4} = opc1;
4514 let Inst{3-0} = CRm;
4517 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4518 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4520 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4522 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4523 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4524 GPR:$Rt, GPR:$Rt2, c_imm:$CRm), NoItinerary,
4525 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4526 let Inst{31-28} = 0b1111;
4527 let Inst{23-21} = 0b010;
4528 let Inst{20} = direction;
4536 let Inst{15-12} = Rt;
4537 let Inst{19-16} = Rt2;
4538 let Inst{11-8} = cop;
4539 let Inst{7-4} = opc1;
4540 let Inst{3-0} = CRm;
4543 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4544 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4546 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4548 //===----------------------------------------------------------------------===//
4549 // Move between special register and ARM core register
4552 // Move to ARM core register from Special Register
4553 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
4554 "mrs", "\t$Rd, apsr", []> {
4556 let Inst{23-16} = 0b00001111;
4557 let Inst{15-12} = Rd;
4558 let Inst{7-4} = 0b0000;
4561 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPR:$Rd, pred:$p)>, Requires<[IsARM]>;
4563 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
4564 "mrs", "\t$Rd, spsr", []> {
4566 let Inst{23-16} = 0b01001111;
4567 let Inst{15-12} = Rd;
4568 let Inst{7-4} = 0b0000;
4571 // Move from ARM core register to Special Register
4573 // No need to have both system and application versions, the encodings are the
4574 // same and the assembly parser has no way to distinguish between them. The mask
4575 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4576 // the mask with the fields to be accessed in the special register.
4577 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4578 "msr", "\t$mask, $Rn", []> {
4583 let Inst{22} = mask{4}; // R bit
4584 let Inst{21-20} = 0b10;
4585 let Inst{19-16} = mask{3-0};
4586 let Inst{15-12} = 0b1111;
4587 let Inst{11-4} = 0b00000000;
4591 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4592 "msr", "\t$mask, $a", []> {
4597 let Inst{22} = mask{4}; // R bit
4598 let Inst{21-20} = 0b10;
4599 let Inst{19-16} = mask{3-0};
4600 let Inst{15-12} = 0b1111;
4604 //===----------------------------------------------------------------------===//
4608 // __aeabi_read_tp preserves the registers r1-r3.
4609 // This is a pseudo inst so that we can get the encoding right,
4610 // complete with fixup for the aeabi_read_tp function.
4612 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4613 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4614 [(set R0, ARMthread_pointer)]>;
4617 //===----------------------------------------------------------------------===//
4618 // SJLJ Exception handling intrinsics
4619 // eh_sjlj_setjmp() is an instruction sequence to store the return
4620 // address and save #0 in R0 for the non-longjmp case.
4621 // Since by its nature we may be coming from some other function to get
4622 // here, and we're using the stack frame for the containing function to
4623 // save/restore registers, we can't keep anything live in regs across
4624 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4625 // when we get here from a longjmp(). We force everything out of registers
4626 // except for our own input by listing the relevant registers in Defs. By
4627 // doing so, we also cause the prologue/epilogue code to actively preserve
4628 // all of the callee-saved resgisters, which is exactly what we want.
4629 // A constant value is passed in $val, and we use the location as a scratch.
4631 // These are pseudo-instructions and are lowered to individual MC-insts, so
4632 // no encoding information is necessary.
4634 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4635 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ], hasSideEffects = 1, isBarrier = 1,
4636 usesCustomInserter = 1 in {
4637 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4639 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4640 Requires<[IsARM, HasVFP2]>;
4644 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4645 hasSideEffects = 1, isBarrier = 1 in {
4646 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4648 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4649 Requires<[IsARM, NoVFP]>;
4652 // FIXME: Non-Darwin version(s)
4653 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4654 Defs = [ R7, LR, SP ] in {
4655 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4657 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4658 Requires<[IsARM, IsDarwin]>;
4661 // eh.sjlj.dispatchsetup pseudo-instruction.
4662 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
4663 // handled when the pseudo is expanded (which happens before any passes
4664 // that need the instruction size).
4665 let isBarrier = 1, hasSideEffects = 1 in
4666 def Int_eh_sjlj_dispatchsetup :
4667 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
4668 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
4669 Requires<[IsDarwin]>;
4671 //===----------------------------------------------------------------------===//
4672 // Non-Instruction Patterns
4675 // ARMv4 indirect branch using (MOVr PC, dst)
4676 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4677 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4678 4, IIC_Br, [(brind GPR:$dst)],
4679 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4680 Requires<[IsARM, NoV4T]>;
4682 // Large immediate handling.
4684 // 32-bit immediate using two piece so_imms or movw + movt.
4685 // This is a single pseudo instruction, the benefit is that it can be remat'd
4686 // as a single unit instead of having to handle reg inputs.
4687 // FIXME: Remove this when we can do generalized remat.
4688 let isReMaterializable = 1, isMoveImm = 1 in
4689 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4690 [(set GPR:$dst, (arm_i32imm:$src))]>,
4693 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4694 // It also makes it possible to rematerialize the instructions.
4695 // FIXME: Remove this when we can do generalized remat and when machine licm
4696 // can properly the instructions.
4697 let isReMaterializable = 1 in {
4698 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4700 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4701 Requires<[IsARM, UseMovt]>;
4703 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4705 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4706 Requires<[IsARM, UseMovt]>;
4708 let AddedComplexity = 10 in
4709 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4711 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4712 Requires<[IsARM, UseMovt]>;
4713 } // isReMaterializable
4715 // ConstantPool, GlobalAddress, and JumpTable
4716 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4717 Requires<[IsARM, DontUseMovt]>;
4718 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4719 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4720 Requires<[IsARM, UseMovt]>;
4721 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4722 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4724 // TODO: add,sub,and, 3-instr forms?
4727 def : ARMPat<(ARMtcret tcGPR:$dst),
4728 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
4730 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
4731 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
4733 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
4734 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
4736 def : ARMPat<(ARMtcret tcGPR:$dst),
4737 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
4739 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
4740 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
4742 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
4743 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
4746 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
4747 Requires<[IsARM, IsNotDarwin]>;
4748 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
4749 Requires<[IsARM, IsDarwin]>;
4751 // zextload i1 -> zextload i8
4752 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4753 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4755 // extload -> zextload
4756 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4757 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4758 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4759 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4761 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4763 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4764 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4767 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4768 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4769 (SMULBB GPR:$a, GPR:$b)>;
4770 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4771 (SMULBB GPR:$a, GPR:$b)>;
4772 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4773 (sra GPR:$b, (i32 16))),
4774 (SMULBT GPR:$a, GPR:$b)>;
4775 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
4776 (SMULBT GPR:$a, GPR:$b)>;
4777 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4778 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4779 (SMULTB GPR:$a, GPR:$b)>;
4780 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
4781 (SMULTB GPR:$a, GPR:$b)>;
4782 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4784 (SMULWB GPR:$a, GPR:$b)>;
4785 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
4786 (SMULWB GPR:$a, GPR:$b)>;
4788 def : ARMV5TEPat<(add GPR:$acc,
4789 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4790 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4791 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4792 def : ARMV5TEPat<(add GPR:$acc,
4793 (mul sext_16_node:$a, sext_16_node:$b)),
4794 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4795 def : ARMV5TEPat<(add GPR:$acc,
4796 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4797 (sra GPR:$b, (i32 16)))),
4798 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4799 def : ARMV5TEPat<(add GPR:$acc,
4800 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
4801 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4802 def : ARMV5TEPat<(add GPR:$acc,
4803 (mul (sra GPR:$a, (i32 16)),
4804 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4805 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4806 def : ARMV5TEPat<(add GPR:$acc,
4807 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
4808 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4809 def : ARMV5TEPat<(add GPR:$acc,
4810 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4812 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4813 def : ARMV5TEPat<(add GPR:$acc,
4814 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
4815 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4818 // Pre-v7 uses MCR for synchronization barriers.
4819 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
4820 Requires<[IsARM, HasV6]>;
4822 // SXT/UXT with no rotate
4823 let AddedComplexity = 16 in {
4824 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
4825 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
4826 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
4827 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
4828 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
4829 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
4830 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
4833 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
4834 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
4836 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
4837 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
4838 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
4839 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
4841 // Atomic load/store patterns
4842 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
4843 (LDRBrs ldst_so_reg:$src)>;
4844 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
4845 (LDRBi12 addrmode_imm12:$src)>;
4846 def : ARMPat<(atomic_load_16 addrmode3:$src),
4847 (LDRH addrmode3:$src)>;
4848 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
4849 (LDRrs ldst_so_reg:$src)>;
4850 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
4851 (LDRi12 addrmode_imm12:$src)>;
4852 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
4853 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
4854 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
4855 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
4856 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
4857 (STRH GPR:$val, addrmode3:$ptr)>;
4858 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
4859 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
4860 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
4861 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
4864 //===----------------------------------------------------------------------===//
4868 include "ARMInstrThumb.td"
4870 //===----------------------------------------------------------------------===//
4874 include "ARMInstrThumb2.td"
4876 //===----------------------------------------------------------------------===//
4877 // Floating Point Support
4880 include "ARMInstrVFP.td"
4882 //===----------------------------------------------------------------------===//
4883 // Advanced SIMD (NEON) Support
4886 include "ARMInstrNEON.td"
4888 //===----------------------------------------------------------------------===//
4889 // Assembler aliases
4893 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
4894 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
4895 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
4897 // System instructions
4898 def : MnemonicAlias<"swi", "svc">;
4900 // Load / Store Multiple
4901 def : MnemonicAlias<"ldmfd", "ldm">;
4902 def : MnemonicAlias<"ldmia", "ldm">;
4903 def : MnemonicAlias<"ldmea", "ldmdb">;
4904 def : MnemonicAlias<"stmfd", "stmdb">;
4905 def : MnemonicAlias<"stmia", "stm">;
4906 def : MnemonicAlias<"stmea", "stm">;
4908 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4909 // shift amount is zero (i.e., unspecified).
4910 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4911 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4912 Requires<[IsARM, HasV6]>;
4913 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4914 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4915 Requires<[IsARM, HasV6]>;
4917 // PUSH/POP aliases for STM/LDM
4918 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
4919 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4921 // SSAT/USAT optional shift operand.
4922 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4923 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4924 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4925 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4928 // Extend instruction optional rotate operand.
4929 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4930 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4931 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4932 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4933 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4934 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4935 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
4936 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4937 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
4938 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4939 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
4940 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4942 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4943 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4944 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4945 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4946 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4947 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4948 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
4949 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4950 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
4951 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4952 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
4953 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4957 def : MnemonicAlias<"rfefa", "rfeda">;
4958 def : MnemonicAlias<"rfeea", "rfedb">;
4959 def : MnemonicAlias<"rfefd", "rfeia">;
4960 def : MnemonicAlias<"rfeed", "rfeib">;
4961 def : MnemonicAlias<"rfe", "rfeia">;
4964 def : MnemonicAlias<"srsfa", "srsda">;
4965 def : MnemonicAlias<"srsea", "srsdb">;
4966 def : MnemonicAlias<"srsfd", "srsia">;
4967 def : MnemonicAlias<"srsed", "srsib">;
4968 def : MnemonicAlias<"srs", "srsia">;
4971 def : MnemonicAlias<"qsubaddx", "qsax">;
4973 def : MnemonicAlias<"saddsubx", "sasx">;
4974 // SHASX == SHADDSUBX
4975 def : MnemonicAlias<"shaddsubx", "shasx">;
4976 // SHSAX == SHSUBADDX
4977 def : MnemonicAlias<"shsubaddx", "shsax">;
4979 def : MnemonicAlias<"ssubaddx", "ssax">;
4981 def : MnemonicAlias<"uaddsubx", "uasx">;
4982 // UHASX == UHADDSUBX
4983 def : MnemonicAlias<"uhaddsubx", "uhasx">;
4984 // UHSAX == UHSUBADDX
4985 def : MnemonicAlias<"uhsubaddx", "uhsax">;
4986 // UQASX == UQADDSUBX
4987 def : MnemonicAlias<"uqaddsubx", "uqasx">;
4988 // UQSAX == UQSUBADDX
4989 def : MnemonicAlias<"uqsubaddx", "uqsax">;
4991 def : MnemonicAlias<"usubaddx", "usax">;
4993 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
4995 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
4996 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;