1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file describes the ARM instructions in TableGen format.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // ARM specific DAG Nodes.
20 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
21 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
23 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
25 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
27 def SDT_ARMCMov : SDTypeProfile<1, 3,
28 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
31 def SDT_ARMBrcond : SDTypeProfile<0, 2,
32 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
34 def SDT_ARMBrJT : SDTypeProfile<0, 3,
35 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
38 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
40 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
41 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
43 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
46 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
47 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
49 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
50 [SDNPHasChain, SDNPOutFlag]>;
51 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
52 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
54 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
55 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
56 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
57 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
58 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
59 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
61 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTRet,
62 [SDNPHasChain, SDNPOptInFlag]>;
64 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
66 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
69 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
70 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
72 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
75 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
78 def ARMcmpNZ : SDNode<"ARMISD::CMPNZ", SDT_ARMCmp,
81 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
83 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
84 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
85 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
87 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
89 //===----------------------------------------------------------------------===//
90 // ARM Instruction Predicate Definitions.
92 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
93 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
94 def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
95 def IsThumb : Predicate<"Subtarget->isThumb()">;
96 def IsARM : Predicate<"!Subtarget->isThumb()">;
98 //===----------------------------------------------------------------------===//
99 // ARM Flag Definitions.
101 class RegConstraint<string C> {
102 string Constraints = C;
105 //===----------------------------------------------------------------------===//
106 // ARM specific transformation functions and pattern fragments.
109 // so_imm_XFORM - Return a so_imm value packed into the format described for
111 def so_imm_XFORM : SDNodeXForm<imm, [{
112 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(N->getValue()),
116 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
117 // so_imm_neg def below.
118 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
119 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(-(int)N->getValue()),
123 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
124 // so_imm_not def below.
125 def so_imm_not_XFORM : SDNodeXForm<imm, [{
126 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(~(int)N->getValue()),
130 // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
131 def rot_imm : PatLeaf<(i32 imm), [{
132 int32_t v = (int32_t)N->getValue();
133 return v == 8 || v == 16 || v == 24;
136 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
137 def imm1_15 : PatLeaf<(i32 imm), [{
138 return (int32_t)N->getValue() >= 1 && (int32_t)N->getValue() < 16;
141 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
142 def imm16_31 : PatLeaf<(i32 imm), [{
143 return (int32_t)N->getValue() >= 16 && (int32_t)N->getValue() < 32;
147 PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(-(int)N->getValue()) != -1; }],
151 PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(~(int)N->getValue()) != -1; }],
154 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
155 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
156 return CurDAG->ComputeNumSignBits(SDOperand(N,0)) >= 17;
161 //===----------------------------------------------------------------------===//
162 // Operand Definitions.
166 def brtarget : Operand<OtherVT>;
168 // A list of registers separated by comma. Used by load/store multiple.
169 def reglist : Operand<i32> {
170 let PrintMethod = "printRegisterList";
173 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
174 def cpinst_operand : Operand<i32> {
175 let PrintMethod = "printCPInstOperand";
178 def jtblock_operand : Operand<i32> {
179 let PrintMethod = "printJTBlockOperand";
183 def pclabel : Operand<i32> {
184 let PrintMethod = "printPCLabel";
187 // shifter_operand operands: so_reg and so_imm.
188 def so_reg : Operand<i32>, // reg reg imm
189 ComplexPattern<i32, 3, "SelectShifterOperandReg",
190 [shl,srl,sra,rotr]> {
191 let PrintMethod = "printSORegOperand";
192 let MIOperandInfo = (ops GPR, GPR, i32imm);
195 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
196 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
197 // represented in the imm field in the same 12-bit form that they are encoded
198 // into so_imm instructions: the 8-bit immediate is the least significant bits
199 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
200 def so_imm : Operand<i32>,
202 [{ return ARM_AM::getSOImmVal(N->getValue()) != -1; }],
204 let PrintMethod = "printSOImmOperand";
207 // Break so_imm's up into two pieces. This handles immediates with up to 16
208 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
209 // get the first/second pieces.
210 def so_imm2part : Operand<i32>,
212 [{ return ARM_AM::isSOImmTwoPartVal((unsigned)N->getValue()); }]> {
213 let PrintMethod = "printSOImm2PartOperand";
216 def so_imm2part_1 : SDNodeXForm<imm, [{
217 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getValue());
218 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
221 def so_imm2part_2 : SDNodeXForm<imm, [{
222 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getValue());
223 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
227 // Define ARM specific addressing modes.
229 // addrmode2 := reg +/- reg shop imm
230 // addrmode2 := reg +/- imm12
232 def addrmode2 : Operand<i32>,
233 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
234 let PrintMethod = "printAddrMode2Operand";
235 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
238 def am2offset : Operand<i32>,
239 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
240 let PrintMethod = "printAddrMode2OffsetOperand";
241 let MIOperandInfo = (ops GPR, i32imm);
244 // addrmode3 := reg +/- reg
245 // addrmode3 := reg +/- imm8
247 def addrmode3 : Operand<i32>,
248 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
249 let PrintMethod = "printAddrMode3Operand";
250 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
253 def am3offset : Operand<i32>,
254 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
255 let PrintMethod = "printAddrMode3OffsetOperand";
256 let MIOperandInfo = (ops GPR, i32imm);
259 // addrmode4 := reg, <mode|W>
261 def addrmode4 : Operand<i32>,
262 ComplexPattern<i32, 2, "", []> {
263 let PrintMethod = "printAddrMode4Operand";
264 let MIOperandInfo = (ops GPR, i32imm);
267 // addrmode5 := reg +/- imm8*4
269 def addrmode5 : Operand<i32>,
270 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
271 let PrintMethod = "printAddrMode5Operand";
272 let MIOperandInfo = (ops GPR, i32imm);
275 // addrmodepc := pc + reg
277 def addrmodepc : Operand<i32>,
278 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
279 let PrintMethod = "printAddrModePCOperand";
280 let MIOperandInfo = (ops GPR, i32imm);
283 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
284 // register whose default is 0 (no register).
285 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
286 (ops (i32 14), (i32 zero_reg))> {
287 let PrintMethod = "printPredicateOperand";
290 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
292 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
293 let PrintMethod = "printSBitModifierOperand";
296 //===----------------------------------------------------------------------===//
297 // ARM Instruction flags. These need to match ARMInstrInfo.h.
301 class AddrMode<bits<4> val> {
304 def AddrModeNone : AddrMode<0>;
305 def AddrMode1 : AddrMode<1>;
306 def AddrMode2 : AddrMode<2>;
307 def AddrMode3 : AddrMode<3>;
308 def AddrMode4 : AddrMode<4>;
309 def AddrMode5 : AddrMode<5>;
310 def AddrModeT1 : AddrMode<6>;
311 def AddrModeT2 : AddrMode<7>;
312 def AddrModeT4 : AddrMode<8>;
313 def AddrModeTs : AddrMode<9>;
316 class SizeFlagVal<bits<3> val> {
319 def SizeInvalid : SizeFlagVal<0>; // Unset.
320 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
321 def Size8Bytes : SizeFlagVal<2>;
322 def Size4Bytes : SizeFlagVal<3>;
323 def Size2Bytes : SizeFlagVal<4>;
325 // Load / store index mode.
326 class IndexMode<bits<2> val> {
329 def IndexModeNone : IndexMode<0>;
330 def IndexModePre : IndexMode<1>;
331 def IndexModePost : IndexMode<2>;
333 //===----------------------------------------------------------------------===//
334 // ARM Instruction Format Definitions.
337 // Format specifies the encoding used by the instruction. This is part of the
338 // ad-hoc solution used to emit machine instruction encodings by our machine
340 class Format<bits<5> val> {
344 def Pseudo : Format<1>;
345 def MulFrm : Format<2>;
346 def MulSMLAW : Format<3>;
347 def MulSMULW : Format<4>;
348 def MulSMLA : Format<5>;
349 def MulSMUL : Format<6>;
350 def Branch : Format<7>;
351 def BranchMisc : Format<8>;
353 def DPRdIm : Format<9>;
354 def DPRdReg : Format<10>;
355 def DPRdSoReg : Format<11>;
356 def DPRdMisc : Format<12>;
357 def DPRnIm : Format<13>;
358 def DPRnReg : Format<14>;
359 def DPRnSoReg : Format<15>;
360 def DPRIm : Format<16>;
361 def DPRReg : Format<17>;
362 def DPRSoReg : Format<18>;
363 def DPRImS : Format<19>;
364 def DPRRegS : Format<20>;
365 def DPRSoRegS : Format<21>;
367 def LdFrm : Format<22>;
368 def StFrm : Format<23>;
370 def ArithMisc : Format<24>;
371 def ThumbFrm : Format<25>;
372 def VFPFrm : Format<26>;
376 //===----------------------------------------------------------------------===//
378 // ARM Instruction templates.
381 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
382 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
383 list<Predicate> Predicates = [IsARM];
385 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
386 list<Predicate> Predicates = [IsARM, HasV5TE];
388 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
389 list<Predicate> Predicates = [IsARM, HasV6];
392 class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im,
393 Format f, string cstr>
395 let Namespace = "ARM";
397 bits<4> Opcode = opcod;
399 bits<4> AddrModeBits = AM.Value;
402 bits<3> SizeFlag = SZ.Value;
405 bits<2> IndexModeBits = IM.Value;
408 bits<5> Form = F.Value;
410 let Constraints = cstr;
413 class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern>
414 : InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> {
415 let OutOperandList = oops;
416 let InOperandList = iops;
418 let Pattern = pattern;
421 // Almost all ARM instructions are predicable.
422 class I<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
423 IndexMode im, Format f, string opc, string asm, string cstr,
425 : InstARM<opcod, am, sz, im, f, cstr> {
426 let OutOperandList = oops;
427 let InOperandList = !con(iops, (ops pred:$p));
428 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
429 let Pattern = pattern;
430 list<Predicate> Predicates = [IsARM];
433 // Same as I except it can optionally modify CPSR. Note it's modeled as
434 // an input operand since by default it's a zero register. It will
435 // become an implicit def once it's "flipped".
436 class sI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
437 IndexMode im, Format f, string opc, string asm, string cstr,
439 : InstARM<opcod, am, sz, im, f, cstr> {
440 let OutOperandList = oops;
441 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
442 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
443 let Pattern = pattern;
444 list<Predicate> Predicates = [IsARM];
447 class AI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
448 string asm, list<dag> pattern>
449 : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
451 class AsI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
452 string asm, list<dag> pattern>
453 : sI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
455 class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
456 string asm, list<dag> pattern>
457 : I<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
459 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
460 string asm, list<dag> pattern>
461 : sI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
463 class AI2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
464 string asm, list<dag> pattern>
465 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
467 class AI3<bits<4> opcod, dag oops, dag iops, Format f, string opc,
468 string asm, list<dag> pattern>
469 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
471 class AI4<bits<4> opcod, dag oops, dag iops, Format f, string opc,
472 string asm, list<dag> pattern>
473 : I<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, opc,
475 class AI1x2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
476 string asm, list<dag> pattern>
477 : I<opcod, oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc,
481 class AI2pr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
482 string asm, string cstr, list<dag> pattern>
483 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
485 class AI3pr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
486 string asm, string cstr, list<dag> pattern>
487 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
491 class AI2po<bits<4> opcod, dag oops, dag iops, Format f, string opc,
492 string asm, string cstr, list<dag> pattern>
493 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
495 class AI3po<bits<4> opcod, dag oops, dag iops, Format f, string opc,
496 string asm, string cstr, list<dag> pattern>
497 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
501 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
502 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
505 /// AI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
506 /// binop that produces a value.
507 multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode> {
508 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm,
509 opc, " $dst, $a, $b",
510 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
511 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPRReg,
512 opc, " $dst, $a, $b",
513 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
514 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg,
515 opc, " $dst, $a, $b",
516 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
519 /// ASI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
520 /// instruction modifies the CSPR register.
521 let Defs = [CPSR] in {
522 multiclass ASI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode> {
523 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRImS,
524 opc, "s $dst, $a, $b",
525 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
526 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPRRegS,
527 opc, "s $dst, $a, $b",
528 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
529 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoRegS,
530 opc, "s $dst, $a, $b",
531 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
535 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
536 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
537 /// a explicit result, only implicitly set CPSR.
538 let Defs = [CPSR] in {
539 multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> {
540 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPRnIm,
542 [(opnode GPR:$a, so_imm:$b)]>;
543 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPRnReg,
545 [(opnode GPR:$a, GPR:$b)]>;
546 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPRnSoReg,
548 [(opnode GPR:$a, so_reg:$b)]>;
552 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
553 /// register and one whose operand is a register rotated by 8/16/24.
554 multiclass AI_unary_rrot<bits<4> opcod, string opc, PatFrag opnode> {
555 def r : AI<opcod, (outs GPR:$dst), (ins GPR:$Src), Pseudo,
557 [(set GPR:$dst, (opnode GPR:$Src))]>, Requires<[IsARM, HasV6]>;
558 def r_rot : AI<opcod, (outs GPR:$dst), (ins GPR:$Src, i32imm:$rot), Pseudo,
559 opc, " $dst, $Src, ror $rot",
560 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>,
561 Requires<[IsARM, HasV6]>;
564 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
565 /// register and one whose operand is a register rotated by 8/16/24.
566 multiclass AI_bin_rrot<bits<4> opcod, string opc, PatFrag opnode> {
567 def rr : AI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
568 Pseudo, opc, " $dst, $LHS, $RHS",
569 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
570 Requires<[IsARM, HasV6]>;
571 def rr_rot : AI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
572 Pseudo, opc, " $dst, $LHS, $RHS, ror $rot",
573 [(set GPR:$dst, (opnode GPR:$LHS,
574 (rotr GPR:$RHS, rot_imm:$rot)))]>,
575 Requires<[IsARM, HasV6]>;
579 class XI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
580 IndexMode im, Format f, string asm, string cstr, list<dag> pattern>
581 : InstARM<opcod, am, sz, im, f, cstr> {
582 let OutOperandList = oops;
583 let InOperandList = iops;
585 let Pattern = pattern;
586 list<Predicate> Predicates = [IsARM];
589 class AXI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
591 : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
593 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm,
595 : XI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm,
597 class AXI2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
599 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
601 class AXI3<bits<4> opcod, dag oops, dag iops, Format f, string asm,
603 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
605 class AXI4<bits<4> opcod, dag oops, dag iops, Format f, string asm,
607 : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
610 class AXIx2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
612 : XI<opcod, oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, f, asm,
615 // BR_JT instructions
616 class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
617 : XI<opcod, oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BranchMisc,
619 class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
620 : XI<opcod, oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BranchMisc,
622 class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
623 : XI<opcod, oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BranchMisc,
626 /// AsXI1_bin_c_irs - Same as AsI1_bin_irs but without the predicate operand and
627 /// setting carry bit. But it can optionally set CPSR.
628 let Uses = [CPSR] in {
629 multiclass AsXI1_bin_c_irs<bits<4> opcod, string opc, PatFrag opnode> {
630 def ri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
631 DPRIm, !strconcat(opc, "${s} $dst, $a, $b"),
632 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
633 def rr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, cc_out:$s),
634 DPRReg, !strconcat(opc, "${s} $dst, $a, $b"),
635 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
636 def rs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
637 DPRSoReg, !strconcat(opc, "${s} $dst, $a, $b"),
638 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
642 //===----------------------------------------------------------------------===//
644 //===----------------------------------------------------------------------===//
646 //===----------------------------------------------------------------------===//
647 // Miscellaneous Instructions.
649 def IMPLICIT_DEF_GPR :
650 PseudoInst<(outs GPR:$rD), (ins pred:$p),
651 "@ IMPLICIT_DEF_GPR $rD",
652 [(set GPR:$rD, (undef))]>;
655 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
656 /// the function. The first operand is the ID# for this instruction, the second
657 /// is the index into the MachineConstantPool that this is, the third is the
658 /// size in bytes of this constant pool entry.
659 let isNotDuplicable = 1 in
660 def CONSTPOOL_ENTRY :
661 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
663 "${instid:label} ${cpidx:cpentry}", []>;
665 let Defs = [SP], Uses = [SP] in {
667 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p),
668 "@ ADJCALLSTACKUP $amt1",
669 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>;
671 def ADJCALLSTACKDOWN :
672 PseudoInst<(outs), (ins i32imm:$amt, pred:$p),
673 "@ ADJCALLSTACKDOWN $amt",
674 [(ARMcallseq_start imm:$amt)]>;
678 PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
679 ".loc $file, $line, $col",
680 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
682 let isNotDuplicable = 1 in {
683 def PICADD : AXI1<0x0, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
684 Pseudo, "$cp:\n\tadd$p $dst, pc, $a",
685 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
687 let isLoad = 1, AddedComplexity = 10 in {
688 def PICLD : AXI2<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
689 Pseudo, "${addr:label}:\n\tldr$p $dst, $addr",
690 [(set GPR:$dst, (load addrmodepc:$addr))]>;
692 def PICLDZH : AXI3<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
693 Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr",
694 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
696 def PICLDZB : AXI2<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
697 Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr",
698 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
700 def PICLDH : AXI3<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
701 Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr",
702 [(set GPR:$dst, (extloadi16 addrmodepc:$addr))]>;
704 def PICLDB : AXI2<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
705 Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr",
706 [(set GPR:$dst, (extloadi8 addrmodepc:$addr))]>;
708 def PICLDSH : AXI3<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
709 Pseudo, "${addr:label}:\n\tldr${p}sh $dst, $addr",
710 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
712 def PICLDSB : AXI3<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
713 Pseudo, "${addr:label}:\n\tldr${p}sb $dst, $addr",
714 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
716 let isStore = 1, AddedComplexity = 10 in {
717 def PICSTR : AXI2<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
718 Pseudo, "${addr:label}:\n\tstr$p $src, $addr",
719 [(store GPR:$src, addrmodepc:$addr)]>;
721 def PICSTRH : AXI3<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
722 Pseudo, "${addr:label}:\n\tstr${p}h $src, $addr",
723 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
725 def PICSTRB : AXI2<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
726 Pseudo, "${addr:label}:\n\tstr${p}b $src, $addr",
727 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
731 //===----------------------------------------------------------------------===//
732 // Control Flow Instructions.
735 let isReturn = 1, isTerminator = 1 in
736 def BX_RET : AI<0x1, (outs), (ins), BranchMisc, "bx", " lr", [(ARMretflag)]>;
738 // FIXME: remove when we have a way to marking a MI with these properties.
739 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
741 let isLoad = 1, isReturn = 1, isTerminator = 1 in
742 def LDM_RET : AXI4<0x0, (outs),
743 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
744 LdFrm, "ldm${p}${addr:submode} $addr, $dst1",
748 Defs = [R0, R1, R2, R3, R12, LR,
749 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
750 def BL : AXI<0xB, (outs), (ins i32imm:$func, variable_ops), Branch,
752 [(ARMcall tglobaladdr:$func)]>;
754 def BL_pred : AI<0xB, (outs), (ins i32imm:$func, variable_ops),
755 Branch, "bl", " ${func:call}",
756 [(ARMcall_pred tglobaladdr:$func)]>;
759 def BLX : AXI<0x2, (outs), (ins GPR:$func, variable_ops), BranchMisc,
761 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T]>;
764 def BX : AXIx2<0x0, (outs), (ins GPR:$func, variable_ops),
765 BranchMisc, "mov lr, pc\n\tbx $func",
766 [(ARMcall_nolink GPR:$func)]>;
770 let isBranch = 1, isTerminator = 1 in {
771 // B is "predicable" since it can be xformed into a Bcc.
772 let isBarrier = 1 in {
773 let isPredicable = 1 in
774 def B : AXI<0xA, (outs), (ins brtarget:$target), Branch, "b $target",
777 let isNotDuplicable = 1, isIndirectBranch = 1 in {
778 def BR_JTr : JTI<0x0, (outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
779 "mov pc, $target \n$jt",
780 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
781 def BR_JTm : JTI2<0x0, (outs), (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
782 "ldr pc, $target \n$jt",
783 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
785 def BR_JTadd : JTI1<0x0, (outs), (ins GPR:$target, GPR:$idx, jtblock_operand:$jt,
787 "add pc, $target, $idx \n$jt",
788 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
793 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
794 // a two-value operand where a dag node expects two operands. :(
795 def Bcc : AI<0xA, (outs), (ins brtarget:$target), Branch,
797 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
800 //===----------------------------------------------------------------------===//
801 // Load / store Instructions.
806 def LDR : AI2<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
807 "ldr", " $dst, $addr",
808 [(set GPR:$dst, (load addrmode2:$addr))]>;
810 // Special LDR for loads from non-pc-relative constpools.
811 let isReMaterializable = 1 in
812 def LDRcp : AI2<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
813 "ldr", " $dst, $addr", []>;
815 // Loads with zero extension
816 def LDRH : AI3<0xB, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
817 "ldr", "h $dst, $addr",
818 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
820 def LDRB : AI2<0x1, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
821 "ldr", "b $dst, $addr",
822 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
824 // Loads with sign extension
825 def LDRSH : AI3<0xE, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
826 "ldr", "sh $dst, $addr",
827 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
829 def LDRSB : AI3<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
830 "ldr", "sb $dst, $addr",
831 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
834 def LDRD : AI3<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
835 "ldr", "d $dst, $addr",
836 []>, Requires<[IsARM, HasV5T]>;
839 def LDR_PRE : AI2pr<0x0, (outs GPR:$dst, GPR:$base_wb),
840 (ins addrmode2:$addr), LdFrm,
841 "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>;
843 def LDR_POST : AI2po<0x0, (outs GPR:$dst, GPR:$base_wb),
844 (ins GPR:$base, am2offset:$offset), LdFrm,
845 "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>;
847 def LDRH_PRE : AI3pr<0xB, (outs GPR:$dst, GPR:$base_wb),
848 (ins addrmode3:$addr), LdFrm,
849 "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>;
851 def LDRH_POST : AI3po<0xB, (outs GPR:$dst, GPR:$base_wb),
852 (ins GPR:$base,am3offset:$offset), LdFrm,
853 "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>;
855 def LDRB_PRE : AI2pr<0x1, (outs GPR:$dst, GPR:$base_wb),
856 (ins addrmode2:$addr), LdFrm,
857 "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>;
859 def LDRB_POST : AI2po<0x1, (outs GPR:$dst, GPR:$base_wb),
860 (ins GPR:$base,am2offset:$offset), LdFrm,
861 "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>;
863 def LDRSH_PRE : AI3pr<0xE, (outs GPR:$dst, GPR:$base_wb),
864 (ins addrmode3:$addr), LdFrm,
865 "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>;
867 def LDRSH_POST: AI3po<0xE, (outs GPR:$dst, GPR:$base_wb),
868 (ins GPR:$base,am3offset:$offset), LdFrm,
869 "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>;
871 def LDRSB_PRE : AI3pr<0xD, (outs GPR:$dst, GPR:$base_wb),
872 (ins addrmode3:$addr), LdFrm,
873 "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>;
875 def LDRSB_POST: AI3po<0xD, (outs GPR:$dst, GPR:$base_wb),
876 (ins GPR:$base,am3offset:$offset), LdFrm,
877 "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
882 def STR : AI2<0x0, (outs), (ins GPR:$src, addrmode2:$addr), StFrm,
883 "str", " $src, $addr",
884 [(store GPR:$src, addrmode2:$addr)]>;
886 // Stores with truncate
887 def STRH : AI3<0xB, (outs), (ins GPR:$src, addrmode3:$addr), StFrm,
888 "str", "h $src, $addr",
889 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
891 def STRB : AI2<0x1, (outs), (ins GPR:$src, addrmode2:$addr), StFrm,
892 "str", "b $src, $addr",
893 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
896 def STRD : AI3<0xF, (outs), (ins GPR:$src, addrmode3:$addr), StFrm,
897 "str", "d $src, $addr",
898 []>, Requires<[IsARM, HasV5T]>;
901 def STR_PRE : AI2pr<0x0, (outs GPR:$base_wb),
902 (ins GPR:$src, GPR:$base, am2offset:$offset), StFrm,
903 "str", " $src, [$base, $offset]!", "$base = $base_wb",
905 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
907 def STR_POST : AI2po<0x0, (outs GPR:$base_wb),
908 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
909 "str", " $src, [$base], $offset", "$base = $base_wb",
911 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
913 def STRH_PRE : AI3pr<0xB, (outs GPR:$base_wb),
914 (ins GPR:$src, GPR:$base,am3offset:$offset), StFrm,
915 "str", "h $src, [$base, $offset]!", "$base = $base_wb",
917 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
919 def STRH_POST: AI3po<0xB, (outs GPR:$base_wb),
920 (ins GPR:$src, GPR:$base,am3offset:$offset), StFrm,
921 "str", "h $src, [$base], $offset", "$base = $base_wb",
922 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
923 GPR:$base, am3offset:$offset))]>;
925 def STRB_PRE : AI2pr<0x1, (outs GPR:$base_wb),
926 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
927 "str", "b $src, [$base, $offset]!", "$base = $base_wb",
928 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
929 GPR:$base, am2offset:$offset))]>;
931 def STRB_POST: AI2po<0x1, (outs GPR:$base_wb),
932 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
933 "str", "b $src, [$base], $offset", "$base = $base_wb",
934 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
935 GPR:$base, am2offset:$offset))]>;
938 //===----------------------------------------------------------------------===//
939 // Load / store multiple Instructions.
942 // FIXME: $dst1 should be a def.
944 def LDM : AXI4<0x0, (outs),
945 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
946 LdFrm, "ldm${p}${addr:submode} $addr, $dst1",
950 def STM : AXI4<0x0, (outs),
951 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
952 StFrm, "stm${p}${addr:submode} $addr, $src1",
955 //===----------------------------------------------------------------------===//
956 // Move Instructions.
959 def MOVr : AsI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdReg,
960 "mov", " $dst, $src", []>;
961 def MOVs : AsI1<0xD, (outs GPR:$dst), (ins so_reg:$src), DPRdSoReg,
962 "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>;
964 let isReMaterializable = 1 in
965 def MOVi : AsI1<0xD, (outs GPR:$dst), (ins so_imm:$src), DPRdIm,
966 "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>;
968 def MOVrx : AsI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc,
969 "mov", " $dst, $src, rrx",
970 [(set GPR:$dst, (ARMrrx GPR:$src))]>;
972 // These aren't really mov instructions, but we have to define them this way
973 // due to flag operands.
975 let Defs = [CPSR] in {
976 def MOVsrl_flag : AI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc,
977 "mov", "s $dst, $src, lsr #1",
978 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>;
979 def MOVsra_flag : AI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc,
980 "mov", "s $dst, $src, asr #1",
981 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>;
984 //===----------------------------------------------------------------------===//
985 // Extend Instructions.
990 defm SXTB : AI_unary_rrot<0x0, "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
991 defm SXTH : AI_unary_rrot<0x0, "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
993 defm SXTAB : AI_bin_rrot<0x0, "sxtab",
994 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
995 defm SXTAH : AI_bin_rrot<0x0, "sxtah",
996 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
998 // TODO: SXT(A){B|H}16
1002 let AddedComplexity = 16 in {
1003 defm UXTB : AI_unary_rrot<0x0, "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
1004 defm UXTH : AI_unary_rrot<0x0, "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1005 defm UXTB16 : AI_unary_rrot<0x0, "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1007 def : ARMV6Pat<(and (shl GPR:$Src, 8), 0xFF00FF),
1008 (UXTB16r_rot GPR:$Src, 24)>;
1009 def : ARMV6Pat<(and (srl GPR:$Src, 8), 0xFF00FF),
1010 (UXTB16r_rot GPR:$Src, 8)>;
1012 defm UXTAB : AI_bin_rrot<0x0, "uxtab",
1013 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1014 defm UXTAH : AI_bin_rrot<0x0, "uxtah",
1015 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1018 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
1019 //defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
1021 // TODO: UXT(A){B|H}16
1023 //===----------------------------------------------------------------------===//
1024 // Arithmetic Instructions.
1027 defm ADD : AsI1_bin_irs<0x4, "add", BinOpFrag<(add node:$LHS, node:$RHS)>>;
1028 defm SUB : AsI1_bin_irs<0x2, "sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1030 // ADD and SUB with 's' bit set.
1031 defm ADDS : ASI1_bin_s_irs<0x4, "add", BinOpFrag<(addc node:$LHS, node:$RHS)>>;
1032 defm SUBS : ASI1_bin_s_irs<0x2, "sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1034 // FIXME: Do not allow ADC / SBC to be predicated for now.
1035 defm ADC : AsXI1_bin_c_irs<0x5, "adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>;
1036 defm SBC : AsXI1_bin_c_irs<0x6, "sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
1038 // These don't define reg/reg forms, because they are handled above.
1039 def RSBri : AsI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm,
1040 "rsb", " $dst, $a, $b",
1041 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>;
1043 def RSBrs : AsI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg,
1044 "rsb", " $dst, $a, $b",
1045 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>;
1047 // RSB with 's' bit set.
1048 let Defs = [CPSR] in {
1049 def RSBSri : AI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm,
1050 "rsb", "s $dst, $a, $b",
1051 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>;
1052 def RSBSrs : AI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg,
1053 "rsb", "s $dst, $a, $b",
1054 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>;
1057 // FIXME: Do not allow RSC to be predicated for now. But they can set CPSR.
1058 let Uses = [CPSR] in {
1059 def RSCri : AXI1<0x7, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
1060 DPRIm, "rsc${s} $dst, $a, $b",
1061 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>;
1062 def RSCrs : AXI1<0x7, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
1063 DPRSoReg, "rsc${s} $dst, $a, $b",
1064 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>;
1067 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1068 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
1069 (SUBri GPR:$src, so_imm_neg:$imm)>;
1071 //def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
1072 // (SUBSri GPR:$src, so_imm_neg:$imm)>;
1073 //def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
1074 // (SBCri GPR:$src, so_imm_neg:$imm)>;
1076 // Note: These are implemented in C++ code, because they have to generate
1077 // ADD/SUBrs instructions, which use a complex pattern that a xform function
1079 // (mul X, 2^n+1) -> (add (X << n), X)
1080 // (mul X, 2^n-1) -> (rsb X, (X << n))
1083 //===----------------------------------------------------------------------===//
1084 // Bitwise Instructions.
1087 defm AND : AsI1_bin_irs<0x0, "and", BinOpFrag<(and node:$LHS, node:$RHS)>>;
1088 defm ORR : AsI1_bin_irs<0xC, "orr", BinOpFrag<(or node:$LHS, node:$RHS)>>;
1089 defm EOR : AsI1_bin_irs<0x1, "eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>;
1090 defm BIC : AsI1_bin_irs<0xE, "bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1092 def MVNr : AsI<0xE, (outs GPR:$dst), (ins GPR:$src), DPRdReg,
1093 "mvn", " $dst, $src", [(set GPR:$dst, (not GPR:$src))]>;
1094 def MVNs : AsI<0xE, (outs GPR:$dst), (ins so_reg:$src), DPRdSoReg,
1095 "mvn", " $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>;
1096 let isReMaterializable = 1 in
1097 def MVNi : AsI<0xE, (outs GPR:$dst), (ins so_imm:$imm), DPRdIm,
1098 "mvn", " $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>;
1100 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
1101 (BICri GPR:$src, so_imm_not:$imm)>;
1103 //===----------------------------------------------------------------------===//
1104 // Multiply Instructions.
1107 def MUL : AsI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,
1108 "mul", " $dst, $a, $b",
1109 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
1111 def MLA : AsI<0x2, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1112 MulFrm, "mla", " $dst, $a, $b, $c",
1113 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
1115 // Extra precision multiplies with low / high results
1116 def SMULL : AsI<0xC, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
1117 MulFrm, "smull", " $ldst, $hdst, $a, $b", []>;
1119 def UMULL : AsI<0x8, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
1120 MulFrm, "umull", " $ldst, $hdst, $a, $b", []>;
1122 // Multiply + accumulate
1123 def SMLAL : AsI<0xE, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
1124 MulFrm, "smlal", " $ldst, $hdst, $a, $b", []>;
1126 def UMLAL : AsI<0xA, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
1127 MulFrm, "umlal", " $ldst, $hdst, $a, $b", []>;
1129 def UMAAL : AI<0x0, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), MulFrm,
1130 "umaal", " $ldst, $hdst, $a, $b", []>,
1131 Requires<[IsARM, HasV6]>;
1133 // Most significant word multiply
1134 def SMMUL : AI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,
1135 "smmul", " $dst, $a, $b",
1136 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
1137 Requires<[IsARM, HasV6]>;
1139 def SMMLA : AI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), MulFrm,
1140 "smmla", " $dst, $a, $b, $c",
1141 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
1142 Requires<[IsARM, HasV6]>;
1145 def SMMLS : AI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), MulFrm,
1146 "smmls", " $dst, $a, $b, $c",
1147 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
1148 Requires<[IsARM, HasV6]>;
1150 multiclass AI_smul<string opc, PatFrag opnode> {
1151 def BB : AI<0x8, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,
1152 !strconcat(opc, "bb"), " $dst, $a, $b",
1153 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1154 (sext_inreg GPR:$b, i16)))]>,
1155 Requires<[IsARM, HasV5TE]>;
1157 def BT : AI<0xC, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,
1158 !strconcat(opc, "bt"), " $dst, $a, $b",
1159 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1160 (sra GPR:$b, 16)))]>,
1161 Requires<[IsARM, HasV5TE]>;
1163 def TB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,
1164 !strconcat(opc, "tb"), " $dst, $a, $b",
1165 [(set GPR:$dst, (opnode (sra GPR:$a, 16),
1166 (sext_inreg GPR:$b, i16)))]>,
1167 Requires<[IsARM, HasV5TE]>;
1169 def TT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,
1170 !strconcat(opc, "tt"), " $dst, $a, $b",
1171 [(set GPR:$dst, (opnode (sra GPR:$a, 16),
1172 (sra GPR:$b, 16)))]>,
1173 Requires<[IsARM, HasV5TE]>;
1175 def WB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMULW,
1176 !strconcat(opc, "wb"), " $dst, $a, $b",
1177 [(set GPR:$dst, (sra (opnode GPR:$a,
1178 (sext_inreg GPR:$b, i16)), 16))]>,
1179 Requires<[IsARM, HasV5TE]>;
1181 def WT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMULW,
1182 !strconcat(opc, "wt"), " $dst, $a, $b",
1183 [(set GPR:$dst, (sra (opnode GPR:$a,
1184 (sra GPR:$b, 16)), 16))]>,
1185 Requires<[IsARM, HasV5TE]>;
1189 multiclass AI_smla<string opc, PatFrag opnode> {
1190 def BB : AI<0x8, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,
1191 !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
1192 [(set GPR:$dst, (add GPR:$acc,
1193 (opnode (sext_inreg GPR:$a, i16),
1194 (sext_inreg GPR:$b, i16))))]>,
1195 Requires<[IsARM, HasV5TE]>;
1197 def BT : AI<0xC, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,
1198 !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
1199 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1200 (sra GPR:$b, 16))))]>,
1201 Requires<[IsARM, HasV5TE]>;
1203 def TB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,
1204 !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
1205 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
1206 (sext_inreg GPR:$b, i16))))]>,
1207 Requires<[IsARM, HasV5TE]>;
1209 def TT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,
1210 !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
1211 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
1212 (sra GPR:$b, 16))))]>,
1213 Requires<[IsARM, HasV5TE]>;
1215 def WB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLAW,
1216 !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
1217 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1218 (sext_inreg GPR:$b, i16)), 16)))]>,
1219 Requires<[IsARM, HasV5TE]>;
1221 def WT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLAW,
1222 !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
1223 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1224 (sra GPR:$b, 16)), 16)))]>,
1225 Requires<[IsARM, HasV5TE]>;
1228 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1229 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1231 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
1232 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1234 //===----------------------------------------------------------------------===//
1235 // Misc. Arithmetic Instructions.
1238 def CLZ : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc,
1239 "clz", " $dst, $src",
1240 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]>;
1242 def REV : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc,
1243 "rev", " $dst, $src",
1244 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]>;
1246 def REV16 : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc,
1247 "rev16", " $dst, $src",
1249 (or (and (srl GPR:$src, 8), 0xFF),
1250 (or (and (shl GPR:$src, 8), 0xFF00),
1251 (or (and (srl GPR:$src, 8), 0xFF0000),
1252 (and (shl GPR:$src, 8), 0xFF000000)))))]>,
1253 Requires<[IsARM, HasV6]>;
1255 def REVSH : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc,
1256 "revsh", " $dst, $src",
1259 (or (srl (and GPR:$src, 0xFF00), 8),
1260 (shl GPR:$src, 8)), i16))]>,
1261 Requires<[IsARM, HasV6]>;
1263 def PKHBT : AI<0x0, (outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1264 Pseudo, "pkhbt", " $dst, $src1, $src2, LSL $shamt",
1265 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1266 (and (shl GPR:$src2, (i32 imm:$shamt)),
1268 Requires<[IsARM, HasV6]>;
1270 // Alternate cases for PKHBT where identities eliminate some nodes.
1271 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1272 (PKHBT GPR:$src1, GPR:$src2, 0)>;
1273 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1274 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1277 def PKHTB : AI<0x0, (outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1278 Pseudo, "pkhtb", " $dst, $src1, $src2, ASR $shamt",
1279 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1280 (and (sra GPR:$src2, imm16_31:$shamt),
1281 0xFFFF)))]>, Requires<[IsARM, HasV6]>;
1283 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
1284 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1285 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, 16)),
1286 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1287 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1288 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1289 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1292 //===----------------------------------------------------------------------===//
1293 // Comparison Instructions...
1296 defm CMP : AI1_cmp_irs<0xA, "cmp",
1297 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1298 defm CMN : AI1_cmp_irs<0xB, "cmn",
1299 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1301 // Note that TST/TEQ don't set all the same flags that CMP does!
1302 defm TST : AI1_cmp_irs<0x8, "tst",
1303 BinOpFrag<(ARMcmpNZ (and node:$LHS, node:$RHS), 0)>>;
1304 defm TEQ : AI1_cmp_irs<0x9, "teq",
1305 BinOpFrag<(ARMcmpNZ (xor node:$LHS, node:$RHS), 0)>>;
1307 defm CMPnz : AI1_cmp_irs<0xA, "cmp",
1308 BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>;
1309 defm CMNnz : AI1_cmp_irs<0xA, "cmn",
1310 BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>;
1312 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1313 (CMNri GPR:$src, so_imm_neg:$imm)>;
1315 def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm),
1316 (CMNri GPR:$src, so_imm_neg:$imm)>;
1319 // Conditional moves
1320 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1321 // a two-value operand where a dag node expects two operands. :(
1322 def MOVCCr : AI<0xD, (outs GPR:$dst), (ins GPR:$false, GPR:$true),
1323 DPRdReg, "mov", " $dst, $true",
1324 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1325 RegConstraint<"$false = $dst">;
1327 def MOVCCs : AI<0xD, (outs GPR:$dst), (ins GPR:$false, so_reg:$true),
1328 DPRdSoReg, "mov", " $dst, $true",
1329 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
1330 RegConstraint<"$false = $dst">;
1332 def MOVCCi : AI<0xD, (outs GPR:$dst), (ins GPR:$false, so_imm:$true),
1333 DPRdIm, "mov", " $dst, $true",
1334 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1335 RegConstraint<"$false = $dst">;
1338 // LEApcrel - Load a pc-relative address into a register without offending the
1340 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p), Pseudo,
1341 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
1342 "${:private}PCRELL${:uid}+8))\n"),
1343 !strconcat("${:private}PCRELL${:uid}:\n\t",
1344 "add$p $dst, pc, #PCRELV${:uid}")),
1347 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, i32imm:$id, pred:$p),
1349 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
1350 "${:private}PCRELL${:uid}+8))\n"),
1351 !strconcat("${:private}PCRELL${:uid}:\n\t",
1352 "add$p $dst, pc, #PCRELV${:uid}")),
1355 //===----------------------------------------------------------------------===//
1359 // __aeabi_read_tp preserves the registers r1-r3.
1361 Defs = [R0, R12, LR, CPSR] in {
1362 def TPsoft : AXI<0x0, (outs), (ins), BranchMisc,
1363 "bl __aeabi_read_tp",
1364 [(set R0, ARMthread_pointer)]>;
1367 //===----------------------------------------------------------------------===//
1368 // Non-Instruction Patterns
1371 // ConstantPool, GlobalAddress, and JumpTable
1372 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>;
1373 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
1374 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1375 (LEApcrelJT tjumptable:$dst, imm:$id)>;
1377 // Large immediate handling.
1379 // Two piece so_imms.
1380 let isReMaterializable = 1 in
1381 def MOVi2pieces : AI1x2<0x0, (outs GPR:$dst), (ins so_imm2part:$src), DPRdMisc,
1382 "mov", " $dst, $src",
1383 [(set GPR:$dst, so_imm2part:$src)]>;
1385 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
1386 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1387 (so_imm2part_2 imm:$RHS))>;
1388 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
1389 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1390 (so_imm2part_2 imm:$RHS))>;
1392 // TODO: add,sub,and, 3-instr forms?
1396 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
1398 // zextload i1 -> zextload i8
1399 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1401 // extload -> zextload
1402 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1403 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1404 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
1406 // truncstore i1 -> truncstore i8
1407 def : ARMPat<(truncstorei1 GPR:$src, addrmode2:$dst),
1408 (STRB GPR:$src, addrmode2:$dst)>;
1409 def : ARMPat<(pre_truncsti1 GPR:$src, GPR:$base, am2offset:$offset),
1410 (STRB_PRE GPR:$src, GPR:$base, am2offset:$offset)>;
1411 def : ARMPat<(post_truncsti1 GPR:$src, GPR:$base, am2offset:$offset),
1412 (STRB_POST GPR:$src, GPR:$base, am2offset:$offset)>;
1415 def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra (shl GPR:$b, 16), 16)),
1416 (SMULBB GPR:$a, GPR:$b)>;
1417 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
1418 (SMULBB GPR:$a, GPR:$b)>;
1419 def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16)),
1420 (SMULBT GPR:$a, GPR:$b)>;
1421 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, 16)),
1422 (SMULBT GPR:$a, GPR:$b)>;
1423 def : ARMV5TEPat<(mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16)),
1424 (SMULTB GPR:$a, GPR:$b)>;
1425 def : ARMV5TEPat<(mul (sra GPR:$a, 16), sext_16_node:$b),
1426 (SMULTB GPR:$a, GPR:$b)>;
1427 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16),
1428 (SMULWB GPR:$a, GPR:$b)>;
1429 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), 16),
1430 (SMULWB GPR:$a, GPR:$b)>;
1432 def : ARMV5TEPat<(add GPR:$acc,
1433 (mul (sra (shl GPR:$a, 16), 16),
1434 (sra (shl GPR:$b, 16), 16))),
1435 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1436 def : ARMV5TEPat<(add GPR:$acc,
1437 (mul sext_16_node:$a, sext_16_node:$b)),
1438 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1439 def : ARMV5TEPat<(add GPR:$acc,
1440 (mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16))),
1441 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1442 def : ARMV5TEPat<(add GPR:$acc,
1443 (mul sext_16_node:$a, (sra GPR:$b, 16))),
1444 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1445 def : ARMV5TEPat<(add GPR:$acc,
1446 (mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16))),
1447 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1448 def : ARMV5TEPat<(add GPR:$acc,
1449 (mul (sra GPR:$a, 16), sext_16_node:$b)),
1450 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1451 def : ARMV5TEPat<(add GPR:$acc,
1452 (sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16)),
1453 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1454 def : ARMV5TEPat<(add GPR:$acc,
1455 (sra (mul GPR:$a, sext_16_node:$b), 16)),
1456 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1458 //===----------------------------------------------------------------------===//
1462 include "ARMInstrThumb.td"
1464 //===----------------------------------------------------------------------===//
1465 // Floating Point Support
1468 include "ARMInstrVFP.td"