1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisInt<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
68 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
70 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
71 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
75 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
76 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
77 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
79 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
80 [SDNPHasChain, SDNPOutGlue]>;
81 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
82 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
84 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
85 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
87 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
88 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
90 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
91 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
94 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
95 [SDNPHasChain, SDNPOptInGlue]>;
97 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
100 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
101 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
103 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
105 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
108 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
111 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
114 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
115 [SDNPOutGlue, SDNPCommutative]>;
117 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
119 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
120 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
121 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
123 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
124 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
125 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
126 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
127 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
128 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
129 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
132 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
134 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
136 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
137 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
139 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
141 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
142 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
145 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
147 //===----------------------------------------------------------------------===//
148 // ARM Instruction Predicate Definitions.
150 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
151 AssemblerPredicate<"HasV4TOps">;
152 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
153 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
154 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
155 AssemblerPredicate<"HasV5TEOps">;
156 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
157 AssemblerPredicate<"HasV6Ops">;
158 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
159 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
160 AssemblerPredicate<"HasV6T2Ops">;
161 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
162 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
163 AssemblerPredicate<"HasV7Ops">;
164 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
165 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
166 AssemblerPredicate<"FeatureVFP2">;
167 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
168 AssemblerPredicate<"FeatureVFP3">;
169 def HasNEON : Predicate<"Subtarget->hasNEON()">,
170 AssemblerPredicate<"FeatureNEON">;
171 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
172 AssemblerPredicate<"FeatureFP16">;
173 def HasDivide : Predicate<"Subtarget->hasDivide()">,
174 AssemblerPredicate<"FeatureHWDiv">;
175 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
176 AssemblerPredicate<"FeatureT2XtPk">;
177 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
178 AssemblerPredicate<"FeatureDSPThumb2">;
179 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
180 AssemblerPredicate<"FeatureDB">;
181 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
182 AssemblerPredicate<"FeatureMP">;
183 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
184 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
185 def IsThumb : Predicate<"Subtarget->isThumb()">,
186 AssemblerPredicate<"ModeThumb">;
187 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
188 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
189 AssemblerPredicate<"ModeThumb,FeatureThumb2">;
190 def IsARM : Predicate<"!Subtarget->isThumb()">,
191 AssemblerPredicate<"!ModeThumb">;
192 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
193 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
195 // FIXME: Eventually this will be just "hasV6T2Ops".
196 def UseMovt : Predicate<"Subtarget->useMovt()">;
197 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
198 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
200 //===----------------------------------------------------------------------===//
201 // ARM Flag Definitions.
203 class RegConstraint<string C> {
204 string Constraints = C;
207 //===----------------------------------------------------------------------===//
208 // ARM specific transformation functions and pattern fragments.
211 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
212 // so_imm_neg def below.
213 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
214 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
217 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
218 // so_imm_not def below.
219 def so_imm_not_XFORM : SDNodeXForm<imm, [{
220 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
223 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
224 def imm1_15 : ImmLeaf<i32, [{
225 return (int32_t)Imm >= 1 && (int32_t)Imm < 16;
228 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
229 def imm16_31 : ImmLeaf<i32, [{
230 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
235 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
236 }], so_imm_neg_XFORM>;
240 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
241 }], so_imm_not_XFORM>;
243 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
244 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
245 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
248 /// Split a 32-bit immediate into two 16 bit parts.
249 def hi16 : SDNodeXForm<imm, [{
250 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
253 def lo16AllZero : PatLeaf<(i32 imm), [{
254 // Returns true if all low 16-bits are 0.
255 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
258 /// imm0_65535 - An immediate is in the range [0.65535].
259 def Imm0_65535AsmOperand: AsmOperandClass { let Name = "Imm0_65535"; }
260 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
261 return Imm >= 0 && Imm < 65536;
263 let ParserMatchClass = Imm0_65535AsmOperand;
266 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
267 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
269 /// adde and sube predicates - True based on whether the carry flag output
270 /// will be needed or not.
271 def adde_dead_carry :
272 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
273 [{return !N->hasAnyUseOfValue(1);}]>;
274 def sube_dead_carry :
275 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
276 [{return !N->hasAnyUseOfValue(1);}]>;
277 def adde_live_carry :
278 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
279 [{return N->hasAnyUseOfValue(1);}]>;
280 def sube_live_carry :
281 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
282 [{return N->hasAnyUseOfValue(1);}]>;
284 // An 'and' node with a single use.
285 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
286 return N->hasOneUse();
289 // An 'xor' node with a single use.
290 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
291 return N->hasOneUse();
294 // An 'fmul' node with a single use.
295 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
296 return N->hasOneUse();
299 // An 'fadd' node which checks for single non-hazardous use.
300 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
301 return hasNoVMLxHazardUse(N);
304 // An 'fsub' node which checks for single non-hazardous use.
305 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
306 return hasNoVMLxHazardUse(N);
309 //===----------------------------------------------------------------------===//
310 // Operand Definitions.
314 // FIXME: rename brtarget to t2_brtarget
315 def brtarget : Operand<OtherVT> {
316 let EncoderMethod = "getBranchTargetOpValue";
317 let OperandType = "OPERAND_PCREL";
320 // FIXME: get rid of this one?
321 def uncondbrtarget : Operand<OtherVT> {
322 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
323 let OperandType = "OPERAND_PCREL";
326 // Branch target for ARM. Handles conditional/unconditional
327 def br_target : Operand<OtherVT> {
328 let EncoderMethod = "getARMBranchTargetOpValue";
329 let OperandType = "OPERAND_PCREL";
333 // FIXME: rename bltarget to t2_bl_target?
334 def bltarget : Operand<i32> {
335 // Encoded the same as branch targets.
336 let EncoderMethod = "getBranchTargetOpValue";
337 let OperandType = "OPERAND_PCREL";
340 // Call target for ARM. Handles conditional/unconditional
341 // FIXME: rename bl_target to t2_bltarget?
342 def bl_target : Operand<i32> {
343 // Encoded the same as branch targets.
344 let EncoderMethod = "getARMBranchTargetOpValue";
345 let OperandType = "OPERAND_PCREL";
349 // A list of registers separated by comma. Used by load/store multiple.
350 def RegListAsmOperand : AsmOperandClass {
351 let Name = "RegList";
352 let SuperClasses = [];
355 def DPRRegListAsmOperand : AsmOperandClass {
356 let Name = "DPRRegList";
357 let SuperClasses = [];
360 def SPRRegListAsmOperand : AsmOperandClass {
361 let Name = "SPRRegList";
362 let SuperClasses = [];
365 def reglist : Operand<i32> {
366 let EncoderMethod = "getRegisterListOpValue";
367 let ParserMatchClass = RegListAsmOperand;
368 let PrintMethod = "printRegisterList";
371 def dpr_reglist : Operand<i32> {
372 let EncoderMethod = "getRegisterListOpValue";
373 let ParserMatchClass = DPRRegListAsmOperand;
374 let PrintMethod = "printRegisterList";
377 def spr_reglist : Operand<i32> {
378 let EncoderMethod = "getRegisterListOpValue";
379 let ParserMatchClass = SPRRegListAsmOperand;
380 let PrintMethod = "printRegisterList";
383 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
384 def cpinst_operand : Operand<i32> {
385 let PrintMethod = "printCPInstOperand";
389 def pclabel : Operand<i32> {
390 let PrintMethod = "printPCLabel";
393 // ADR instruction labels.
394 def adrlabel : Operand<i32> {
395 let EncoderMethod = "getAdrLabelOpValue";
398 def neon_vcvt_imm32 : Operand<i32> {
399 let EncoderMethod = "getNEONVcvtImm32OpValue";
402 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
403 def rot_imm : Operand<i32>, ImmLeaf<i32, [{
404 int32_t v = (int32_t)Imm;
405 return v == 8 || v == 16 || v == 24; }]> {
406 let EncoderMethod = "getRotImmOpValue";
409 def ShifterAsmOperand : AsmOperandClass {
410 let Name = "Shifter";
411 let SuperClasses = [];
414 // shift_imm: An integer that encodes a shift amount and the type of shift
415 // (currently either asr or lsl) using the same encoding used for the
416 // immediates in so_reg operands.
417 def shift_imm : Operand<i32> {
418 let PrintMethod = "printShiftImmOperand";
419 let ParserMatchClass = ShifterAsmOperand;
422 def ShiftedRegAsmOperand : AsmOperandClass {
423 let Name = "ShiftedReg";
426 // shifter_operand operands: so_reg and so_imm.
427 def so_reg : Operand<i32>, // reg reg imm
428 ComplexPattern<i32, 3, "SelectShifterOperandReg",
429 [shl,srl,sra,rotr]> {
430 let EncoderMethod = "getSORegOpValue";
431 let PrintMethod = "printSORegOperand";
432 let ParserMatchClass = ShiftedRegAsmOperand;
433 let MIOperandInfo = (ops GPR, GPR, shift_imm);
435 // FIXME: Does this need to be distinct from so_reg?
436 def shift_so_reg : Operand<i32>, // reg reg imm
437 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
438 [shl,srl,sra,rotr]> {
439 let EncoderMethod = "getSORegOpValue";
440 let PrintMethod = "printSORegOperand";
441 let MIOperandInfo = (ops GPR, GPR, shift_imm);
444 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
445 // 8-bit immediate rotated by an arbitrary number of bits.
446 def SOImmAsmOperand: AsmOperandClass { let Name = "ARMSOImm"; }
447 def so_imm : Operand<i32>, ImmLeaf<i32, [{
448 return ARM_AM::getSOImmVal(Imm) != -1;
450 let EncoderMethod = "getSOImmOpValue";
451 let ParserMatchClass = SOImmAsmOperand;
454 // Break so_imm's up into two pieces. This handles immediates with up to 16
455 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
456 // get the first/second pieces.
457 def so_imm2part : PatLeaf<(imm), [{
458 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
461 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
463 def arm_i32imm : PatLeaf<(imm), [{
464 if (Subtarget->hasV6T2Ops())
466 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
469 /// imm0_7 predicate - Immediate in the range [0,31].
470 def Imm0_7AsmOperand: AsmOperandClass { let Name = "Imm0_7"; }
471 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
472 return Imm >= 0 && Imm < 8;
474 let ParserMatchClass = Imm0_7AsmOperand;
477 /// imm0_15 predicate - Immediate in the range [0,31].
478 def Imm0_15AsmOperand: AsmOperandClass { let Name = "Imm0_15"; }
479 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
480 return Imm >= 0 && Imm < 16;
482 let ParserMatchClass = Imm0_15AsmOperand;
485 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
486 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
487 return Imm >= 0 && Imm < 32;
490 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
491 def imm0_31_m1 : Operand<i32>, ImmLeaf<i32, [{
492 return Imm >= 0 && Imm < 32;
494 let EncoderMethod = "getImmMinusOneOpValue";
497 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
498 // a relocatable expression.
500 // FIXME: This really needs a Thumb version separate from the ARM version.
501 // While the range is the same, and can thus use the same match class,
502 // the encoding is different so it should have a different encoder method.
503 def Imm0_65535ExprAsmOperand: AsmOperandClass { let Name = "Imm0_65535Expr"; }
504 def imm0_65535_expr : Operand<i32> {
505 let EncoderMethod = "getHiLo16ImmOpValue";
506 let ParserMatchClass = Imm0_65535ExprAsmOperand;
509 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
511 def bf_inv_mask_imm : Operand<i32>,
513 return ARM::isBitFieldInvertedMask(N->getZExtValue());
515 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
516 let PrintMethod = "printBitfieldInvMaskImmOperand";
519 /// lsb_pos_imm - position of the lsb bit, used by BFI4p and t2BFI4p
520 def lsb_pos_imm : Operand<i32>, ImmLeaf<i32, [{
521 return isInt<5>(Imm);
524 /// width_imm - number of bits to be copied, used by BFI4p and t2BFI4p
525 def width_imm : Operand<i32>, ImmLeaf<i32, [{
526 return Imm > 0 && Imm <= 32;
528 let EncoderMethod = "getMsbOpValue";
531 def ssat_imm : Operand<i32>, ImmLeaf<i32, [{
532 return Imm > 0 && Imm <= 32;
534 let EncoderMethod = "getSsatBitPosValue";
537 // Define ARM specific addressing modes.
539 def MemMode2AsmOperand : AsmOperandClass {
540 let Name = "MemMode2";
541 let SuperClasses = [];
542 let ParserMethod = "tryParseMemMode2Operand";
545 def MemMode3AsmOperand : AsmOperandClass {
546 let Name = "MemMode3";
547 let SuperClasses = [];
548 let ParserMethod = "tryParseMemMode3Operand";
551 // addrmode_imm12 := reg +/- imm12
553 def addrmode_imm12 : Operand<i32>,
554 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
555 // 12-bit immediate operand. Note that instructions using this encode
556 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
557 // immediate values are as normal.
559 let EncoderMethod = "getAddrModeImm12OpValue";
560 let PrintMethod = "printAddrModeImm12Operand";
561 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
563 // ldst_so_reg := reg +/- reg shop imm
565 def ldst_so_reg : Operand<i32>,
566 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
567 let EncoderMethod = "getLdStSORegOpValue";
568 // FIXME: Simplify the printer
569 let PrintMethod = "printAddrMode2Operand";
570 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
573 // addrmode2 := reg +/- imm12
574 // := reg +/- reg shop imm
576 def addrmode2 : Operand<i32>,
577 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
578 let EncoderMethod = "getAddrMode2OpValue";
579 let PrintMethod = "printAddrMode2Operand";
580 let ParserMatchClass = MemMode2AsmOperand;
581 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
584 def am2offset : Operand<i32>,
585 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
586 [], [SDNPWantRoot]> {
587 let EncoderMethod = "getAddrMode2OffsetOpValue";
588 let PrintMethod = "printAddrMode2OffsetOperand";
589 let MIOperandInfo = (ops GPR, i32imm);
592 // addrmode3 := reg +/- reg
593 // addrmode3 := reg +/- imm8
595 def addrmode3 : Operand<i32>,
596 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
597 let EncoderMethod = "getAddrMode3OpValue";
598 let PrintMethod = "printAddrMode3Operand";
599 let ParserMatchClass = MemMode3AsmOperand;
600 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
603 def am3offset : Operand<i32>,
604 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
605 [], [SDNPWantRoot]> {
606 let EncoderMethod = "getAddrMode3OffsetOpValue";
607 let PrintMethod = "printAddrMode3OffsetOperand";
608 let MIOperandInfo = (ops GPR, i32imm);
611 // ldstm_mode := {ia, ib, da, db}
613 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
614 let EncoderMethod = "getLdStmModeOpValue";
615 let PrintMethod = "printLdStmModeOperand";
618 def MemMode5AsmOperand : AsmOperandClass {
619 let Name = "MemMode5";
620 let SuperClasses = [];
623 // addrmode5 := reg +/- imm8*4
625 def addrmode5 : Operand<i32>,
626 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
627 let PrintMethod = "printAddrMode5Operand";
628 let MIOperandInfo = (ops GPR:$base, i32imm);
629 let ParserMatchClass = MemMode5AsmOperand;
630 let EncoderMethod = "getAddrMode5OpValue";
633 // addrmode6 := reg with optional alignment
635 def addrmode6 : Operand<i32>,
636 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
637 let PrintMethod = "printAddrMode6Operand";
638 let MIOperandInfo = (ops GPR:$addr, i32imm);
639 let EncoderMethod = "getAddrMode6AddressOpValue";
642 def am6offset : Operand<i32>,
643 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
644 [], [SDNPWantRoot]> {
645 let PrintMethod = "printAddrMode6OffsetOperand";
646 let MIOperandInfo = (ops GPR);
647 let EncoderMethod = "getAddrMode6OffsetOpValue";
650 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
651 // (single element from one lane) for size 32.
652 def addrmode6oneL32 : Operand<i32>,
653 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
654 let PrintMethod = "printAddrMode6Operand";
655 let MIOperandInfo = (ops GPR:$addr, i32imm);
656 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
659 // Special version of addrmode6 to handle alignment encoding for VLD-dup
660 // instructions, specifically VLD4-dup.
661 def addrmode6dup : Operand<i32>,
662 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
663 let PrintMethod = "printAddrMode6Operand";
664 let MIOperandInfo = (ops GPR:$addr, i32imm);
665 let EncoderMethod = "getAddrMode6DupAddressOpValue";
668 // addrmodepc := pc + reg
670 def addrmodepc : Operand<i32>,
671 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
672 let PrintMethod = "printAddrModePCOperand";
673 let MIOperandInfo = (ops GPR, i32imm);
676 def MemMode7AsmOperand : AsmOperandClass {
677 let Name = "MemMode7";
678 let SuperClasses = [];
682 // Used by load/store exclusive instructions. Useful to enable right assembly
683 // parsing and printing. Not used for any codegen matching.
685 def addrmode7 : Operand<i32> {
686 let PrintMethod = "printAddrMode7Operand";
687 let MIOperandInfo = (ops GPR);
688 let ParserMatchClass = MemMode7AsmOperand;
691 def nohash_imm : Operand<i32> {
692 let PrintMethod = "printNoHashImmediate";
695 def CoprocNumAsmOperand : AsmOperandClass {
696 let Name = "CoprocNum";
697 let SuperClasses = [];
698 let ParserMethod = "tryParseCoprocNumOperand";
701 def CoprocRegAsmOperand : AsmOperandClass {
702 let Name = "CoprocReg";
703 let SuperClasses = [];
704 let ParserMethod = "tryParseCoprocRegOperand";
707 def p_imm : Operand<i32> {
708 let PrintMethod = "printPImmediate";
709 let ParserMatchClass = CoprocNumAsmOperand;
712 def c_imm : Operand<i32> {
713 let PrintMethod = "printCImmediate";
714 let ParserMatchClass = CoprocRegAsmOperand;
717 //===----------------------------------------------------------------------===//
719 include "ARMInstrFormats.td"
721 //===----------------------------------------------------------------------===//
722 // Multiclass helpers...
725 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
726 /// binop that produces a value.
727 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
728 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
729 PatFrag opnode, string baseOpc, bit Commutable = 0> {
730 // The register-immediate version is re-materializable. This is useful
731 // in particular for taking the address of a local.
732 let isReMaterializable = 1 in {
733 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
734 iii, opc, "\t$Rd, $Rn, $imm",
735 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
740 let Inst{19-16} = Rn;
741 let Inst{15-12} = Rd;
742 let Inst{11-0} = imm;
745 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
746 iir, opc, "\t$Rd, $Rn, $Rm",
747 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
752 let isCommutable = Commutable;
753 let Inst{19-16} = Rn;
754 let Inst{15-12} = Rd;
755 let Inst{11-4} = 0b00000000;
758 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
759 iis, opc, "\t$Rd, $Rn, $shift",
760 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
765 let Inst{19-16} = Rn;
766 let Inst{15-12} = Rd;
767 let Inst{11-0} = shift;
770 // Assembly aliases for optional destination operand when it's the same
771 // as the source operand.
772 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
773 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
774 so_imm:$imm, pred:$p,
777 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
778 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
782 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
783 (!cast<Instruction>(!strconcat(baseOpc, "rs")) GPR:$Rdn, GPR:$Rdn,
784 so_reg:$shift, pred:$p,
789 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
790 /// instruction modifies the CPSR register.
791 let isCodeGenOnly = 1, Defs = [CPSR] in {
792 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
793 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
794 PatFrag opnode, bit Commutable = 0> {
795 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
796 iii, opc, "\t$Rd, $Rn, $imm",
797 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
803 let Inst{19-16} = Rn;
804 let Inst{15-12} = Rd;
805 let Inst{11-0} = imm;
807 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
808 iir, opc, "\t$Rd, $Rn, $Rm",
809 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
813 let isCommutable = Commutable;
816 let Inst{19-16} = Rn;
817 let Inst{15-12} = Rd;
818 let Inst{11-4} = 0b00000000;
821 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
822 iis, opc, "\t$Rd, $Rn, $shift",
823 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
829 let Inst{19-16} = Rn;
830 let Inst{15-12} = Rd;
831 let Inst{11-0} = shift;
836 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
837 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
838 /// a explicit result, only implicitly set CPSR.
839 let isCompare = 1, Defs = [CPSR] in {
840 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
841 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
842 PatFrag opnode, bit Commutable = 0> {
843 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
845 [(opnode GPR:$Rn, so_imm:$imm)]> {
850 let Inst{19-16} = Rn;
851 let Inst{15-12} = 0b0000;
852 let Inst{11-0} = imm;
854 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
856 [(opnode GPR:$Rn, GPR:$Rm)]> {
859 let isCommutable = Commutable;
862 let Inst{19-16} = Rn;
863 let Inst{15-12} = 0b0000;
864 let Inst{11-4} = 0b00000000;
867 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
868 opc, "\t$Rn, $shift",
869 [(opnode GPR:$Rn, so_reg:$shift)]> {
874 let Inst{19-16} = Rn;
875 let Inst{15-12} = 0b0000;
876 let Inst{11-0} = shift;
881 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
882 /// register and one whose operand is a register rotated by 8/16/24.
883 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
884 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
885 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
886 IIC_iEXTr, opc, "\t$Rd, $Rm",
887 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
888 Requires<[IsARM, HasV6]> {
891 let Inst{19-16} = 0b1111;
892 let Inst{15-12} = Rd;
893 let Inst{11-10} = 0b00;
896 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
897 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
898 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
899 Requires<[IsARM, HasV6]> {
903 let Inst{19-16} = 0b1111;
904 let Inst{15-12} = Rd;
905 let Inst{11-10} = rot;
910 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
911 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
912 IIC_iEXTr, opc, "\t$Rd, $Rm",
913 [/* For disassembly only; pattern left blank */]>,
914 Requires<[IsARM, HasV6]> {
915 let Inst{19-16} = 0b1111;
916 let Inst{11-10} = 0b00;
918 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
919 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
920 [/* For disassembly only; pattern left blank */]>,
921 Requires<[IsARM, HasV6]> {
923 let Inst{19-16} = 0b1111;
924 let Inst{11-10} = rot;
928 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
929 /// register and one whose operand is a register rotated by 8/16/24.
930 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
931 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
932 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
933 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
934 Requires<[IsARM, HasV6]> {
938 let Inst{19-16} = Rn;
939 let Inst{15-12} = Rd;
940 let Inst{11-10} = 0b00;
941 let Inst{9-4} = 0b000111;
944 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
946 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
947 [(set GPR:$Rd, (opnode GPR:$Rn,
948 (rotr GPR:$Rm, rot_imm:$rot)))]>,
949 Requires<[IsARM, HasV6]> {
954 let Inst{19-16} = Rn;
955 let Inst{15-12} = Rd;
956 let Inst{11-10} = rot;
957 let Inst{9-4} = 0b000111;
962 // For disassembly only.
963 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
964 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
965 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
966 [/* For disassembly only; pattern left blank */]>,
967 Requires<[IsARM, HasV6]> {
968 let Inst{11-10} = 0b00;
970 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
972 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
973 [/* For disassembly only; pattern left blank */]>,
974 Requires<[IsARM, HasV6]> {
977 let Inst{19-16} = Rn;
978 let Inst{11-10} = rot;
982 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
983 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
984 string baseOpc, bit Commutable = 0> {
985 let Uses = [CPSR] in {
986 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
987 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
988 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
994 let Inst{15-12} = Rd;
995 let Inst{19-16} = Rn;
996 let Inst{11-0} = imm;
998 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
999 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1000 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1005 let Inst{11-4} = 0b00000000;
1007 let isCommutable = Commutable;
1009 let Inst{15-12} = Rd;
1010 let Inst{19-16} = Rn;
1012 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
1013 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1014 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
1020 let Inst{11-0} = shift;
1021 let Inst{15-12} = Rd;
1022 let Inst{19-16} = Rn;
1025 // Assembly aliases for optional destination operand when it's the same
1026 // as the source operand.
1027 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1028 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1029 so_imm:$imm, pred:$p,
1032 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1033 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1037 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1038 (!cast<Instruction>(!strconcat(baseOpc, "rs")) GPR:$Rdn, GPR:$Rdn,
1039 so_reg:$shift, pred:$p,
1044 // Carry setting variants
1045 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
1046 let usesCustomInserter = 1 in {
1047 multiclass AI1_adde_sube_s_irs<PatFrag opnode, bit Commutable = 0> {
1048 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1050 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>;
1051 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1053 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
1054 let isCommutable = Commutable;
1056 def rs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
1058 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>;
1062 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1063 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1064 InstrItinClass iir, PatFrag opnode> {
1065 // Note: We use the complex addrmode_imm12 rather than just an input
1066 // GPR and a constrained immediate so that we can use this to match
1067 // frame index references and avoid matching constant pool references.
1068 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1069 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1070 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1073 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1074 let Inst{19-16} = addr{16-13}; // Rn
1075 let Inst{15-12} = Rt;
1076 let Inst{11-0} = addr{11-0}; // imm12
1078 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1079 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1080 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1083 let shift{4} = 0; // Inst{4} = 0
1084 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1085 let Inst{19-16} = shift{16-13}; // Rn
1086 let Inst{15-12} = Rt;
1087 let Inst{11-0} = shift{11-0};
1092 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1093 InstrItinClass iir, PatFrag opnode> {
1094 // Note: We use the complex addrmode_imm12 rather than just an input
1095 // GPR and a constrained immediate so that we can use this to match
1096 // frame index references and avoid matching constant pool references.
1097 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1098 (ins GPR:$Rt, addrmode_imm12:$addr),
1099 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1100 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1103 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1104 let Inst{19-16} = addr{16-13}; // Rn
1105 let Inst{15-12} = Rt;
1106 let Inst{11-0} = addr{11-0}; // imm12
1108 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1109 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1110 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1113 let shift{4} = 0; // Inst{4} = 0
1114 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1115 let Inst{19-16} = shift{16-13}; // Rn
1116 let Inst{15-12} = Rt;
1117 let Inst{11-0} = shift{11-0};
1120 //===----------------------------------------------------------------------===//
1122 //===----------------------------------------------------------------------===//
1124 //===----------------------------------------------------------------------===//
1125 // Miscellaneous Instructions.
1128 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1129 /// the function. The first operand is the ID# for this instruction, the second
1130 /// is the index into the MachineConstantPool that this is, the third is the
1131 /// size in bytes of this constant pool entry.
1132 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1133 def CONSTPOOL_ENTRY :
1134 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1135 i32imm:$size), NoItinerary, []>;
1137 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1138 // from removing one half of the matched pairs. That breaks PEI, which assumes
1139 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1140 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1141 def ADJCALLSTACKUP :
1142 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1143 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1145 def ADJCALLSTACKDOWN :
1146 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1147 [(ARMcallseq_start timm:$amt)]>;
1150 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
1151 [/* For disassembly only; pattern left blank */]>,
1152 Requires<[IsARM, HasV6T2]> {
1153 let Inst{27-16} = 0b001100100000;
1154 let Inst{15-8} = 0b11110000;
1155 let Inst{7-0} = 0b00000000;
1158 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
1159 [/* For disassembly only; pattern left blank */]>,
1160 Requires<[IsARM, HasV6T2]> {
1161 let Inst{27-16} = 0b001100100000;
1162 let Inst{15-8} = 0b11110000;
1163 let Inst{7-0} = 0b00000001;
1166 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
1167 [/* For disassembly only; pattern left blank */]>,
1168 Requires<[IsARM, HasV6T2]> {
1169 let Inst{27-16} = 0b001100100000;
1170 let Inst{15-8} = 0b11110000;
1171 let Inst{7-0} = 0b00000010;
1174 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
1175 [/* For disassembly only; pattern left blank */]>,
1176 Requires<[IsARM, HasV6T2]> {
1177 let Inst{27-16} = 0b001100100000;
1178 let Inst{15-8} = 0b11110000;
1179 let Inst{7-0} = 0b00000011;
1182 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
1184 [/* For disassembly only; pattern left blank */]>,
1185 Requires<[IsARM, HasV6]> {
1190 let Inst{15-12} = Rd;
1191 let Inst{19-16} = Rn;
1192 let Inst{27-20} = 0b01101000;
1193 let Inst{7-4} = 0b1011;
1194 let Inst{11-8} = 0b1111;
1197 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1198 [/* For disassembly only; pattern left blank */]>,
1199 Requires<[IsARM, HasV6T2]> {
1200 let Inst{27-16} = 0b001100100000;
1201 let Inst{15-8} = 0b11110000;
1202 let Inst{7-0} = 0b00000100;
1205 // The i32imm operand $val can be used by a debugger to store more information
1206 // about the breakpoint.
1207 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1208 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1210 let Inst{3-0} = val{3-0};
1211 let Inst{19-8} = val{15-4};
1212 let Inst{27-20} = 0b00010010;
1213 let Inst{7-4} = 0b0111;
1216 // Change Processor State is a system instruction -- for disassembly and
1218 // FIXME: Since the asm parser has currently no clean way to handle optional
1219 // operands, create 3 versions of the same instruction. Once there's a clean
1220 // framework to represent optional operands, change this behavior.
1221 class CPS<dag iops, string asm_ops>
1222 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1223 [/* For disassembly only; pattern left blank */]>, Requires<[IsARM]> {
1229 let Inst{31-28} = 0b1111;
1230 let Inst{27-20} = 0b00010000;
1231 let Inst{19-18} = imod;
1232 let Inst{17} = M; // Enabled if mode is set;
1234 let Inst{8-6} = iflags;
1236 let Inst{4-0} = mode;
1240 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
1241 "$imod\t$iflags, $mode">;
1242 let mode = 0, M = 0 in
1243 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1245 let imod = 0, iflags = 0, M = 1 in
1246 def CPS1p : CPS<(ins i32imm:$mode), "\t$mode">;
1248 // Preload signals the memory system of possible future data/instruction access.
1249 // These are for disassembly only.
1250 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1252 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1253 !strconcat(opc, "\t$addr"),
1254 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1257 let Inst{31-26} = 0b111101;
1258 let Inst{25} = 0; // 0 for immediate form
1259 let Inst{24} = data;
1260 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1261 let Inst{22} = read;
1262 let Inst{21-20} = 0b01;
1263 let Inst{19-16} = addr{16-13}; // Rn
1264 let Inst{15-12} = 0b1111;
1265 let Inst{11-0} = addr{11-0}; // imm12
1268 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1269 !strconcat(opc, "\t$shift"),
1270 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1272 let Inst{31-26} = 0b111101;
1273 let Inst{25} = 1; // 1 for register form
1274 let Inst{24} = data;
1275 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1276 let Inst{22} = read;
1277 let Inst{21-20} = 0b01;
1278 let Inst{19-16} = shift{16-13}; // Rn
1279 let Inst{15-12} = 0b1111;
1280 let Inst{11-0} = shift{11-0};
1284 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1285 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1286 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1288 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1290 [/* For disassembly only; pattern left blank */]>,
1293 let Inst{31-10} = 0b1111000100000001000000;
1298 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1299 []>, Requires<[IsARM, HasV7]> {
1301 let Inst{27-4} = 0b001100100000111100001111;
1302 let Inst{3-0} = opt;
1305 // A5.4 Permanently UNDEFINED instructions.
1306 let isBarrier = 1, isTerminator = 1 in
1307 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1310 let Inst = 0xe7ffdefe;
1313 // Address computation and loads and stores in PIC mode.
1314 let isNotDuplicable = 1 in {
1315 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1317 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1319 let AddedComplexity = 10 in {
1320 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1322 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1324 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1326 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1328 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1330 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1332 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1334 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1336 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1338 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1340 let AddedComplexity = 10 in {
1341 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1342 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1344 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1345 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1346 addrmodepc:$addr)]>;
1348 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1349 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1351 } // isNotDuplicable = 1
1354 // LEApcrel - Load a pc-relative address into a register without offending the
1356 let neverHasSideEffects = 1, isReMaterializable = 1 in
1357 // The 'adr' mnemonic encodes differently if the label is before or after
1358 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1359 // know until then which form of the instruction will be used.
1360 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1361 MiscFrm, IIC_iALUi, "adr", "\t$Rd, #$label", []> {
1364 let Inst{27-25} = 0b001;
1366 let Inst{19-16} = 0b1111;
1367 let Inst{15-12} = Rd;
1368 let Inst{11-0} = label;
1370 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1373 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1374 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1377 //===----------------------------------------------------------------------===//
1378 // Control Flow Instructions.
1381 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1383 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1384 "bx", "\tlr", [(ARMretflag)]>,
1385 Requires<[IsARM, HasV4T]> {
1386 let Inst{27-0} = 0b0001001011111111111100011110;
1390 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1391 "mov", "\tpc, lr", [(ARMretflag)]>,
1392 Requires<[IsARM, NoV4T]> {
1393 let Inst{27-0} = 0b0001101000001111000000001110;
1397 // Indirect branches
1398 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1400 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1401 [(brind GPR:$dst)]>,
1402 Requires<[IsARM, HasV4T]> {
1404 let Inst{31-4} = 0b1110000100101111111111110001;
1405 let Inst{3-0} = dst;
1408 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1409 "bx", "\t$dst", [/* pattern left blank */]>,
1410 Requires<[IsARM, HasV4T]> {
1412 let Inst{27-4} = 0b000100101111111111110001;
1413 let Inst{3-0} = dst;
1417 // All calls clobber the non-callee saved registers. SP is marked as
1418 // a use to prevent stack-pointer assignments that appear immediately
1419 // before calls from potentially appearing dead.
1421 // On non-Darwin platforms R9 is callee-saved.
1422 // FIXME: Do we really need a non-predicated version? If so, it should
1423 // at least be a pseudo instruction expanding to the predicated version
1424 // at MC lowering time.
1425 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1427 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1428 IIC_Br, "bl\t$func",
1429 [(ARMcall tglobaladdr:$func)]>,
1430 Requires<[IsARM, IsNotDarwin]> {
1431 let Inst{31-28} = 0b1110;
1433 let Inst{23-0} = func;
1436 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1437 IIC_Br, "bl", "\t$func",
1438 [(ARMcall_pred tglobaladdr:$func)]>,
1439 Requires<[IsARM, IsNotDarwin]> {
1441 let Inst{23-0} = func;
1445 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1446 IIC_Br, "blx\t$func",
1447 [(ARMcall GPR:$func)]>,
1448 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1450 let Inst{31-4} = 0b1110000100101111111111110011;
1451 let Inst{3-0} = func;
1454 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1455 IIC_Br, "blx", "\t$func",
1456 [(ARMcall_pred GPR:$func)]>,
1457 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1459 let Inst{27-4} = 0b000100101111111111110011;
1460 let Inst{3-0} = func;
1464 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1465 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1466 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1467 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1470 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1471 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1472 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1476 // On Darwin R9 is call-clobbered.
1477 // R7 is marked as a use to prevent frame-pointer assignments from being
1478 // moved above / below calls.
1479 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1480 Uses = [R7, SP] in {
1481 def BLr9 : ARMPseudoExpand<(outs), (ins bl_target:$func, variable_ops),
1483 [(ARMcall tglobaladdr:$func)], (BL bl_target:$func)>,
1484 Requires<[IsARM, IsDarwin]>;
1486 def BLr9_pred : ARMPseudoExpand<(outs),
1487 (ins bl_target:$func, pred:$p, variable_ops),
1489 [(ARMcall_pred tglobaladdr:$func)],
1490 (BL_pred bl_target:$func, pred:$p)>,
1491 Requires<[IsARM, IsDarwin]>;
1494 def BLXr9 : ARMPseudoExpand<(outs), (ins GPR:$func, variable_ops),
1496 [(ARMcall GPR:$func)],
1498 Requires<[IsARM, HasV5T, IsDarwin]>;
1500 def BLXr9_pred: ARMPseudoExpand<(outs), (ins GPR:$func, pred:$p,variable_ops),
1502 [(ARMcall_pred GPR:$func)],
1503 (BLX_pred GPR:$func, pred:$p)>,
1504 Requires<[IsARM, HasV5T, IsDarwin]>;
1507 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1508 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1509 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1510 Requires<[IsARM, HasV4T, IsDarwin]>;
1513 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1514 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1515 Requires<[IsARM, NoV4T, IsDarwin]>;
1518 let isBranch = 1, isTerminator = 1 in {
1519 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1520 // a two-value operand where a dag node expects two operands. :(
1521 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1522 IIC_Br, "b", "\t$target",
1523 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1525 let Inst{23-0} = target;
1528 let isBarrier = 1 in {
1529 // B is "predicable" since it's just a Bcc with an 'always' condition.
1530 let isPredicable = 1 in
1531 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1532 // should be sufficient.
1533 // FIXME: Is B really a Barrier? That doesn't seem right.
1534 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
1535 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
1537 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1538 def BR_JTr : ARMPseudoInst<(outs),
1539 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1541 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1542 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1543 // into i12 and rs suffixed versions.
1544 def BR_JTm : ARMPseudoInst<(outs),
1545 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1547 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1549 def BR_JTadd : ARMPseudoInst<(outs),
1550 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1552 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1554 } // isNotDuplicable = 1, isIndirectBranch = 1
1559 // BLX (immediate) -- for disassembly only
1560 def BLXi : AXI<(outs), (ins br_target:$target), BrMiscFrm, NoItinerary,
1561 "blx\t$target", [/* pattern left blank */]>,
1562 Requires<[IsARM, HasV5T]> {
1563 let Inst{31-25} = 0b1111101;
1565 let Inst{23-0} = target{24-1};
1566 let Inst{24} = target{0};
1569 // Branch and Exchange Jazelle
1570 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1571 [/* pattern left blank */]> {
1573 let Inst{23-20} = 0b0010;
1574 let Inst{19-8} = 0xfff;
1575 let Inst{7-4} = 0b0010;
1576 let Inst{3-0} = func;
1581 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1583 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
1585 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1586 IIC_Br, []>, Requires<[IsDarwin]>;
1588 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1589 IIC_Br, []>, Requires<[IsDarwin]>;
1591 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst, variable_ops),
1593 (Bcc br_target:$dst, (ops 14, zero_reg))>,
1594 Requires<[IsARM, IsDarwin]>;
1596 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
1599 Requires<[IsARM, IsDarwin]>;
1603 // Non-Darwin versions (the difference is R9).
1604 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
1606 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1607 IIC_Br, []>, Requires<[IsNotDarwin]>;
1609 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1610 IIC_Br, []>, Requires<[IsNotDarwin]>;
1612 def TAILJMPdND : ARMPseudoExpand<(outs), (ins brtarget:$dst, variable_ops),
1614 (Bcc br_target:$dst, (ops 14, zero_reg))>,
1615 Requires<[IsARM, IsNotDarwin]>;
1617 def TAILJMPrND : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
1620 Requires<[IsARM, IsNotDarwin]>;
1628 // Secure Monitor Call is a system instruction -- for disassembly only
1629 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1630 [/* For disassembly only; pattern left blank */]> {
1632 let Inst{23-4} = 0b01100000000000000111;
1633 let Inst{3-0} = opt;
1636 // Supervisor Call (Software Interrupt) -- for disassembly only
1637 let isCall = 1, Uses = [SP] in {
1638 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1639 [/* For disassembly only; pattern left blank */]> {
1641 let Inst{23-0} = svc;
1645 // Store Return State is a system instruction -- for disassembly only
1646 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1647 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1648 NoItinerary, "srs${amode}\tsp!, $mode",
1649 [/* For disassembly only; pattern left blank */]> {
1650 let Inst{31-28} = 0b1111;
1651 let Inst{22-20} = 0b110; // W = 1
1652 let Inst{19-8} = 0xd05;
1653 let Inst{7-5} = 0b000;
1656 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1657 NoItinerary, "srs${amode}\tsp, $mode",
1658 [/* For disassembly only; pattern left blank */]> {
1659 let Inst{31-28} = 0b1111;
1660 let Inst{22-20} = 0b100; // W = 0
1661 let Inst{19-8} = 0xd05;
1662 let Inst{7-5} = 0b000;
1665 // Return From Exception is a system instruction -- for disassembly only
1666 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1667 NoItinerary, "rfe${amode}\t$base!",
1668 [/* For disassembly only; pattern left blank */]> {
1669 let Inst{31-28} = 0b1111;
1670 let Inst{22-20} = 0b011; // W = 1
1671 let Inst{15-0} = 0x0a00;
1674 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1675 NoItinerary, "rfe${amode}\t$base",
1676 [/* For disassembly only; pattern left blank */]> {
1677 let Inst{31-28} = 0b1111;
1678 let Inst{22-20} = 0b001; // W = 0
1679 let Inst{15-0} = 0x0a00;
1681 } // isCodeGenOnly = 1
1683 //===----------------------------------------------------------------------===//
1684 // Load / store Instructions.
1690 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1691 UnOpFrag<(load node:$Src)>>;
1692 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1693 UnOpFrag<(zextloadi8 node:$Src)>>;
1694 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1695 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1696 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1697 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1699 // Special LDR for loads from non-pc-relative constpools.
1700 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1701 isReMaterializable = 1 in
1702 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1703 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
1707 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1708 let Inst{19-16} = 0b1111;
1709 let Inst{15-12} = Rt;
1710 let Inst{11-0} = addr{11-0}; // imm12
1713 // Loads with zero extension
1714 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1715 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
1716 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
1718 // Loads with sign extension
1719 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1720 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
1721 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
1723 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1724 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
1725 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
1727 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1729 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
1730 (ins addrmode3:$addr), LdMiscFrm,
1731 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
1732 []>, Requires<[IsARM, HasV5TE]>;
1736 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
1737 def _PRE : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1738 (ins addrmode2:$addr), IndexModePre, LdFrm, itin,
1739 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1741 // {13} 1 == Rm, 0 == imm12
1745 let Inst{25} = addr{13};
1746 let Inst{23} = addr{12};
1747 let Inst{19-16} = addr{17-14};
1748 let Inst{11-0} = addr{11-0};
1749 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1751 def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1752 (ins GPR:$Rn, am2offset:$offset),
1753 IndexModePost, LdFrm, itin,
1754 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1755 // {13} 1 == Rm, 0 == imm12
1760 let Inst{25} = offset{13};
1761 let Inst{23} = offset{12};
1762 let Inst{19-16} = Rn;
1763 let Inst{11-0} = offset{11-0};
1767 let mayLoad = 1, neverHasSideEffects = 1 in {
1768 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
1769 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
1772 multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
1773 def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1774 (ins addrmode3:$addr), IndexModePre,
1776 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1778 let Inst{23} = addr{8}; // U bit
1779 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1780 let Inst{19-16} = addr{12-9}; // Rn
1781 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1782 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1784 def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1785 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1787 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1790 let Inst{23} = offset{8}; // U bit
1791 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1792 let Inst{19-16} = Rn;
1793 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1794 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1798 let mayLoad = 1, neverHasSideEffects = 1 in {
1799 defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
1800 defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
1801 defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
1802 let hasExtraDefRegAllocReq = 1 in {
1803 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
1804 (ins addrmode3:$addr), IndexModePre,
1805 LdMiscFrm, IIC_iLoad_d_ru,
1806 "ldrd", "\t$Rt, $Rt2, $addr!",
1807 "$addr.base = $Rn_wb", []> {
1809 let Inst{23} = addr{8}; // U bit
1810 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1811 let Inst{19-16} = addr{12-9}; // Rn
1812 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1813 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1815 def LDRD_POST: AI3ldstidx<0b1101, 0, 1, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
1816 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1817 LdMiscFrm, IIC_iLoad_d_ru,
1818 "ldrd", "\t$Rt, $Rt2, [$Rn], $offset",
1819 "$Rn = $Rn_wb", []> {
1822 let Inst{23} = offset{8}; // U bit
1823 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1824 let Inst{19-16} = Rn;
1825 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1826 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1828 } // hasExtraDefRegAllocReq = 1
1829 } // mayLoad = 1, neverHasSideEffects = 1
1831 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1832 let mayLoad = 1, neverHasSideEffects = 1 in {
1833 def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$base_wb),
1834 (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_ru,
1835 "ldrt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1837 // {13} 1 == Rm, 0 == imm12
1841 let Inst{25} = addr{13};
1842 let Inst{23} = addr{12};
1843 let Inst{21} = 1; // overwrite
1844 let Inst{19-16} = addr{17-14};
1845 let Inst{11-0} = addr{11-0};
1846 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1848 def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1849 (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_bh_ru,
1850 "ldrbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1852 // {13} 1 == Rm, 0 == imm12
1856 let Inst{25} = addr{13};
1857 let Inst{23} = addr{12};
1858 let Inst{21} = 1; // overwrite
1859 let Inst{19-16} = addr{17-14};
1860 let Inst{11-0} = addr{11-0};
1861 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1863 def LDRSBT : AI3ldstidxT<0b1101, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1864 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1865 "ldrsbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1866 let Inst{21} = 1; // overwrite
1868 def LDRHT : AI3ldstidxT<0b1011, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1869 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1870 "ldrht", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1871 let Inst{21} = 1; // overwrite
1873 def LDRSHT : AI3ldstidxT<0b1111, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1874 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1875 "ldrsht", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1876 let Inst{21} = 1; // overwrite
1882 // Stores with truncate
1883 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
1884 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
1885 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
1888 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1889 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
1890 StMiscFrm, IIC_iStore_d_r,
1891 "strd", "\t$Rt, $src2, $addr", []>, Requires<[IsARM, HasV5TE]>;
1894 def STR_PRE : AI2stridx<0, 1, (outs GPR:$Rn_wb),
1895 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1896 IndexModePre, StFrm, IIC_iStore_ru,
1897 "str", "\t$Rt, [$Rn, $offset]!",
1898 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1900 (pre_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1902 def STR_POST : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1903 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1904 IndexModePost, StFrm, IIC_iStore_ru,
1905 "str", "\t$Rt, [$Rn], $offset",
1906 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1908 (post_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1910 def STRB_PRE : AI2stridx<1, 1, (outs GPR:$Rn_wb),
1911 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1912 IndexModePre, StFrm, IIC_iStore_bh_ru,
1913 "strb", "\t$Rt, [$Rn, $offset]!",
1914 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1915 [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
1916 GPR:$Rn, am2offset:$offset))]>;
1917 def STRB_POST: AI2stridx<1, 0, (outs GPR:$Rn_wb),
1918 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1919 IndexModePost, StFrm, IIC_iStore_bh_ru,
1920 "strb", "\t$Rt, [$Rn], $offset",
1921 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1922 [(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
1923 GPR:$Rn, am2offset:$offset))]>;
1925 def STRH_PRE : AI3stridx<0b1011, 0, 1, (outs GPR:$Rn_wb),
1926 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1927 IndexModePre, StMiscFrm, IIC_iStore_ru,
1928 "strh", "\t$Rt, [$Rn, $offset]!",
1929 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1931 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
1933 def STRH_POST: AI3stridx<0b1011, 0, 0, (outs GPR:$Rn_wb),
1934 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1935 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
1936 "strh", "\t$Rt, [$Rn], $offset",
1937 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1938 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
1939 GPR:$Rn, am3offset:$offset))]>;
1941 // For disassembly only
1942 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1943 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1944 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1945 StMiscFrm, IIC_iStore_d_ru,
1946 "strd", "\t$src1, $src2, [$base, $offset]!",
1947 "$base = $base_wb", []>;
1949 // For disassembly only
1950 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1951 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1952 StMiscFrm, IIC_iStore_d_ru,
1953 "strd", "\t$src1, $src2, [$base], $offset",
1954 "$base = $base_wb", []>;
1955 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1957 // STRT, STRBT, and STRHT are for disassembly only.
1959 def STRT : AI2stridxT<0, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
1960 IndexModePost, StFrm, IIC_iStore_ru,
1961 "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
1962 [/* For disassembly only; pattern left blank */]> {
1963 let Inst{21} = 1; // overwrite
1964 let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
1967 def STRBT : AI2stridxT<1, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
1968 IndexModePost, StFrm, IIC_iStore_bh_ru,
1969 "strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
1970 [/* For disassembly only; pattern left blank */]> {
1971 let Inst{21} = 1; // overwrite
1972 let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
1975 def STRHT: AI3sthpo<(outs GPR:$base_wb), (ins GPR:$Rt, addrmode3:$addr),
1976 StMiscFrm, IIC_iStore_bh_ru,
1977 "strht", "\t$Rt, $addr", "$addr.base = $base_wb",
1978 [/* For disassembly only; pattern left blank */]> {
1979 let Inst{21} = 1; // overwrite
1980 let AsmMatchConverter = "CvtStWriteBackRegAddrMode3";
1983 //===----------------------------------------------------------------------===//
1984 // Load / store multiple Instructions.
1987 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
1988 InstrItinClass itin, InstrItinClass itin_upd> {
1989 // IA is the default, so no need for an explicit suffix on the
1990 // mnemonic here. Without it is the cannonical spelling.
1992 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1993 IndexModeNone, f, itin,
1994 !strconcat(asm, "${p}\t$Rn, $regs"), "", []> {
1995 let Inst{24-23} = 0b01; // Increment After
1996 let Inst{21} = 0; // No writeback
1997 let Inst{20} = L_bit;
2000 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2001 IndexModeUpd, f, itin_upd,
2002 !strconcat(asm, "${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2003 let Inst{24-23} = 0b01; // Increment After
2004 let Inst{21} = 1; // Writeback
2005 let Inst{20} = L_bit;
2008 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2009 IndexModeNone, f, itin,
2010 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
2011 let Inst{24-23} = 0b00; // Decrement After
2012 let Inst{21} = 0; // No writeback
2013 let Inst{20} = L_bit;
2016 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2017 IndexModeUpd, f, itin_upd,
2018 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2019 let Inst{24-23} = 0b00; // Decrement After
2020 let Inst{21} = 1; // Writeback
2021 let Inst{20} = L_bit;
2024 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2025 IndexModeNone, f, itin,
2026 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
2027 let Inst{24-23} = 0b10; // Decrement Before
2028 let Inst{21} = 0; // No writeback
2029 let Inst{20} = L_bit;
2032 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2033 IndexModeUpd, f, itin_upd,
2034 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2035 let Inst{24-23} = 0b10; // Decrement Before
2036 let Inst{21} = 1; // Writeback
2037 let Inst{20} = L_bit;
2040 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2041 IndexModeNone, f, itin,
2042 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
2043 let Inst{24-23} = 0b11; // Increment Before
2044 let Inst{21} = 0; // No writeback
2045 let Inst{20} = L_bit;
2048 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2049 IndexModeUpd, f, itin_upd,
2050 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2051 let Inst{24-23} = 0b11; // Increment Before
2052 let Inst{21} = 1; // Writeback
2053 let Inst{20} = L_bit;
2057 let neverHasSideEffects = 1 in {
2059 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2060 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
2062 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2063 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
2065 } // neverHasSideEffects
2067 // FIXME: remove when we have a way to marking a MI with these properties.
2068 // FIXME: Should pc be an implicit operand like PICADD, etc?
2069 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2070 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2071 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2072 reglist:$regs, variable_ops),
2073 4, IIC_iLoad_mBr, [],
2074 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2075 RegConstraint<"$Rn = $wb">;
2077 //===----------------------------------------------------------------------===//
2078 // Move Instructions.
2081 let neverHasSideEffects = 1 in
2082 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2083 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2087 let Inst{19-16} = 0b0000;
2088 let Inst{11-4} = 0b00000000;
2091 let Inst{15-12} = Rd;
2094 // A version for the smaller set of tail call registers.
2095 let neverHasSideEffects = 1 in
2096 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2097 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2101 let Inst{11-4} = 0b00000000;
2104 let Inst{15-12} = Rd;
2107 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
2108 DPSoRegFrm, IIC_iMOVsr,
2109 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
2113 let Inst{15-12} = Rd;
2114 let Inst{19-16} = 0b0000;
2115 let Inst{11-0} = src;
2119 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2120 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2121 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2125 let Inst{15-12} = Rd;
2126 let Inst{19-16} = 0b0000;
2127 let Inst{11-0} = imm;
2130 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2131 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
2133 "movw", "\t$Rd, $imm",
2134 [(set GPR:$Rd, imm0_65535:$imm)]>,
2135 Requires<[IsARM, HasV6T2]>, UnaryDP {
2138 let Inst{15-12} = Rd;
2139 let Inst{11-0} = imm{11-0};
2140 let Inst{19-16} = imm{15-12};
2145 def : InstAlias<"mov${p} $Rd, $imm",
2146 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
2149 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2150 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2152 let Constraints = "$src = $Rd" in {
2153 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, imm0_65535_expr:$imm),
2155 "movt", "\t$Rd, $imm",
2157 (or (and GPR:$src, 0xffff),
2158 lo16AllZero:$imm))]>, UnaryDP,
2159 Requires<[IsARM, HasV6T2]> {
2162 let Inst{15-12} = Rd;
2163 let Inst{11-0} = imm{11-0};
2164 let Inst{19-16} = imm{15-12};
2169 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2170 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2174 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2175 Requires<[IsARM, HasV6T2]>;
2177 let Uses = [CPSR] in
2178 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2179 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2182 // These aren't really mov instructions, but we have to define them this way
2183 // due to flag operands.
2185 let Defs = [CPSR] in {
2186 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2187 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2189 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2190 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2194 //===----------------------------------------------------------------------===//
2195 // Extend Instructions.
2200 defm SXTB : AI_ext_rrot<0b01101010,
2201 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2202 defm SXTH : AI_ext_rrot<0b01101011,
2203 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2205 defm SXTAB : AI_exta_rrot<0b01101010,
2206 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2207 defm SXTAH : AI_exta_rrot<0b01101011,
2208 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2210 // For disassembly only
2211 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2213 // For disassembly only
2214 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2218 let AddedComplexity = 16 in {
2219 defm UXTB : AI_ext_rrot<0b01101110,
2220 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2221 defm UXTH : AI_ext_rrot<0b01101111,
2222 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2223 defm UXTB16 : AI_ext_rrot<0b01101100,
2224 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2226 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2227 // The transformation should probably be done as a combiner action
2228 // instead so we can include a check for masking back in the upper
2229 // eight bits of the source into the lower eight bits of the result.
2230 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2231 // (UXTB16r_rot GPR:$Src, 24)>;
2232 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2233 (UXTB16r_rot GPR:$Src, 8)>;
2235 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2236 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2237 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2238 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2241 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2242 // For disassembly only
2243 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2246 def SBFX : I<(outs GPR:$Rd),
2247 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2248 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
2249 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2250 Requires<[IsARM, HasV6T2]> {
2255 let Inst{27-21} = 0b0111101;
2256 let Inst{6-4} = 0b101;
2257 let Inst{20-16} = width;
2258 let Inst{15-12} = Rd;
2259 let Inst{11-7} = lsb;
2263 def UBFX : I<(outs GPR:$Rd),
2264 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2265 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
2266 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2267 Requires<[IsARM, HasV6T2]> {
2272 let Inst{27-21} = 0b0111111;
2273 let Inst{6-4} = 0b101;
2274 let Inst{20-16} = width;
2275 let Inst{15-12} = Rd;
2276 let Inst{11-7} = lsb;
2280 //===----------------------------------------------------------------------===//
2281 // Arithmetic Instructions.
2284 defm ADD : AsI1_bin_irs<0b0100, "add",
2285 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2286 BinOpFrag<(add node:$LHS, node:$RHS)>, "ADD", 1>;
2287 defm SUB : AsI1_bin_irs<0b0010, "sub",
2288 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2289 BinOpFrag<(sub node:$LHS, node:$RHS)>, "SUB">;
2291 // ADD and SUB with 's' bit set.
2292 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
2293 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2294 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
2295 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
2296 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2297 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
2299 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
2300 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>,
2302 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
2303 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>,
2306 // ADC and SUBC with 's' bit set.
2307 let usesCustomInserter = 1 in {
2308 defm ADCS : AI1_adde_sube_s_irs<
2309 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
2310 defm SBCS : AI1_adde_sube_s_irs<
2311 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
2314 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2315 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
2316 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
2321 let Inst{15-12} = Rd;
2322 let Inst{19-16} = Rn;
2323 let Inst{11-0} = imm;
2326 // The reg/reg form is only defined for the disassembler; for codegen it is
2327 // equivalent to SUBrr.
2328 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2329 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
2330 [/* For disassembly only; pattern left blank */]> {
2334 let Inst{11-4} = 0b00000000;
2337 let Inst{15-12} = Rd;
2338 let Inst{19-16} = Rn;
2341 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2342 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2343 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
2348 let Inst{11-0} = shift;
2349 let Inst{15-12} = Rd;
2350 let Inst{19-16} = Rn;
2353 // RSB with 's' bit set.
2354 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
2355 let usesCustomInserter = 1 in {
2356 def RSBSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2358 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]>;
2359 def RSBSrr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2361 [/* For disassembly only; pattern left blank */]>;
2362 def RSBSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2364 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]>;
2367 let Uses = [CPSR] in {
2368 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2369 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2370 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2376 let Inst{15-12} = Rd;
2377 let Inst{19-16} = Rn;
2378 let Inst{11-0} = imm;
2380 // The reg/reg form is only defined for the disassembler; for codegen it is
2381 // equivalent to SUBrr.
2382 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2383 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2384 [/* For disassembly only; pattern left blank */]> {
2388 let Inst{11-4} = 0b00000000;
2391 let Inst{15-12} = Rd;
2392 let Inst{19-16} = Rn;
2394 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2395 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2396 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2402 let Inst{11-0} = shift;
2403 let Inst{15-12} = Rd;
2404 let Inst{19-16} = Rn;
2408 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
2409 let usesCustomInserter = 1, Uses = [CPSR] in {
2410 def RSCSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2412 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>;
2413 def RSCSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2415 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>;
2418 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2419 // The assume-no-carry-in form uses the negation of the input since add/sub
2420 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2421 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2423 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2424 (SUBri GPR:$src, so_imm_neg:$imm)>;
2425 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2426 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2427 // The with-carry-in form matches bitwise not instead of the negation.
2428 // Effectively, the inverse interpretation of the carry flag already accounts
2429 // for part of the negation.
2430 def : ARMPat<(adde_dead_carry GPR:$src, so_imm_not:$imm),
2431 (SBCri GPR:$src, so_imm_not:$imm)>;
2432 def : ARMPat<(adde_live_carry GPR:$src, so_imm_not:$imm),
2433 (SBCSri GPR:$src, so_imm_not:$imm)>;
2435 // Note: These are implemented in C++ code, because they have to generate
2436 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2438 // (mul X, 2^n+1) -> (add (X << n), X)
2439 // (mul X, 2^n-1) -> (rsb X, (X << n))
2441 // ARM Arithmetic Instruction -- for disassembly only
2442 // GPR:$dst = GPR:$a op GPR:$b
2443 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2444 list<dag> pattern = [/* For disassembly only; pattern left blank */],
2445 dag iops = (ins GPR:$Rn, GPR:$Rm), string asm = "\t$Rd, $Rn, $Rm">
2446 : AI<(outs GPR:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
2450 let Inst{27-20} = op27_20;
2451 let Inst{11-4} = op11_4;
2452 let Inst{19-16} = Rn;
2453 let Inst{15-12} = Rd;
2457 // Saturating add/subtract -- for disassembly only
2459 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2460 [(set GPR:$Rd, (int_arm_qadd GPR:$Rm, GPR:$Rn))],
2461 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2462 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2463 [(set GPR:$Rd, (int_arm_qsub GPR:$Rm, GPR:$Rn))],
2464 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2465 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [], (ins GPR:$Rm, GPR:$Rn),
2467 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [], (ins GPR:$Rm, GPR:$Rn),
2470 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2471 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2472 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2473 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2474 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2475 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2476 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2477 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2478 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2479 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2480 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2481 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2483 // Signed/Unsigned add/subtract -- for disassembly only
2485 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2486 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2487 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2488 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2489 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2490 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2491 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2492 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2493 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2494 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2495 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2496 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2498 // Signed/Unsigned halving add/subtract -- for disassembly only
2500 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2501 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2502 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2503 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2504 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2505 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2506 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2507 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2508 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2509 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2510 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2511 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2513 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2515 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2516 MulFrm /* for convenience */, NoItinerary, "usad8",
2517 "\t$Rd, $Rn, $Rm", []>,
2518 Requires<[IsARM, HasV6]> {
2522 let Inst{27-20} = 0b01111000;
2523 let Inst{15-12} = 0b1111;
2524 let Inst{7-4} = 0b0001;
2525 let Inst{19-16} = Rd;
2526 let Inst{11-8} = Rm;
2529 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2530 MulFrm /* for convenience */, NoItinerary, "usada8",
2531 "\t$Rd, $Rn, $Rm, $Ra", []>,
2532 Requires<[IsARM, HasV6]> {
2537 let Inst{27-20} = 0b01111000;
2538 let Inst{7-4} = 0b0001;
2539 let Inst{19-16} = Rd;
2540 let Inst{15-12} = Ra;
2541 let Inst{11-8} = Rm;
2545 // Signed/Unsigned saturate -- for disassembly only
2547 def SSAT : AI<(outs GPR:$Rd), (ins ssat_imm:$sat_imm, GPR:$a, shift_imm:$sh),
2548 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2549 [/* For disassembly only; pattern left blank */]> {
2554 let Inst{27-21} = 0b0110101;
2555 let Inst{5-4} = 0b01;
2556 let Inst{20-16} = sat_imm;
2557 let Inst{15-12} = Rd;
2558 let Inst{11-7} = sh{7-3};
2559 let Inst{6} = sh{0};
2563 def SSAT16 : AI<(outs GPR:$Rd), (ins ssat_imm:$sat_imm, GPR:$Rn), SatFrm,
2564 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2565 [/* For disassembly only; pattern left blank */]> {
2569 let Inst{27-20} = 0b01101010;
2570 let Inst{11-4} = 0b11110011;
2571 let Inst{15-12} = Rd;
2572 let Inst{19-16} = sat_imm;
2576 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2577 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2578 [/* For disassembly only; pattern left blank */]> {
2583 let Inst{27-21} = 0b0110111;
2584 let Inst{5-4} = 0b01;
2585 let Inst{15-12} = Rd;
2586 let Inst{11-7} = sh{7-3};
2587 let Inst{6} = sh{0};
2588 let Inst{20-16} = sat_imm;
2592 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2593 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2594 [/* For disassembly only; pattern left blank */]> {
2598 let Inst{27-20} = 0b01101110;
2599 let Inst{11-4} = 0b11110011;
2600 let Inst{15-12} = Rd;
2601 let Inst{19-16} = sat_imm;
2605 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2606 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2608 //===----------------------------------------------------------------------===//
2609 // Bitwise Instructions.
2612 defm AND : AsI1_bin_irs<0b0000, "and",
2613 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2614 BinOpFrag<(and node:$LHS, node:$RHS)>, "AND", 1>;
2615 defm ORR : AsI1_bin_irs<0b1100, "orr",
2616 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2617 BinOpFrag<(or node:$LHS, node:$RHS)>, "ORR", 1>;
2618 defm EOR : AsI1_bin_irs<0b0001, "eor",
2619 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2620 BinOpFrag<(xor node:$LHS, node:$RHS)>, "EOR", 1>;
2621 defm BIC : AsI1_bin_irs<0b1110, "bic",
2622 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2623 BinOpFrag<(and node:$LHS, (not node:$RHS))>, "BIC">;
2625 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2626 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
2627 "bfc", "\t$Rd, $imm", "$src = $Rd",
2628 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2629 Requires<[IsARM, HasV6T2]> {
2632 let Inst{27-21} = 0b0111110;
2633 let Inst{6-0} = 0b0011111;
2634 let Inst{15-12} = Rd;
2635 let Inst{11-7} = imm{4-0}; // lsb
2636 let Inst{20-16} = imm{9-5}; // width
2639 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2640 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2641 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
2642 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2643 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2644 bf_inv_mask_imm:$imm))]>,
2645 Requires<[IsARM, HasV6T2]> {
2649 let Inst{27-21} = 0b0111110;
2650 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2651 let Inst{15-12} = Rd;
2652 let Inst{11-7} = imm{4-0}; // lsb
2653 let Inst{20-16} = imm{9-5}; // width
2657 // GNU as only supports this form of bfi (w/ 4 arguments)
2658 let isAsmParserOnly = 1 in
2659 def BFI4p : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn,
2660 lsb_pos_imm:$lsb, width_imm:$width),
2661 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
2662 "bfi", "\t$Rd, $Rn, $lsb, $width", "$src = $Rd",
2663 []>, Requires<[IsARM, HasV6T2]> {
2668 let Inst{27-21} = 0b0111110;
2669 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2670 let Inst{15-12} = Rd;
2671 let Inst{11-7} = lsb;
2672 let Inst{20-16} = width; // Custom encoder => lsb+width-1
2676 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2677 "mvn", "\t$Rd, $Rm",
2678 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2682 let Inst{19-16} = 0b0000;
2683 let Inst{11-4} = 0b00000000;
2684 let Inst{15-12} = Rd;
2687 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2688 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2689 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2693 let Inst{19-16} = 0b0000;
2694 let Inst{15-12} = Rd;
2695 let Inst{11-0} = shift;
2697 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2698 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2699 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2700 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2704 let Inst{19-16} = 0b0000;
2705 let Inst{15-12} = Rd;
2706 let Inst{11-0} = imm;
2709 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2710 (BICri GPR:$src, so_imm_not:$imm)>;
2712 //===----------------------------------------------------------------------===//
2713 // Multiply Instructions.
2715 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2716 string opc, string asm, list<dag> pattern>
2717 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2721 let Inst{19-16} = Rd;
2722 let Inst{11-8} = Rm;
2725 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2726 string opc, string asm, list<dag> pattern>
2727 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2732 let Inst{19-16} = RdHi;
2733 let Inst{15-12} = RdLo;
2734 let Inst{11-8} = Rm;
2738 // FIXME: The v5 pseudos are only necessary for the additional Constraint
2739 // property. Remove them when it's possible to add those properties
2740 // on an individual MachineInstr, not just an instuction description.
2741 let isCommutable = 1 in {
2742 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2743 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2744 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2745 Requires<[IsARM, HasV6]> {
2746 let Inst{15-12} = 0b0000;
2749 let Constraints = "@earlyclobber $Rd" in
2750 def MULv5: ARMPseudoExpand<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
2751 pred:$p, cc_out:$s),
2753 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))],
2754 (MUL GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
2755 Requires<[IsARM, NoV6]>;
2758 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2759 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2760 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2761 Requires<[IsARM, HasV6]> {
2763 let Inst{15-12} = Ra;
2766 let Constraints = "@earlyclobber $Rd" in
2767 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
2768 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
2770 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
2771 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
2772 Requires<[IsARM, NoV6]>;
2774 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2775 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
2776 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
2777 Requires<[IsARM, HasV6T2]> {
2782 let Inst{19-16} = Rd;
2783 let Inst{15-12} = Ra;
2784 let Inst{11-8} = Rm;
2788 // Extra precision multiplies with low / high results
2789 let neverHasSideEffects = 1 in {
2790 let isCommutable = 1 in {
2791 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2792 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2793 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2794 Requires<[IsARM, HasV6]>;
2796 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2797 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2798 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2799 Requires<[IsARM, HasV6]>;
2801 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2802 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
2803 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2805 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
2806 Requires<[IsARM, NoV6]>;
2808 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
2809 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2811 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
2812 Requires<[IsARM, NoV6]>;
2816 // Multiply + accumulate
2817 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2818 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2819 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2820 Requires<[IsARM, HasV6]>;
2821 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2822 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2823 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2824 Requires<[IsARM, HasV6]>;
2826 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2827 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2828 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2829 Requires<[IsARM, HasV6]> {
2834 let Inst{19-16} = RdLo;
2835 let Inst{15-12} = RdHi;
2836 let Inst{11-8} = Rm;
2840 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2841 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
2842 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2844 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
2845 Requires<[IsARM, NoV6]>;
2846 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
2847 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2849 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
2850 Requires<[IsARM, NoV6]>;
2851 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
2852 (ins GPR:$Rn, GPR:$Rm, pred:$p),
2854 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
2855 Requires<[IsARM, NoV6]>;
2858 } // neverHasSideEffects
2860 // Most significant word multiply
2861 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2862 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2863 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2864 Requires<[IsARM, HasV6]> {
2865 let Inst{15-12} = 0b1111;
2868 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2869 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2870 [/* For disassembly only; pattern left blank */]>,
2871 Requires<[IsARM, HasV6]> {
2872 let Inst{15-12} = 0b1111;
2875 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2876 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2877 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2878 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2879 Requires<[IsARM, HasV6]>;
2881 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2882 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2883 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2884 [/* For disassembly only; pattern left blank */]>,
2885 Requires<[IsARM, HasV6]>;
2887 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2888 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2889 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2890 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2891 Requires<[IsARM, HasV6]>;
2893 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2894 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2895 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2896 [/* For disassembly only; pattern left blank */]>,
2897 Requires<[IsARM, HasV6]>;
2899 multiclass AI_smul<string opc, PatFrag opnode> {
2900 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2901 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2902 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2903 (sext_inreg GPR:$Rm, i16)))]>,
2904 Requires<[IsARM, HasV5TE]>;
2906 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2907 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2908 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2909 (sra GPR:$Rm, (i32 16))))]>,
2910 Requires<[IsARM, HasV5TE]>;
2912 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2913 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2914 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2915 (sext_inreg GPR:$Rm, i16)))]>,
2916 Requires<[IsARM, HasV5TE]>;
2918 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2919 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2920 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2921 (sra GPR:$Rm, (i32 16))))]>,
2922 Requires<[IsARM, HasV5TE]>;
2924 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2925 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2926 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2927 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2928 Requires<[IsARM, HasV5TE]>;
2930 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2931 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2932 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2933 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2934 Requires<[IsARM, HasV5TE]>;
2938 multiclass AI_smla<string opc, PatFrag opnode> {
2939 def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
2940 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2941 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2942 [(set GPR:$Rd, (add GPR:$Ra,
2943 (opnode (sext_inreg GPR:$Rn, i16),
2944 (sext_inreg GPR:$Rm, i16))))]>,
2945 Requires<[IsARM, HasV5TE]>;
2947 def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd),
2948 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2949 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2950 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2951 (sra GPR:$Rm, (i32 16)))))]>,
2952 Requires<[IsARM, HasV5TE]>;
2954 def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd),
2955 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2956 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2957 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2958 (sext_inreg GPR:$Rm, i16))))]>,
2959 Requires<[IsARM, HasV5TE]>;
2961 def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
2962 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2963 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2964 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2965 (sra GPR:$Rm, (i32 16)))))]>,
2966 Requires<[IsARM, HasV5TE]>;
2968 def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd),
2969 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2970 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2971 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2972 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2973 Requires<[IsARM, HasV5TE]>;
2975 def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd),
2976 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2977 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2978 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2979 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2980 Requires<[IsARM, HasV5TE]>;
2983 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2984 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2986 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2987 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2988 (ins GPR:$Rn, GPR:$Rm),
2989 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2990 [/* For disassembly only; pattern left blank */]>,
2991 Requires<[IsARM, HasV5TE]>;
2993 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2994 (ins GPR:$Rn, GPR:$Rm),
2995 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2996 [/* For disassembly only; pattern left blank */]>,
2997 Requires<[IsARM, HasV5TE]>;
2999 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
3000 (ins GPR:$Rn, GPR:$Rm),
3001 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
3002 [/* For disassembly only; pattern left blank */]>,
3003 Requires<[IsARM, HasV5TE]>;
3005 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
3006 (ins GPR:$Rn, GPR:$Rm),
3007 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
3008 [/* For disassembly only; pattern left blank */]>,
3009 Requires<[IsARM, HasV5TE]>;
3011 // Helper class for AI_smld -- for disassembly only
3012 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3013 InstrItinClass itin, string opc, string asm>
3014 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3021 let Inst{21-20} = 0b00;
3022 let Inst{22} = long;
3023 let Inst{27-23} = 0b01110;
3024 let Inst{11-8} = Rm;
3027 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3028 InstrItinClass itin, string opc, string asm>
3029 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3031 let Inst{15-12} = 0b1111;
3032 let Inst{19-16} = Rd;
3034 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3035 InstrItinClass itin, string opc, string asm>
3036 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3038 let Inst{15-12} = Ra;
3040 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3041 InstrItinClass itin, string opc, string asm>
3042 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3045 let Inst{19-16} = RdHi;
3046 let Inst{15-12} = RdLo;
3049 multiclass AI_smld<bit sub, string opc> {
3051 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3052 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3054 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3055 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3057 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
3058 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
3059 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3061 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
3062 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
3063 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3067 defm SMLA : AI_smld<0, "smla">;
3068 defm SMLS : AI_smld<1, "smls">;
3070 multiclass AI_sdml<bit sub, string opc> {
3072 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3073 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3074 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3075 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3078 defm SMUA : AI_sdml<0, "smua">;
3079 defm SMUS : AI_sdml<1, "smus">;
3081 //===----------------------------------------------------------------------===//
3082 // Misc. Arithmetic Instructions.
3085 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3086 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3087 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3089 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3090 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3091 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3092 Requires<[IsARM, HasV6T2]>;
3094 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3095 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3096 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3098 let AddedComplexity = 5 in
3099 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3100 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3101 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3102 Requires<[IsARM, HasV6]>;
3104 let AddedComplexity = 5 in
3105 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3106 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3107 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3108 Requires<[IsARM, HasV6]>;
3110 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3111 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3114 def lsl_shift_imm : SDNodeXForm<imm, [{
3115 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
3116 return CurDAG->getTargetConstant(Sh, MVT::i32);
3119 def lsl_amt : ImmLeaf<i32, [{
3120 return Imm > 0 && Imm < 32;
3123 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
3124 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3125 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3126 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
3127 (and (shl GPR:$Rm, lsl_amt:$sh),
3129 Requires<[IsARM, HasV6]>;
3131 // Alternate cases for PKHBT where identities eliminate some nodes.
3132 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
3133 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
3134 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
3135 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
3137 def asr_shift_imm : SDNodeXForm<imm, [{
3138 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
3139 return CurDAG->getTargetConstant(Sh, MVT::i32);
3142 def asr_amt : ImmLeaf<i32, [{
3143 return Imm > 0 && Imm <= 32;
3146 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3147 // will match the pattern below.
3148 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
3149 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3150 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3151 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
3152 (and (sra GPR:$Rm, asr_amt:$sh),
3154 Requires<[IsARM, HasV6]>;
3156 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3157 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3158 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
3159 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
3160 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
3161 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
3162 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
3164 //===----------------------------------------------------------------------===//
3165 // Comparison Instructions...
3168 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3169 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3170 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3172 // ARMcmpZ can re-use the above instruction definitions.
3173 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3174 (CMPri GPR:$src, so_imm:$imm)>;
3175 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3176 (CMPrr GPR:$src, GPR:$rhs)>;
3177 def : ARMPat<(ARMcmpZ GPR:$src, so_reg:$rhs),
3178 (CMPrs GPR:$src, so_reg:$rhs)>;
3180 // FIXME: We have to be careful when using the CMN instruction and comparison
3181 // with 0. One would expect these two pieces of code should give identical
3197 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3198 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3199 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3200 // value of r0 and the carry bit (because the "carry bit" parameter to
3201 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3202 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3203 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3204 // parameter to AddWithCarry is defined as 0).
3206 // When x is 0 and unsigned:
3210 // ~x + 1 = 0x1 0000 0000
3211 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3213 // Therefore, we should disable CMN when comparing against zero, until we can
3214 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3215 // when it's a comparison which doesn't look at the 'carry' flag).
3217 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3219 // This is related to <rdar://problem/7569620>.
3221 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3222 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3224 // Note that TST/TEQ don't set all the same flags that CMP does!
3225 defm TST : AI1_cmp_irs<0b1000, "tst",
3226 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3227 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3228 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3229 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3230 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3232 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
3233 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3234 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
3236 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3237 // (CMNri GPR:$src, so_imm_neg:$imm)>;
3239 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3240 (CMNzri GPR:$src, so_imm_neg:$imm)>;
3242 // Pseudo i64 compares for some floating point compares.
3243 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3245 def BCCi64 : PseudoInst<(outs),
3246 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3248 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3250 def BCCZi64 : PseudoInst<(outs),
3251 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3252 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3253 } // usesCustomInserter
3256 // Conditional moves
3257 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3258 // a two-value operand where a dag node expects two operands. :(
3259 let neverHasSideEffects = 1 in {
3260 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3262 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3263 RegConstraint<"$false = $Rd">;
3264 def MOVCCs : ARMPseudoInst<(outs GPR:$Rd),
3265 (ins GPR:$false, so_reg:$shift, pred:$p),
3267 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
3268 RegConstraint<"$false = $Rd">;
3270 let isMoveImm = 1 in
3271 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3272 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
3275 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3277 let isMoveImm = 1 in
3278 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3279 (ins GPR:$false, so_imm:$imm, pred:$p),
3281 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3282 RegConstraint<"$false = $Rd">;
3284 // Two instruction predicate mov immediate.
3285 let isMoveImm = 1 in
3286 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
3287 (ins GPR:$false, i32imm:$src, pred:$p),
3288 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3290 let isMoveImm = 1 in
3291 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
3292 (ins GPR:$false, so_imm:$imm, pred:$p),
3294 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3295 RegConstraint<"$false = $Rd">;
3296 } // neverHasSideEffects
3298 //===----------------------------------------------------------------------===//
3299 // Atomic operations intrinsics
3302 def memb_opt : Operand<i32> {
3303 let PrintMethod = "printMemBOption";
3304 let ParserMatchClass = MemBarrierOptOperand;
3307 // memory barriers protect the atomic sequences
3308 let hasSideEffects = 1 in {
3309 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3310 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3311 Requires<[IsARM, HasDB]> {
3313 let Inst{31-4} = 0xf57ff05;
3314 let Inst{3-0} = opt;
3318 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3319 "dsb", "\t$opt", []>,
3320 Requires<[IsARM, HasDB]> {
3322 let Inst{31-4} = 0xf57ff04;
3323 let Inst{3-0} = opt;
3326 // ISB has only full system option
3327 def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3328 "isb", "\t$opt", []>,
3329 Requires<[IsARM, HasDB]> {
3331 let Inst{31-4} = 0xf57ff06;
3332 let Inst{3-0} = opt;
3335 let usesCustomInserter = 1 in {
3336 let Uses = [CPSR] in {
3337 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
3338 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3339 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
3340 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
3341 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3342 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
3343 def ATOMIC_LOAD_AND_I8 : PseudoInst<
3344 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3345 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
3346 def ATOMIC_LOAD_OR_I8 : PseudoInst<
3347 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3348 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
3349 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
3350 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3351 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
3352 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
3353 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3354 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
3355 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
3356 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3357 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
3358 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
3359 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3360 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
3361 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
3362 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3363 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
3364 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
3365 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3366 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
3367 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
3368 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3369 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
3370 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
3371 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3372 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
3373 def ATOMIC_LOAD_AND_I16 : PseudoInst<
3374 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3375 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
3376 def ATOMIC_LOAD_OR_I16 : PseudoInst<
3377 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3378 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
3379 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
3380 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3381 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
3382 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
3383 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3384 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
3385 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
3386 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3387 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
3388 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
3389 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3390 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
3391 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
3392 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3393 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
3394 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
3395 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3396 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
3397 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
3398 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3399 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
3400 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
3401 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3402 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
3403 def ATOMIC_LOAD_AND_I32 : PseudoInst<
3404 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3405 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
3406 def ATOMIC_LOAD_OR_I32 : PseudoInst<
3407 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3408 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
3409 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
3410 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3411 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
3412 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
3413 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3414 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
3415 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
3416 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3417 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
3418 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
3419 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3420 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
3421 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
3422 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3423 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
3424 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
3425 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3426 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
3428 def ATOMIC_SWAP_I8 : PseudoInst<
3429 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3430 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3431 def ATOMIC_SWAP_I16 : PseudoInst<
3432 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3433 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3434 def ATOMIC_SWAP_I32 : PseudoInst<
3435 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3436 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3438 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3439 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3440 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3441 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3442 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3443 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3444 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3445 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3446 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3450 let mayLoad = 1 in {
3451 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3452 "ldrexb", "\t$Rt, $addr", []>;
3453 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3454 "ldrexh", "\t$Rt, $addr", []>;
3455 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3456 "ldrex", "\t$Rt, $addr", []>;
3457 let hasExtraDefRegAllocReq = 1 in
3458 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode7:$addr),
3459 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []>;
3462 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3463 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3464 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
3465 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3466 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
3467 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3468 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
3471 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
3472 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3473 (ins GPR:$Rt, GPR:$Rt2, addrmode7:$addr),
3474 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []>;
3476 // Clear-Exclusive is for disassembly only.
3477 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3478 [/* For disassembly only; pattern left blank */]>,
3479 Requires<[IsARM, HasV7]> {
3480 let Inst{31-0} = 0b11110101011111111111000000011111;
3483 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3484 let mayLoad = 1 in {
3485 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3486 [/* For disassembly only; pattern left blank */]>;
3487 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3488 [/* For disassembly only; pattern left blank */]>;
3491 //===----------------------------------------------------------------------===//
3492 // Coprocessor Instructions.
3495 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3496 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3497 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3498 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3499 imm:$CRm, imm:$opc2)]> {
3507 let Inst{3-0} = CRm;
3509 let Inst{7-5} = opc2;
3510 let Inst{11-8} = cop;
3511 let Inst{15-12} = CRd;
3512 let Inst{19-16} = CRn;
3513 let Inst{23-20} = opc1;
3516 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3517 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3518 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3519 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3520 imm:$CRm, imm:$opc2)]> {
3521 let Inst{31-28} = 0b1111;
3529 let Inst{3-0} = CRm;
3531 let Inst{7-5} = opc2;
3532 let Inst{11-8} = cop;
3533 let Inst{15-12} = CRd;
3534 let Inst{19-16} = CRn;
3535 let Inst{23-20} = opc1;
3538 class ACI<dag oops, dag iops, string opc, string asm,
3539 IndexMode im = IndexModeNone>
3540 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
3541 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3542 let Inst{27-25} = 0b110;
3545 multiclass LdStCop<bits<4> op31_28, bit load, dag ops, string opc, string cond>{
3547 def _OFFSET : ACI<(outs),
3548 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3549 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr"> {
3550 let Inst{31-28} = op31_28;
3551 let Inst{24} = 1; // P = 1
3552 let Inst{21} = 0; // W = 0
3553 let Inst{22} = 0; // D = 0
3554 let Inst{20} = load;
3557 def _PRE : ACI<(outs),
3558 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3559 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr!", IndexModePre> {
3560 let Inst{31-28} = op31_28;
3561 let Inst{24} = 1; // P = 1
3562 let Inst{21} = 1; // W = 1
3563 let Inst{22} = 0; // D = 0
3564 let Inst{20} = load;
3567 def _POST : ACI<(outs),
3568 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3569 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr", IndexModePost> {
3570 let Inst{31-28} = op31_28;
3571 let Inst{24} = 0; // P = 0
3572 let Inst{21} = 1; // W = 1
3573 let Inst{22} = 0; // D = 0
3574 let Inst{20} = load;
3577 def _OPTION : ACI<(outs),
3578 !con((ins nohash_imm:$cop,nohash_imm:$CRd,GPR:$base, nohash_imm:$option),
3580 !strconcat(opc, cond), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3581 let Inst{31-28} = op31_28;
3582 let Inst{24} = 0; // P = 0
3583 let Inst{23} = 1; // U = 1
3584 let Inst{21} = 0; // W = 0
3585 let Inst{22} = 0; // D = 0
3586 let Inst{20} = load;
3589 def L_OFFSET : ACI<(outs),
3590 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3591 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr"> {
3592 let Inst{31-28} = op31_28;
3593 let Inst{24} = 1; // P = 1
3594 let Inst{21} = 0; // W = 0
3595 let Inst{22} = 1; // D = 1
3596 let Inst{20} = load;
3599 def L_PRE : ACI<(outs),
3600 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3601 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr!",
3603 let Inst{31-28} = op31_28;
3604 let Inst{24} = 1; // P = 1
3605 let Inst{21} = 1; // W = 1
3606 let Inst{22} = 1; // D = 1
3607 let Inst{20} = load;
3610 def L_POST : ACI<(outs),
3611 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3612 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr",
3614 let Inst{31-28} = op31_28;
3615 let Inst{24} = 0; // P = 0
3616 let Inst{21} = 1; // W = 1
3617 let Inst{22} = 1; // D = 1
3618 let Inst{20} = load;
3621 def L_OPTION : ACI<(outs),
3622 !con((ins nohash_imm:$cop, nohash_imm:$CRd,GPR:$base,nohash_imm:$option),
3624 !strconcat(!strconcat(opc, "l"), cond),
3625 "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3626 let Inst{31-28} = op31_28;
3627 let Inst{24} = 0; // P = 0
3628 let Inst{23} = 1; // U = 1
3629 let Inst{21} = 0; // W = 0
3630 let Inst{22} = 1; // D = 1
3631 let Inst{20} = load;
3635 defm LDC : LdStCop<{?,?,?,?}, 1, (ins pred:$p), "ldc", "${p}">;
3636 defm LDC2 : LdStCop<0b1111, 1, (ins), "ldc2", "">;
3637 defm STC : LdStCop<{?,?,?,?}, 0, (ins pred:$p), "stc", "${p}">;
3638 defm STC2 : LdStCop<0b1111, 0, (ins), "stc2", "">;
3640 //===----------------------------------------------------------------------===//
3641 // Move between coprocessor and ARM core register -- for disassembly only
3644 class MovRCopro<string opc, bit direction, dag oops, dag iops,
3646 : ABI<0b1110, oops, iops, NoItinerary, opc,
3647 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
3648 let Inst{20} = direction;
3658 let Inst{15-12} = Rt;
3659 let Inst{11-8} = cop;
3660 let Inst{23-21} = opc1;
3661 let Inst{7-5} = opc2;
3662 let Inst{3-0} = CRm;
3663 let Inst{19-16} = CRn;
3666 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
3668 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3669 c_imm:$CRm, imm0_7:$opc2),
3670 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3671 imm:$CRm, imm:$opc2)]>;
3672 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
3674 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
3677 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3678 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3680 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
3682 : ABXI<0b1110, oops, iops, NoItinerary,
3683 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
3684 let Inst{31-28} = 0b1111;
3685 let Inst{20} = direction;
3695 let Inst{15-12} = Rt;
3696 let Inst{11-8} = cop;
3697 let Inst{23-21} = opc1;
3698 let Inst{7-5} = opc2;
3699 let Inst{3-0} = CRm;
3700 let Inst{19-16} = CRn;
3703 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
3705 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3706 c_imm:$CRm, imm0_7:$opc2),
3707 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3708 imm:$CRm, imm:$opc2)]>;
3709 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
3711 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
3714 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
3715 imm:$CRm, imm:$opc2),
3716 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3718 class MovRRCopro<string opc, bit direction,
3719 list<dag> pattern = [/* For disassembly only */]>
3720 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3721 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3722 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
3723 let Inst{23-21} = 0b010;
3724 let Inst{20} = direction;
3732 let Inst{15-12} = Rt;
3733 let Inst{19-16} = Rt2;
3734 let Inst{11-8} = cop;
3735 let Inst{7-4} = opc1;
3736 let Inst{3-0} = CRm;
3739 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
3740 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3742 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
3744 class MovRRCopro2<string opc, bit direction,
3745 list<dag> pattern = [/* For disassembly only */]>
3746 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3747 GPR:$Rt, GPR:$Rt2, c_imm:$CRm), NoItinerary,
3748 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3749 let Inst{31-28} = 0b1111;
3750 let Inst{23-21} = 0b010;
3751 let Inst{20} = direction;
3759 let Inst{15-12} = Rt;
3760 let Inst{19-16} = Rt2;
3761 let Inst{11-8} = cop;
3762 let Inst{7-4} = opc1;
3763 let Inst{3-0} = CRm;
3766 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
3767 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3769 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
3771 //===----------------------------------------------------------------------===//
3772 // Move between special register and ARM core register -- for disassembly only
3775 // Move to ARM core register from Special Register
3776 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3777 [/* For disassembly only; pattern left blank */]> {
3779 let Inst{23-16} = 0b00001111;
3780 let Inst{15-12} = Rd;
3781 let Inst{7-4} = 0b0000;
3784 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,"mrs","\t$Rd, spsr",
3785 [/* For disassembly only; pattern left blank */]> {
3787 let Inst{23-16} = 0b01001111;
3788 let Inst{15-12} = Rd;
3789 let Inst{7-4} = 0b0000;
3792 // Move from ARM core register to Special Register
3794 // No need to have both system and application versions, the encodings are the
3795 // same and the assembly parser has no way to distinguish between them. The mask
3796 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3797 // the mask with the fields to be accessed in the special register.
3798 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
3799 "msr", "\t$mask, $Rn",
3800 [/* For disassembly only; pattern left blank */]> {
3805 let Inst{22} = mask{4}; // R bit
3806 let Inst{21-20} = 0b10;
3807 let Inst{19-16} = mask{3-0};
3808 let Inst{15-12} = 0b1111;
3809 let Inst{11-4} = 0b00000000;
3813 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
3814 "msr", "\t$mask, $a",
3815 [/* For disassembly only; pattern left blank */]> {
3820 let Inst{22} = mask{4}; // R bit
3821 let Inst{21-20} = 0b10;
3822 let Inst{19-16} = mask{3-0};
3823 let Inst{15-12} = 0b1111;
3827 //===----------------------------------------------------------------------===//
3831 // __aeabi_read_tp preserves the registers r1-r3.
3832 // This is a pseudo inst so that we can get the encoding right,
3833 // complete with fixup for the aeabi_read_tp function.
3835 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
3836 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
3837 [(set R0, ARMthread_pointer)]>;
3840 //===----------------------------------------------------------------------===//
3841 // SJLJ Exception handling intrinsics
3842 // eh_sjlj_setjmp() is an instruction sequence to store the return
3843 // address and save #0 in R0 for the non-longjmp case.
3844 // Since by its nature we may be coming from some other function to get
3845 // here, and we're using the stack frame for the containing function to
3846 // save/restore registers, we can't keep anything live in regs across
3847 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3848 // when we get here from a longjmp(). We force everything out of registers
3849 // except for our own input by listing the relevant registers in Defs. By
3850 // doing so, we also cause the prologue/epilogue code to actively preserve
3851 // all of the callee-saved resgisters, which is exactly what we want.
3852 // A constant value is passed in $val, and we use the location as a scratch.
3854 // These are pseudo-instructions and are lowered to individual MC-insts, so
3855 // no encoding information is necessary.
3857 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
3858 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ], hasSideEffects = 1, isBarrier = 1 in {
3859 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3861 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3862 Requires<[IsARM, HasVFP2]>;
3866 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
3867 hasSideEffects = 1, isBarrier = 1 in {
3868 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3870 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3871 Requires<[IsARM, NoVFP]>;
3874 // FIXME: Non-Darwin version(s)
3875 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3876 Defs = [ R7, LR, SP ] in {
3877 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
3879 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3880 Requires<[IsARM, IsDarwin]>;
3883 // eh.sjlj.dispatchsetup pseudo-instruction.
3884 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3885 // handled when the pseudo is expanded (which happens before any passes
3886 // that need the instruction size).
3887 let isBarrier = 1, hasSideEffects = 1 in
3888 def Int_eh_sjlj_dispatchsetup :
3889 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
3890 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
3891 Requires<[IsDarwin]>;
3893 //===----------------------------------------------------------------------===//
3894 // Non-Instruction Patterns
3897 // ARMv4 indirect branch using (MOVr PC, dst)
3898 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
3899 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
3900 4, IIC_Br, [(brind GPR:$dst)],
3901 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
3902 Requires<[IsARM, NoV4T]>;
3904 // Large immediate handling.
3906 // 32-bit immediate using two piece so_imms or movw + movt.
3907 // This is a single pseudo instruction, the benefit is that it can be remat'd
3908 // as a single unit instead of having to handle reg inputs.
3909 // FIXME: Remove this when we can do generalized remat.
3910 let isReMaterializable = 1, isMoveImm = 1 in
3911 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3912 [(set GPR:$dst, (arm_i32imm:$src))]>,
3915 // Pseudo instruction that combines movw + movt + add pc (if PIC).
3916 // It also makes it possible to rematerialize the instructions.
3917 // FIXME: Remove this when we can do generalized remat and when machine licm
3918 // can properly the instructions.
3919 let isReMaterializable = 1 in {
3920 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3922 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3923 Requires<[IsARM, UseMovt]>;
3925 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3927 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3928 Requires<[IsARM, UseMovt]>;
3930 let AddedComplexity = 10 in
3931 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3933 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
3934 Requires<[IsARM, UseMovt]>;
3935 } // isReMaterializable
3937 // ConstantPool, GlobalAddress, and JumpTable
3938 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3939 Requires<[IsARM, DontUseMovt]>;
3940 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3941 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3942 Requires<[IsARM, UseMovt]>;
3943 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3944 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3946 // TODO: add,sub,and, 3-instr forms?
3949 def : ARMPat<(ARMtcret tcGPR:$dst),
3950 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3952 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3953 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3955 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3956 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3958 def : ARMPat<(ARMtcret tcGPR:$dst),
3959 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3961 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3962 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3964 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3965 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3968 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3969 Requires<[IsARM, IsNotDarwin]>;
3970 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3971 Requires<[IsARM, IsDarwin]>;
3973 // zextload i1 -> zextload i8
3974 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3975 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3977 // extload -> zextload
3978 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3979 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3980 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3981 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3983 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3985 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3986 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3989 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3990 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3991 (SMULBB GPR:$a, GPR:$b)>;
3992 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3993 (SMULBB GPR:$a, GPR:$b)>;
3994 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3995 (sra GPR:$b, (i32 16))),
3996 (SMULBT GPR:$a, GPR:$b)>;
3997 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3998 (SMULBT GPR:$a, GPR:$b)>;
3999 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4000 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4001 (SMULTB GPR:$a, GPR:$b)>;
4002 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
4003 (SMULTB GPR:$a, GPR:$b)>;
4004 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4006 (SMULWB GPR:$a, GPR:$b)>;
4007 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
4008 (SMULWB GPR:$a, GPR:$b)>;
4010 def : ARMV5TEPat<(add GPR:$acc,
4011 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4012 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4013 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4014 def : ARMV5TEPat<(add GPR:$acc,
4015 (mul sext_16_node:$a, sext_16_node:$b)),
4016 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4017 def : ARMV5TEPat<(add GPR:$acc,
4018 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4019 (sra GPR:$b, (i32 16)))),
4020 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4021 def : ARMV5TEPat<(add GPR:$acc,
4022 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
4023 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4024 def : ARMV5TEPat<(add GPR:$acc,
4025 (mul (sra GPR:$a, (i32 16)),
4026 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4027 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4028 def : ARMV5TEPat<(add GPR:$acc,
4029 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
4030 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4031 def : ARMV5TEPat<(add GPR:$acc,
4032 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4034 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4035 def : ARMV5TEPat<(add GPR:$acc,
4036 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
4037 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4040 // Pre-v7 uses MCR for synchronization barriers.
4041 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
4042 Requires<[IsARM, HasV6]>;
4045 //===----------------------------------------------------------------------===//
4049 include "ARMInstrThumb.td"
4051 //===----------------------------------------------------------------------===//
4055 include "ARMInstrThumb2.td"
4057 //===----------------------------------------------------------------------===//
4058 // Floating Point Support
4061 include "ARMInstrVFP.td"
4063 //===----------------------------------------------------------------------===//
4064 // Advanced SIMD (NEON) Support
4067 include "ARMInstrNEON.td"
4069 //===----------------------------------------------------------------------===//
4070 // Assembler aliases
4074 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
4075 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
4076 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
4078 // System instructions
4079 def : MnemonicAlias<"swi", "svc">;
4081 // Load / Store Multiple
4082 def : MnemonicAlias<"ldmfd", "ldm">;
4083 def : MnemonicAlias<"ldmia", "ldm">;
4084 def : MnemonicAlias<"stmfd", "stmdb">;
4085 def : MnemonicAlias<"stmia", "stm">;
4086 def : MnemonicAlias<"stmea", "stm">;