1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
67 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
68 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
72 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
74 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
75 [SDNPHasChain, SDNPOutFlag]>;
76 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
77 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
79 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
80 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
82 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
83 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
85 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
86 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
89 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
90 [SDNPHasChain, SDNPOptInFlag]>;
92 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
94 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
97 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
98 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
100 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
102 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
105 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
108 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
111 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
112 [SDNPOutFlag, SDNPCommutative]>;
114 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
116 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
117 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
118 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
120 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
121 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
122 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
123 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
124 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
125 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
126 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
129 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
131 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
134 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
136 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
137 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
140 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
142 //===----------------------------------------------------------------------===//
143 // ARM Instruction Predicate Definitions.
145 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
146 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
147 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
148 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
149 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
150 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
151 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
152 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
153 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
154 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
155 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
156 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
157 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
158 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
160 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
162 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
163 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
164 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
165 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
166 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
167 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
168 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
169 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
171 // FIXME: Eventually this will be just "hasV6T2Ops".
172 def UseMovt : Predicate<"Subtarget->useMovt()">;
173 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
174 def UseVMLx : Predicate<"Subtarget->useVMLx()">;
176 //===----------------------------------------------------------------------===//
177 // ARM Flag Definitions.
179 class RegConstraint<string C> {
180 string Constraints = C;
183 //===----------------------------------------------------------------------===//
184 // ARM specific transformation functions and pattern fragments.
187 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
188 // so_imm_neg def below.
189 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
190 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
193 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
194 // so_imm_not def below.
195 def so_imm_not_XFORM : SDNodeXForm<imm, [{
196 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
199 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
200 def imm1_15 : PatLeaf<(i32 imm), [{
201 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
204 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
205 def imm16_31 : PatLeaf<(i32 imm), [{
206 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
211 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
212 }], so_imm_neg_XFORM>;
216 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
217 }], so_imm_not_XFORM>;
219 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
220 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
221 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
224 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
226 def bf_inv_mask_imm : Operand<i32>,
228 return ARM::isBitFieldInvertedMask(N->getZExtValue());
230 string EncoderMethod = "getBitfieldInvertedMaskOpValue";
231 let PrintMethod = "printBitfieldInvMaskImmOperand";
234 /// Split a 32-bit immediate into two 16 bit parts.
235 def hi16 : SDNodeXForm<imm, [{
236 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
239 def lo16AllZero : PatLeaf<(i32 imm), [{
240 // Returns true if all low 16-bits are 0.
241 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
244 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
246 def imm0_65535 : PatLeaf<(i32 imm), [{
247 return (uint32_t)N->getZExtValue() < 65536;
250 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
251 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
253 /// adde and sube predicates - True based on whether the carry flag output
254 /// will be needed or not.
255 def adde_dead_carry :
256 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
257 [{return !N->hasAnyUseOfValue(1);}]>;
258 def sube_dead_carry :
259 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
260 [{return !N->hasAnyUseOfValue(1);}]>;
261 def adde_live_carry :
262 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
263 [{return N->hasAnyUseOfValue(1);}]>;
264 def sube_live_carry :
265 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
266 [{return N->hasAnyUseOfValue(1);}]>;
268 //===----------------------------------------------------------------------===//
269 // Operand Definitions.
273 def brtarget : Operand<OtherVT>;
275 // A list of registers separated by comma. Used by load/store multiple.
276 def reglist : Operand<i32> {
277 string EncoderMethod = "getRegisterListOpValue";
278 let PrintMethod = "printRegisterList";
281 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
282 def cpinst_operand : Operand<i32> {
283 let PrintMethod = "printCPInstOperand";
286 def jtblock_operand : Operand<i32> {
287 let PrintMethod = "printJTBlockOperand";
289 def jt2block_operand : Operand<i32> {
290 let PrintMethod = "printJT2BlockOperand";
294 def pclabel : Operand<i32> {
295 let PrintMethod = "printPCLabel";
298 def neon_vcvt_imm32 : Operand<i32> {
299 string EncoderMethod = "getNEONVcvtImm32OpValue";
302 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
303 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
304 int32_t v = (int32_t)N->getZExtValue();
305 return v == 8 || v == 16 || v == 24; }]> {
306 string EncoderMethod = "getRotImmOpValue";
309 // shift_imm: An integer that encodes a shift amount and the type of shift
310 // (currently either asr or lsl) using the same encoding used for the
311 // immediates in so_reg operands.
312 def shift_imm : Operand<i32> {
313 let PrintMethod = "printShiftImmOperand";
316 // shifter_operand operands: so_reg and so_imm.
317 def so_reg : Operand<i32>, // reg reg imm
318 ComplexPattern<i32, 3, "SelectShifterOperandReg",
319 [shl,srl,sra,rotr]> {
320 string EncoderMethod = "getSORegOpValue";
321 let PrintMethod = "printSORegOperand";
322 let MIOperandInfo = (ops GPR, GPR, i32imm);
324 def shift_so_reg : Operand<i32>, // reg reg imm
325 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
326 [shl,srl,sra,rotr]> {
327 string EncoderMethod = "getSORegOpValue";
328 let PrintMethod = "printSORegOperand";
329 let MIOperandInfo = (ops GPR, GPR, i32imm);
332 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
333 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
334 // represented in the imm field in the same 12-bit form that they are encoded
335 // into so_imm instructions: the 8-bit immediate is the least significant bits
336 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
337 def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> {
338 string EncoderMethod = "getSOImmOpValue";
339 let PrintMethod = "printSOImmOperand";
342 // Break so_imm's up into two pieces. This handles immediates with up to 16
343 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
344 // get the first/second pieces.
345 def so_imm2part : Operand<i32>,
347 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
349 let PrintMethod = "printSOImm2PartOperand";
352 def so_imm2part_1 : SDNodeXForm<imm, [{
353 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
354 return CurDAG->getTargetConstant(V, MVT::i32);
357 def so_imm2part_2 : SDNodeXForm<imm, [{
358 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
359 return CurDAG->getTargetConstant(V, MVT::i32);
362 def so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
363 return ARM_AM::isSOImmTwoPartVal(-(int)N->getZExtValue());
365 let PrintMethod = "printSOImm2PartOperand";
368 def so_neg_imm2part_1 : SDNodeXForm<imm, [{
369 unsigned V = ARM_AM::getSOImmTwoPartFirst(-(int)N->getZExtValue());
370 return CurDAG->getTargetConstant(V, MVT::i32);
373 def so_neg_imm2part_2 : SDNodeXForm<imm, [{
374 unsigned V = ARM_AM::getSOImmTwoPartSecond(-(int)N->getZExtValue());
375 return CurDAG->getTargetConstant(V, MVT::i32);
378 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
379 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
380 return (int32_t)N->getZExtValue() < 32;
383 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
384 def imm0_31_m1 : Operand<i32>, PatLeaf<(imm), [{
385 return (int32_t)N->getZExtValue() < 32;
387 string EncoderMethod = "getImmMinusOneOpValue";
390 // Define ARM specific addressing modes.
393 // addrmode_imm12 := reg +/- imm12
395 def addrmode_imm12 : Operand<i32>,
396 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
397 // 12-bit immediate operand. Note that instructions using this encode
398 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
399 // immediate values are as normal.
401 string EncoderMethod = "getAddrModeImm12OpValue";
402 let PrintMethod = "printAddrModeImm12Operand";
403 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
405 // ldst_so_reg := reg +/- reg shop imm
407 def ldst_so_reg : Operand<i32>,
408 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
409 // FIXME: Simplify the printer
410 // FIXME: Add EncoderMethod for this addressing mode
411 let PrintMethod = "printAddrMode2Operand";
412 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
415 // addrmode2 := reg +/- imm12
416 // := reg +/- reg shop imm
418 def addrmode2 : Operand<i32>,
419 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
420 let PrintMethod = "printAddrMode2Operand";
421 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
424 def am2offset : Operand<i32>,
425 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
426 [], [SDNPWantRoot]> {
427 let PrintMethod = "printAddrMode2OffsetOperand";
428 let MIOperandInfo = (ops GPR, i32imm);
431 // addrmode3 := reg +/- reg
432 // addrmode3 := reg +/- imm8
434 def addrmode3 : Operand<i32>,
435 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
436 let PrintMethod = "printAddrMode3Operand";
437 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
440 def am3offset : Operand<i32>,
441 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
442 [], [SDNPWantRoot]> {
443 let PrintMethod = "printAddrMode3OffsetOperand";
444 let MIOperandInfo = (ops GPR, i32imm);
447 // addrmode4 := reg, <mode|W>
449 def addrmode4 : Operand<i32>,
450 ComplexPattern<i32, 2, "SelectAddrMode4", []> {
451 let PrintMethod = "printAddrMode4Operand";
452 let MIOperandInfo = (ops GPR:$addr, i32imm);
455 def ARMMemMode5AsmOperand : AsmOperandClass {
456 let Name = "MemMode5";
457 let SuperClasses = [];
460 // addrmode5 := reg +/- imm8*4
462 def addrmode5 : Operand<i32>,
463 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
464 let PrintMethod = "printAddrMode5Operand";
465 let MIOperandInfo = (ops GPR:$base, i32imm);
466 let ParserMatchClass = ARMMemMode5AsmOperand;
469 // addrmode6 := reg with optional writeback
471 def addrmode6 : Operand<i32>,
472 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
473 let PrintMethod = "printAddrMode6Operand";
474 let MIOperandInfo = (ops GPR:$addr, i32imm);
475 string EncoderMethod = "getAddrMode6RegisterOperand";
478 def am6offset : Operand<i32> {
479 let PrintMethod = "printAddrMode6OffsetOperand";
480 let MIOperandInfo = (ops GPR);
481 string EncoderMethod = "getAddrMode6OffsetOperand";
484 // addrmodepc := pc + reg
486 def addrmodepc : Operand<i32>,
487 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
488 let PrintMethod = "printAddrModePCOperand";
489 let MIOperandInfo = (ops GPR, i32imm);
492 def nohash_imm : Operand<i32> {
493 let PrintMethod = "printNoHashImmediate";
496 //===----------------------------------------------------------------------===//
498 include "ARMInstrFormats.td"
500 //===----------------------------------------------------------------------===//
501 // Multiclass helpers...
504 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
505 /// binop that produces a value.
506 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
507 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
508 PatFrag opnode, bit Commutable = 0> {
509 // The register-immediate version is re-materializable. This is useful
510 // in particular for taking the address of a local.
511 let isReMaterializable = 1 in {
512 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
513 iii, opc, "\t$Rd, $Rn, $imm",
514 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
519 let Inst{15-12} = Rd;
520 let Inst{19-16} = Rn;
521 let Inst{11-0} = imm;
524 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
525 iir, opc, "\t$Rd, $Rn, $Rm",
526 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
530 let Inst{11-4} = 0b00000000;
532 let isCommutable = Commutable;
534 let Inst{15-12} = Rd;
535 let Inst{19-16} = Rn;
537 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
538 iis, opc, "\t$Rd, $Rn, $shift",
539 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
544 let Inst{11-0} = shift;
545 let Inst{15-12} = Rd;
546 let Inst{19-16} = Rn;
550 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
551 /// instruction modifies the CPSR register.
552 let Defs = [CPSR] in {
553 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
554 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
555 PatFrag opnode, bit Commutable = 0> {
556 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
557 iii, opc, "\t$Rd, $Rn, $imm",
558 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
563 let Inst{15-12} = Rd;
564 let Inst{19-16} = Rn;
565 let Inst{11-0} = imm;
568 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
569 iir, opc, "\t$Rd, $Rn, $Rm",
570 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
574 let Inst{11-4} = 0b00000000;
576 let isCommutable = Commutable;
578 let Inst{15-12} = Rd;
579 let Inst{19-16} = Rn;
582 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
583 iis, opc, "\t$Rd, $Rn, $shift",
584 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
589 let Inst{11-0} = shift;
590 let Inst{15-12} = Rd;
591 let Inst{19-16} = Rn;
597 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
598 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
599 /// a explicit result, only implicitly set CPSR.
600 let isCompare = 1, Defs = [CPSR] in {
601 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
602 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
603 PatFrag opnode, bit Commutable = 0> {
604 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
606 [(opnode GPR:$Rn, so_imm:$imm)]> {
610 let Inst{15-12} = 0b0000;
611 let Inst{19-16} = Rn;
612 let Inst{11-0} = imm;
616 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
618 [(opnode GPR:$Rn, GPR:$Rm)]> {
621 let Inst{11-4} = 0b00000000;
623 let isCommutable = Commutable;
625 let Inst{15-12} = 0b0000;
626 let Inst{19-16} = Rn;
629 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
630 opc, "\t$Rn, $shift",
631 [(opnode GPR:$Rn, so_reg:$shift)]> {
635 let Inst{11-0} = shift;
636 let Inst{15-12} = 0b0000;
637 let Inst{19-16} = Rn;
643 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
644 /// register and one whose operand is a register rotated by 8/16/24.
645 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
646 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
647 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
648 IIC_iEXTr, opc, "\t$Rd, $Rm",
649 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
650 Requires<[IsARM, HasV6]> {
653 let Inst{15-12} = Rd;
655 let Inst{11-10} = 0b00;
656 let Inst{19-16} = 0b1111;
658 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
659 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
660 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
661 Requires<[IsARM, HasV6]> {
665 let Inst{15-12} = Rd;
666 let Inst{11-10} = rot;
668 let Inst{19-16} = 0b1111;
672 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
673 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
674 IIC_iEXTr, opc, "\t$Rd, $Rm",
675 [/* For disassembly only; pattern left blank */]>,
676 Requires<[IsARM, HasV6]> {
677 let Inst{11-10} = 0b00;
678 let Inst{19-16} = 0b1111;
680 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
681 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
682 [/* For disassembly only; pattern left blank */]>,
683 Requires<[IsARM, HasV6]> {
685 let Inst{11-10} = rot;
686 let Inst{19-16} = 0b1111;
690 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
691 /// register and one whose operand is a register rotated by 8/16/24.
692 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
693 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
694 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
695 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
696 Requires<[IsARM, HasV6]> {
697 let Inst{11-10} = 0b00;
699 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
701 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
702 [(set GPR:$Rd, (opnode GPR:$Rn,
703 (rotr GPR:$Rm, rot_imm:$rot)))]>,
704 Requires<[IsARM, HasV6]> {
707 let Inst{19-16} = Rn;
708 let Inst{11-10} = rot;
712 // For disassembly only.
713 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
714 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
715 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
716 [/* For disassembly only; pattern left blank */]>,
717 Requires<[IsARM, HasV6]> {
718 let Inst{11-10} = 0b00;
720 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
722 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
723 [/* For disassembly only; pattern left blank */]>,
724 Requires<[IsARM, HasV6]> {
727 let Inst{19-16} = Rn;
728 let Inst{11-10} = rot;
732 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
733 let Uses = [CPSR] in {
734 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
735 bit Commutable = 0> {
736 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
737 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
738 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
744 let Inst{15-12} = Rd;
745 let Inst{19-16} = Rn;
746 let Inst{11-0} = imm;
748 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
749 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
750 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
755 let Inst{11-4} = 0b00000000;
757 let isCommutable = Commutable;
759 let Inst{15-12} = Rd;
760 let Inst{19-16} = Rn;
762 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
763 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
764 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
770 let Inst{11-0} = shift;
771 let Inst{15-12} = Rd;
772 let Inst{19-16} = Rn;
775 // Carry setting variants
776 let Defs = [CPSR] in {
777 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
778 bit Commutable = 0> {
779 def Sri : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
780 DPFrm, IIC_iALUi, !strconcat(opc, "\t$Rd, $Rn, $imm"),
781 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
786 let Inst{15-12} = Rd;
787 let Inst{19-16} = Rn;
788 let Inst{11-0} = imm;
792 def Srr : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
793 DPFrm, IIC_iALUr, !strconcat(opc, "\t$Rd, $Rn, $Rm"),
794 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
799 let Inst{11-4} = 0b00000000;
800 let isCommutable = Commutable;
802 let Inst{15-12} = Rd;
803 let Inst{19-16} = Rn;
807 def Srs : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
808 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$Rd, $Rn, $shift"),
809 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
814 let Inst{11-0} = shift;
815 let Inst{15-12} = Rd;
816 let Inst{19-16} = Rn;
824 let canFoldAsLoad = 1, isReMaterializable = 1 in {
825 multiclass AI_ldr1<bit opc22, string opc, InstrItinClass iii,
826 InstrItinClass iir, PatFrag opnode> {
827 // Note: We use the complex addrmode_imm12 rather than just an input
828 // GPR and a constrained immediate so that we can use this to match
829 // frame index references and avoid matching constant pool references.
830 def i12 : AIldst1<0b010, opc22, 1, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
831 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
832 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
835 let Inst{23} = addr{12}; // U (add = ('U' == 1))
836 let Inst{19-16} = addr{16-13}; // Rn
837 let Inst{15-12} = Rt;
838 let Inst{11-0} = addr{11-0}; // imm12
840 def rs : AIldst1<0b011, opc22, 1, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
841 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
842 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
845 let Inst{23} = shift{12}; // U (add = ('U' == 1))
846 let Inst{19-16} = shift{16-13}; // Rn
847 let Inst{11-0} = shift{11-0};
852 multiclass AI_str1<bit opc22, string opc, InstrItinClass iii,
853 InstrItinClass iir, PatFrag opnode> {
854 // Note: We use the complex addrmode_imm12 rather than just an input
855 // GPR and a constrained immediate so that we can use this to match
856 // frame index references and avoid matching constant pool references.
857 def i12 : AIldst1<0b010, opc22, 0, (outs),
858 (ins GPR:$Rt, addrmode_imm12:$addr),
859 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
860 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
863 let Inst{23} = addr{12}; // U (add = ('U' == 1))
864 let Inst{19-16} = addr{16-13}; // Rn
865 let Inst{15-12} = Rt;
866 let Inst{11-0} = addr{11-0}; // imm12
868 def rs : AIldst1<0b011, opc22, 0, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
869 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
870 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
873 let Inst{23} = shift{12}; // U (add = ('U' == 1))
874 let Inst{19-16} = shift{16-13}; // Rn
875 let Inst{11-0} = shift{11-0};
878 //===----------------------------------------------------------------------===//
880 //===----------------------------------------------------------------------===//
882 //===----------------------------------------------------------------------===//
883 // Miscellaneous Instructions.
886 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
887 /// the function. The first operand is the ID# for this instruction, the second
888 /// is the index into the MachineConstantPool that this is, the third is the
889 /// size in bytes of this constant pool entry.
890 let neverHasSideEffects = 1, isNotDuplicable = 1 in
891 def CONSTPOOL_ENTRY :
892 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
893 i32imm:$size), NoItinerary, "", []>;
895 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
896 // from removing one half of the matched pairs. That breaks PEI, which assumes
897 // these will always be in pairs, and asserts if it finds otherwise. Better way?
898 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
900 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary, "",
901 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
903 def ADJCALLSTACKDOWN :
904 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary, "",
905 [(ARMcallseq_start timm:$amt)]>;
908 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
909 [/* For disassembly only; pattern left blank */]>,
910 Requires<[IsARM, HasV6T2]> {
911 let Inst{27-16} = 0b001100100000;
912 let Inst{15-8} = 0b11110000;
913 let Inst{7-0} = 0b00000000;
916 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
917 [/* For disassembly only; pattern left blank */]>,
918 Requires<[IsARM, HasV6T2]> {
919 let Inst{27-16} = 0b001100100000;
920 let Inst{15-8} = 0b11110000;
921 let Inst{7-0} = 0b00000001;
924 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
925 [/* For disassembly only; pattern left blank */]>,
926 Requires<[IsARM, HasV6T2]> {
927 let Inst{27-16} = 0b001100100000;
928 let Inst{15-8} = 0b11110000;
929 let Inst{7-0} = 0b00000010;
932 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
933 [/* For disassembly only; pattern left blank */]>,
934 Requires<[IsARM, HasV6T2]> {
935 let Inst{27-16} = 0b001100100000;
936 let Inst{15-8} = 0b11110000;
937 let Inst{7-0} = 0b00000011;
940 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
942 [/* For disassembly only; pattern left blank */]>,
943 Requires<[IsARM, HasV6]> {
948 let Inst{15-12} = Rd;
949 let Inst{19-16} = Rn;
950 let Inst{27-20} = 0b01101000;
951 let Inst{7-4} = 0b1011;
952 let Inst{11-8} = 0b1111;
955 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
956 [/* For disassembly only; pattern left blank */]>,
957 Requires<[IsARM, HasV6T2]> {
958 let Inst{27-16} = 0b001100100000;
959 let Inst{15-8} = 0b11110000;
960 let Inst{7-0} = 0b00000100;
963 // The i32imm operand $val can be used by a debugger to store more information
964 // about the breakpoint.
965 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
966 [/* For disassembly only; pattern left blank */]>,
969 let Inst{3-0} = val{3-0};
970 let Inst{19-8} = val{15-4};
971 let Inst{27-20} = 0b00010010;
972 let Inst{7-4} = 0b0111;
975 // Change Processor State is a system instruction -- for disassembly only.
976 // The singleton $opt operand contains the following information:
977 // opt{4-0} = mode from Inst{4-0}
978 // opt{5} = changemode from Inst{17}
979 // opt{8-6} = AIF from Inst{8-6}
980 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
981 // FIXME: Integrated assembler will need these split out.
982 def CPS : AXI<(outs), (ins cps_opt:$opt), MiscFrm, NoItinerary, "cps$opt",
983 [/* For disassembly only; pattern left blank */]>,
985 let Inst{31-28} = 0b1111;
986 let Inst{27-20} = 0b00010000;
991 // Preload signals the memory system of possible future data/instruction access.
992 // These are for disassembly only.
994 // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
995 // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
996 multiclass APreLoad<bit data, bit read, string opc> {
998 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, NoItinerary,
999 !strconcat(opc, "\t$addr"), []> {
1002 let Inst{31-26} = 0b111101;
1003 let Inst{25} = 0; // 0 for immediate form
1004 let Inst{24} = data;
1005 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1006 let Inst{22} = read;
1007 let Inst{21-20} = 0b01;
1008 let Inst{19-16} = addr{16-13}; // Rn
1009 let Inst{15-12} = Rt;
1010 let Inst{11-0} = addr{11-0}; // imm12
1013 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, NoItinerary,
1014 !strconcat(opc, "\t$shift"), []> {
1017 let Inst{31-26} = 0b111101;
1018 let Inst{25} = 1; // 1 for register form
1019 let Inst{24} = data;
1020 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1021 let Inst{22} = read;
1022 let Inst{21-20} = 0b01;
1023 let Inst{19-16} = shift{16-13}; // Rn
1024 let Inst{11-0} = shift{11-0};
1028 defm PLD : APreLoad<1, 1, "pld">;
1029 defm PLDW : APreLoad<1, 0, "pldw">;
1030 defm PLI : APreLoad<0, 1, "pli">;
1032 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1034 [/* For disassembly only; pattern left blank */]>,
1037 let Inst{31-10} = 0b1111000100000001000000;
1042 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1043 [/* For disassembly only; pattern left blank */]>,
1044 Requires<[IsARM, HasV7]> {
1046 let Inst{27-4} = 0b001100100000111100001111;
1047 let Inst{3-0} = opt;
1050 // A5.4 Permanently UNDEFINED instructions.
1051 let isBarrier = 1, isTerminator = 1 in
1052 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1055 let Inst{27-25} = 0b011;
1056 let Inst{24-20} = 0b11111;
1057 let Inst{7-5} = 0b111;
1061 // Address computation and loads and stores in PIC mode.
1062 // FIXME: These PIC insn patterns are pseudos, but derive from the normal insn
1063 // classes (AXI1, et.al.) and so have encoding information and such,
1064 // which is suboptimal. Once the rest of the code emitter (including
1065 // JIT) is MC-ized we should look at refactoring these into true
1066 // pseudos. As is, the encoding information ends up being ignored,
1067 // as these instructions are lowered to individual MC-insts.
1068 let isNotDuplicable = 1 in {
1069 def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1070 Pseudo, IIC_iALUr, "",
1071 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1073 let AddedComplexity = 10 in {
1074 def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1075 Pseudo, IIC_iLoad_r, "",
1076 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1078 def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1079 Pseudo, IIC_iLoad_bh_r, "",
1080 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
1082 def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1083 Pseudo, IIC_iLoad_bh_r, "",
1084 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
1086 def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1087 Pseudo, IIC_iLoad_bh_r, "",
1088 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
1090 def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1091 Pseudo, IIC_iLoad_bh_r, "",
1092 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
1094 let AddedComplexity = 10 in {
1095 def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1096 Pseudo, IIC_iStore_r, "",
1097 [(store GPR:$src, addrmodepc:$addr)]>;
1099 def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1100 Pseudo, IIC_iStore_bh_r, "",
1101 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
1103 def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1104 Pseudo, IIC_iStore_bh_r, "",
1105 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1107 } // isNotDuplicable = 1
1110 // LEApcrel - Load a pc-relative address into a register without offending the
1112 // FIXME: These are marked as pseudos, but they're really not(?). They're just
1113 // the ADR instruction. Is this the right way to handle that? They need
1114 // encoding information regardless.
1115 let neverHasSideEffects = 1 in {
1116 let isReMaterializable = 1 in
1117 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
1119 "adr$p\t$dst, #$label", []>;
1121 } // neverHasSideEffects
1122 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
1123 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1125 "adr$p\t$dst, #${label}_${id}", []> {
1129 //===----------------------------------------------------------------------===//
1130 // Control Flow Instructions.
1133 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1135 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1136 "bx", "\tlr", [(ARMretflag)]>,
1137 Requires<[IsARM, HasV4T]> {
1138 let Inst{27-0} = 0b0001001011111111111100011110;
1142 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1143 "mov", "\tpc, lr", [(ARMretflag)]>,
1144 Requires<[IsARM, NoV4T]> {
1145 let Inst{27-0} = 0b0001101000001111000000001110;
1149 // Indirect branches
1150 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1152 def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1153 [(brind GPR:$dst)]>,
1154 Requires<[IsARM, HasV4T]> {
1156 let Inst{31-4} = 0b1110000100101111111111110001;
1157 let Inst{3-0} = dst;
1161 def MOVPCRX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "mov\tpc, $dst",
1162 [(brind GPR:$dst)]>,
1163 Requires<[IsARM, NoV4T]> {
1165 let Inst{31-4} = 0b1110000110100000111100000000;
1166 let Inst{3-0} = dst;
1170 // FIXME: remove when we have a way to marking a MI with these properties.
1171 // FIXME: Should pc be an implicit operand like PICADD, etc?
1172 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1173 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1174 def LDM_RET : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1175 reglist:$dsts, variable_ops),
1176 IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr,
1177 "ldm${addr:submode}${p}\t$addr!, $dsts",
1178 "$addr.addr = $wb", []>;
1180 // On non-Darwin platforms R9 is callee-saved.
1182 Defs = [R0, R1, R2, R3, R12, LR,
1183 D0, D1, D2, D3, D4, D5, D6, D7,
1184 D16, D17, D18, D19, D20, D21, D22, D23,
1185 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
1186 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
1187 IIC_Br, "bl\t$func",
1188 [(ARMcall tglobaladdr:$func)]>,
1189 Requires<[IsARM, IsNotDarwin]> {
1190 let Inst{31-28} = 0b1110;
1191 // FIXME: Encoding info for $func. Needs fixups bits.
1194 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
1195 IIC_Br, "bl", "\t$func",
1196 [(ARMcall_pred tglobaladdr:$func)]>,
1197 Requires<[IsARM, IsNotDarwin]>;
1200 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1201 IIC_Br, "blx\t$func",
1202 [(ARMcall GPR:$func)]>,
1203 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1205 let Inst{27-4} = 0b000100101111111111110011;
1206 let Inst{3-0} = func;
1210 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1211 def BX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1212 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
1213 [(ARMcall_nolink tGPR:$func)]>,
1214 Requires<[IsARM, HasV4T, IsNotDarwin]> {
1216 let Inst{27-4} = 0b000100101111111111110001;
1217 let Inst{3-0} = func;
1221 def BMOVPCRX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1222 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
1223 [(ARMcall_nolink tGPR:$func)]>,
1224 Requires<[IsARM, NoV4T, IsNotDarwin]> {
1226 let Inst{27-4} = 0b000110100000111100000000;
1227 let Inst{3-0} = func;
1231 // On Darwin R9 is call-clobbered.
1233 Defs = [R0, R1, R2, R3, R9, R12, LR,
1234 D0, D1, D2, D3, D4, D5, D6, D7,
1235 D16, D17, D18, D19, D20, D21, D22, D23,
1236 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
1237 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
1238 IIC_Br, "bl\t$func",
1239 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
1240 let Inst{31-28} = 0b1110;
1241 // FIXME: Encoding info for $func. Needs fixups bits.
1244 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
1245 IIC_Br, "bl", "\t$func",
1246 [(ARMcall_pred tglobaladdr:$func)]>,
1247 Requires<[IsARM, IsDarwin]>;
1250 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1251 IIC_Br, "blx\t$func",
1252 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
1254 let Inst{27-4} = 0b000100101111111111110011;
1255 let Inst{3-0} = func;
1259 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1260 def BXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1261 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
1262 [(ARMcall_nolink tGPR:$func)]>,
1263 Requires<[IsARM, HasV4T, IsDarwin]> {
1265 let Inst{27-4} = 0b000100101111111111110001;
1266 let Inst{3-0} = func;
1270 def BMOVPCRXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1271 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
1272 [(ARMcall_nolink tGPR:$func)]>,
1273 Requires<[IsARM, NoV4T, IsDarwin]> {
1275 let Inst{27-4} = 0b000110100000111100000000;
1276 let Inst{3-0} = func;
1282 // FIXME: These should probably be xformed into the non-TC versions of the
1283 // instructions as part of MC lowering.
1284 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1286 let Defs = [R0, R1, R2, R3, R9, R12,
1287 D0, D1, D2, D3, D4, D5, D6, D7,
1288 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1289 D27, D28, D29, D30, D31, PC],
1291 def TCRETURNdi : AInoP<(outs), (ins i32imm:$dst, variable_ops),
1293 "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
1295 def TCRETURNri : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
1297 "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
1299 def TAILJMPd : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1300 IIC_Br, "b\t$dst @ TAILCALL",
1301 []>, Requires<[IsDarwin]>;
1303 def TAILJMPdt: ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1304 IIC_Br, "b.w\t$dst @ TAILCALL",
1305 []>, Requires<[IsDarwin]>;
1307 def TAILJMPr : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1308 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1309 []>, Requires<[IsDarwin]> {
1311 let Inst{31-4} = 0b1110000100101111111111110001;
1312 let Inst{3-0} = dst;
1316 // Non-Darwin versions (the difference is R9).
1317 let Defs = [R0, R1, R2, R3, R12,
1318 D0, D1, D2, D3, D4, D5, D6, D7,
1319 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1320 D27, D28, D29, D30, D31, PC],
1322 def TCRETURNdiND : AInoP<(outs), (ins i32imm:$dst, variable_ops),
1324 "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
1326 def TCRETURNriND : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
1328 "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
1330 def TAILJMPdND : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1331 IIC_Br, "b\t$dst @ TAILCALL",
1332 []>, Requires<[IsARM, IsNotDarwin]>;
1334 def TAILJMPdNDt : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1335 IIC_Br, "b.w\t$dst @ TAILCALL",
1336 []>, Requires<[IsThumb, IsNotDarwin]>;
1338 def TAILJMPrND : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1339 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1340 []>, Requires<[IsNotDarwin]> {
1342 let Inst{31-4} = 0b1110000100101111111111110001;
1343 let Inst{3-0} = dst;
1348 let isBranch = 1, isTerminator = 1 in {
1349 // B is "predicable" since it can be xformed into a Bcc.
1350 let isBarrier = 1 in {
1351 let isPredicable = 1 in
1352 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
1353 "b\t$target", [(br bb:$target)]>;
1355 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1356 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
1357 IIC_Br, "mov\tpc, $target$jt",
1358 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
1359 let Inst{11-4} = 0b00000000;
1360 let Inst{15-12} = 0b1111;
1361 let Inst{20} = 0; // S Bit
1362 let Inst{24-21} = 0b1101;
1363 let Inst{27-25} = 0b000;
1365 def BR_JTm : JTI<(outs),
1366 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
1367 IIC_Br, "ldr\tpc, $target$jt",
1368 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1370 let Inst{15-12} = 0b1111;
1371 let Inst{20} = 1; // L bit
1372 let Inst{21} = 0; // W bit
1373 let Inst{22} = 0; // B bit
1374 let Inst{24} = 1; // P bit
1375 let Inst{27-25} = 0b011;
1377 def BR_JTadd : JTI<(outs),
1378 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
1379 IIC_Br, "add\tpc, $target, $idx$jt",
1380 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1382 let Inst{15-12} = 0b1111;
1383 let Inst{20} = 0; // S bit
1384 let Inst{24-21} = 0b0100;
1385 let Inst{27-25} = 0b000;
1387 } // isNotDuplicable = 1, isIndirectBranch = 1
1390 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1391 // a two-value operand where a dag node expects two operands. :(
1392 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
1393 IIC_Br, "b", "\t$target",
1394 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
1397 // Branch and Exchange Jazelle -- for disassembly only
1398 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1399 [/* For disassembly only; pattern left blank */]> {
1400 let Inst{23-20} = 0b0010;
1401 //let Inst{19-8} = 0xfff;
1402 let Inst{7-4} = 0b0010;
1405 // Secure Monitor Call is a system instruction -- for disassembly only
1406 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1407 [/* For disassembly only; pattern left blank */]> {
1409 let Inst{23-4} = 0b01100000000000000111;
1410 let Inst{3-0} = opt;
1413 // Supervisor Call (Software Interrupt) -- for disassembly only
1415 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1416 [/* For disassembly only; pattern left blank */]> {
1418 let Inst{23-0} = svc;
1422 // Store Return State is a system instruction -- for disassembly only
1423 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1424 def SRSW : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, i32imm:$mode),
1425 NoItinerary, "srs${addr:submode}\tsp!, $mode",
1426 [/* For disassembly only; pattern left blank */]> {
1427 let Inst{31-28} = 0b1111;
1428 let Inst{22-20} = 0b110; // W = 1
1431 def SRS : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, i32imm:$mode),
1432 NoItinerary, "srs${addr:submode}\tsp, $mode",
1433 [/* For disassembly only; pattern left blank */]> {
1434 let Inst{31-28} = 0b1111;
1435 let Inst{22-20} = 0b100; // W = 0
1438 // Return From Exception is a system instruction -- for disassembly only
1439 def RFEW : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, GPR:$base),
1440 NoItinerary, "rfe${addr:submode}\t$base!",
1441 [/* For disassembly only; pattern left blank */]> {
1442 let Inst{31-28} = 0b1111;
1443 let Inst{22-20} = 0b011; // W = 1
1446 def RFE : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, GPR:$base),
1447 NoItinerary, "rfe${addr:submode}\t$base",
1448 [/* For disassembly only; pattern left blank */]> {
1449 let Inst{31-28} = 0b1111;
1450 let Inst{22-20} = 0b001; // W = 0
1452 } // isCodeGenOnly = 1
1454 //===----------------------------------------------------------------------===//
1455 // Load / store Instructions.
1461 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1462 UnOpFrag<(load node:$Src)>>;
1463 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1464 UnOpFrag<(zextloadi8 node:$Src)>>;
1465 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1466 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1467 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1468 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1470 // Special LDR for loads from non-pc-relative constpools.
1471 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1472 isReMaterializable = 1 in
1473 def LDRcp : AIldst1<0b010, 0, 1, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1474 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr", []> {
1477 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1478 let Inst{19-16} = 0b1111;
1479 let Inst{15-12} = Rt;
1480 let Inst{11-0} = addr{11-0}; // imm12
1483 // Loads with zero extension
1484 def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1485 IIC_iLoad_bh_r, "ldrh", "\t$dst, $addr",
1486 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
1488 // Loads with sign extension
1489 def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1490 IIC_iLoad_bh_r, "ldrsh", "\t$dst, $addr",
1491 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
1493 def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1494 IIC_iLoad_bh_r, "ldrsb", "\t$dst, $addr",
1495 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
1497 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1499 def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
1500 IIC_iLoad_d_r, "ldrd", "\t$dst1, $addr",
1501 []>, Requires<[IsARM, HasV5TE]>;
1504 def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
1505 (ins addrmode2:$addr), LdFrm, IIC_iLoad_ru,
1506 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1508 def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
1509 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoad_ru,
1510 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1512 def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
1513 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru,
1514 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1516 def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
1517 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1518 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1520 def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
1521 (ins addrmode2:$addr), LdFrm, IIC_iLoad_bh_ru,
1522 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1524 def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
1525 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru,
1526 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1528 def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
1529 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru,
1530 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1532 def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
1533 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1534 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1536 def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
1537 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru,
1538 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1540 def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
1541 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_ru,
1542 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1544 // For disassembly only
1545 def LDRD_PRE : AI3lddpr<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
1546 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_d_ru,
1547 "ldrd", "\t$dst1, $dst2, $addr!", "$addr.base = $base_wb", []>,
1548 Requires<[IsARM, HasV5TE]>;
1550 // For disassembly only
1551 def LDRD_POST : AI3lddpo<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
1552 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_d_ru,
1553 "ldrd", "\t$dst1, $dst2, [$base], $offset", "$base = $base_wb", []>,
1554 Requires<[IsARM, HasV5TE]>;
1556 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1558 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1560 def LDRT : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
1561 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoad_ru,
1562 "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1563 let Inst{21} = 1; // overwrite
1566 def LDRBT : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
1567 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru,
1568 "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1569 let Inst{21} = 1; // overwrite
1572 def LDRSBT : AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
1573 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1574 "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1575 let Inst{21} = 1; // overwrite
1578 def LDRHT : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
1579 (ins GPR:$base, am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1580 "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1581 let Inst{21} = 1; // overwrite
1584 def LDRSHT : AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
1585 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1586 "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1587 let Inst{21} = 1; // overwrite
1592 // Stores with truncate
1593 def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm,
1594 IIC_iStore_bh_r, "strh", "\t$src, $addr",
1595 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
1598 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1599 def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
1600 StMiscFrm, IIC_iStore_d_r,
1601 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
1604 def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
1605 (ins GPR:$src, GPR:$base, am2offset:$offset),
1606 StFrm, IIC_iStore_ru,
1607 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
1609 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
1611 def STR_POST : AI2stwpo<(outs GPR:$base_wb),
1612 (ins GPR:$src, GPR:$base,am2offset:$offset),
1613 StFrm, IIC_iStore_ru,
1614 "str", "\t$src, [$base], $offset", "$base = $base_wb",
1616 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
1618 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
1619 (ins GPR:$src, GPR:$base,am3offset:$offset),
1620 StMiscFrm, IIC_iStore_ru,
1621 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
1623 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
1625 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
1626 (ins GPR:$src, GPR:$base,am3offset:$offset),
1627 StMiscFrm, IIC_iStore_bh_ru,
1628 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
1629 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
1630 GPR:$base, am3offset:$offset))]>;
1632 def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
1633 (ins GPR:$src, GPR:$base,am2offset:$offset),
1634 StFrm, IIC_iStore_bh_ru,
1635 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
1636 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
1637 GPR:$base, am2offset:$offset))]>;
1639 def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
1640 (ins GPR:$src, GPR:$base,am2offset:$offset),
1641 StFrm, IIC_iStore_bh_ru,
1642 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
1643 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
1644 GPR:$base, am2offset:$offset))]>;
1646 // For disassembly only
1647 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1648 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1649 StMiscFrm, IIC_iStore_d_ru,
1650 "strd", "\t$src1, $src2, [$base, $offset]!",
1651 "$base = $base_wb", []>;
1653 // For disassembly only
1654 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1655 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1656 StMiscFrm, IIC_iStore_d_ru,
1657 "strd", "\t$src1, $src2, [$base], $offset",
1658 "$base = $base_wb", []>;
1660 // STRT, STRBT, and STRHT are for disassembly only.
1662 def STRT : AI2stwpo<(outs GPR:$base_wb),
1663 (ins GPR:$src, GPR:$base,am2offset:$offset),
1664 StFrm, IIC_iStore_ru,
1665 "strt", "\t$src, [$base], $offset", "$base = $base_wb",
1666 [/* For disassembly only; pattern left blank */]> {
1667 let Inst{21} = 1; // overwrite
1670 def STRBT : AI2stbpo<(outs GPR:$base_wb),
1671 (ins GPR:$src, GPR:$base,am2offset:$offset),
1672 StFrm, IIC_iStore_bh_ru,
1673 "strbt", "\t$src, [$base], $offset", "$base = $base_wb",
1674 [/* For disassembly only; pattern left blank */]> {
1675 let Inst{21} = 1; // overwrite
1678 def STRHT: AI3sthpo<(outs GPR:$base_wb),
1679 (ins GPR:$src, GPR:$base,am3offset:$offset),
1680 StMiscFrm, IIC_iStore_bh_ru,
1681 "strht", "\t$src, [$base], $offset", "$base = $base_wb",
1682 [/* For disassembly only; pattern left blank */]> {
1683 let Inst{21} = 1; // overwrite
1686 //===----------------------------------------------------------------------===//
1687 // Load / store multiple Instructions.
1690 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
1691 isCodeGenOnly = 1 in {
1692 def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p,
1693 reglist:$dsts, variable_ops),
1694 IndexModeNone, LdStMulFrm, IIC_iLoad_m,
1695 "ldm${addr:submode}${p}\t$addr, $dsts", "", []>;
1697 def LDM_UPD : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1698 reglist:$dsts, variable_ops),
1699 IndexModeUpd, LdStMulFrm, IIC_iLoad_mu,
1700 "ldm${addr:submode}${p}\t$addr!, $dsts",
1701 "$addr.addr = $wb", []>;
1702 } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
1704 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
1705 isCodeGenOnly = 1 in {
1706 def STM : AXI4st<(outs), (ins addrmode4:$addr, pred:$p,
1707 reglist:$srcs, variable_ops),
1708 IndexModeNone, LdStMulFrm, IIC_iStore_m,
1709 "stm${addr:submode}${p}\t$addr, $srcs", "", []>;
1711 def STM_UPD : AXI4st<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1712 reglist:$srcs, variable_ops),
1713 IndexModeUpd, LdStMulFrm, IIC_iStore_mu,
1714 "stm${addr:submode}${p}\t$addr!, $srcs",
1715 "$addr.addr = $wb", []>;
1716 } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
1718 //===----------------------------------------------------------------------===//
1719 // Move Instructions.
1722 let neverHasSideEffects = 1 in
1723 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
1724 "mov", "\t$Rd, $Rm", []>, UnaryDP {
1728 let Inst{11-4} = 0b00000000;
1731 let Inst{15-12} = Rd;
1734 // A version for the smaller set of tail call registers.
1735 let neverHasSideEffects = 1 in
1736 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
1737 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
1741 let Inst{11-4} = 0b00000000;
1744 let Inst{15-12} = Rd;
1747 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
1748 DPSoRegFrm, IIC_iMOVsr,
1749 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
1753 let Inst{15-12} = Rd;
1754 let Inst{11-0} = src;
1758 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1759 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
1760 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
1764 let Inst{15-12} = Rd;
1765 let Inst{19-16} = 0b0000;
1766 let Inst{11-0} = imm;
1769 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1770 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins i32imm:$imm),
1772 "movw", "\t$Rd, $imm",
1773 [(set GPR:$Rd, imm0_65535:$imm)]>,
1774 Requires<[IsARM, HasV6T2]>, UnaryDP {
1777 let Inst{15-12} = Rd;
1778 let Inst{11-0} = imm{11-0};
1779 let Inst{19-16} = imm{15-12};
1784 let Constraints = "$src = $Rd" in
1785 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, i32imm:$imm),
1787 "movt", "\t$Rd, $imm",
1789 (or (and GPR:$src, 0xffff),
1790 lo16AllZero:$imm))]>, UnaryDP,
1791 Requires<[IsARM, HasV6T2]> {
1794 let Inst{15-12} = Rd;
1795 let Inst{11-0} = imm{11-0};
1796 let Inst{19-16} = imm{15-12};
1801 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
1802 Requires<[IsARM, HasV6T2]>;
1804 let Uses = [CPSR] in
1805 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi, "",
1806 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
1809 // These aren't really mov instructions, but we have to define them this way
1810 // due to flag operands.
1812 let Defs = [CPSR] in {
1813 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, "",
1814 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
1816 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, "",
1817 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
1821 //===----------------------------------------------------------------------===//
1822 // Extend Instructions.
1827 defm SXTB : AI_ext_rrot<0b01101010,
1828 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
1829 defm SXTH : AI_ext_rrot<0b01101011,
1830 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
1832 defm SXTAB : AI_exta_rrot<0b01101010,
1833 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1834 defm SXTAH : AI_exta_rrot<0b01101011,
1835 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1837 // For disassembly only
1838 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
1840 // For disassembly only
1841 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
1845 let AddedComplexity = 16 in {
1846 defm UXTB : AI_ext_rrot<0b01101110,
1847 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
1848 defm UXTH : AI_ext_rrot<0b01101111,
1849 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1850 defm UXTB16 : AI_ext_rrot<0b01101100,
1851 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1853 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1854 // The transformation should probably be done as a combiner action
1855 // instead so we can include a check for masking back in the upper
1856 // eight bits of the source into the lower eight bits of the result.
1857 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1858 // (UXTB16r_rot GPR:$Src, 24)>;
1859 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1860 (UXTB16r_rot GPR:$Src, 8)>;
1862 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
1863 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1864 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
1865 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1868 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
1869 // For disassembly only
1870 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
1873 def SBFX : I<(outs GPR:$Rd),
1874 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
1875 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
1876 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
1877 Requires<[IsARM, HasV6T2]> {
1882 let Inst{27-21} = 0b0111101;
1883 let Inst{6-4} = 0b101;
1884 let Inst{20-16} = width;
1885 let Inst{15-12} = Rd;
1886 let Inst{11-7} = lsb;
1890 def UBFX : I<(outs GPR:$Rd),
1891 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
1892 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
1893 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
1894 Requires<[IsARM, HasV6T2]> {
1899 let Inst{27-21} = 0b0111111;
1900 let Inst{6-4} = 0b101;
1901 let Inst{20-16} = width;
1902 let Inst{15-12} = Rd;
1903 let Inst{11-7} = lsb;
1907 //===----------------------------------------------------------------------===//
1908 // Arithmetic Instructions.
1911 defm ADD : AsI1_bin_irs<0b0100, "add",
1912 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
1913 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1914 defm SUB : AsI1_bin_irs<0b0010, "sub",
1915 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
1916 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1918 // ADD and SUB with 's' bit set.
1919 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
1920 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
1921 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1922 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
1923 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
1924 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1926 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
1927 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1928 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
1929 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1930 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
1931 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
1932 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
1933 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
1935 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1936 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
1937 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
1942 let Inst{15-12} = Rd;
1943 let Inst{19-16} = Rn;
1944 let Inst{11-0} = imm;
1947 // The reg/reg form is only defined for the disassembler; for codegen it is
1948 // equivalent to SUBrr.
1949 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1950 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
1951 [/* For disassembly only; pattern left blank */]> {
1955 let Inst{11-4} = 0b00000000;
1958 let Inst{15-12} = Rd;
1959 let Inst{19-16} = Rn;
1962 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
1963 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
1964 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
1969 let Inst{11-0} = shift;
1970 let Inst{15-12} = Rd;
1971 let Inst{19-16} = Rn;
1974 // RSB with 's' bit set.
1975 let Defs = [CPSR] in {
1976 def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1977 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
1978 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
1984 let Inst{15-12} = Rd;
1985 let Inst{19-16} = Rn;
1986 let Inst{11-0} = imm;
1988 def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
1989 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
1990 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
1996 let Inst{11-0} = shift;
1997 let Inst{15-12} = Rd;
1998 let Inst{19-16} = Rn;
2002 let Uses = [CPSR] in {
2003 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2004 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2005 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2011 let Inst{15-12} = Rd;
2012 let Inst{19-16} = Rn;
2013 let Inst{11-0} = imm;
2015 // The reg/reg form is only defined for the disassembler; for codegen it is
2016 // equivalent to SUBrr.
2017 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2018 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2019 [/* For disassembly only; pattern left blank */]> {
2023 let Inst{11-4} = 0b00000000;
2026 let Inst{15-12} = Rd;
2027 let Inst{19-16} = Rn;
2029 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2030 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2031 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2037 let Inst{11-0} = shift;
2038 let Inst{15-12} = Rd;
2039 let Inst{19-16} = Rn;
2043 // FIXME: Allow these to be predicated.
2044 let Defs = [CPSR], Uses = [CPSR] in {
2045 def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2046 DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
2047 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2054 let Inst{15-12} = Rd;
2055 let Inst{19-16} = Rn;
2056 let Inst{11-0} = imm;
2058 def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2059 DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
2060 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2067 let Inst{11-0} = shift;
2068 let Inst{15-12} = Rd;
2069 let Inst{19-16} = Rn;
2073 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2074 // The assume-no-carry-in form uses the negation of the input since add/sub
2075 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2076 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2078 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2079 (SUBri GPR:$src, so_imm_neg:$imm)>;
2080 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2081 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2082 // The with-carry-in form matches bitwise not instead of the negation.
2083 // Effectively, the inverse interpretation of the carry flag already accounts
2084 // for part of the negation.
2085 def : ARMPat<(adde GPR:$src, so_imm_not:$imm),
2086 (SBCri GPR:$src, so_imm_not:$imm)>;
2088 // Note: These are implemented in C++ code, because they have to generate
2089 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2091 // (mul X, 2^n+1) -> (add (X << n), X)
2092 // (mul X, 2^n-1) -> (rsb X, (X << n))
2094 // ARM Arithmetic Instruction -- for disassembly only
2095 // GPR:$dst = GPR:$a op GPR:$b
2096 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2097 list<dag> pattern = [/* For disassembly only; pattern left blank */]>
2098 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iALUr,
2099 opc, "\t$Rd, $Rn, $Rm", pattern> {
2103 let Inst{27-20} = op27_20;
2104 let Inst{11-4} = op11_4;
2105 let Inst{19-16} = Rn;
2106 let Inst{15-12} = Rd;
2110 // Saturating add/subtract -- for disassembly only
2112 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2113 [(set GPR:$Rd, (int_arm_qadd GPR:$Rn, GPR:$Rm))]>;
2114 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2115 [(set GPR:$Rd, (int_arm_qsub GPR:$Rn, GPR:$Rm))]>;
2116 def QDADD : AAI<0b00010100, 0b00000101, "qdadd">;
2117 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub">;
2119 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2120 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2121 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2122 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2123 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2124 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2125 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2126 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2127 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2128 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2129 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2130 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2132 // Signed/Unsigned add/subtract -- for disassembly only
2134 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2135 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2136 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2137 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2138 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2139 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2140 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2141 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2142 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2143 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2144 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2145 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2147 // Signed/Unsigned halving add/subtract -- for disassembly only
2149 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2150 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2151 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2152 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2153 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2154 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2155 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2156 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2157 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2158 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2159 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2160 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2162 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2164 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2165 MulFrm /* for convenience */, NoItinerary, "usad8",
2166 "\t$Rd, $Rn, $Rm", []>,
2167 Requires<[IsARM, HasV6]> {
2171 let Inst{27-20} = 0b01111000;
2172 let Inst{15-12} = 0b1111;
2173 let Inst{7-4} = 0b0001;
2174 let Inst{19-16} = Rd;
2175 let Inst{11-8} = Rm;
2178 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2179 MulFrm /* for convenience */, NoItinerary, "usada8",
2180 "\t$Rd, $Rn, $Rm, $Ra", []>,
2181 Requires<[IsARM, HasV6]> {
2186 let Inst{27-20} = 0b01111000;
2187 let Inst{7-4} = 0b0001;
2188 let Inst{19-16} = Rd;
2189 let Inst{15-12} = Ra;
2190 let Inst{11-8} = Rm;
2194 // Signed/Unsigned saturate -- for disassembly only
2196 def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2197 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2198 [/* For disassembly only; pattern left blank */]> {
2203 let Inst{27-21} = 0b0110101;
2204 let Inst{5-4} = 0b01;
2205 let Inst{20-16} = sat_imm;
2206 let Inst{15-12} = Rd;
2207 let Inst{11-7} = sh{7-3};
2208 let Inst{6} = sh{0};
2212 def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm,
2213 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2214 [/* For disassembly only; pattern left blank */]> {
2218 let Inst{27-20} = 0b01101010;
2219 let Inst{11-4} = 0b11110011;
2220 let Inst{15-12} = Rd;
2221 let Inst{19-16} = sat_imm;
2225 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2226 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2227 [/* For disassembly only; pattern left blank */]> {
2232 let Inst{27-21} = 0b0110111;
2233 let Inst{5-4} = 0b01;
2234 let Inst{15-12} = Rd;
2235 let Inst{11-7} = sh{7-3};
2236 let Inst{6} = sh{0};
2237 let Inst{20-16} = sat_imm;
2241 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2242 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2243 [/* For disassembly only; pattern left blank */]> {
2247 let Inst{27-20} = 0b01101110;
2248 let Inst{11-4} = 0b11110011;
2249 let Inst{15-12} = Rd;
2250 let Inst{19-16} = sat_imm;
2254 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2255 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2257 //===----------------------------------------------------------------------===//
2258 // Bitwise Instructions.
2261 defm AND : AsI1_bin_irs<0b0000, "and",
2262 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2263 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2264 defm ORR : AsI1_bin_irs<0b1100, "orr",
2265 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2266 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2267 defm EOR : AsI1_bin_irs<0b0001, "eor",
2268 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2269 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2270 defm BIC : AsI1_bin_irs<0b1110, "bic",
2271 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2272 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2274 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2275 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2276 "bfc", "\t$Rd, $imm", "$src = $Rd",
2277 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2278 Requires<[IsARM, HasV6T2]> {
2281 let Inst{27-21} = 0b0111110;
2282 let Inst{6-0} = 0b0011111;
2283 let Inst{15-12} = Rd;
2284 let Inst{11-7} = imm{4-0}; // lsb
2285 let Inst{20-16} = imm{9-5}; // width
2288 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2289 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2290 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2291 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2292 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2293 bf_inv_mask_imm:$imm))]>,
2294 Requires<[IsARM, HasV6T2]> {
2298 let Inst{27-21} = 0b0111110;
2299 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2300 let Inst{15-12} = Rd;
2301 let Inst{11-7} = imm{4-0}; // lsb
2302 let Inst{20-16} = imm{9-5}; // width
2306 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2307 "mvn", "\t$Rd, $Rm",
2308 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2312 let Inst{19-16} = 0b0000;
2313 let Inst{11-4} = 0b00000000;
2314 let Inst{15-12} = Rd;
2317 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2318 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2319 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2324 let Inst{19-16} = 0b0000;
2325 let Inst{15-12} = Rd;
2326 let Inst{11-0} = shift;
2328 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
2329 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2330 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2331 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2336 let Inst{19-16} = 0b0000;
2337 let Inst{15-12} = Rd;
2338 let Inst{11-0} = imm;
2341 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2342 (BICri GPR:$src, so_imm_not:$imm)>;
2344 //===----------------------------------------------------------------------===//
2345 // Multiply Instructions.
2347 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2348 string opc, string asm, list<dag> pattern>
2349 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2353 let Inst{19-16} = Rd;
2354 let Inst{11-8} = Rm;
2357 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2358 string opc, string asm, list<dag> pattern>
2359 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2364 let Inst{19-16} = RdHi;
2365 let Inst{15-12} = RdLo;
2366 let Inst{11-8} = Rm;
2370 let isCommutable = 1 in
2371 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2372 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2373 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>;
2375 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2376 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2377 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]> {
2379 let Inst{15-12} = Ra;
2382 def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
2383 IIC_iMAC32, "mls", "\t$dst, $a, $b, $c",
2384 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
2385 Requires<[IsARM, HasV6T2]> {
2389 let Inst{19-16} = Rd;
2390 let Inst{11-8} = Rm;
2394 // Extra precision multiplies with low / high results
2396 let neverHasSideEffects = 1 in {
2397 let isCommutable = 1 in {
2398 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2399 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2400 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2402 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2403 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2404 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2407 // Multiply + accumulate
2408 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2409 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2410 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2412 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2413 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2414 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2416 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2417 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2418 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2419 Requires<[IsARM, HasV6]> {
2424 let Inst{19-16} = RdLo;
2425 let Inst{15-12} = RdHi;
2426 let Inst{11-8} = Rm;
2429 } // neverHasSideEffects
2431 // Most significant word multiply
2432 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2433 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2434 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2435 Requires<[IsARM, HasV6]> {
2436 let Inst{15-12} = 0b1111;
2439 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2440 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2441 [/* For disassembly only; pattern left blank */]>,
2442 Requires<[IsARM, HasV6]> {
2443 let Inst{15-12} = 0b1111;
2446 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2447 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2448 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2449 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2450 Requires<[IsARM, HasV6]>;
2452 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2453 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2454 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2455 [/* For disassembly only; pattern left blank */]>,
2456 Requires<[IsARM, HasV6]>;
2458 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2459 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2460 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2461 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2462 Requires<[IsARM, HasV6]>;
2464 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2465 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2466 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2467 [/* For disassembly only; pattern left blank */]>,
2468 Requires<[IsARM, HasV6]>;
2470 multiclass AI_smul<string opc, PatFrag opnode> {
2471 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2472 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2473 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2474 (sext_inreg GPR:$Rm, i16)))]>,
2475 Requires<[IsARM, HasV5TE]>;
2477 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2478 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2479 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2480 (sra GPR:$Rm, (i32 16))))]>,
2481 Requires<[IsARM, HasV5TE]>;
2483 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2484 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2485 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2486 (sext_inreg GPR:$Rm, i16)))]>,
2487 Requires<[IsARM, HasV5TE]>;
2489 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2490 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2491 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2492 (sra GPR:$Rm, (i32 16))))]>,
2493 Requires<[IsARM, HasV5TE]>;
2495 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2496 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2497 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2498 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2499 Requires<[IsARM, HasV5TE]>;
2501 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2502 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2503 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2504 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2505 Requires<[IsARM, HasV5TE]>;
2509 multiclass AI_smla<string opc, PatFrag opnode> {
2510 def BB : AMulxyI<0b0001000, 0b00, (outs GPR:$Rd),
2511 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2512 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2513 [(set GPR:$Rd, (add GPR:$Ra,
2514 (opnode (sext_inreg GPR:$Rn, i16),
2515 (sext_inreg GPR:$Rm, i16))))]>,
2516 Requires<[IsARM, HasV5TE]>;
2518 def BT : AMulxyI<0b0001000, 0b10, (outs GPR:$Rd),
2519 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2520 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2521 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2522 (sra GPR:$Rm, (i32 16)))))]>,
2523 Requires<[IsARM, HasV5TE]>;
2525 def TB : AMulxyI<0b0001000, 0b01, (outs GPR:$Rd),
2526 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2527 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2528 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2529 (sext_inreg GPR:$Rm, i16))))]>,
2530 Requires<[IsARM, HasV5TE]>;
2532 def TT : AMulxyI<0b0001000, 0b11, (outs GPR:$Rd),
2533 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2534 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2535 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2536 (sra GPR:$Rm, (i32 16)))))]>,
2537 Requires<[IsARM, HasV5TE]>;
2539 def WB : AMulxyI<0b0001001, 0b00, (outs GPR:$Rd),
2540 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2541 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2542 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2543 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2544 Requires<[IsARM, HasV5TE]>;
2546 def WT : AMulxyI<0b0001001, 0b10, (outs GPR:$Rd),
2547 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2548 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2549 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2550 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2551 Requires<[IsARM, HasV5TE]>;
2554 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2555 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2557 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2558 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2559 (ins GPR:$Rn, GPR:$Rm),
2560 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2561 [/* For disassembly only; pattern left blank */]>,
2562 Requires<[IsARM, HasV5TE]>;
2564 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2565 (ins GPR:$Rn, GPR:$Rm),
2566 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2567 [/* For disassembly only; pattern left blank */]>,
2568 Requires<[IsARM, HasV5TE]>;
2570 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2571 (ins GPR:$Rn, GPR:$Rm),
2572 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2573 [/* For disassembly only; pattern left blank */]>,
2574 Requires<[IsARM, HasV5TE]>;
2576 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2577 (ins GPR:$Rn, GPR:$Rm),
2578 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2579 [/* For disassembly only; pattern left blank */]>,
2580 Requires<[IsARM, HasV5TE]>;
2582 // Helper class for AI_smld -- for disassembly only
2583 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2584 InstrItinClass itin, string opc, string asm>
2585 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2592 let Inst{21-20} = 0b00;
2593 let Inst{22} = long;
2594 let Inst{27-23} = 0b01110;
2595 let Inst{11-8} = Rm;
2598 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2599 InstrItinClass itin, string opc, string asm>
2600 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2602 let Inst{15-12} = 0b1111;
2603 let Inst{19-16} = Rd;
2605 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2606 InstrItinClass itin, string opc, string asm>
2607 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2609 let Inst{15-12} = Ra;
2611 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2612 InstrItinClass itin, string opc, string asm>
2613 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2616 let Inst{19-16} = RdHi;
2617 let Inst{15-12} = RdLo;
2620 multiclass AI_smld<bit sub, string opc> {
2622 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2623 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
2625 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2626 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
2628 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
2629 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2630 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
2632 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
2633 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2634 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
2638 defm SMLA : AI_smld<0, "smla">;
2639 defm SMLS : AI_smld<1, "smls">;
2641 multiclass AI_sdml<bit sub, string opc> {
2643 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2644 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
2645 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2646 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
2649 defm SMUA : AI_sdml<0, "smua">;
2650 defm SMUS : AI_sdml<1, "smus">;
2652 //===----------------------------------------------------------------------===//
2653 // Misc. Arithmetic Instructions.
2656 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
2657 IIC_iUNAr, "clz", "\t$Rd, $Rm",
2658 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
2660 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2661 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
2662 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
2663 Requires<[IsARM, HasV6T2]>;
2665 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2666 IIC_iUNAr, "rev", "\t$Rd, $Rm",
2667 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
2669 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2670 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
2672 (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
2673 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
2674 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
2675 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
2676 Requires<[IsARM, HasV6]>;
2678 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2679 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
2682 (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
2683 (shl GPR:$Rm, (i32 8))), i16))]>,
2684 Requires<[IsARM, HasV6]>;
2686 def lsl_shift_imm : SDNodeXForm<imm, [{
2687 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
2688 return CurDAG->getTargetConstant(Sh, MVT::i32);
2691 def lsl_amt : PatLeaf<(i32 imm), [{
2692 return (N->getZExtValue() < 32);
2695 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
2696 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2697 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2698 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
2699 (and (shl GPR:$Rm, lsl_amt:$sh),
2701 Requires<[IsARM, HasV6]>;
2703 // Alternate cases for PKHBT where identities eliminate some nodes.
2704 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
2705 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
2706 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
2707 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
2709 def asr_shift_imm : SDNodeXForm<imm, [{
2710 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
2711 return CurDAG->getTargetConstant(Sh, MVT::i32);
2714 def asr_amt : PatLeaf<(i32 imm), [{
2715 return (N->getZExtValue() <= 32);
2718 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2719 // will match the pattern below.
2720 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
2721 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2722 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2723 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
2724 (and (sra GPR:$Rm, asr_amt:$sh),
2726 Requires<[IsARM, HasV6]>;
2728 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2729 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2730 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
2731 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
2732 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
2733 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
2734 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
2736 //===----------------------------------------------------------------------===//
2737 // Comparison Instructions...
2740 defm CMP : AI1_cmp_irs<0b1010, "cmp",
2741 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2742 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2744 // FIXME: We have to be careful when using the CMN instruction and comparison
2745 // with 0. One would expect these two pieces of code should give identical
2761 // However, the CMN gives the *opposite* result when r1 is 0. This is because
2762 // the carry flag is set in the CMP case but not in the CMN case. In short, the
2763 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
2764 // value of r0 and the carry bit (because the "carry bit" parameter to
2765 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
2766 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
2767 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
2768 // parameter to AddWithCarry is defined as 0).
2770 // When x is 0 and unsigned:
2774 // ~x + 1 = 0x1 0000 0000
2775 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
2777 // Therefore, we should disable CMN when comparing against zero, until we can
2778 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
2779 // when it's a comparison which doesn't look at the 'carry' flag).
2781 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
2783 // This is related to <rdar://problem/7569620>.
2785 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
2786 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2788 // Note that TST/TEQ don't set all the same flags that CMP does!
2789 defm TST : AI1_cmp_irs<0b1000, "tst",
2790 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2791 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>, 1>;
2792 defm TEQ : AI1_cmp_irs<0b1001, "teq",
2793 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2794 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>, 1>;
2796 defm CMPz : AI1_cmp_irs<0b1010, "cmp",
2797 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2798 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
2799 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
2800 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2801 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2803 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
2804 // (CMNri GPR:$src, so_imm_neg:$imm)>;
2806 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
2807 (CMNzri GPR:$src, so_imm_neg:$imm)>;
2809 // Pseudo i64 compares for some floating point compares.
2810 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
2812 def BCCi64 : PseudoInst<(outs),
2813 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
2815 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
2817 def BCCZi64 : PseudoInst<(outs),
2818 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br, "",
2819 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
2820 } // usesCustomInserter
2823 // Conditional moves
2824 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2825 // a two-value operand where a dag node expects two operands. :(
2826 // FIXME: These should all be pseudo-instructions that get expanded to
2827 // the normal MOV instructions. That would fix the dependency on
2828 // special casing them in tblgen.
2829 let neverHasSideEffects = 1 in {
2830 def MOVCCr : AI1<0b1101, (outs GPR:$Rd), (ins GPR:$false, GPR:$Rm), DPFrm,
2831 IIC_iCMOVr, "mov", "\t$Rd, $Rm",
2832 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2833 RegConstraint<"$false = $Rd">, UnaryDP {
2838 let Inst{15-12} = Rd;
2839 let Inst{11-4} = 0b00000000;
2843 def MOVCCs : AI1<0b1101, (outs GPR:$Rd),
2844 (ins GPR:$false, so_reg:$shift), DPSoRegFrm, IIC_iCMOVsr,
2845 "mov", "\t$Rd, $shift",
2846 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
2847 RegConstraint<"$false = $Rd">, UnaryDP {
2853 let Inst{19-16} = Rn;
2854 let Inst{15-12} = Rd;
2855 let Inst{11-0} = shift;
2858 def MOVCCi16 : AI1<0b1000, (outs GPR:$Rd), (ins GPR:$false, i32imm:$imm),
2860 "movw", "\t$Rd, $imm",
2862 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
2868 let Inst{19-16} = imm{15-12};
2869 let Inst{15-12} = Rd;
2870 let Inst{11-0} = imm{11-0};
2873 def MOVCCi : AI1<0b1101, (outs GPR:$Rd),
2874 (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi,
2875 "mov", "\t$Rd, $imm",
2876 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2877 RegConstraint<"$false = $Rd">, UnaryDP {
2882 let Inst{19-16} = 0b0000;
2883 let Inst{15-12} = Rd;
2884 let Inst{11-0} = imm;
2886 } // neverHasSideEffects
2888 //===----------------------------------------------------------------------===//
2889 // Atomic operations intrinsics
2892 def memb_opt : Operand<i32> {
2893 let PrintMethod = "printMemBOption";
2896 // memory barriers protect the atomic sequences
2897 let hasSideEffects = 1 in {
2898 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
2899 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2900 Requires<[IsARM, HasDB]> {
2902 let Inst{31-4} = 0xf57ff05;
2903 let Inst{3-0} = opt;
2906 def DMB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary,
2907 "mcr", "\tp15, 0, $zero, c7, c10, 5",
2908 [(ARMMemBarrierMCR GPR:$zero)]>,
2909 Requires<[IsARM, HasV6]> {
2910 // FIXME: add encoding
2914 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
2916 [/* For disassembly only; pattern left blank */]>,
2917 Requires<[IsARM, HasDB]> {
2919 let Inst{31-4} = 0xf57ff04;
2920 let Inst{3-0} = opt;
2923 // ISB has only full system option -- for disassembly only
2924 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
2925 Requires<[IsARM, HasDB]> {
2926 let Inst{31-4} = 0xf57ff06;
2927 let Inst{3-0} = 0b1111;
2930 let usesCustomInserter = 1 in {
2931 let Uses = [CPSR] in {
2932 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
2933 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2934 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
2935 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
2936 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2937 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
2938 def ATOMIC_LOAD_AND_I8 : PseudoInst<
2939 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2940 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
2941 def ATOMIC_LOAD_OR_I8 : PseudoInst<
2942 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2943 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
2944 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
2945 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2946 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
2947 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
2948 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2949 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
2950 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
2951 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2952 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
2953 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
2954 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2955 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
2956 def ATOMIC_LOAD_AND_I16 : PseudoInst<
2957 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2958 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
2959 def ATOMIC_LOAD_OR_I16 : PseudoInst<
2960 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2961 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
2962 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
2963 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2964 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
2965 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
2966 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2967 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
2968 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
2969 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2970 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
2971 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
2972 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2973 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
2974 def ATOMIC_LOAD_AND_I32 : PseudoInst<
2975 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2976 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
2977 def ATOMIC_LOAD_OR_I32 : PseudoInst<
2978 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2979 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
2980 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
2981 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2982 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
2983 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
2984 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2985 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
2987 def ATOMIC_SWAP_I8 : PseudoInst<
2988 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, "",
2989 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
2990 def ATOMIC_SWAP_I16 : PseudoInst<
2991 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, "",
2992 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
2993 def ATOMIC_SWAP_I32 : PseudoInst<
2994 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, "",
2995 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
2997 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
2998 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, "",
2999 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3000 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3001 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, "",
3002 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3003 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3004 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, "",
3005 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3009 let mayLoad = 1 in {
3010 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3011 "ldrexb", "\t$Rt, [$Rn]",
3013 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3014 "ldrexh", "\t$Rt, [$Rn]",
3016 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3017 "ldrex", "\t$Rt, [$Rn]",
3019 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins GPR:$Rn),
3021 "ldrexd", "\t$Rt, $Rt2, [$Rn]",
3025 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3026 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$src, GPR:$Rn),
3028 "strexb", "\t$Rd, $src, [$Rn]",
3030 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3032 "strexh", "\t$Rd, $Rt, [$Rn]",
3034 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3036 "strex", "\t$Rd, $Rt, [$Rn]",
3038 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3039 (ins GPR:$Rt, GPR:$Rt2, GPR:$Rn),
3041 "strexd", "\t$Rd, $Rt, $Rt2, [$Rn]",
3045 // Clear-Exclusive is for disassembly only.
3046 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3047 [/* For disassembly only; pattern left blank */]>,
3048 Requires<[IsARM, HasV7]> {
3049 let Inst{31-0} = 0b11110101011111111111000000011111;
3052 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3053 let mayLoad = 1 in {
3054 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3055 [/* For disassembly only; pattern left blank */]>;
3056 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3057 [/* For disassembly only; pattern left blank */]>;
3060 //===----------------------------------------------------------------------===//
3064 // __aeabi_read_tp preserves the registers r1-r3.
3065 // FIXME: This needs to be a pseudo of some sort so that we can get the
3066 // encoding right, complete with fixup for the aeabi_read_tp function.
3068 Defs = [R0, R12, LR, CPSR] in {
3069 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
3070 "bl\t__aeabi_read_tp",
3071 [(set R0, ARMthread_pointer)]>;
3074 //===----------------------------------------------------------------------===//
3075 // SJLJ Exception handling intrinsics
3076 // eh_sjlj_setjmp() is an instruction sequence to store the return
3077 // address and save #0 in R0 for the non-longjmp case.
3078 // Since by its nature we may be coming from some other function to get
3079 // here, and we're using the stack frame for the containing function to
3080 // save/restore registers, we can't keep anything live in regs across
3081 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3082 // when we get here from a longjmp(). We force everthing out of registers
3083 // except for our own input by listing the relevant registers in Defs. By
3084 // doing so, we also cause the prologue/epilogue code to actively preserve
3085 // all of the callee-saved resgisters, which is exactly what we want.
3086 // A constant value is passed in $val, and we use the location as a scratch.
3088 // These are pseudo-instructions and are lowered to individual MC-insts, so
3089 // no encoding information is necessary.
3091 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
3092 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
3093 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
3094 D31 ], hasSideEffects = 1, isBarrier = 1 in {
3095 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src, GPR:$val),
3096 AddrModeNone, SizeSpecial, IndexModeNone,
3097 Pseudo, NoItinerary, "", "",
3098 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3099 Requires<[IsARM, HasVFP2]>;
3103 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
3104 hasSideEffects = 1, isBarrier = 1 in {
3105 def Int_eh_sjlj_setjmp_nofp : XI<(outs), (ins GPR:$src, GPR:$val),
3106 AddrModeNone, SizeSpecial, IndexModeNone,
3107 Pseudo, NoItinerary, "", "",
3108 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3109 Requires<[IsARM, NoVFP]>;
3112 // FIXME: Non-Darwin version(s)
3113 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3114 Defs = [ R7, LR, SP ] in {
3115 def Int_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
3116 AddrModeNone, SizeSpecial, IndexModeNone,
3117 Pseudo, NoItinerary, "", "",
3118 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3119 Requires<[IsARM, IsDarwin]>;
3122 // eh.sjlj.dispatchsetup pseudo-instruction.
3123 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3124 // handled when the pseudo is expanded (which happens before any passes
3125 // that need the instruction size).
3126 let isBarrier = 1, hasSideEffects = 1 in
3127 def Int_eh_sjlj_dispatchsetup :
3128 PseudoInst<(outs), (ins GPR:$src), NoItinerary, "",
3129 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
3130 Requires<[IsDarwin]>;
3132 //===----------------------------------------------------------------------===//
3133 // Non-Instruction Patterns
3136 // Large immediate handling.
3138 // Two piece so_imms.
3139 // FIXME: Remove this when we can do generalized remat.
3140 let isReMaterializable = 1 in
3141 def MOVi2pieces : PseudoInst<(outs GPR:$dst), (ins so_imm2part:$src),
3143 [(set GPR:$dst, (so_imm2part:$src))]>,
3144 Requires<[IsARM, NoV6T2]>;
3146 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
3147 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
3148 (so_imm2part_2 imm:$RHS))>;
3149 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
3150 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
3151 (so_imm2part_2 imm:$RHS))>;
3152 def : ARMPat<(add GPR:$LHS, so_imm2part:$RHS),
3153 (ADDri (ADDri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
3154 (so_imm2part_2 imm:$RHS))>;
3155 def : ARMPat<(add GPR:$LHS, so_neg_imm2part:$RHS),
3156 (SUBri (SUBri GPR:$LHS, (so_neg_imm2part_1 imm:$RHS)),
3157 (so_neg_imm2part_2 imm:$RHS))>;
3159 // 32-bit immediate using movw + movt.
3160 // This is a single pseudo instruction, the benefit is that it can be remat'd
3161 // as a single unit instead of having to handle reg inputs.
3162 // FIXME: Remove this when we can do generalized remat.
3163 let isReMaterializable = 1 in
3164 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, "",
3165 [(set GPR:$dst, (i32 imm:$src))]>,
3166 Requires<[IsARM, HasV6T2]>;
3168 // ConstantPool, GlobalAddress, and JumpTable
3169 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3170 Requires<[IsARM, DontUseMovt]>;
3171 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3172 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3173 Requires<[IsARM, UseMovt]>;
3174 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3175 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3177 // TODO: add,sub,and, 3-instr forms?
3180 def : ARMPat<(ARMtcret tcGPR:$dst),
3181 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3183 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3184 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3186 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3187 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3189 def : ARMPat<(ARMtcret tcGPR:$dst),
3190 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3192 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3193 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3195 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3196 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3199 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3200 Requires<[IsARM, IsNotDarwin]>;
3201 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3202 Requires<[IsARM, IsDarwin]>;
3204 // zextload i1 -> zextload i8
3205 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3206 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3208 // extload -> zextload
3209 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3210 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3211 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3212 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3214 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3216 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3217 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3220 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3221 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3222 (SMULBB GPR:$a, GPR:$b)>;
3223 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3224 (SMULBB GPR:$a, GPR:$b)>;
3225 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3226 (sra GPR:$b, (i32 16))),
3227 (SMULBT GPR:$a, GPR:$b)>;
3228 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3229 (SMULBT GPR:$a, GPR:$b)>;
3230 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3231 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3232 (SMULTB GPR:$a, GPR:$b)>;
3233 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3234 (SMULTB GPR:$a, GPR:$b)>;
3235 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3237 (SMULWB GPR:$a, GPR:$b)>;
3238 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3239 (SMULWB GPR:$a, GPR:$b)>;
3241 def : ARMV5TEPat<(add GPR:$acc,
3242 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3243 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3244 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3245 def : ARMV5TEPat<(add GPR:$acc,
3246 (mul sext_16_node:$a, sext_16_node:$b)),
3247 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3248 def : ARMV5TEPat<(add GPR:$acc,
3249 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3250 (sra GPR:$b, (i32 16)))),
3251 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3252 def : ARMV5TEPat<(add GPR:$acc,
3253 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3254 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3255 def : ARMV5TEPat<(add GPR:$acc,
3256 (mul (sra GPR:$a, (i32 16)),
3257 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3258 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3259 def : ARMV5TEPat<(add GPR:$acc,
3260 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3261 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3262 def : ARMV5TEPat<(add GPR:$acc,
3263 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3265 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3266 def : ARMV5TEPat<(add GPR:$acc,
3267 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3268 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3270 //===----------------------------------------------------------------------===//
3274 include "ARMInstrThumb.td"
3276 //===----------------------------------------------------------------------===//
3280 include "ARMInstrThumb2.td"
3282 //===----------------------------------------------------------------------===//
3283 // Floating Point Support
3286 include "ARMInstrVFP.td"
3288 //===----------------------------------------------------------------------===//
3289 // Advanced SIMD (NEON) Support
3292 include "ARMInstrNEON.td"
3294 //===----------------------------------------------------------------------===//
3295 // Coprocessor Instructions. For disassembly only.
3298 def CDP : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3299 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3300 NoItinerary, "cdp", "\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3301 [/* For disassembly only; pattern left blank */]> {
3305 def CDP2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3306 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3307 NoItinerary, "cdp2\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3308 [/* For disassembly only; pattern left blank */]> {
3309 let Inst{31-28} = 0b1111;
3313 class ACI<dag oops, dag iops, string opc, string asm>
3314 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
3315 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3316 let Inst{27-25} = 0b110;
3319 multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
3321 def _OFFSET : ACI<(outs),
3322 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3323 opc, "\tp$cop, cr$CRd, $addr"> {
3324 let Inst{31-28} = op31_28;
3325 let Inst{24} = 1; // P = 1
3326 let Inst{21} = 0; // W = 0
3327 let Inst{22} = 0; // D = 0
3328 let Inst{20} = load;
3331 def _PRE : ACI<(outs),
3332 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3333 opc, "\tp$cop, cr$CRd, $addr!"> {
3334 let Inst{31-28} = op31_28;
3335 let Inst{24} = 1; // P = 1
3336 let Inst{21} = 1; // W = 1
3337 let Inst{22} = 0; // D = 0
3338 let Inst{20} = load;
3341 def _POST : ACI<(outs),
3342 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3343 opc, "\tp$cop, cr$CRd, [$base], $offset"> {
3344 let Inst{31-28} = op31_28;
3345 let Inst{24} = 0; // P = 0
3346 let Inst{21} = 1; // W = 1
3347 let Inst{22} = 0; // D = 0
3348 let Inst{20} = load;
3351 def _OPTION : ACI<(outs),
3352 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option),
3353 opc, "\tp$cop, cr$CRd, [$base], $option"> {
3354 let Inst{31-28} = op31_28;
3355 let Inst{24} = 0; // P = 0
3356 let Inst{23} = 1; // U = 1
3357 let Inst{21} = 0; // W = 0
3358 let Inst{22} = 0; // D = 0
3359 let Inst{20} = load;
3362 def L_OFFSET : ACI<(outs),
3363 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3364 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
3365 let Inst{31-28} = op31_28;
3366 let Inst{24} = 1; // P = 1
3367 let Inst{21} = 0; // W = 0
3368 let Inst{22} = 1; // D = 1
3369 let Inst{20} = load;
3372 def L_PRE : ACI<(outs),
3373 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3374 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
3375 let Inst{31-28} = op31_28;
3376 let Inst{24} = 1; // P = 1
3377 let Inst{21} = 1; // W = 1
3378 let Inst{22} = 1; // D = 1
3379 let Inst{20} = load;
3382 def L_POST : ACI<(outs),
3383 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3384 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $offset"> {
3385 let Inst{31-28} = op31_28;
3386 let Inst{24} = 0; // P = 0
3387 let Inst{21} = 1; // W = 1
3388 let Inst{22} = 1; // D = 1
3389 let Inst{20} = load;
3392 def L_OPTION : ACI<(outs),
3393 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
3394 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $option"> {
3395 let Inst{31-28} = op31_28;
3396 let Inst{24} = 0; // P = 0
3397 let Inst{23} = 1; // U = 1
3398 let Inst{21} = 0; // W = 0
3399 let Inst{22} = 1; // D = 1
3400 let Inst{20} = load;
3404 defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">;
3405 defm LDC2 : LdStCop<0b1111, 1, "ldc2">;
3406 defm STC : LdStCop<{?,?,?,?}, 0, "stc">;
3407 defm STC2 : LdStCop<0b1111, 0, "stc2">;
3409 def MCR : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3410 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3411 NoItinerary, "mcr", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3412 [/* For disassembly only; pattern left blank */]> {
3417 def MCR2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3418 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3419 NoItinerary, "mcr2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3420 [/* For disassembly only; pattern left blank */]> {
3421 let Inst{31-28} = 0b1111;
3426 def MRC : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3427 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3428 NoItinerary, "mrc", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3429 [/* For disassembly only; pattern left blank */]> {
3434 def MRC2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3435 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3436 NoItinerary, "mrc2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3437 [/* For disassembly only; pattern left blank */]> {
3438 let Inst{31-28} = 0b1111;
3443 def MCRR : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3444 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3445 NoItinerary, "mcrr", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3446 [/* For disassembly only; pattern left blank */]> {
3447 let Inst{23-20} = 0b0100;
3450 def MCRR2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3451 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3452 NoItinerary, "mcrr2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3453 [/* For disassembly only; pattern left blank */]> {
3454 let Inst{31-28} = 0b1111;
3455 let Inst{23-20} = 0b0100;
3458 def MRRC : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3459 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3460 NoItinerary, "mrrc", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3461 [/* For disassembly only; pattern left blank */]> {
3462 let Inst{23-20} = 0b0101;
3465 def MRRC2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3466 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3467 NoItinerary, "mrrc2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3468 [/* For disassembly only; pattern left blank */]> {
3469 let Inst{31-28} = 0b1111;
3470 let Inst{23-20} = 0b0101;
3473 //===----------------------------------------------------------------------===//
3474 // Move between special register and ARM core register -- for disassembly only
3477 def MRS : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary, "mrs", "\t$dst, cpsr",
3478 [/* For disassembly only; pattern left blank */]> {
3479 let Inst{23-20} = 0b0000;
3480 let Inst{7-4} = 0b0000;
3483 def MRSsys : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary,"mrs","\t$dst, spsr",
3484 [/* For disassembly only; pattern left blank */]> {
3485 let Inst{23-20} = 0b0100;
3486 let Inst{7-4} = 0b0000;
3489 def MSR : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3490 "msr", "\tcpsr$mask, $src",
3491 [/* For disassembly only; pattern left blank */]> {
3492 let Inst{23-20} = 0b0010;
3493 let Inst{7-4} = 0b0000;
3496 def MSRi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3497 "msr", "\tcpsr$mask, $a",
3498 [/* For disassembly only; pattern left blank */]> {
3499 let Inst{23-20} = 0b0010;
3500 let Inst{7-4} = 0b0000;
3503 def MSRsys : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3504 "msr", "\tspsr$mask, $src",
3505 [/* For disassembly only; pattern left blank */]> {
3506 let Inst{23-20} = 0b0110;
3507 let Inst{7-4} = 0b0000;
3510 def MSRsysi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3511 "msr", "\tspsr$mask, $a",
3512 [/* For disassembly only; pattern left blank */]> {
3513 let Inst{23-20} = 0b0110;
3514 let Inst{7-4} = 0b0000;