1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
39 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
40 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
42 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
43 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
46 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
47 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
49 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
50 [SDNPHasChain, SDNPOutFlag]>;
51 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
52 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
54 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
55 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
56 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
57 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
58 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
59 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
61 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
62 [SDNPHasChain, SDNPOptInFlag]>;
64 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
66 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
69 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
70 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
72 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
75 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
78 def ARMcmpNZ : SDNode<"ARMISD::CMPNZ", SDT_ARMCmp,
81 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
83 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
84 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
85 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
87 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
88 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", SDT_ARMEH_SJLJ_Setjmp>;
90 //===----------------------------------------------------------------------===//
91 // ARM Instruction Predicate Definitions.
93 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
94 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
95 def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
96 def IsThumb : Predicate<"Subtarget->isThumb()">;
97 def IsThumb2 : Predicate<"Subtarget->isThumb2()">;
98 def IsARM : Predicate<"!Subtarget->isThumb()">;
100 //===----------------------------------------------------------------------===//
101 // ARM Flag Definitions.
103 class RegConstraint<string C> {
104 string Constraints = C;
107 //===----------------------------------------------------------------------===//
108 // ARM specific transformation functions and pattern fragments.
111 // so_imm_XFORM - Return a so_imm value packed into the format described for
113 def so_imm_XFORM : SDNodeXForm<imm, [{
114 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(N->getZExtValue()),
118 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
119 // so_imm_neg def below.
120 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
121 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(-(int)N->getZExtValue()),
125 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
126 // so_imm_not def below.
127 def so_imm_not_XFORM : SDNodeXForm<imm, [{
128 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(~(int)N->getZExtValue()),
132 // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
133 def rot_imm : PatLeaf<(i32 imm), [{
134 int32_t v = (int32_t)N->getZExtValue();
135 return v == 8 || v == 16 || v == 24;
138 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
139 def imm1_15 : PatLeaf<(i32 imm), [{
140 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
143 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
144 def imm16_31 : PatLeaf<(i32 imm), [{
145 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
150 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
151 }], so_imm_neg_XFORM>;
155 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
156 }], so_imm_not_XFORM>;
158 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
159 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
160 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
163 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
164 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
166 //===----------------------------------------------------------------------===//
167 // Operand Definitions.
171 def brtarget : Operand<OtherVT>;
173 // A list of registers separated by comma. Used by load/store multiple.
174 def reglist : Operand<i32> {
175 let PrintMethod = "printRegisterList";
178 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
179 def cpinst_operand : Operand<i32> {
180 let PrintMethod = "printCPInstOperand";
183 def jtblock_operand : Operand<i32> {
184 let PrintMethod = "printJTBlockOperand";
188 def pclabel : Operand<i32> {
189 let PrintMethod = "printPCLabel";
192 // shifter_operand operands: so_reg and so_imm.
193 def so_reg : Operand<i32>, // reg reg imm
194 ComplexPattern<i32, 3, "SelectShifterOperandReg",
195 [shl,srl,sra,rotr]> {
196 let PrintMethod = "printSORegOperand";
197 let MIOperandInfo = (ops GPR, GPR, i32imm);
200 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
201 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
202 // represented in the imm field in the same 12-bit form that they are encoded
203 // into so_imm instructions: the 8-bit immediate is the least significant bits
204 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
205 def so_imm : Operand<i32>,
207 [{ return ARM_AM::getSOImmVal(N->getZExtValue()) != -1; }],
209 let PrintMethod = "printSOImmOperand";
212 // Break so_imm's up into two pieces. This handles immediates with up to 16
213 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
214 // get the first/second pieces.
215 def so_imm2part : Operand<i32>,
217 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
219 let PrintMethod = "printSOImm2PartOperand";
222 def so_imm2part_1 : SDNodeXForm<imm, [{
223 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
224 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
227 def so_imm2part_2 : SDNodeXForm<imm, [{
228 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
229 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
233 // Define ARM specific addressing modes.
235 // addrmode2 := reg +/- reg shop imm
236 // addrmode2 := reg +/- imm12
238 def addrmode2 : Operand<i32>,
239 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
240 let PrintMethod = "printAddrMode2Operand";
241 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
244 def am2offset : Operand<i32>,
245 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
246 let PrintMethod = "printAddrMode2OffsetOperand";
247 let MIOperandInfo = (ops GPR, i32imm);
250 // addrmode3 := reg +/- reg
251 // addrmode3 := reg +/- imm8
253 def addrmode3 : Operand<i32>,
254 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
255 let PrintMethod = "printAddrMode3Operand";
256 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
259 def am3offset : Operand<i32>,
260 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
261 let PrintMethod = "printAddrMode3OffsetOperand";
262 let MIOperandInfo = (ops GPR, i32imm);
265 // addrmode4 := reg, <mode|W>
267 def addrmode4 : Operand<i32>,
268 ComplexPattern<i32, 2, "", []> {
269 let PrintMethod = "printAddrMode4Operand";
270 let MIOperandInfo = (ops GPR, i32imm);
273 // addrmode5 := reg +/- imm8*4
275 def addrmode5 : Operand<i32>,
276 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
277 let PrintMethod = "printAddrMode5Operand";
278 let MIOperandInfo = (ops GPR, i32imm);
281 // addrmodepc := pc + reg
283 def addrmodepc : Operand<i32>,
284 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
285 let PrintMethod = "printAddrModePCOperand";
286 let MIOperandInfo = (ops GPR, i32imm);
289 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
290 // register whose default is 0 (no register).
291 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
292 (ops (i32 14), (i32 zero_reg))> {
293 let PrintMethod = "printPredicateOperand";
296 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
298 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
299 let PrintMethod = "printSBitModifierOperand";
302 //===----------------------------------------------------------------------===//
303 // ARM Instruction flags. These need to match ARMInstrInfo.h.
307 class AddrMode<bits<4> val> {
310 def AddrModeNone : AddrMode<0>;
311 def AddrMode1 : AddrMode<1>;
312 def AddrMode2 : AddrMode<2>;
313 def AddrMode3 : AddrMode<3>;
314 def AddrMode4 : AddrMode<4>;
315 def AddrMode5 : AddrMode<5>;
316 def AddrModeT1 : AddrMode<6>;
317 def AddrModeT2 : AddrMode<7>;
318 def AddrModeT4 : AddrMode<8>;
319 def AddrModeTs : AddrMode<9>;
322 class SizeFlagVal<bits<3> val> {
325 def SizeInvalid : SizeFlagVal<0>; // Unset.
326 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
327 def Size8Bytes : SizeFlagVal<2>;
328 def Size4Bytes : SizeFlagVal<3>;
329 def Size2Bytes : SizeFlagVal<4>;
331 // Load / store index mode.
332 class IndexMode<bits<2> val> {
335 def IndexModeNone : IndexMode<0>;
336 def IndexModePre : IndexMode<1>;
337 def IndexModePost : IndexMode<2>;
339 //===----------------------------------------------------------------------===//
341 include "ARMInstrFormats.td"
343 //===----------------------------------------------------------------------===//
344 // Multiclass helpers...
347 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
348 /// binop that produces a value.
349 multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode> {
350 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
351 opc, " $dst, $a, $b",
352 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
353 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
354 opc, " $dst, $a, $b",
355 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
356 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
357 opc, " $dst, $a, $b",
358 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
361 /// ASI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
362 /// instruction modifies the CSPR register.
363 let Defs = [CPSR] in {
364 multiclass ASI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode> {
365 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
366 opc, "s $dst, $a, $b",
367 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
368 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
369 opc, "s $dst, $a, $b",
370 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
371 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
372 opc, "s $dst, $a, $b",
373 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
377 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
378 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
379 /// a explicit result, only implicitly set CPSR.
380 let Defs = [CPSR] in {
381 multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> {
382 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm,
384 [(opnode GPR:$a, so_imm:$b)]>;
385 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm,
387 [(opnode GPR:$a, GPR:$b)]>;
388 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
390 [(opnode GPR:$a, so_reg:$b)]>;
394 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
395 /// register and one whose operand is a register rotated by 8/16/24.
396 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
397 multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
398 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$Src),
400 [(set GPR:$dst, (opnode GPR:$Src))]>,
401 Requires<[IsARM, HasV6]> {
402 let Inst{19-16} = 0b1111;
404 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$Src, i32imm:$rot),
405 opc, " $dst, $Src, ror $rot",
406 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>,
407 Requires<[IsARM, HasV6]> {
408 let Inst{19-16} = 0b1111;
412 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
413 /// register and one whose operand is a register rotated by 8/16/24.
414 multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
415 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
416 opc, " $dst, $LHS, $RHS",
417 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
418 Requires<[IsARM, HasV6]>;
419 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
420 opc, " $dst, $LHS, $RHS, ror $rot",
421 [(set GPR:$dst, (opnode GPR:$LHS,
422 (rotr GPR:$RHS, rot_imm:$rot)))]>,
423 Requires<[IsARM, HasV6]>;
426 /// AsXI1_bin_c_irs - Same as AsI1_bin_irs but without the predicate operand and
427 /// setting carry bit. But it can optionally set CPSR.
428 let Uses = [CPSR] in {
429 multiclass AsXI1_bin_c_irs<bits<4> opcod, string opc, PatFrag opnode> {
430 def ri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
431 DPFrm, !strconcat(opc, "${s} $dst, $a, $b"),
432 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
433 def rr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, cc_out:$s),
434 DPFrm, !strconcat(opc, "${s} $dst, $a, $b"),
435 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
436 def rs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
437 DPSoRegFrm, !strconcat(opc, "${s} $dst, $a, $b"),
438 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
442 //===----------------------------------------------------------------------===//
444 //===----------------------------------------------------------------------===//
446 //===----------------------------------------------------------------------===//
447 // Miscellaneous Instructions.
450 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
451 /// the function. The first operand is the ID# for this instruction, the second
452 /// is the index into the MachineConstantPool that this is, the third is the
453 /// size in bytes of this constant pool entry.
454 let isNotDuplicable = 1 in
455 def CONSTPOOL_ENTRY :
456 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
458 "${instid:label} ${cpidx:cpentry}", []>;
460 let Defs = [SP], Uses = [SP] in {
462 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p),
463 "@ ADJCALLSTACKUP $amt1",
464 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
466 def ADJCALLSTACKDOWN :
467 PseudoInst<(outs), (ins i32imm:$amt, pred:$p),
468 "@ ADJCALLSTACKDOWN $amt",
469 [(ARMcallseq_start timm:$amt)]>;
473 PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
474 ".loc $file, $line, $col",
475 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
478 // Address computation and loads and stores in PIC mode.
479 let isNotDuplicable = 1 in {
480 def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
481 Pseudo, "$cp:\n\tadd$p $dst, pc, $a",
482 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
484 let AddedComplexity = 10 in {
485 let canFoldAsLoad = 1 in
486 def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
487 Pseudo, "${addr:label}:\n\tldr$p $dst, $addr",
488 [(set GPR:$dst, (load addrmodepc:$addr))]>;
490 def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
491 Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr",
492 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
494 def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
495 Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr",
496 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
498 def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
499 Pseudo, "${addr:label}:\n\tldr${p}sh $dst, $addr",
500 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
502 def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
503 Pseudo, "${addr:label}:\n\tldr${p}sb $dst, $addr",
504 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
506 let AddedComplexity = 10 in {
507 def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
508 Pseudo, "${addr:label}:\n\tstr$p $src, $addr",
509 [(store GPR:$src, addrmodepc:$addr)]>;
511 def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
512 Pseudo, "${addr:label}:\n\tstr${p}h $src, $addr",
513 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
515 def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
516 Pseudo, "${addr:label}:\n\tstr${p}b $src, $addr",
517 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
519 } // isNotDuplicable = 1
521 //===----------------------------------------------------------------------===//
522 // Control Flow Instructions.
525 let isReturn = 1, isTerminator = 1 in
526 def BX_RET : AI<(outs), (ins), BrMiscFrm, "bx", " lr", [(ARMretflag)]> {
527 let Inst{7-4} = 0b0001;
528 let Inst{19-8} = 0b111111111111;
529 let Inst{27-20} = 0b00010010;
532 // FIXME: remove when we have a way to marking a MI with these properties.
533 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
535 // FIXME: Should pc be an implicit operand like PICADD, etc?
536 let isReturn = 1, isTerminator = 1 in
537 def LDM_RET : AXI4ld<(outs),
538 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
539 LdStMulFrm, "ldm${p}${addr:submode} $addr, $dst1",
543 Defs = [R0, R1, R2, R3, R12, LR,
544 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
545 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
547 [(ARMcall tglobaladdr:$func)]>;
549 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
550 "bl", " ${func:call}",
551 [(ARMcall_pred tglobaladdr:$func)]>;
554 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
556 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T]> {
557 let Inst{7-4} = 0b0011;
558 let Inst{19-8} = 0b111111111111;
559 let Inst{27-20} = 0b00010010;
564 def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops),
565 "mov lr, pc\n\tbx $func",
566 [(ARMcall_nolink GPR:$func)]>;
570 let isBranch = 1, isTerminator = 1 in {
571 // B is "predicable" since it can be xformed into a Bcc.
572 let isBarrier = 1 in {
573 let isPredicable = 1 in
574 def B : ABXI<0b1010, (outs), (ins brtarget:$target), "b $target",
577 let isNotDuplicable = 1, isIndirectBranch = 1 in {
578 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
579 "mov pc, $target \n$jt",
580 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
581 let Inst{20} = 0; // S Bit
582 let Inst{24-21} = 0b1101;
583 let Inst{27-26} = {0,0};
585 def BR_JTm : JTI<(outs),
586 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
587 "ldr pc, $target \n$jt",
588 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
590 let Inst{20} = 1; // L bit
591 let Inst{21} = 0; // W bit
592 let Inst{22} = 0; // B bit
593 let Inst{24} = 1; // P bit
594 let Inst{27-26} = {0,1};
596 def BR_JTadd : JTI<(outs),
597 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
598 "add pc, $target, $idx \n$jt",
599 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
601 let Inst{20} = 0; // S bit
602 let Inst{24-21} = 0b0100;
603 let Inst{27-26} = {0,0};
605 } // isNotDuplicable = 1, isIndirectBranch = 1
608 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
609 // a two-value operand where a dag node expects two operands. :(
610 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
612 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
615 //===----------------------------------------------------------------------===//
616 // Load / store Instructions.
620 let canFoldAsLoad = 1 in
621 def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
622 "ldr", " $dst, $addr",
623 [(set GPR:$dst, (load addrmode2:$addr))]>;
625 // Special LDR for loads from non-pc-relative constpools.
626 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
627 def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
628 "ldr", " $dst, $addr", []>;
630 // Loads with zero extension
631 def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
632 "ldr", "h $dst, $addr",
633 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
635 def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
636 "ldr", "b $dst, $addr",
637 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
639 // Loads with sign extension
640 def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
641 "ldr", "sh $dst, $addr",
642 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
644 def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
645 "ldr", "sb $dst, $addr",
646 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
650 def LDRD : AI3ldd<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
651 "ldr", "d $dst, $addr",
652 []>, Requires<[IsARM, HasV5T]>;
655 def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
656 (ins addrmode2:$addr), LdFrm,
657 "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>;
659 def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
660 (ins GPR:$base, am2offset:$offset), LdFrm,
661 "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>;
663 def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
664 (ins addrmode3:$addr), LdMiscFrm,
665 "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>;
667 def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
668 (ins GPR:$base,am3offset:$offset), LdMiscFrm,
669 "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>;
671 def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
672 (ins addrmode2:$addr), LdFrm,
673 "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>;
675 def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
676 (ins GPR:$base,am2offset:$offset), LdFrm,
677 "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>;
679 def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
680 (ins addrmode3:$addr), LdMiscFrm,
681 "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>;
683 def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
684 (ins GPR:$base,am3offset:$offset), LdMiscFrm,
685 "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>;
687 def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
688 (ins addrmode3:$addr), LdMiscFrm,
689 "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>;
691 def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
692 (ins GPR:$base,am3offset:$offset), LdMiscFrm,
693 "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
697 def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm,
698 "str", " $src, $addr",
699 [(store GPR:$src, addrmode2:$addr)]>;
701 // Stores with truncate
702 def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm,
703 "str", "h $src, $addr",
704 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
706 def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm,
707 "str", "b $src, $addr",
708 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
712 def STRD : AI3std<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm,
713 "str", "d $src, $addr",
714 []>, Requires<[IsARM, HasV5T]>;
717 def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
718 (ins GPR:$src, GPR:$base, am2offset:$offset), StFrm,
719 "str", " $src, [$base, $offset]!", "$base = $base_wb",
721 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
723 def STR_POST : AI2stwpo<(outs GPR:$base_wb),
724 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
725 "str", " $src, [$base], $offset", "$base = $base_wb",
727 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
729 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
730 (ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm,
731 "str", "h $src, [$base, $offset]!", "$base = $base_wb",
733 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
735 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
736 (ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm,
737 "str", "h $src, [$base], $offset", "$base = $base_wb",
738 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
739 GPR:$base, am3offset:$offset))]>;
741 def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
742 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
743 "str", "b $src, [$base, $offset]!", "$base = $base_wb",
744 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
745 GPR:$base, am2offset:$offset))]>;
747 def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
748 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
749 "str", "b $src, [$base], $offset", "$base = $base_wb",
750 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
751 GPR:$base, am2offset:$offset))]>;
753 //===----------------------------------------------------------------------===//
754 // Load / store multiple Instructions.
757 // FIXME: $dst1 should be a def.
759 def LDM : AXI4ld<(outs),
760 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
761 LdStMulFrm, "ldm${p}${addr:submode} $addr, $dst1",
765 def STM : AXI4st<(outs),
766 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
767 LdStMulFrm, "stm${p}${addr:submode} $addr, $src1",
770 //===----------------------------------------------------------------------===//
771 // Move Instructions.
774 def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm,
775 "mov", " $dst, $src", []>, UnaryDP;
776 def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
777 "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP;
779 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
780 def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm,
781 "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP;
783 def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
784 "mov", " $dst, $src, rrx",
785 [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
787 // These aren't really mov instructions, but we have to define them this way
788 // due to flag operands.
790 let Defs = [CPSR] in {
791 def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
792 "mov", "s $dst, $src, lsr #1",
793 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP;
794 def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
795 "mov", "s $dst, $src, asr #1",
796 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP;
799 //===----------------------------------------------------------------------===//
800 // Extend Instructions.
805 defm SXTB : AI_unary_rrot<0b01101010,
806 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
807 defm SXTH : AI_unary_rrot<0b01101011,
808 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
810 defm SXTAB : AI_bin_rrot<0b01101010,
811 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
812 defm SXTAH : AI_bin_rrot<0b01101011,
813 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
815 // TODO: SXT(A){B|H}16
819 let AddedComplexity = 16 in {
820 defm UXTB : AI_unary_rrot<0b01101110,
821 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
822 defm UXTH : AI_unary_rrot<0b01101111,
823 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
824 defm UXTB16 : AI_unary_rrot<0b01101100,
825 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
827 def : ARMV6Pat<(and (shl GPR:$Src, 8), 0xFF00FF),
828 (UXTB16r_rot GPR:$Src, 24)>;
829 def : ARMV6Pat<(and (srl GPR:$Src, 8), 0xFF00FF),
830 (UXTB16r_rot GPR:$Src, 8)>;
832 defm UXTAB : AI_bin_rrot<0b01101110, "uxtab",
833 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
834 defm UXTAH : AI_bin_rrot<0b01101111, "uxtah",
835 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
838 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
839 //defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
841 // TODO: UXT(A){B|H}16
843 //===----------------------------------------------------------------------===//
844 // Arithmetic Instructions.
847 defm ADD : AsI1_bin_irs<0b0100, "add",
848 BinOpFrag<(add node:$LHS, node:$RHS)>>;
849 defm SUB : AsI1_bin_irs<0b0010, "sub",
850 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
852 // ADD and SUB with 's' bit set.
853 defm ADDS : ASI1_bin_s_irs<0b0100, "add",
854 BinOpFrag<(addc node:$LHS, node:$RHS)>>;
855 defm SUBS : ASI1_bin_s_irs<0b0010, "sub",
856 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
858 // FIXME: Do not allow ADC / SBC to be predicated for now.
859 defm ADC : AsXI1_bin_c_irs<0b0101, "adc",
860 BinOpFrag<(adde node:$LHS, node:$RHS)>>;
861 defm SBC : AsXI1_bin_c_irs<0b0110, "sbc",
862 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
864 // These don't define reg/reg forms, because they are handled above.
865 def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
866 "rsb", " $dst, $a, $b",
867 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>;
869 def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
870 "rsb", " $dst, $a, $b",
871 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>;
873 // RSB with 's' bit set.
874 let Defs = [CPSR] in {
875 def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
876 "rsb", "s $dst, $a, $b",
877 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>;
878 def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
879 "rsb", "s $dst, $a, $b",
880 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>;
883 // FIXME: Do not allow RSC to be predicated for now. But they can set CPSR.
884 let Uses = [CPSR] in {
885 def RSCri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
886 DPFrm, "rsc${s} $dst, $a, $b",
887 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>;
888 def RSCrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
889 DPSoRegFrm, "rsc${s} $dst, $a, $b",
890 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>;
893 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
894 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
895 (SUBri GPR:$src, so_imm_neg:$imm)>;
897 //def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
898 // (SUBSri GPR:$src, so_imm_neg:$imm)>;
899 //def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
900 // (SBCri GPR:$src, so_imm_neg:$imm)>;
902 // Note: These are implemented in C++ code, because they have to generate
903 // ADD/SUBrs instructions, which use a complex pattern that a xform function
905 // (mul X, 2^n+1) -> (add (X << n), X)
906 // (mul X, 2^n-1) -> (rsb X, (X << n))
909 //===----------------------------------------------------------------------===//
910 // Bitwise Instructions.
913 defm AND : AsI1_bin_irs<0b0000, "and",
914 BinOpFrag<(and node:$LHS, node:$RHS)>>;
915 defm ORR : AsI1_bin_irs<0b1100, "orr",
916 BinOpFrag<(or node:$LHS, node:$RHS)>>;
917 defm EOR : AsI1_bin_irs<0b0001, "eor",
918 BinOpFrag<(xor node:$LHS, node:$RHS)>>;
919 defm BIC : AsI1_bin_irs<0b1110, "bic",
920 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
922 def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm,
923 "mvn", " $dst, $src",
924 [(set GPR:$dst, (not GPR:$src))]>, UnaryDP;
925 def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
926 "mvn", " $dst, $src",
927 [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP;
928 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
929 def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
930 "mvn", " $dst, $imm",
931 [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP;
933 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
934 (BICri GPR:$src, so_imm_not:$imm)>;
936 //===----------------------------------------------------------------------===//
937 // Multiply Instructions.
940 def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
941 "mul", " $dst, $a, $b",
942 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
944 def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
945 "mla", " $dst, $a, $b, $c",
946 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
948 // Extra precision multiplies with low / high results
949 def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst),
950 (ins GPR:$a, GPR:$b),
951 "smull", " $ldst, $hdst, $a, $b", []>;
953 def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst),
954 (ins GPR:$a, GPR:$b),
955 "umull", " $ldst, $hdst, $a, $b", []>;
957 // Multiply + accumulate
958 def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst),
959 (ins GPR:$a, GPR:$b),
960 "smlal", " $ldst, $hdst, $a, $b", []>;
962 def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst),
963 (ins GPR:$a, GPR:$b),
964 "umlal", " $ldst, $hdst, $a, $b", []>;
966 def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst),
967 (ins GPR:$a, GPR:$b),
968 "umaal", " $ldst, $hdst, $a, $b", []>,
969 Requires<[IsARM, HasV6]>;
971 // Most significant word multiply
972 def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
973 "smmul", " $dst, $a, $b",
974 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
975 Requires<[IsARM, HasV6]> {
976 let Inst{7-4} = 0b0001;
977 let Inst{15-12} = 0b1111;
980 def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
981 "smmla", " $dst, $a, $b, $c",
982 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
983 Requires<[IsARM, HasV6]> {
984 let Inst{7-4} = 0b0001;
988 def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
989 "smmls", " $dst, $a, $b, $c",
990 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
991 Requires<[IsARM, HasV6]> {
992 let Inst{7-4} = 0b1101;
995 multiclass AI_smul<string opc, PatFrag opnode> {
996 def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
997 !strconcat(opc, "bb"), " $dst, $a, $b",
998 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
999 (sext_inreg GPR:$b, i16)))]>,
1000 Requires<[IsARM, HasV5TE]> {
1005 def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1006 !strconcat(opc, "bt"), " $dst, $a, $b",
1007 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1008 (sra GPR:$b, 16)))]>,
1009 Requires<[IsARM, HasV5TE]> {
1014 def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1015 !strconcat(opc, "tb"), " $dst, $a, $b",
1016 [(set GPR:$dst, (opnode (sra GPR:$a, 16),
1017 (sext_inreg GPR:$b, i16)))]>,
1018 Requires<[IsARM, HasV5TE]> {
1023 def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1024 !strconcat(opc, "tt"), " $dst, $a, $b",
1025 [(set GPR:$dst, (opnode (sra GPR:$a, 16),
1026 (sra GPR:$b, 16)))]>,
1027 Requires<[IsARM, HasV5TE]> {
1032 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1033 !strconcat(opc, "wb"), " $dst, $a, $b",
1034 [(set GPR:$dst, (sra (opnode GPR:$a,
1035 (sext_inreg GPR:$b, i16)), 16))]>,
1036 Requires<[IsARM, HasV5TE]> {
1041 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1042 !strconcat(opc, "wt"), " $dst, $a, $b",
1043 [(set GPR:$dst, (sra (opnode GPR:$a,
1044 (sra GPR:$b, 16)), 16))]>,
1045 Requires<[IsARM, HasV5TE]> {
1052 multiclass AI_smla<string opc, PatFrag opnode> {
1053 def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1054 !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
1055 [(set GPR:$dst, (add GPR:$acc,
1056 (opnode (sext_inreg GPR:$a, i16),
1057 (sext_inreg GPR:$b, i16))))]>,
1058 Requires<[IsARM, HasV5TE]> {
1063 def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1064 !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
1065 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1066 (sra GPR:$b, 16))))]>,
1067 Requires<[IsARM, HasV5TE]> {
1072 def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1073 !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
1074 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
1075 (sext_inreg GPR:$b, i16))))]>,
1076 Requires<[IsARM, HasV5TE]> {
1081 def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1082 !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
1083 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
1084 (sra GPR:$b, 16))))]>,
1085 Requires<[IsARM, HasV5TE]> {
1090 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1091 !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
1092 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1093 (sext_inreg GPR:$b, i16)), 16)))]>,
1094 Requires<[IsARM, HasV5TE]> {
1099 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1100 !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
1101 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1102 (sra GPR:$b, 16)), 16)))]>,
1103 Requires<[IsARM, HasV5TE]> {
1109 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1110 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1112 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
1113 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1115 //===----------------------------------------------------------------------===//
1116 // Misc. Arithmetic Instructions.
1119 def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src),
1120 "clz", " $dst, $src",
1121 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> {
1122 let Inst{7-4} = 0b0001;
1123 let Inst{11-8} = 0b1111;
1124 let Inst{19-16} = 0b1111;
1127 def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src),
1128 "rev", " $dst, $src",
1129 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> {
1130 let Inst{7-4} = 0b0011;
1131 let Inst{11-8} = 0b1111;
1132 let Inst{19-16} = 0b1111;
1135 def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src),
1136 "rev16", " $dst, $src",
1138 (or (and (srl GPR:$src, 8), 0xFF),
1139 (or (and (shl GPR:$src, 8), 0xFF00),
1140 (or (and (srl GPR:$src, 8), 0xFF0000),
1141 (and (shl GPR:$src, 8), 0xFF000000)))))]>,
1142 Requires<[IsARM, HasV6]> {
1143 let Inst{7-4} = 0b1011;
1144 let Inst{11-8} = 0b1111;
1145 let Inst{19-16} = 0b1111;
1148 def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src),
1149 "revsh", " $dst, $src",
1152 (or (srl (and GPR:$src, 0xFF00), 8),
1153 (shl GPR:$src, 8)), i16))]>,
1154 Requires<[IsARM, HasV6]> {
1155 let Inst{7-4} = 0b1011;
1156 let Inst{11-8} = 0b1111;
1157 let Inst{19-16} = 0b1111;
1160 def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst),
1161 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1162 "pkhbt", " $dst, $src1, $src2, LSL $shamt",
1163 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1164 (and (shl GPR:$src2, (i32 imm:$shamt)),
1166 Requires<[IsARM, HasV6]> {
1167 let Inst{6-4} = 0b001;
1170 // Alternate cases for PKHBT where identities eliminate some nodes.
1171 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1172 (PKHBT GPR:$src1, GPR:$src2, 0)>;
1173 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1174 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1177 def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst),
1178 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1179 "pkhtb", " $dst, $src1, $src2, ASR $shamt",
1180 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1181 (and (sra GPR:$src2, imm16_31:$shamt),
1182 0xFFFF)))]>, Requires<[IsARM, HasV6]> {
1183 let Inst{6-4} = 0b101;
1186 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
1187 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1188 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, 16)),
1189 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1190 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1191 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1192 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1194 //===----------------------------------------------------------------------===//
1195 // Comparison Instructions...
1198 defm CMP : AI1_cmp_irs<0b1010, "cmp",
1199 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1200 defm CMN : AI1_cmp_irs<0b1011, "cmn",
1201 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1203 // Note that TST/TEQ don't set all the same flags that CMP does!
1204 defm TST : AI1_cmp_irs<0b1000, "tst",
1205 BinOpFrag<(ARMcmpNZ (and node:$LHS, node:$RHS), 0)>>;
1206 defm TEQ : AI1_cmp_irs<0b1001, "teq",
1207 BinOpFrag<(ARMcmpNZ (xor node:$LHS, node:$RHS), 0)>>;
1209 defm CMPnz : AI1_cmp_irs<0b1010, "cmp",
1210 BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>;
1211 defm CMNnz : AI1_cmp_irs<0b1011, "cmn",
1212 BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>;
1214 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1215 (CMNri GPR:$src, so_imm_neg:$imm)>;
1217 def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm),
1218 (CMNri GPR:$src, so_imm_neg:$imm)>;
1221 // Conditional moves
1222 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1223 // a two-value operand where a dag node expects two operands. :(
1224 def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
1225 "mov", " $dst, $true",
1226 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1227 RegConstraint<"$false = $dst">, UnaryDP;
1229 def MOVCCs : AI1<0b1101, (outs GPR:$dst),
1230 (ins GPR:$false, so_reg:$true), DPSoRegFrm,
1231 "mov", " $dst, $true",
1232 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
1233 RegConstraint<"$false = $dst">, UnaryDP;
1235 def MOVCCi : AI1<0b1101, (outs GPR:$dst),
1236 (ins GPR:$false, so_imm:$true), DPFrm,
1237 "mov", " $dst, $true",
1238 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1239 RegConstraint<"$false = $dst">, UnaryDP;
1242 // LEApcrel - Load a pc-relative address into a register without offending the
1244 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p), Pseudo,
1245 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
1246 "${:private}PCRELL${:uid}+8))\n"),
1247 !strconcat("${:private}PCRELL${:uid}:\n\t",
1248 "add$p $dst, pc, #PCRELV${:uid}")),
1251 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, i32imm:$id, pred:$p),
1253 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
1254 "${:private}PCRELL${:uid}+8))\n"),
1255 !strconcat("${:private}PCRELL${:uid}:\n\t",
1256 "add$p $dst, pc, #PCRELV${:uid}")),
1259 //===----------------------------------------------------------------------===//
1263 // __aeabi_read_tp preserves the registers r1-r3.
1265 Defs = [R0, R12, LR, CPSR] in {
1266 def TPsoft : ABXI<0b1011, (outs), (ins),
1267 "bl __aeabi_read_tp",
1268 [(set R0, ARMthread_pointer)]>;
1271 //===----------------------------------------------------------------------===//
1272 // SJLJ Exception handling intrinsics
1273 // eh_sjlj_setjmp() is a three instruction sequence to store the return
1274 // address and save #0 in R0 for the non-longjmp case.
1275 // Since by its nature we may be coming from some other function to get
1276 // here, and we're using the stack frame for the containing function to
1277 // save/restore registers, we can't keep anything live in regs across
1278 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
1279 // when we get here from a longjmp(). We force everthing out of registers
1280 // except for our own input by listing the relevant registers in Defs. By
1281 // doing so, we also cause the prologue/epilogue code to actively preserve
1282 // all of the callee-saved resgisters, which is exactly what we want.
1284 [ R0, R1, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR,
1285 D0, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15 ] in {
1286 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src),
1287 AddrModeNone, SizeSpecial, IndexModeNone, Pseudo,
1288 "add r0, pc, #4\n\t"
1289 "str r0, [$src, #+4]\n\t"
1290 "mov r0, #0 @ eh_setjmp", "",
1291 [(set R0, (ARMeh_sjlj_setjmp GPR:$src))]>;
1294 //===----------------------------------------------------------------------===//
1295 // Non-Instruction Patterns
1298 // ConstantPool, GlobalAddress, and JumpTable
1299 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>;
1300 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
1301 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1302 (LEApcrelJT tjumptable:$dst, imm:$id)>;
1304 // Large immediate handling.
1306 // Two piece so_imms.
1307 let isReMaterializable = 1 in
1308 def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src), Pseudo,
1309 "mov", " $dst, $src",
1310 [(set GPR:$dst, so_imm2part:$src)]>;
1312 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
1313 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1314 (so_imm2part_2 imm:$RHS))>;
1315 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
1316 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1317 (so_imm2part_2 imm:$RHS))>;
1319 // TODO: add,sub,and, 3-instr forms?
1323 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
1325 // zextload i1 -> zextload i8
1326 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1328 // extload -> zextload
1329 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1330 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1331 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
1333 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
1334 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
1337 def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra (shl GPR:$b, 16), 16)),
1338 (SMULBB GPR:$a, GPR:$b)>;
1339 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
1340 (SMULBB GPR:$a, GPR:$b)>;
1341 def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16)),
1342 (SMULBT GPR:$a, GPR:$b)>;
1343 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, 16)),
1344 (SMULBT GPR:$a, GPR:$b)>;
1345 def : ARMV5TEPat<(mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16)),
1346 (SMULTB GPR:$a, GPR:$b)>;
1347 def : ARMV5TEPat<(mul (sra GPR:$a, 16), sext_16_node:$b),
1348 (SMULTB GPR:$a, GPR:$b)>;
1349 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16),
1350 (SMULWB GPR:$a, GPR:$b)>;
1351 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), 16),
1352 (SMULWB GPR:$a, GPR:$b)>;
1354 def : ARMV5TEPat<(add GPR:$acc,
1355 (mul (sra (shl GPR:$a, 16), 16),
1356 (sra (shl GPR:$b, 16), 16))),
1357 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1358 def : ARMV5TEPat<(add GPR:$acc,
1359 (mul sext_16_node:$a, sext_16_node:$b)),
1360 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1361 def : ARMV5TEPat<(add GPR:$acc,
1362 (mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16))),
1363 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1364 def : ARMV5TEPat<(add GPR:$acc,
1365 (mul sext_16_node:$a, (sra GPR:$b, 16))),
1366 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1367 def : ARMV5TEPat<(add GPR:$acc,
1368 (mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16))),
1369 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1370 def : ARMV5TEPat<(add GPR:$acc,
1371 (mul (sra GPR:$a, 16), sext_16_node:$b)),
1372 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1373 def : ARMV5TEPat<(add GPR:$acc,
1374 (sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16)),
1375 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1376 def : ARMV5TEPat<(add GPR:$acc,
1377 (sra (mul GPR:$a, sext_16_node:$b), 16)),
1378 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1380 //===----------------------------------------------------------------------===//
1384 include "ARMInstrThumb.td"
1386 //===----------------------------------------------------------------------===//
1387 // Floating Point Support
1390 include "ARMInstrVFP.td"