1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
39 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
40 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
42 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
43 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
46 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
47 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
49 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
50 [SDNPHasChain, SDNPOutFlag]>;
51 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
52 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
54 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
55 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
56 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
57 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
58 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
59 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
61 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
62 [SDNPHasChain, SDNPOptInFlag]>;
64 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
66 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
69 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
70 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
72 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
75 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
78 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
79 [SDNPOutFlag,SDNPCommutative]>;
81 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
83 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
84 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
85 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
87 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
88 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", SDT_ARMEH_SJLJ_Setjmp>;
90 //===----------------------------------------------------------------------===//
91 // ARM Instruction Predicate Definitions.
93 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
94 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
95 def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
96 def HasV7 : Predicate<"Subtarget->hasV7Ops()">;
97 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">;
98 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">;
99 def HasNEON : Predicate<"Subtarget->hasNEON()">;
100 def IsThumb : Predicate<"Subtarget->isThumb()">;
101 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
102 def IsThumb2 : Predicate<"Subtarget->isThumb2()">;
103 def IsARM : Predicate<"!Subtarget->isThumb()">;
104 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
105 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
106 def CarryDefIsUnused : Predicate<"!N.getNode()->hasAnyUseOfValue(1)">;
107 def CarryDefIsUsed : Predicate<"N.getNode()->hasAnyUseOfValue(1)">;
109 //===----------------------------------------------------------------------===//
110 // ARM Flag Definitions.
112 class RegConstraint<string C> {
113 string Constraints = C;
116 //===----------------------------------------------------------------------===//
117 // ARM specific transformation functions and pattern fragments.
120 // so_imm_XFORM - Return a so_imm value packed into the format described for
122 def so_imm_XFORM : SDNodeXForm<imm, [{
123 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(N->getZExtValue()),
127 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
128 // so_imm_neg def below.
129 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
130 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(-(int)N->getZExtValue()),
134 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
135 // so_imm_not def below.
136 def so_imm_not_XFORM : SDNodeXForm<imm, [{
137 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(~(int)N->getZExtValue()),
141 // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
142 def rot_imm : PatLeaf<(i32 imm), [{
143 int32_t v = (int32_t)N->getZExtValue();
144 return v == 8 || v == 16 || v == 24;
147 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
148 def imm1_15 : PatLeaf<(i32 imm), [{
149 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
152 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
153 def imm16_31 : PatLeaf<(i32 imm), [{
154 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
159 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
160 }], so_imm_neg_XFORM>;
164 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
165 }], so_imm_not_XFORM>;
167 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
168 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
169 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
172 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
173 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
175 //===----------------------------------------------------------------------===//
176 // Operand Definitions.
180 def brtarget : Operand<OtherVT>;
182 // A list of registers separated by comma. Used by load/store multiple.
183 def reglist : Operand<i32> {
184 let PrintMethod = "printRegisterList";
187 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
188 def cpinst_operand : Operand<i32> {
189 let PrintMethod = "printCPInstOperand";
192 def jtblock_operand : Operand<i32> {
193 let PrintMethod = "printJTBlockOperand";
197 def pclabel : Operand<i32> {
198 let PrintMethod = "printPCLabel";
201 // shifter_operand operands: so_reg and so_imm.
202 def so_reg : Operand<i32>, // reg reg imm
203 ComplexPattern<i32, 3, "SelectShifterOperandReg",
204 [shl,srl,sra,rotr]> {
205 let PrintMethod = "printSORegOperand";
206 let MIOperandInfo = (ops GPR, GPR, i32imm);
209 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
210 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
211 // represented in the imm field in the same 12-bit form that they are encoded
212 // into so_imm instructions: the 8-bit immediate is the least significant bits
213 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
214 def so_imm : Operand<i32>,
216 [{ return ARM_AM::getSOImmVal(N->getZExtValue()) != -1; }],
218 let PrintMethod = "printSOImmOperand";
221 // Break so_imm's up into two pieces. This handles immediates with up to 16
222 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
223 // get the first/second pieces.
224 def so_imm2part : Operand<i32>,
226 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
228 let PrintMethod = "printSOImm2PartOperand";
231 def so_imm2part_1 : SDNodeXForm<imm, [{
232 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
233 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
236 def so_imm2part_2 : SDNodeXForm<imm, [{
237 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
238 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
242 // Define ARM specific addressing modes.
244 // addrmode2 := reg +/- reg shop imm
245 // addrmode2 := reg +/- imm12
247 def addrmode2 : Operand<i32>,
248 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
249 let PrintMethod = "printAddrMode2Operand";
250 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
253 def am2offset : Operand<i32>,
254 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
255 let PrintMethod = "printAddrMode2OffsetOperand";
256 let MIOperandInfo = (ops GPR, i32imm);
259 // addrmode3 := reg +/- reg
260 // addrmode3 := reg +/- imm8
262 def addrmode3 : Operand<i32>,
263 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
264 let PrintMethod = "printAddrMode3Operand";
265 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
268 def am3offset : Operand<i32>,
269 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
270 let PrintMethod = "printAddrMode3OffsetOperand";
271 let MIOperandInfo = (ops GPR, i32imm);
274 // addrmode4 := reg, <mode|W>
276 def addrmode4 : Operand<i32>,
277 ComplexPattern<i32, 2, "", []> {
278 let PrintMethod = "printAddrMode4Operand";
279 let MIOperandInfo = (ops GPR, i32imm);
282 // addrmode5 := reg +/- imm8*4
284 def addrmode5 : Operand<i32>,
285 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
286 let PrintMethod = "printAddrMode5Operand";
287 let MIOperandInfo = (ops GPR, i32imm);
290 // addrmode6 := reg with optional writeback
292 def addrmode6 : Operand<i32>,
293 ComplexPattern<i32, 3, "SelectAddrMode6", []> {
294 let PrintMethod = "printAddrMode6Operand";
295 let MIOperandInfo = (ops GPR:$addr, GPR:$upd, i32imm);
298 // addrmodepc := pc + reg
300 def addrmodepc : Operand<i32>,
301 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
302 let PrintMethod = "printAddrModePCOperand";
303 let MIOperandInfo = (ops GPR, i32imm);
306 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
307 // register whose default is 0 (no register).
308 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
309 (ops (i32 14), (i32 zero_reg))> {
310 let PrintMethod = "printPredicateOperand";
313 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
315 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
316 let PrintMethod = "printSBitModifierOperand";
319 //===----------------------------------------------------------------------===//
321 include "ARMInstrFormats.td"
323 //===----------------------------------------------------------------------===//
324 // Multiclass helpers...
327 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
328 /// binop that produces a value.
329 multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
330 bit Commutable = 0> {
331 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
332 opc, " $dst, $a, $b",
333 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
334 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
335 opc, " $dst, $a, $b",
336 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
337 let isCommutable = Commutable;
339 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
340 opc, " $dst, $a, $b",
341 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
344 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
345 /// instruction modifies the CSPR register.
346 let Defs = [CPSR] in {
347 multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
348 bit Commutable = 0> {
349 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
350 opc, "s $dst, $a, $b",
351 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
352 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
353 opc, "s $dst, $a, $b",
354 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
355 let isCommutable = Commutable;
357 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
358 opc, "s $dst, $a, $b",
359 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
363 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
364 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
365 /// a explicit result, only implicitly set CPSR.
366 let Defs = [CPSR] in {
367 multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode,
368 bit Commutable = 0> {
369 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm,
371 [(opnode GPR:$a, so_imm:$b)]>;
372 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm,
374 [(opnode GPR:$a, GPR:$b)]> {
375 let isCommutable = Commutable;
377 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
379 [(opnode GPR:$a, so_reg:$b)]>;
383 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
384 /// register and one whose operand is a register rotated by 8/16/24.
385 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
386 multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
387 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$Src),
389 [(set GPR:$dst, (opnode GPR:$Src))]>,
390 Requires<[IsARM, HasV6]> {
391 let Inst{19-16} = 0b1111;
393 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$Src, i32imm:$rot),
394 opc, " $dst, $Src, ror $rot",
395 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>,
396 Requires<[IsARM, HasV6]> {
397 let Inst{19-16} = 0b1111;
401 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
402 /// register and one whose operand is a register rotated by 8/16/24.
403 multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
404 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
405 opc, " $dst, $LHS, $RHS",
406 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
407 Requires<[IsARM, HasV6]>;
408 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
409 opc, " $dst, $LHS, $RHS, ror $rot",
410 [(set GPR:$dst, (opnode GPR:$LHS,
411 (rotr GPR:$RHS, rot_imm:$rot)))]>,
412 Requires<[IsARM, HasV6]>;
415 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
416 let Uses = [CPSR] in {
417 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
418 bit Commutable = 0> {
419 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
420 DPFrm, opc, " $dst, $a, $b",
421 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
422 Requires<[IsARM, CarryDefIsUnused]>;
423 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
424 DPFrm, opc, " $dst, $a, $b",
425 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
426 Requires<[IsARM, CarryDefIsUnused]> {
427 let isCommutable = Commutable;
429 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
430 DPSoRegFrm, opc, " $dst, $a, $b",
431 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
432 Requires<[IsARM, CarryDefIsUnused]>;
433 // Carry setting variants
434 def Sri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
435 DPFrm, !strconcat(opc, "s $dst, $a, $b"),
436 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
437 Requires<[IsARM, CarryDefIsUsed]> {
440 def Srr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
441 DPFrm, !strconcat(opc, "s $dst, $a, $b"),
442 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
443 Requires<[IsARM, CarryDefIsUsed]> {
446 def Srs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
447 DPSoRegFrm, !strconcat(opc, "s $dst, $a, $b"),
448 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
449 Requires<[IsARM, CarryDefIsUsed]> {
455 //===----------------------------------------------------------------------===//
457 //===----------------------------------------------------------------------===//
459 //===----------------------------------------------------------------------===//
460 // Miscellaneous Instructions.
463 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
464 /// the function. The first operand is the ID# for this instruction, the second
465 /// is the index into the MachineConstantPool that this is, the third is the
466 /// size in bytes of this constant pool entry.
467 let neverHasSideEffects = 1, isNotDuplicable = 1 in
468 def CONSTPOOL_ENTRY :
469 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
471 "${instid:label} ${cpidx:cpentry}", []>;
473 let Defs = [SP], Uses = [SP] in {
475 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p),
476 "@ ADJCALLSTACKUP $amt1",
477 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
479 def ADJCALLSTACKDOWN :
480 PseudoInst<(outs), (ins i32imm:$amt, pred:$p),
481 "@ ADJCALLSTACKDOWN $amt",
482 [(ARMcallseq_start timm:$amt)]>;
486 PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
487 ".loc $file, $line, $col",
488 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
491 // Address computation and loads and stores in PIC mode.
492 let isNotDuplicable = 1 in {
493 def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
494 Pseudo, "$cp:\n\tadd$p $dst, pc, $a",
495 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
497 let AddedComplexity = 10 in {
498 let canFoldAsLoad = 1 in
499 def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
500 Pseudo, "${addr:label}:\n\tldr$p $dst, $addr",
501 [(set GPR:$dst, (load addrmodepc:$addr))]>;
503 def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
504 Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr",
505 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
507 def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
508 Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr",
509 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
511 def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
512 Pseudo, "${addr:label}:\n\tldr${p}sh $dst, $addr",
513 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
515 def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
516 Pseudo, "${addr:label}:\n\tldr${p}sb $dst, $addr",
517 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
519 let AddedComplexity = 10 in {
520 def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
521 Pseudo, "${addr:label}:\n\tstr$p $src, $addr",
522 [(store GPR:$src, addrmodepc:$addr)]>;
524 def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
525 Pseudo, "${addr:label}:\n\tstr${p}h $src, $addr",
526 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
528 def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
529 Pseudo, "${addr:label}:\n\tstr${p}b $src, $addr",
530 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
532 } // isNotDuplicable = 1
535 // LEApcrel - Load a pc-relative address into a register without offending the
537 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p), Pseudo,
538 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
539 "${:private}PCRELL${:uid}+8))\n"),
540 !strconcat("${:private}PCRELL${:uid}:\n\t",
541 "add$p $dst, pc, #PCRELV${:uid}")),
544 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
545 (ins i32imm:$label, i32imm:$id, pred:$p),
547 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
548 "${:private}PCRELL${:uid}+8))\n"),
549 !strconcat("${:private}PCRELL${:uid}:\n\t",
550 "add$p $dst, pc, #PCRELV${:uid}")),
553 //===----------------------------------------------------------------------===//
554 // Control Flow Instructions.
557 let isReturn = 1, isTerminator = 1 in
558 def BX_RET : AI<(outs), (ins), BrMiscFrm, "bx", " lr", [(ARMretflag)]> {
559 let Inst{7-4} = 0b0001;
560 let Inst{19-8} = 0b111111111111;
561 let Inst{27-20} = 0b00010010;
564 // FIXME: remove when we have a way to marking a MI with these properties.
565 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
567 // FIXME: Should pc be an implicit operand like PICADD, etc?
568 let isReturn = 1, isTerminator = 1 in
569 def LDM_RET : AXI4ld<(outs),
570 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
571 LdStMulFrm, "ldm${p}${addr:submode} $addr, $dst1",
574 // On non-Darwin platforms R9 is callee-saved.
575 let isCall = 1, Itinerary = IIC_Br,
576 Defs = [R0, R1, R2, R3, R12, LR,
577 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
578 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
580 [(ARMcall tglobaladdr:$func)]>, Requires<[IsNotDarwin]>;
582 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
583 "bl", " ${func:call}",
584 [(ARMcall_pred tglobaladdr:$func)]>, Requires<[IsNotDarwin]>;
587 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
589 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsNotDarwin]> {
590 let Inst{7-4} = 0b0011;
591 let Inst{19-8} = 0b111111111111;
592 let Inst{27-20} = 0b00010010;
597 def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops),
598 "mov lr, pc\n\tbx $func",
599 [(ARMcall_nolink GPR:$func)]>, Requires<[IsNotDarwin]>;
603 // On Darwin R9 is call-clobbered.
604 let isCall = 1, Itinerary = IIC_Br,
605 Defs = [R0, R1, R2, R3, R9, R12, LR,
606 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
607 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
609 [(ARMcall tglobaladdr:$func)]>, Requires<[IsDarwin]>;
611 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
612 "bl", " ${func:call}",
613 [(ARMcall_pred tglobaladdr:$func)]>, Requires<[IsDarwin]>;
616 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
618 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
619 let Inst{7-4} = 0b0011;
620 let Inst{19-8} = 0b111111111111;
621 let Inst{27-20} = 0b00010010;
626 def BXr9 : ABXIx2<(outs), (ins GPR:$func, variable_ops),
627 "mov lr, pc\n\tbx $func",
628 [(ARMcall_nolink GPR:$func)]>, Requires<[IsDarwin]>;
632 let isBranch = 1, isTerminator = 1, Itinerary = IIC_Br in {
633 // B is "predicable" since it can be xformed into a Bcc.
634 let isBarrier = 1 in {
635 let isPredicable = 1 in
636 def B : ABXI<0b1010, (outs), (ins brtarget:$target), "b $target",
639 let isNotDuplicable = 1, isIndirectBranch = 1 in {
640 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
641 "mov pc, $target \n$jt",
642 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
643 let Inst{20} = 0; // S Bit
644 let Inst{24-21} = 0b1101;
645 let Inst{27-26} = {0,0};
647 def BR_JTm : JTI<(outs),
648 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
649 "ldr pc, $target \n$jt",
650 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
652 let Inst{20} = 1; // L bit
653 let Inst{21} = 0; // W bit
654 let Inst{22} = 0; // B bit
655 let Inst{24} = 1; // P bit
656 let Inst{27-26} = {0,1};
658 def BR_JTadd : JTI<(outs),
659 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
660 "add pc, $target, $idx \n$jt",
661 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
663 let Inst{20} = 0; // S bit
664 let Inst{24-21} = 0b0100;
665 let Inst{27-26} = {0,0};
667 } // isNotDuplicable = 1, isIndirectBranch = 1
670 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
671 // a two-value operand where a dag node expects two operands. :(
672 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
674 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
677 //===----------------------------------------------------------------------===//
678 // Load / store Instructions.
682 let canFoldAsLoad = 1 in
683 def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
684 "ldr", " $dst, $addr",
685 [(set GPR:$dst, (load addrmode2:$addr))]>;
687 // Special LDR for loads from non-pc-relative constpools.
688 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
689 def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
690 "ldr", " $dst, $addr", []>;
692 // Loads with zero extension
693 def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
694 "ldr", "h $dst, $addr",
695 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
697 def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
698 "ldr", "b $dst, $addr",
699 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
701 // Loads with sign extension
702 def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
703 "ldr", "sh $dst, $addr",
704 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
706 def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
707 "ldr", "sb $dst, $addr",
708 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
712 def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
713 "ldr", "d $dst1, $addr", []>, Requires<[IsARM, HasV5T]>;
716 def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
717 (ins addrmode2:$addr), LdFrm,
718 "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>;
720 def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
721 (ins GPR:$base, am2offset:$offset), LdFrm,
722 "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>;
724 def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
725 (ins addrmode3:$addr), LdMiscFrm,
726 "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>;
728 def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
729 (ins GPR:$base,am3offset:$offset), LdMiscFrm,
730 "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>;
732 def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
733 (ins addrmode2:$addr), LdFrm,
734 "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>;
736 def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
737 (ins GPR:$base,am2offset:$offset), LdFrm,
738 "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>;
740 def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
741 (ins addrmode3:$addr), LdMiscFrm,
742 "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>;
744 def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
745 (ins GPR:$base,am3offset:$offset), LdMiscFrm,
746 "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>;
748 def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
749 (ins addrmode3:$addr), LdMiscFrm,
750 "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>;
752 def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
753 (ins GPR:$base,am3offset:$offset), LdMiscFrm,
754 "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
758 def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm,
759 "str", " $src, $addr",
760 [(store GPR:$src, addrmode2:$addr)]>;
762 // Stores with truncate
763 def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm,
764 "str", "h $src, $addr",
765 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
767 def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm,
768 "str", "b $src, $addr",
769 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
773 def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),StMiscFrm,
774 "str", "d $src1, $addr", []>, Requires<[IsARM, HasV5T]>;
777 def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
778 (ins GPR:$src, GPR:$base, am2offset:$offset), StFrm,
779 "str", " $src, [$base, $offset]!", "$base = $base_wb",
781 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
783 def STR_POST : AI2stwpo<(outs GPR:$base_wb),
784 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
785 "str", " $src, [$base], $offset", "$base = $base_wb",
787 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
789 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
790 (ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm,
791 "str", "h $src, [$base, $offset]!", "$base = $base_wb",
793 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
795 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
796 (ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm,
797 "str", "h $src, [$base], $offset", "$base = $base_wb",
798 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
799 GPR:$base, am3offset:$offset))]>;
801 def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
802 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
803 "str", "b $src, [$base, $offset]!", "$base = $base_wb",
804 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
805 GPR:$base, am2offset:$offset))]>;
807 def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
808 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
809 "str", "b $src, [$base], $offset", "$base = $base_wb",
810 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
811 GPR:$base, am2offset:$offset))]>;
813 //===----------------------------------------------------------------------===//
814 // Load / store multiple Instructions.
817 // FIXME: $dst1 should be a def.
819 def LDM : AXI4ld<(outs),
820 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
821 LdStMulFrm, "ldm${p}${addr:submode} $addr, $dst1",
825 def STM : AXI4st<(outs),
826 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
827 LdStMulFrm, "stm${p}${addr:submode} $addr, $src1",
830 //===----------------------------------------------------------------------===//
831 // Move Instructions.
834 let neverHasSideEffects = 1 in
835 def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm,
836 "mov", " $dst, $src", []>, UnaryDP;
837 def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
838 "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP;
840 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
841 def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm,
842 "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP;
844 def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
845 "mov", " $dst, $src, rrx",
846 [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
848 // These aren't really mov instructions, but we have to define them this way
849 // due to flag operands.
851 let Defs = [CPSR] in {
852 def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
853 "mov", "s $dst, $src, lsr #1",
854 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP;
855 def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
856 "mov", "s $dst, $src, asr #1",
857 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP;
860 //===----------------------------------------------------------------------===//
861 // Extend Instructions.
866 defm SXTB : AI_unary_rrot<0b01101010,
867 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
868 defm SXTH : AI_unary_rrot<0b01101011,
869 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
871 defm SXTAB : AI_bin_rrot<0b01101010,
872 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
873 defm SXTAH : AI_bin_rrot<0b01101011,
874 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
876 // TODO: SXT(A){B|H}16
880 let AddedComplexity = 16 in {
881 defm UXTB : AI_unary_rrot<0b01101110,
882 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
883 defm UXTH : AI_unary_rrot<0b01101111,
884 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
885 defm UXTB16 : AI_unary_rrot<0b01101100,
886 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
888 def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
889 (UXTB16r_rot GPR:$Src, 24)>;
890 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
891 (UXTB16r_rot GPR:$Src, 8)>;
893 defm UXTAB : AI_bin_rrot<0b01101110, "uxtab",
894 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
895 defm UXTAH : AI_bin_rrot<0b01101111, "uxtah",
896 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
899 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
900 //defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
902 // TODO: UXT(A){B|H}16
904 //===----------------------------------------------------------------------===//
905 // Arithmetic Instructions.
908 defm ADD : AsI1_bin_irs<0b0100, "add",
909 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
910 defm SUB : AsI1_bin_irs<0b0010, "sub",
911 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
913 // ADD and SUB with 's' bit set.
914 defm ADDS : AI1_bin_s_irs<0b0100, "add",
915 BinOpFrag<(addc node:$LHS, node:$RHS)>>;
916 defm SUBS : AI1_bin_s_irs<0b0010, "sub",
917 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
919 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
920 BinOpFrag<(adde node:$LHS, node:$RHS)>, 1>;
921 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
922 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
924 // These don't define reg/reg forms, because they are handled above.
925 def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
926 "rsb", " $dst, $a, $b",
927 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>;
929 def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
930 "rsb", " $dst, $a, $b",
931 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>;
933 // RSB with 's' bit set.
934 let Defs = [CPSR] in {
935 def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
936 "rsb", "s $dst, $a, $b",
937 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>;
938 def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
939 "rsb", "s $dst, $a, $b",
940 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>;
943 let Uses = [CPSR] in {
944 def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
945 DPFrm, "rsc", " $dst, $a, $b",
946 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
947 Requires<[IsARM, CarryDefIsUnused]>;
948 def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
949 DPSoRegFrm, "rsc", " $dst, $a, $b",
950 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
951 Requires<[IsARM, CarryDefIsUnused]>;
954 // FIXME: Allow these to be predicated.
955 let Defs = [CPSR], Uses = [CPSR] in {
956 def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
957 DPFrm, "rscs $dst, $a, $b",
958 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
959 Requires<[IsARM, CarryDefIsUnused]>;
960 def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
961 DPSoRegFrm, "rscs $dst, $a, $b",
962 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
963 Requires<[IsARM, CarryDefIsUnused]>;
966 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
967 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
968 (SUBri GPR:$src, so_imm_neg:$imm)>;
970 //def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
971 // (SUBSri GPR:$src, so_imm_neg:$imm)>;
972 //def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
973 // (SBCri GPR:$src, so_imm_neg:$imm)>;
975 // Note: These are implemented in C++ code, because they have to generate
976 // ADD/SUBrs instructions, which use a complex pattern that a xform function
978 // (mul X, 2^n+1) -> (add (X << n), X)
979 // (mul X, 2^n-1) -> (rsb X, (X << n))
982 //===----------------------------------------------------------------------===//
983 // Bitwise Instructions.
986 defm AND : AsI1_bin_irs<0b0000, "and",
987 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
988 defm ORR : AsI1_bin_irs<0b1100, "orr",
989 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
990 defm EOR : AsI1_bin_irs<0b0001, "eor",
991 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
992 defm BIC : AsI1_bin_irs<0b1110, "bic",
993 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
995 def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm,
996 "mvn", " $dst, $src",
997 [(set GPR:$dst, (not GPR:$src))]>, UnaryDP;
998 def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
999 "mvn", " $dst, $src",
1000 [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP;
1001 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1002 def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
1003 "mvn", " $dst, $imm",
1004 [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP;
1006 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
1007 (BICri GPR:$src, so_imm_not:$imm)>;
1009 //===----------------------------------------------------------------------===//
1010 // Multiply Instructions.
1013 let isCommutable = 1 in
1014 def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1015 "mul", " $dst, $a, $b",
1016 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
1018 def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1019 "mla", " $dst, $a, $b, $c",
1020 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
1022 // Extra precision multiplies with low / high results
1023 let neverHasSideEffects = 1 in {
1024 let isCommutable = 1 in {
1025 def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst),
1026 (ins GPR:$a, GPR:$b),
1027 "smull", " $ldst, $hdst, $a, $b", []>;
1029 def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst),
1030 (ins GPR:$a, GPR:$b),
1031 "umull", " $ldst, $hdst, $a, $b", []>;
1034 // Multiply + accumulate
1035 def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst),
1036 (ins GPR:$a, GPR:$b),
1037 "smlal", " $ldst, $hdst, $a, $b", []>;
1039 def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst),
1040 (ins GPR:$a, GPR:$b),
1041 "umlal", " $ldst, $hdst, $a, $b", []>;
1043 def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst),
1044 (ins GPR:$a, GPR:$b),
1045 "umaal", " $ldst, $hdst, $a, $b", []>,
1046 Requires<[IsARM, HasV6]>;
1047 } // neverHasSideEffects
1049 // Most significant word multiply
1050 def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1051 "smmul", " $dst, $a, $b",
1052 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
1053 Requires<[IsARM, HasV6]> {
1054 let Inst{7-4} = 0b0001;
1055 let Inst{15-12} = 0b1111;
1058 def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1059 "smmla", " $dst, $a, $b, $c",
1060 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
1061 Requires<[IsARM, HasV6]> {
1062 let Inst{7-4} = 0b0001;
1066 def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1067 "smmls", " $dst, $a, $b, $c",
1068 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
1069 Requires<[IsARM, HasV6]> {
1070 let Inst{7-4} = 0b1101;
1073 multiclass AI_smul<string opc, PatFrag opnode> {
1074 def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1075 !strconcat(opc, "bb"), " $dst, $a, $b",
1076 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1077 (sext_inreg GPR:$b, i16)))]>,
1078 Requires<[IsARM, HasV5TE]> {
1083 def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1084 !strconcat(opc, "bt"), " $dst, $a, $b",
1085 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1086 (sra GPR:$b, (i32 16))))]>,
1087 Requires<[IsARM, HasV5TE]> {
1092 def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1093 !strconcat(opc, "tb"), " $dst, $a, $b",
1094 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1095 (sext_inreg GPR:$b, i16)))]>,
1096 Requires<[IsARM, HasV5TE]> {
1101 def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1102 !strconcat(opc, "tt"), " $dst, $a, $b",
1103 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1104 (sra GPR:$b, (i32 16))))]>,
1105 Requires<[IsARM, HasV5TE]> {
1110 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1111 !strconcat(opc, "wb"), " $dst, $a, $b",
1112 [(set GPR:$dst, (sra (opnode GPR:$a,
1113 (sext_inreg GPR:$b, i16)), (i32 16)))]>,
1114 Requires<[IsARM, HasV5TE]> {
1119 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1120 !strconcat(opc, "wt"), " $dst, $a, $b",
1121 [(set GPR:$dst, (sra (opnode GPR:$a,
1122 (sra GPR:$b, (i32 16))), (i32 16)))]>,
1123 Requires<[IsARM, HasV5TE]> {
1130 multiclass AI_smla<string opc, PatFrag opnode> {
1131 def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1132 !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
1133 [(set GPR:$dst, (add GPR:$acc,
1134 (opnode (sext_inreg GPR:$a, i16),
1135 (sext_inreg GPR:$b, i16))))]>,
1136 Requires<[IsARM, HasV5TE]> {
1141 def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1142 !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
1143 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1144 (sra GPR:$b, (i32 16)))))]>,
1145 Requires<[IsARM, HasV5TE]> {
1150 def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1151 !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
1152 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1153 (sext_inreg GPR:$b, i16))))]>,
1154 Requires<[IsARM, HasV5TE]> {
1159 def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1160 !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
1161 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1162 (sra GPR:$b, (i32 16)))))]>,
1163 Requires<[IsARM, HasV5TE]> {
1168 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1169 !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
1170 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1171 (sext_inreg GPR:$b, i16)), (i32 16))))]>,
1172 Requires<[IsARM, HasV5TE]> {
1177 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1178 !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
1179 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1180 (sra GPR:$b, (i32 16))), (i32 16))))]>,
1181 Requires<[IsARM, HasV5TE]> {
1187 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1188 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1190 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
1191 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1193 //===----------------------------------------------------------------------===//
1194 // Misc. Arithmetic Instructions.
1197 def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src),
1198 "clz", " $dst, $src",
1199 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> {
1200 let Inst{7-4} = 0b0001;
1201 let Inst{11-8} = 0b1111;
1202 let Inst{19-16} = 0b1111;
1205 def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src),
1206 "rev", " $dst, $src",
1207 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> {
1208 let Inst{7-4} = 0b0011;
1209 let Inst{11-8} = 0b1111;
1210 let Inst{19-16} = 0b1111;
1213 def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src),
1214 "rev16", " $dst, $src",
1216 (or (and (srl GPR:$src, (i32 8)), 0xFF),
1217 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
1218 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
1219 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>,
1220 Requires<[IsARM, HasV6]> {
1221 let Inst{7-4} = 0b1011;
1222 let Inst{11-8} = 0b1111;
1223 let Inst{19-16} = 0b1111;
1226 def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src),
1227 "revsh", " $dst, $src",
1230 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
1231 (shl GPR:$src, (i32 8))), i16))]>,
1232 Requires<[IsARM, HasV6]> {
1233 let Inst{7-4} = 0b1011;
1234 let Inst{11-8} = 0b1111;
1235 let Inst{19-16} = 0b1111;
1238 def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst),
1239 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1240 "pkhbt", " $dst, $src1, $src2, LSL $shamt",
1241 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1242 (and (shl GPR:$src2, (i32 imm:$shamt)),
1244 Requires<[IsARM, HasV6]> {
1245 let Inst{6-4} = 0b001;
1248 // Alternate cases for PKHBT where identities eliminate some nodes.
1249 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1250 (PKHBT GPR:$src1, GPR:$src2, 0)>;
1251 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1252 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1255 def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst),
1256 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1257 "pkhtb", " $dst, $src1, $src2, ASR $shamt",
1258 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1259 (and (sra GPR:$src2, imm16_31:$shamt),
1260 0xFFFF)))]>, Requires<[IsARM, HasV6]> {
1261 let Inst{6-4} = 0b101;
1264 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
1265 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1266 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
1267 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1268 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1269 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1270 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1272 //===----------------------------------------------------------------------===//
1273 // Comparison Instructions...
1276 defm CMP : AI1_cmp_irs<0b1010, "cmp",
1277 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1278 defm CMN : AI1_cmp_irs<0b1011, "cmn",
1279 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1281 // Note that TST/TEQ don't set all the same flags that CMP does!
1282 defm TST : AI1_cmp_irs<0b1000, "tst",
1283 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>, 1>;
1284 defm TEQ : AI1_cmp_irs<0b1001, "teq",
1285 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>, 1>;
1287 defm CMPz : AI1_cmp_irs<0b1010, "cmp",
1288 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
1289 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
1290 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
1292 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1293 (CMNri GPR:$src, so_imm_neg:$imm)>;
1295 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
1296 (CMNri GPR:$src, so_imm_neg:$imm)>;
1299 // Conditional moves
1300 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1301 // a two-value operand where a dag node expects two operands. :(
1302 def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
1303 "mov", " $dst, $true",
1304 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1305 RegConstraint<"$false = $dst">, UnaryDP;
1307 def MOVCCs : AI1<0b1101, (outs GPR:$dst),
1308 (ins GPR:$false, so_reg:$true), DPSoRegFrm,
1309 "mov", " $dst, $true",
1310 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
1311 RegConstraint<"$false = $dst">, UnaryDP;
1313 def MOVCCi : AI1<0b1101, (outs GPR:$dst),
1314 (ins GPR:$false, so_imm:$true), DPFrm,
1315 "mov", " $dst, $true",
1316 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1317 RegConstraint<"$false = $dst">, UnaryDP;
1320 //===----------------------------------------------------------------------===//
1324 // __aeabi_read_tp preserves the registers r1-r3.
1326 Defs = [R0, R12, LR, CPSR] in {
1327 def TPsoft : ABXI<0b1011, (outs), (ins),
1328 "bl __aeabi_read_tp",
1329 [(set R0, ARMthread_pointer)]>;
1332 //===----------------------------------------------------------------------===//
1333 // SJLJ Exception handling intrinsics
1334 // eh_sjlj_setjmp() is a three instruction sequence to store the return
1335 // address and save #0 in R0 for the non-longjmp case.
1336 // Since by its nature we may be coming from some other function to get
1337 // here, and we're using the stack frame for the containing function to
1338 // save/restore registers, we can't keep anything live in regs across
1339 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
1340 // when we get here from a longjmp(). We force everthing out of registers
1341 // except for our own input by listing the relevant registers in Defs. By
1342 // doing so, we also cause the prologue/epilogue code to actively preserve
1343 // all of the callee-saved resgisters, which is exactly what we want.
1345 [ R0, R1, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR,
1346 D0, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15 ] in {
1347 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src),
1348 AddrModeNone, SizeSpecial, IndexModeNone, Pseudo,
1349 "add r0, pc, #4\n\t"
1350 "str r0, [$src, #+4]\n\t"
1351 "mov r0, #0 @ eh_setjmp", "",
1352 [(set R0, (ARMeh_sjlj_setjmp GPR:$src))]>;
1355 //===----------------------------------------------------------------------===//
1356 // Non-Instruction Patterns
1359 // ConstantPool, GlobalAddress, and JumpTable
1360 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>;
1361 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
1362 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1363 (LEApcrelJT tjumptable:$dst, imm:$id)>;
1365 // Large immediate handling.
1367 // Two piece so_imms.
1368 let isReMaterializable = 1 in
1369 def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src), Pseudo,
1370 "mov", " $dst, $src",
1371 [(set GPR:$dst, so_imm2part:$src)]>;
1373 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
1374 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1375 (so_imm2part_2 imm:$RHS))>;
1376 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
1377 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1378 (so_imm2part_2 imm:$RHS))>;
1380 // TODO: add,sub,and, 3-instr forms?
1384 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
1385 Requires<[IsNotDarwin]>;
1386 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
1387 Requires<[IsDarwin]>;
1389 // zextload i1 -> zextload i8
1390 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1392 // extload -> zextload
1393 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1394 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1395 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
1397 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
1398 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
1401 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1402 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1403 (SMULBB GPR:$a, GPR:$b)>;
1404 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
1405 (SMULBB GPR:$a, GPR:$b)>;
1406 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1407 (sra GPR:$b, (i32 16))),
1408 (SMULBT GPR:$a, GPR:$b)>;
1409 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
1410 (SMULBT GPR:$a, GPR:$b)>;
1411 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
1412 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1413 (SMULTB GPR:$a, GPR:$b)>;
1414 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
1415 (SMULTB GPR:$a, GPR:$b)>;
1416 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1418 (SMULWB GPR:$a, GPR:$b)>;
1419 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
1420 (SMULWB GPR:$a, GPR:$b)>;
1422 def : ARMV5TEPat<(add GPR:$acc,
1423 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1424 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1425 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1426 def : ARMV5TEPat<(add GPR:$acc,
1427 (mul sext_16_node:$a, sext_16_node:$b)),
1428 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1429 def : ARMV5TEPat<(add GPR:$acc,
1430 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1431 (sra GPR:$b, (i32 16)))),
1432 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1433 def : ARMV5TEPat<(add GPR:$acc,
1434 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
1435 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1436 def : ARMV5TEPat<(add GPR:$acc,
1437 (mul (sra GPR:$a, (i32 16)),
1438 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1439 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1440 def : ARMV5TEPat<(add GPR:$acc,
1441 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
1442 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1443 def : ARMV5TEPat<(add GPR:$acc,
1444 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1446 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1447 def : ARMV5TEPat<(add GPR:$acc,
1448 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
1449 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1451 //===----------------------------------------------------------------------===//
1455 include "ARMInstrThumb.td"
1457 //===----------------------------------------------------------------------===//
1461 include "ARMInstrThumb2.td"
1463 //===----------------------------------------------------------------------===//
1464 // Floating Point Support
1467 include "ARMInstrVFP.td"
1469 //===----------------------------------------------------------------------===//
1470 // Advanced SIMD (NEON) Support
1473 include "ARMInstrNEON.td"