1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
67 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
68 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
72 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
73 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
74 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
76 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
77 [SDNPHasChain, SDNPOutGlue]>;
78 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
79 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
81 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
82 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
84 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
85 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
87 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
88 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
91 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
92 [SDNPHasChain, SDNPOptInGlue]>;
94 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
97 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
98 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
100 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
102 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
105 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
108 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
111 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
112 [SDNPOutGlue, SDNPCommutative]>;
114 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
116 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
117 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
118 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
120 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
121 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
122 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
123 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
124 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
125 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
126 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
129 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
131 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
133 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDTPrefetch,
134 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
136 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
138 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
139 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
142 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
144 //===----------------------------------------------------------------------===//
145 // ARM Instruction Predicate Definitions.
147 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
148 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
149 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
150 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
151 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
152 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
153 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
154 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
155 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
156 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
157 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
158 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
159 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
160 def HasFP16 : Predicate<"Subtarget->hasFP16()">, AssemblerPredicate;
161 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
162 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
164 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
166 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
168 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
169 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
170 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
171 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
172 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
173 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
174 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
175 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
177 // FIXME: Eventually this will be just "hasV6T2Ops".
178 def UseMovt : Predicate<"Subtarget->useMovt()">;
179 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
180 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
182 //===----------------------------------------------------------------------===//
183 // ARM Flag Definitions.
185 class RegConstraint<string C> {
186 string Constraints = C;
189 //===----------------------------------------------------------------------===//
190 // ARM specific transformation functions and pattern fragments.
193 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
194 // so_imm_neg def below.
195 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
196 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
199 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
200 // so_imm_not def below.
201 def so_imm_not_XFORM : SDNodeXForm<imm, [{
202 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
205 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
206 def imm1_15 : PatLeaf<(i32 imm), [{
207 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
210 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
211 def imm16_31 : PatLeaf<(i32 imm), [{
212 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
217 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
218 }], so_imm_neg_XFORM>;
222 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
223 }], so_imm_not_XFORM>;
225 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
226 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
227 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
230 /// Split a 32-bit immediate into two 16 bit parts.
231 def hi16 : SDNodeXForm<imm, [{
232 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
235 def lo16AllZero : PatLeaf<(i32 imm), [{
236 // Returns true if all low 16-bits are 0.
237 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
240 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
242 def imm0_65535 : PatLeaf<(i32 imm), [{
243 return (uint32_t)N->getZExtValue() < 65536;
246 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
247 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
249 /// adde and sube predicates - True based on whether the carry flag output
250 /// will be needed or not.
251 def adde_dead_carry :
252 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
253 [{return !N->hasAnyUseOfValue(1);}]>;
254 def sube_dead_carry :
255 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
256 [{return !N->hasAnyUseOfValue(1);}]>;
257 def adde_live_carry :
258 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
259 [{return N->hasAnyUseOfValue(1);}]>;
260 def sube_live_carry :
261 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
262 [{return N->hasAnyUseOfValue(1);}]>;
264 // An 'and' node with a single use.
265 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
266 return N->hasOneUse();
269 // An 'xor' node with a single use.
270 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
271 return N->hasOneUse();
274 // An 'fmul' node with a single use.
275 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
276 return N->hasOneUse();
279 // An 'fadd' node which checks for single non-hazardous use.
280 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
281 return hasNoVMLxHazardUse(N);
284 // An 'fsub' node which checks for single non-hazardous use.
285 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
286 return hasNoVMLxHazardUse(N);
289 //===----------------------------------------------------------------------===//
290 // Operand Definitions.
294 // FIXME: rename brtarget to t2_brtarget
295 def brtarget : Operand<OtherVT> {
296 let EncoderMethod = "getBranchTargetOpValue";
299 // FIXME: get rid of this one?
300 def uncondbrtarget : Operand<OtherVT> {
301 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
304 // Branch target for ARM. Handles conditional/unconditional
305 def br_target : Operand<OtherVT> {
306 let EncoderMethod = "getARMBranchTargetOpValue";
310 // FIXME: rename bltarget to t2_bl_target?
311 def bltarget : Operand<i32> {
312 // Encoded the same as branch targets.
313 let EncoderMethod = "getBranchTargetOpValue";
316 // Call target for ARM. Handles conditional/unconditional
317 // FIXME: rename bl_target to t2_bltarget?
318 def bl_target : Operand<i32> {
319 // Encoded the same as branch targets.
320 let EncoderMethod = "getARMBranchTargetOpValue";
324 // A list of registers separated by comma. Used by load/store multiple.
325 def RegListAsmOperand : AsmOperandClass {
326 let Name = "RegList";
327 let SuperClasses = [];
330 def DPRRegListAsmOperand : AsmOperandClass {
331 let Name = "DPRRegList";
332 let SuperClasses = [];
335 def SPRRegListAsmOperand : AsmOperandClass {
336 let Name = "SPRRegList";
337 let SuperClasses = [];
340 def reglist : Operand<i32> {
341 let EncoderMethod = "getRegisterListOpValue";
342 let ParserMatchClass = RegListAsmOperand;
343 let PrintMethod = "printRegisterList";
346 def dpr_reglist : Operand<i32> {
347 let EncoderMethod = "getRegisterListOpValue";
348 let ParserMatchClass = DPRRegListAsmOperand;
349 let PrintMethod = "printRegisterList";
352 def spr_reglist : Operand<i32> {
353 let EncoderMethod = "getRegisterListOpValue";
354 let ParserMatchClass = SPRRegListAsmOperand;
355 let PrintMethod = "printRegisterList";
358 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
359 def cpinst_operand : Operand<i32> {
360 let PrintMethod = "printCPInstOperand";
364 def pclabel : Operand<i32> {
365 let PrintMethod = "printPCLabel";
368 // ADR instruction labels.
369 def adrlabel : Operand<i32> {
370 let EncoderMethod = "getAdrLabelOpValue";
373 def neon_vcvt_imm32 : Operand<i32> {
374 let EncoderMethod = "getNEONVcvtImm32OpValue";
377 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
378 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
379 int32_t v = (int32_t)N->getZExtValue();
380 return v == 8 || v == 16 || v == 24; }]> {
381 let EncoderMethod = "getRotImmOpValue";
384 // shift_imm: An integer that encodes a shift amount and the type of shift
385 // (currently either asr or lsl) using the same encoding used for the
386 // immediates in so_reg operands.
387 def shift_imm : Operand<i32> {
388 let PrintMethod = "printShiftImmOperand";
391 // shifter_operand operands: so_reg and so_imm.
392 def so_reg : Operand<i32>, // reg reg imm
393 ComplexPattern<i32, 3, "SelectShifterOperandReg",
394 [shl,srl,sra,rotr]> {
395 let EncoderMethod = "getSORegOpValue";
396 let PrintMethod = "printSORegOperand";
397 let MIOperandInfo = (ops GPR, GPR, i32imm);
399 def shift_so_reg : Operand<i32>, // reg reg imm
400 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
401 [shl,srl,sra,rotr]> {
402 let EncoderMethod = "getSORegOpValue";
403 let PrintMethod = "printSORegOperand";
404 let MIOperandInfo = (ops GPR, GPR, i32imm);
407 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
408 // 8-bit immediate rotated by an arbitrary number of bits.
409 def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> {
410 let EncoderMethod = "getSOImmOpValue";
411 let PrintMethod = "printSOImmOperand";
414 // Break so_imm's up into two pieces. This handles immediates with up to 16
415 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
416 // get the first/second pieces.
417 def so_imm2part : PatLeaf<(imm), [{
418 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
421 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
423 def arm_i32imm : PatLeaf<(imm), [{
424 if (Subtarget->hasV6T2Ops())
426 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
429 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
430 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
431 return (int32_t)N->getZExtValue() < 32;
434 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
435 def imm0_31_m1 : Operand<i32>, PatLeaf<(imm), [{
436 return (int32_t)N->getZExtValue() < 32;
438 let EncoderMethod = "getImmMinusOneOpValue";
441 // i32imm_hilo16 - For movt/movw - sets the MC Encoder method.
442 // The imm is split into imm{15-12}, imm{11-0}
444 def i32imm_hilo16 : Operand<i32> {
445 let EncoderMethod = "getHiLo16ImmOpValue";
448 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
450 def bf_inv_mask_imm : Operand<i32>,
452 return ARM::isBitFieldInvertedMask(N->getZExtValue());
454 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
455 let PrintMethod = "printBitfieldInvMaskImmOperand";
458 /// lsb_pos_imm - position of the lsb bit, used by BFI4p and t2BFI4p
459 def lsb_pos_imm : Operand<i32>, PatLeaf<(imm), [{
460 return isInt<5>(N->getSExtValue());
463 /// width_imm - number of bits to be copied, used by BFI4p and t2BFI4p
464 def width_imm : Operand<i32>, PatLeaf<(imm), [{
465 return N->getSExtValue() > 0 && N->getSExtValue() <= 32;
467 let EncoderMethod = "getMsbOpValue";
470 // Define ARM specific addressing modes.
473 // addrmode_imm12 := reg +/- imm12
475 def addrmode_imm12 : Operand<i32>,
476 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
477 // 12-bit immediate operand. Note that instructions using this encode
478 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
479 // immediate values are as normal.
481 let EncoderMethod = "getAddrModeImm12OpValue";
482 let PrintMethod = "printAddrModeImm12Operand";
483 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
485 // ldst_so_reg := reg +/- reg shop imm
487 def ldst_so_reg : Operand<i32>,
488 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
489 let EncoderMethod = "getLdStSORegOpValue";
490 // FIXME: Simplify the printer
491 let PrintMethod = "printAddrMode2Operand";
492 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
495 // addrmode2 := reg +/- imm12
496 // := reg +/- reg shop imm
498 def addrmode2 : Operand<i32>,
499 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
500 let EncoderMethod = "getAddrMode2OpValue";
501 let PrintMethod = "printAddrMode2Operand";
502 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
505 def am2offset : Operand<i32>,
506 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
507 [], [SDNPWantRoot]> {
508 let EncoderMethod = "getAddrMode2OffsetOpValue";
509 let PrintMethod = "printAddrMode2OffsetOperand";
510 let MIOperandInfo = (ops GPR, i32imm);
513 // addrmode3 := reg +/- reg
514 // addrmode3 := reg +/- imm8
516 def addrmode3 : Operand<i32>,
517 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
518 let EncoderMethod = "getAddrMode3OpValue";
519 let PrintMethod = "printAddrMode3Operand";
520 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
523 def am3offset : Operand<i32>,
524 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
525 [], [SDNPWantRoot]> {
526 let EncoderMethod = "getAddrMode3OffsetOpValue";
527 let PrintMethod = "printAddrMode3OffsetOperand";
528 let MIOperandInfo = (ops GPR, i32imm);
531 // ldstm_mode := {ia, ib, da, db}
533 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
534 let EncoderMethod = "getLdStmModeOpValue";
535 let PrintMethod = "printLdStmModeOperand";
538 def MemMode5AsmOperand : AsmOperandClass {
539 let Name = "MemMode5";
540 let SuperClasses = [];
543 // addrmode5 := reg +/- imm8*4
545 def addrmode5 : Operand<i32>,
546 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
547 let PrintMethod = "printAddrMode5Operand";
548 let MIOperandInfo = (ops GPR:$base, i32imm);
549 let ParserMatchClass = MemMode5AsmOperand;
550 let EncoderMethod = "getAddrMode5OpValue";
553 // addrmode6 := reg with optional alignment
555 def addrmode6 : Operand<i32>,
556 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
557 let PrintMethod = "printAddrMode6Operand";
558 let MIOperandInfo = (ops GPR:$addr, i32imm);
559 let EncoderMethod = "getAddrMode6AddressOpValue";
562 def am6offset : Operand<i32>,
563 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
564 [], [SDNPWantRoot]> {
565 let PrintMethod = "printAddrMode6OffsetOperand";
566 let MIOperandInfo = (ops GPR);
567 let EncoderMethod = "getAddrMode6OffsetOpValue";
570 // Special version of addrmode6 to handle alignment encoding for VLD-dup
571 // instructions, specifically VLD4-dup.
572 def addrmode6dup : Operand<i32>,
573 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
574 let PrintMethod = "printAddrMode6Operand";
575 let MIOperandInfo = (ops GPR:$addr, i32imm);
576 let EncoderMethod = "getAddrMode6DupAddressOpValue";
579 // addrmodepc := pc + reg
581 def addrmodepc : Operand<i32>,
582 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
583 let PrintMethod = "printAddrModePCOperand";
584 let MIOperandInfo = (ops GPR, i32imm);
587 def nohash_imm : Operand<i32> {
588 let PrintMethod = "printNoHashImmediate";
591 def CoprocNumAsmOperand : AsmOperandClass {
592 let Name = "CoprocNum";
593 let SuperClasses = [];
594 let ParserMethod = "tryParseCoprocNumOperand";
597 def CoprocRegAsmOperand : AsmOperandClass {
598 let Name = "CoprocReg";
599 let SuperClasses = [];
600 let ParserMethod = "tryParseCoprocRegOperand";
603 def p_imm : Operand<i32> {
604 let PrintMethod = "printPImmediate";
605 let ParserMatchClass = CoprocNumAsmOperand;
608 def c_imm : Operand<i32> {
609 let PrintMethod = "printCImmediate";
610 let ParserMatchClass = CoprocRegAsmOperand;
613 //===----------------------------------------------------------------------===//
615 include "ARMInstrFormats.td"
617 //===----------------------------------------------------------------------===//
618 // Multiclass helpers...
621 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
622 /// binop that produces a value.
623 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
624 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
625 PatFrag opnode, bit Commutable = 0> {
626 // The register-immediate version is re-materializable. This is useful
627 // in particular for taking the address of a local.
628 let isReMaterializable = 1 in {
629 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
630 iii, opc, "\t$Rd, $Rn, $imm",
631 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
636 let Inst{19-16} = Rn;
637 let Inst{15-12} = Rd;
638 let Inst{11-0} = imm;
641 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
642 iir, opc, "\t$Rd, $Rn, $Rm",
643 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
648 let isCommutable = Commutable;
649 let Inst{19-16} = Rn;
650 let Inst{15-12} = Rd;
651 let Inst{11-4} = 0b00000000;
654 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
655 iis, opc, "\t$Rd, $Rn, $shift",
656 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
661 let Inst{19-16} = Rn;
662 let Inst{15-12} = Rd;
663 let Inst{11-0} = shift;
667 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
668 /// instruction modifies the CPSR register.
669 let isCodeGenOnly = 1, Defs = [CPSR] in {
670 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
671 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
672 PatFrag opnode, bit Commutable = 0> {
673 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
674 iii, opc, "\t$Rd, $Rn, $imm",
675 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
681 let Inst{19-16} = Rn;
682 let Inst{15-12} = Rd;
683 let Inst{11-0} = imm;
685 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
686 iir, opc, "\t$Rd, $Rn, $Rm",
687 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
691 let isCommutable = Commutable;
694 let Inst{19-16} = Rn;
695 let Inst{15-12} = Rd;
696 let Inst{11-4} = 0b00000000;
699 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
700 iis, opc, "\t$Rd, $Rn, $shift",
701 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
707 let Inst{19-16} = Rn;
708 let Inst{15-12} = Rd;
709 let Inst{11-0} = shift;
714 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
715 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
716 /// a explicit result, only implicitly set CPSR.
717 let isCompare = 1, Defs = [CPSR] in {
718 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
719 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
720 PatFrag opnode, bit Commutable = 0> {
721 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
723 [(opnode GPR:$Rn, so_imm:$imm)]> {
728 let Inst{19-16} = Rn;
729 let Inst{15-12} = 0b0000;
730 let Inst{11-0} = imm;
732 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
734 [(opnode GPR:$Rn, GPR:$Rm)]> {
737 let isCommutable = Commutable;
740 let Inst{19-16} = Rn;
741 let Inst{15-12} = 0b0000;
742 let Inst{11-4} = 0b00000000;
745 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
746 opc, "\t$Rn, $shift",
747 [(opnode GPR:$Rn, so_reg:$shift)]> {
752 let Inst{19-16} = Rn;
753 let Inst{15-12} = 0b0000;
754 let Inst{11-0} = shift;
759 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
760 /// register and one whose operand is a register rotated by 8/16/24.
761 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
762 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
763 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
764 IIC_iEXTr, opc, "\t$Rd, $Rm",
765 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
766 Requires<[IsARM, HasV6]> {
769 let Inst{19-16} = 0b1111;
770 let Inst{15-12} = Rd;
771 let Inst{11-10} = 0b00;
774 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
775 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
776 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
777 Requires<[IsARM, HasV6]> {
781 let Inst{19-16} = 0b1111;
782 let Inst{15-12} = Rd;
783 let Inst{11-10} = rot;
788 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
789 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
790 IIC_iEXTr, opc, "\t$Rd, $Rm",
791 [/* For disassembly only; pattern left blank */]>,
792 Requires<[IsARM, HasV6]> {
793 let Inst{19-16} = 0b1111;
794 let Inst{11-10} = 0b00;
796 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
797 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
798 [/* For disassembly only; pattern left blank */]>,
799 Requires<[IsARM, HasV6]> {
801 let Inst{19-16} = 0b1111;
802 let Inst{11-10} = rot;
806 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
807 /// register and one whose operand is a register rotated by 8/16/24.
808 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
809 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
810 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
811 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
812 Requires<[IsARM, HasV6]> {
816 let Inst{19-16} = Rn;
817 let Inst{15-12} = Rd;
818 let Inst{11-10} = 0b00;
819 let Inst{9-4} = 0b000111;
822 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
824 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
825 [(set GPR:$Rd, (opnode GPR:$Rn,
826 (rotr GPR:$Rm, rot_imm:$rot)))]>,
827 Requires<[IsARM, HasV6]> {
832 let Inst{19-16} = Rn;
833 let Inst{15-12} = Rd;
834 let Inst{11-10} = rot;
835 let Inst{9-4} = 0b000111;
840 // For disassembly only.
841 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
842 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
843 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
844 [/* For disassembly only; pattern left blank */]>,
845 Requires<[IsARM, HasV6]> {
846 let Inst{11-10} = 0b00;
848 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
850 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
851 [/* For disassembly only; pattern left blank */]>,
852 Requires<[IsARM, HasV6]> {
855 let Inst{19-16} = Rn;
856 let Inst{11-10} = rot;
860 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
861 let Uses = [CPSR] in {
862 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
863 bit Commutable = 0> {
864 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
865 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
866 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
872 let Inst{15-12} = Rd;
873 let Inst{19-16} = Rn;
874 let Inst{11-0} = imm;
876 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
877 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
878 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
883 let Inst{11-4} = 0b00000000;
885 let isCommutable = Commutable;
887 let Inst{15-12} = Rd;
888 let Inst{19-16} = Rn;
890 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
891 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
892 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
898 let Inst{11-0} = shift;
899 let Inst{15-12} = Rd;
900 let Inst{19-16} = Rn;
903 // Carry setting variants
904 let isCodeGenOnly = 1, Defs = [CPSR] in {
905 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
906 bit Commutable = 0> {
907 def Sri : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
908 DPFrm, IIC_iALUi, !strconcat(opc, "\t$Rd, $Rn, $imm"),
909 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
914 let Inst{15-12} = Rd;
915 let Inst{19-16} = Rn;
916 let Inst{11-0} = imm;
920 def Srr : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
921 DPFrm, IIC_iALUr, !strconcat(opc, "\t$Rd, $Rn, $Rm"),
922 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
927 let Inst{11-4} = 0b00000000;
928 let isCommutable = Commutable;
930 let Inst{15-12} = Rd;
931 let Inst{19-16} = Rn;
935 def Srs : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
936 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$Rd, $Rn, $shift"),
937 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
942 let Inst{11-0} = shift;
943 let Inst{15-12} = Rd;
944 let Inst{19-16} = Rn;
952 let canFoldAsLoad = 1, isReMaterializable = 1 in {
953 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
954 InstrItinClass iir, PatFrag opnode> {
955 // Note: We use the complex addrmode_imm12 rather than just an input
956 // GPR and a constrained immediate so that we can use this to match
957 // frame index references and avoid matching constant pool references.
958 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
959 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
960 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
963 let Inst{23} = addr{12}; // U (add = ('U' == 1))
964 let Inst{19-16} = addr{16-13}; // Rn
965 let Inst{15-12} = Rt;
966 let Inst{11-0} = addr{11-0}; // imm12
968 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
969 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
970 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
973 let Inst{23} = shift{12}; // U (add = ('U' == 1))
974 let Inst{19-16} = shift{16-13}; // Rn
975 let Inst{15-12} = Rt;
976 let Inst{11-0} = shift{11-0};
981 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
982 InstrItinClass iir, PatFrag opnode> {
983 // Note: We use the complex addrmode_imm12 rather than just an input
984 // GPR and a constrained immediate so that we can use this to match
985 // frame index references and avoid matching constant pool references.
986 def i12 : AI2ldst<0b010, 0, isByte, (outs),
987 (ins GPR:$Rt, addrmode_imm12:$addr),
988 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
989 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
992 let Inst{23} = addr{12}; // U (add = ('U' == 1))
993 let Inst{19-16} = addr{16-13}; // Rn
994 let Inst{15-12} = Rt;
995 let Inst{11-0} = addr{11-0}; // imm12
997 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
998 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
999 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1002 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1003 let Inst{19-16} = shift{16-13}; // Rn
1004 let Inst{15-12} = Rt;
1005 let Inst{11-0} = shift{11-0};
1008 //===----------------------------------------------------------------------===//
1010 //===----------------------------------------------------------------------===//
1012 //===----------------------------------------------------------------------===//
1013 // Miscellaneous Instructions.
1016 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1017 /// the function. The first operand is the ID# for this instruction, the second
1018 /// is the index into the MachineConstantPool that this is, the third is the
1019 /// size in bytes of this constant pool entry.
1020 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1021 def CONSTPOOL_ENTRY :
1022 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1023 i32imm:$size), NoItinerary, []>;
1025 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1026 // from removing one half of the matched pairs. That breaks PEI, which assumes
1027 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1028 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1029 def ADJCALLSTACKUP :
1030 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1031 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1033 def ADJCALLSTACKDOWN :
1034 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1035 [(ARMcallseq_start timm:$amt)]>;
1038 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
1039 [/* For disassembly only; pattern left blank */]>,
1040 Requires<[IsARM, HasV6T2]> {
1041 let Inst{27-16} = 0b001100100000;
1042 let Inst{15-8} = 0b11110000;
1043 let Inst{7-0} = 0b00000000;
1046 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
1047 [/* For disassembly only; pattern left blank */]>,
1048 Requires<[IsARM, HasV6T2]> {
1049 let Inst{27-16} = 0b001100100000;
1050 let Inst{15-8} = 0b11110000;
1051 let Inst{7-0} = 0b00000001;
1054 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
1055 [/* For disassembly only; pattern left blank */]>,
1056 Requires<[IsARM, HasV6T2]> {
1057 let Inst{27-16} = 0b001100100000;
1058 let Inst{15-8} = 0b11110000;
1059 let Inst{7-0} = 0b00000010;
1062 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
1063 [/* For disassembly only; pattern left blank */]>,
1064 Requires<[IsARM, HasV6T2]> {
1065 let Inst{27-16} = 0b001100100000;
1066 let Inst{15-8} = 0b11110000;
1067 let Inst{7-0} = 0b00000011;
1070 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
1072 [/* For disassembly only; pattern left blank */]>,
1073 Requires<[IsARM, HasV6]> {
1078 let Inst{15-12} = Rd;
1079 let Inst{19-16} = Rn;
1080 let Inst{27-20} = 0b01101000;
1081 let Inst{7-4} = 0b1011;
1082 let Inst{11-8} = 0b1111;
1085 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1086 [/* For disassembly only; pattern left blank */]>,
1087 Requires<[IsARM, HasV6T2]> {
1088 let Inst{27-16} = 0b001100100000;
1089 let Inst{15-8} = 0b11110000;
1090 let Inst{7-0} = 0b00000100;
1093 // The i32imm operand $val can be used by a debugger to store more information
1094 // about the breakpoint.
1095 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
1096 [/* For disassembly only; pattern left blank */]>,
1099 let Inst{3-0} = val{3-0};
1100 let Inst{19-8} = val{15-4};
1101 let Inst{27-20} = 0b00010010;
1102 let Inst{7-4} = 0b0111;
1105 // Change Processor State is a system instruction -- for disassembly and
1107 // FIXME: Since the asm parser has currently no clean way to handle optional
1108 // operands, create 3 versions of the same instruction. Once there's a clean
1109 // framework to represent optional operands, change this behavior.
1110 class CPS<dag iops, string asm_ops>
1111 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1112 [/* For disassembly only; pattern left blank */]>, Requires<[IsARM]> {
1118 let Inst{31-28} = 0b1111;
1119 let Inst{27-20} = 0b00010000;
1120 let Inst{19-18} = imod;
1121 let Inst{17} = M; // Enabled if mode is set;
1123 let Inst{8-6} = iflags;
1125 let Inst{4-0} = mode;
1129 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
1130 "$imod\t$iflags, $mode">;
1131 let mode = 0, M = 0 in
1132 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1134 let imod = 0, iflags = 0, M = 1 in
1135 def CPS1p : CPS<(ins i32imm:$mode), "\t$mode">;
1137 // Preload signals the memory system of possible future data/instruction access.
1138 // These are for disassembly only.
1139 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1141 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1142 !strconcat(opc, "\t$addr"),
1143 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1146 let Inst{31-26} = 0b111101;
1147 let Inst{25} = 0; // 0 for immediate form
1148 let Inst{24} = data;
1149 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1150 let Inst{22} = read;
1151 let Inst{21-20} = 0b01;
1152 let Inst{19-16} = addr{16-13}; // Rn
1153 let Inst{15-12} = 0b1111;
1154 let Inst{11-0} = addr{11-0}; // imm12
1157 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1158 !strconcat(opc, "\t$shift"),
1159 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1161 let Inst{31-26} = 0b111101;
1162 let Inst{25} = 1; // 1 for register form
1163 let Inst{24} = data;
1164 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1165 let Inst{22} = read;
1166 let Inst{21-20} = 0b01;
1167 let Inst{19-16} = shift{16-13}; // Rn
1168 let Inst{15-12} = 0b1111;
1169 let Inst{11-0} = shift{11-0};
1173 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1174 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1175 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1177 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1179 [/* For disassembly only; pattern left blank */]>,
1182 let Inst{31-10} = 0b1111000100000001000000;
1187 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1188 [/* For disassembly only; pattern left blank */]>,
1189 Requires<[IsARM, HasV7]> {
1191 let Inst{27-4} = 0b001100100000111100001111;
1192 let Inst{3-0} = opt;
1195 // A5.4 Permanently UNDEFINED instructions.
1196 let isBarrier = 1, isTerminator = 1 in
1197 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1200 let Inst = 0xe7ffdefe;
1203 // Address computation and loads and stores in PIC mode.
1204 let isNotDuplicable = 1 in {
1205 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1206 Size4Bytes, IIC_iALUr,
1207 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1209 let AddedComplexity = 10 in {
1210 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1211 Size4Bytes, IIC_iLoad_r,
1212 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1214 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1215 Size4Bytes, IIC_iLoad_bh_r,
1216 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1218 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1219 Size4Bytes, IIC_iLoad_bh_r,
1220 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1222 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1223 Size4Bytes, IIC_iLoad_bh_r,
1224 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1226 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1227 Size4Bytes, IIC_iLoad_bh_r,
1228 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1230 let AddedComplexity = 10 in {
1231 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1232 Size4Bytes, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1234 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1235 Size4Bytes, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1236 addrmodepc:$addr)]>;
1238 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1239 Size4Bytes, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1241 } // isNotDuplicable = 1
1244 // LEApcrel - Load a pc-relative address into a register without offending the
1246 let neverHasSideEffects = 1, isReMaterializable = 1 in
1247 // The 'adr' mnemonic encodes differently if the label is before or after
1248 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1249 // know until then which form of the instruction will be used.
1250 def ADR : AI1<0, (outs GPR:$Rd), (ins adrlabel:$label),
1251 MiscFrm, IIC_iALUi, "adr", "\t$Rd, #$label", []> {
1254 let Inst{27-25} = 0b001;
1256 let Inst{19-16} = 0b1111;
1257 let Inst{15-12} = Rd;
1258 let Inst{11-0} = label;
1260 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1261 Size4Bytes, IIC_iALUi, []>;
1263 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1264 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1265 Size4Bytes, IIC_iALUi, []>;
1267 //===----------------------------------------------------------------------===//
1268 // Control Flow Instructions.
1271 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1273 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1274 "bx", "\tlr", [(ARMretflag)]>,
1275 Requires<[IsARM, HasV4T]> {
1276 let Inst{27-0} = 0b0001001011111111111100011110;
1280 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1281 "mov", "\tpc, lr", [(ARMretflag)]>,
1282 Requires<[IsARM, NoV4T]> {
1283 let Inst{27-0} = 0b0001101000001111000000001110;
1287 // Indirect branches
1288 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1290 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1291 [(brind GPR:$dst)]>,
1292 Requires<[IsARM, HasV4T]> {
1294 let Inst{31-4} = 0b1110000100101111111111110001;
1295 let Inst{3-0} = dst;
1299 // FIXME: We would really like to define this as a vanilla ARMPat like:
1300 // ARMPat<(brind GPR:$dst), (MOVr PC, GPR:$dst)>
1301 // With that, however, we can't set isBranch, isTerminator, etc..
1302 def MOVPCRX : ARMPseudoInst<(outs), (ins GPR:$dst),
1303 Size4Bytes, IIC_Br, [(brind GPR:$dst)]>,
1304 Requires<[IsARM, NoV4T]>;
1307 // All calls clobber the non-callee saved registers. SP is marked as
1308 // a use to prevent stack-pointer assignments that appear immediately
1309 // before calls from potentially appearing dead.
1311 // On non-Darwin platforms R9 is callee-saved.
1312 Defs = [R0, R1, R2, R3, R12, LR,
1313 D0, D1, D2, D3, D4, D5, D6, D7,
1314 D16, D17, D18, D19, D20, D21, D22, D23,
1315 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1317 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1318 IIC_Br, "bl\t$func",
1319 [(ARMcall tglobaladdr:$func)]>,
1320 Requires<[IsARM, IsNotDarwin]> {
1321 let Inst{31-28} = 0b1110;
1323 let Inst{23-0} = func;
1326 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1327 IIC_Br, "bl", "\t$func",
1328 [(ARMcall_pred tglobaladdr:$func)]>,
1329 Requires<[IsARM, IsNotDarwin]> {
1331 let Inst{23-0} = func;
1335 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1336 IIC_Br, "blx\t$func",
1337 [(ARMcall GPR:$func)]>,
1338 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1340 let Inst{31-4} = 0b1110000100101111111111110011;
1341 let Inst{3-0} = func;
1344 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1345 IIC_Br, "blx", "\t$func",
1346 [(ARMcall_pred GPR:$func)]>,
1347 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1349 let Inst{27-4} = 0b000100101111111111110011;
1350 let Inst{3-0} = func;
1354 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1355 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1356 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1357 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1360 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1361 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1362 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1366 // On Darwin R9 is call-clobbered.
1367 // R7 is marked as a use to prevent frame-pointer assignments from being
1368 // moved above / below calls.
1369 Defs = [R0, R1, R2, R3, R9, R12, LR,
1370 D0, D1, D2, D3, D4, D5, D6, D7,
1371 D16, D17, D18, D19, D20, D21, D22, D23,
1372 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1373 Uses = [R7, SP] in {
1374 def BLr9 : ABXI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1375 IIC_Br, "bl\t$func",
1376 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
1377 let Inst{31-28} = 0b1110;
1379 let Inst{23-0} = func;
1382 def BLr9_pred : ABI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1383 IIC_Br, "bl", "\t$func",
1384 [(ARMcall_pred tglobaladdr:$func)]>,
1385 Requires<[IsARM, IsDarwin]> {
1387 let Inst{23-0} = func;
1391 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1392 IIC_Br, "blx\t$func",
1393 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
1395 let Inst{31-4} = 0b1110000100101111111111110011;
1396 let Inst{3-0} = func;
1399 def BLXr9_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1400 IIC_Br, "blx", "\t$func",
1401 [(ARMcall_pred GPR:$func)]>,
1402 Requires<[IsARM, HasV5T, IsDarwin]> {
1404 let Inst{27-4} = 0b000100101111111111110011;
1405 let Inst{3-0} = func;
1409 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1410 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1411 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1412 Requires<[IsARM, HasV4T, IsDarwin]>;
1415 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1416 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1417 Requires<[IsARM, NoV4T, IsDarwin]>;
1422 // FIXME: These should probably be xformed into the non-TC versions of the
1423 // instructions as part of MC lowering.
1424 // FIXME: These seem to be used for both Thumb and ARM instruction selection.
1425 // Thumb should have its own version since the instruction is actually
1426 // different, even though the mnemonic is the same.
1427 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1429 let Defs = [R0, R1, R2, R3, R9, R12,
1430 D0, D1, D2, D3, D4, D5, D6, D7,
1431 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1432 D27, D28, D29, D30, D31, PC],
1434 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1435 IIC_Br, []>, Requires<[IsDarwin]>;
1437 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1438 IIC_Br, []>, Requires<[IsDarwin]>;
1440 def TAILJMPd : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1441 IIC_Br, "b\t$dst @ TAILCALL",
1442 []>, Requires<[IsARM, IsDarwin]>;
1444 def TAILJMPdt: ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1445 IIC_Br, "b.w\t$dst @ TAILCALL",
1446 []>, Requires<[IsThumb, IsDarwin]>;
1448 def TAILJMPr : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1449 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1450 []>, Requires<[IsDarwin]> {
1452 let Inst{31-4} = 0b1110000100101111111111110001;
1453 let Inst{3-0} = dst;
1457 // Non-Darwin versions (the difference is R9).
1458 let Defs = [R0, R1, R2, R3, R12,
1459 D0, D1, D2, D3, D4, D5, D6, D7,
1460 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1461 D27, D28, D29, D30, D31, PC],
1463 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1464 IIC_Br, []>, Requires<[IsNotDarwin]>;
1466 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1467 IIC_Br, []>, Requires<[IsNotDarwin]>;
1469 def TAILJMPdND : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1470 IIC_Br, "b\t$dst @ TAILCALL",
1471 []>, Requires<[IsARM, IsNotDarwin]>;
1473 def TAILJMPdNDt : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1474 IIC_Br, "b.w\t$dst @ TAILCALL",
1475 []>, Requires<[IsThumb, IsNotDarwin]>;
1477 def TAILJMPrND : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1478 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1479 []>, Requires<[IsNotDarwin]> {
1481 let Inst{31-4} = 0b1110000100101111111111110001;
1482 let Inst{3-0} = dst;
1487 let isBranch = 1, isTerminator = 1 in {
1488 // B is "predicable" since it can be xformed into a Bcc.
1489 let isBarrier = 1 in {
1490 let isPredicable = 1 in
1491 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
1492 "b\t$target", [(br bb:$target)]> {
1494 let Inst{31-28} = 0b1110;
1495 let Inst{23-0} = target;
1498 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1499 def BR_JTr : ARMPseudoInst<(outs),
1500 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1501 SizeSpecial, IIC_Br,
1502 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1503 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1504 // into i12 and rs suffixed versions.
1505 def BR_JTm : ARMPseudoInst<(outs),
1506 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1507 SizeSpecial, IIC_Br,
1508 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1510 def BR_JTadd : ARMPseudoInst<(outs),
1511 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1512 SizeSpecial, IIC_Br,
1513 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1515 } // isNotDuplicable = 1, isIndirectBranch = 1
1518 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1519 // a two-value operand where a dag node expects two operands. :(
1520 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1521 IIC_Br, "b", "\t$target",
1522 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1524 let Inst{23-0} = target;
1528 // Branch and Exchange Jazelle -- for disassembly only
1529 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1530 [/* For disassembly only; pattern left blank */]> {
1531 let Inst{23-20} = 0b0010;
1532 //let Inst{19-8} = 0xfff;
1533 let Inst{7-4} = 0b0010;
1536 // Secure Monitor Call is a system instruction -- for disassembly only
1537 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1538 [/* For disassembly only; pattern left blank */]> {
1540 let Inst{23-4} = 0b01100000000000000111;
1541 let Inst{3-0} = opt;
1544 // Supervisor Call (Software Interrupt) -- for disassembly only
1545 let isCall = 1, Uses = [SP] in {
1546 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1547 [/* For disassembly only; pattern left blank */]> {
1549 let Inst{23-0} = svc;
1553 // Store Return State is a system instruction -- for disassembly only
1554 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1555 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1556 NoItinerary, "srs${amode}\tsp!, $mode",
1557 [/* For disassembly only; pattern left blank */]> {
1558 let Inst{31-28} = 0b1111;
1559 let Inst{22-20} = 0b110; // W = 1
1562 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1563 NoItinerary, "srs${amode}\tsp, $mode",
1564 [/* For disassembly only; pattern left blank */]> {
1565 let Inst{31-28} = 0b1111;
1566 let Inst{22-20} = 0b100; // W = 0
1569 // Return From Exception is a system instruction -- for disassembly only
1570 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1571 NoItinerary, "rfe${amode}\t$base!",
1572 [/* For disassembly only; pattern left blank */]> {
1573 let Inst{31-28} = 0b1111;
1574 let Inst{22-20} = 0b011; // W = 1
1577 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1578 NoItinerary, "rfe${amode}\t$base",
1579 [/* For disassembly only; pattern left blank */]> {
1580 let Inst{31-28} = 0b1111;
1581 let Inst{22-20} = 0b001; // W = 0
1583 } // isCodeGenOnly = 1
1585 //===----------------------------------------------------------------------===//
1586 // Load / store Instructions.
1592 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1593 UnOpFrag<(load node:$Src)>>;
1594 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1595 UnOpFrag<(zextloadi8 node:$Src)>>;
1596 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1597 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1598 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1599 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1601 // Special LDR for loads from non-pc-relative constpools.
1602 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1603 isReMaterializable = 1 in
1604 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1605 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
1609 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1610 let Inst{19-16} = 0b1111;
1611 let Inst{15-12} = Rt;
1612 let Inst{11-0} = addr{11-0}; // imm12
1615 // Loads with zero extension
1616 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1617 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
1618 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
1620 // Loads with sign extension
1621 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1622 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
1623 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
1625 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1626 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
1627 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
1629 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
1630 isCodeGenOnly = 1 in { // $dst2 doesn't exist in asmstring?
1631 // FIXME: $dst2 isn't in the asm string as it's implied by $Rd (dst2 = Rd+1)
1632 // how to represent that such that tblgen is happy and we don't
1633 // mark this codegen only?
1635 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
1636 (ins addrmode3:$addr), LdMiscFrm,
1637 IIC_iLoad_d_r, "ldrd", "\t$Rd, $addr",
1638 []>, Requires<[IsARM, HasV5TE]>;
1642 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
1643 def _PRE : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1644 (ins addrmode2:$addr), IndexModePre, LdFrm, itin,
1645 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1647 // {13} 1 == Rm, 0 == imm12
1651 let Inst{25} = addr{13};
1652 let Inst{23} = addr{12};
1653 let Inst{19-16} = addr{17-14};
1654 let Inst{11-0} = addr{11-0};
1656 def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1657 (ins GPR:$Rn, am2offset:$offset),
1658 IndexModePost, LdFrm, itin,
1659 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1660 // {13} 1 == Rm, 0 == imm12
1665 let Inst{25} = offset{13};
1666 let Inst{23} = offset{12};
1667 let Inst{19-16} = Rn;
1668 let Inst{11-0} = offset{11-0};
1672 let mayLoad = 1, neverHasSideEffects = 1 in {
1673 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
1674 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
1677 multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
1678 def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1679 (ins addrmode3:$addr), IndexModePre,
1681 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1683 let Inst{23} = addr{8}; // U bit
1684 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1685 let Inst{19-16} = addr{12-9}; // Rn
1686 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1687 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1689 def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1690 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1692 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1695 let Inst{23} = offset{8}; // U bit
1696 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1697 let Inst{19-16} = Rn;
1698 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1699 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1703 let mayLoad = 1, neverHasSideEffects = 1 in {
1704 defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
1705 defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
1706 defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
1707 let hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1708 defm LDRD : AI3_ldridx<0b1101, 0, "ldrd", IIC_iLoad_d_ru>;
1709 } // mayLoad = 1, neverHasSideEffects = 1
1711 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1712 let mayLoad = 1, neverHasSideEffects = 1 in {
1713 def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$dst, GPR:$base_wb),
1714 (ins GPR:$base, am2offset:$offset), IndexModeNone,
1715 LdFrm, IIC_iLoad_ru,
1716 "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1717 let Inst{21} = 1; // overwrite
1719 def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1720 (ins GPR:$base, am2offset:$offset), IndexModeNone,
1721 LdFrm, IIC_iLoad_bh_ru,
1722 "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1723 let Inst{21} = 1; // overwrite
1725 def LDRSBT : AI3ldstidx<0b1101, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1726 (ins GPR:$base, am3offset:$offset), IndexModePost,
1727 LdMiscFrm, IIC_iLoad_bh_ru,
1728 "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1729 let Inst{21} = 1; // overwrite
1731 def LDRHT : AI3ldstidx<0b1011, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1732 (ins GPR:$base, am3offset:$offset), IndexModePost,
1733 LdMiscFrm, IIC_iLoad_bh_ru,
1734 "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1735 let Inst{21} = 1; // overwrite
1737 def LDRSHT : AI3ldstidx<0b1111, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1738 (ins GPR:$base, am3offset:$offset), IndexModePost,
1739 LdMiscFrm, IIC_iLoad_bh_ru,
1740 "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1741 let Inst{21} = 1; // overwrite
1747 // Stores with truncate
1748 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
1749 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
1750 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
1753 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
1754 isCodeGenOnly = 1 in // $src2 doesn't exist in asm string
1755 def STRD : AI3str<0b1111, (outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
1756 StMiscFrm, IIC_iStore_d_r,
1757 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
1760 def STR_PRE : AI2stridx<0, 1, (outs GPR:$Rn_wb),
1761 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1762 IndexModePre, StFrm, IIC_iStore_ru,
1763 "str", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1765 (pre_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1767 def STR_POST : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1768 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1769 IndexModePost, StFrm, IIC_iStore_ru,
1770 "str", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1772 (post_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1774 def STRB_PRE : AI2stridx<1, 1, (outs GPR:$Rn_wb),
1775 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1776 IndexModePre, StFrm, IIC_iStore_bh_ru,
1777 "strb", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1778 [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
1779 GPR:$Rn, am2offset:$offset))]>;
1780 def STRB_POST: AI2stridx<1, 0, (outs GPR:$Rn_wb),
1781 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1782 IndexModePost, StFrm, IIC_iStore_bh_ru,
1783 "strb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1784 [(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
1785 GPR:$Rn, am2offset:$offset))]>;
1787 def STRH_PRE : AI3stridx<0b1011, 0, 1, (outs GPR:$Rn_wb),
1788 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1789 IndexModePre, StMiscFrm, IIC_iStore_ru,
1790 "strh", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1792 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
1794 def STRH_POST: AI3stridx<0b1011, 0, 0, (outs GPR:$Rn_wb),
1795 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1796 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
1797 "strh", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1798 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
1799 GPR:$Rn, am3offset:$offset))]>;
1801 // For disassembly only
1802 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1803 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1804 StMiscFrm, IIC_iStore_d_ru,
1805 "strd", "\t$src1, $src2, [$base, $offset]!",
1806 "$base = $base_wb", []>;
1808 // For disassembly only
1809 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1810 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1811 StMiscFrm, IIC_iStore_d_ru,
1812 "strd", "\t$src1, $src2, [$base], $offset",
1813 "$base = $base_wb", []>;
1815 // STRT, STRBT, and STRHT are for disassembly only.
1817 def STRT : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1818 (ins GPR:$Rt, GPR:$Rn,am2offset:$offset),
1819 IndexModeNone, StFrm, IIC_iStore_ru,
1820 "strt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1821 [/* For disassembly only; pattern left blank */]> {
1822 let Inst{21} = 1; // overwrite
1825 def STRBT : AI2stridx<1, 0, (outs GPR:$Rn_wb),
1826 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1827 IndexModeNone, StFrm, IIC_iStore_bh_ru,
1828 "strbt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1829 [/* For disassembly only; pattern left blank */]> {
1830 let Inst{21} = 1; // overwrite
1833 def STRHT: AI3sthpo<(outs GPR:$base_wb),
1834 (ins GPR:$src, GPR:$base,am3offset:$offset),
1835 StMiscFrm, IIC_iStore_bh_ru,
1836 "strht", "\t$src, [$base], $offset", "$base = $base_wb",
1837 [/* For disassembly only; pattern left blank */]> {
1838 let Inst{21} = 1; // overwrite
1841 //===----------------------------------------------------------------------===//
1842 // Load / store multiple Instructions.
1845 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
1846 InstrItinClass itin, InstrItinClass itin_upd> {
1848 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1849 IndexModeNone, f, itin,
1850 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
1851 let Inst{24-23} = 0b01; // Increment After
1852 let Inst{21} = 0; // No writeback
1853 let Inst{20} = L_bit;
1856 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1857 IndexModeUpd, f, itin_upd,
1858 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1859 let Inst{24-23} = 0b01; // Increment After
1860 let Inst{21} = 1; // Writeback
1861 let Inst{20} = L_bit;
1864 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1865 IndexModeNone, f, itin,
1866 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
1867 let Inst{24-23} = 0b00; // Decrement After
1868 let Inst{21} = 0; // No writeback
1869 let Inst{20} = L_bit;
1872 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1873 IndexModeUpd, f, itin_upd,
1874 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1875 let Inst{24-23} = 0b00; // Decrement After
1876 let Inst{21} = 1; // Writeback
1877 let Inst{20} = L_bit;
1880 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1881 IndexModeNone, f, itin,
1882 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
1883 let Inst{24-23} = 0b10; // Decrement Before
1884 let Inst{21} = 0; // No writeback
1885 let Inst{20} = L_bit;
1888 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1889 IndexModeUpd, f, itin_upd,
1890 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1891 let Inst{24-23} = 0b10; // Decrement Before
1892 let Inst{21} = 1; // Writeback
1893 let Inst{20} = L_bit;
1896 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1897 IndexModeNone, f, itin,
1898 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
1899 let Inst{24-23} = 0b11; // Increment Before
1900 let Inst{21} = 0; // No writeback
1901 let Inst{20} = L_bit;
1904 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1905 IndexModeUpd, f, itin_upd,
1906 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1907 let Inst{24-23} = 0b11; // Increment Before
1908 let Inst{21} = 1; // Writeback
1909 let Inst{20} = L_bit;
1913 let neverHasSideEffects = 1 in {
1915 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1916 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
1918 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1919 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
1921 } // neverHasSideEffects
1923 // Load / Store Multiple Mnemonic Aliases
1924 def : MnemonicAlias<"ldm", "ldmia">;
1925 def : MnemonicAlias<"stm", "stmia">;
1927 // FIXME: remove when we have a way to marking a MI with these properties.
1928 // FIXME: Should pc be an implicit operand like PICADD, etc?
1929 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1930 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1931 def LDMIA_RET : ARMPseudoInst<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
1932 reglist:$regs, variable_ops),
1933 Size4Bytes, IIC_iLoad_mBr, []>,
1934 RegConstraint<"$Rn = $wb">;
1936 //===----------------------------------------------------------------------===//
1937 // Move Instructions.
1940 let neverHasSideEffects = 1 in
1941 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
1942 "mov", "\t$Rd, $Rm", []>, UnaryDP {
1946 let Inst{11-4} = 0b00000000;
1949 let Inst{15-12} = Rd;
1952 // A version for the smaller set of tail call registers.
1953 let neverHasSideEffects = 1 in
1954 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
1955 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
1959 let Inst{11-4} = 0b00000000;
1962 let Inst{15-12} = Rd;
1965 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
1966 DPSoRegFrm, IIC_iMOVsr,
1967 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
1971 let Inst{15-12} = Rd;
1972 let Inst{11-0} = src;
1976 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1977 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
1978 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
1982 let Inst{15-12} = Rd;
1983 let Inst{19-16} = 0b0000;
1984 let Inst{11-0} = imm;
1987 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1988 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins i32imm_hilo16:$imm),
1990 "movw", "\t$Rd, $imm",
1991 [(set GPR:$Rd, imm0_65535:$imm)]>,
1992 Requires<[IsARM, HasV6T2]>, UnaryDP {
1995 let Inst{15-12} = Rd;
1996 let Inst{11-0} = imm{11-0};
1997 let Inst{19-16} = imm{15-12};
2002 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2003 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2005 let Constraints = "$src = $Rd" in {
2006 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, i32imm_hilo16:$imm),
2008 "movt", "\t$Rd, $imm",
2010 (or (and GPR:$src, 0xffff),
2011 lo16AllZero:$imm))]>, UnaryDP,
2012 Requires<[IsARM, HasV6T2]> {
2015 let Inst{15-12} = Rd;
2016 let Inst{11-0} = imm{11-0};
2017 let Inst{19-16} = imm{15-12};
2022 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2023 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2027 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2028 Requires<[IsARM, HasV6T2]>;
2030 let Uses = [CPSR] in
2031 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2032 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2035 // These aren't really mov instructions, but we have to define them this way
2036 // due to flag operands.
2038 let Defs = [CPSR] in {
2039 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2040 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2042 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2043 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2047 //===----------------------------------------------------------------------===//
2048 // Extend Instructions.
2053 defm SXTB : AI_ext_rrot<0b01101010,
2054 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2055 defm SXTH : AI_ext_rrot<0b01101011,
2056 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2058 defm SXTAB : AI_exta_rrot<0b01101010,
2059 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2060 defm SXTAH : AI_exta_rrot<0b01101011,
2061 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2063 // For disassembly only
2064 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2066 // For disassembly only
2067 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2071 let AddedComplexity = 16 in {
2072 defm UXTB : AI_ext_rrot<0b01101110,
2073 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2074 defm UXTH : AI_ext_rrot<0b01101111,
2075 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2076 defm UXTB16 : AI_ext_rrot<0b01101100,
2077 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2079 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2080 // The transformation should probably be done as a combiner action
2081 // instead so we can include a check for masking back in the upper
2082 // eight bits of the source into the lower eight bits of the result.
2083 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2084 // (UXTB16r_rot GPR:$Src, 24)>;
2085 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2086 (UXTB16r_rot GPR:$Src, 8)>;
2088 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2089 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2090 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2091 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2094 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2095 // For disassembly only
2096 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2099 def SBFX : I<(outs GPR:$Rd),
2100 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2101 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2102 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2103 Requires<[IsARM, HasV6T2]> {
2108 let Inst{27-21} = 0b0111101;
2109 let Inst{6-4} = 0b101;
2110 let Inst{20-16} = width;
2111 let Inst{15-12} = Rd;
2112 let Inst{11-7} = lsb;
2116 def UBFX : I<(outs GPR:$Rd),
2117 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2118 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2119 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2120 Requires<[IsARM, HasV6T2]> {
2125 let Inst{27-21} = 0b0111111;
2126 let Inst{6-4} = 0b101;
2127 let Inst{20-16} = width;
2128 let Inst{15-12} = Rd;
2129 let Inst{11-7} = lsb;
2133 //===----------------------------------------------------------------------===//
2134 // Arithmetic Instructions.
2137 defm ADD : AsI1_bin_irs<0b0100, "add",
2138 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2139 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
2140 defm SUB : AsI1_bin_irs<0b0010, "sub",
2141 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2142 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
2144 // ADD and SUB with 's' bit set.
2145 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
2146 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2147 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
2148 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
2149 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2150 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
2152 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
2153 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
2154 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
2155 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
2157 // ADC and SUBC with 's' bit set.
2158 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
2159 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
2160 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
2161 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
2163 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2164 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
2165 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
2170 let Inst{15-12} = Rd;
2171 let Inst{19-16} = Rn;
2172 let Inst{11-0} = imm;
2175 // The reg/reg form is only defined for the disassembler; for codegen it is
2176 // equivalent to SUBrr.
2177 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2178 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
2179 [/* For disassembly only; pattern left blank */]> {
2183 let Inst{11-4} = 0b00000000;
2186 let Inst{15-12} = Rd;
2187 let Inst{19-16} = Rn;
2190 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2191 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2192 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
2197 let Inst{11-0} = shift;
2198 let Inst{15-12} = Rd;
2199 let Inst{19-16} = Rn;
2202 // RSB with 's' bit set.
2203 let isCodeGenOnly = 1, Defs = [CPSR] in {
2204 def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2205 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
2206 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
2212 let Inst{15-12} = Rd;
2213 let Inst{19-16} = Rn;
2214 let Inst{11-0} = imm;
2216 def RSBSrr : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2217 IIC_iALUr, "rsbs", "\t$Rd, $Rn, $Rm",
2218 [/* For disassembly only; pattern left blank */]> {
2222 let Inst{11-4} = 0b00000000;
2226 let Inst{15-12} = Rd;
2227 let Inst{19-16} = Rn;
2229 def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2230 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
2231 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
2237 let Inst{11-0} = shift;
2238 let Inst{15-12} = Rd;
2239 let Inst{19-16} = Rn;
2243 let Uses = [CPSR] in {
2244 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2245 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2246 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2252 let Inst{15-12} = Rd;
2253 let Inst{19-16} = Rn;
2254 let Inst{11-0} = imm;
2256 // The reg/reg form is only defined for the disassembler; for codegen it is
2257 // equivalent to SUBrr.
2258 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2259 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2260 [/* For disassembly only; pattern left blank */]> {
2264 let Inst{11-4} = 0b00000000;
2267 let Inst{15-12} = Rd;
2268 let Inst{19-16} = Rn;
2270 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2271 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2272 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2278 let Inst{11-0} = shift;
2279 let Inst{15-12} = Rd;
2280 let Inst{19-16} = Rn;
2284 // FIXME: Allow these to be predicated.
2285 let isCodeGenOnly = 1, Defs = [CPSR], Uses = [CPSR] in {
2286 def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2287 DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
2288 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2295 let Inst{15-12} = Rd;
2296 let Inst{19-16} = Rn;
2297 let Inst{11-0} = imm;
2299 def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2300 DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
2301 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2308 let Inst{11-0} = shift;
2309 let Inst{15-12} = Rd;
2310 let Inst{19-16} = Rn;
2314 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2315 // The assume-no-carry-in form uses the negation of the input since add/sub
2316 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2317 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2319 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2320 (SUBri GPR:$src, so_imm_neg:$imm)>;
2321 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2322 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2323 // The with-carry-in form matches bitwise not instead of the negation.
2324 // Effectively, the inverse interpretation of the carry flag already accounts
2325 // for part of the negation.
2326 def : ARMPat<(adde GPR:$src, so_imm_not:$imm),
2327 (SBCri GPR:$src, so_imm_not:$imm)>;
2329 // Note: These are implemented in C++ code, because they have to generate
2330 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2332 // (mul X, 2^n+1) -> (add (X << n), X)
2333 // (mul X, 2^n-1) -> (rsb X, (X << n))
2335 // ARM Arithmetic Instruction -- for disassembly only
2336 // GPR:$dst = GPR:$a op GPR:$b
2337 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2338 list<dag> pattern = [/* For disassembly only; pattern left blank */],
2339 dag iops = (ins GPR:$Rn, GPR:$Rm), string asm = "\t$Rd, $Rn, $Rm">
2340 : AI<(outs GPR:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
2344 let Inst{27-20} = op27_20;
2345 let Inst{11-4} = op11_4;
2346 let Inst{19-16} = Rn;
2347 let Inst{15-12} = Rd;
2351 // Saturating add/subtract -- for disassembly only
2353 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2354 [(set GPR:$Rd, (int_arm_qadd GPR:$Rm, GPR:$Rn))],
2355 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2356 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2357 [(set GPR:$Rd, (int_arm_qsub GPR:$Rm, GPR:$Rn))],
2358 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2359 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [], (ins GPR:$Rm, GPR:$Rn),
2361 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [], (ins GPR:$Rm, GPR:$Rn),
2364 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2365 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2366 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2367 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2368 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2369 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2370 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2371 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2372 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2373 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2374 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2375 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2377 // Signed/Unsigned add/subtract -- for disassembly only
2379 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2380 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2381 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2382 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2383 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2384 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2385 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2386 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2387 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2388 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2389 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2390 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2392 // Signed/Unsigned halving add/subtract -- for disassembly only
2394 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2395 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2396 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2397 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2398 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2399 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2400 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2401 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2402 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2403 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2404 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2405 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2407 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2409 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2410 MulFrm /* for convenience */, NoItinerary, "usad8",
2411 "\t$Rd, $Rn, $Rm", []>,
2412 Requires<[IsARM, HasV6]> {
2416 let Inst{27-20} = 0b01111000;
2417 let Inst{15-12} = 0b1111;
2418 let Inst{7-4} = 0b0001;
2419 let Inst{19-16} = Rd;
2420 let Inst{11-8} = Rm;
2423 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2424 MulFrm /* for convenience */, NoItinerary, "usada8",
2425 "\t$Rd, $Rn, $Rm, $Ra", []>,
2426 Requires<[IsARM, HasV6]> {
2431 let Inst{27-20} = 0b01111000;
2432 let Inst{7-4} = 0b0001;
2433 let Inst{19-16} = Rd;
2434 let Inst{15-12} = Ra;
2435 let Inst{11-8} = Rm;
2439 // Signed/Unsigned saturate -- for disassembly only
2441 def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2442 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2443 [/* For disassembly only; pattern left blank */]> {
2448 let Inst{27-21} = 0b0110101;
2449 let Inst{5-4} = 0b01;
2450 let Inst{20-16} = sat_imm;
2451 let Inst{15-12} = Rd;
2452 let Inst{11-7} = sh{7-3};
2453 let Inst{6} = sh{0};
2457 def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm,
2458 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2459 [/* For disassembly only; pattern left blank */]> {
2463 let Inst{27-20} = 0b01101010;
2464 let Inst{11-4} = 0b11110011;
2465 let Inst{15-12} = Rd;
2466 let Inst{19-16} = sat_imm;
2470 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2471 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2472 [/* For disassembly only; pattern left blank */]> {
2477 let Inst{27-21} = 0b0110111;
2478 let Inst{5-4} = 0b01;
2479 let Inst{15-12} = Rd;
2480 let Inst{11-7} = sh{7-3};
2481 let Inst{6} = sh{0};
2482 let Inst{20-16} = sat_imm;
2486 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2487 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2488 [/* For disassembly only; pattern left blank */]> {
2492 let Inst{27-20} = 0b01101110;
2493 let Inst{11-4} = 0b11110011;
2494 let Inst{15-12} = Rd;
2495 let Inst{19-16} = sat_imm;
2499 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2500 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2502 //===----------------------------------------------------------------------===//
2503 // Bitwise Instructions.
2506 defm AND : AsI1_bin_irs<0b0000, "and",
2507 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2508 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2509 defm ORR : AsI1_bin_irs<0b1100, "orr",
2510 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2511 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2512 defm EOR : AsI1_bin_irs<0b0001, "eor",
2513 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2514 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2515 defm BIC : AsI1_bin_irs<0b1110, "bic",
2516 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2517 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2519 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2520 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2521 "bfc", "\t$Rd, $imm", "$src = $Rd",
2522 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2523 Requires<[IsARM, HasV6T2]> {
2526 let Inst{27-21} = 0b0111110;
2527 let Inst{6-0} = 0b0011111;
2528 let Inst{15-12} = Rd;
2529 let Inst{11-7} = imm{4-0}; // lsb
2530 let Inst{20-16} = imm{9-5}; // width
2533 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2534 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2535 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2536 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2537 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2538 bf_inv_mask_imm:$imm))]>,
2539 Requires<[IsARM, HasV6T2]> {
2543 let Inst{27-21} = 0b0111110;
2544 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2545 let Inst{15-12} = Rd;
2546 let Inst{11-7} = imm{4-0}; // lsb
2547 let Inst{20-16} = imm{9-5}; // width
2551 // GNU as only supports this form of bfi (w/ 4 arguments)
2552 let isAsmParserOnly = 1 in
2553 def BFI4p : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn,
2554 lsb_pos_imm:$lsb, width_imm:$width),
2555 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2556 "bfi", "\t$Rd, $Rn, $lsb, $width", "$src = $Rd",
2557 []>, Requires<[IsARM, HasV6T2]> {
2562 let Inst{27-21} = 0b0111110;
2563 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2564 let Inst{15-12} = Rd;
2565 let Inst{11-7} = lsb;
2566 let Inst{20-16} = width; // Custom encoder => lsb+width-1
2570 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2571 "mvn", "\t$Rd, $Rm",
2572 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2576 let Inst{19-16} = 0b0000;
2577 let Inst{11-4} = 0b00000000;
2578 let Inst{15-12} = Rd;
2581 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2582 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2583 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2587 let Inst{19-16} = 0b0000;
2588 let Inst{15-12} = Rd;
2589 let Inst{11-0} = shift;
2591 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2592 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2593 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2594 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2598 let Inst{19-16} = 0b0000;
2599 let Inst{15-12} = Rd;
2600 let Inst{11-0} = imm;
2603 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2604 (BICri GPR:$src, so_imm_not:$imm)>;
2606 //===----------------------------------------------------------------------===//
2607 // Multiply Instructions.
2609 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2610 string opc, string asm, list<dag> pattern>
2611 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2615 let Inst{19-16} = Rd;
2616 let Inst{11-8} = Rm;
2619 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2620 string opc, string asm, list<dag> pattern>
2621 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2626 let Inst{19-16} = RdHi;
2627 let Inst{15-12} = RdLo;
2628 let Inst{11-8} = Rm;
2632 let isCommutable = 1 in {
2633 let Constraints = "@earlyclobber $Rd" in
2634 def MULv5: ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
2635 pred:$p, cc_out:$s),
2636 Size4Bytes, IIC_iMUL32,
2637 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2638 Requires<[IsARM, NoV6]>;
2640 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2641 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2642 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2643 Requires<[IsARM, HasV6]>;
2646 let Constraints = "@earlyclobber $Rd" in
2647 def MLAv5: ARMPseudoInst<(outs GPR:$Rd),
2648 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
2649 Size4Bytes, IIC_iMAC32,
2650 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2651 Requires<[IsARM, NoV6]> {
2653 let Inst{15-12} = Ra;
2655 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2656 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2657 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2658 Requires<[IsARM, HasV6]> {
2660 let Inst{15-12} = Ra;
2663 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2664 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
2665 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
2666 Requires<[IsARM, HasV6T2]> {
2671 let Inst{19-16} = Rd;
2672 let Inst{15-12} = Ra;
2673 let Inst{11-8} = Rm;
2677 // Extra precision multiplies with low / high results
2679 let neverHasSideEffects = 1 in {
2680 let isCommutable = 1 in {
2681 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2682 def SMULLv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2683 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2684 Size4Bytes, IIC_iMUL64, []>,
2685 Requires<[IsARM, NoV6]>;
2687 def UMULLv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2688 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2689 Size4Bytes, IIC_iMUL64, []>,
2690 Requires<[IsARM, NoV6]>;
2693 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2694 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2695 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2696 Requires<[IsARM, HasV6]>;
2698 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2699 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2700 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2701 Requires<[IsARM, HasV6]>;
2704 // Multiply + accumulate
2705 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2706 def SMLALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2707 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2708 Size4Bytes, IIC_iMAC64, []>,
2709 Requires<[IsARM, NoV6]>;
2710 def UMLALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2711 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2712 Size4Bytes, IIC_iMAC64, []>,
2713 Requires<[IsARM, NoV6]>;
2714 def UMAALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2715 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2716 Size4Bytes, IIC_iMAC64, []>,
2717 Requires<[IsARM, NoV6]>;
2721 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2722 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2723 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2724 Requires<[IsARM, HasV6]>;
2725 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2726 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2727 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2728 Requires<[IsARM, HasV6]>;
2730 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2731 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2732 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2733 Requires<[IsARM, HasV6]> {
2738 let Inst{19-16} = RdLo;
2739 let Inst{15-12} = RdHi;
2740 let Inst{11-8} = Rm;
2743 } // neverHasSideEffects
2745 // Most significant word multiply
2746 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2747 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2748 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2749 Requires<[IsARM, HasV6]> {
2750 let Inst{15-12} = 0b1111;
2753 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2754 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2755 [/* For disassembly only; pattern left blank */]>,
2756 Requires<[IsARM, HasV6]> {
2757 let Inst{15-12} = 0b1111;
2760 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2761 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2762 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2763 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2764 Requires<[IsARM, HasV6]>;
2766 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2767 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2768 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2769 [/* For disassembly only; pattern left blank */]>,
2770 Requires<[IsARM, HasV6]>;
2772 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2773 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2774 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2775 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2776 Requires<[IsARM, HasV6]>;
2778 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2779 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2780 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2781 [/* For disassembly only; pattern left blank */]>,
2782 Requires<[IsARM, HasV6]>;
2784 multiclass AI_smul<string opc, PatFrag opnode> {
2785 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2786 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2787 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2788 (sext_inreg GPR:$Rm, i16)))]>,
2789 Requires<[IsARM, HasV5TE]>;
2791 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2792 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2793 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2794 (sra GPR:$Rm, (i32 16))))]>,
2795 Requires<[IsARM, HasV5TE]>;
2797 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2798 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2799 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2800 (sext_inreg GPR:$Rm, i16)))]>,
2801 Requires<[IsARM, HasV5TE]>;
2803 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2804 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2805 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2806 (sra GPR:$Rm, (i32 16))))]>,
2807 Requires<[IsARM, HasV5TE]>;
2809 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2810 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2811 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2812 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2813 Requires<[IsARM, HasV5TE]>;
2815 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2816 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2817 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2818 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2819 Requires<[IsARM, HasV5TE]>;
2823 multiclass AI_smla<string opc, PatFrag opnode> {
2824 def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
2825 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2826 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2827 [(set GPR:$Rd, (add GPR:$Ra,
2828 (opnode (sext_inreg GPR:$Rn, i16),
2829 (sext_inreg GPR:$Rm, i16))))]>,
2830 Requires<[IsARM, HasV5TE]>;
2832 def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd),
2833 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2834 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2835 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2836 (sra GPR:$Rm, (i32 16)))))]>,
2837 Requires<[IsARM, HasV5TE]>;
2839 def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd),
2840 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2841 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2842 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2843 (sext_inreg GPR:$Rm, i16))))]>,
2844 Requires<[IsARM, HasV5TE]>;
2846 def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
2847 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2848 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2849 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2850 (sra GPR:$Rm, (i32 16)))))]>,
2851 Requires<[IsARM, HasV5TE]>;
2853 def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd),
2854 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2855 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2856 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2857 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2858 Requires<[IsARM, HasV5TE]>;
2860 def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd),
2861 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2862 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2863 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2864 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2865 Requires<[IsARM, HasV5TE]>;
2868 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2869 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2871 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2872 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2873 (ins GPR:$Rn, GPR:$Rm),
2874 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2875 [/* For disassembly only; pattern left blank */]>,
2876 Requires<[IsARM, HasV5TE]>;
2878 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2879 (ins GPR:$Rn, GPR:$Rm),
2880 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2881 [/* For disassembly only; pattern left blank */]>,
2882 Requires<[IsARM, HasV5TE]>;
2884 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2885 (ins GPR:$Rn, GPR:$Rm),
2886 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2887 [/* For disassembly only; pattern left blank */]>,
2888 Requires<[IsARM, HasV5TE]>;
2890 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2891 (ins GPR:$Rn, GPR:$Rm),
2892 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2893 [/* For disassembly only; pattern left blank */]>,
2894 Requires<[IsARM, HasV5TE]>;
2896 // Helper class for AI_smld -- for disassembly only
2897 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2898 InstrItinClass itin, string opc, string asm>
2899 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2906 let Inst{21-20} = 0b00;
2907 let Inst{22} = long;
2908 let Inst{27-23} = 0b01110;
2909 let Inst{11-8} = Rm;
2912 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2913 InstrItinClass itin, string opc, string asm>
2914 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2916 let Inst{15-12} = 0b1111;
2917 let Inst{19-16} = Rd;
2919 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2920 InstrItinClass itin, string opc, string asm>
2921 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2923 let Inst{15-12} = Ra;
2925 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2926 InstrItinClass itin, string opc, string asm>
2927 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2930 let Inst{19-16} = RdHi;
2931 let Inst{15-12} = RdLo;
2934 multiclass AI_smld<bit sub, string opc> {
2936 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2937 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
2939 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2940 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
2942 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
2943 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2944 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
2946 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
2947 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2948 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
2952 defm SMLA : AI_smld<0, "smla">;
2953 defm SMLS : AI_smld<1, "smls">;
2955 multiclass AI_sdml<bit sub, string opc> {
2957 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2958 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
2959 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2960 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
2963 defm SMUA : AI_sdml<0, "smua">;
2964 defm SMUS : AI_sdml<1, "smus">;
2966 //===----------------------------------------------------------------------===//
2967 // Misc. Arithmetic Instructions.
2970 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
2971 IIC_iUNAr, "clz", "\t$Rd, $Rm",
2972 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
2974 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2975 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
2976 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
2977 Requires<[IsARM, HasV6T2]>;
2979 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2980 IIC_iUNAr, "rev", "\t$Rd, $Rm",
2981 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
2983 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2984 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
2986 (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
2987 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
2988 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
2989 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
2990 Requires<[IsARM, HasV6]>;
2992 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2993 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
2996 (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
2997 (shl GPR:$Rm, (i32 8))), i16))]>,
2998 Requires<[IsARM, HasV6]>;
3000 def lsl_shift_imm : SDNodeXForm<imm, [{
3001 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
3002 return CurDAG->getTargetConstant(Sh, MVT::i32);
3005 def lsl_amt : PatLeaf<(i32 imm), [{
3006 return (N->getZExtValue() < 32);
3009 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
3010 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3011 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3012 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
3013 (and (shl GPR:$Rm, lsl_amt:$sh),
3015 Requires<[IsARM, HasV6]>;
3017 // Alternate cases for PKHBT where identities eliminate some nodes.
3018 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
3019 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
3020 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
3021 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
3023 def asr_shift_imm : SDNodeXForm<imm, [{
3024 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
3025 return CurDAG->getTargetConstant(Sh, MVT::i32);
3028 def asr_amt : PatLeaf<(i32 imm), [{
3029 return (N->getZExtValue() <= 32);
3032 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3033 // will match the pattern below.
3034 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
3035 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3036 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3037 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
3038 (and (sra GPR:$Rm, asr_amt:$sh),
3040 Requires<[IsARM, HasV6]>;
3042 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3043 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3044 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
3045 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
3046 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
3047 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
3048 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
3050 //===----------------------------------------------------------------------===//
3051 // Comparison Instructions...
3054 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3055 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3056 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3058 // ARMcmpZ can re-use the above instruction definitions.
3059 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3060 (CMPri GPR:$src, so_imm:$imm)>;
3061 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3062 (CMPrr GPR:$src, GPR:$rhs)>;
3063 def : ARMPat<(ARMcmpZ GPR:$src, so_reg:$rhs),
3064 (CMPrs GPR:$src, so_reg:$rhs)>;
3066 // FIXME: We have to be careful when using the CMN instruction and comparison
3067 // with 0. One would expect these two pieces of code should give identical
3083 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3084 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3085 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3086 // value of r0 and the carry bit (because the "carry bit" parameter to
3087 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3088 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3089 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3090 // parameter to AddWithCarry is defined as 0).
3092 // When x is 0 and unsigned:
3096 // ~x + 1 = 0x1 0000 0000
3097 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3099 // Therefore, we should disable CMN when comparing against zero, until we can
3100 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3101 // when it's a comparison which doesn't look at the 'carry' flag).
3103 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3105 // This is related to <rdar://problem/7569620>.
3107 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3108 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3110 // Note that TST/TEQ don't set all the same flags that CMP does!
3111 defm TST : AI1_cmp_irs<0b1000, "tst",
3112 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3113 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3114 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3115 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3116 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3118 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
3119 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3120 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
3122 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3123 // (CMNri GPR:$src, so_imm_neg:$imm)>;
3125 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3126 (CMNzri GPR:$src, so_imm_neg:$imm)>;
3128 // Pseudo i64 compares for some floating point compares.
3129 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3131 def BCCi64 : PseudoInst<(outs),
3132 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3134 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3136 def BCCZi64 : PseudoInst<(outs),
3137 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3138 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3139 } // usesCustomInserter
3142 // Conditional moves
3143 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3144 // a two-value operand where a dag node expects two operands. :(
3145 let neverHasSideEffects = 1 in {
3146 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3147 Size4Bytes, IIC_iCMOVr,
3148 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3149 RegConstraint<"$false = $Rd">;
3150 def MOVCCs : ARMPseudoInst<(outs GPR:$Rd),
3151 (ins GPR:$false, so_reg:$shift, pred:$p),
3152 Size4Bytes, IIC_iCMOVsr,
3153 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
3154 RegConstraint<"$false = $Rd">;
3156 let isMoveImm = 1 in
3157 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3158 (ins GPR:$false, i32imm_hilo16:$imm, pred:$p),
3159 Size4Bytes, IIC_iMOVi,
3161 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3163 let isMoveImm = 1 in
3164 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3165 (ins GPR:$false, so_imm:$imm, pred:$p),
3166 Size4Bytes, IIC_iCMOVi,
3167 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3168 RegConstraint<"$false = $Rd">;
3170 // Two instruction predicate mov immediate.
3171 let isMoveImm = 1 in
3172 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
3173 (ins GPR:$false, i32imm:$src, pred:$p),
3174 Size8Bytes, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3176 let isMoveImm = 1 in
3177 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
3178 (ins GPR:$false, so_imm:$imm, pred:$p),
3179 Size4Bytes, IIC_iCMOVi,
3180 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3181 RegConstraint<"$false = $Rd">;
3182 } // neverHasSideEffects
3184 //===----------------------------------------------------------------------===//
3185 // Atomic operations intrinsics
3188 def memb_opt : Operand<i32> {
3189 let PrintMethod = "printMemBOption";
3190 let ParserMatchClass = MemBarrierOptOperand;
3193 // memory barriers protect the atomic sequences
3194 let hasSideEffects = 1 in {
3195 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3196 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3197 Requires<[IsARM, HasDB]> {
3199 let Inst{31-4} = 0xf57ff05;
3200 let Inst{3-0} = opt;
3204 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3206 [/* For disassembly only; pattern left blank */]>,
3207 Requires<[IsARM, HasDB]> {
3209 let Inst{31-4} = 0xf57ff04;
3210 let Inst{3-0} = opt;
3213 // ISB has only full system option -- for disassembly only
3214 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
3215 Requires<[IsARM, HasDB]> {
3216 let Inst{31-4} = 0xf57ff06;
3217 let Inst{3-0} = 0b1111;
3220 let usesCustomInserter = 1 in {
3221 let Uses = [CPSR] in {
3222 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
3223 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3224 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
3225 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
3226 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3227 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
3228 def ATOMIC_LOAD_AND_I8 : PseudoInst<
3229 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3230 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
3231 def ATOMIC_LOAD_OR_I8 : PseudoInst<
3232 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3233 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
3234 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
3235 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3236 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
3237 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
3238 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3239 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
3240 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
3241 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3242 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
3243 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
3244 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3245 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
3246 def ATOMIC_LOAD_AND_I16 : PseudoInst<
3247 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3248 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
3249 def ATOMIC_LOAD_OR_I16 : PseudoInst<
3250 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3251 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
3252 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
3253 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3254 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
3255 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
3256 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3257 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
3258 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
3259 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3260 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
3261 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
3262 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3263 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
3264 def ATOMIC_LOAD_AND_I32 : PseudoInst<
3265 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3266 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
3267 def ATOMIC_LOAD_OR_I32 : PseudoInst<
3268 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3269 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
3270 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
3271 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3272 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
3273 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
3274 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3275 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
3277 def ATOMIC_SWAP_I8 : PseudoInst<
3278 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3279 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3280 def ATOMIC_SWAP_I16 : PseudoInst<
3281 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3282 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3283 def ATOMIC_SWAP_I32 : PseudoInst<
3284 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3285 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3287 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3288 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3289 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3290 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3291 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3292 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3293 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3294 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3295 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3299 let mayLoad = 1 in {
3300 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3301 "ldrexb", "\t$Rt, [$Rn]",
3303 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3304 "ldrexh", "\t$Rt, [$Rn]",
3306 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3307 "ldrex", "\t$Rt, [$Rn]",
3309 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins GPR:$Rn),
3311 "ldrexd", "\t$Rt, $Rt2, [$Rn]",
3315 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3316 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$src, GPR:$Rn),
3318 "strexb", "\t$Rd, $src, [$Rn]",
3320 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3322 "strexh", "\t$Rd, $Rt, [$Rn]",
3324 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3326 "strex", "\t$Rd, $Rt, [$Rn]",
3328 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3329 (ins GPR:$Rt, GPR:$Rt2, GPR:$Rn),
3331 "strexd", "\t$Rd, $Rt, $Rt2, [$Rn]",
3335 // Clear-Exclusive is for disassembly only.
3336 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3337 [/* For disassembly only; pattern left blank */]>,
3338 Requires<[IsARM, HasV7]> {
3339 let Inst{31-0} = 0b11110101011111111111000000011111;
3342 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3343 let mayLoad = 1 in {
3344 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3345 [/* For disassembly only; pattern left blank */]>;
3346 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3347 [/* For disassembly only; pattern left blank */]>;
3350 //===----------------------------------------------------------------------===//
3351 // Coprocessor Instructions.
3354 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3355 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3356 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3357 [/* For disassembly only; pattern left blank */]> {
3365 let Inst{3-0} = CRm;
3367 let Inst{7-5} = opc2;
3368 let Inst{11-8} = cop;
3369 let Inst{15-12} = CRd;
3370 let Inst{19-16} = CRn;
3371 let Inst{23-20} = opc1;
3374 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3375 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3376 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3377 [/* For disassembly only; pattern left blank */]> {
3378 let Inst{31-28} = 0b1111;
3386 let Inst{3-0} = CRm;
3388 let Inst{7-5} = opc2;
3389 let Inst{11-8} = cop;
3390 let Inst{15-12} = CRd;
3391 let Inst{19-16} = CRn;
3392 let Inst{23-20} = opc1;
3395 class ACI<dag oops, dag iops, string opc, string asm>
3396 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
3397 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3398 let Inst{27-25} = 0b110;
3401 multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
3403 def _OFFSET : ACI<(outs),
3404 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3405 opc, "\tp$cop, cr$CRd, $addr"> {
3406 let Inst{31-28} = op31_28;
3407 let Inst{24} = 1; // P = 1
3408 let Inst{21} = 0; // W = 0
3409 let Inst{22} = 0; // D = 0
3410 let Inst{20} = load;
3413 def _PRE : ACI<(outs),
3414 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3415 opc, "\tp$cop, cr$CRd, $addr!"> {
3416 let Inst{31-28} = op31_28;
3417 let Inst{24} = 1; // P = 1
3418 let Inst{21} = 1; // W = 1
3419 let Inst{22} = 0; // D = 0
3420 let Inst{20} = load;
3423 def _POST : ACI<(outs),
3424 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3425 opc, "\tp$cop, cr$CRd, [$base], $offset"> {
3426 let Inst{31-28} = op31_28;
3427 let Inst{24} = 0; // P = 0
3428 let Inst{21} = 1; // W = 1
3429 let Inst{22} = 0; // D = 0
3430 let Inst{20} = load;
3433 def _OPTION : ACI<(outs),
3434 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option),
3435 opc, "\tp$cop, cr$CRd, [$base], $option"> {
3436 let Inst{31-28} = op31_28;
3437 let Inst{24} = 0; // P = 0
3438 let Inst{23} = 1; // U = 1
3439 let Inst{21} = 0; // W = 0
3440 let Inst{22} = 0; // D = 0
3441 let Inst{20} = load;
3444 def L_OFFSET : ACI<(outs),
3445 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3446 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
3447 let Inst{31-28} = op31_28;
3448 let Inst{24} = 1; // P = 1
3449 let Inst{21} = 0; // W = 0
3450 let Inst{22} = 1; // D = 1
3451 let Inst{20} = load;
3454 def L_PRE : ACI<(outs),
3455 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3456 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
3457 let Inst{31-28} = op31_28;
3458 let Inst{24} = 1; // P = 1
3459 let Inst{21} = 1; // W = 1
3460 let Inst{22} = 1; // D = 1
3461 let Inst{20} = load;
3464 def L_POST : ACI<(outs),
3465 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3466 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $offset"> {
3467 let Inst{31-28} = op31_28;
3468 let Inst{24} = 0; // P = 0
3469 let Inst{21} = 1; // W = 1
3470 let Inst{22} = 1; // D = 1
3471 let Inst{20} = load;
3474 def L_OPTION : ACI<(outs),
3475 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
3476 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $option"> {
3477 let Inst{31-28} = op31_28;
3478 let Inst{24} = 0; // P = 0
3479 let Inst{23} = 1; // U = 1
3480 let Inst{21} = 0; // W = 0
3481 let Inst{22} = 1; // D = 1
3482 let Inst{20} = load;
3486 defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">;
3487 defm LDC2 : LdStCop<0b1111, 1, "ldc2">;
3488 defm STC : LdStCop<{?,?,?,?}, 0, "stc">;
3489 defm STC2 : LdStCop<0b1111, 0, "stc2">;
3491 //===----------------------------------------------------------------------===//
3492 // Move between coprocessor and ARM core register -- for disassembly only
3495 class MovRCopro<string opc, bit direction>
3496 : ABI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3497 GPR:$Rt, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3498 NoItinerary, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
3499 [/* For disassembly only; pattern left blank */]> {
3500 let Inst{20} = direction;
3510 let Inst{15-12} = Rt;
3511 let Inst{11-8} = cop;
3512 let Inst{23-21} = opc1;
3513 let Inst{7-5} = opc2;
3514 let Inst{3-0} = CRm;
3515 let Inst{19-16} = CRn;
3518 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */>;
3519 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */>;
3521 class MovRCopro2<string opc, bit direction>
3522 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3523 GPR:$Rt, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3524 NoItinerary, !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3525 [/* For disassembly only; pattern left blank */]> {
3526 let Inst{31-28} = 0b1111;
3527 let Inst{20} = direction;
3537 let Inst{15-12} = Rt;
3538 let Inst{11-8} = cop;
3539 let Inst{23-21} = opc1;
3540 let Inst{7-5} = opc2;
3541 let Inst{3-0} = CRm;
3542 let Inst{19-16} = CRn;
3545 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */>;
3546 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */>;
3548 class MovRRCopro<string opc, bit direction>
3549 : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
3550 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3551 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm",
3552 [/* For disassembly only; pattern left blank */]> {
3553 let Inst{23-21} = 0b010;
3554 let Inst{20} = direction;
3562 let Inst{15-12} = Rt;
3563 let Inst{19-16} = Rt2;
3564 let Inst{11-8} = cop;
3565 let Inst{7-4} = opc1;
3566 let Inst{3-0} = CRm;
3569 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */>;
3570 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
3572 class MovRRCopro2<string opc, bit direction>
3573 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
3574 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3575 NoItinerary, !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"),
3576 [/* For disassembly only; pattern left blank */]> {
3577 let Inst{31-28} = 0b1111;
3578 let Inst{23-21} = 0b010;
3579 let Inst{20} = direction;
3587 let Inst{15-12} = Rt;
3588 let Inst{19-16} = Rt2;
3589 let Inst{11-8} = cop;
3590 let Inst{7-4} = opc1;
3591 let Inst{3-0} = CRm;
3594 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */>;
3595 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
3597 //===----------------------------------------------------------------------===//
3598 // Move between special register and ARM core register -- for disassembly only
3601 // Move to ARM core register from Special Register
3602 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3603 [/* For disassembly only; pattern left blank */]> {
3605 let Inst{23-16} = 0b00001111;
3606 let Inst{15-12} = Rd;
3607 let Inst{7-4} = 0b0000;
3610 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,"mrs","\t$Rd, spsr",
3611 [/* For disassembly only; pattern left blank */]> {
3613 let Inst{23-16} = 0b01001111;
3614 let Inst{15-12} = Rd;
3615 let Inst{7-4} = 0b0000;
3618 // Move from ARM core register to Special Register
3620 // No need to have both system and application versions, the encodings are the
3621 // same and the assembly parser has no way to distinguish between them. The mask
3622 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3623 // the mask with the fields to be accessed in the special register.
3624 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
3625 "msr", "\t$mask, $Rn",
3626 [/* For disassembly only; pattern left blank */]> {
3631 let Inst{22} = mask{4}; // R bit
3632 let Inst{21-20} = 0b10;
3633 let Inst{19-16} = mask{3-0};
3634 let Inst{15-12} = 0b1111;
3635 let Inst{11-4} = 0b00000000;
3639 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
3640 "msr", "\t$mask, $a",
3641 [/* For disassembly only; pattern left blank */]> {
3646 let Inst{22} = mask{4}; // R bit
3647 let Inst{21-20} = 0b10;
3648 let Inst{19-16} = mask{3-0};
3649 let Inst{15-12} = 0b1111;
3653 //===----------------------------------------------------------------------===//
3657 // __aeabi_read_tp preserves the registers r1-r3.
3658 // This is a pseudo inst so that we can get the encoding right,
3659 // complete with fixup for the aeabi_read_tp function.
3661 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
3662 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
3663 [(set R0, ARMthread_pointer)]>;
3666 //===----------------------------------------------------------------------===//
3667 // SJLJ Exception handling intrinsics
3668 // eh_sjlj_setjmp() is an instruction sequence to store the return
3669 // address and save #0 in R0 for the non-longjmp case.
3670 // Since by its nature we may be coming from some other function to get
3671 // here, and we're using the stack frame for the containing function to
3672 // save/restore registers, we can't keep anything live in regs across
3673 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3674 // when we get here from a longjmp(). We force everthing out of registers
3675 // except for our own input by listing the relevant registers in Defs. By
3676 // doing so, we also cause the prologue/epilogue code to actively preserve
3677 // all of the callee-saved resgisters, which is exactly what we want.
3678 // A constant value is passed in $val, and we use the location as a scratch.
3680 // These are pseudo-instructions and are lowered to individual MC-insts, so
3681 // no encoding information is necessary.
3683 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
3684 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
3685 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
3686 D31 ], hasSideEffects = 1, isBarrier = 1 in {
3687 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3689 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3690 Requires<[IsARM, HasVFP2]>;
3694 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
3695 hasSideEffects = 1, isBarrier = 1 in {
3696 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3698 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3699 Requires<[IsARM, NoVFP]>;
3702 // FIXME: Non-Darwin version(s)
3703 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3704 Defs = [ R7, LR, SP ] in {
3705 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
3707 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3708 Requires<[IsARM, IsDarwin]>;
3711 // eh.sjlj.dispatchsetup pseudo-instruction.
3712 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3713 // handled when the pseudo is expanded (which happens before any passes
3714 // that need the instruction size).
3715 let isBarrier = 1, hasSideEffects = 1 in
3716 def Int_eh_sjlj_dispatchsetup :
3717 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
3718 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
3719 Requires<[IsDarwin]>;
3721 //===----------------------------------------------------------------------===//
3722 // Non-Instruction Patterns
3725 // Large immediate handling.
3727 // 32-bit immediate using two piece so_imms or movw + movt.
3728 // This is a single pseudo instruction, the benefit is that it can be remat'd
3729 // as a single unit instead of having to handle reg inputs.
3730 // FIXME: Remove this when we can do generalized remat.
3731 let isReMaterializable = 1, isMoveImm = 1 in
3732 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3733 [(set GPR:$dst, (arm_i32imm:$src))]>,
3736 // Pseudo instruction that combines movw + movt + add pc (if PIC).
3737 // It also makes it possible to rematerialize the instructions.
3738 // FIXME: Remove this when we can do generalized remat and when machine licm
3739 // can properly the instructions.
3740 let isReMaterializable = 1 in {
3741 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3743 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3744 Requires<[IsARM, UseMovt]>;
3746 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3748 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3749 Requires<[IsARM, UseMovt]>;
3751 let AddedComplexity = 10 in
3752 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3754 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
3755 Requires<[IsARM, UseMovt]>;
3756 } // isReMaterializable
3758 // ConstantPool, GlobalAddress, and JumpTable
3759 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3760 Requires<[IsARM, DontUseMovt]>;
3761 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3762 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3763 Requires<[IsARM, UseMovt]>;
3764 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3765 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3767 // TODO: add,sub,and, 3-instr forms?
3770 def : ARMPat<(ARMtcret tcGPR:$dst),
3771 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3773 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3774 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3776 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3777 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3779 def : ARMPat<(ARMtcret tcGPR:$dst),
3780 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3782 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3783 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3785 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3786 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3789 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3790 Requires<[IsARM, IsNotDarwin]>;
3791 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3792 Requires<[IsARM, IsDarwin]>;
3794 // zextload i1 -> zextload i8
3795 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3796 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3798 // extload -> zextload
3799 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3800 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3801 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3802 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3804 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3806 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3807 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3810 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3811 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3812 (SMULBB GPR:$a, GPR:$b)>;
3813 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3814 (SMULBB GPR:$a, GPR:$b)>;
3815 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3816 (sra GPR:$b, (i32 16))),
3817 (SMULBT GPR:$a, GPR:$b)>;
3818 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3819 (SMULBT GPR:$a, GPR:$b)>;
3820 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3821 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3822 (SMULTB GPR:$a, GPR:$b)>;
3823 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3824 (SMULTB GPR:$a, GPR:$b)>;
3825 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3827 (SMULWB GPR:$a, GPR:$b)>;
3828 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3829 (SMULWB GPR:$a, GPR:$b)>;
3831 def : ARMV5TEPat<(add GPR:$acc,
3832 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3833 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3834 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3835 def : ARMV5TEPat<(add GPR:$acc,
3836 (mul sext_16_node:$a, sext_16_node:$b)),
3837 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3838 def : ARMV5TEPat<(add GPR:$acc,
3839 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3840 (sra GPR:$b, (i32 16)))),
3841 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3842 def : ARMV5TEPat<(add GPR:$acc,
3843 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3844 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3845 def : ARMV5TEPat<(add GPR:$acc,
3846 (mul (sra GPR:$a, (i32 16)),
3847 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3848 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3849 def : ARMV5TEPat<(add GPR:$acc,
3850 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3851 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3852 def : ARMV5TEPat<(add GPR:$acc,
3853 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3855 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3856 def : ARMV5TEPat<(add GPR:$acc,
3857 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3858 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3861 // Pre-v7 uses MCR for synchronization barriers.
3862 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
3863 Requires<[IsARM, HasV6]>;
3866 //===----------------------------------------------------------------------===//
3870 include "ARMInstrThumb.td"
3872 //===----------------------------------------------------------------------===//
3876 include "ARMInstrThumb2.td"
3878 //===----------------------------------------------------------------------===//
3879 // Floating Point Support
3882 include "ARMInstrVFP.td"
3884 //===----------------------------------------------------------------------===//
3885 // Advanced SIMD (NEON) Support
3888 include "ARMInstrNEON.td"