1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
67 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
68 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
72 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
74 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
75 [SDNPHasChain, SDNPOutFlag]>;
76 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
77 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
79 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
80 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
82 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
83 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
85 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
86 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
89 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
90 [SDNPHasChain, SDNPOptInFlag]>;
92 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
94 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
97 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
98 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
100 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
102 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
105 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
108 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
111 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
112 [SDNPOutFlag, SDNPCommutative]>;
114 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
116 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
117 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
118 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
120 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
121 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
122 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
123 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
124 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
125 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
126 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
129 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
131 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
133 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDTPrefetch,
134 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
136 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
138 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
139 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
142 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
144 //===----------------------------------------------------------------------===//
145 // ARM Instruction Predicate Definitions.
147 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
148 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
149 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
150 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
151 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
152 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
153 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
154 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
155 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
156 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
157 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
158 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
159 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
160 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
162 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
164 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
166 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
167 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
168 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
169 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
170 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
171 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
172 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
173 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
175 // FIXME: Eventually this will be just "hasV6T2Ops".
176 def UseMovt : Predicate<"Subtarget->useMovt()">;
177 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
178 def UseVMLx : Predicate<"Subtarget->useVMLx()">;
180 //===----------------------------------------------------------------------===//
181 // ARM Flag Definitions.
183 class RegConstraint<string C> {
184 string Constraints = C;
187 //===----------------------------------------------------------------------===//
188 // ARM specific transformation functions and pattern fragments.
191 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
192 // so_imm_neg def below.
193 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
194 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
197 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
198 // so_imm_not def below.
199 def so_imm_not_XFORM : SDNodeXForm<imm, [{
200 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
203 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
204 def imm1_15 : PatLeaf<(i32 imm), [{
205 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
208 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
209 def imm16_31 : PatLeaf<(i32 imm), [{
210 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
215 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
216 }], so_imm_neg_XFORM>;
220 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
221 }], so_imm_not_XFORM>;
223 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
224 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
225 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
228 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
230 def bf_inv_mask_imm : Operand<i32>,
232 return ARM::isBitFieldInvertedMask(N->getZExtValue());
234 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
235 let PrintMethod = "printBitfieldInvMaskImmOperand";
238 /// Split a 32-bit immediate into two 16 bit parts.
239 def hi16 : SDNodeXForm<imm, [{
240 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
243 def lo16AllZero : PatLeaf<(i32 imm), [{
244 // Returns true if all low 16-bits are 0.
245 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
248 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
250 def imm0_65535 : PatLeaf<(i32 imm), [{
251 return (uint32_t)N->getZExtValue() < 65536;
254 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
255 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
257 /// adde and sube predicates - True based on whether the carry flag output
258 /// will be needed or not.
259 def adde_dead_carry :
260 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
261 [{return !N->hasAnyUseOfValue(1);}]>;
262 def sube_dead_carry :
263 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
264 [{return !N->hasAnyUseOfValue(1);}]>;
265 def adde_live_carry :
266 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
267 [{return N->hasAnyUseOfValue(1);}]>;
268 def sube_live_carry :
269 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
270 [{return N->hasAnyUseOfValue(1);}]>;
272 // An 'and' node with a single use.
273 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
274 return N->hasOneUse();
277 // An 'xor' node with a single use.
278 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
279 return N->hasOneUse();
282 //===----------------------------------------------------------------------===//
283 // Operand Definitions.
287 def brtarget : Operand<OtherVT> {
288 let EncoderMethod = "getBranchTargetOpValue";
292 def bltarget : Operand<i32> {
293 // Encoded the same as branch targets.
294 let EncoderMethod = "getBranchTargetOpValue";
297 // A list of registers separated by comma. Used by load/store multiple.
298 def RegListAsmOperand : AsmOperandClass {
299 let Name = "RegList";
300 let SuperClasses = [];
303 def DPRRegListAsmOperand : AsmOperandClass {
304 let Name = "DPRRegList";
305 let SuperClasses = [];
308 def SPRRegListAsmOperand : AsmOperandClass {
309 let Name = "SPRRegList";
310 let SuperClasses = [];
313 def reglist : Operand<i32> {
314 let EncoderMethod = "getRegisterListOpValue";
315 let ParserMatchClass = RegListAsmOperand;
316 let PrintMethod = "printRegisterList";
319 def dpr_reglist : Operand<i32> {
320 let EncoderMethod = "getRegisterListOpValue";
321 let ParserMatchClass = DPRRegListAsmOperand;
322 let PrintMethod = "printRegisterList";
325 def spr_reglist : Operand<i32> {
326 let EncoderMethod = "getRegisterListOpValue";
327 let ParserMatchClass = SPRRegListAsmOperand;
328 let PrintMethod = "printRegisterList";
331 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
332 def cpinst_operand : Operand<i32> {
333 let PrintMethod = "printCPInstOperand";
337 def pclabel : Operand<i32> {
338 let PrintMethod = "printPCLabel";
341 def neon_vcvt_imm32 : Operand<i32> {
342 let EncoderMethod = "getNEONVcvtImm32OpValue";
345 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
346 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
347 int32_t v = (int32_t)N->getZExtValue();
348 return v == 8 || v == 16 || v == 24; }]> {
349 let EncoderMethod = "getRotImmOpValue";
352 // shift_imm: An integer that encodes a shift amount and the type of shift
353 // (currently either asr or lsl) using the same encoding used for the
354 // immediates in so_reg operands.
355 def shift_imm : Operand<i32> {
356 let PrintMethod = "printShiftImmOperand";
359 // shifter_operand operands: so_reg and so_imm.
360 def so_reg : Operand<i32>, // reg reg imm
361 ComplexPattern<i32, 3, "SelectShifterOperandReg",
362 [shl,srl,sra,rotr]> {
363 let EncoderMethod = "getSORegOpValue";
364 let PrintMethod = "printSORegOperand";
365 let MIOperandInfo = (ops GPR, GPR, i32imm);
367 def shift_so_reg : Operand<i32>, // reg reg imm
368 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
369 [shl,srl,sra,rotr]> {
370 let EncoderMethod = "getSORegOpValue";
371 let PrintMethod = "printSORegOperand";
372 let MIOperandInfo = (ops GPR, GPR, i32imm);
375 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
376 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
377 // represented in the imm field in the same 12-bit form that they are encoded
378 // into so_imm instructions: the 8-bit immediate is the least significant bits
379 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
380 def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> {
381 let EncoderMethod = "getSOImmOpValue";
382 let PrintMethod = "printSOImmOperand";
385 // Break so_imm's up into two pieces. This handles immediates with up to 16
386 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
387 // get the first/second pieces.
388 def so_imm2part : PatLeaf<(imm), [{
389 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
392 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
394 def arm_i32imm : PatLeaf<(imm), [{
395 if (Subtarget->hasV6T2Ops())
397 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
400 def so_imm2part_1 : SDNodeXForm<imm, [{
401 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
402 return CurDAG->getTargetConstant(V, MVT::i32);
405 def so_imm2part_2 : SDNodeXForm<imm, [{
406 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
407 return CurDAG->getTargetConstant(V, MVT::i32);
410 def so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
411 return ARM_AM::isSOImmTwoPartVal(-(int)N->getZExtValue());
413 let PrintMethod = "printSOImm2PartOperand";
416 def so_neg_imm2part_1 : SDNodeXForm<imm, [{
417 unsigned V = ARM_AM::getSOImmTwoPartFirst(-(int)N->getZExtValue());
418 return CurDAG->getTargetConstant(V, MVT::i32);
421 def so_neg_imm2part_2 : SDNodeXForm<imm, [{
422 unsigned V = ARM_AM::getSOImmTwoPartSecond(-(int)N->getZExtValue());
423 return CurDAG->getTargetConstant(V, MVT::i32);
426 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
427 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
428 return (int32_t)N->getZExtValue() < 32;
431 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
432 def imm0_31_m1 : Operand<i32>, PatLeaf<(imm), [{
433 return (int32_t)N->getZExtValue() < 32;
435 let EncoderMethod = "getImmMinusOneOpValue";
438 // For movt/movw - sets the MC Encoder method.
439 // The imm is split into imm{15-12}, imm{11-0}
441 def movt_imm : Operand<i32> {
442 let EncoderMethod = "getMovtImmOpValue";
445 // Define ARM specific addressing modes.
448 // addrmode_imm12 := reg +/- imm12
450 def addrmode_imm12 : Operand<i32>,
451 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
452 // 12-bit immediate operand. Note that instructions using this encode
453 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
454 // immediate values are as normal.
456 let EncoderMethod = "getAddrModeImm12OpValue";
457 let PrintMethod = "printAddrModeImm12Operand";
458 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
460 // ldst_so_reg := reg +/- reg shop imm
462 def ldst_so_reg : Operand<i32>,
463 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
464 let EncoderMethod = "getLdStSORegOpValue";
465 // FIXME: Simplify the printer
466 let PrintMethod = "printAddrMode2Operand";
467 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
470 // addrmode2 := reg +/- imm12
471 // := reg +/- reg shop imm
473 def addrmode2 : Operand<i32>,
474 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
475 string EncoderMethod = "getAddrMode2OpValue";
476 let PrintMethod = "printAddrMode2Operand";
477 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
480 def am2offset : Operand<i32>,
481 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
482 [], [SDNPWantRoot]> {
483 string EncoderMethod = "getAddrMode2OffsetOpValue";
484 let PrintMethod = "printAddrMode2OffsetOperand";
485 let MIOperandInfo = (ops GPR, i32imm);
488 // addrmode3 := reg +/- reg
489 // addrmode3 := reg +/- imm8
491 def addrmode3 : Operand<i32>,
492 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
493 let EncoderMethod = "getAddrMode3OpValue";
494 let PrintMethod = "printAddrMode3Operand";
495 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
498 def am3offset : Operand<i32>,
499 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
500 [], [SDNPWantRoot]> {
501 let EncoderMethod = "getAddrMode3OffsetOpValue";
502 let PrintMethod = "printAddrMode3OffsetOperand";
503 let MIOperandInfo = (ops GPR, i32imm);
506 // ldstm_mode := {ia, ib, da, db}
508 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
509 let EncoderMethod = "getLdStmModeOpValue";
510 let PrintMethod = "printLdStmModeOperand";
513 def MemMode5AsmOperand : AsmOperandClass {
514 let Name = "MemMode5";
515 let SuperClasses = [];
518 // addrmode5 := reg +/- imm8*4
520 def addrmode5 : Operand<i32>,
521 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
522 let PrintMethod = "printAddrMode5Operand";
523 let MIOperandInfo = (ops GPR:$base, i32imm);
524 let ParserMatchClass = MemMode5AsmOperand;
525 let EncoderMethod = "getAddrMode5OpValue";
528 // addrmode6 := reg with optional writeback
530 def addrmode6 : Operand<i32>,
531 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
532 let PrintMethod = "printAddrMode6Operand";
533 let MIOperandInfo = (ops GPR:$addr, i32imm);
534 let EncoderMethod = "getAddrMode6AddressOpValue";
537 def am6offset : Operand<i32> {
538 let PrintMethod = "printAddrMode6OffsetOperand";
539 let MIOperandInfo = (ops GPR);
540 let EncoderMethod = "getAddrMode6OffsetOpValue";
543 // addrmodepc := pc + reg
545 def addrmodepc : Operand<i32>,
546 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
547 let PrintMethod = "printAddrModePCOperand";
548 let MIOperandInfo = (ops GPR, i32imm);
551 def nohash_imm : Operand<i32> {
552 let PrintMethod = "printNoHashImmediate";
555 //===----------------------------------------------------------------------===//
557 include "ARMInstrFormats.td"
559 //===----------------------------------------------------------------------===//
560 // Multiclass helpers...
563 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
564 /// binop that produces a value.
565 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
566 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
567 PatFrag opnode, bit Commutable = 0> {
568 // The register-immediate version is re-materializable. This is useful
569 // in particular for taking the address of a local.
570 let isReMaterializable = 1 in {
571 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
572 iii, opc, "\t$Rd, $Rn, $imm",
573 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
578 let Inst{19-16} = Rn;
579 let Inst{15-12} = Rd;
580 let Inst{11-0} = imm;
583 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
584 iir, opc, "\t$Rd, $Rn, $Rm",
585 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
590 let isCommutable = Commutable;
591 let Inst{19-16} = Rn;
592 let Inst{15-12} = Rd;
593 let Inst{11-4} = 0b00000000;
596 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
597 iis, opc, "\t$Rd, $Rn, $shift",
598 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
603 let Inst{19-16} = Rn;
604 let Inst{15-12} = Rd;
605 let Inst{11-0} = shift;
609 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
610 /// instruction modifies the CPSR register.
611 let Defs = [CPSR] in {
612 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
613 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
614 PatFrag opnode, bit Commutable = 0> {
615 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
616 iii, opc, "\t$Rd, $Rn, $imm",
617 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
623 let Inst{19-16} = Rn;
624 let Inst{15-12} = Rd;
625 let Inst{11-0} = imm;
627 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
628 iir, opc, "\t$Rd, $Rn, $Rm",
629 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
633 let isCommutable = Commutable;
636 let Inst{19-16} = Rn;
637 let Inst{15-12} = Rd;
638 let Inst{11-4} = 0b00000000;
641 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
642 iis, opc, "\t$Rd, $Rn, $shift",
643 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
649 let Inst{19-16} = Rn;
650 let Inst{15-12} = Rd;
651 let Inst{11-0} = shift;
656 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
657 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
658 /// a explicit result, only implicitly set CPSR.
659 let isCompare = 1, Defs = [CPSR] in {
660 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
661 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
662 PatFrag opnode, bit Commutable = 0> {
663 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
665 [(opnode GPR:$Rn, so_imm:$imm)]> {
670 let Inst{19-16} = Rn;
671 let Inst{15-12} = 0b0000;
672 let Inst{11-0} = imm;
674 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
676 [(opnode GPR:$Rn, GPR:$Rm)]> {
679 let isCommutable = Commutable;
682 let Inst{19-16} = Rn;
683 let Inst{15-12} = 0b0000;
684 let Inst{11-4} = 0b00000000;
687 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
688 opc, "\t$Rn, $shift",
689 [(opnode GPR:$Rn, so_reg:$shift)]> {
694 let Inst{19-16} = Rn;
695 let Inst{15-12} = 0b0000;
696 let Inst{11-0} = shift;
701 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
702 /// register and one whose operand is a register rotated by 8/16/24.
703 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
704 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
705 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
706 IIC_iEXTr, opc, "\t$Rd, $Rm",
707 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
708 Requires<[IsARM, HasV6]> {
711 let Inst{19-16} = 0b1111;
712 let Inst{15-12} = Rd;
713 let Inst{11-10} = 0b00;
716 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
717 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
718 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
719 Requires<[IsARM, HasV6]> {
723 let Inst{19-16} = 0b1111;
724 let Inst{15-12} = Rd;
725 let Inst{11-10} = rot;
730 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
731 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
732 IIC_iEXTr, opc, "\t$Rd, $Rm",
733 [/* For disassembly only; pattern left blank */]>,
734 Requires<[IsARM, HasV6]> {
735 let Inst{19-16} = 0b1111;
736 let Inst{11-10} = 0b00;
738 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
739 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
740 [/* For disassembly only; pattern left blank */]>,
741 Requires<[IsARM, HasV6]> {
743 let Inst{19-16} = 0b1111;
744 let Inst{11-10} = rot;
748 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
749 /// register and one whose operand is a register rotated by 8/16/24.
750 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
751 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
752 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
753 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
754 Requires<[IsARM, HasV6]> {
758 let Inst{19-16} = Rn;
759 let Inst{15-12} = Rd;
760 let Inst{11-10} = 0b00;
761 let Inst{9-4} = 0b000111;
764 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
766 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
767 [(set GPR:$Rd, (opnode GPR:$Rn,
768 (rotr GPR:$Rm, rot_imm:$rot)))]>,
769 Requires<[IsARM, HasV6]> {
774 let Inst{19-16} = Rn;
775 let Inst{15-12} = Rd;
776 let Inst{11-10} = rot;
777 let Inst{9-4} = 0b000111;
782 // For disassembly only.
783 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
784 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
785 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
786 [/* For disassembly only; pattern left blank */]>,
787 Requires<[IsARM, HasV6]> {
788 let Inst{11-10} = 0b00;
790 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
792 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
793 [/* For disassembly only; pattern left blank */]>,
794 Requires<[IsARM, HasV6]> {
797 let Inst{19-16} = Rn;
798 let Inst{11-10} = rot;
802 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
803 let Uses = [CPSR] in {
804 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
805 bit Commutable = 0> {
806 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
807 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
808 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
814 let Inst{15-12} = Rd;
815 let Inst{19-16} = Rn;
816 let Inst{11-0} = imm;
818 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
819 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
820 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
825 let Inst{11-4} = 0b00000000;
827 let isCommutable = Commutable;
829 let Inst{15-12} = Rd;
830 let Inst{19-16} = Rn;
832 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
833 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
834 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
840 let Inst{11-0} = shift;
841 let Inst{15-12} = Rd;
842 let Inst{19-16} = Rn;
845 // Carry setting variants
846 let Defs = [CPSR] in {
847 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
848 bit Commutable = 0> {
849 def Sri : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
850 DPFrm, IIC_iALUi, !strconcat(opc, "\t$Rd, $Rn, $imm"),
851 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
856 let Inst{15-12} = Rd;
857 let Inst{19-16} = Rn;
858 let Inst{11-0} = imm;
862 def Srr : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
863 DPFrm, IIC_iALUr, !strconcat(opc, "\t$Rd, $Rn, $Rm"),
864 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
869 let Inst{11-4} = 0b00000000;
870 let isCommutable = Commutable;
872 let Inst{15-12} = Rd;
873 let Inst{19-16} = Rn;
877 def Srs : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
878 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$Rd, $Rn, $shift"),
879 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
884 let Inst{11-0} = shift;
885 let Inst{15-12} = Rd;
886 let Inst{19-16} = Rn;
894 let canFoldAsLoad = 1, isReMaterializable = 1 in {
895 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
896 InstrItinClass iir, PatFrag opnode> {
897 // Note: We use the complex addrmode_imm12 rather than just an input
898 // GPR and a constrained immediate so that we can use this to match
899 // frame index references and avoid matching constant pool references.
900 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
901 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
902 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
905 let Inst{23} = addr{12}; // U (add = ('U' == 1))
906 let Inst{19-16} = addr{16-13}; // Rn
907 let Inst{15-12} = Rt;
908 let Inst{11-0} = addr{11-0}; // imm12
910 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
911 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
912 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
915 let Inst{23} = shift{12}; // U (add = ('U' == 1))
916 let Inst{19-16} = shift{16-13}; // Rn
917 let Inst{15-12} = Rt;
918 let Inst{11-0} = shift{11-0};
923 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
924 InstrItinClass iir, PatFrag opnode> {
925 // Note: We use the complex addrmode_imm12 rather than just an input
926 // GPR and a constrained immediate so that we can use this to match
927 // frame index references and avoid matching constant pool references.
928 def i12 : AI2ldst<0b010, 0, isByte, (outs),
929 (ins GPR:$Rt, addrmode_imm12:$addr),
930 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
931 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
934 let Inst{23} = addr{12}; // U (add = ('U' == 1))
935 let Inst{19-16} = addr{16-13}; // Rn
936 let Inst{15-12} = Rt;
937 let Inst{11-0} = addr{11-0}; // imm12
939 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
940 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
941 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
944 let Inst{23} = shift{12}; // U (add = ('U' == 1))
945 let Inst{19-16} = shift{16-13}; // Rn
946 let Inst{15-12} = Rt;
947 let Inst{11-0} = shift{11-0};
950 //===----------------------------------------------------------------------===//
952 //===----------------------------------------------------------------------===//
954 //===----------------------------------------------------------------------===//
955 // Miscellaneous Instructions.
958 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
959 /// the function. The first operand is the ID# for this instruction, the second
960 /// is the index into the MachineConstantPool that this is, the third is the
961 /// size in bytes of this constant pool entry.
962 let neverHasSideEffects = 1, isNotDuplicable = 1 in
963 def CONSTPOOL_ENTRY :
964 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
965 i32imm:$size), NoItinerary, []>;
967 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
968 // from removing one half of the matched pairs. That breaks PEI, which assumes
969 // these will always be in pairs, and asserts if it finds otherwise. Better way?
970 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
972 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
973 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
975 def ADJCALLSTACKDOWN :
976 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
977 [(ARMcallseq_start timm:$amt)]>;
980 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
981 [/* For disassembly only; pattern left blank */]>,
982 Requires<[IsARM, HasV6T2]> {
983 let Inst{27-16} = 0b001100100000;
984 let Inst{15-8} = 0b11110000;
985 let Inst{7-0} = 0b00000000;
988 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
989 [/* For disassembly only; pattern left blank */]>,
990 Requires<[IsARM, HasV6T2]> {
991 let Inst{27-16} = 0b001100100000;
992 let Inst{15-8} = 0b11110000;
993 let Inst{7-0} = 0b00000001;
996 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
997 [/* For disassembly only; pattern left blank */]>,
998 Requires<[IsARM, HasV6T2]> {
999 let Inst{27-16} = 0b001100100000;
1000 let Inst{15-8} = 0b11110000;
1001 let Inst{7-0} = 0b00000010;
1004 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
1005 [/* For disassembly only; pattern left blank */]>,
1006 Requires<[IsARM, HasV6T2]> {
1007 let Inst{27-16} = 0b001100100000;
1008 let Inst{15-8} = 0b11110000;
1009 let Inst{7-0} = 0b00000011;
1012 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
1014 [/* For disassembly only; pattern left blank */]>,
1015 Requires<[IsARM, HasV6]> {
1020 let Inst{15-12} = Rd;
1021 let Inst{19-16} = Rn;
1022 let Inst{27-20} = 0b01101000;
1023 let Inst{7-4} = 0b1011;
1024 let Inst{11-8} = 0b1111;
1027 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1028 [/* For disassembly only; pattern left blank */]>,
1029 Requires<[IsARM, HasV6T2]> {
1030 let Inst{27-16} = 0b001100100000;
1031 let Inst{15-8} = 0b11110000;
1032 let Inst{7-0} = 0b00000100;
1035 // The i32imm operand $val can be used by a debugger to store more information
1036 // about the breakpoint.
1037 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
1038 [/* For disassembly only; pattern left blank */]>,
1041 let Inst{3-0} = val{3-0};
1042 let Inst{19-8} = val{15-4};
1043 let Inst{27-20} = 0b00010010;
1044 let Inst{7-4} = 0b0111;
1047 // Change Processor State is a system instruction -- for disassembly only.
1048 // The singleton $opt operand contains the following information:
1049 // opt{4-0} = mode from Inst{4-0}
1050 // opt{5} = changemode from Inst{17}
1051 // opt{8-6} = AIF from Inst{8-6}
1052 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
1053 // FIXME: Integrated assembler will need these split out.
1054 def CPS : AXI<(outs), (ins cps_opt:$opt), MiscFrm, NoItinerary, "cps$opt",
1055 [/* For disassembly only; pattern left blank */]>,
1057 let Inst{31-28} = 0b1111;
1058 let Inst{27-20} = 0b00010000;
1063 // Preload signals the memory system of possible future data/instruction access.
1064 // These are for disassembly only.
1065 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1067 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1068 !strconcat(opc, "\t$addr"),
1069 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1072 let Inst{31-26} = 0b111101;
1073 let Inst{25} = 0; // 0 for immediate form
1074 let Inst{24} = data;
1075 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1076 let Inst{22} = read;
1077 let Inst{21-20} = 0b01;
1078 let Inst{19-16} = addr{16-13}; // Rn
1079 let Inst{15-12} = Rt;
1080 let Inst{11-0} = addr{11-0}; // imm12
1083 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1084 !strconcat(opc, "\t$shift"),
1085 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1088 let Inst{31-26} = 0b111101;
1089 let Inst{25} = 1; // 1 for register form
1090 let Inst{24} = data;
1091 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1092 let Inst{22} = read;
1093 let Inst{21-20} = 0b01;
1094 let Inst{19-16} = shift{16-13}; // Rn
1095 let Inst{11-0} = shift{11-0};
1099 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1100 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1101 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1103 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1105 [/* For disassembly only; pattern left blank */]>,
1108 let Inst{31-10} = 0b1111000100000001000000;
1113 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1114 [/* For disassembly only; pattern left blank */]>,
1115 Requires<[IsARM, HasV7]> {
1117 let Inst{27-4} = 0b001100100000111100001111;
1118 let Inst{3-0} = opt;
1121 // A5.4 Permanently UNDEFINED instructions.
1122 let isBarrier = 1, isTerminator = 1 in
1123 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1126 let Inst = 0xe7ffdefe;
1129 // Address computation and loads and stores in PIC mode.
1130 let isNotDuplicable = 1 in {
1131 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1132 Size4Bytes, IIC_iALUr,
1133 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1135 let AddedComplexity = 10 in {
1136 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1137 Size4Bytes, IIC_iLoad_r,
1138 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1140 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1141 Size4Bytes, IIC_iLoad_bh_r,
1142 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1144 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1145 Size4Bytes, IIC_iLoad_bh_r,
1146 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1148 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1149 Size4Bytes, IIC_iLoad_bh_r,
1150 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1152 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1153 Size4Bytes, IIC_iLoad_bh_r,
1154 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1156 let AddedComplexity = 10 in {
1157 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1158 Size4Bytes, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1160 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1161 Size4Bytes, IIC_iStore_bh_r, [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
1163 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1164 Size4Bytes, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1166 } // isNotDuplicable = 1
1169 // LEApcrel - Load a pc-relative address into a register without offending the
1171 let neverHasSideEffects = 1 in {
1172 let isReMaterializable = 1 in
1173 // FIXME: We want one cannonical LEApcrel instruction and to express one or
1174 // both of these as pseudo-instructions that get expanded to it.
1175 def LEApcrel : AXI1<0, (outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1177 "adr$p\t$Rd, #$label", []>;
1179 } // neverHasSideEffects
1180 def LEApcrelJT : AXI1<0b0100, (outs GPR:$Rd),
1181 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1183 "adr$p\t$Rd, #${label}_${id}", []> {
1186 let Inst{31-28} = p;
1187 let Inst{27-25} = 0b001;
1189 let Inst{19-16} = 0b1111;
1190 let Inst{15-12} = Rd;
1191 // FIXME: Add label encoding/fixup
1194 //===----------------------------------------------------------------------===//
1195 // Control Flow Instructions.
1198 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1200 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1201 "bx", "\tlr", [(ARMretflag)]>,
1202 Requires<[IsARM, HasV4T]> {
1203 let Inst{27-0} = 0b0001001011111111111100011110;
1207 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1208 "mov", "\tpc, lr", [(ARMretflag)]>,
1209 Requires<[IsARM, NoV4T]> {
1210 let Inst{27-0} = 0b0001101000001111000000001110;
1214 // Indirect branches
1215 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1217 def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1218 [(brind GPR:$dst)]>,
1219 Requires<[IsARM, HasV4T]> {
1221 let Inst{31-4} = 0b1110000100101111111111110001;
1222 let Inst{3-0} = dst;
1226 def MOVPCRX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "mov\tpc, $dst",
1227 [(brind GPR:$dst)]>,
1228 Requires<[IsARM, NoV4T]> {
1230 let Inst{31-4} = 0b1110000110100000111100000000;
1231 let Inst{3-0} = dst;
1235 // All calls clobber the non-callee saved registers. SP is marked as
1236 // a use to prevent stack-pointer assignments that appear immediately
1237 // before calls from potentially appearing dead.
1239 // On non-Darwin platforms R9 is callee-saved.
1240 Defs = [R0, R1, R2, R3, R12, LR,
1241 D0, D1, D2, D3, D4, D5, D6, D7,
1242 D16, D17, D18, D19, D20, D21, D22, D23,
1243 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1245 def BL : ABXI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1246 IIC_Br, "bl\t$func",
1247 [(ARMcall tglobaladdr:$func)]>,
1248 Requires<[IsARM, IsNotDarwin]> {
1249 let Inst{31-28} = 0b1110;
1251 let Inst{23-0} = func;
1254 def BL_pred : ABI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1255 IIC_Br, "bl", "\t$func",
1256 [(ARMcall_pred tglobaladdr:$func)]>,
1257 Requires<[IsARM, IsNotDarwin]> {
1259 let Inst{23-0} = func;
1263 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1264 IIC_Br, "blx\t$func",
1265 [(ARMcall GPR:$func)]>,
1266 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1268 let Inst{31-4} = 0b1110000100101111111111110011;
1269 let Inst{3-0} = func;
1273 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1274 // FIXME: x2 insn patterns like this need to be pseudo instructions.
1275 def BX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1276 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
1277 [(ARMcall_nolink tGPR:$func)]>,
1278 Requires<[IsARM, HasV4T, IsNotDarwin]> {
1280 let Inst{27-4} = 0b000100101111111111110001;
1281 let Inst{3-0} = func;
1285 def BMOVPCRX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1286 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
1287 [(ARMcall_nolink tGPR:$func)]>,
1288 Requires<[IsARM, NoV4T, IsNotDarwin]> {
1290 let Inst{27-4} = 0b000110100000111100000000;
1291 let Inst{3-0} = func;
1296 // On Darwin R9 is call-clobbered.
1297 // R7 is marked as a use to prevent frame-pointer assignments from being
1298 // moved above / below calls.
1299 Defs = [R0, R1, R2, R3, R9, R12, LR,
1300 D0, D1, D2, D3, D4, D5, D6, D7,
1301 D16, D17, D18, D19, D20, D21, D22, D23,
1302 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1303 Uses = [R7, SP] in {
1304 def BLr9 : ABXI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1305 IIC_Br, "bl\t$func",
1306 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
1307 let Inst{31-28} = 0b1110;
1309 let Inst{23-0} = func;
1312 def BLr9_pred : ABI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1313 IIC_Br, "bl", "\t$func",
1314 [(ARMcall_pred tglobaladdr:$func)]>,
1315 Requires<[IsARM, IsDarwin]> {
1317 let Inst{23-0} = func;
1321 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1322 IIC_Br, "blx\t$func",
1323 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
1325 let Inst{31-4} = 0b1110000100101111111111110011;
1326 let Inst{3-0} = func;
1330 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1331 def BXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1332 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
1333 [(ARMcall_nolink tGPR:$func)]>,
1334 Requires<[IsARM, HasV4T, IsDarwin]> {
1336 let Inst{27-4} = 0b000100101111111111110001;
1337 let Inst{3-0} = func;
1341 def BMOVPCRXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1342 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
1343 [(ARMcall_nolink tGPR:$func)]>,
1344 Requires<[IsARM, NoV4T, IsDarwin]> {
1346 let Inst{27-4} = 0b000110100000111100000000;
1347 let Inst{3-0} = func;
1353 // FIXME: These should probably be xformed into the non-TC versions of the
1354 // instructions as part of MC lowering.
1355 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1357 let Defs = [R0, R1, R2, R3, R9, R12,
1358 D0, D1, D2, D3, D4, D5, D6, D7,
1359 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1360 D27, D28, D29, D30, D31, PC],
1362 def TCRETURNdi : AInoP<(outs), (ins i32imm:$dst, variable_ops),
1364 "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
1366 def TCRETURNri : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
1368 "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
1370 def TAILJMPd : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1371 IIC_Br, "b\t$dst @ TAILCALL",
1372 []>, Requires<[IsDarwin]>;
1374 def TAILJMPdt: ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1375 IIC_Br, "b.w\t$dst @ TAILCALL",
1376 []>, Requires<[IsDarwin]>;
1378 def TAILJMPr : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1379 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1380 []>, Requires<[IsDarwin]> {
1382 let Inst{31-4} = 0b1110000100101111111111110001;
1383 let Inst{3-0} = dst;
1387 // Non-Darwin versions (the difference is R9).
1388 let Defs = [R0, R1, R2, R3, R12,
1389 D0, D1, D2, D3, D4, D5, D6, D7,
1390 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1391 D27, D28, D29, D30, D31, PC],
1393 def TCRETURNdiND : AInoP<(outs), (ins i32imm:$dst, variable_ops),
1395 "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
1397 def TCRETURNriND : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
1399 "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
1401 def TAILJMPdND : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1402 IIC_Br, "b\t$dst @ TAILCALL",
1403 []>, Requires<[IsARM, IsNotDarwin]>;
1405 def TAILJMPdNDt : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1406 IIC_Br, "b.w\t$dst @ TAILCALL",
1407 []>, Requires<[IsThumb, IsNotDarwin]>;
1409 def TAILJMPrND : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1410 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1411 []>, Requires<[IsNotDarwin]> {
1413 let Inst{31-4} = 0b1110000100101111111111110001;
1414 let Inst{3-0} = dst;
1419 let isBranch = 1, isTerminator = 1 in {
1420 // B is "predicable" since it can be xformed into a Bcc.
1421 let isBarrier = 1 in {
1422 let isPredicable = 1 in
1423 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
1424 "b\t$target", [(br bb:$target)]> {
1426 let Inst{31-28} = 0b1110;
1427 let Inst{23-0} = target;
1430 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1431 def BR_JTr : ARMPseudoInst<(outs),
1432 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1433 SizeSpecial, IIC_Br,
1434 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1435 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1436 // into i12 and rs suffixed versions.
1437 def BR_JTm : ARMPseudoInst<(outs),
1438 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1439 SizeSpecial, IIC_Br,
1440 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1442 def BR_JTadd : ARMPseudoInst<(outs),
1443 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1444 SizeSpecial, IIC_Br,
1445 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1447 } // isNotDuplicable = 1, isIndirectBranch = 1
1450 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1451 // a two-value operand where a dag node expects two operands. :(
1452 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
1453 IIC_Br, "b", "\t$target",
1454 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1456 let Inst{23-0} = target;
1460 // Branch and Exchange Jazelle -- for disassembly only
1461 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1462 [/* For disassembly only; pattern left blank */]> {
1463 let Inst{23-20} = 0b0010;
1464 //let Inst{19-8} = 0xfff;
1465 let Inst{7-4} = 0b0010;
1468 // Secure Monitor Call is a system instruction -- for disassembly only
1469 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1470 [/* For disassembly only; pattern left blank */]> {
1472 let Inst{23-4} = 0b01100000000000000111;
1473 let Inst{3-0} = opt;
1476 // Supervisor Call (Software Interrupt) -- for disassembly only
1477 let isCall = 1, Uses = [SP] in {
1478 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1479 [/* For disassembly only; pattern left blank */]> {
1481 let Inst{23-0} = svc;
1485 // Store Return State is a system instruction -- for disassembly only
1486 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1487 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1488 NoItinerary, "srs${amode}\tsp!, $mode",
1489 [/* For disassembly only; pattern left blank */]> {
1490 let Inst{31-28} = 0b1111;
1491 let Inst{22-20} = 0b110; // W = 1
1494 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1495 NoItinerary, "srs${amode}\tsp, $mode",
1496 [/* For disassembly only; pattern left blank */]> {
1497 let Inst{31-28} = 0b1111;
1498 let Inst{22-20} = 0b100; // W = 0
1501 // Return From Exception is a system instruction -- for disassembly only
1502 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1503 NoItinerary, "rfe${amode}\t$base!",
1504 [/* For disassembly only; pattern left blank */]> {
1505 let Inst{31-28} = 0b1111;
1506 let Inst{22-20} = 0b011; // W = 1
1509 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1510 NoItinerary, "rfe${amode}\t$base",
1511 [/* For disassembly only; pattern left blank */]> {
1512 let Inst{31-28} = 0b1111;
1513 let Inst{22-20} = 0b001; // W = 0
1515 } // isCodeGenOnly = 1
1517 //===----------------------------------------------------------------------===//
1518 // Load / store Instructions.
1524 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1525 UnOpFrag<(load node:$Src)>>;
1526 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1527 UnOpFrag<(zextloadi8 node:$Src)>>;
1528 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1529 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1530 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1531 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1533 // Special LDR for loads from non-pc-relative constpools.
1534 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1535 isReMaterializable = 1 in
1536 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1537 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
1541 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1542 let Inst{19-16} = 0b1111;
1543 let Inst{15-12} = Rt;
1544 let Inst{11-0} = addr{11-0}; // imm12
1547 // Loads with zero extension
1548 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1549 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
1550 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
1552 // Loads with sign extension
1553 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1554 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
1555 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
1557 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1558 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
1559 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
1561 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
1562 isCodeGenOnly = 1 in { // $dst2 doesn't exist in asmstring?
1563 // FIXME: $dst2 isn't in the asm string as it's implied by $Rd (dst2 = Rd+1)
1564 // how to represent that such that tblgen is happy and we don't
1565 // mark this codegen only?
1567 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
1568 (ins addrmode3:$addr), LdMiscFrm,
1569 IIC_iLoad_d_r, "ldrd", "\t$Rd, $addr",
1570 []>, Requires<[IsARM, HasV5TE]>;
1574 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
1575 def _PRE : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1576 (ins addrmode2:$addr), IndexModePre, LdFrm, itin,
1577 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1579 // {13} 1 == Rm, 0 == imm12
1583 let Inst{25} = addr{13};
1584 let Inst{23} = addr{12};
1585 let Inst{19-16} = addr{17-14};
1586 let Inst{11-0} = addr{11-0};
1588 def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1589 (ins GPR:$Rn, am2offset:$offset),
1590 IndexModePost, LdFrm, itin,
1591 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1592 // {13} 1 == Rm, 0 == imm12
1597 let Inst{25} = offset{13};
1598 let Inst{23} = offset{12};
1599 let Inst{19-16} = Rn;
1600 let Inst{11-0} = offset{11-0};
1604 let mayLoad = 1, neverHasSideEffects = 1 in {
1605 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
1606 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
1609 multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
1610 def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1611 (ins addrmode3:$addr), IndexModePre,
1613 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1615 let Inst{23} = addr{8}; // U bit
1616 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1617 let Inst{19-16} = addr{12-9}; // Rn
1618 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1619 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1621 def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1622 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1624 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1627 let Inst{23} = offset{8}; // U bit
1628 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1629 let Inst{19-16} = Rn;
1630 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1631 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1635 let mayLoad = 1, neverHasSideEffects = 1 in {
1636 defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
1637 defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
1638 defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
1639 let hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1640 defm LDRD : AI3_ldridx<0b1101, 0, "ldrd", IIC_iLoad_d_ru>;
1641 } // mayLoad = 1, neverHasSideEffects = 1
1643 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1644 let mayLoad = 1, neverHasSideEffects = 1 in {
1645 def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$dst, GPR:$base_wb),
1646 (ins GPR:$base, am2offset:$offset), IndexModeNone,
1647 LdFrm, IIC_iLoad_ru,
1648 "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1649 let Inst{21} = 1; // overwrite
1651 def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1652 (ins GPR:$base, am2offset:$offset), IndexModeNone,
1653 LdFrm, IIC_iLoad_bh_ru,
1654 "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1655 let Inst{21} = 1; // overwrite
1657 def LDRSBT : AI3ldstidx<0b1101, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1658 (ins GPR:$base, am3offset:$offset), IndexModePost,
1659 LdMiscFrm, IIC_iLoad_bh_ru,
1660 "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1661 let Inst{21} = 1; // overwrite
1663 def LDRHT : AI3ldstidx<0b1011, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1664 (ins GPR:$base, am3offset:$offset), IndexModePost,
1665 LdMiscFrm, IIC_iLoad_bh_ru,
1666 "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1667 let Inst{21} = 1; // overwrite
1669 def LDRSHT : AI3ldstidx<0b1111, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1670 (ins GPR:$base, am3offset:$offset), IndexModePost,
1671 LdMiscFrm, IIC_iLoad_bh_ru,
1672 "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1673 let Inst{21} = 1; // overwrite
1679 // Stores with truncate
1680 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
1681 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
1682 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
1685 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
1686 isCodeGenOnly = 1 in // $src2 doesn't exist in asm string
1687 def STRD : AI3str<0b1111, (outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
1688 StMiscFrm, IIC_iStore_d_r,
1689 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
1692 def STR_PRE : AI2stridx<0, 1, (outs GPR:$Rn_wb),
1693 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1694 IndexModePre, StFrm, IIC_iStore_ru,
1695 "str", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1697 (pre_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1699 def STR_POST : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1700 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1701 IndexModePost, StFrm, IIC_iStore_ru,
1702 "str", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1704 (post_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1706 def STRB_PRE : AI2stridx<1, 1, (outs GPR:$Rn_wb),
1707 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1708 IndexModePre, StFrm, IIC_iStore_bh_ru,
1709 "strb", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1710 [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
1711 GPR:$Rn, am2offset:$offset))]>;
1712 def STRB_POST: AI2stridx<1, 0, (outs GPR:$Rn_wb),
1713 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1714 IndexModePost, StFrm, IIC_iStore_bh_ru,
1715 "strb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1716 [(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
1717 GPR:$Rn, am2offset:$offset))]>;
1719 def STRH_PRE : AI3stridx<0b1011, 0, 1, (outs GPR:$Rn_wb),
1720 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1721 IndexModePre, StMiscFrm, IIC_iStore_ru,
1722 "strh", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1724 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
1726 def STRH_POST: AI3stridx<0b1011, 0, 0, (outs GPR:$Rn_wb),
1727 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1728 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
1729 "strh", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1730 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
1731 GPR:$Rn, am3offset:$offset))]>;
1733 // For disassembly only
1734 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1735 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1736 StMiscFrm, IIC_iStore_d_ru,
1737 "strd", "\t$src1, $src2, [$base, $offset]!",
1738 "$base = $base_wb", []>;
1740 // For disassembly only
1741 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1742 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1743 StMiscFrm, IIC_iStore_d_ru,
1744 "strd", "\t$src1, $src2, [$base], $offset",
1745 "$base = $base_wb", []>;
1747 // STRT, STRBT, and STRHT are for disassembly only.
1749 def STRT : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1750 (ins GPR:$Rt, GPR:$Rn,am2offset:$offset),
1751 IndexModeNone, StFrm, IIC_iStore_ru,
1752 "strt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1753 [/* For disassembly only; pattern left blank */]> {
1754 let Inst{21} = 1; // overwrite
1757 def STRBT : AI2stridx<1, 0, (outs GPR:$Rn_wb),
1758 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1759 IndexModeNone, StFrm, IIC_iStore_bh_ru,
1760 "strbt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1761 [/* For disassembly only; pattern left blank */]> {
1762 let Inst{21} = 1; // overwrite
1765 def STRHT: AI3sthpo<(outs GPR:$base_wb),
1766 (ins GPR:$src, GPR:$base,am3offset:$offset),
1767 StMiscFrm, IIC_iStore_bh_ru,
1768 "strht", "\t$src, [$base], $offset", "$base = $base_wb",
1769 [/* For disassembly only; pattern left blank */]> {
1770 let Inst{21} = 1; // overwrite
1773 //===----------------------------------------------------------------------===//
1774 // Load / store multiple Instructions.
1777 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
1778 InstrItinClass itin, InstrItinClass itin_upd> {
1780 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1781 IndexModeNone, f, itin,
1782 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
1783 let Inst{24-23} = 0b01; // Increment After
1784 let Inst{21} = 0; // No writeback
1785 let Inst{20} = L_bit;
1788 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1789 IndexModeUpd, f, itin_upd,
1790 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1791 let Inst{24-23} = 0b01; // Increment After
1792 let Inst{21} = 1; // Writeback
1793 let Inst{20} = L_bit;
1796 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1797 IndexModeNone, f, itin,
1798 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
1799 let Inst{24-23} = 0b00; // Decrement After
1800 let Inst{21} = 0; // No writeback
1801 let Inst{20} = L_bit;
1804 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1805 IndexModeUpd, f, itin_upd,
1806 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1807 let Inst{24-23} = 0b00; // Decrement After
1808 let Inst{21} = 1; // Writeback
1809 let Inst{20} = L_bit;
1812 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1813 IndexModeNone, f, itin,
1814 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
1815 let Inst{24-23} = 0b10; // Decrement Before
1816 let Inst{21} = 0; // No writeback
1817 let Inst{20} = L_bit;
1820 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1821 IndexModeUpd, f, itin_upd,
1822 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1823 let Inst{24-23} = 0b10; // Decrement Before
1824 let Inst{21} = 1; // Writeback
1825 let Inst{20} = L_bit;
1828 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1829 IndexModeNone, f, itin,
1830 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
1831 let Inst{24-23} = 0b11; // Increment Before
1832 let Inst{21} = 0; // No writeback
1833 let Inst{20} = L_bit;
1836 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1837 IndexModeUpd, f, itin_upd,
1838 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1839 let Inst{24-23} = 0b11; // Increment Before
1840 let Inst{21} = 1; // Writeback
1841 let Inst{20} = L_bit;
1845 let neverHasSideEffects = 1 in {
1847 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1848 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
1850 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1851 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
1853 } // neverHasSideEffects
1855 // Load / Store Multiple Mnemnoic Aliases
1856 def : MnemonicAlias<"ldm", "ldmia">;
1857 def : MnemonicAlias<"stm", "stmia">;
1859 // FIXME: remove when we have a way to marking a MI with these properties.
1860 // FIXME: Should pc be an implicit operand like PICADD, etc?
1861 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1862 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1863 def LDMIA_RET : AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
1864 reglist:$regs, variable_ops),
1865 IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr,
1866 "ldmia${p}\t$Rn!, $regs",
1868 let Inst{24-23} = 0b01; // Increment After
1869 let Inst{21} = 1; // Writeback
1870 let Inst{20} = 1; // Load
1873 //===----------------------------------------------------------------------===//
1874 // Move Instructions.
1877 let neverHasSideEffects = 1 in
1878 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
1879 "mov", "\t$Rd, $Rm", []>, UnaryDP {
1883 let Inst{11-4} = 0b00000000;
1886 let Inst{15-12} = Rd;
1889 // A version for the smaller set of tail call registers.
1890 let neverHasSideEffects = 1 in
1891 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
1892 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
1896 let Inst{11-4} = 0b00000000;
1899 let Inst{15-12} = Rd;
1902 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
1903 DPSoRegFrm, IIC_iMOVsr,
1904 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
1908 let Inst{15-12} = Rd;
1909 let Inst{11-0} = src;
1913 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1914 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
1915 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
1919 let Inst{15-12} = Rd;
1920 let Inst{19-16} = 0b0000;
1921 let Inst{11-0} = imm;
1924 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1925 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins movt_imm:$imm),
1927 "movw", "\t$Rd, $imm",
1928 [(set GPR:$Rd, imm0_65535:$imm)]>,
1929 Requires<[IsARM, HasV6T2]>, UnaryDP {
1932 let Inst{15-12} = Rd;
1933 let Inst{11-0} = imm{11-0};
1934 let Inst{19-16} = imm{15-12};
1939 let Constraints = "$src = $Rd" in
1940 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, movt_imm:$imm),
1942 "movt", "\t$Rd, $imm",
1944 (or (and GPR:$src, 0xffff),
1945 lo16AllZero:$imm))]>, UnaryDP,
1946 Requires<[IsARM, HasV6T2]> {
1949 let Inst{15-12} = Rd;
1950 let Inst{11-0} = imm{11-0};
1951 let Inst{19-16} = imm{15-12};
1956 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
1957 Requires<[IsARM, HasV6T2]>;
1959 let Uses = [CPSR] in
1960 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
1961 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
1964 // These aren't really mov instructions, but we have to define them this way
1965 // due to flag operands.
1967 let Defs = [CPSR] in {
1968 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1969 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
1971 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1972 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
1976 //===----------------------------------------------------------------------===//
1977 // Extend Instructions.
1982 defm SXTB : AI_ext_rrot<0b01101010,
1983 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
1984 defm SXTH : AI_ext_rrot<0b01101011,
1985 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
1987 defm SXTAB : AI_exta_rrot<0b01101010,
1988 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1989 defm SXTAH : AI_exta_rrot<0b01101011,
1990 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1992 // For disassembly only
1993 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
1995 // For disassembly only
1996 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2000 let AddedComplexity = 16 in {
2001 defm UXTB : AI_ext_rrot<0b01101110,
2002 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2003 defm UXTH : AI_ext_rrot<0b01101111,
2004 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2005 defm UXTB16 : AI_ext_rrot<0b01101100,
2006 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2008 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2009 // The transformation should probably be done as a combiner action
2010 // instead so we can include a check for masking back in the upper
2011 // eight bits of the source into the lower eight bits of the result.
2012 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2013 // (UXTB16r_rot GPR:$Src, 24)>;
2014 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2015 (UXTB16r_rot GPR:$Src, 8)>;
2017 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2018 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2019 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2020 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2023 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2024 // For disassembly only
2025 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2028 def SBFX : I<(outs GPR:$Rd),
2029 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2030 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2031 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2032 Requires<[IsARM, HasV6T2]> {
2037 let Inst{27-21} = 0b0111101;
2038 let Inst{6-4} = 0b101;
2039 let Inst{20-16} = width;
2040 let Inst{15-12} = Rd;
2041 let Inst{11-7} = lsb;
2045 def UBFX : I<(outs GPR:$Rd),
2046 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2047 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2048 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2049 Requires<[IsARM, HasV6T2]> {
2054 let Inst{27-21} = 0b0111111;
2055 let Inst{6-4} = 0b101;
2056 let Inst{20-16} = width;
2057 let Inst{15-12} = Rd;
2058 let Inst{11-7} = lsb;
2062 //===----------------------------------------------------------------------===//
2063 // Arithmetic Instructions.
2066 defm ADD : AsI1_bin_irs<0b0100, "add",
2067 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2068 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
2069 defm SUB : AsI1_bin_irs<0b0010, "sub",
2070 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2071 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
2073 // ADD and SUB with 's' bit set.
2074 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
2075 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2076 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
2077 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
2078 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2079 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
2081 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
2082 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
2083 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
2084 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
2085 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
2086 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
2087 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
2088 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
2090 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2091 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
2092 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
2097 let Inst{15-12} = Rd;
2098 let Inst{19-16} = Rn;
2099 let Inst{11-0} = imm;
2102 // The reg/reg form is only defined for the disassembler; for codegen it is
2103 // equivalent to SUBrr.
2104 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2105 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
2106 [/* For disassembly only; pattern left blank */]> {
2110 let Inst{11-4} = 0b00000000;
2113 let Inst{15-12} = Rd;
2114 let Inst{19-16} = Rn;
2117 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2118 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2119 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
2124 let Inst{11-0} = shift;
2125 let Inst{15-12} = Rd;
2126 let Inst{19-16} = Rn;
2129 // RSB with 's' bit set.
2130 let Defs = [CPSR] in {
2131 def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2132 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
2133 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
2139 let Inst{15-12} = Rd;
2140 let Inst{19-16} = Rn;
2141 let Inst{11-0} = imm;
2143 def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2144 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
2145 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
2151 let Inst{11-0} = shift;
2152 let Inst{15-12} = Rd;
2153 let Inst{19-16} = Rn;
2157 let Uses = [CPSR] in {
2158 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2159 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2160 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2166 let Inst{15-12} = Rd;
2167 let Inst{19-16} = Rn;
2168 let Inst{11-0} = imm;
2170 // The reg/reg form is only defined for the disassembler; for codegen it is
2171 // equivalent to SUBrr.
2172 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2173 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2174 [/* For disassembly only; pattern left blank */]> {
2178 let Inst{11-4} = 0b00000000;
2181 let Inst{15-12} = Rd;
2182 let Inst{19-16} = Rn;
2184 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2185 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2186 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2192 let Inst{11-0} = shift;
2193 let Inst{15-12} = Rd;
2194 let Inst{19-16} = Rn;
2198 // FIXME: Allow these to be predicated.
2199 let Defs = [CPSR], Uses = [CPSR] in {
2200 def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2201 DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
2202 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2209 let Inst{15-12} = Rd;
2210 let Inst{19-16} = Rn;
2211 let Inst{11-0} = imm;
2213 def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2214 DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
2215 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2222 let Inst{11-0} = shift;
2223 let Inst{15-12} = Rd;
2224 let Inst{19-16} = Rn;
2228 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2229 // The assume-no-carry-in form uses the negation of the input since add/sub
2230 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2231 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2233 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2234 (SUBri GPR:$src, so_imm_neg:$imm)>;
2235 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2236 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2237 // The with-carry-in form matches bitwise not instead of the negation.
2238 // Effectively, the inverse interpretation of the carry flag already accounts
2239 // for part of the negation.
2240 def : ARMPat<(adde GPR:$src, so_imm_not:$imm),
2241 (SBCri GPR:$src, so_imm_not:$imm)>;
2243 // Note: These are implemented in C++ code, because they have to generate
2244 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2246 // (mul X, 2^n+1) -> (add (X << n), X)
2247 // (mul X, 2^n-1) -> (rsb X, (X << n))
2249 // ARM Arithmetic Instruction -- for disassembly only
2250 // GPR:$dst = GPR:$a op GPR:$b
2251 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2252 list<dag> pattern = [/* For disassembly only; pattern left blank */]>
2253 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iALUr,
2254 opc, "\t$Rd, $Rn, $Rm", pattern> {
2258 let Inst{27-20} = op27_20;
2259 let Inst{11-4} = op11_4;
2260 let Inst{19-16} = Rn;
2261 let Inst{15-12} = Rd;
2265 // Saturating add/subtract -- for disassembly only
2267 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2268 [(set GPR:$Rd, (int_arm_qadd GPR:$Rn, GPR:$Rm))]>;
2269 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2270 [(set GPR:$Rd, (int_arm_qsub GPR:$Rn, GPR:$Rm))]>;
2271 def QDADD : AAI<0b00010100, 0b00000101, "qdadd">;
2272 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub">;
2274 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2275 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2276 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2277 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2278 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2279 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2280 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2281 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2282 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2283 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2284 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2285 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2287 // Signed/Unsigned add/subtract -- for disassembly only
2289 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2290 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2291 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2292 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2293 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2294 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2295 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2296 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2297 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2298 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2299 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2300 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2302 // Signed/Unsigned halving add/subtract -- for disassembly only
2304 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2305 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2306 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2307 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2308 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2309 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2310 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2311 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2312 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2313 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2314 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2315 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2317 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2319 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2320 MulFrm /* for convenience */, NoItinerary, "usad8",
2321 "\t$Rd, $Rn, $Rm", []>,
2322 Requires<[IsARM, HasV6]> {
2326 let Inst{27-20} = 0b01111000;
2327 let Inst{15-12} = 0b1111;
2328 let Inst{7-4} = 0b0001;
2329 let Inst{19-16} = Rd;
2330 let Inst{11-8} = Rm;
2333 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2334 MulFrm /* for convenience */, NoItinerary, "usada8",
2335 "\t$Rd, $Rn, $Rm, $Ra", []>,
2336 Requires<[IsARM, HasV6]> {
2341 let Inst{27-20} = 0b01111000;
2342 let Inst{7-4} = 0b0001;
2343 let Inst{19-16} = Rd;
2344 let Inst{15-12} = Ra;
2345 let Inst{11-8} = Rm;
2349 // Signed/Unsigned saturate -- for disassembly only
2351 def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2352 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2353 [/* For disassembly only; pattern left blank */]> {
2358 let Inst{27-21} = 0b0110101;
2359 let Inst{5-4} = 0b01;
2360 let Inst{20-16} = sat_imm;
2361 let Inst{15-12} = Rd;
2362 let Inst{11-7} = sh{7-3};
2363 let Inst{6} = sh{0};
2367 def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm,
2368 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2369 [/* For disassembly only; pattern left blank */]> {
2373 let Inst{27-20} = 0b01101010;
2374 let Inst{11-4} = 0b11110011;
2375 let Inst{15-12} = Rd;
2376 let Inst{19-16} = sat_imm;
2380 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2381 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2382 [/* For disassembly only; pattern left blank */]> {
2387 let Inst{27-21} = 0b0110111;
2388 let Inst{5-4} = 0b01;
2389 let Inst{15-12} = Rd;
2390 let Inst{11-7} = sh{7-3};
2391 let Inst{6} = sh{0};
2392 let Inst{20-16} = sat_imm;
2396 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2397 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2398 [/* For disassembly only; pattern left blank */]> {
2402 let Inst{27-20} = 0b01101110;
2403 let Inst{11-4} = 0b11110011;
2404 let Inst{15-12} = Rd;
2405 let Inst{19-16} = sat_imm;
2409 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2410 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2412 //===----------------------------------------------------------------------===//
2413 // Bitwise Instructions.
2416 defm AND : AsI1_bin_irs<0b0000, "and",
2417 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2418 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2419 defm ORR : AsI1_bin_irs<0b1100, "orr",
2420 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2421 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2422 defm EOR : AsI1_bin_irs<0b0001, "eor",
2423 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2424 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2425 defm BIC : AsI1_bin_irs<0b1110, "bic",
2426 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2427 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2429 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2430 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2431 "bfc", "\t$Rd, $imm", "$src = $Rd",
2432 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2433 Requires<[IsARM, HasV6T2]> {
2436 let Inst{27-21} = 0b0111110;
2437 let Inst{6-0} = 0b0011111;
2438 let Inst{15-12} = Rd;
2439 let Inst{11-7} = imm{4-0}; // lsb
2440 let Inst{20-16} = imm{9-5}; // width
2443 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2444 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2445 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2446 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2447 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2448 bf_inv_mask_imm:$imm))]>,
2449 Requires<[IsARM, HasV6T2]> {
2453 let Inst{27-21} = 0b0111110;
2454 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2455 let Inst{15-12} = Rd;
2456 let Inst{11-7} = imm{4-0}; // lsb
2457 let Inst{20-16} = imm{9-5}; // width
2461 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2462 "mvn", "\t$Rd, $Rm",
2463 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2467 let Inst{19-16} = 0b0000;
2468 let Inst{11-4} = 0b00000000;
2469 let Inst{15-12} = Rd;
2472 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2473 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2474 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2478 let Inst{19-16} = 0b0000;
2479 let Inst{15-12} = Rd;
2480 let Inst{11-0} = shift;
2482 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2483 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2484 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2485 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2489 let Inst{19-16} = 0b0000;
2490 let Inst{15-12} = Rd;
2491 let Inst{11-0} = imm;
2494 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2495 (BICri GPR:$src, so_imm_not:$imm)>;
2497 //===----------------------------------------------------------------------===//
2498 // Multiply Instructions.
2500 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2501 string opc, string asm, list<dag> pattern>
2502 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2506 let Inst{19-16} = Rd;
2507 let Inst{11-8} = Rm;
2510 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2511 string opc, string asm, list<dag> pattern>
2512 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2517 let Inst{19-16} = RdHi;
2518 let Inst{15-12} = RdLo;
2519 let Inst{11-8} = Rm;
2523 let isCommutable = 1 in
2524 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2525 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2526 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>;
2528 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2529 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2530 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]> {
2532 let Inst{15-12} = Ra;
2535 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2536 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
2537 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
2538 Requires<[IsARM, HasV6T2]> {
2543 let Inst{19-16} = Rd;
2544 let Inst{15-12} = Ra;
2545 let Inst{11-8} = Rm;
2549 // Extra precision multiplies with low / high results
2551 let neverHasSideEffects = 1 in {
2552 let isCommutable = 1 in {
2553 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2554 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2555 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2557 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2558 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2559 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2562 // Multiply + accumulate
2563 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2564 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2565 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2567 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2568 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2569 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2571 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2572 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2573 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2574 Requires<[IsARM, HasV6]> {
2579 let Inst{19-16} = RdLo;
2580 let Inst{15-12} = RdHi;
2581 let Inst{11-8} = Rm;
2584 } // neverHasSideEffects
2586 // Most significant word multiply
2587 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2588 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2589 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2590 Requires<[IsARM, HasV6]> {
2591 let Inst{15-12} = 0b1111;
2594 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2595 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2596 [/* For disassembly only; pattern left blank */]>,
2597 Requires<[IsARM, HasV6]> {
2598 let Inst{15-12} = 0b1111;
2601 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2602 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2603 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2604 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2605 Requires<[IsARM, HasV6]>;
2607 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2608 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2609 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2610 [/* For disassembly only; pattern left blank */]>,
2611 Requires<[IsARM, HasV6]>;
2613 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2614 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2615 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2616 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2617 Requires<[IsARM, HasV6]>;
2619 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2620 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2621 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2622 [/* For disassembly only; pattern left blank */]>,
2623 Requires<[IsARM, HasV6]>;
2625 multiclass AI_smul<string opc, PatFrag opnode> {
2626 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2627 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2628 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2629 (sext_inreg GPR:$Rm, i16)))]>,
2630 Requires<[IsARM, HasV5TE]>;
2632 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2633 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2634 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2635 (sra GPR:$Rm, (i32 16))))]>,
2636 Requires<[IsARM, HasV5TE]>;
2638 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2639 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2640 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2641 (sext_inreg GPR:$Rm, i16)))]>,
2642 Requires<[IsARM, HasV5TE]>;
2644 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2645 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2646 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2647 (sra GPR:$Rm, (i32 16))))]>,
2648 Requires<[IsARM, HasV5TE]>;
2650 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2651 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2652 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2653 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2654 Requires<[IsARM, HasV5TE]>;
2656 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2657 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2658 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2659 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2660 Requires<[IsARM, HasV5TE]>;
2664 multiclass AI_smla<string opc, PatFrag opnode> {
2665 def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
2666 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2667 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2668 [(set GPR:$Rd, (add GPR:$Ra,
2669 (opnode (sext_inreg GPR:$Rn, i16),
2670 (sext_inreg GPR:$Rm, i16))))]>,
2671 Requires<[IsARM, HasV5TE]>;
2673 def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd),
2674 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2675 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2676 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2677 (sra GPR:$Rm, (i32 16)))))]>,
2678 Requires<[IsARM, HasV5TE]>;
2680 def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd),
2681 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2682 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2683 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2684 (sext_inreg GPR:$Rm, i16))))]>,
2685 Requires<[IsARM, HasV5TE]>;
2687 def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
2688 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2689 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2690 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2691 (sra GPR:$Rm, (i32 16)))))]>,
2692 Requires<[IsARM, HasV5TE]>;
2694 def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd),
2695 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2696 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2697 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2698 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2699 Requires<[IsARM, HasV5TE]>;
2701 def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd),
2702 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2703 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2704 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2705 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2706 Requires<[IsARM, HasV5TE]>;
2709 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2710 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2712 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2713 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2714 (ins GPR:$Rn, GPR:$Rm),
2715 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2716 [/* For disassembly only; pattern left blank */]>,
2717 Requires<[IsARM, HasV5TE]>;
2719 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2720 (ins GPR:$Rn, GPR:$Rm),
2721 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2722 [/* For disassembly only; pattern left blank */]>,
2723 Requires<[IsARM, HasV5TE]>;
2725 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2726 (ins GPR:$Rn, GPR:$Rm),
2727 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2728 [/* For disassembly only; pattern left blank */]>,
2729 Requires<[IsARM, HasV5TE]>;
2731 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2732 (ins GPR:$Rn, GPR:$Rm),
2733 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2734 [/* For disassembly only; pattern left blank */]>,
2735 Requires<[IsARM, HasV5TE]>;
2737 // Helper class for AI_smld -- for disassembly only
2738 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2739 InstrItinClass itin, string opc, string asm>
2740 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2747 let Inst{21-20} = 0b00;
2748 let Inst{22} = long;
2749 let Inst{27-23} = 0b01110;
2750 let Inst{11-8} = Rm;
2753 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2754 InstrItinClass itin, string opc, string asm>
2755 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2757 let Inst{15-12} = 0b1111;
2758 let Inst{19-16} = Rd;
2760 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2761 InstrItinClass itin, string opc, string asm>
2762 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2764 let Inst{15-12} = Ra;
2766 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2767 InstrItinClass itin, string opc, string asm>
2768 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2771 let Inst{19-16} = RdHi;
2772 let Inst{15-12} = RdLo;
2775 multiclass AI_smld<bit sub, string opc> {
2777 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2778 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
2780 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2781 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
2783 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
2784 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2785 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
2787 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
2788 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2789 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
2793 defm SMLA : AI_smld<0, "smla">;
2794 defm SMLS : AI_smld<1, "smls">;
2796 multiclass AI_sdml<bit sub, string opc> {
2798 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2799 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
2800 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2801 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
2804 defm SMUA : AI_sdml<0, "smua">;
2805 defm SMUS : AI_sdml<1, "smus">;
2807 //===----------------------------------------------------------------------===//
2808 // Misc. Arithmetic Instructions.
2811 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
2812 IIC_iUNAr, "clz", "\t$Rd, $Rm",
2813 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
2815 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2816 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
2817 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
2818 Requires<[IsARM, HasV6T2]>;
2820 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2821 IIC_iUNAr, "rev", "\t$Rd, $Rm",
2822 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
2824 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2825 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
2827 (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
2828 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
2829 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
2830 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
2831 Requires<[IsARM, HasV6]>;
2833 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2834 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
2837 (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
2838 (shl GPR:$Rm, (i32 8))), i16))]>,
2839 Requires<[IsARM, HasV6]>;
2841 def lsl_shift_imm : SDNodeXForm<imm, [{
2842 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
2843 return CurDAG->getTargetConstant(Sh, MVT::i32);
2846 def lsl_amt : PatLeaf<(i32 imm), [{
2847 return (N->getZExtValue() < 32);
2850 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
2851 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2852 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2853 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
2854 (and (shl GPR:$Rm, lsl_amt:$sh),
2856 Requires<[IsARM, HasV6]>;
2858 // Alternate cases for PKHBT where identities eliminate some nodes.
2859 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
2860 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
2861 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
2862 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
2864 def asr_shift_imm : SDNodeXForm<imm, [{
2865 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
2866 return CurDAG->getTargetConstant(Sh, MVT::i32);
2869 def asr_amt : PatLeaf<(i32 imm), [{
2870 return (N->getZExtValue() <= 32);
2873 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2874 // will match the pattern below.
2875 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
2876 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2877 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2878 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
2879 (and (sra GPR:$Rm, asr_amt:$sh),
2881 Requires<[IsARM, HasV6]>;
2883 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2884 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2885 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
2886 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
2887 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
2888 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
2889 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
2891 //===----------------------------------------------------------------------===//
2892 // Comparison Instructions...
2895 defm CMP : AI1_cmp_irs<0b1010, "cmp",
2896 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2897 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2899 // FIXME: We have to be careful when using the CMN instruction and comparison
2900 // with 0. One would expect these two pieces of code should give identical
2916 // However, the CMN gives the *opposite* result when r1 is 0. This is because
2917 // the carry flag is set in the CMP case but not in the CMN case. In short, the
2918 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
2919 // value of r0 and the carry bit (because the "carry bit" parameter to
2920 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
2921 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
2922 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
2923 // parameter to AddWithCarry is defined as 0).
2925 // When x is 0 and unsigned:
2929 // ~x + 1 = 0x1 0000 0000
2930 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
2932 // Therefore, we should disable CMN when comparing against zero, until we can
2933 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
2934 // when it's a comparison which doesn't look at the 'carry' flag).
2936 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
2938 // This is related to <rdar://problem/7569620>.
2940 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
2941 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2943 // Note that TST/TEQ don't set all the same flags that CMP does!
2944 defm TST : AI1_cmp_irs<0b1000, "tst",
2945 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2946 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
2947 defm TEQ : AI1_cmp_irs<0b1001, "teq",
2948 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2949 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
2951 defm CMPz : AI1_cmp_irs<0b1010, "cmp",
2952 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2953 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
2954 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
2955 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2956 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2958 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
2959 // (CMNri GPR:$src, so_imm_neg:$imm)>;
2961 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
2962 (CMNzri GPR:$src, so_imm_neg:$imm)>;
2964 // Pseudo i64 compares for some floating point compares.
2965 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
2967 def BCCi64 : PseudoInst<(outs),
2968 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
2970 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
2972 def BCCZi64 : PseudoInst<(outs),
2973 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
2974 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
2975 } // usesCustomInserter
2978 // Conditional moves
2979 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2980 // a two-value operand where a dag node expects two operands. :(
2981 // FIXME: These should all be pseudo-instructions that get expanded to
2982 // the normal MOV instructions. That would fix the dependency on
2983 // special casing them in tblgen.
2984 let neverHasSideEffects = 1 in {
2985 def MOVCCr : AI1<0b1101, (outs GPR:$Rd), (ins GPR:$false, GPR:$Rm), DPFrm,
2986 IIC_iCMOVr, "mov", "\t$Rd, $Rm",
2987 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2988 RegConstraint<"$false = $Rd">, UnaryDP {
2993 let Inst{15-12} = Rd;
2994 let Inst{11-4} = 0b00000000;
2998 def MOVCCs : AI1<0b1101, (outs GPR:$Rd),
2999 (ins GPR:$false, so_reg:$shift), DPSoRegFrm, IIC_iCMOVsr,
3000 "mov", "\t$Rd, $shift",
3001 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
3002 RegConstraint<"$false = $Rd">, UnaryDP {
3007 let Inst{19-16} = 0;
3008 let Inst{15-12} = Rd;
3009 let Inst{11-0} = shift;
3012 let isMoveImm = 1 in
3013 def MOVCCi16 : AI1<0b1000, (outs GPR:$Rd), (ins GPR:$false, movt_imm:$imm),
3015 "movw", "\t$Rd, $imm",
3017 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
3023 let Inst{19-16} = imm{15-12};
3024 let Inst{15-12} = Rd;
3025 let Inst{11-0} = imm{11-0};
3028 let isMoveImm = 1 in
3029 def MOVCCi : AI1<0b1101, (outs GPR:$Rd),
3030 (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi,
3031 "mov", "\t$Rd, $imm",
3032 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3033 RegConstraint<"$false = $Rd">, UnaryDP {
3038 let Inst{19-16} = 0b0000;
3039 let Inst{15-12} = Rd;
3040 let Inst{11-0} = imm;
3043 // Two instruction predicate mov immediate.
3044 let isMoveImm = 1 in
3045 def MOVCCi32imm : PseudoInst<(outs GPR:$Rd),
3046 (ins GPR:$false, i32imm:$src, pred:$p),
3047 IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3049 let isMoveImm = 1 in
3050 def MVNCCi : AI1<0b1111, (outs GPR:$Rd),
3051 (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi,
3052 "mvn", "\t$Rd, $imm",
3053 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3054 RegConstraint<"$false = $Rd">, UnaryDP {
3059 let Inst{19-16} = 0b0000;
3060 let Inst{15-12} = Rd;
3061 let Inst{11-0} = imm;
3063 } // neverHasSideEffects
3065 //===----------------------------------------------------------------------===//
3066 // Atomic operations intrinsics
3069 def memb_opt : Operand<i32> {
3070 let PrintMethod = "printMemBOption";
3073 // memory barriers protect the atomic sequences
3074 let hasSideEffects = 1 in {
3075 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3076 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3077 Requires<[IsARM, HasDB]> {
3079 let Inst{31-4} = 0xf57ff05;
3080 let Inst{3-0} = opt;
3083 def DMB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary,
3084 "mcr", "\tp15, 0, $zero, c7, c10, 5",
3085 [(ARMMemBarrierMCR GPR:$zero)]>,
3086 Requires<[IsARM, HasV6]> {
3087 // FIXME: add encoding
3091 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3093 [/* For disassembly only; pattern left blank */]>,
3094 Requires<[IsARM, HasDB]> {
3096 let Inst{31-4} = 0xf57ff04;
3097 let Inst{3-0} = opt;
3100 // ISB has only full system option -- for disassembly only
3101 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
3102 Requires<[IsARM, HasDB]> {
3103 let Inst{31-4} = 0xf57ff06;
3104 let Inst{3-0} = 0b1111;
3107 let usesCustomInserter = 1 in {
3108 let Uses = [CPSR] in {
3109 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
3110 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3111 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
3112 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
3113 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3114 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
3115 def ATOMIC_LOAD_AND_I8 : PseudoInst<
3116 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3117 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
3118 def ATOMIC_LOAD_OR_I8 : PseudoInst<
3119 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3120 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
3121 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
3122 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3123 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
3124 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
3125 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3126 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
3127 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
3128 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3129 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
3130 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
3131 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3132 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
3133 def ATOMIC_LOAD_AND_I16 : PseudoInst<
3134 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3135 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
3136 def ATOMIC_LOAD_OR_I16 : PseudoInst<
3137 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3138 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
3139 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
3140 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3141 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
3142 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
3143 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3144 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
3145 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
3146 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3147 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
3148 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
3149 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3150 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
3151 def ATOMIC_LOAD_AND_I32 : PseudoInst<
3152 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3153 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
3154 def ATOMIC_LOAD_OR_I32 : PseudoInst<
3155 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3156 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
3157 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
3158 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3159 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
3160 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
3161 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3162 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
3164 def ATOMIC_SWAP_I8 : PseudoInst<
3165 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3166 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3167 def ATOMIC_SWAP_I16 : PseudoInst<
3168 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3169 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3170 def ATOMIC_SWAP_I32 : PseudoInst<
3171 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3172 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3174 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3175 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3176 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3177 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3178 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3179 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3180 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3181 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3182 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3186 let mayLoad = 1 in {
3187 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3188 "ldrexb", "\t$Rt, [$Rn]",
3190 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3191 "ldrexh", "\t$Rt, [$Rn]",
3193 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3194 "ldrex", "\t$Rt, [$Rn]",
3196 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins GPR:$Rn),
3198 "ldrexd", "\t$Rt, $Rt2, [$Rn]",
3202 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3203 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$src, GPR:$Rn),
3205 "strexb", "\t$Rd, $src, [$Rn]",
3207 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3209 "strexh", "\t$Rd, $Rt, [$Rn]",
3211 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3213 "strex", "\t$Rd, $Rt, [$Rn]",
3215 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3216 (ins GPR:$Rt, GPR:$Rt2, GPR:$Rn),
3218 "strexd", "\t$Rd, $Rt, $Rt2, [$Rn]",
3222 // Clear-Exclusive is for disassembly only.
3223 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3224 [/* For disassembly only; pattern left blank */]>,
3225 Requires<[IsARM, HasV7]> {
3226 let Inst{31-0} = 0b11110101011111111111000000011111;
3229 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3230 let mayLoad = 1 in {
3231 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3232 [/* For disassembly only; pattern left blank */]>;
3233 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3234 [/* For disassembly only; pattern left blank */]>;
3237 //===----------------------------------------------------------------------===//
3241 // __aeabi_read_tp preserves the registers r1-r3.
3242 // FIXME: This needs to be a pseudo of some sort so that we can get the
3243 // encoding right, complete with fixup for the aeabi_read_tp function.
3245 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
3246 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
3247 "bl\t__aeabi_read_tp",
3248 [(set R0, ARMthread_pointer)]>;
3251 //===----------------------------------------------------------------------===//
3252 // SJLJ Exception handling intrinsics
3253 // eh_sjlj_setjmp() is an instruction sequence to store the return
3254 // address and save #0 in R0 for the non-longjmp case.
3255 // Since by its nature we may be coming from some other function to get
3256 // here, and we're using the stack frame for the containing function to
3257 // save/restore registers, we can't keep anything live in regs across
3258 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3259 // when we get here from a longjmp(). We force everthing out of registers
3260 // except for our own input by listing the relevant registers in Defs. By
3261 // doing so, we also cause the prologue/epilogue code to actively preserve
3262 // all of the callee-saved resgisters, which is exactly what we want.
3263 // A constant value is passed in $val, and we use the location as a scratch.
3265 // These are pseudo-instructions and are lowered to individual MC-insts, so
3266 // no encoding information is necessary.
3268 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
3269 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
3270 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
3271 D31 ], hasSideEffects = 1, isBarrier = 1 in {
3272 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3274 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3275 Requires<[IsARM, HasVFP2]>;
3279 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
3280 hasSideEffects = 1, isBarrier = 1 in {
3281 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3283 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3284 Requires<[IsARM, NoVFP]>;
3287 // FIXME: Non-Darwin version(s)
3288 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3289 Defs = [ R7, LR, SP ] in {
3290 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
3292 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3293 Requires<[IsARM, IsDarwin]>;
3296 // eh.sjlj.dispatchsetup pseudo-instruction.
3297 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3298 // handled when the pseudo is expanded (which happens before any passes
3299 // that need the instruction size).
3300 let isBarrier = 1, hasSideEffects = 1 in
3301 def Int_eh_sjlj_dispatchsetup :
3302 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
3303 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
3304 Requires<[IsDarwin]>;
3306 //===----------------------------------------------------------------------===//
3307 // Non-Instruction Patterns
3310 // Large immediate handling.
3312 // 32-bit immediate using two piece so_imms or movw + movt.
3313 // This is a single pseudo instruction, the benefit is that it can be remat'd
3314 // as a single unit instead of having to handle reg inputs.
3315 // FIXME: Remove this when we can do generalized remat.
3316 let isReMaterializable = 1, isMoveImm = 1 in
3317 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3318 [(set GPR:$dst, (arm_i32imm:$src))]>,
3321 // ConstantPool, GlobalAddress, and JumpTable
3322 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3323 Requires<[IsARM, DontUseMovt]>;
3324 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3325 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3326 Requires<[IsARM, UseMovt]>;
3327 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3328 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3330 // TODO: add,sub,and, 3-instr forms?
3333 def : ARMPat<(ARMtcret tcGPR:$dst),
3334 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3336 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3337 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3339 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3340 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3342 def : ARMPat<(ARMtcret tcGPR:$dst),
3343 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3345 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3346 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3348 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3349 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3352 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3353 Requires<[IsARM, IsNotDarwin]>;
3354 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3355 Requires<[IsARM, IsDarwin]>;
3357 // zextload i1 -> zextload i8
3358 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3359 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3361 // extload -> zextload
3362 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3363 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3364 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3365 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3367 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3369 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3370 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3373 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3374 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3375 (SMULBB GPR:$a, GPR:$b)>;
3376 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3377 (SMULBB GPR:$a, GPR:$b)>;
3378 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3379 (sra GPR:$b, (i32 16))),
3380 (SMULBT GPR:$a, GPR:$b)>;
3381 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3382 (SMULBT GPR:$a, GPR:$b)>;
3383 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3384 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3385 (SMULTB GPR:$a, GPR:$b)>;
3386 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3387 (SMULTB GPR:$a, GPR:$b)>;
3388 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3390 (SMULWB GPR:$a, GPR:$b)>;
3391 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3392 (SMULWB GPR:$a, GPR:$b)>;
3394 def : ARMV5TEPat<(add GPR:$acc,
3395 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3396 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3397 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3398 def : ARMV5TEPat<(add GPR:$acc,
3399 (mul sext_16_node:$a, sext_16_node:$b)),
3400 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3401 def : ARMV5TEPat<(add GPR:$acc,
3402 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3403 (sra GPR:$b, (i32 16)))),
3404 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3405 def : ARMV5TEPat<(add GPR:$acc,
3406 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3407 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3408 def : ARMV5TEPat<(add GPR:$acc,
3409 (mul (sra GPR:$a, (i32 16)),
3410 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3411 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3412 def : ARMV5TEPat<(add GPR:$acc,
3413 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3414 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3415 def : ARMV5TEPat<(add GPR:$acc,
3416 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3418 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3419 def : ARMV5TEPat<(add GPR:$acc,
3420 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3421 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3423 //===----------------------------------------------------------------------===//
3427 include "ARMInstrThumb.td"
3429 //===----------------------------------------------------------------------===//
3433 include "ARMInstrThumb2.td"
3435 //===----------------------------------------------------------------------===//
3436 // Floating Point Support
3439 include "ARMInstrVFP.td"
3441 //===----------------------------------------------------------------------===//
3442 // Advanced SIMD (NEON) Support
3445 include "ARMInstrNEON.td"
3447 //===----------------------------------------------------------------------===//
3448 // Coprocessor Instructions. For disassembly only.
3451 def CDP : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3452 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3453 NoItinerary, "cdp", "\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3454 [/* For disassembly only; pattern left blank */]> {
3458 def CDP2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3459 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3460 NoItinerary, "cdp2\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3461 [/* For disassembly only; pattern left blank */]> {
3462 let Inst{31-28} = 0b1111;
3466 class ACI<dag oops, dag iops, string opc, string asm>
3467 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
3468 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3469 let Inst{27-25} = 0b110;
3472 multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
3474 def _OFFSET : ACI<(outs),
3475 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3476 opc, "\tp$cop, cr$CRd, $addr"> {
3477 let Inst{31-28} = op31_28;
3478 let Inst{24} = 1; // P = 1
3479 let Inst{21} = 0; // W = 0
3480 let Inst{22} = 0; // D = 0
3481 let Inst{20} = load;
3484 def _PRE : ACI<(outs),
3485 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3486 opc, "\tp$cop, cr$CRd, $addr!"> {
3487 let Inst{31-28} = op31_28;
3488 let Inst{24} = 1; // P = 1
3489 let Inst{21} = 1; // W = 1
3490 let Inst{22} = 0; // D = 0
3491 let Inst{20} = load;
3494 def _POST : ACI<(outs),
3495 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3496 opc, "\tp$cop, cr$CRd, [$base], $offset"> {
3497 let Inst{31-28} = op31_28;
3498 let Inst{24} = 0; // P = 0
3499 let Inst{21} = 1; // W = 1
3500 let Inst{22} = 0; // D = 0
3501 let Inst{20} = load;
3504 def _OPTION : ACI<(outs),
3505 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option),
3506 opc, "\tp$cop, cr$CRd, [$base], $option"> {
3507 let Inst{31-28} = op31_28;
3508 let Inst{24} = 0; // P = 0
3509 let Inst{23} = 1; // U = 1
3510 let Inst{21} = 0; // W = 0
3511 let Inst{22} = 0; // D = 0
3512 let Inst{20} = load;
3515 def L_OFFSET : ACI<(outs),
3516 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3517 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
3518 let Inst{31-28} = op31_28;
3519 let Inst{24} = 1; // P = 1
3520 let Inst{21} = 0; // W = 0
3521 let Inst{22} = 1; // D = 1
3522 let Inst{20} = load;
3525 def L_PRE : ACI<(outs),
3526 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3527 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
3528 let Inst{31-28} = op31_28;
3529 let Inst{24} = 1; // P = 1
3530 let Inst{21} = 1; // W = 1
3531 let Inst{22} = 1; // D = 1
3532 let Inst{20} = load;
3535 def L_POST : ACI<(outs),
3536 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3537 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $offset"> {
3538 let Inst{31-28} = op31_28;
3539 let Inst{24} = 0; // P = 0
3540 let Inst{21} = 1; // W = 1
3541 let Inst{22} = 1; // D = 1
3542 let Inst{20} = load;
3545 def L_OPTION : ACI<(outs),
3546 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
3547 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $option"> {
3548 let Inst{31-28} = op31_28;
3549 let Inst{24} = 0; // P = 0
3550 let Inst{23} = 1; // U = 1
3551 let Inst{21} = 0; // W = 0
3552 let Inst{22} = 1; // D = 1
3553 let Inst{20} = load;
3557 defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">;
3558 defm LDC2 : LdStCop<0b1111, 1, "ldc2">;
3559 defm STC : LdStCop<{?,?,?,?}, 0, "stc">;
3560 defm STC2 : LdStCop<0b1111, 0, "stc2">;
3562 def MCR : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3563 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3564 NoItinerary, "mcr", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3565 [/* For disassembly only; pattern left blank */]> {
3570 def MCR2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3571 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3572 NoItinerary, "mcr2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3573 [/* For disassembly only; pattern left blank */]> {
3574 let Inst{31-28} = 0b1111;
3579 def MRC : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3580 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3581 NoItinerary, "mrc", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3582 [/* For disassembly only; pattern left blank */]> {
3587 def MRC2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3588 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3589 NoItinerary, "mrc2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3590 [/* For disassembly only; pattern left blank */]> {
3591 let Inst{31-28} = 0b1111;
3596 def MCRR : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3597 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3598 NoItinerary, "mcrr", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3599 [/* For disassembly only; pattern left blank */]> {
3600 let Inst{23-20} = 0b0100;
3603 def MCRR2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3604 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3605 NoItinerary, "mcrr2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3606 [/* For disassembly only; pattern left blank */]> {
3607 let Inst{31-28} = 0b1111;
3608 let Inst{23-20} = 0b0100;
3611 def MRRC : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3612 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3613 NoItinerary, "mrrc", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3614 [/* For disassembly only; pattern left blank */]> {
3615 let Inst{23-20} = 0b0101;
3618 def MRRC2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3619 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3620 NoItinerary, "mrrc2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3621 [/* For disassembly only; pattern left blank */]> {
3622 let Inst{31-28} = 0b1111;
3623 let Inst{23-20} = 0b0101;
3626 //===----------------------------------------------------------------------===//
3627 // Move between special register and ARM core register -- for disassembly only
3630 def MRS : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary, "mrs", "\t$dst, cpsr",
3631 [/* For disassembly only; pattern left blank */]> {
3632 let Inst{23-20} = 0b0000;
3633 let Inst{7-4} = 0b0000;
3636 def MRSsys : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary,"mrs","\t$dst, spsr",
3637 [/* For disassembly only; pattern left blank */]> {
3638 let Inst{23-20} = 0b0100;
3639 let Inst{7-4} = 0b0000;
3642 def MSR : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3643 "msr", "\tcpsr$mask, $src",
3644 [/* For disassembly only; pattern left blank */]> {
3645 let Inst{23-20} = 0b0010;
3646 let Inst{7-4} = 0b0000;
3649 def MSRi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3650 "msr", "\tcpsr$mask, $a",
3651 [/* For disassembly only; pattern left blank */]> {
3652 let Inst{23-20} = 0b0010;
3653 let Inst{7-4} = 0b0000;
3656 def MSRsys : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3657 "msr", "\tspsr$mask, $src",
3658 [/* For disassembly only; pattern left blank */]> {
3659 let Inst{23-20} = 0b0110;
3660 let Inst{7-4} = 0b0000;
3663 def MSRsysi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3664 "msr", "\tspsr$mask, $a",
3665 [/* For disassembly only; pattern left blank */]> {
3666 let Inst{23-20} = 0b0110;
3667 let Inst{7-4} = 0b0000;