1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
63 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
66 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
68 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
69 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
74 SDTCisInt<0>, SDTCisVT<1, i32>]>;
76 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
77 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
84 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
85 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
86 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
87 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
89 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
90 [SDNPHasChain, SDNPOutGlue]>;
91 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
92 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
94 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
95 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
97 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
98 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
100 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
101 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
104 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
105 [SDNPHasChain, SDNPOptInGlue]>;
107 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
110 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
111 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
113 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
115 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
118 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
121 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
124 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
125 [SDNPOutGlue, SDNPCommutative]>;
127 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
129 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
130 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
131 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
133 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
135 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
136 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
137 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
139 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
140 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
141 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
142 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
143 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
145 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
147 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
149 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
150 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
152 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
154 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
155 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
158 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
160 //===----------------------------------------------------------------------===//
161 // ARM Instruction Predicate Definitions.
163 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
164 AssemblerPredicate<"HasV4TOps">;
165 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
166 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
167 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
168 AssemblerPredicate<"HasV5TEOps">;
169 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
170 AssemblerPredicate<"HasV6Ops">;
171 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
172 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
173 AssemblerPredicate<"HasV6T2Ops">;
174 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
175 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
176 AssemblerPredicate<"HasV7Ops">;
177 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
178 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
179 AssemblerPredicate<"FeatureVFP2">;
180 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
181 AssemblerPredicate<"FeatureVFP3">;
182 def HasNEON : Predicate<"Subtarget->hasNEON()">,
183 AssemblerPredicate<"FeatureNEON">;
184 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
185 AssemblerPredicate<"FeatureFP16">;
186 def HasDivide : Predicate<"Subtarget->hasDivide()">,
187 AssemblerPredicate<"FeatureHWDiv">;
188 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
189 AssemblerPredicate<"FeatureT2XtPk">;
190 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
191 AssemblerPredicate<"FeatureDSPThumb2">;
192 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
193 AssemblerPredicate<"FeatureDB">;
194 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
195 AssemblerPredicate<"FeatureMP">;
196 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
197 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
198 def IsThumb : Predicate<"Subtarget->isThumb()">,
199 AssemblerPredicate<"ModeThumb">;
200 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
201 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
202 AssemblerPredicate<"ModeThumb,FeatureThumb2">;
203 def IsMClass : Predicate<"Subtarget->isMClass()">,
204 AssemblerPredicate<"FeatureMClass">;
205 def IsARClass : Predicate<"!Subtarget->isMClass()">,
206 AssemblerPredicate<"!FeatureMClass">;
207 def IsARM : Predicate<"!Subtarget->isThumb()">,
208 AssemblerPredicate<"!ModeThumb">;
209 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
210 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
211 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
213 // FIXME: Eventually this will be just "hasV6T2Ops".
214 def UseMovt : Predicate<"Subtarget->useMovt()">;
215 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
216 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
218 //===----------------------------------------------------------------------===//
219 // ARM Flag Definitions.
221 class RegConstraint<string C> {
222 string Constraints = C;
225 //===----------------------------------------------------------------------===//
226 // ARM specific transformation functions and pattern fragments.
229 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
230 // so_imm_neg def below.
231 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
232 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
235 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
236 // so_imm_not def below.
237 def so_imm_not_XFORM : SDNodeXForm<imm, [{
238 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
241 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
242 def imm1_15 : ImmLeaf<i32, [{
243 return (int32_t)Imm >= 1 && (int32_t)Imm < 16;
246 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
247 def imm16_31 : ImmLeaf<i32, [{
248 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
253 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
254 }], so_imm_neg_XFORM>;
256 // Note: this pattern doesn't require an encoder method and such, as it's
257 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
258 // is handled by the destination instructions, which use t2_so_imm.
259 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
261 Operand<i32>, PatLeaf<(imm), [{
262 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
263 }], so_imm_not_XFORM> {
264 let ParserMatchClass = so_imm_not_asmoperand;
267 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
268 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
269 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
272 /// Split a 32-bit immediate into two 16 bit parts.
273 def hi16 : SDNodeXForm<imm, [{
274 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
277 def lo16AllZero : PatLeaf<(i32 imm), [{
278 // Returns true if all low 16-bits are 0.
279 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
282 class BinOpWithFlagFrag<dag res> :
283 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
284 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
285 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
287 // An 'and' node with a single use.
288 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
289 return N->hasOneUse();
292 // An 'xor' node with a single use.
293 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
294 return N->hasOneUse();
297 // An 'fmul' node with a single use.
298 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
299 return N->hasOneUse();
302 // An 'fadd' node which checks for single non-hazardous use.
303 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
304 return hasNoVMLxHazardUse(N);
307 // An 'fsub' node which checks for single non-hazardous use.
308 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
309 return hasNoVMLxHazardUse(N);
312 //===----------------------------------------------------------------------===//
313 // Operand Definitions.
316 // Immediate operands with a shared generic asm render method.
317 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
320 // FIXME: rename brtarget to t2_brtarget
321 def brtarget : Operand<OtherVT> {
322 let EncoderMethod = "getBranchTargetOpValue";
323 let OperandType = "OPERAND_PCREL";
324 let DecoderMethod = "DecodeT2BROperand";
327 // FIXME: get rid of this one?
328 def uncondbrtarget : Operand<OtherVT> {
329 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
330 let OperandType = "OPERAND_PCREL";
333 // Branch target for ARM. Handles conditional/unconditional
334 def br_target : Operand<OtherVT> {
335 let EncoderMethod = "getARMBranchTargetOpValue";
336 let OperandType = "OPERAND_PCREL";
340 // FIXME: rename bltarget to t2_bl_target?
341 def bltarget : Operand<i32> {
342 // Encoded the same as branch targets.
343 let EncoderMethod = "getBranchTargetOpValue";
344 let OperandType = "OPERAND_PCREL";
347 // Call target for ARM. Handles conditional/unconditional
348 // FIXME: rename bl_target to t2_bltarget?
349 def bl_target : Operand<i32> {
350 // Encoded the same as branch targets.
351 let EncoderMethod = "getARMBranchTargetOpValue";
352 let OperandType = "OPERAND_PCREL";
355 def blx_target : Operand<i32> {
356 // Encoded the same as branch targets.
357 let EncoderMethod = "getARMBLXTargetOpValue";
358 let OperandType = "OPERAND_PCREL";
361 // A list of registers separated by comma. Used by load/store multiple.
362 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
363 def reglist : Operand<i32> {
364 let EncoderMethod = "getRegisterListOpValue";
365 let ParserMatchClass = RegListAsmOperand;
366 let PrintMethod = "printRegisterList";
367 let DecoderMethod = "DecodeRegListOperand";
370 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
371 def dpr_reglist : Operand<i32> {
372 let EncoderMethod = "getRegisterListOpValue";
373 let ParserMatchClass = DPRRegListAsmOperand;
374 let PrintMethod = "printRegisterList";
375 let DecoderMethod = "DecodeDPRRegListOperand";
378 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
379 def spr_reglist : Operand<i32> {
380 let EncoderMethod = "getRegisterListOpValue";
381 let ParserMatchClass = SPRRegListAsmOperand;
382 let PrintMethod = "printRegisterList";
383 let DecoderMethod = "DecodeSPRRegListOperand";
386 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
387 def cpinst_operand : Operand<i32> {
388 let PrintMethod = "printCPInstOperand";
392 def pclabel : Operand<i32> {
393 let PrintMethod = "printPCLabel";
396 // ADR instruction labels.
397 def adrlabel : Operand<i32> {
398 let EncoderMethod = "getAdrLabelOpValue";
401 def neon_vcvt_imm32 : Operand<i32> {
402 let EncoderMethod = "getNEONVcvtImm32OpValue";
403 let DecoderMethod = "DecodeVCVTImmOperand";
406 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
407 def rot_imm_XFORM: SDNodeXForm<imm, [{
408 switch (N->getZExtValue()){
410 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
411 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
412 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
413 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
416 def RotImmAsmOperand : AsmOperandClass {
418 let ParserMethod = "parseRotImm";
420 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
421 int32_t v = N->getZExtValue();
422 return v == 8 || v == 16 || v == 24; }],
424 let PrintMethod = "printRotImmOperand";
425 let ParserMatchClass = RotImmAsmOperand;
428 // shift_imm: An integer that encodes a shift amount and the type of shift
429 // (asr or lsl). The 6-bit immediate encodes as:
432 // {4-0} imm5 shift amount.
433 // asr #32 encoded as imm5 == 0.
434 def ShifterImmAsmOperand : AsmOperandClass {
435 let Name = "ShifterImm";
436 let ParserMethod = "parseShifterImm";
438 def shift_imm : Operand<i32> {
439 let PrintMethod = "printShiftImmOperand";
440 let ParserMatchClass = ShifterImmAsmOperand;
443 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
444 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
445 def so_reg_reg : Operand<i32>, // reg reg imm
446 ComplexPattern<i32, 3, "SelectRegShifterOperand",
447 [shl, srl, sra, rotr]> {
448 let EncoderMethod = "getSORegRegOpValue";
449 let PrintMethod = "printSORegRegOperand";
450 let DecoderMethod = "DecodeSORegRegOperand";
451 let ParserMatchClass = ShiftedRegAsmOperand;
452 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
455 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
456 def so_reg_imm : Operand<i32>, // reg imm
457 ComplexPattern<i32, 2, "SelectImmShifterOperand",
458 [shl, srl, sra, rotr]> {
459 let EncoderMethod = "getSORegImmOpValue";
460 let PrintMethod = "printSORegImmOperand";
461 let DecoderMethod = "DecodeSORegImmOperand";
462 let ParserMatchClass = ShiftedImmAsmOperand;
463 let MIOperandInfo = (ops GPR, i32imm);
466 // FIXME: Does this need to be distinct from so_reg?
467 def shift_so_reg_reg : Operand<i32>, // reg reg imm
468 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
469 [shl,srl,sra,rotr]> {
470 let EncoderMethod = "getSORegRegOpValue";
471 let PrintMethod = "printSORegRegOperand";
472 let DecoderMethod = "DecodeSORegRegOperand";
473 let MIOperandInfo = (ops GPR, GPR, i32imm);
476 // FIXME: Does this need to be distinct from so_reg?
477 def shift_so_reg_imm : Operand<i32>, // reg reg imm
478 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
479 [shl,srl,sra,rotr]> {
480 let EncoderMethod = "getSORegImmOpValue";
481 let PrintMethod = "printSORegImmOperand";
482 let DecoderMethod = "DecodeSORegImmOperand";
483 let MIOperandInfo = (ops GPR, i32imm);
487 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
488 // 8-bit immediate rotated by an arbitrary number of bits.
489 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
490 def so_imm : Operand<i32>, ImmLeaf<i32, [{
491 return ARM_AM::getSOImmVal(Imm) != -1;
493 let EncoderMethod = "getSOImmOpValue";
494 let ParserMatchClass = SOImmAsmOperand;
495 let DecoderMethod = "DecodeSOImmOperand";
498 // Break so_imm's up into two pieces. This handles immediates with up to 16
499 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
500 // get the first/second pieces.
501 def so_imm2part : PatLeaf<(imm), [{
502 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
505 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
507 def arm_i32imm : PatLeaf<(imm), [{
508 if (Subtarget->hasV6T2Ops())
510 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
513 /// imm0_7 predicate - Immediate in the range [0,7].
514 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
515 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
516 return Imm >= 0 && Imm < 8;
518 let ParserMatchClass = Imm0_7AsmOperand;
521 /// imm0_15 predicate - Immediate in the range [0,15].
522 def Imm0_15AsmOperand: ImmAsmOperand { let Name = "Imm0_15"; }
523 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
524 return Imm >= 0 && Imm < 16;
526 let ParserMatchClass = Imm0_15AsmOperand;
529 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
530 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
531 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
532 return Imm >= 0 && Imm < 32;
534 let ParserMatchClass = Imm0_31AsmOperand;
537 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
538 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
539 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
540 return Imm >= 0 && Imm < 32;
542 let ParserMatchClass = Imm0_32AsmOperand;
545 /// imm0_255 predicate - Immediate in the range [0,255].
546 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
547 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
548 let ParserMatchClass = Imm0_255AsmOperand;
551 /// imm0_65535 - An immediate is in the range [0.65535].
552 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
553 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
554 return Imm >= 0 && Imm < 65536;
556 let ParserMatchClass = Imm0_65535AsmOperand;
559 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
560 // a relocatable expression.
562 // FIXME: This really needs a Thumb version separate from the ARM version.
563 // While the range is the same, and can thus use the same match class,
564 // the encoding is different so it should have a different encoder method.
565 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
566 def imm0_65535_expr : Operand<i32> {
567 let EncoderMethod = "getHiLo16ImmOpValue";
568 let ParserMatchClass = Imm0_65535ExprAsmOperand;
571 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
572 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
573 def imm24b : Operand<i32>, ImmLeaf<i32, [{
574 return Imm >= 0 && Imm <= 0xffffff;
576 let ParserMatchClass = Imm24bitAsmOperand;
580 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
582 def BitfieldAsmOperand : AsmOperandClass {
583 let Name = "Bitfield";
584 let ParserMethod = "parseBitfield";
586 def bf_inv_mask_imm : Operand<i32>,
588 return ARM::isBitFieldInvertedMask(N->getZExtValue());
590 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
591 let PrintMethod = "printBitfieldInvMaskImmOperand";
592 let DecoderMethod = "DecodeBitfieldMaskOperand";
593 let ParserMatchClass = BitfieldAsmOperand;
596 def imm1_32_XFORM: SDNodeXForm<imm, [{
597 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
599 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
600 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
601 uint64_t Imm = N->getZExtValue();
602 return Imm > 0 && Imm <= 32;
605 let PrintMethod = "printImmPlusOneOperand";
606 let ParserMatchClass = Imm1_32AsmOperand;
609 def imm1_16_XFORM: SDNodeXForm<imm, [{
610 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
612 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
613 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
615 let PrintMethod = "printImmPlusOneOperand";
616 let ParserMatchClass = Imm1_16AsmOperand;
619 // Define ARM specific addressing modes.
620 // addrmode_imm12 := reg +/- imm12
622 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
623 def addrmode_imm12 : Operand<i32>,
624 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
625 // 12-bit immediate operand. Note that instructions using this encode
626 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
627 // immediate values are as normal.
629 let EncoderMethod = "getAddrModeImm12OpValue";
630 let PrintMethod = "printAddrModeImm12Operand";
631 let DecoderMethod = "DecodeAddrModeImm12Operand";
632 let ParserMatchClass = MemImm12OffsetAsmOperand;
633 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
635 // ldst_so_reg := reg +/- reg shop imm
637 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
638 def ldst_so_reg : Operand<i32>,
639 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
640 let EncoderMethod = "getLdStSORegOpValue";
641 // FIXME: Simplify the printer
642 let PrintMethod = "printAddrMode2Operand";
643 let DecoderMethod = "DecodeSORegMemOperand";
644 let ParserMatchClass = MemRegOffsetAsmOperand;
645 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
648 // postidx_imm8 := +/- [0,255]
651 // {8} 1 is imm8 is non-negative. 0 otherwise.
652 // {7-0} [0,255] imm8 value.
653 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
654 def postidx_imm8 : Operand<i32> {
655 let PrintMethod = "printPostIdxImm8Operand";
656 let ParserMatchClass = PostIdxImm8AsmOperand;
657 let MIOperandInfo = (ops i32imm);
660 // postidx_imm8s4 := +/- [0,1020]
663 // {8} 1 is imm8 is non-negative. 0 otherwise.
664 // {7-0} [0,255] imm8 value, scaled by 4.
665 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
666 def postidx_imm8s4 : Operand<i32> {
667 let PrintMethod = "printPostIdxImm8s4Operand";
668 let ParserMatchClass = PostIdxImm8s4AsmOperand;
669 let MIOperandInfo = (ops i32imm);
673 // postidx_reg := +/- reg
675 def PostIdxRegAsmOperand : AsmOperandClass {
676 let Name = "PostIdxReg";
677 let ParserMethod = "parsePostIdxReg";
679 def postidx_reg : Operand<i32> {
680 let EncoderMethod = "getPostIdxRegOpValue";
681 let DecoderMethod = "DecodePostIdxReg";
682 let PrintMethod = "printPostIdxRegOperand";
683 let ParserMatchClass = PostIdxRegAsmOperand;
684 let MIOperandInfo = (ops GPR, i32imm);
688 // addrmode2 := reg +/- imm12
689 // := reg +/- reg shop imm
691 // FIXME: addrmode2 should be refactored the rest of the way to always
692 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
693 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
694 def addrmode2 : Operand<i32>,
695 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
696 let EncoderMethod = "getAddrMode2OpValue";
697 let PrintMethod = "printAddrMode2Operand";
698 let ParserMatchClass = AddrMode2AsmOperand;
699 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
702 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
703 let Name = "PostIdxRegShifted";
704 let ParserMethod = "parsePostIdxReg";
706 def am2offset_reg : Operand<i32>,
707 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
708 [], [SDNPWantRoot]> {
709 let EncoderMethod = "getAddrMode2OffsetOpValue";
710 let PrintMethod = "printAddrMode2OffsetOperand";
711 // When using this for assembly, it's always as a post-index offset.
712 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
713 let MIOperandInfo = (ops GPR, i32imm);
716 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
717 // the GPR is purely vestigal at this point.
718 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
719 def am2offset_imm : Operand<i32>,
720 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
721 [], [SDNPWantRoot]> {
722 let EncoderMethod = "getAddrMode2OffsetOpValue";
723 let PrintMethod = "printAddrMode2OffsetOperand";
724 let ParserMatchClass = AM2OffsetImmAsmOperand;
725 let MIOperandInfo = (ops GPR, i32imm);
729 // addrmode3 := reg +/- reg
730 // addrmode3 := reg +/- imm8
732 // FIXME: split into imm vs. reg versions.
733 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
734 def addrmode3 : Operand<i32>,
735 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
736 let EncoderMethod = "getAddrMode3OpValue";
737 let PrintMethod = "printAddrMode3Operand";
738 let ParserMatchClass = AddrMode3AsmOperand;
739 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
742 // FIXME: split into imm vs. reg versions.
743 // FIXME: parser method to handle +/- register.
744 def AM3OffsetAsmOperand : AsmOperandClass {
745 let Name = "AM3Offset";
746 let ParserMethod = "parseAM3Offset";
748 def am3offset : Operand<i32>,
749 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
750 [], [SDNPWantRoot]> {
751 let EncoderMethod = "getAddrMode3OffsetOpValue";
752 let PrintMethod = "printAddrMode3OffsetOperand";
753 let ParserMatchClass = AM3OffsetAsmOperand;
754 let MIOperandInfo = (ops GPR, i32imm);
757 // ldstm_mode := {ia, ib, da, db}
759 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
760 let EncoderMethod = "getLdStmModeOpValue";
761 let PrintMethod = "printLdStmModeOperand";
764 // addrmode5 := reg +/- imm8*4
766 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
767 def addrmode5 : Operand<i32>,
768 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
769 let PrintMethod = "printAddrMode5Operand";
770 let EncoderMethod = "getAddrMode5OpValue";
771 let DecoderMethod = "DecodeAddrMode5Operand";
772 let ParserMatchClass = AddrMode5AsmOperand;
773 let MIOperandInfo = (ops GPR:$base, i32imm);
776 // addrmode6 := reg with optional alignment
778 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
779 def addrmode6 : Operand<i32>,
780 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
781 let PrintMethod = "printAddrMode6Operand";
782 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
783 let EncoderMethod = "getAddrMode6AddressOpValue";
784 let DecoderMethod = "DecodeAddrMode6Operand";
785 let ParserMatchClass = AddrMode6AsmOperand;
788 def am6offset : Operand<i32>,
789 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
790 [], [SDNPWantRoot]> {
791 let PrintMethod = "printAddrMode6OffsetOperand";
792 let MIOperandInfo = (ops GPR);
793 let EncoderMethod = "getAddrMode6OffsetOpValue";
794 let DecoderMethod = "DecodeGPRRegisterClass";
797 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
798 // (single element from one lane) for size 32.
799 def addrmode6oneL32 : Operand<i32>,
800 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
801 let PrintMethod = "printAddrMode6Operand";
802 let MIOperandInfo = (ops GPR:$addr, i32imm);
803 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
806 // Special version of addrmode6 to handle alignment encoding for VLD-dup
807 // instructions, specifically VLD4-dup.
808 def addrmode6dup : Operand<i32>,
809 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
810 let PrintMethod = "printAddrMode6Operand";
811 let MIOperandInfo = (ops GPR:$addr, i32imm);
812 let EncoderMethod = "getAddrMode6DupAddressOpValue";
815 // addrmodepc := pc + reg
817 def addrmodepc : Operand<i32>,
818 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
819 let PrintMethod = "printAddrModePCOperand";
820 let MIOperandInfo = (ops GPR, i32imm);
823 // addr_offset_none := reg
825 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
826 def addr_offset_none : Operand<i32>,
827 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
828 let PrintMethod = "printAddrMode7Operand";
829 let DecoderMethod = "DecodeAddrMode7Operand";
830 let ParserMatchClass = MemNoOffsetAsmOperand;
831 let MIOperandInfo = (ops GPR:$base);
834 def nohash_imm : Operand<i32> {
835 let PrintMethod = "printNoHashImmediate";
838 def CoprocNumAsmOperand : AsmOperandClass {
839 let Name = "CoprocNum";
840 let ParserMethod = "parseCoprocNumOperand";
842 def p_imm : Operand<i32> {
843 let PrintMethod = "printPImmediate";
844 let ParserMatchClass = CoprocNumAsmOperand;
845 let DecoderMethod = "DecodeCoprocessor";
848 def CoprocRegAsmOperand : AsmOperandClass {
849 let Name = "CoprocReg";
850 let ParserMethod = "parseCoprocRegOperand";
852 def c_imm : Operand<i32> {
853 let PrintMethod = "printCImmediate";
854 let ParserMatchClass = CoprocRegAsmOperand;
856 def CoprocOptionAsmOperand : AsmOperandClass {
857 let Name = "CoprocOption";
858 let ParserMethod = "parseCoprocOptionOperand";
860 def coproc_option_imm : Operand<i32> {
861 let PrintMethod = "printCoprocOptionImm";
862 let ParserMatchClass = CoprocOptionAsmOperand;
865 //===----------------------------------------------------------------------===//
867 include "ARMInstrFormats.td"
869 //===----------------------------------------------------------------------===//
870 // Multiclass helpers...
873 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
874 /// binop that produces a value.
875 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
876 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
877 PatFrag opnode, string baseOpc, bit Commutable = 0> {
878 // The register-immediate version is re-materializable. This is useful
879 // in particular for taking the address of a local.
880 let isReMaterializable = 1 in {
881 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
882 iii, opc, "\t$Rd, $Rn, $imm",
883 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
888 let Inst{19-16} = Rn;
889 let Inst{15-12} = Rd;
890 let Inst{11-0} = imm;
893 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
894 iir, opc, "\t$Rd, $Rn, $Rm",
895 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
900 let isCommutable = Commutable;
901 let Inst{19-16} = Rn;
902 let Inst{15-12} = Rd;
903 let Inst{11-4} = 0b00000000;
907 def rsi : AsI1<opcod, (outs GPR:$Rd),
908 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
909 iis, opc, "\t$Rd, $Rn, $shift",
910 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
915 let Inst{19-16} = Rn;
916 let Inst{15-12} = Rd;
917 let Inst{11-5} = shift{11-5};
919 let Inst{3-0} = shift{3-0};
922 def rsr : AsI1<opcod, (outs GPR:$Rd),
923 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
924 iis, opc, "\t$Rd, $Rn, $shift",
925 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
930 let Inst{19-16} = Rn;
931 let Inst{15-12} = Rd;
932 let Inst{11-8} = shift{11-8};
934 let Inst{6-5} = shift{6-5};
936 let Inst{3-0} = shift{3-0};
939 // Assembly aliases for optional destination operand when it's the same
940 // as the source operand.
941 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
942 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
943 so_imm:$imm, pred:$p,
946 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
947 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
951 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
952 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
953 so_reg_imm:$shift, pred:$p,
956 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
957 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
958 so_reg_reg:$shift, pred:$p,
964 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
965 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
966 /// it is equivalent to the AsI1_bin_irs counterpart.
967 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
968 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
969 PatFrag opnode, string baseOpc, bit Commutable = 0> {
970 // The register-immediate version is re-materializable. This is useful
971 // in particular for taking the address of a local.
972 let isReMaterializable = 1 in {
973 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
974 iii, opc, "\t$Rd, $Rn, $imm",
975 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]> {
980 let Inst{19-16} = Rn;
981 let Inst{15-12} = Rd;
982 let Inst{11-0} = imm;
985 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
986 iir, opc, "\t$Rd, $Rn, $Rm",
987 [/* pattern left blank */]> {
991 let Inst{11-4} = 0b00000000;
994 let Inst{15-12} = Rd;
995 let Inst{19-16} = Rn;
998 def rsi : AsI1<opcod, (outs GPR:$Rd),
999 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1000 iis, opc, "\t$Rd, $Rn, $shift",
1001 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]> {
1006 let Inst{19-16} = Rn;
1007 let Inst{15-12} = Rd;
1008 let Inst{11-5} = shift{11-5};
1010 let Inst{3-0} = shift{3-0};
1013 def rsr : AsI1<opcod, (outs GPR:$Rd),
1014 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1015 iis, opc, "\t$Rd, $Rn, $shift",
1016 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]> {
1021 let Inst{19-16} = Rn;
1022 let Inst{15-12} = Rd;
1023 let Inst{11-8} = shift{11-8};
1025 let Inst{6-5} = shift{6-5};
1027 let Inst{3-0} = shift{3-0};
1030 // Assembly aliases for optional destination operand when it's the same
1031 // as the source operand.
1032 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1033 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1034 so_imm:$imm, pred:$p,
1037 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1038 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1042 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1043 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1044 so_reg_imm:$shift, pred:$p,
1047 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1048 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1049 so_reg_reg:$shift, pred:$p,
1055 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1057 /// These opcodes will be converted to the real non-S opcodes by
1058 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1059 let hasPostISelHook = 1, Defs = [CPSR] in {
1060 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1061 InstrItinClass iis, PatFrag opnode,
1062 bit Commutable = 0> {
1063 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1065 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>;
1067 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1069 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> {
1070 let isCommutable = Commutable;
1072 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1073 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1075 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1076 so_reg_imm:$shift))]>;
1078 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1079 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1081 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1082 so_reg_reg:$shift))]>;
1086 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1087 /// operands are reversed.
1088 let hasPostISelHook = 1, Defs = [CPSR] in {
1089 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1090 InstrItinClass iis, PatFrag opnode,
1091 bit Commutable = 0> {
1092 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1094 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>;
1096 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1097 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1099 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1102 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1103 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1105 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1110 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1111 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1112 /// a explicit result, only implicitly set CPSR.
1113 let isCompare = 1, Defs = [CPSR] in {
1114 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1115 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1116 PatFrag opnode, bit Commutable = 0> {
1117 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1119 [(opnode GPR:$Rn, so_imm:$imm)]> {
1124 let Inst{19-16} = Rn;
1125 let Inst{15-12} = 0b0000;
1126 let Inst{11-0} = imm;
1128 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1130 [(opnode GPR:$Rn, GPR:$Rm)]> {
1133 let isCommutable = Commutable;
1136 let Inst{19-16} = Rn;
1137 let Inst{15-12} = 0b0000;
1138 let Inst{11-4} = 0b00000000;
1141 def rsi : AI1<opcod, (outs),
1142 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1143 opc, "\t$Rn, $shift",
1144 [(opnode GPR:$Rn, so_reg_imm:$shift)]> {
1149 let Inst{19-16} = Rn;
1150 let Inst{15-12} = 0b0000;
1151 let Inst{11-5} = shift{11-5};
1153 let Inst{3-0} = shift{3-0};
1155 def rsr : AI1<opcod, (outs),
1156 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1157 opc, "\t$Rn, $shift",
1158 [(opnode GPR:$Rn, so_reg_reg:$shift)]> {
1163 let Inst{19-16} = Rn;
1164 let Inst{15-12} = 0b0000;
1165 let Inst{11-8} = shift{11-8};
1167 let Inst{6-5} = shift{6-5};
1169 let Inst{3-0} = shift{3-0};
1175 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1176 /// register and one whose operand is a register rotated by 8/16/24.
1177 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1178 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1179 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1180 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1181 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1182 Requires<[IsARM, HasV6]> {
1186 let Inst{19-16} = 0b1111;
1187 let Inst{15-12} = Rd;
1188 let Inst{11-10} = rot;
1192 class AI_ext_rrot_np<bits<8> opcod, string opc>
1193 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1194 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1195 Requires<[IsARM, HasV6]> {
1197 let Inst{19-16} = 0b1111;
1198 let Inst{11-10} = rot;
1201 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1202 /// register and one whose operand is a register rotated by 8/16/24.
1203 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1204 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1205 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1206 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1207 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1208 Requires<[IsARM, HasV6]> {
1213 let Inst{19-16} = Rn;
1214 let Inst{15-12} = Rd;
1215 let Inst{11-10} = rot;
1216 let Inst{9-4} = 0b000111;
1220 class AI_exta_rrot_np<bits<8> opcod, string opc>
1221 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1222 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1223 Requires<[IsARM, HasV6]> {
1226 let Inst{19-16} = Rn;
1227 let Inst{11-10} = rot;
1230 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1231 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1232 string baseOpc, bit Commutable = 0> {
1233 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1234 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1235 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1236 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1242 let Inst{15-12} = Rd;
1243 let Inst{19-16} = Rn;
1244 let Inst{11-0} = imm;
1246 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1247 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1248 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1253 let Inst{11-4} = 0b00000000;
1255 let isCommutable = Commutable;
1257 let Inst{15-12} = Rd;
1258 let Inst{19-16} = Rn;
1260 def rsi : AsI1<opcod, (outs GPR:$Rd),
1261 (ins GPR:$Rn, so_reg_imm:$shift),
1262 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1263 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1269 let Inst{19-16} = Rn;
1270 let Inst{15-12} = Rd;
1271 let Inst{11-5} = shift{11-5};
1273 let Inst{3-0} = shift{3-0};
1275 def rsr : AsI1<opcod, (outs GPR:$Rd),
1276 (ins GPR:$Rn, so_reg_reg:$shift),
1277 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1278 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_reg:$shift, CPSR))]>,
1284 let Inst{19-16} = Rn;
1285 let Inst{15-12} = Rd;
1286 let Inst{11-8} = shift{11-8};
1288 let Inst{6-5} = shift{6-5};
1290 let Inst{3-0} = shift{3-0};
1294 // Assembly aliases for optional destination operand when it's the same
1295 // as the source operand.
1296 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1297 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1298 so_imm:$imm, pred:$p,
1301 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1302 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1306 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1307 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1308 so_reg_imm:$shift, pred:$p,
1311 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1312 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1313 so_reg_reg:$shift, pred:$p,
1318 /// AI1_rsc_irs - Define instructions and patterns for rsc
1319 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode,
1321 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1322 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1323 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1324 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1330 let Inst{15-12} = Rd;
1331 let Inst{19-16} = Rn;
1332 let Inst{11-0} = imm;
1334 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1335 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1336 [/* pattern left blank */]> {
1340 let Inst{11-4} = 0b00000000;
1343 let Inst{15-12} = Rd;
1344 let Inst{19-16} = Rn;
1346 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1347 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1348 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1354 let Inst{19-16} = Rn;
1355 let Inst{15-12} = Rd;
1356 let Inst{11-5} = shift{11-5};
1358 let Inst{3-0} = shift{3-0};
1360 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1361 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1362 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1368 let Inst{19-16} = Rn;
1369 let Inst{15-12} = Rd;
1370 let Inst{11-8} = shift{11-8};
1372 let Inst{6-5} = shift{6-5};
1374 let Inst{3-0} = shift{3-0};
1378 // Assembly aliases for optional destination operand when it's the same
1379 // as the source operand.
1380 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1381 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1382 so_imm:$imm, pred:$p,
1385 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1386 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1390 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1391 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1392 so_reg_imm:$shift, pred:$p,
1395 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1396 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1397 so_reg_reg:$shift, pred:$p,
1402 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1403 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1404 InstrItinClass iir, PatFrag opnode> {
1405 // Note: We use the complex addrmode_imm12 rather than just an input
1406 // GPR and a constrained immediate so that we can use this to match
1407 // frame index references and avoid matching constant pool references.
1408 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1409 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1410 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1413 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1414 let Inst{19-16} = addr{16-13}; // Rn
1415 let Inst{15-12} = Rt;
1416 let Inst{11-0} = addr{11-0}; // imm12
1418 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1419 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1420 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1423 let shift{4} = 0; // Inst{4} = 0
1424 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1425 let Inst{19-16} = shift{16-13}; // Rn
1426 let Inst{15-12} = Rt;
1427 let Inst{11-0} = shift{11-0};
1432 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1433 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1434 InstrItinClass iir, PatFrag opnode> {
1435 // Note: We use the complex addrmode_imm12 rather than just an input
1436 // GPR and a constrained immediate so that we can use this to match
1437 // frame index references and avoid matching constant pool references.
1438 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), (ins addrmode_imm12:$addr),
1439 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1440 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1443 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1444 let Inst{19-16} = addr{16-13}; // Rn
1445 let Inst{15-12} = Rt;
1446 let Inst{11-0} = addr{11-0}; // imm12
1448 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), (ins ldst_so_reg:$shift),
1449 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1450 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1453 let shift{4} = 0; // Inst{4} = 0
1454 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1455 let Inst{19-16} = shift{16-13}; // Rn
1456 let Inst{15-12} = Rt;
1457 let Inst{11-0} = shift{11-0};
1463 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1464 InstrItinClass iir, PatFrag opnode> {
1465 // Note: We use the complex addrmode_imm12 rather than just an input
1466 // GPR and a constrained immediate so that we can use this to match
1467 // frame index references and avoid matching constant pool references.
1468 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1469 (ins GPR:$Rt, addrmode_imm12:$addr),
1470 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1471 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1474 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1475 let Inst{19-16} = addr{16-13}; // Rn
1476 let Inst{15-12} = Rt;
1477 let Inst{11-0} = addr{11-0}; // imm12
1479 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1480 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1481 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1484 let shift{4} = 0; // Inst{4} = 0
1485 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1486 let Inst{19-16} = shift{16-13}; // Rn
1487 let Inst{15-12} = Rt;
1488 let Inst{11-0} = shift{11-0};
1492 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1493 InstrItinClass iir, PatFrag opnode> {
1494 // Note: We use the complex addrmode_imm12 rather than just an input
1495 // GPR and a constrained immediate so that we can use this to match
1496 // frame index references and avoid matching constant pool references.
1497 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1498 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1499 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1500 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1503 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1504 let Inst{19-16} = addr{16-13}; // Rn
1505 let Inst{15-12} = Rt;
1506 let Inst{11-0} = addr{11-0}; // imm12
1508 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1509 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1510 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1513 let shift{4} = 0; // Inst{4} = 0
1514 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1515 let Inst{19-16} = shift{16-13}; // Rn
1516 let Inst{15-12} = Rt;
1517 let Inst{11-0} = shift{11-0};
1522 //===----------------------------------------------------------------------===//
1524 //===----------------------------------------------------------------------===//
1526 //===----------------------------------------------------------------------===//
1527 // Miscellaneous Instructions.
1530 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1531 /// the function. The first operand is the ID# for this instruction, the second
1532 /// is the index into the MachineConstantPool that this is, the third is the
1533 /// size in bytes of this constant pool entry.
1534 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1535 def CONSTPOOL_ENTRY :
1536 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1537 i32imm:$size), NoItinerary, []>;
1539 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1540 // from removing one half of the matched pairs. That breaks PEI, which assumes
1541 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1542 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1543 def ADJCALLSTACKUP :
1544 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1545 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1547 def ADJCALLSTACKDOWN :
1548 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1549 [(ARMcallseq_start timm:$amt)]>;
1552 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1553 // (These pseudos use a hand-written selection code).
1554 let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
1555 def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1556 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1558 def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1559 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1561 def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1562 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1564 def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1565 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1567 def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1568 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1570 def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1571 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1573 def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1574 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1576 def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1577 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
1578 GPR:$set1, GPR:$set2),
1582 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "", []>,
1583 Requires<[IsARM, HasV6T2]> {
1584 let Inst{27-16} = 0b001100100000;
1585 let Inst{15-8} = 0b11110000;
1586 let Inst{7-0} = 0b00000000;
1589 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "", []>,
1590 Requires<[IsARM, HasV6T2]> {
1591 let Inst{27-16} = 0b001100100000;
1592 let Inst{15-8} = 0b11110000;
1593 let Inst{7-0} = 0b00000001;
1596 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "", []>,
1597 Requires<[IsARM, HasV6T2]> {
1598 let Inst{27-16} = 0b001100100000;
1599 let Inst{15-8} = 0b11110000;
1600 let Inst{7-0} = 0b00000010;
1603 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "", []>,
1604 Requires<[IsARM, HasV6T2]> {
1605 let Inst{27-16} = 0b001100100000;
1606 let Inst{15-8} = 0b11110000;
1607 let Inst{7-0} = 0b00000011;
1610 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1611 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1616 let Inst{15-12} = Rd;
1617 let Inst{19-16} = Rn;
1618 let Inst{27-20} = 0b01101000;
1619 let Inst{7-4} = 0b1011;
1620 let Inst{11-8} = 0b1111;
1623 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1624 []>, Requires<[IsARM, HasV6T2]> {
1625 let Inst{27-16} = 0b001100100000;
1626 let Inst{15-8} = 0b11110000;
1627 let Inst{7-0} = 0b00000100;
1630 // The i32imm operand $val can be used by a debugger to store more information
1631 // about the breakpoint.
1632 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1633 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1635 let Inst{3-0} = val{3-0};
1636 let Inst{19-8} = val{15-4};
1637 let Inst{27-20} = 0b00010010;
1638 let Inst{7-4} = 0b0111;
1641 // Change Processor State
1642 // FIXME: We should use InstAlias to handle the optional operands.
1643 class CPS<dag iops, string asm_ops>
1644 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1645 []>, Requires<[IsARM]> {
1651 let Inst{31-28} = 0b1111;
1652 let Inst{27-20} = 0b00010000;
1653 let Inst{19-18} = imod;
1654 let Inst{17} = M; // Enabled if mode is set;
1655 let Inst{16-9} = 0b00000000;
1656 let Inst{8-6} = iflags;
1658 let Inst{4-0} = mode;
1661 let DecoderMethod = "DecodeCPSInstruction" in {
1663 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1664 "$imod\t$iflags, $mode">;
1665 let mode = 0, M = 0 in
1666 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1668 let imod = 0, iflags = 0, M = 1 in
1669 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1672 // Preload signals the memory system of possible future data/instruction access.
1673 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1675 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1676 !strconcat(opc, "\t$addr"),
1677 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1680 let Inst{31-26} = 0b111101;
1681 let Inst{25} = 0; // 0 for immediate form
1682 let Inst{24} = data;
1683 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1684 let Inst{22} = read;
1685 let Inst{21-20} = 0b01;
1686 let Inst{19-16} = addr{16-13}; // Rn
1687 let Inst{15-12} = 0b1111;
1688 let Inst{11-0} = addr{11-0}; // imm12
1691 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1692 !strconcat(opc, "\t$shift"),
1693 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1695 let Inst{31-26} = 0b111101;
1696 let Inst{25} = 1; // 1 for register form
1697 let Inst{24} = data;
1698 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1699 let Inst{22} = read;
1700 let Inst{21-20} = 0b01;
1701 let Inst{19-16} = shift{16-13}; // Rn
1702 let Inst{15-12} = 0b1111;
1703 let Inst{11-0} = shift{11-0};
1708 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1709 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1710 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1712 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1713 "setend\t$end", []>, Requires<[IsARM]> {
1715 let Inst{31-10} = 0b1111000100000001000000;
1720 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1721 []>, Requires<[IsARM, HasV7]> {
1723 let Inst{27-4} = 0b001100100000111100001111;
1724 let Inst{3-0} = opt;
1727 // A5.4 Permanently UNDEFINED instructions.
1728 let isBarrier = 1, isTerminator = 1 in
1729 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1732 let Inst = 0xe7ffdefe;
1735 // Address computation and loads and stores in PIC mode.
1736 let isNotDuplicable = 1 in {
1737 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1739 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1741 let AddedComplexity = 10 in {
1742 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1744 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1746 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1748 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1750 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1752 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1754 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1756 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1758 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1760 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1762 let AddedComplexity = 10 in {
1763 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1764 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1766 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1767 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1768 addrmodepc:$addr)]>;
1770 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1771 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1773 } // isNotDuplicable = 1
1776 // LEApcrel - Load a pc-relative address into a register without offending the
1778 let neverHasSideEffects = 1, isReMaterializable = 1 in
1779 // The 'adr' mnemonic encodes differently if the label is before or after
1780 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1781 // know until then which form of the instruction will be used.
1782 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1783 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []> {
1786 let Inst{27-25} = 0b001;
1788 let Inst{23-22} = label{13-12};
1791 let Inst{19-16} = 0b1111;
1792 let Inst{15-12} = Rd;
1793 let Inst{11-0} = label{11-0};
1795 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1798 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1799 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1802 //===----------------------------------------------------------------------===//
1803 // Control Flow Instructions.
1806 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1808 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1809 "bx", "\tlr", [(ARMretflag)]>,
1810 Requires<[IsARM, HasV4T]> {
1811 let Inst{27-0} = 0b0001001011111111111100011110;
1815 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1816 "mov", "\tpc, lr", [(ARMretflag)]>,
1817 Requires<[IsARM, NoV4T]> {
1818 let Inst{27-0} = 0b0001101000001111000000001110;
1822 // Indirect branches
1823 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1825 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1826 [(brind GPR:$dst)]>,
1827 Requires<[IsARM, HasV4T]> {
1829 let Inst{31-4} = 0b1110000100101111111111110001;
1830 let Inst{3-0} = dst;
1833 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1834 "bx", "\t$dst", [/* pattern left blank */]>,
1835 Requires<[IsARM, HasV4T]> {
1837 let Inst{27-4} = 0b000100101111111111110001;
1838 let Inst{3-0} = dst;
1842 // All calls clobber the non-callee saved registers. SP is marked as
1843 // a use to prevent stack-pointer assignments that appear immediately
1844 // before calls from potentially appearing dead.
1846 // On non-Darwin platforms R9 is callee-saved.
1847 // FIXME: Do we really need a non-predicated version? If so, it should
1848 // at least be a pseudo instruction expanding to the predicated version
1849 // at MC lowering time.
1850 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1852 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1853 IIC_Br, "bl\t$func",
1854 [(ARMcall tglobaladdr:$func)]>,
1855 Requires<[IsARM, IsNotDarwin]> {
1856 let Inst{31-28} = 0b1110;
1858 let Inst{23-0} = func;
1859 let DecoderMethod = "DecodeBranchImmInstruction";
1862 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1863 IIC_Br, "bl", "\t$func",
1864 [(ARMcall_pred tglobaladdr:$func)]>,
1865 Requires<[IsARM, IsNotDarwin]> {
1867 let Inst{23-0} = func;
1868 let DecoderMethod = "DecodeBranchImmInstruction";
1872 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1873 IIC_Br, "blx\t$func",
1874 [(ARMcall GPR:$func)]>,
1875 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1877 let Inst{31-4} = 0b1110000100101111111111110011;
1878 let Inst{3-0} = func;
1881 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1882 IIC_Br, "blx", "\t$func",
1883 [(ARMcall_pred GPR:$func)]>,
1884 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1886 let Inst{27-4} = 0b000100101111111111110011;
1887 let Inst{3-0} = func;
1891 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1892 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1893 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1894 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1897 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1898 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1899 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1903 // On Darwin R9 is call-clobbered.
1904 // R7 is marked as a use to prevent frame-pointer assignments from being
1905 // moved above / below calls.
1906 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1907 Uses = [R7, SP] in {
1908 def BLr9 : ARMPseudoExpand<(outs), (ins bl_target:$func, variable_ops),
1910 [(ARMcall tglobaladdr:$func)], (BL bl_target:$func)>,
1911 Requires<[IsARM, IsDarwin]>;
1913 def BLr9_pred : ARMPseudoExpand<(outs),
1914 (ins bl_target:$func, pred:$p, variable_ops),
1916 [(ARMcall_pred tglobaladdr:$func)],
1917 (BL_pred bl_target:$func, pred:$p)>,
1918 Requires<[IsARM, IsDarwin]>;
1921 def BLXr9 : ARMPseudoExpand<(outs), (ins GPR:$func, variable_ops),
1923 [(ARMcall GPR:$func)],
1925 Requires<[IsARM, HasV5T, IsDarwin]>;
1927 def BLXr9_pred: ARMPseudoExpand<(outs), (ins GPR:$func, pred:$p,variable_ops),
1929 [(ARMcall_pred GPR:$func)],
1930 (BLX_pred GPR:$func, pred:$p)>,
1931 Requires<[IsARM, HasV5T, IsDarwin]>;
1934 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1935 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1936 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1937 Requires<[IsARM, HasV4T, IsDarwin]>;
1940 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1941 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1942 Requires<[IsARM, NoV4T, IsDarwin]>;
1945 let isBranch = 1, isTerminator = 1 in {
1946 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1947 // a two-value operand where a dag node expects two operands. :(
1948 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1949 IIC_Br, "b", "\t$target",
1950 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1952 let Inst{23-0} = target;
1953 let DecoderMethod = "DecodeBranchImmInstruction";
1956 let isBarrier = 1 in {
1957 // B is "predicable" since it's just a Bcc with an 'always' condition.
1958 let isPredicable = 1 in
1959 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1960 // should be sufficient.
1961 // FIXME: Is B really a Barrier? That doesn't seem right.
1962 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
1963 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
1965 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1966 def BR_JTr : ARMPseudoInst<(outs),
1967 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1969 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1970 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1971 // into i12 and rs suffixed versions.
1972 def BR_JTm : ARMPseudoInst<(outs),
1973 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1975 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1977 def BR_JTadd : ARMPseudoInst<(outs),
1978 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1980 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1982 } // isNotDuplicable = 1, isIndirectBranch = 1
1988 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
1989 "blx\t$target", []>,
1990 Requires<[IsARM, HasV5T]> {
1991 let Inst{31-25} = 0b1111101;
1993 let Inst{23-0} = target{24-1};
1994 let Inst{24} = target{0};
1997 // Branch and Exchange Jazelle
1998 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1999 [/* pattern left blank */]> {
2001 let Inst{23-20} = 0b0010;
2002 let Inst{19-8} = 0xfff;
2003 let Inst{7-4} = 0b0010;
2004 let Inst{3-0} = func;
2009 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
2011 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
2013 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
2014 IIC_Br, []>, Requires<[IsDarwin]>;
2016 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
2017 IIC_Br, []>, Requires<[IsDarwin]>;
2019 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst, variable_ops),
2021 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2022 Requires<[IsARM, IsDarwin]>;
2024 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
2027 Requires<[IsARM, IsDarwin]>;
2031 // Non-Darwin versions (the difference is R9).
2032 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
2034 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
2035 IIC_Br, []>, Requires<[IsNotDarwin]>;
2037 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
2038 IIC_Br, []>, Requires<[IsNotDarwin]>;
2040 def TAILJMPdND : ARMPseudoExpand<(outs), (ins brtarget:$dst, variable_ops),
2042 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2043 Requires<[IsARM, IsNotDarwin]>;
2045 def TAILJMPrND : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
2048 Requires<[IsARM, IsNotDarwin]>;
2052 // Secure Monitor Call is a system instruction.
2053 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2056 let Inst{23-4} = 0b01100000000000000111;
2057 let Inst{3-0} = opt;
2060 // Supervisor Call (Software Interrupt)
2061 let isCall = 1, Uses = [SP] in {
2062 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
2064 let Inst{23-0} = svc;
2068 // Store Return State
2069 class SRSI<bit wb, string asm>
2070 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2071 NoItinerary, asm, "", []> {
2073 let Inst{31-28} = 0b1111;
2074 let Inst{27-25} = 0b100;
2078 let Inst{19-16} = 0b1101; // SP
2079 let Inst{15-5} = 0b00000101000;
2080 let Inst{4-0} = mode;
2083 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2084 let Inst{24-23} = 0;
2086 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2087 let Inst{24-23} = 0;
2089 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2090 let Inst{24-23} = 0b10;
2092 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2093 let Inst{24-23} = 0b10;
2095 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2096 let Inst{24-23} = 0b01;
2098 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2099 let Inst{24-23} = 0b01;
2101 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2102 let Inst{24-23} = 0b11;
2104 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2105 let Inst{24-23} = 0b11;
2108 // Return From Exception
2109 class RFEI<bit wb, string asm>
2110 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2111 NoItinerary, asm, "", []> {
2113 let Inst{31-28} = 0b1111;
2114 let Inst{27-25} = 0b100;
2118 let Inst{19-16} = Rn;
2119 let Inst{15-0} = 0xa00;
2122 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2123 let Inst{24-23} = 0;
2125 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2126 let Inst{24-23} = 0;
2128 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2129 let Inst{24-23} = 0b10;
2131 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2132 let Inst{24-23} = 0b10;
2134 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2135 let Inst{24-23} = 0b01;
2137 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2138 let Inst{24-23} = 0b01;
2140 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2141 let Inst{24-23} = 0b11;
2143 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2144 let Inst{24-23} = 0b11;
2147 //===----------------------------------------------------------------------===//
2148 // Load / Store Instructions.
2154 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2155 UnOpFrag<(load node:$Src)>>;
2156 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2157 UnOpFrag<(zextloadi8 node:$Src)>>;
2158 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2159 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2160 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2161 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2163 // Special LDR for loads from non-pc-relative constpools.
2164 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2165 isReMaterializable = 1, isCodeGenOnly = 1 in
2166 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2167 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2171 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2172 let Inst{19-16} = 0b1111;
2173 let Inst{15-12} = Rt;
2174 let Inst{11-0} = addr{11-0}; // imm12
2177 // Loads with zero extension
2178 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2179 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2180 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2182 // Loads with sign extension
2183 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2184 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2185 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2187 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2188 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2189 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2191 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2193 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2194 (ins addrmode3:$addr), LdMiscFrm,
2195 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2196 []>, Requires<[IsARM, HasV5TE]>;
2200 multiclass AI2_ldridx<bit isByte, string opc,
2201 InstrItinClass iii, InstrItinClass iir> {
2202 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2203 (ins addrmode_imm12:$addr), IndexModePre, LdFrm, iii,
2204 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2207 let Inst{23} = addr{12};
2208 let Inst{19-16} = addr{16-13};
2209 let Inst{11-0} = addr{11-0};
2210 let DecoderMethod = "DecodeLDRPreImm";
2211 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
2214 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2215 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2216 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2219 let Inst{23} = addr{12};
2220 let Inst{19-16} = addr{16-13};
2221 let Inst{11-0} = addr{11-0};
2223 let DecoderMethod = "DecodeLDRPreReg";
2224 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2227 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2228 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2229 IndexModePost, LdFrm, iir,
2230 opc, "\t$Rt, $addr, $offset",
2231 "$addr.base = $Rn_wb", []> {
2237 let Inst{23} = offset{12};
2238 let Inst{19-16} = addr;
2239 let Inst{11-0} = offset{11-0};
2241 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2244 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2245 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2246 IndexModePost, LdFrm, iii,
2247 opc, "\t$Rt, $addr, $offset",
2248 "$addr.base = $Rn_wb", []> {
2254 let Inst{23} = offset{12};
2255 let Inst{19-16} = addr;
2256 let Inst{11-0} = offset{11-0};
2258 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2263 let mayLoad = 1, neverHasSideEffects = 1 in {
2264 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2265 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2266 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2267 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2270 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2271 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2272 (ins addrmode3:$addr), IndexModePre,
2274 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2276 let Inst{23} = addr{8}; // U bit
2277 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2278 let Inst{19-16} = addr{12-9}; // Rn
2279 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2280 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2281 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
2282 let DecoderMethod = "DecodeAddrMode3Instruction";
2284 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2285 (ins addr_offset_none:$addr, am3offset:$offset),
2286 IndexModePost, LdMiscFrm, itin,
2287 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2291 let Inst{23} = offset{8}; // U bit
2292 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2293 let Inst{19-16} = addr;
2294 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2295 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2296 let DecoderMethod = "DecodeAddrMode3Instruction";
2300 let mayLoad = 1, neverHasSideEffects = 1 in {
2301 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2302 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2303 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2304 let hasExtraDefRegAllocReq = 1 in {
2305 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2306 (ins addrmode3:$addr), IndexModePre,
2307 LdMiscFrm, IIC_iLoad_d_ru,
2308 "ldrd", "\t$Rt, $Rt2, $addr!",
2309 "$addr.base = $Rn_wb", []> {
2311 let Inst{23} = addr{8}; // U bit
2312 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2313 let Inst{19-16} = addr{12-9}; // Rn
2314 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2315 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2316 let DecoderMethod = "DecodeAddrMode3Instruction";
2317 let AsmMatchConverter = "cvtLdrdPre";
2319 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2320 (ins addr_offset_none:$addr, am3offset:$offset),
2321 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2322 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2323 "$addr.base = $Rn_wb", []> {
2326 let Inst{23} = offset{8}; // U bit
2327 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2328 let Inst{19-16} = addr;
2329 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2330 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2331 let DecoderMethod = "DecodeAddrMode3Instruction";
2333 } // hasExtraDefRegAllocReq = 1
2334 } // mayLoad = 1, neverHasSideEffects = 1
2336 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2337 let mayLoad = 1, neverHasSideEffects = 1 in {
2338 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2339 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2340 IndexModePost, LdFrm, IIC_iLoad_ru,
2341 "ldrt", "\t$Rt, $addr, $offset",
2342 "$addr.base = $Rn_wb", []> {
2348 let Inst{23} = offset{12};
2349 let Inst{21} = 1; // overwrite
2350 let Inst{19-16} = addr;
2351 let Inst{11-5} = offset{11-5};
2353 let Inst{3-0} = offset{3-0};
2354 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2357 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2358 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2359 IndexModePost, LdFrm, IIC_iLoad_ru,
2360 "ldrt", "\t$Rt, $addr, $offset",
2361 "$addr.base = $Rn_wb", []> {
2367 let Inst{23} = offset{12};
2368 let Inst{21} = 1; // overwrite
2369 let Inst{19-16} = addr;
2370 let Inst{11-0} = offset{11-0};
2371 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2374 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2375 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2376 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2377 "ldrbt", "\t$Rt, $addr, $offset",
2378 "$addr.base = $Rn_wb", []> {
2384 let Inst{23} = offset{12};
2385 let Inst{21} = 1; // overwrite
2386 let Inst{19-16} = addr;
2387 let Inst{11-5} = offset{11-5};
2389 let Inst{3-0} = offset{3-0};
2390 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2393 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2394 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2395 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2396 "ldrbt", "\t$Rt, $addr, $offset",
2397 "$addr.base = $Rn_wb", []> {
2403 let Inst{23} = offset{12};
2404 let Inst{21} = 1; // overwrite
2405 let Inst{19-16} = addr;
2406 let Inst{11-0} = offset{11-0};
2407 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2410 multiclass AI3ldrT<bits<4> op, string opc> {
2411 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2412 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2413 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2414 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2416 let Inst{23} = offset{8};
2418 let Inst{11-8} = offset{7-4};
2419 let Inst{3-0} = offset{3-0};
2420 let AsmMatchConverter = "cvtLdExtTWriteBackImm";
2422 def r : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2423 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2424 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2425 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2427 let Inst{23} = Rm{4};
2430 let Inst{3-0} = Rm{3-0};
2431 let AsmMatchConverter = "cvtLdExtTWriteBackReg";
2435 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2436 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2437 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2442 // Stores with truncate
2443 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2444 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2445 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2448 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2449 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2450 StMiscFrm, IIC_iStore_d_r,
2451 "strd", "\t$Rt, $src2, $addr", []>,
2452 Requires<[IsARM, HasV5TE]> {
2457 multiclass AI2_stridx<bit isByte, string opc,
2458 InstrItinClass iii, InstrItinClass iir> {
2459 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2460 (ins GPR:$Rt, addrmode_imm12:$addr), IndexModePre,
2462 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2465 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2466 let Inst{19-16} = addr{16-13}; // Rn
2467 let Inst{11-0} = addr{11-0}; // imm12
2468 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
2469 let DecoderMethod = "DecodeSTRPreImm";
2472 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2473 (ins GPR:$Rt, ldst_so_reg:$addr),
2474 IndexModePre, StFrm, iir,
2475 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2478 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2479 let Inst{19-16} = addr{16-13}; // Rn
2480 let Inst{11-0} = addr{11-0};
2481 let Inst{4} = 0; // Inst{4} = 0
2482 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2483 let DecoderMethod = "DecodeSTRPreReg";
2485 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2486 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2487 IndexModePost, StFrm, iir,
2488 opc, "\t$Rt, $addr, $offset",
2489 "$addr.base = $Rn_wb", []> {
2495 let Inst{23} = offset{12};
2496 let Inst{19-16} = addr;
2497 let Inst{11-0} = offset{11-0};
2499 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2502 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2503 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2504 IndexModePost, StFrm, iii,
2505 opc, "\t$Rt, $addr, $offset",
2506 "$addr.base = $Rn_wb", []> {
2512 let Inst{23} = offset{12};
2513 let Inst{19-16} = addr;
2514 let Inst{11-0} = offset{11-0};
2516 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2520 let mayStore = 1, neverHasSideEffects = 1 in {
2521 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2522 // IIC_iStore_siu depending on whether it the offset register is shifted.
2523 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2524 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2527 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2528 am2offset_reg:$offset),
2529 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2530 am2offset_reg:$offset)>;
2531 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2532 am2offset_imm:$offset),
2533 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2534 am2offset_imm:$offset)>;
2535 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2536 am2offset_reg:$offset),
2537 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2538 am2offset_reg:$offset)>;
2539 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2540 am2offset_imm:$offset),
2541 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2542 am2offset_imm:$offset)>;
2544 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2545 // put the patterns on the instruction definitions directly as ISel wants
2546 // the address base and offset to be separate operands, not a single
2547 // complex operand like we represent the instructions themselves. The
2548 // pseudos map between the two.
2549 let usesCustomInserter = 1,
2550 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2551 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2552 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2555 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2556 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2557 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2560 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2561 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2562 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2565 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2566 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2567 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2570 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2571 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2572 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2575 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2580 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2581 (ins GPR:$Rt, addrmode3:$addr), IndexModePre,
2582 StMiscFrm, IIC_iStore_bh_ru,
2583 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2585 let Inst{23} = addr{8}; // U bit
2586 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2587 let Inst{19-16} = addr{12-9}; // Rn
2588 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2589 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2590 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
2591 let DecoderMethod = "DecodeAddrMode3Instruction";
2594 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2595 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2596 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2597 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2598 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2599 addr_offset_none:$addr,
2600 am3offset:$offset))]> {
2603 let Inst{23} = offset{8}; // U bit
2604 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2605 let Inst{19-16} = addr;
2606 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2607 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2608 let DecoderMethod = "DecodeAddrMode3Instruction";
2611 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2612 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2613 (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2614 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2615 "strd", "\t$Rt, $Rt2, $addr!",
2616 "$addr.base = $Rn_wb", []> {
2618 let Inst{23} = addr{8}; // U bit
2619 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2620 let Inst{19-16} = addr{12-9}; // Rn
2621 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2622 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2623 let DecoderMethod = "DecodeAddrMode3Instruction";
2624 let AsmMatchConverter = "cvtStrdPre";
2627 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2628 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2630 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2631 "strd", "\t$Rt, $Rt2, $addr, $offset",
2632 "$addr.base = $Rn_wb", []> {
2635 let Inst{23} = offset{8}; // U bit
2636 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2637 let Inst{19-16} = addr;
2638 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2639 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2640 let DecoderMethod = "DecodeAddrMode3Instruction";
2642 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2644 // STRT, STRBT, and STRHT
2646 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2647 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2648 IndexModePost, StFrm, IIC_iStore_bh_ru,
2649 "strbt", "\t$Rt, $addr, $offset",
2650 "$addr.base = $Rn_wb", []> {
2656 let Inst{23} = offset{12};
2657 let Inst{21} = 1; // overwrite
2658 let Inst{19-16} = addr;
2659 let Inst{11-5} = offset{11-5};
2661 let Inst{3-0} = offset{3-0};
2662 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2665 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2666 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2667 IndexModePost, StFrm, IIC_iStore_bh_ru,
2668 "strbt", "\t$Rt, $addr, $offset",
2669 "$addr.base = $Rn_wb", []> {
2675 let Inst{23} = offset{12};
2676 let Inst{21} = 1; // overwrite
2677 let Inst{19-16} = addr;
2678 let Inst{11-0} = offset{11-0};
2679 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2682 let mayStore = 1, neverHasSideEffects = 1 in {
2683 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2684 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2685 IndexModePost, StFrm, IIC_iStore_ru,
2686 "strt", "\t$Rt, $addr, $offset",
2687 "$addr.base = $Rn_wb", []> {
2693 let Inst{23} = offset{12};
2694 let Inst{21} = 1; // overwrite
2695 let Inst{19-16} = addr;
2696 let Inst{11-5} = offset{11-5};
2698 let Inst{3-0} = offset{3-0};
2699 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2702 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2703 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2704 IndexModePost, StFrm, IIC_iStore_ru,
2705 "strt", "\t$Rt, $addr, $offset",
2706 "$addr.base = $Rn_wb", []> {
2712 let Inst{23} = offset{12};
2713 let Inst{21} = 1; // overwrite
2714 let Inst{19-16} = addr;
2715 let Inst{11-0} = offset{11-0};
2716 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2721 multiclass AI3strT<bits<4> op, string opc> {
2722 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2723 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2724 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2725 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2727 let Inst{23} = offset{8};
2729 let Inst{11-8} = offset{7-4};
2730 let Inst{3-0} = offset{3-0};
2731 let AsmMatchConverter = "cvtStExtTWriteBackImm";
2733 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2734 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2735 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2736 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2738 let Inst{23} = Rm{4};
2741 let Inst{3-0} = Rm{3-0};
2742 let AsmMatchConverter = "cvtStExtTWriteBackReg";
2747 defm STRHT : AI3strT<0b1011, "strht">;
2750 //===----------------------------------------------------------------------===//
2751 // Load / store multiple Instructions.
2754 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
2755 InstrItinClass itin, InstrItinClass itin_upd> {
2756 // IA is the default, so no need for an explicit suffix on the
2757 // mnemonic here. Without it is the cannonical spelling.
2759 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2760 IndexModeNone, f, itin,
2761 !strconcat(asm, "${p}\t$Rn, $regs"), "", []> {
2762 let Inst{24-23} = 0b01; // Increment After
2763 let Inst{21} = 0; // No writeback
2764 let Inst{20} = L_bit;
2767 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2768 IndexModeUpd, f, itin_upd,
2769 !strconcat(asm, "${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2770 let Inst{24-23} = 0b01; // Increment After
2771 let Inst{21} = 1; // Writeback
2772 let Inst{20} = L_bit;
2774 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2777 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2778 IndexModeNone, f, itin,
2779 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
2780 let Inst{24-23} = 0b00; // Decrement After
2781 let Inst{21} = 0; // No writeback
2782 let Inst{20} = L_bit;
2785 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2786 IndexModeUpd, f, itin_upd,
2787 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2788 let Inst{24-23} = 0b00; // Decrement After
2789 let Inst{21} = 1; // Writeback
2790 let Inst{20} = L_bit;
2792 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2795 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2796 IndexModeNone, f, itin,
2797 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
2798 let Inst{24-23} = 0b10; // Decrement Before
2799 let Inst{21} = 0; // No writeback
2800 let Inst{20} = L_bit;
2803 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2804 IndexModeUpd, f, itin_upd,
2805 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2806 let Inst{24-23} = 0b10; // Decrement Before
2807 let Inst{21} = 1; // Writeback
2808 let Inst{20} = L_bit;
2810 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2813 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2814 IndexModeNone, f, itin,
2815 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
2816 let Inst{24-23} = 0b11; // Increment Before
2817 let Inst{21} = 0; // No writeback
2818 let Inst{20} = L_bit;
2821 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2822 IndexModeUpd, f, itin_upd,
2823 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2824 let Inst{24-23} = 0b11; // Increment Before
2825 let Inst{21} = 1; // Writeback
2826 let Inst{20} = L_bit;
2828 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2832 let neverHasSideEffects = 1 in {
2834 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2835 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
2837 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2838 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
2840 } // neverHasSideEffects
2842 // FIXME: remove when we have a way to marking a MI with these properties.
2843 // FIXME: Should pc be an implicit operand like PICADD, etc?
2844 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2845 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2846 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2847 reglist:$regs, variable_ops),
2848 4, IIC_iLoad_mBr, [],
2849 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2850 RegConstraint<"$Rn = $wb">;
2852 //===----------------------------------------------------------------------===//
2853 // Move Instructions.
2856 let neverHasSideEffects = 1 in
2857 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2858 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2862 let Inst{19-16} = 0b0000;
2863 let Inst{11-4} = 0b00000000;
2866 let Inst{15-12} = Rd;
2869 def : ARMInstAlias<"movs${p} $Rd, $Rm",
2870 (MOVr GPR:$Rd, GPR:$Rm, pred:$p, CPSR)>;
2872 // A version for the smaller set of tail call registers.
2873 let neverHasSideEffects = 1 in
2874 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2875 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2879 let Inst{11-4} = 0b00000000;
2882 let Inst{15-12} = Rd;
2885 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2886 DPSoRegRegFrm, IIC_iMOVsr,
2887 "mov", "\t$Rd, $src",
2888 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP {
2891 let Inst{15-12} = Rd;
2892 let Inst{19-16} = 0b0000;
2893 let Inst{11-8} = src{11-8};
2895 let Inst{6-5} = src{6-5};
2897 let Inst{3-0} = src{3-0};
2901 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
2902 DPSoRegImmFrm, IIC_iMOVsr,
2903 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
2907 let Inst{15-12} = Rd;
2908 let Inst{19-16} = 0b0000;
2909 let Inst{11-5} = src{11-5};
2911 let Inst{3-0} = src{3-0};
2915 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2916 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2917 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2921 let Inst{15-12} = Rd;
2922 let Inst{19-16} = 0b0000;
2923 let Inst{11-0} = imm;
2926 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2927 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
2929 "movw", "\t$Rd, $imm",
2930 [(set GPR:$Rd, imm0_65535:$imm)]>,
2931 Requires<[IsARM, HasV6T2]>, UnaryDP {
2934 let Inst{15-12} = Rd;
2935 let Inst{11-0} = imm{11-0};
2936 let Inst{19-16} = imm{15-12};
2939 let DecoderMethod = "DecodeArmMOVTWInstruction";
2942 def : InstAlias<"mov${p} $Rd, $imm",
2943 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
2946 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2947 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2949 let Constraints = "$src = $Rd" in {
2950 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
2951 (ins GPR:$src, imm0_65535_expr:$imm),
2953 "movt", "\t$Rd, $imm",
2955 (or (and GPR:$src, 0xffff),
2956 lo16AllZero:$imm))]>, UnaryDP,
2957 Requires<[IsARM, HasV6T2]> {
2960 let Inst{15-12} = Rd;
2961 let Inst{11-0} = imm{11-0};
2962 let Inst{19-16} = imm{15-12};
2965 let DecoderMethod = "DecodeArmMOVTWInstruction";
2968 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2969 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2973 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2974 Requires<[IsARM, HasV6T2]>;
2976 let Uses = [CPSR] in
2977 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2978 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2981 // These aren't really mov instructions, but we have to define them this way
2982 // due to flag operands.
2984 let Defs = [CPSR] in {
2985 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2986 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2988 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2989 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2993 //===----------------------------------------------------------------------===//
2994 // Extend Instructions.
2999 def SXTB : AI_ext_rrot<0b01101010,
3000 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3001 def SXTH : AI_ext_rrot<0b01101011,
3002 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3004 def SXTAB : AI_exta_rrot<0b01101010,
3005 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3006 def SXTAH : AI_exta_rrot<0b01101011,
3007 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3009 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3011 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3015 let AddedComplexity = 16 in {
3016 def UXTB : AI_ext_rrot<0b01101110,
3017 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3018 def UXTH : AI_ext_rrot<0b01101111,
3019 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3020 def UXTB16 : AI_ext_rrot<0b01101100,
3021 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3023 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3024 // The transformation should probably be done as a combiner action
3025 // instead so we can include a check for masking back in the upper
3026 // eight bits of the source into the lower eight bits of the result.
3027 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3028 // (UXTB16r_rot GPR:$Src, 3)>;
3029 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3030 (UXTB16 GPR:$Src, 1)>;
3032 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3033 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3034 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3035 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3038 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3039 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3042 def SBFX : I<(outs GPRnopc:$Rd),
3043 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3044 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3045 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3046 Requires<[IsARM, HasV6T2]> {
3051 let Inst{27-21} = 0b0111101;
3052 let Inst{6-4} = 0b101;
3053 let Inst{20-16} = width;
3054 let Inst{15-12} = Rd;
3055 let Inst{11-7} = lsb;
3059 def UBFX : I<(outs GPR:$Rd),
3060 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3061 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3062 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3063 Requires<[IsARM, HasV6T2]> {
3068 let Inst{27-21} = 0b0111111;
3069 let Inst{6-4} = 0b101;
3070 let Inst{20-16} = width;
3071 let Inst{15-12} = Rd;
3072 let Inst{11-7} = lsb;
3076 //===----------------------------------------------------------------------===//
3077 // Arithmetic Instructions.
3080 defm ADD : AsI1_bin_irs<0b0100, "add",
3081 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3082 BinOpFrag<(add node:$LHS, node:$RHS)>, "ADD", 1>;
3083 defm SUB : AsI1_bin_irs<0b0010, "sub",
3084 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3085 BinOpFrag<(sub node:$LHS, node:$RHS)>, "SUB">;
3087 // ADD and SUB with 's' bit set.
3089 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3090 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3091 // AdjustInstrPostInstrSelection where we determine whether or not to
3092 // set the "s" bit based on CPSR liveness.
3094 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3095 // support for an optional CPSR definition that corresponds to the DAG
3096 // node's second value. We can then eliminate the implicit def of CPSR.
3097 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3098 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3099 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3100 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3102 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3103 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>,
3105 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3106 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3109 defm RSB : AsI1_rbin_irs <0b0011, "rsb",
3110 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3111 BinOpFrag<(sub node:$LHS, node:$RHS)>, "RSB">;
3113 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3114 // CPSR and the implicit def of CPSR is not needed.
3115 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3116 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3118 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3119 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3122 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3123 // The assume-no-carry-in form uses the negation of the input since add/sub
3124 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3125 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3127 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3128 (SUBri GPR:$src, so_imm_neg:$imm)>;
3129 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3130 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3132 // The with-carry-in form matches bitwise not instead of the negation.
3133 // Effectively, the inverse interpretation of the carry flag already accounts
3134 // for part of the negation.
3135 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3136 (SBCri GPR:$src, so_imm_not:$imm)>;
3138 // Note: These are implemented in C++ code, because they have to generate
3139 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3141 // (mul X, 2^n+1) -> (add (X << n), X)
3142 // (mul X, 2^n-1) -> (rsb X, (X << n))
3144 // ARM Arithmetic Instruction
3145 // GPR:$dst = GPR:$a op GPR:$b
3146 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3147 list<dag> pattern = [],
3148 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3149 string asm = "\t$Rd, $Rn, $Rm">
3150 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
3154 let Inst{27-20} = op27_20;
3155 let Inst{11-4} = op11_4;
3156 let Inst{19-16} = Rn;
3157 let Inst{15-12} = Rd;
3161 // Saturating add/subtract
3163 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3164 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3165 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3166 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3167 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3168 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3169 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3170 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3172 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3173 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3176 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3177 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3178 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3179 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3180 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3181 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3182 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3183 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3184 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3185 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3186 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3187 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3189 // Signed/Unsigned add/subtract
3191 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3192 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3193 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3194 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3195 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3196 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3197 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3198 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3199 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3200 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3201 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3202 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3204 // Signed/Unsigned halving add/subtract
3206 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3207 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3208 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3209 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3210 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3211 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3212 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3213 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3214 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3215 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3216 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3217 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3219 // Unsigned Sum of Absolute Differences [and Accumulate].
3221 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3222 MulFrm /* for convenience */, NoItinerary, "usad8",
3223 "\t$Rd, $Rn, $Rm", []>,
3224 Requires<[IsARM, HasV6]> {
3228 let Inst{27-20} = 0b01111000;
3229 let Inst{15-12} = 0b1111;
3230 let Inst{7-4} = 0b0001;
3231 let Inst{19-16} = Rd;
3232 let Inst{11-8} = Rm;
3235 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3236 MulFrm /* for convenience */, NoItinerary, "usada8",
3237 "\t$Rd, $Rn, $Rm, $Ra", []>,
3238 Requires<[IsARM, HasV6]> {
3243 let Inst{27-20} = 0b01111000;
3244 let Inst{7-4} = 0b0001;
3245 let Inst{19-16} = Rd;
3246 let Inst{15-12} = Ra;
3247 let Inst{11-8} = Rm;
3251 // Signed/Unsigned saturate
3253 def SSAT : AI<(outs GPRnopc:$Rd),
3254 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3255 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3260 let Inst{27-21} = 0b0110101;
3261 let Inst{5-4} = 0b01;
3262 let Inst{20-16} = sat_imm;
3263 let Inst{15-12} = Rd;
3264 let Inst{11-7} = sh{4-0};
3265 let Inst{6} = sh{5};
3269 def SSAT16 : AI<(outs GPRnopc:$Rd),
3270 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3271 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3275 let Inst{27-20} = 0b01101010;
3276 let Inst{11-4} = 0b11110011;
3277 let Inst{15-12} = Rd;
3278 let Inst{19-16} = sat_imm;
3282 def USAT : AI<(outs GPRnopc:$Rd),
3283 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3284 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3289 let Inst{27-21} = 0b0110111;
3290 let Inst{5-4} = 0b01;
3291 let Inst{15-12} = Rd;
3292 let Inst{11-7} = sh{4-0};
3293 let Inst{6} = sh{5};
3294 let Inst{20-16} = sat_imm;
3298 def USAT16 : AI<(outs GPRnopc:$Rd),
3299 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3300 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3304 let Inst{27-20} = 0b01101110;
3305 let Inst{11-4} = 0b11110011;
3306 let Inst{15-12} = Rd;
3307 let Inst{19-16} = sat_imm;
3311 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3312 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3313 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3314 (USAT imm:$pos, GPRnopc:$a, 0)>;
3316 //===----------------------------------------------------------------------===//
3317 // Bitwise Instructions.
3320 defm AND : AsI1_bin_irs<0b0000, "and",
3321 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3322 BinOpFrag<(and node:$LHS, node:$RHS)>, "AND", 1>;
3323 defm ORR : AsI1_bin_irs<0b1100, "orr",
3324 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3325 BinOpFrag<(or node:$LHS, node:$RHS)>, "ORR", 1>;
3326 defm EOR : AsI1_bin_irs<0b0001, "eor",
3327 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3328 BinOpFrag<(xor node:$LHS, node:$RHS)>, "EOR", 1>;
3329 defm BIC : AsI1_bin_irs<0b1110, "bic",
3330 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3331 BinOpFrag<(and node:$LHS, (not node:$RHS))>, "BIC">;
3333 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3334 // like in the actual instruction encoding. The complexity of mapping the mask
3335 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3336 // instruction description.
3337 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3338 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3339 "bfc", "\t$Rd, $imm", "$src = $Rd",
3340 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3341 Requires<[IsARM, HasV6T2]> {
3344 let Inst{27-21} = 0b0111110;
3345 let Inst{6-0} = 0b0011111;
3346 let Inst{15-12} = Rd;
3347 let Inst{11-7} = imm{4-0}; // lsb
3348 let Inst{20-16} = imm{9-5}; // msb
3351 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3352 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3353 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3354 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3355 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3356 bf_inv_mask_imm:$imm))]>,
3357 Requires<[IsARM, HasV6T2]> {
3361 let Inst{27-21} = 0b0111110;
3362 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3363 let Inst{15-12} = Rd;
3364 let Inst{11-7} = imm{4-0}; // lsb
3365 let Inst{20-16} = imm{9-5}; // width
3369 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3370 "mvn", "\t$Rd, $Rm",
3371 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
3375 let Inst{19-16} = 0b0000;
3376 let Inst{11-4} = 0b00000000;
3377 let Inst{15-12} = Rd;
3380 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3381 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3382 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
3386 let Inst{19-16} = 0b0000;
3387 let Inst{15-12} = Rd;
3388 let Inst{11-5} = shift{11-5};
3390 let Inst{3-0} = shift{3-0};
3392 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3393 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3394 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
3398 let Inst{19-16} = 0b0000;
3399 let Inst{15-12} = Rd;
3400 let Inst{11-8} = shift{11-8};
3402 let Inst{6-5} = shift{6-5};
3404 let Inst{3-0} = shift{3-0};
3406 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3407 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3408 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3409 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
3413 let Inst{19-16} = 0b0000;
3414 let Inst{15-12} = Rd;
3415 let Inst{11-0} = imm;
3418 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3419 (BICri GPR:$src, so_imm_not:$imm)>;
3421 //===----------------------------------------------------------------------===//
3422 // Multiply Instructions.
3424 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3425 string opc, string asm, list<dag> pattern>
3426 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3430 let Inst{19-16} = Rd;
3431 let Inst{11-8} = Rm;
3434 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3435 string opc, string asm, list<dag> pattern>
3436 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3441 let Inst{19-16} = RdHi;
3442 let Inst{15-12} = RdLo;
3443 let Inst{11-8} = Rm;
3447 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3448 // property. Remove them when it's possible to add those properties
3449 // on an individual MachineInstr, not just an instuction description.
3450 let isCommutable = 1 in {
3451 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3452 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3453 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
3454 Requires<[IsARM, HasV6]> {
3455 let Inst{15-12} = 0b0000;
3458 let Constraints = "@earlyclobber $Rd" in
3459 def MULv5: ARMPseudoExpand<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
3460 pred:$p, cc_out:$s),
3462 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))],
3463 (MUL GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3464 Requires<[IsARM, NoV6]>;
3467 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3468 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3469 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3470 Requires<[IsARM, HasV6]> {
3472 let Inst{15-12} = Ra;
3475 let Constraints = "@earlyclobber $Rd" in
3476 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3477 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3479 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3480 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3481 Requires<[IsARM, NoV6]>;
3483 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3484 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3485 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3486 Requires<[IsARM, HasV6T2]> {
3491 let Inst{19-16} = Rd;
3492 let Inst{15-12} = Ra;
3493 let Inst{11-8} = Rm;
3497 // Extra precision multiplies with low / high results
3498 let neverHasSideEffects = 1 in {
3499 let isCommutable = 1 in {
3500 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3501 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3502 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3503 Requires<[IsARM, HasV6]>;
3505 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3506 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3507 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3508 Requires<[IsARM, HasV6]>;
3510 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3511 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3512 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3514 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3515 Requires<[IsARM, NoV6]>;
3517 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3518 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3520 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3521 Requires<[IsARM, NoV6]>;
3525 // Multiply + accumulate
3526 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3527 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3528 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3529 Requires<[IsARM, HasV6]>;
3530 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3531 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3532 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3533 Requires<[IsARM, HasV6]>;
3535 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3536 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3537 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3538 Requires<[IsARM, HasV6]> {
3543 let Inst{19-16} = RdHi;
3544 let Inst{15-12} = RdLo;
3545 let Inst{11-8} = Rm;
3549 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3550 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3551 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3553 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3554 Requires<[IsARM, NoV6]>;
3555 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3556 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3558 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3559 Requires<[IsARM, NoV6]>;
3560 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3561 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3563 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3564 Requires<[IsARM, NoV6]>;
3567 } // neverHasSideEffects
3569 // Most significant word multiply
3570 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3571 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3572 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3573 Requires<[IsARM, HasV6]> {
3574 let Inst{15-12} = 0b1111;
3577 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3578 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3579 Requires<[IsARM, HasV6]> {
3580 let Inst{15-12} = 0b1111;
3583 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3584 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3585 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3586 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3587 Requires<[IsARM, HasV6]>;
3589 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3590 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3591 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3592 Requires<[IsARM, HasV6]>;
3594 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3595 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3596 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
3597 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
3598 Requires<[IsARM, HasV6]>;
3600 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3601 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3602 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3603 Requires<[IsARM, HasV6]>;
3605 multiclass AI_smul<string opc, PatFrag opnode> {
3606 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3607 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3608 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3609 (sext_inreg GPR:$Rm, i16)))]>,
3610 Requires<[IsARM, HasV5TE]>;
3612 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3613 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3614 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3615 (sra GPR:$Rm, (i32 16))))]>,
3616 Requires<[IsARM, HasV5TE]>;
3618 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3619 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3620 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3621 (sext_inreg GPR:$Rm, i16)))]>,
3622 Requires<[IsARM, HasV5TE]>;
3624 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3625 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3626 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3627 (sra GPR:$Rm, (i32 16))))]>,
3628 Requires<[IsARM, HasV5TE]>;
3630 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3631 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3632 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3633 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3634 Requires<[IsARM, HasV5TE]>;
3636 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3637 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3638 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3639 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3640 Requires<[IsARM, HasV5TE]>;
3644 multiclass AI_smla<string opc, PatFrag opnode> {
3645 let DecoderMethod = "DecodeSMLAInstruction" in {
3646 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3647 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3648 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3649 [(set GPRnopc:$Rd, (add GPR:$Ra,
3650 (opnode (sext_inreg GPRnopc:$Rn, i16),
3651 (sext_inreg GPRnopc:$Rm, i16))))]>,
3652 Requires<[IsARM, HasV5TE]>;
3654 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3655 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3656 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3658 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3659 (sra GPRnopc:$Rm, (i32 16)))))]>,
3660 Requires<[IsARM, HasV5TE]>;
3662 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3663 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3664 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3666 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3667 (sext_inreg GPRnopc:$Rm, i16))))]>,
3668 Requires<[IsARM, HasV5TE]>;
3670 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3671 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3672 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3674 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3675 (sra GPRnopc:$Rm, (i32 16)))))]>,
3676 Requires<[IsARM, HasV5TE]>;
3678 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3679 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3680 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3682 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3683 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3684 Requires<[IsARM, HasV5TE]>;
3686 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3687 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3688 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3690 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3691 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3692 Requires<[IsARM, HasV5TE]>;
3696 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3697 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3699 // Halfword multiply accumulate long: SMLAL<x><y>.
3700 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3701 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3702 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3703 Requires<[IsARM, HasV5TE]>;
3705 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3706 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3707 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3708 Requires<[IsARM, HasV5TE]>;
3710 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3711 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3712 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3713 Requires<[IsARM, HasV5TE]>;
3715 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3716 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3717 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3718 Requires<[IsARM, HasV5TE]>;
3720 // Helper class for AI_smld.
3721 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3722 InstrItinClass itin, string opc, string asm>
3723 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3726 let Inst{27-23} = 0b01110;
3727 let Inst{22} = long;
3728 let Inst{21-20} = 0b00;
3729 let Inst{11-8} = Rm;
3736 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3737 InstrItinClass itin, string opc, string asm>
3738 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3740 let Inst{15-12} = 0b1111;
3741 let Inst{19-16} = Rd;
3743 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3744 InstrItinClass itin, string opc, string asm>
3745 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3748 let Inst{19-16} = Rd;
3749 let Inst{15-12} = Ra;
3751 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3752 InstrItinClass itin, string opc, string asm>
3753 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3756 let Inst{19-16} = RdHi;
3757 let Inst{15-12} = RdLo;
3760 multiclass AI_smld<bit sub, string opc> {
3762 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3763 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3764 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3766 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3767 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3768 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3770 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3771 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3772 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3774 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3775 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3776 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3780 defm SMLA : AI_smld<0, "smla">;
3781 defm SMLS : AI_smld<1, "smls">;
3783 multiclass AI_sdml<bit sub, string opc> {
3785 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3786 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3787 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3788 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3791 defm SMUA : AI_sdml<0, "smua">;
3792 defm SMUS : AI_sdml<1, "smus">;
3794 //===----------------------------------------------------------------------===//
3795 // Misc. Arithmetic Instructions.
3798 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3799 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3800 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3802 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3803 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3804 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3805 Requires<[IsARM, HasV6T2]>;
3807 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3808 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3809 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3811 let AddedComplexity = 5 in
3812 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3813 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3814 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3815 Requires<[IsARM, HasV6]>;
3817 let AddedComplexity = 5 in
3818 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3819 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3820 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3821 Requires<[IsARM, HasV6]>;
3823 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3824 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3827 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3828 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3829 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3830 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3831 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3833 Requires<[IsARM, HasV6]>;
3835 // Alternate cases for PKHBT where identities eliminate some nodes.
3836 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3837 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
3838 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
3839 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
3841 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3842 // will match the pattern below.
3843 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
3844 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
3845 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3846 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
3847 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
3849 Requires<[IsARM, HasV6]>;
3851 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3852 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3853 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3854 (srl GPRnopc:$src2, imm16_31:$sh)),
3855 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
3856 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3857 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
3858 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
3860 //===----------------------------------------------------------------------===//
3861 // Comparison Instructions...
3864 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3865 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3866 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3868 // ARMcmpZ can re-use the above instruction definitions.
3869 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3870 (CMPri GPR:$src, so_imm:$imm)>;
3871 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3872 (CMPrr GPR:$src, GPR:$rhs)>;
3873 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
3874 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
3875 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
3876 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
3878 // FIXME: We have to be careful when using the CMN instruction and comparison
3879 // with 0. One would expect these two pieces of code should give identical
3895 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3896 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3897 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3898 // value of r0 and the carry bit (because the "carry bit" parameter to
3899 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3900 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3901 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3902 // parameter to AddWithCarry is defined as 0).
3904 // When x is 0 and unsigned:
3908 // ~x + 1 = 0x1 0000 0000
3909 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3911 // Therefore, we should disable CMN when comparing against zero, until we can
3912 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3913 // when it's a comparison which doesn't look at the 'carry' flag).
3915 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3917 // This is related to <rdar://problem/7569620>.
3919 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3920 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3922 // Note that TST/TEQ don't set all the same flags that CMP does!
3923 defm TST : AI1_cmp_irs<0b1000, "tst",
3924 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3925 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3926 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3927 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3928 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3930 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
3931 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3932 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
3934 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3935 // (CMNri GPR:$src, so_imm_neg:$imm)>;
3937 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3938 (CMNzri GPR:$src, so_imm_neg:$imm)>;
3940 // Pseudo i64 compares for some floating point compares.
3941 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3943 def BCCi64 : PseudoInst<(outs),
3944 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3946 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3948 def BCCZi64 : PseudoInst<(outs),
3949 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3950 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3951 } // usesCustomInserter
3954 // Conditional moves
3955 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3956 // a two-value operand where a dag node expects two operands. :(
3957 let neverHasSideEffects = 1 in {
3958 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3960 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3961 RegConstraint<"$false = $Rd">;
3962 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
3963 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
3965 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
3966 imm:$cc, CCR:$ccr))*/]>,
3967 RegConstraint<"$false = $Rd">;
3968 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
3969 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
3971 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
3972 imm:$cc, CCR:$ccr))*/]>,
3973 RegConstraint<"$false = $Rd">;
3976 let isMoveImm = 1 in
3977 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3978 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
3981 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3983 let isMoveImm = 1 in
3984 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3985 (ins GPR:$false, so_imm:$imm, pred:$p),
3987 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3988 RegConstraint<"$false = $Rd">;
3990 // Two instruction predicate mov immediate.
3991 let isMoveImm = 1 in
3992 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
3993 (ins GPR:$false, i32imm:$src, pred:$p),
3994 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3996 let isMoveImm = 1 in
3997 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
3998 (ins GPR:$false, so_imm:$imm, pred:$p),
4000 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
4001 RegConstraint<"$false = $Rd">;
4002 } // neverHasSideEffects
4004 //===----------------------------------------------------------------------===//
4005 // Atomic operations intrinsics
4008 def MemBarrierOptOperand : AsmOperandClass {
4009 let Name = "MemBarrierOpt";
4010 let ParserMethod = "parseMemBarrierOptOperand";
4012 def memb_opt : Operand<i32> {
4013 let PrintMethod = "printMemBOption";
4014 let ParserMatchClass = MemBarrierOptOperand;
4015 let DecoderMethod = "DecodeMemBarrierOption";
4018 // memory barriers protect the atomic sequences
4019 let hasSideEffects = 1 in {
4020 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4021 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
4022 Requires<[IsARM, HasDB]> {
4024 let Inst{31-4} = 0xf57ff05;
4025 let Inst{3-0} = opt;
4029 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4030 "dsb", "\t$opt", []>,
4031 Requires<[IsARM, HasDB]> {
4033 let Inst{31-4} = 0xf57ff04;
4034 let Inst{3-0} = opt;
4037 // ISB has only full system option
4038 def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4039 "isb", "\t$opt", []>,
4040 Requires<[IsARM, HasDB]> {
4042 let Inst{31-4} = 0xf57ff06;
4043 let Inst{3-0} = opt;
4046 // Pseudo isntruction that combines movs + predicated rsbmi
4047 // to implement integer ABS
4048 let usesCustomInserter = 1, Defs = [CPSR] in {
4049 def ABS : ARMPseudoInst<
4050 (outs GPR:$dst), (ins GPR:$src),
4051 8, NoItinerary, []>;
4054 let usesCustomInserter = 1 in {
4055 let Defs = [CPSR] in {
4056 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4057 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4058 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
4059 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4060 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4061 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
4062 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4063 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4064 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
4065 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4066 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4067 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4068 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4069 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4070 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4071 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4072 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4073 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4074 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4075 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4076 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4077 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4078 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4079 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4080 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4081 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4082 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4083 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4084 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4085 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4086 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4087 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4088 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4089 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4090 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4091 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4092 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4093 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4094 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4095 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4096 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4097 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4098 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4099 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4100 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4101 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4102 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4103 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4104 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4105 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4106 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4107 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4108 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4109 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4110 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4111 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4112 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4113 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4114 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4115 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4116 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4117 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4118 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4119 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4120 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4121 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4122 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4123 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4124 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4125 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4126 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4127 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4128 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4129 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4130 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4131 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4132 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4133 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4134 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4135 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4136 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4137 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4138 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4139 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4140 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4141 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4142 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4143 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4144 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4145 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4147 def ATOMIC_SWAP_I8 : PseudoInst<
4148 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4149 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4150 def ATOMIC_SWAP_I16 : PseudoInst<
4151 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4152 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4153 def ATOMIC_SWAP_I32 : PseudoInst<
4154 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4155 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4157 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4158 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4159 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4160 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4161 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4162 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4163 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4164 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4165 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4169 let mayLoad = 1 in {
4170 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4172 "ldrexb", "\t$Rt, $addr", []>;
4173 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4174 NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
4175 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4176 NoItinerary, "ldrex", "\t$Rt, $addr", []>;
4177 let hasExtraDefRegAllocReq = 1 in
4178 def LDREXD: AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2),(ins addr_offset_none:$addr),
4179 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []> {
4180 let DecoderMethod = "DecodeDoubleRegLoad";
4184 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4185 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4186 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
4187 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4188 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
4189 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4190 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
4193 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
4194 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4195 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr),
4196 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []> {
4197 let DecoderMethod = "DecodeDoubleRegStore";
4200 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
4201 Requires<[IsARM, HasV7]> {
4202 let Inst{31-0} = 0b11110101011111111111000000011111;
4205 // SWP/SWPB are deprecated in V6/V7.
4206 let mayLoad = 1, mayStore = 1 in {
4207 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
4209 def SWPB: AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
4213 //===----------------------------------------------------------------------===//
4214 // Coprocessor Instructions.
4217 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4218 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4219 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4220 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4221 imm:$CRm, imm:$opc2)]> {
4229 let Inst{3-0} = CRm;
4231 let Inst{7-5} = opc2;
4232 let Inst{11-8} = cop;
4233 let Inst{15-12} = CRd;
4234 let Inst{19-16} = CRn;
4235 let Inst{23-20} = opc1;
4238 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4239 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4240 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4241 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4242 imm:$CRm, imm:$opc2)]> {
4243 let Inst{31-28} = 0b1111;
4251 let Inst{3-0} = CRm;
4253 let Inst{7-5} = opc2;
4254 let Inst{11-8} = cop;
4255 let Inst{15-12} = CRd;
4256 let Inst{19-16} = CRn;
4257 let Inst{23-20} = opc1;
4260 class ACI<dag oops, dag iops, string opc, string asm,
4261 IndexMode im = IndexModeNone>
4262 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4264 let Inst{27-25} = 0b110;
4266 class ACInoP<dag oops, dag iops, string opc, string asm,
4267 IndexMode im = IndexModeNone>
4268 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4270 let Inst{31-28} = 0b1111;
4271 let Inst{27-25} = 0b110;
4273 multiclass LdStCop<bit load, bit Dbit, string asm> {
4274 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4275 asm, "\t$cop, $CRd, $addr"> {
4279 let Inst{24} = 1; // P = 1
4280 let Inst{23} = addr{8};
4281 let Inst{22} = Dbit;
4282 let Inst{21} = 0; // W = 0
4283 let Inst{20} = load;
4284 let Inst{19-16} = addr{12-9};
4285 let Inst{15-12} = CRd;
4286 let Inst{11-8} = cop;
4287 let Inst{7-0} = addr{7-0};
4288 let DecoderMethod = "DecodeCopMemInstruction";
4290 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4291 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4295 let Inst{24} = 1; // P = 1
4296 let Inst{23} = addr{8};
4297 let Inst{22} = Dbit;
4298 let Inst{21} = 1; // W = 1
4299 let Inst{20} = load;
4300 let Inst{19-16} = addr{12-9};
4301 let Inst{15-12} = CRd;
4302 let Inst{11-8} = cop;
4303 let Inst{7-0} = addr{7-0};
4304 let DecoderMethod = "DecodeCopMemInstruction";
4306 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4307 postidx_imm8s4:$offset),
4308 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4313 let Inst{24} = 0; // P = 0
4314 let Inst{23} = offset{8};
4315 let Inst{22} = Dbit;
4316 let Inst{21} = 1; // W = 1
4317 let Inst{20} = load;
4318 let Inst{19-16} = addr;
4319 let Inst{15-12} = CRd;
4320 let Inst{11-8} = cop;
4321 let Inst{7-0} = offset{7-0};
4322 let DecoderMethod = "DecodeCopMemInstruction";
4324 def _OPTION : ACI<(outs),
4325 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4326 coproc_option_imm:$option),
4327 asm, "\t$cop, $CRd, $addr, $option"> {
4332 let Inst{24} = 0; // P = 0
4333 let Inst{23} = 1; // U = 1
4334 let Inst{22} = Dbit;
4335 let Inst{21} = 0; // W = 0
4336 let Inst{20} = load;
4337 let Inst{19-16} = addr;
4338 let Inst{15-12} = CRd;
4339 let Inst{11-8} = cop;
4340 let Inst{7-0} = option;
4341 let DecoderMethod = "DecodeCopMemInstruction";
4344 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4345 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4346 asm, "\t$cop, $CRd, $addr"> {
4350 let Inst{24} = 1; // P = 1
4351 let Inst{23} = addr{8};
4352 let Inst{22} = Dbit;
4353 let Inst{21} = 0; // W = 0
4354 let Inst{20} = load;
4355 let Inst{19-16} = addr{12-9};
4356 let Inst{15-12} = CRd;
4357 let Inst{11-8} = cop;
4358 let Inst{7-0} = addr{7-0};
4359 let DecoderMethod = "DecodeCopMemInstruction";
4361 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4362 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4366 let Inst{24} = 1; // P = 1
4367 let Inst{23} = addr{8};
4368 let Inst{22} = Dbit;
4369 let Inst{21} = 1; // W = 1
4370 let Inst{20} = load;
4371 let Inst{19-16} = addr{12-9};
4372 let Inst{15-12} = CRd;
4373 let Inst{11-8} = cop;
4374 let Inst{7-0} = addr{7-0};
4375 let DecoderMethod = "DecodeCopMemInstruction";
4377 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4378 postidx_imm8s4:$offset),
4379 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4384 let Inst{24} = 0; // P = 0
4385 let Inst{23} = offset{8};
4386 let Inst{22} = Dbit;
4387 let Inst{21} = 1; // W = 1
4388 let Inst{20} = load;
4389 let Inst{19-16} = addr;
4390 let Inst{15-12} = CRd;
4391 let Inst{11-8} = cop;
4392 let Inst{7-0} = offset{7-0};
4393 let DecoderMethod = "DecodeCopMemInstruction";
4395 def _OPTION : ACInoP<(outs),
4396 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4397 coproc_option_imm:$option),
4398 asm, "\t$cop, $CRd, $addr, $option"> {
4403 let Inst{24} = 0; // P = 0
4404 let Inst{23} = 1; // U = 1
4405 let Inst{22} = Dbit;
4406 let Inst{21} = 0; // W = 0
4407 let Inst{20} = load;
4408 let Inst{19-16} = addr;
4409 let Inst{15-12} = CRd;
4410 let Inst{11-8} = cop;
4411 let Inst{7-0} = option;
4412 let DecoderMethod = "DecodeCopMemInstruction";
4416 defm LDC : LdStCop <1, 0, "ldc">;
4417 defm LDCL : LdStCop <1, 1, "ldcl">;
4418 defm STC : LdStCop <0, 0, "stc">;
4419 defm STCL : LdStCop <0, 1, "stcl">;
4420 defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
4421 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
4422 defm STC2 : LdSt2Cop<0, 0, "stc2">;
4423 defm STC2L : LdSt2Cop<0, 1, "stc2l">;
4425 //===----------------------------------------------------------------------===//
4426 // Move between coprocessor and ARM core register.
4429 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4431 : ABI<0b1110, oops, iops, NoItinerary, opc,
4432 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4433 let Inst{20} = direction;
4443 let Inst{15-12} = Rt;
4444 let Inst{11-8} = cop;
4445 let Inst{23-21} = opc1;
4446 let Inst{7-5} = opc2;
4447 let Inst{3-0} = CRm;
4448 let Inst{19-16} = CRn;
4451 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4453 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4454 c_imm:$CRm, imm0_7:$opc2),
4455 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4456 imm:$CRm, imm:$opc2)]>;
4457 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4459 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4462 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4463 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4465 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4467 : ABXI<0b1110, oops, iops, NoItinerary,
4468 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4469 let Inst{31-28} = 0b1111;
4470 let Inst{20} = direction;
4480 let Inst{15-12} = Rt;
4481 let Inst{11-8} = cop;
4482 let Inst{23-21} = opc1;
4483 let Inst{7-5} = opc2;
4484 let Inst{3-0} = CRm;
4485 let Inst{19-16} = CRn;
4488 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4490 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4491 c_imm:$CRm, imm0_7:$opc2),
4492 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4493 imm:$CRm, imm:$opc2)]>;
4494 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4496 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4499 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4500 imm:$CRm, imm:$opc2),
4501 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4503 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4504 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4505 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
4506 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4507 let Inst{23-21} = 0b010;
4508 let Inst{20} = direction;
4516 let Inst{15-12} = Rt;
4517 let Inst{19-16} = Rt2;
4518 let Inst{11-8} = cop;
4519 let Inst{7-4} = opc1;
4520 let Inst{3-0} = CRm;
4523 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4524 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4526 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4528 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4529 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4530 GPR:$Rt, GPR:$Rt2, c_imm:$CRm), NoItinerary,
4531 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4532 let Inst{31-28} = 0b1111;
4533 let Inst{23-21} = 0b010;
4534 let Inst{20} = direction;
4542 let Inst{15-12} = Rt;
4543 let Inst{19-16} = Rt2;
4544 let Inst{11-8} = cop;
4545 let Inst{7-4} = opc1;
4546 let Inst{3-0} = CRm;
4549 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4550 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4552 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4554 //===----------------------------------------------------------------------===//
4555 // Move between special register and ARM core register
4558 // Move to ARM core register from Special Register
4559 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
4560 "mrs", "\t$Rd, apsr", []> {
4562 let Inst{23-16} = 0b00001111;
4563 let Inst{15-12} = Rd;
4564 let Inst{7-4} = 0b0000;
4567 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPR:$Rd, pred:$p)>, Requires<[IsARM]>;
4569 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
4570 "mrs", "\t$Rd, spsr", []> {
4572 let Inst{23-16} = 0b01001111;
4573 let Inst{15-12} = Rd;
4574 let Inst{7-4} = 0b0000;
4577 // Move from ARM core register to Special Register
4579 // No need to have both system and application versions, the encodings are the
4580 // same and the assembly parser has no way to distinguish between them. The mask
4581 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4582 // the mask with the fields to be accessed in the special register.
4583 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4584 "msr", "\t$mask, $Rn", []> {
4589 let Inst{22} = mask{4}; // R bit
4590 let Inst{21-20} = 0b10;
4591 let Inst{19-16} = mask{3-0};
4592 let Inst{15-12} = 0b1111;
4593 let Inst{11-4} = 0b00000000;
4597 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4598 "msr", "\t$mask, $a", []> {
4603 let Inst{22} = mask{4}; // R bit
4604 let Inst{21-20} = 0b10;
4605 let Inst{19-16} = mask{3-0};
4606 let Inst{15-12} = 0b1111;
4610 //===----------------------------------------------------------------------===//
4614 // __aeabi_read_tp preserves the registers r1-r3.
4615 // This is a pseudo inst so that we can get the encoding right,
4616 // complete with fixup for the aeabi_read_tp function.
4618 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4619 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4620 [(set R0, ARMthread_pointer)]>;
4623 //===----------------------------------------------------------------------===//
4624 // SJLJ Exception handling intrinsics
4625 // eh_sjlj_setjmp() is an instruction sequence to store the return
4626 // address and save #0 in R0 for the non-longjmp case.
4627 // Since by its nature we may be coming from some other function to get
4628 // here, and we're using the stack frame for the containing function to
4629 // save/restore registers, we can't keep anything live in regs across
4630 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4631 // when we get here from a longjmp(). We force everything out of registers
4632 // except for our own input by listing the relevant registers in Defs. By
4633 // doing so, we also cause the prologue/epilogue code to actively preserve
4634 // all of the callee-saved resgisters, which is exactly what we want.
4635 // A constant value is passed in $val, and we use the location as a scratch.
4637 // These are pseudo-instructions and are lowered to individual MC-insts, so
4638 // no encoding information is necessary.
4640 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4641 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ], hasSideEffects = 1, isBarrier = 1,
4642 usesCustomInserter = 1 in {
4643 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4645 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4646 Requires<[IsARM, HasVFP2]>;
4650 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4651 hasSideEffects = 1, isBarrier = 1 in {
4652 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4654 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4655 Requires<[IsARM, NoVFP]>;
4658 // FIXME: Non-Darwin version(s)
4659 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4660 Defs = [ R7, LR, SP ] in {
4661 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4663 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4664 Requires<[IsARM, IsDarwin]>;
4667 // eh.sjlj.dispatchsetup pseudo-instruction.
4668 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
4669 // handled when the pseudo is expanded (which happens before any passes
4670 // that need the instruction size).
4671 let isBarrier = 1, hasSideEffects = 1 in
4672 def eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
4674 //===----------------------------------------------------------------------===//
4675 // Non-Instruction Patterns
4678 // ARMv4 indirect branch using (MOVr PC, dst)
4679 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4680 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4681 4, IIC_Br, [(brind GPR:$dst)],
4682 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4683 Requires<[IsARM, NoV4T]>;
4685 // Large immediate handling.
4687 // 32-bit immediate using two piece so_imms or movw + movt.
4688 // This is a single pseudo instruction, the benefit is that it can be remat'd
4689 // as a single unit instead of having to handle reg inputs.
4690 // FIXME: Remove this when we can do generalized remat.
4691 let isReMaterializable = 1, isMoveImm = 1 in
4692 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4693 [(set GPR:$dst, (arm_i32imm:$src))]>,
4696 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4697 // It also makes it possible to rematerialize the instructions.
4698 // FIXME: Remove this when we can do generalized remat and when machine licm
4699 // can properly the instructions.
4700 let isReMaterializable = 1 in {
4701 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4703 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4704 Requires<[IsARM, UseMovt]>;
4706 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4708 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4709 Requires<[IsARM, UseMovt]>;
4711 let AddedComplexity = 10 in
4712 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4714 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4715 Requires<[IsARM, UseMovt]>;
4716 } // isReMaterializable
4718 // ConstantPool, GlobalAddress, and JumpTable
4719 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4720 Requires<[IsARM, DontUseMovt]>;
4721 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4722 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4723 Requires<[IsARM, UseMovt]>;
4724 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4725 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4727 // TODO: add,sub,and, 3-instr forms?
4730 def : ARMPat<(ARMtcret tcGPR:$dst),
4731 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
4733 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
4734 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
4736 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
4737 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
4739 def : ARMPat<(ARMtcret tcGPR:$dst),
4740 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
4742 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
4743 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
4745 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
4746 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
4749 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
4750 Requires<[IsARM, IsNotDarwin]>;
4751 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
4752 Requires<[IsARM, IsDarwin]>;
4754 // zextload i1 -> zextload i8
4755 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4756 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4758 // extload -> zextload
4759 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4760 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4761 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4762 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4764 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4766 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4767 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4770 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4771 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4772 (SMULBB GPR:$a, GPR:$b)>;
4773 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4774 (SMULBB GPR:$a, GPR:$b)>;
4775 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4776 (sra GPR:$b, (i32 16))),
4777 (SMULBT GPR:$a, GPR:$b)>;
4778 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
4779 (SMULBT GPR:$a, GPR:$b)>;
4780 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4781 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4782 (SMULTB GPR:$a, GPR:$b)>;
4783 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
4784 (SMULTB GPR:$a, GPR:$b)>;
4785 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4787 (SMULWB GPR:$a, GPR:$b)>;
4788 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
4789 (SMULWB GPR:$a, GPR:$b)>;
4791 def : ARMV5TEPat<(add GPR:$acc,
4792 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4793 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4794 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4795 def : ARMV5TEPat<(add GPR:$acc,
4796 (mul sext_16_node:$a, sext_16_node:$b)),
4797 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4798 def : ARMV5TEPat<(add GPR:$acc,
4799 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4800 (sra GPR:$b, (i32 16)))),
4801 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4802 def : ARMV5TEPat<(add GPR:$acc,
4803 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
4804 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4805 def : ARMV5TEPat<(add GPR:$acc,
4806 (mul (sra GPR:$a, (i32 16)),
4807 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4808 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4809 def : ARMV5TEPat<(add GPR:$acc,
4810 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
4811 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4812 def : ARMV5TEPat<(add GPR:$acc,
4813 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4815 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4816 def : ARMV5TEPat<(add GPR:$acc,
4817 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
4818 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4821 // Pre-v7 uses MCR for synchronization barriers.
4822 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
4823 Requires<[IsARM, HasV6]>;
4825 // SXT/UXT with no rotate
4826 let AddedComplexity = 16 in {
4827 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
4828 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
4829 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
4830 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
4831 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
4832 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
4833 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
4836 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
4837 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
4839 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
4840 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
4841 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
4842 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
4844 // Atomic load/store patterns
4845 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
4846 (LDRBrs ldst_so_reg:$src)>;
4847 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
4848 (LDRBi12 addrmode_imm12:$src)>;
4849 def : ARMPat<(atomic_load_16 addrmode3:$src),
4850 (LDRH addrmode3:$src)>;
4851 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
4852 (LDRrs ldst_so_reg:$src)>;
4853 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
4854 (LDRi12 addrmode_imm12:$src)>;
4855 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
4856 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
4857 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
4858 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
4859 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
4860 (STRH GPR:$val, addrmode3:$ptr)>;
4861 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
4862 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
4863 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
4864 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
4867 //===----------------------------------------------------------------------===//
4871 include "ARMInstrThumb.td"
4873 //===----------------------------------------------------------------------===//
4877 include "ARMInstrThumb2.td"
4879 //===----------------------------------------------------------------------===//
4880 // Floating Point Support
4883 include "ARMInstrVFP.td"
4885 //===----------------------------------------------------------------------===//
4886 // Advanced SIMD (NEON) Support
4889 include "ARMInstrNEON.td"
4891 //===----------------------------------------------------------------------===//
4892 // Assembler aliases
4896 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
4897 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
4898 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
4900 // System instructions
4901 def : MnemonicAlias<"swi", "svc">;
4903 // Load / Store Multiple
4904 def : MnemonicAlias<"ldmfd", "ldm">;
4905 def : MnemonicAlias<"ldmia", "ldm">;
4906 def : MnemonicAlias<"ldmea", "ldmdb">;
4907 def : MnemonicAlias<"stmfd", "stmdb">;
4908 def : MnemonicAlias<"stmia", "stm">;
4909 def : MnemonicAlias<"stmea", "stm">;
4911 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4912 // shift amount is zero (i.e., unspecified).
4913 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4914 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4915 Requires<[IsARM, HasV6]>;
4916 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4917 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4918 Requires<[IsARM, HasV6]>;
4920 // PUSH/POP aliases for STM/LDM
4921 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
4922 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4924 // SSAT/USAT optional shift operand.
4925 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4926 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4927 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4928 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4931 // Extend instruction optional rotate operand.
4932 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4933 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4934 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4935 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4936 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4937 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4938 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
4939 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4940 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
4941 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4942 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
4943 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4945 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4946 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4947 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4948 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4949 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4950 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4951 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
4952 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4953 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
4954 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4955 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
4956 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4960 def : MnemonicAlias<"rfefa", "rfeda">;
4961 def : MnemonicAlias<"rfeea", "rfedb">;
4962 def : MnemonicAlias<"rfefd", "rfeia">;
4963 def : MnemonicAlias<"rfeed", "rfeib">;
4964 def : MnemonicAlias<"rfe", "rfeia">;
4967 def : MnemonicAlias<"srsfa", "srsda">;
4968 def : MnemonicAlias<"srsea", "srsdb">;
4969 def : MnemonicAlias<"srsfd", "srsia">;
4970 def : MnemonicAlias<"srsed", "srsib">;
4971 def : MnemonicAlias<"srs", "srsia">;
4974 def : MnemonicAlias<"qsubaddx", "qsax">;
4976 def : MnemonicAlias<"saddsubx", "sasx">;
4977 // SHASX == SHADDSUBX
4978 def : MnemonicAlias<"shaddsubx", "shasx">;
4979 // SHSAX == SHSUBADDX
4980 def : MnemonicAlias<"shsubaddx", "shsax">;
4982 def : MnemonicAlias<"ssubaddx", "ssax">;
4984 def : MnemonicAlias<"uaddsubx", "uasx">;
4985 // UHASX == UHADDSUBX
4986 def : MnemonicAlias<"uhaddsubx", "uhasx">;
4987 // UHSAX == UHSUBADDX
4988 def : MnemonicAlias<"uhsubaddx", "uhsax">;
4989 // UQASX == UQADDSUBX
4990 def : MnemonicAlias<"uqaddsubx", "uqasx">;
4991 // UQSAX == UQSUBADDX
4992 def : MnemonicAlias<"uqsubaddx", "uqsax">;
4994 def : MnemonicAlias<"usubaddx", "usax">;
4996 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
4998 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
4999 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5001 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5002 // LSR, ROR, and RRX instructions.
5003 // FIXME: We need C++ parser hooks to map the alias to the MOV
5004 // encoding. It seems we should be able to do that sort of thing
5005 // in tblgen, but it could get ugly.
5006 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5007 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5009 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5010 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5012 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5013 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5015 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5016 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5018 // shifter instructions also support a two-operand form.
5019 def : ARMInstAlias<"asr${s}${p} $Rm, $imm",
5020 (ASRi GPR:$Rm, GPR:$Rm, imm0_32:$imm, pred:$p, cc_out:$s)>;
5021 def : ARMInstAlias<"lsr${s}${p} $Rm, $imm",
5022 (LSRi GPR:$Rm, GPR:$Rm, imm0_32:$imm, pred:$p, cc_out:$s)>;
5023 def : ARMInstAlias<"lsl${s}${p} $Rm, $imm",
5024 (LSLi GPR:$Rm, GPR:$Rm, imm0_31:$imm, pred:$p, cc_out:$s)>;
5025 def : ARMInstAlias<"ror${s}${p} $Rm, $imm",
5026 (RORi GPR:$Rm, GPR:$Rm, imm0_31:$imm, pred:$p, cc_out:$s)>;
5029 // 'mul' instruction can be specified with only two operands.
5030 def : ARMInstAlias<"mul${s}${p} $Rn, $Rm",
5031 (MUL rGPR:$Rn, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;