1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisInt<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
68 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
70 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
71 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
75 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
76 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
77 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
79 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
80 [SDNPHasChain, SDNPOutGlue]>;
81 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
82 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
84 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
85 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
87 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
88 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
90 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
91 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
94 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
95 [SDNPHasChain, SDNPOptInGlue]>;
97 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
100 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
101 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
103 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
105 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
108 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
111 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
114 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
115 [SDNPOutGlue, SDNPCommutative]>;
117 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
119 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
120 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
121 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
123 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
124 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
125 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
126 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
127 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
128 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
129 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
132 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
134 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
136 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
137 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
139 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
141 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
142 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
145 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
147 //===----------------------------------------------------------------------===//
148 // ARM Instruction Predicate Definitions.
150 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
151 AssemblerPredicate<"HasV4TOps">;
152 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
153 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
154 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
155 AssemblerPredicate<"HasV5TEOps">;
156 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
157 AssemblerPredicate<"HasV6Ops">;
158 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
159 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
160 AssemblerPredicate<"HasV6T2Ops">;
161 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
162 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
163 AssemblerPredicate<"HasV7Ops">;
164 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
165 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
166 AssemblerPredicate<"FeatureVFP2">;
167 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
168 AssemblerPredicate<"FeatureVFP3">;
169 def HasNEON : Predicate<"Subtarget->hasNEON()">,
170 AssemblerPredicate<"FeatureNEON">;
171 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
172 AssemblerPredicate<"FeatureFP16">;
173 def HasDivide : Predicate<"Subtarget->hasDivide()">,
174 AssemblerPredicate<"FeatureHWDiv">;
175 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
176 AssemblerPredicate<"FeatureT2XtPk">;
177 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
178 AssemblerPredicate<"FeatureDSPThumb2">;
179 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
180 AssemblerPredicate<"FeatureDB">;
181 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
182 AssemblerPredicate<"FeatureMP">;
183 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
184 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
185 def IsThumb : Predicate<"Subtarget->isThumb()">,
186 AssemblerPredicate<"ModeThumb">;
187 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
188 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
189 AssemblerPredicate<"ModeThumb,FeatureThumb2">;
190 def IsARM : Predicate<"!Subtarget->isThumb()">,
191 AssemblerPredicate<"!ModeThumb">;
192 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
193 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
195 // FIXME: Eventually this will be just "hasV6T2Ops".
196 def UseMovt : Predicate<"Subtarget->useMovt()">;
197 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
198 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
200 //===----------------------------------------------------------------------===//
201 // ARM Flag Definitions.
203 class RegConstraint<string C> {
204 string Constraints = C;
207 //===----------------------------------------------------------------------===//
208 // ARM specific transformation functions and pattern fragments.
211 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
212 // so_imm_neg def below.
213 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
214 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
217 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
218 // so_imm_not def below.
219 def so_imm_not_XFORM : SDNodeXForm<imm, [{
220 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
223 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
224 def imm1_15 : ImmLeaf<i32, [{
225 return (int32_t)Imm >= 1 && (int32_t)Imm < 16;
228 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
229 def imm16_31 : ImmLeaf<i32, [{
230 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
235 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
236 }], so_imm_neg_XFORM>;
240 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
241 }], so_imm_not_XFORM>;
243 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
244 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
245 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
248 /// Split a 32-bit immediate into two 16 bit parts.
249 def hi16 : SDNodeXForm<imm, [{
250 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
253 def lo16AllZero : PatLeaf<(i32 imm), [{
254 // Returns true if all low 16-bits are 0.
255 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
258 /// imm0_65535 - An immediate is in the range [0.65535].
259 def Imm0_65535AsmOperand: AsmOperandClass { let Name = "Imm0_65535"; }
260 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
261 return Imm >= 0 && Imm < 65536;
263 let ParserMatchClass = Imm0_65535AsmOperand;
266 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
267 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
269 /// adde and sube predicates - True based on whether the carry flag output
270 /// will be needed or not.
271 def adde_dead_carry :
272 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
273 [{return !N->hasAnyUseOfValue(1);}]>;
274 def sube_dead_carry :
275 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
276 [{return !N->hasAnyUseOfValue(1);}]>;
277 def adde_live_carry :
278 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
279 [{return N->hasAnyUseOfValue(1);}]>;
280 def sube_live_carry :
281 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
282 [{return N->hasAnyUseOfValue(1);}]>;
284 // An 'and' node with a single use.
285 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
286 return N->hasOneUse();
289 // An 'xor' node with a single use.
290 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
291 return N->hasOneUse();
294 // An 'fmul' node with a single use.
295 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
296 return N->hasOneUse();
299 // An 'fadd' node which checks for single non-hazardous use.
300 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
301 return hasNoVMLxHazardUse(N);
304 // An 'fsub' node which checks for single non-hazardous use.
305 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
306 return hasNoVMLxHazardUse(N);
309 //===----------------------------------------------------------------------===//
310 // Operand Definitions.
314 // FIXME: rename brtarget to t2_brtarget
315 def brtarget : Operand<OtherVT> {
316 let EncoderMethod = "getBranchTargetOpValue";
317 let OperandType = "OPERAND_PCREL";
318 let DecoderMethod = "DecodeT2BROperand";
321 // FIXME: get rid of this one?
322 def uncondbrtarget : Operand<OtherVT> {
323 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
324 let OperandType = "OPERAND_PCREL";
327 // Branch target for ARM. Handles conditional/unconditional
328 def br_target : Operand<OtherVT> {
329 let EncoderMethod = "getARMBranchTargetOpValue";
330 let OperandType = "OPERAND_PCREL";
334 // FIXME: rename bltarget to t2_bl_target?
335 def bltarget : Operand<i32> {
336 // Encoded the same as branch targets.
337 let EncoderMethod = "getBranchTargetOpValue";
338 let OperandType = "OPERAND_PCREL";
341 // Call target for ARM. Handles conditional/unconditional
342 // FIXME: rename bl_target to t2_bltarget?
343 def bl_target : Operand<i32> {
344 // Encoded the same as branch targets.
345 let EncoderMethod = "getARMBranchTargetOpValue";
346 let OperandType = "OPERAND_PCREL";
349 def blx_target : Operand<i32> {
350 // Encoded the same as branch targets.
351 let EncoderMethod = "getARMBLXTargetOpValue";
352 let OperandType = "OPERAND_PCREL";
355 // A list of registers separated by comma. Used by load/store multiple.
356 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
357 def reglist : Operand<i32> {
358 let EncoderMethod = "getRegisterListOpValue";
359 let ParserMatchClass = RegListAsmOperand;
360 let PrintMethod = "printRegisterList";
361 let DecoderMethod = "DecodeRegListOperand";
364 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
365 def dpr_reglist : Operand<i32> {
366 let EncoderMethod = "getRegisterListOpValue";
367 let ParserMatchClass = DPRRegListAsmOperand;
368 let PrintMethod = "printRegisterList";
369 let DecoderMethod = "DecodeDPRRegListOperand";
372 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
373 def spr_reglist : Operand<i32> {
374 let EncoderMethod = "getRegisterListOpValue";
375 let ParserMatchClass = SPRRegListAsmOperand;
376 let PrintMethod = "printRegisterList";
377 let DecoderMethod = "DecodeSPRRegListOperand";
380 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
381 def cpinst_operand : Operand<i32> {
382 let PrintMethod = "printCPInstOperand";
386 def pclabel : Operand<i32> {
387 let PrintMethod = "printPCLabel";
390 // ADR instruction labels.
391 def adrlabel : Operand<i32> {
392 let EncoderMethod = "getAdrLabelOpValue";
395 def neon_vcvt_imm32 : Operand<i32> {
396 let EncoderMethod = "getNEONVcvtImm32OpValue";
397 let DecoderMethod = "DecodeVCVTImmOperand";
400 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
401 def rot_imm_XFORM: SDNodeXForm<imm, [{
402 switch (N->getZExtValue()){
404 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
405 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
406 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
407 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
410 def RotImmAsmOperand : AsmOperandClass {
412 let ParserMethod = "parseRotImm";
414 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
415 int32_t v = N->getZExtValue();
416 return v == 8 || v == 16 || v == 24; }],
418 let PrintMethod = "printRotImmOperand";
419 let ParserMatchClass = RotImmAsmOperand;
422 // shift_imm: An integer that encodes a shift amount and the type of shift
423 // (asr or lsl). The 6-bit immediate encodes as:
426 // {4-0} imm5 shift amount.
427 // asr #32 encoded as imm5 == 0.
428 def ShifterImmAsmOperand : AsmOperandClass {
429 let Name = "ShifterImm";
430 let ParserMethod = "parseShifterImm";
432 def shift_imm : Operand<i32> {
433 let PrintMethod = "printShiftImmOperand";
434 let ParserMatchClass = ShifterImmAsmOperand;
437 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
438 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
439 def so_reg_reg : Operand<i32>, // reg reg imm
440 ComplexPattern<i32, 3, "SelectRegShifterOperand",
441 [shl, srl, sra, rotr]> {
442 let EncoderMethod = "getSORegRegOpValue";
443 let PrintMethod = "printSORegRegOperand";
444 let DecoderMethod = "DecodeSORegRegOperand";
445 let ParserMatchClass = ShiftedRegAsmOperand;
446 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
449 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
450 def so_reg_imm : Operand<i32>, // reg imm
451 ComplexPattern<i32, 2, "SelectImmShifterOperand",
452 [shl, srl, sra, rotr]> {
453 let EncoderMethod = "getSORegImmOpValue";
454 let PrintMethod = "printSORegImmOperand";
455 let DecoderMethod = "DecodeSORegImmOperand";
456 let ParserMatchClass = ShiftedImmAsmOperand;
457 let MIOperandInfo = (ops GPR, i32imm);
460 // FIXME: Does this need to be distinct from so_reg?
461 def shift_so_reg_reg : Operand<i32>, // reg reg imm
462 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
463 [shl,srl,sra,rotr]> {
464 let EncoderMethod = "getSORegRegOpValue";
465 let PrintMethod = "printSORegRegOperand";
466 let DecoderMethod = "DecodeSORegRegOperand";
467 let MIOperandInfo = (ops GPR, GPR, i32imm);
470 // FIXME: Does this need to be distinct from so_reg?
471 def shift_so_reg_imm : Operand<i32>, // reg reg imm
472 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
473 [shl,srl,sra,rotr]> {
474 let EncoderMethod = "getSORegImmOpValue";
475 let PrintMethod = "printSORegImmOperand";
476 let DecoderMethod = "DecodeSORegImmOperand";
477 let MIOperandInfo = (ops GPR, i32imm);
481 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
482 // 8-bit immediate rotated by an arbitrary number of bits.
483 def SOImmAsmOperand: AsmOperandClass { let Name = "ARMSOImm"; }
484 def so_imm : Operand<i32>, ImmLeaf<i32, [{
485 return ARM_AM::getSOImmVal(Imm) != -1;
487 let EncoderMethod = "getSOImmOpValue";
488 let ParserMatchClass = SOImmAsmOperand;
489 let DecoderMethod = "DecodeSOImmOperand";
492 // Break so_imm's up into two pieces. This handles immediates with up to 16
493 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
494 // get the first/second pieces.
495 def so_imm2part : PatLeaf<(imm), [{
496 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
499 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
501 def arm_i32imm : PatLeaf<(imm), [{
502 if (Subtarget->hasV6T2Ops())
504 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
507 /// imm0_7 predicate - Immediate in the range [0,7].
508 def Imm0_7AsmOperand: AsmOperandClass { let Name = "Imm0_7"; }
509 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
510 return Imm >= 0 && Imm < 8;
512 let ParserMatchClass = Imm0_7AsmOperand;
515 /// imm0_15 predicate - Immediate in the range [0,15].
516 def Imm0_15AsmOperand: AsmOperandClass { let Name = "Imm0_15"; }
517 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
518 return Imm >= 0 && Imm < 16;
520 let ParserMatchClass = Imm0_15AsmOperand;
523 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
524 def Imm0_31AsmOperand: AsmOperandClass { let Name = "Imm0_31"; }
525 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
526 return Imm >= 0 && Imm < 32;
528 let ParserMatchClass = Imm0_31AsmOperand;
531 /// imm0_255 predicate - Immediate in the range [0,255].
532 def Imm0_255AsmOperand : AsmOperandClass { let Name = "Imm0_255"; }
533 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
534 let ParserMatchClass = Imm0_255AsmOperand;
537 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
538 // a relocatable expression.
540 // FIXME: This really needs a Thumb version separate from the ARM version.
541 // While the range is the same, and can thus use the same match class,
542 // the encoding is different so it should have a different encoder method.
543 def Imm0_65535ExprAsmOperand: AsmOperandClass { let Name = "Imm0_65535Expr"; }
544 def imm0_65535_expr : Operand<i32> {
545 let EncoderMethod = "getHiLo16ImmOpValue";
546 let ParserMatchClass = Imm0_65535ExprAsmOperand;
549 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
550 def Imm24bitAsmOperand: AsmOperandClass { let Name = "Imm24bit"; }
551 def imm24b : Operand<i32>, ImmLeaf<i32, [{
552 return Imm >= 0 && Imm <= 0xffffff;
554 let ParserMatchClass = Imm24bitAsmOperand;
558 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
560 def BitfieldAsmOperand : AsmOperandClass {
561 let Name = "Bitfield";
562 let ParserMethod = "parseBitfield";
564 def bf_inv_mask_imm : Operand<i32>,
566 return ARM::isBitFieldInvertedMask(N->getZExtValue());
568 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
569 let PrintMethod = "printBitfieldInvMaskImmOperand";
570 let DecoderMethod = "DecodeBitfieldMaskOperand";
571 let ParserMatchClass = BitfieldAsmOperand;
574 /// lsb_pos_imm - position of the lsb bit, used by BFI4p and t2BFI4p
575 def lsb_pos_imm : Operand<i32>, ImmLeaf<i32, [{
576 return isInt<5>(Imm);
579 /// width_imm - number of bits to be copied, used by BFI4p and t2BFI4p
580 def width_imm : Operand<i32>, ImmLeaf<i32, [{
581 return Imm > 0 && Imm <= 32;
583 let EncoderMethod = "getMsbOpValue";
586 def imm1_32_XFORM: SDNodeXForm<imm, [{
587 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
589 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
590 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
591 uint64_t Imm = N->getZExtValue();
592 return Imm > 0 && Imm <= 32;
595 let PrintMethod = "printImmPlusOneOperand";
596 let ParserMatchClass = Imm1_32AsmOperand;
599 def imm1_16_XFORM: SDNodeXForm<imm, [{
600 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
602 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
603 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
605 let PrintMethod = "printImmPlusOneOperand";
606 let ParserMatchClass = Imm1_16AsmOperand;
609 // Define ARM specific addressing modes.
610 // addrmode_imm12 := reg +/- imm12
612 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
613 def addrmode_imm12 : Operand<i32>,
614 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
615 // 12-bit immediate operand. Note that instructions using this encode
616 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
617 // immediate values are as normal.
619 let EncoderMethod = "getAddrModeImm12OpValue";
620 let PrintMethod = "printAddrModeImm12Operand";
621 let DecoderMethod = "DecodeAddrModeImm12Operand";
622 let ParserMatchClass = MemImm12OffsetAsmOperand;
623 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
625 // ldst_so_reg := reg +/- reg shop imm
627 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
628 def ldst_so_reg : Operand<i32>,
629 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
630 let EncoderMethod = "getLdStSORegOpValue";
631 // FIXME: Simplify the printer
632 let PrintMethod = "printAddrMode2Operand";
633 let DecoderMethod = "DecodeSORegMemOperand";
634 let ParserMatchClass = MemRegOffsetAsmOperand;
635 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
638 // postidx_imm8 := +/- [0,255]
641 // {8} 1 is imm8 is non-negative. 0 otherwise.
642 // {7-0} [0,255] imm8 value.
643 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
644 def postidx_imm8 : Operand<i32> {
645 let PrintMethod = "printPostIdxImm8Operand";
646 let ParserMatchClass = PostIdxImm8AsmOperand;
647 let MIOperandInfo = (ops i32imm);
650 // postidx_imm8s4 := +/- [0,1020]
653 // {8} 1 is imm8 is non-negative. 0 otherwise.
654 // {7-0} [0,255] imm8 value, scaled by 4.
655 def postidx_imm8s4 : Operand<i32> {
656 let PrintMethod = "printPostIdxImm8s4Operand";
657 let MIOperandInfo = (ops i32imm);
661 // postidx_reg := +/- reg
663 def PostIdxRegAsmOperand : AsmOperandClass {
664 let Name = "PostIdxReg";
665 let ParserMethod = "parsePostIdxReg";
667 def postidx_reg : Operand<i32> {
668 let EncoderMethod = "getPostIdxRegOpValue";
669 let DecoderMethod = "DecodePostIdxReg";
670 let PrintMethod = "printPostIdxRegOperand";
671 let ParserMatchClass = PostIdxRegAsmOperand;
672 let MIOperandInfo = (ops GPR, i32imm);
676 // addrmode2 := reg +/- imm12
677 // := reg +/- reg shop imm
679 // FIXME: addrmode2 should be refactored the rest of the way to always
680 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
681 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
682 def addrmode2 : Operand<i32>,
683 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
684 let EncoderMethod = "getAddrMode2OpValue";
685 let PrintMethod = "printAddrMode2Operand";
686 let ParserMatchClass = AddrMode2AsmOperand;
687 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
690 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
691 let Name = "PostIdxRegShifted";
692 let ParserMethod = "parsePostIdxReg";
694 def am2offset_reg : Operand<i32>,
695 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
696 [], [SDNPWantRoot]> {
697 let EncoderMethod = "getAddrMode2OffsetOpValue";
698 let PrintMethod = "printAddrMode2OffsetOperand";
699 // When using this for assembly, it's always as a post-index offset.
700 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
701 let MIOperandInfo = (ops GPR, i32imm);
704 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
705 // the GPR is purely vestigal at this point.
706 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
707 def am2offset_imm : Operand<i32>,
708 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
709 [], [SDNPWantRoot]> {
710 let EncoderMethod = "getAddrMode2OffsetOpValue";
711 let PrintMethod = "printAddrMode2OffsetOperand";
712 let ParserMatchClass = AM2OffsetImmAsmOperand;
713 let MIOperandInfo = (ops GPR, i32imm);
717 // addrmode3 := reg +/- reg
718 // addrmode3 := reg +/- imm8
720 // FIXME: split into imm vs. reg versions.
721 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
722 def addrmode3 : Operand<i32>,
723 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
724 let EncoderMethod = "getAddrMode3OpValue";
725 let PrintMethod = "printAddrMode3Operand";
726 let ParserMatchClass = AddrMode3AsmOperand;
727 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
730 // FIXME: split into imm vs. reg versions.
731 // FIXME: parser method to handle +/- register.
732 def AM3OffsetAsmOperand : AsmOperandClass {
733 let Name = "AM3Offset";
734 let ParserMethod = "parseAM3Offset";
736 def am3offset : Operand<i32>,
737 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
738 [], [SDNPWantRoot]> {
739 let EncoderMethod = "getAddrMode3OffsetOpValue";
740 let PrintMethod = "printAddrMode3OffsetOperand";
741 let ParserMatchClass = AM3OffsetAsmOperand;
742 let MIOperandInfo = (ops GPR, i32imm);
745 // ldstm_mode := {ia, ib, da, db}
747 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
748 let EncoderMethod = "getLdStmModeOpValue";
749 let PrintMethod = "printLdStmModeOperand";
752 // addrmode5 := reg +/- imm8*4
754 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
755 def addrmode5 : Operand<i32>,
756 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
757 let PrintMethod = "printAddrMode5Operand";
758 let EncoderMethod = "getAddrMode5OpValue";
759 let DecoderMethod = "DecodeAddrMode5Operand";
760 let ParserMatchClass = AddrMode5AsmOperand;
761 let MIOperandInfo = (ops GPR:$base, i32imm);
764 // addrmode6 := reg with optional alignment
766 def addrmode6 : Operand<i32>,
767 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
768 let PrintMethod = "printAddrMode6Operand";
769 let MIOperandInfo = (ops GPR:$addr, i32imm);
770 let EncoderMethod = "getAddrMode6AddressOpValue";
771 let DecoderMethod = "DecodeAddrMode6Operand";
774 def am6offset : Operand<i32>,
775 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
776 [], [SDNPWantRoot]> {
777 let PrintMethod = "printAddrMode6OffsetOperand";
778 let MIOperandInfo = (ops GPR);
779 let EncoderMethod = "getAddrMode6OffsetOpValue";
780 let DecoderMethod = "DecodeGPRRegisterClass";
783 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
784 // (single element from one lane) for size 32.
785 def addrmode6oneL32 : Operand<i32>,
786 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
787 let PrintMethod = "printAddrMode6Operand";
788 let MIOperandInfo = (ops GPR:$addr, i32imm);
789 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
792 // Special version of addrmode6 to handle alignment encoding for VLD-dup
793 // instructions, specifically VLD4-dup.
794 def addrmode6dup : Operand<i32>,
795 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
796 let PrintMethod = "printAddrMode6Operand";
797 let MIOperandInfo = (ops GPR:$addr, i32imm);
798 let EncoderMethod = "getAddrMode6DupAddressOpValue";
801 // addrmodepc := pc + reg
803 def addrmodepc : Operand<i32>,
804 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
805 let PrintMethod = "printAddrModePCOperand";
806 let MIOperandInfo = (ops GPR, i32imm);
809 // addr_offset_none := reg
811 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
812 def addr_offset_none : Operand<i32>,
813 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
814 let PrintMethod = "printAddrMode7Operand";
815 let DecoderMethod = "DecodeAddrMode7Operand";
816 let ParserMatchClass = MemNoOffsetAsmOperand;
817 let MIOperandInfo = (ops GPR:$base);
820 def nohash_imm : Operand<i32> {
821 let PrintMethod = "printNoHashImmediate";
824 def CoprocNumAsmOperand : AsmOperandClass {
825 let Name = "CoprocNum";
826 let ParserMethod = "parseCoprocNumOperand";
828 def p_imm : Operand<i32> {
829 let PrintMethod = "printPImmediate";
830 let ParserMatchClass = CoprocNumAsmOperand;
831 let DecoderMethod = "DecodeCoprocessor";
834 def CoprocRegAsmOperand : AsmOperandClass {
835 let Name = "CoprocReg";
836 let ParserMethod = "parseCoprocRegOperand";
838 def c_imm : Operand<i32> {
839 let PrintMethod = "printCImmediate";
840 let ParserMatchClass = CoprocRegAsmOperand;
843 //===----------------------------------------------------------------------===//
845 include "ARMInstrFormats.td"
847 //===----------------------------------------------------------------------===//
848 // Multiclass helpers...
851 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
852 /// binop that produces a value.
853 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
854 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
855 PatFrag opnode, string baseOpc, bit Commutable = 0> {
856 // The register-immediate version is re-materializable. This is useful
857 // in particular for taking the address of a local.
858 let isReMaterializable = 1 in {
859 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
860 iii, opc, "\t$Rd, $Rn, $imm",
861 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
866 let Inst{19-16} = Rn;
867 let Inst{15-12} = Rd;
868 let Inst{11-0} = imm;
871 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
872 iir, opc, "\t$Rd, $Rn, $Rm",
873 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
878 let isCommutable = Commutable;
879 let Inst{19-16} = Rn;
880 let Inst{15-12} = Rd;
881 let Inst{11-4} = 0b00000000;
885 def rsi : AsI1<opcod, (outs GPR:$Rd),
886 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
887 iis, opc, "\t$Rd, $Rn, $shift",
888 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
893 let Inst{19-16} = Rn;
894 let Inst{15-12} = Rd;
895 let Inst{11-5} = shift{11-5};
897 let Inst{3-0} = shift{3-0};
900 def rsr : AsI1<opcod, (outs GPR:$Rd),
901 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
902 iis, opc, "\t$Rd, $Rn, $shift",
903 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
908 let Inst{19-16} = Rn;
909 let Inst{15-12} = Rd;
910 let Inst{11-8} = shift{11-8};
912 let Inst{6-5} = shift{6-5};
914 let Inst{3-0} = shift{3-0};
917 // Assembly aliases for optional destination operand when it's the same
918 // as the source operand.
919 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
920 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
921 so_imm:$imm, pred:$p,
924 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
925 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
929 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
930 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
931 so_reg_imm:$shift, pred:$p,
934 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
935 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
936 so_reg_reg:$shift, pred:$p,
942 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
943 /// instruction modifies the CPSR register.
944 let isCodeGenOnly = 1, Defs = [CPSR] in {
945 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
946 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
947 PatFrag opnode, bit Commutable = 0> {
948 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
949 iii, opc, "\t$Rd, $Rn, $imm",
950 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
956 let Inst{19-16} = Rn;
957 let Inst{15-12} = Rd;
958 let Inst{11-0} = imm;
960 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
961 iir, opc, "\t$Rd, $Rn, $Rm",
962 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
966 let isCommutable = Commutable;
969 let Inst{19-16} = Rn;
970 let Inst{15-12} = Rd;
971 let Inst{11-4} = 0b00000000;
974 def rsi : AI1<opcod, (outs GPR:$Rd),
975 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
976 iis, opc, "\t$Rd, $Rn, $shift",
977 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
983 let Inst{19-16} = Rn;
984 let Inst{15-12} = Rd;
985 let Inst{11-5} = shift{11-5};
987 let Inst{3-0} = shift{3-0};
990 def rsr : AI1<opcod, (outs GPR:$Rd),
991 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
992 iis, opc, "\t$Rd, $Rn, $shift",
993 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
999 let Inst{19-16} = Rn;
1000 let Inst{15-12} = Rd;
1001 let Inst{11-8} = shift{11-8};
1003 let Inst{6-5} = shift{6-5};
1005 let Inst{3-0} = shift{3-0};
1010 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1011 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1012 /// a explicit result, only implicitly set CPSR.
1013 let isCompare = 1, Defs = [CPSR] in {
1014 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1015 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1016 PatFrag opnode, bit Commutable = 0> {
1017 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1019 [(opnode GPR:$Rn, so_imm:$imm)]> {
1024 let Inst{19-16} = Rn;
1025 let Inst{15-12} = 0b0000;
1026 let Inst{11-0} = imm;
1028 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1030 [(opnode GPR:$Rn, GPR:$Rm)]> {
1033 let isCommutable = Commutable;
1036 let Inst{19-16} = Rn;
1037 let Inst{15-12} = 0b0000;
1038 let Inst{11-4} = 0b00000000;
1041 def rsi : AI1<opcod, (outs),
1042 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1043 opc, "\t$Rn, $shift",
1044 [(opnode GPR:$Rn, so_reg_imm:$shift)]> {
1049 let Inst{19-16} = Rn;
1050 let Inst{15-12} = 0b0000;
1051 let Inst{11-5} = shift{11-5};
1053 let Inst{3-0} = shift{3-0};
1055 def rsr : AI1<opcod, (outs),
1056 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1057 opc, "\t$Rn, $shift",
1058 [(opnode GPR:$Rn, so_reg_reg:$shift)]> {
1063 let Inst{19-16} = Rn;
1064 let Inst{15-12} = 0b0000;
1065 let Inst{11-8} = shift{11-8};
1067 let Inst{6-5} = shift{6-5};
1069 let Inst{3-0} = shift{3-0};
1075 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1076 /// register and one whose operand is a register rotated by 8/16/24.
1077 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1078 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1079 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1080 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1081 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1082 Requires<[IsARM, HasV6]> {
1086 let Inst{19-16} = 0b1111;
1087 let Inst{15-12} = Rd;
1088 let Inst{11-10} = rot;
1092 class AI_ext_rrot_np<bits<8> opcod, string opc>
1093 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1094 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1095 Requires<[IsARM, HasV6]> {
1097 let Inst{19-16} = 0b1111;
1098 let Inst{11-10} = rot;
1101 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1102 /// register and one whose operand is a register rotated by 8/16/24.
1103 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1104 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1105 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1106 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1107 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1108 Requires<[IsARM, HasV6]> {
1113 let Inst{19-16} = Rn;
1114 let Inst{15-12} = Rd;
1115 let Inst{11-10} = rot;
1116 let Inst{9-4} = 0b000111;
1120 class AI_exta_rrot_np<bits<8> opcod, string opc>
1121 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1122 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1123 Requires<[IsARM, HasV6]> {
1126 let Inst{19-16} = Rn;
1127 let Inst{11-10} = rot;
1130 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1131 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1132 string baseOpc, bit Commutable = 0> {
1133 let Uses = [CPSR] in {
1134 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1135 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1136 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
1142 let Inst{15-12} = Rd;
1143 let Inst{19-16} = Rn;
1144 let Inst{11-0} = imm;
1146 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1147 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1148 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1153 let Inst{11-4} = 0b00000000;
1155 let isCommutable = Commutable;
1157 let Inst{15-12} = Rd;
1158 let Inst{19-16} = Rn;
1160 def rsi : AsI1<opcod, (outs GPR:$Rd),
1161 (ins GPR:$Rn, so_reg_imm:$shift),
1162 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1163 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1169 let Inst{19-16} = Rn;
1170 let Inst{15-12} = Rd;
1171 let Inst{11-5} = shift{11-5};
1173 let Inst{3-0} = shift{3-0};
1175 def rsr : AsI1<opcod, (outs GPR:$Rd),
1176 (ins GPR:$Rn, so_reg_reg:$shift),
1177 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1178 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1184 let Inst{19-16} = Rn;
1185 let Inst{15-12} = Rd;
1186 let Inst{11-8} = shift{11-8};
1188 let Inst{6-5} = shift{6-5};
1190 let Inst{3-0} = shift{3-0};
1193 // Assembly aliases for optional destination operand when it's the same
1194 // as the source operand.
1195 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1196 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1197 so_imm:$imm, pred:$p,
1200 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1201 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1205 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1206 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1207 so_reg_imm:$shift, pred:$p,
1210 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1211 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1212 so_reg_reg:$shift, pred:$p,
1217 // Carry setting variants
1218 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
1219 let usesCustomInserter = 1 in {
1220 multiclass AI1_adde_sube_s_irs<PatFrag opnode, bit Commutable = 0> {
1221 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1223 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>;
1224 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1226 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
1227 let isCommutable = Commutable;
1229 def rsi : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1231 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>;
1232 def rsr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1234 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>;
1238 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1239 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1240 InstrItinClass iir, PatFrag opnode> {
1241 // Note: We use the complex addrmode_imm12 rather than just an input
1242 // GPR and a constrained immediate so that we can use this to match
1243 // frame index references and avoid matching constant pool references.
1244 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1245 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1246 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1249 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1250 let Inst{19-16} = addr{16-13}; // Rn
1251 let Inst{15-12} = Rt;
1252 let Inst{11-0} = addr{11-0}; // imm12
1254 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1255 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1256 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1259 let shift{4} = 0; // Inst{4} = 0
1260 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1261 let Inst{19-16} = shift{16-13}; // Rn
1262 let Inst{15-12} = Rt;
1263 let Inst{11-0} = shift{11-0};
1268 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1269 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1270 InstrItinClass iir, PatFrag opnode> {
1271 // Note: We use the complex addrmode_imm12 rather than just an input
1272 // GPR and a constrained immediate so that we can use this to match
1273 // frame index references and avoid matching constant pool references.
1274 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), (ins addrmode_imm12:$addr),
1275 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1276 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1279 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1280 let Inst{19-16} = addr{16-13}; // Rn
1281 let Inst{15-12} = Rt;
1282 let Inst{11-0} = addr{11-0}; // imm12
1284 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), (ins ldst_so_reg:$shift),
1285 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1286 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1289 let shift{4} = 0; // Inst{4} = 0
1290 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1291 let Inst{19-16} = shift{16-13}; // Rn
1292 let Inst{15-12} = Rt;
1293 let Inst{11-0} = shift{11-0};
1299 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1300 InstrItinClass iir, PatFrag opnode> {
1301 // Note: We use the complex addrmode_imm12 rather than just an input
1302 // GPR and a constrained immediate so that we can use this to match
1303 // frame index references and avoid matching constant pool references.
1304 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1305 (ins GPR:$Rt, addrmode_imm12:$addr),
1306 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1307 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1310 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1311 let Inst{19-16} = addr{16-13}; // Rn
1312 let Inst{15-12} = Rt;
1313 let Inst{11-0} = addr{11-0}; // imm12
1315 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1316 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1317 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1320 let shift{4} = 0; // Inst{4} = 0
1321 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1322 let Inst{19-16} = shift{16-13}; // Rn
1323 let Inst{15-12} = Rt;
1324 let Inst{11-0} = shift{11-0};
1328 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1329 InstrItinClass iir, PatFrag opnode> {
1330 // Note: We use the complex addrmode_imm12 rather than just an input
1331 // GPR and a constrained immediate so that we can use this to match
1332 // frame index references and avoid matching constant pool references.
1333 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1334 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1335 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1336 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1339 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1340 let Inst{19-16} = addr{16-13}; // Rn
1341 let Inst{15-12} = Rt;
1342 let Inst{11-0} = addr{11-0}; // imm12
1344 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1345 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1346 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1349 let shift{4} = 0; // Inst{4} = 0
1350 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1351 let Inst{19-16} = shift{16-13}; // Rn
1352 let Inst{15-12} = Rt;
1353 let Inst{11-0} = shift{11-0};
1358 //===----------------------------------------------------------------------===//
1360 //===----------------------------------------------------------------------===//
1362 //===----------------------------------------------------------------------===//
1363 // Miscellaneous Instructions.
1366 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1367 /// the function. The first operand is the ID# for this instruction, the second
1368 /// is the index into the MachineConstantPool that this is, the third is the
1369 /// size in bytes of this constant pool entry.
1370 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1371 def CONSTPOOL_ENTRY :
1372 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1373 i32imm:$size), NoItinerary, []>;
1375 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1376 // from removing one half of the matched pairs. That breaks PEI, which assumes
1377 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1378 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1379 def ADJCALLSTACKUP :
1380 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1381 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1383 def ADJCALLSTACKDOWN :
1384 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1385 [(ARMcallseq_start timm:$amt)]>;
1388 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "", []>,
1389 Requires<[IsARM, HasV6T2]> {
1390 let Inst{27-16} = 0b001100100000;
1391 let Inst{15-8} = 0b11110000;
1392 let Inst{7-0} = 0b00000000;
1395 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "", []>,
1396 Requires<[IsARM, HasV6T2]> {
1397 let Inst{27-16} = 0b001100100000;
1398 let Inst{15-8} = 0b11110000;
1399 let Inst{7-0} = 0b00000001;
1402 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "", []>,
1403 Requires<[IsARM, HasV6T2]> {
1404 let Inst{27-16} = 0b001100100000;
1405 let Inst{15-8} = 0b11110000;
1406 let Inst{7-0} = 0b00000010;
1409 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "", []>,
1410 Requires<[IsARM, HasV6T2]> {
1411 let Inst{27-16} = 0b001100100000;
1412 let Inst{15-8} = 0b11110000;
1413 let Inst{7-0} = 0b00000011;
1416 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1417 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1422 let Inst{15-12} = Rd;
1423 let Inst{19-16} = Rn;
1424 let Inst{27-20} = 0b01101000;
1425 let Inst{7-4} = 0b1011;
1426 let Inst{11-8} = 0b1111;
1429 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1430 []>, Requires<[IsARM, HasV6T2]> {
1431 let Inst{27-16} = 0b001100100000;
1432 let Inst{15-8} = 0b11110000;
1433 let Inst{7-0} = 0b00000100;
1436 // The i32imm operand $val can be used by a debugger to store more information
1437 // about the breakpoint.
1438 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1439 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1441 let Inst{3-0} = val{3-0};
1442 let Inst{19-8} = val{15-4};
1443 let Inst{27-20} = 0b00010010;
1444 let Inst{7-4} = 0b0111;
1447 // Change Processor State
1448 // FIXME: We should use InstAlias to handle the optional operands.
1449 class CPS<dag iops, string asm_ops>
1450 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1451 []>, Requires<[IsARM]> {
1457 let Inst{31-28} = 0b1111;
1458 let Inst{27-20} = 0b00010000;
1459 let Inst{19-18} = imod;
1460 let Inst{17} = M; // Enabled if mode is set;
1462 let Inst{8-6} = iflags;
1464 let Inst{4-0} = mode;
1467 let DecoderMethod = "DecodeCPSInstruction" in {
1469 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1470 "$imod\t$iflags, $mode">;
1471 let mode = 0, M = 0 in
1472 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1474 let imod = 0, iflags = 0, M = 1 in
1475 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1478 // Preload signals the memory system of possible future data/instruction access.
1479 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1481 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1482 !strconcat(opc, "\t$addr"),
1483 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1486 let Inst{31-26} = 0b111101;
1487 let Inst{25} = 0; // 0 for immediate form
1488 let Inst{24} = data;
1489 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1490 let Inst{22} = read;
1491 let Inst{21-20} = 0b01;
1492 let Inst{19-16} = addr{16-13}; // Rn
1493 let Inst{15-12} = 0b1111;
1494 let Inst{11-0} = addr{11-0}; // imm12
1497 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1498 !strconcat(opc, "\t$shift"),
1499 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1501 let Inst{31-26} = 0b111101;
1502 let Inst{25} = 1; // 1 for register form
1503 let Inst{24} = data;
1504 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1505 let Inst{22} = read;
1506 let Inst{21-20} = 0b01;
1507 let Inst{19-16} = shift{16-13}; // Rn
1508 let Inst{15-12} = 0b1111;
1509 let Inst{11-0} = shift{11-0};
1513 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1514 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1515 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1517 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1518 "setend\t$end", []>, Requires<[IsARM]> {
1520 let Inst{31-10} = 0b1111000100000001000000;
1525 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1526 []>, Requires<[IsARM, HasV7]> {
1528 let Inst{27-4} = 0b001100100000111100001111;
1529 let Inst{3-0} = opt;
1532 // A5.4 Permanently UNDEFINED instructions.
1533 let isBarrier = 1, isTerminator = 1 in
1534 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1537 let Inst = 0xe7ffdefe;
1540 // Address computation and loads and stores in PIC mode.
1541 let isNotDuplicable = 1 in {
1542 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1544 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1546 let AddedComplexity = 10 in {
1547 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1549 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1551 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1553 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1555 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1557 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1559 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1561 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1563 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1565 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1567 let AddedComplexity = 10 in {
1568 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1569 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1571 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1572 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1573 addrmodepc:$addr)]>;
1575 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1576 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1578 } // isNotDuplicable = 1
1581 // LEApcrel - Load a pc-relative address into a register without offending the
1583 let neverHasSideEffects = 1, isReMaterializable = 1 in
1584 // The 'adr' mnemonic encodes differently if the label is before or after
1585 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1586 // know until then which form of the instruction will be used.
1587 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1588 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []> {
1591 let Inst{27-25} = 0b001;
1593 let Inst{23-22} = label{13-12};
1596 let Inst{19-16} = 0b1111;
1597 let Inst{15-12} = Rd;
1598 let Inst{11-0} = label{11-0};
1600 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1603 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1604 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1607 //===----------------------------------------------------------------------===//
1608 // Control Flow Instructions.
1611 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1613 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1614 "bx", "\tlr", [(ARMretflag)]>,
1615 Requires<[IsARM, HasV4T]> {
1616 let Inst{27-0} = 0b0001001011111111111100011110;
1620 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1621 "mov", "\tpc, lr", [(ARMretflag)]>,
1622 Requires<[IsARM, NoV4T]> {
1623 let Inst{27-0} = 0b0001101000001111000000001110;
1627 // Indirect branches
1628 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1630 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1631 [(brind GPR:$dst)]>,
1632 Requires<[IsARM, HasV4T]> {
1634 let Inst{31-4} = 0b1110000100101111111111110001;
1635 let Inst{3-0} = dst;
1638 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1639 "bx", "\t$dst", [/* pattern left blank */]>,
1640 Requires<[IsARM, HasV4T]> {
1642 let Inst{27-4} = 0b000100101111111111110001;
1643 let Inst{3-0} = dst;
1647 // All calls clobber the non-callee saved registers. SP is marked as
1648 // a use to prevent stack-pointer assignments that appear immediately
1649 // before calls from potentially appearing dead.
1651 // On non-Darwin platforms R9 is callee-saved.
1652 // FIXME: Do we really need a non-predicated version? If so, it should
1653 // at least be a pseudo instruction expanding to the predicated version
1654 // at MC lowering time.
1655 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1657 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1658 IIC_Br, "bl\t$func",
1659 [(ARMcall tglobaladdr:$func)]>,
1660 Requires<[IsARM, IsNotDarwin]> {
1661 let Inst{31-28} = 0b1110;
1663 let Inst{23-0} = func;
1664 let DecoderMethod = "DecodeBranchImmInstruction";
1667 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1668 IIC_Br, "bl", "\t$func",
1669 [(ARMcall_pred tglobaladdr:$func)]>,
1670 Requires<[IsARM, IsNotDarwin]> {
1672 let Inst{23-0} = func;
1673 let DecoderMethod = "DecodeBranchImmInstruction";
1677 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1678 IIC_Br, "blx\t$func",
1679 [(ARMcall GPR:$func)]>,
1680 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1682 let Inst{31-4} = 0b1110000100101111111111110011;
1683 let Inst{3-0} = func;
1686 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1687 IIC_Br, "blx", "\t$func",
1688 [(ARMcall_pred GPR:$func)]>,
1689 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1691 let Inst{27-4} = 0b000100101111111111110011;
1692 let Inst{3-0} = func;
1696 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1697 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1698 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1699 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1702 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1703 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1704 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1708 // On Darwin R9 is call-clobbered.
1709 // R7 is marked as a use to prevent frame-pointer assignments from being
1710 // moved above / below calls.
1711 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1712 Uses = [R7, SP] in {
1713 def BLr9 : ARMPseudoExpand<(outs), (ins bl_target:$func, variable_ops),
1715 [(ARMcall tglobaladdr:$func)], (BL bl_target:$func)>,
1716 Requires<[IsARM, IsDarwin]>;
1718 def BLr9_pred : ARMPseudoExpand<(outs),
1719 (ins bl_target:$func, pred:$p, variable_ops),
1721 [(ARMcall_pred tglobaladdr:$func)],
1722 (BL_pred bl_target:$func, pred:$p)>,
1723 Requires<[IsARM, IsDarwin]>;
1726 def BLXr9 : ARMPseudoExpand<(outs), (ins GPR:$func, variable_ops),
1728 [(ARMcall GPR:$func)],
1730 Requires<[IsARM, HasV5T, IsDarwin]>;
1732 def BLXr9_pred: ARMPseudoExpand<(outs), (ins GPR:$func, pred:$p,variable_ops),
1734 [(ARMcall_pred GPR:$func)],
1735 (BLX_pred GPR:$func, pred:$p)>,
1736 Requires<[IsARM, HasV5T, IsDarwin]>;
1739 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1740 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1741 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1742 Requires<[IsARM, HasV4T, IsDarwin]>;
1745 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1746 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1747 Requires<[IsARM, NoV4T, IsDarwin]>;
1750 let isBranch = 1, isTerminator = 1 in {
1751 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1752 // a two-value operand where a dag node expects two operands. :(
1753 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1754 IIC_Br, "b", "\t$target",
1755 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1757 let Inst{23-0} = target;
1758 let DecoderMethod = "DecodeBranchImmInstruction";
1761 let isBarrier = 1 in {
1762 // B is "predicable" since it's just a Bcc with an 'always' condition.
1763 let isPredicable = 1 in
1764 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1765 // should be sufficient.
1766 // FIXME: Is B really a Barrier? That doesn't seem right.
1767 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
1768 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
1770 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1771 def BR_JTr : ARMPseudoInst<(outs),
1772 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1774 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1775 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1776 // into i12 and rs suffixed versions.
1777 def BR_JTm : ARMPseudoInst<(outs),
1778 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1780 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1782 def BR_JTadd : ARMPseudoInst<(outs),
1783 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1785 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1787 } // isNotDuplicable = 1, isIndirectBranch = 1
1793 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
1794 "blx\t$target", []>,
1795 Requires<[IsARM, HasV5T]> {
1796 let Inst{31-25} = 0b1111101;
1798 let Inst{23-0} = target{24-1};
1799 let Inst{24} = target{0};
1802 // Branch and Exchange Jazelle
1803 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1804 [/* pattern left blank */]> {
1806 let Inst{23-20} = 0b0010;
1807 let Inst{19-8} = 0xfff;
1808 let Inst{7-4} = 0b0010;
1809 let Inst{3-0} = func;
1814 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1816 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
1818 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1819 IIC_Br, []>, Requires<[IsDarwin]>;
1821 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1822 IIC_Br, []>, Requires<[IsDarwin]>;
1824 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst, variable_ops),
1826 (Bcc br_target:$dst, (ops 14, zero_reg))>,
1827 Requires<[IsARM, IsDarwin]>;
1829 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
1832 Requires<[IsARM, IsDarwin]>;
1836 // Non-Darwin versions (the difference is R9).
1837 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
1839 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1840 IIC_Br, []>, Requires<[IsNotDarwin]>;
1842 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1843 IIC_Br, []>, Requires<[IsNotDarwin]>;
1845 def TAILJMPdND : ARMPseudoExpand<(outs), (ins brtarget:$dst, variable_ops),
1847 (Bcc br_target:$dst, (ops 14, zero_reg))>,
1848 Requires<[IsARM, IsNotDarwin]>;
1850 def TAILJMPrND : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
1853 Requires<[IsARM, IsNotDarwin]>;
1857 // Secure Monitor Call is a system instruction.
1858 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
1861 let Inst{23-4} = 0b01100000000000000111;
1862 let Inst{3-0} = opt;
1865 // Supervisor Call (Software Interrupt)
1866 let isCall = 1, Uses = [SP] in {
1867 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
1869 let Inst{23-0} = svc;
1873 // Store Return State
1874 class SRSI<bit wb, string asm>
1875 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
1876 NoItinerary, asm, "", []> {
1878 let Inst{31-28} = 0b1111;
1879 let Inst{27-25} = 0b100;
1883 let Inst{19-16} = 0b1101; // SP
1884 let Inst{15-5} = 0b00000101000;
1885 let Inst{4-0} = mode;
1888 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
1889 let Inst{24-23} = 0;
1891 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
1892 let Inst{24-23} = 0;
1894 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
1895 let Inst{24-23} = 0b10;
1897 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
1898 let Inst{24-23} = 0b10;
1900 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
1901 let Inst{24-23} = 0b01;
1903 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
1904 let Inst{24-23} = 0b01;
1906 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
1907 let Inst{24-23} = 0b11;
1909 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
1910 let Inst{24-23} = 0b11;
1913 // Return From Exception
1914 class RFEI<bit wb, string asm>
1915 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
1916 NoItinerary, asm, "", []> {
1918 let Inst{31-28} = 0b1111;
1919 let Inst{27-25} = 0b100;
1923 let Inst{19-16} = Rn;
1924 let Inst{15-0} = 0xa00;
1927 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
1928 let Inst{24-23} = 0;
1930 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
1931 let Inst{24-23} = 0;
1933 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
1934 let Inst{24-23} = 0b10;
1936 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
1937 let Inst{24-23} = 0b10;
1939 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
1940 let Inst{24-23} = 0b01;
1942 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
1943 let Inst{24-23} = 0b01;
1945 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
1946 let Inst{24-23} = 0b11;
1948 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
1949 let Inst{24-23} = 0b11;
1952 //===----------------------------------------------------------------------===//
1953 // Load / store Instructions.
1959 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1960 UnOpFrag<(load node:$Src)>>;
1961 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1962 UnOpFrag<(zextloadi8 node:$Src)>>;
1963 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1964 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1965 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1966 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1968 // Special LDR for loads from non-pc-relative constpools.
1969 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1970 isReMaterializable = 1, isCodeGenOnly = 1 in
1971 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1972 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
1976 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1977 let Inst{19-16} = 0b1111;
1978 let Inst{15-12} = Rt;
1979 let Inst{11-0} = addr{11-0}; // imm12
1982 // Loads with zero extension
1983 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1984 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
1985 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
1987 // Loads with sign extension
1988 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1989 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
1990 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
1992 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1993 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
1994 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
1996 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1998 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
1999 (ins addrmode3:$addr), LdMiscFrm,
2000 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2001 []>, Requires<[IsARM, HasV5TE]>;
2005 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
2006 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2007 (ins addrmode_imm12:$addr), IndexModePre, LdFrm, itin,
2008 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2011 let Inst{23} = addr{12};
2012 let Inst{19-16} = addr{16-13};
2013 let Inst{11-0} = addr{11-0};
2014 let DecoderMethod = "DecodeLDRPreImm";
2015 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
2018 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2019 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, itin,
2020 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2023 let Inst{23} = addr{12};
2024 let Inst{19-16} = addr{16-13};
2025 let Inst{11-0} = addr{11-0};
2027 let DecoderMethod = "DecodeLDRPreReg";
2028 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2031 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2032 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2033 IndexModePost, LdFrm, itin,
2034 opc, "\t$Rt, $addr, $offset",
2035 "$addr.base = $Rn_wb", []> {
2041 let Inst{23} = offset{12};
2042 let Inst{19-16} = addr;
2043 let Inst{11-0} = offset{11-0};
2045 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2048 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2049 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2050 IndexModePost, LdFrm, itin,
2051 opc, "\t$Rt, $addr, $offset",
2052 "$addr.base = $Rn_wb", []> {
2058 let Inst{23} = offset{12};
2059 let Inst{19-16} = addr;
2060 let Inst{11-0} = offset{11-0};
2062 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2067 let mayLoad = 1, neverHasSideEffects = 1 in {
2068 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
2069 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
2072 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2073 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2074 (ins addrmode3:$addr), IndexModePre,
2076 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2078 let Inst{23} = addr{8}; // U bit
2079 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2080 let Inst{19-16} = addr{12-9}; // Rn
2081 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2082 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2083 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
2084 let DecoderMethod = "DecodeAddrMode3Instruction";
2086 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2087 (ins addr_offset_none:$addr, am3offset:$offset),
2088 IndexModePost, LdMiscFrm, itin,
2089 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2093 let Inst{23} = offset{8}; // U bit
2094 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2095 let Inst{19-16} = addr;
2096 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2097 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2098 let DecoderMethod = "DecodeAddrMode3Instruction";
2102 let mayLoad = 1, neverHasSideEffects = 1 in {
2103 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2104 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2105 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2106 let hasExtraDefRegAllocReq = 1 in {
2107 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2108 (ins addrmode3:$addr), IndexModePre,
2109 LdMiscFrm, IIC_iLoad_d_ru,
2110 "ldrd", "\t$Rt, $Rt2, $addr!",
2111 "$addr.base = $Rn_wb", []> {
2113 let Inst{23} = addr{8}; // U bit
2114 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2115 let Inst{19-16} = addr{12-9}; // Rn
2116 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2117 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2118 let DecoderMethod = "DecodeAddrMode3Instruction";
2119 let AsmMatchConverter = "cvtLdrdPre";
2121 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2122 (ins addr_offset_none:$addr, am3offset:$offset),
2123 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2124 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2125 "$addr.base = $Rn_wb", []> {
2128 let Inst{23} = offset{8}; // U bit
2129 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2130 let Inst{19-16} = addr;
2131 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2132 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2133 let DecoderMethod = "DecodeAddrMode3Instruction";
2135 } // hasExtraDefRegAllocReq = 1
2136 } // mayLoad = 1, neverHasSideEffects = 1
2138 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2139 let mayLoad = 1, neverHasSideEffects = 1 in {
2140 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2141 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2142 IndexModePost, LdFrm, IIC_iLoad_ru,
2143 "ldrt", "\t$Rt, $addr, $offset",
2144 "$addr.base = $Rn_wb", []> {
2150 let Inst{23} = offset{12};
2151 let Inst{21} = 1; // overwrite
2152 let Inst{19-16} = addr;
2153 let Inst{11-5} = offset{11-5};
2155 let Inst{3-0} = offset{3-0};
2156 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2159 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2160 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2161 IndexModePost, LdFrm, IIC_iLoad_ru,
2162 "ldrt", "\t$Rt, $addr, $offset",
2163 "$addr.base = $Rn_wb", []> {
2169 let Inst{23} = offset{12};
2170 let Inst{21} = 1; // overwrite
2171 let Inst{19-16} = addr;
2172 let Inst{11-0} = offset{11-0};
2173 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2176 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2177 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2178 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2179 "ldrbt", "\t$Rt, $addr, $offset",
2180 "$addr.base = $Rn_wb", []> {
2186 let Inst{23} = offset{12};
2187 let Inst{21} = 1; // overwrite
2188 let Inst{19-16} = addr;
2189 let Inst{11-5} = offset{11-5};
2191 let Inst{3-0} = offset{3-0};
2192 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2195 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2196 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2197 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2198 "ldrbt", "\t$Rt, $addr, $offset",
2199 "$addr.base = $Rn_wb", []> {
2205 let Inst{23} = offset{12};
2206 let Inst{21} = 1; // overwrite
2207 let Inst{19-16} = addr;
2208 let Inst{11-0} = offset{11-0};
2209 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2212 multiclass AI3ldrT<bits<4> op, string opc> {
2213 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2214 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2215 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2216 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2218 let Inst{23} = offset{8};
2220 let Inst{11-8} = offset{7-4};
2221 let Inst{3-0} = offset{3-0};
2222 let AsmMatchConverter = "cvtLdExtTWriteBackImm";
2224 def r : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2225 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2226 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2227 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2229 let Inst{23} = Rm{4};
2232 let Inst{3-0} = Rm{3-0};
2233 let AsmMatchConverter = "cvtLdExtTWriteBackReg";
2237 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2238 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2239 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2244 // Stores with truncate
2245 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2246 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2247 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2250 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2251 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2252 StMiscFrm, IIC_iStore_d_r,
2253 "strd", "\t$Rt, $src2, $addr", []>,
2254 Requires<[IsARM, HasV5TE]> {
2259 multiclass AI2_stridx<bit isByte, string opc, InstrItinClass itin> {
2260 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2261 (ins GPR:$Rt, addrmode_imm12:$addr), IndexModePre,
2263 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2266 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2267 let Inst{19-16} = addr{16-13}; // Rn
2268 let Inst{11-0} = addr{11-0}; // imm12
2269 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
2270 let DecoderMethod = "DecodeSTRPreImm";
2273 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2274 (ins GPR:$Rt, ldst_so_reg:$addr),
2275 IndexModePre, StFrm, itin,
2276 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2279 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2280 let Inst{19-16} = addr{16-13}; // Rn
2281 let Inst{11-0} = addr{11-0};
2282 let Inst{4} = 0; // Inst{4} = 0
2283 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2284 let DecoderMethod = "DecodeSTRPreReg";
2286 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2287 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2288 IndexModePost, StFrm, itin,
2289 opc, "\t$Rt, $addr, $offset",
2290 "$addr.base = $Rn_wb", []> {
2296 let Inst{23} = offset{12};
2297 let Inst{19-16} = addr;
2298 let Inst{11-0} = offset{11-0};
2300 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2303 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2304 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2305 IndexModePost, StFrm, itin,
2306 opc, "\t$Rt, $addr, $offset",
2307 "$addr.base = $Rn_wb", []> {
2313 let Inst{23} = offset{12};
2314 let Inst{19-16} = addr;
2315 let Inst{11-0} = offset{11-0};
2317 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2321 let mayStore = 1, neverHasSideEffects = 1 in {
2322 defm STR : AI2_stridx<0, "str", IIC_iStore_ru>;
2323 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_ru>;
2326 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2327 am2offset_reg:$offset),
2328 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2329 am2offset_reg:$offset)>;
2330 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2331 am2offset_imm:$offset),
2332 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2333 am2offset_imm:$offset)>;
2334 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2335 am2offset_reg:$offset),
2336 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2337 am2offset_reg:$offset)>;
2338 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2339 am2offset_imm:$offset),
2340 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2341 am2offset_imm:$offset)>;
2343 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2344 // put the patterns on the instruction definitions directly as ISel wants
2345 // the address base and offset to be separate operands, not a single
2346 // complex operand like we represent the instructions themselves. The
2347 // pseudos map between the two.
2348 let usesCustomInserter = 1,
2349 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2350 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2351 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2354 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2355 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2356 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2359 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2360 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2361 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2364 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2365 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2366 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2369 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2370 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2371 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2374 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2379 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2380 (ins GPR:$Rt, addrmode3:$addr), IndexModePre,
2381 StMiscFrm, IIC_iStore_bh_ru,
2382 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2384 let Inst{23} = addr{8}; // U bit
2385 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2386 let Inst{19-16} = addr{12-9}; // Rn
2387 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2388 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2389 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
2390 let DecoderMethod = "DecodeAddrMode3Instruction";
2393 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2394 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2395 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2396 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2397 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2398 addr_offset_none:$addr,
2399 am3offset:$offset))]> {
2402 let Inst{23} = offset{8}; // U bit
2403 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2404 let Inst{19-16} = addr;
2405 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2406 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2407 let DecoderMethod = "DecodeAddrMode3Instruction";
2410 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2411 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2412 (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2413 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2414 "strd", "\t$Rt, $Rt2, $addr!",
2415 "$addr.base = $Rn_wb", []> {
2417 let Inst{23} = addr{8}; // U bit
2418 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2419 let Inst{19-16} = addr{12-9}; // Rn
2420 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2421 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2422 let DecoderMethod = "DecodeAddrMode3Instruction";
2423 let AsmMatchConverter = "cvtStrdPre";
2426 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2427 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2429 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2430 "strd", "\t$Rt, $Rt2, $addr, $offset",
2431 "$addr.base = $Rn_wb", []> {
2434 let Inst{23} = offset{8}; // U bit
2435 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2436 let Inst{19-16} = addr;
2437 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2438 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2439 let DecoderMethod = "DecodeAddrMode3Instruction";
2441 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2443 // STRT, STRBT, and STRHT
2445 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2446 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2447 IndexModePost, StFrm, IIC_iStore_bh_ru,
2448 "strbt", "\t$Rt, $addr, $offset",
2449 "$addr.base = $Rn_wb", []> {
2455 let Inst{23} = offset{12};
2456 let Inst{21} = 1; // overwrite
2457 let Inst{19-16} = addr;
2458 let Inst{11-5} = offset{11-5};
2460 let Inst{3-0} = offset{3-0};
2461 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2464 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2465 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2466 IndexModePost, StFrm, IIC_iStore_bh_ru,
2467 "strbt", "\t$Rt, $addr, $offset",
2468 "$addr.base = $Rn_wb", []> {
2474 let Inst{23} = offset{12};
2475 let Inst{21} = 1; // overwrite
2476 let Inst{19-16} = addr;
2477 let Inst{11-0} = offset{11-0};
2478 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2481 let mayStore = 1, neverHasSideEffects = 1 in {
2482 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2483 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2484 IndexModePost, StFrm, IIC_iStore_ru,
2485 "strt", "\t$Rt, $addr, $offset",
2486 "$addr.base = $Rn_wb", []> {
2492 let Inst{23} = offset{12};
2493 let Inst{21} = 1; // overwrite
2494 let Inst{19-16} = addr;
2495 let Inst{11-5} = offset{11-5};
2497 let Inst{3-0} = offset{3-0};
2498 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2501 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2502 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2503 IndexModePost, StFrm, IIC_iStore_ru,
2504 "strt", "\t$Rt, $addr, $offset",
2505 "$addr.base = $Rn_wb", []> {
2511 let Inst{23} = offset{12};
2512 let Inst{21} = 1; // overwrite
2513 let Inst{19-16} = addr;
2514 let Inst{11-0} = offset{11-0};
2515 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2520 multiclass AI3strT<bits<4> op, string opc> {
2521 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2522 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2523 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2524 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2526 let Inst{23} = offset{8};
2528 let Inst{11-8} = offset{7-4};
2529 let Inst{3-0} = offset{3-0};
2530 let AsmMatchConverter = "cvtStExtTWriteBackImm";
2532 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2533 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2534 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2535 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2537 let Inst{23} = Rm{4};
2540 let Inst{3-0} = Rm{3-0};
2541 let AsmMatchConverter = "cvtStExtTWriteBackReg";
2546 defm STRHT : AI3strT<0b1011, "strht">;
2549 //===----------------------------------------------------------------------===//
2550 // Load / store multiple Instructions.
2553 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
2554 InstrItinClass itin, InstrItinClass itin_upd> {
2555 // IA is the default, so no need for an explicit suffix on the
2556 // mnemonic here. Without it is the cannonical spelling.
2558 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2559 IndexModeNone, f, itin,
2560 !strconcat(asm, "${p}\t$Rn, $regs"), "", []> {
2561 let Inst{24-23} = 0b01; // Increment After
2562 let Inst{21} = 0; // No writeback
2563 let Inst{20} = L_bit;
2566 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2567 IndexModeUpd, f, itin_upd,
2568 !strconcat(asm, "${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2569 let Inst{24-23} = 0b01; // Increment After
2570 let Inst{21} = 1; // Writeback
2571 let Inst{20} = L_bit;
2573 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2576 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2577 IndexModeNone, f, itin,
2578 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
2579 let Inst{24-23} = 0b00; // Decrement After
2580 let Inst{21} = 0; // No writeback
2581 let Inst{20} = L_bit;
2584 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2585 IndexModeUpd, f, itin_upd,
2586 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2587 let Inst{24-23} = 0b00; // Decrement After
2588 let Inst{21} = 1; // Writeback
2589 let Inst{20} = L_bit;
2591 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2594 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2595 IndexModeNone, f, itin,
2596 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
2597 let Inst{24-23} = 0b10; // Decrement Before
2598 let Inst{21} = 0; // No writeback
2599 let Inst{20} = L_bit;
2602 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2603 IndexModeUpd, f, itin_upd,
2604 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2605 let Inst{24-23} = 0b10; // Decrement Before
2606 let Inst{21} = 1; // Writeback
2607 let Inst{20} = L_bit;
2609 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2612 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2613 IndexModeNone, f, itin,
2614 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
2615 let Inst{24-23} = 0b11; // Increment Before
2616 let Inst{21} = 0; // No writeback
2617 let Inst{20} = L_bit;
2620 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2621 IndexModeUpd, f, itin_upd,
2622 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2623 let Inst{24-23} = 0b11; // Increment Before
2624 let Inst{21} = 1; // Writeback
2625 let Inst{20} = L_bit;
2627 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2631 let neverHasSideEffects = 1 in {
2633 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2634 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
2636 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2637 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
2639 } // neverHasSideEffects
2641 // FIXME: remove when we have a way to marking a MI with these properties.
2642 // FIXME: Should pc be an implicit operand like PICADD, etc?
2643 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2644 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2645 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2646 reglist:$regs, variable_ops),
2647 4, IIC_iLoad_mBr, [],
2648 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2649 RegConstraint<"$Rn = $wb">;
2651 //===----------------------------------------------------------------------===//
2652 // Move Instructions.
2655 let neverHasSideEffects = 1 in
2656 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2657 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2661 let Inst{19-16} = 0b0000;
2662 let Inst{11-4} = 0b00000000;
2665 let Inst{15-12} = Rd;
2668 // A version for the smaller set of tail call registers.
2669 let neverHasSideEffects = 1 in
2670 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2671 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2675 let Inst{11-4} = 0b00000000;
2678 let Inst{15-12} = Rd;
2681 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2682 DPSoRegRegFrm, IIC_iMOVsr,
2683 "mov", "\t$Rd, $src",
2684 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP {
2687 let Inst{15-12} = Rd;
2688 let Inst{19-16} = 0b0000;
2689 let Inst{11-8} = src{11-8};
2691 let Inst{6-5} = src{6-5};
2693 let Inst{3-0} = src{3-0};
2697 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
2698 DPSoRegImmFrm, IIC_iMOVsr,
2699 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
2703 let Inst{15-12} = Rd;
2704 let Inst{19-16} = 0b0000;
2705 let Inst{11-5} = src{11-5};
2707 let Inst{3-0} = src{3-0};
2711 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2712 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2713 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2717 let Inst{15-12} = Rd;
2718 let Inst{19-16} = 0b0000;
2719 let Inst{11-0} = imm;
2722 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2723 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
2725 "movw", "\t$Rd, $imm",
2726 [(set GPR:$Rd, imm0_65535:$imm)]>,
2727 Requires<[IsARM, HasV6T2]>, UnaryDP {
2730 let Inst{15-12} = Rd;
2731 let Inst{11-0} = imm{11-0};
2732 let Inst{19-16} = imm{15-12};
2737 def : InstAlias<"mov${p} $Rd, $imm",
2738 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
2741 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2742 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2744 let Constraints = "$src = $Rd" in {
2745 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
2746 (ins GPR:$src, imm0_65535_expr:$imm),
2748 "movt", "\t$Rd, $imm",
2750 (or (and GPR:$src, 0xffff),
2751 lo16AllZero:$imm))]>, UnaryDP,
2752 Requires<[IsARM, HasV6T2]> {
2755 let Inst{15-12} = Rd;
2756 let Inst{11-0} = imm{11-0};
2757 let Inst{19-16} = imm{15-12};
2762 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2763 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2767 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2768 Requires<[IsARM, HasV6T2]>;
2770 let Uses = [CPSR] in
2771 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2772 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2775 // These aren't really mov instructions, but we have to define them this way
2776 // due to flag operands.
2778 let Defs = [CPSR] in {
2779 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2780 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2782 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2783 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2787 //===----------------------------------------------------------------------===//
2788 // Extend Instructions.
2793 def SXTB : AI_ext_rrot<0b01101010,
2794 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2795 def SXTH : AI_ext_rrot<0b01101011,
2796 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2798 def SXTAB : AI_exta_rrot<0b01101010,
2799 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2800 def SXTAH : AI_exta_rrot<0b01101011,
2801 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2803 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2805 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2809 let AddedComplexity = 16 in {
2810 def UXTB : AI_ext_rrot<0b01101110,
2811 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2812 def UXTH : AI_ext_rrot<0b01101111,
2813 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2814 def UXTB16 : AI_ext_rrot<0b01101100,
2815 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2817 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2818 // The transformation should probably be done as a combiner action
2819 // instead so we can include a check for masking back in the upper
2820 // eight bits of the source into the lower eight bits of the result.
2821 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2822 // (UXTB16r_rot GPR:$Src, 3)>;
2823 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2824 (UXTB16 GPR:$Src, 1)>;
2826 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2827 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2828 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2829 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2832 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2833 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2836 def SBFX : I<(outs GPRnopc:$Rd),
2837 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
2838 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
2839 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2840 Requires<[IsARM, HasV6T2]> {
2845 let Inst{27-21} = 0b0111101;
2846 let Inst{6-4} = 0b101;
2847 let Inst{20-16} = width;
2848 let Inst{15-12} = Rd;
2849 let Inst{11-7} = lsb;
2853 def UBFX : I<(outs GPR:$Rd),
2854 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
2855 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
2856 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2857 Requires<[IsARM, HasV6T2]> {
2862 let Inst{27-21} = 0b0111111;
2863 let Inst{6-4} = 0b101;
2864 let Inst{20-16} = width;
2865 let Inst{15-12} = Rd;
2866 let Inst{11-7} = lsb;
2870 //===----------------------------------------------------------------------===//
2871 // Arithmetic Instructions.
2874 defm ADD : AsI1_bin_irs<0b0100, "add",
2875 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2876 BinOpFrag<(add node:$LHS, node:$RHS)>, "ADD", 1>;
2877 defm SUB : AsI1_bin_irs<0b0010, "sub",
2878 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2879 BinOpFrag<(sub node:$LHS, node:$RHS)>, "SUB">;
2881 // ADD and SUB with 's' bit set.
2882 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
2883 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2884 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
2885 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
2886 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2887 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
2889 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
2890 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>,
2892 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
2893 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>,
2896 // ADC and SUBC with 's' bit set.
2897 let usesCustomInserter = 1 in {
2898 defm ADCS : AI1_adde_sube_s_irs<
2899 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
2900 defm SBCS : AI1_adde_sube_s_irs<
2901 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
2904 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2905 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
2906 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
2911 let Inst{15-12} = Rd;
2912 let Inst{19-16} = Rn;
2913 let Inst{11-0} = imm;
2916 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2917 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm", []> {
2921 let Inst{11-4} = 0b00000000;
2924 let Inst{15-12} = Rd;
2925 let Inst{19-16} = Rn;
2928 def RSBrsi : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
2929 DPSoRegImmFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2930 [(set GPR:$Rd, (sub so_reg_imm:$shift, GPR:$Rn))]> {
2935 let Inst{19-16} = Rn;
2936 let Inst{15-12} = Rd;
2937 let Inst{11-5} = shift{11-5};
2939 let Inst{3-0} = shift{3-0};
2942 def RSBrsr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
2943 DPSoRegRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2944 [(set GPR:$Rd, (sub so_reg_reg:$shift, GPR:$Rn))]> {
2949 let Inst{19-16} = Rn;
2950 let Inst{15-12} = Rd;
2951 let Inst{11-8} = shift{11-8};
2953 let Inst{6-5} = shift{6-5};
2955 let Inst{3-0} = shift{3-0};
2958 // RSB with 's' bit set.
2959 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
2960 let usesCustomInserter = 1 in {
2961 def RSBSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2963 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]>;
2964 def RSBSrr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2966 def RSBSrsi : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
2968 [(set GPR:$Rd, (subc so_reg_imm:$shift, GPR:$Rn))]>;
2969 def RSBSrsr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
2971 [(set GPR:$Rd, (subc so_reg_reg:$shift, GPR:$Rn))]>;
2974 let Uses = [CPSR] in {
2975 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2976 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2977 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2983 let Inst{15-12} = Rd;
2984 let Inst{19-16} = Rn;
2985 let Inst{11-0} = imm;
2987 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2988 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm", []> {
2992 let Inst{11-4} = 0b00000000;
2995 let Inst{15-12} = Rd;
2996 let Inst{19-16} = Rn;
2998 def RSCrsi : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
2999 DPSoRegImmFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
3000 [(set GPR:$Rd, (sube_dead_carry so_reg_imm:$shift, GPR:$Rn))]>,
3006 let Inst{19-16} = Rn;
3007 let Inst{15-12} = Rd;
3008 let Inst{11-5} = shift{11-5};
3010 let Inst{3-0} = shift{3-0};
3012 def RSCrsr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
3013 DPSoRegRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
3014 [(set GPR:$Rd, (sube_dead_carry so_reg_reg:$shift, GPR:$Rn))]>,
3020 let Inst{19-16} = Rn;
3021 let Inst{15-12} = Rd;
3022 let Inst{11-8} = shift{11-8};
3024 let Inst{6-5} = shift{6-5};
3026 let Inst{3-0} = shift{3-0};
3031 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
3032 let usesCustomInserter = 1, Uses = [CPSR] in {
3033 def RSCSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
3035 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>;
3036 def RSCSrsi : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
3038 [(set GPR:$Rd, (sube_dead_carry so_reg_imm:$shift, GPR:$Rn))]>;
3039 def RSCSrsr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
3041 [(set GPR:$Rd, (sube_dead_carry so_reg_reg:$shift, GPR:$Rn))]>;
3044 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3045 // The assume-no-carry-in form uses the negation of the input since add/sub
3046 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3047 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3049 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3050 (SUBri GPR:$src, so_imm_neg:$imm)>;
3051 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
3052 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3053 // The with-carry-in form matches bitwise not instead of the negation.
3054 // Effectively, the inverse interpretation of the carry flag already accounts
3055 // for part of the negation.
3056 def : ARMPat<(adde_dead_carry GPR:$src, so_imm_not:$imm),
3057 (SBCri GPR:$src, so_imm_not:$imm)>;
3058 def : ARMPat<(adde_live_carry GPR:$src, so_imm_not:$imm),
3059 (SBCSri GPR:$src, so_imm_not:$imm)>;
3061 // Note: These are implemented in C++ code, because they have to generate
3062 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3064 // (mul X, 2^n+1) -> (add (X << n), X)
3065 // (mul X, 2^n-1) -> (rsb X, (X << n))
3067 // ARM Arithmetic Instruction
3068 // GPR:$dst = GPR:$a op GPR:$b
3069 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3070 list<dag> pattern = [],
3071 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3072 string asm = "\t$Rd, $Rn, $Rm">
3073 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
3077 let Inst{27-20} = op27_20;
3078 let Inst{11-4} = op11_4;
3079 let Inst{19-16} = Rn;
3080 let Inst{15-12} = Rd;
3084 // Saturating add/subtract
3086 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3087 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3088 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3089 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3090 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3091 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3092 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3093 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3095 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3096 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3099 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3100 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3101 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3102 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3103 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3104 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3105 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3106 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3107 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3108 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3109 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3110 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3112 // Signed/Unsigned add/subtract
3114 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3115 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3116 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3117 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3118 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3119 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3120 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3121 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3122 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3123 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3124 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3125 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3127 // Signed/Unsigned halving add/subtract
3129 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3130 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3131 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3132 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3133 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3134 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3135 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3136 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3137 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3138 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3139 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3140 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3142 // Unsigned Sum of Absolute Differences [and Accumulate].
3144 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3145 MulFrm /* for convenience */, NoItinerary, "usad8",
3146 "\t$Rd, $Rn, $Rm", []>,
3147 Requires<[IsARM, HasV6]> {
3151 let Inst{27-20} = 0b01111000;
3152 let Inst{15-12} = 0b1111;
3153 let Inst{7-4} = 0b0001;
3154 let Inst{19-16} = Rd;
3155 let Inst{11-8} = Rm;
3158 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3159 MulFrm /* for convenience */, NoItinerary, "usada8",
3160 "\t$Rd, $Rn, $Rm, $Ra", []>,
3161 Requires<[IsARM, HasV6]> {
3166 let Inst{27-20} = 0b01111000;
3167 let Inst{7-4} = 0b0001;
3168 let Inst{19-16} = Rd;
3169 let Inst{15-12} = Ra;
3170 let Inst{11-8} = Rm;
3174 // Signed/Unsigned saturate
3176 def SSAT : AI<(outs GPRnopc:$Rd),
3177 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3178 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3183 let Inst{27-21} = 0b0110101;
3184 let Inst{5-4} = 0b01;
3185 let Inst{20-16} = sat_imm;
3186 let Inst{15-12} = Rd;
3187 let Inst{11-7} = sh{4-0};
3188 let Inst{6} = sh{5};
3192 def SSAT16 : AI<(outs GPRnopc:$Rd),
3193 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3194 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3198 let Inst{27-20} = 0b01101010;
3199 let Inst{11-4} = 0b11110011;
3200 let Inst{15-12} = Rd;
3201 let Inst{19-16} = sat_imm;
3205 def USAT : AI<(outs GPRnopc:$Rd),
3206 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3207 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3212 let Inst{27-21} = 0b0110111;
3213 let Inst{5-4} = 0b01;
3214 let Inst{15-12} = Rd;
3215 let Inst{11-7} = sh{4-0};
3216 let Inst{6} = sh{5};
3217 let Inst{20-16} = sat_imm;
3221 def USAT16 : AI<(outs GPRnopc:$Rd),
3222 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3223 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3227 let Inst{27-20} = 0b01101110;
3228 let Inst{11-4} = 0b11110011;
3229 let Inst{15-12} = Rd;
3230 let Inst{19-16} = sat_imm;
3234 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3235 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3236 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3237 (USAT imm:$pos, GPRnopc:$a, 0)>;
3239 //===----------------------------------------------------------------------===//
3240 // Bitwise Instructions.
3243 defm AND : AsI1_bin_irs<0b0000, "and",
3244 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3245 BinOpFrag<(and node:$LHS, node:$RHS)>, "AND", 1>;
3246 defm ORR : AsI1_bin_irs<0b1100, "orr",
3247 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3248 BinOpFrag<(or node:$LHS, node:$RHS)>, "ORR", 1>;
3249 defm EOR : AsI1_bin_irs<0b0001, "eor",
3250 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3251 BinOpFrag<(xor node:$LHS, node:$RHS)>, "EOR", 1>;
3252 defm BIC : AsI1_bin_irs<0b1110, "bic",
3253 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3254 BinOpFrag<(and node:$LHS, (not node:$RHS))>, "BIC">;
3256 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3257 // like in the actual instruction encoding. The complexity of mapping the mask
3258 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3259 // instruction description.
3260 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3261 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3262 "bfc", "\t$Rd, $imm", "$src = $Rd",
3263 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3264 Requires<[IsARM, HasV6T2]> {
3267 let Inst{27-21} = 0b0111110;
3268 let Inst{6-0} = 0b0011111;
3269 let Inst{15-12} = Rd;
3270 let Inst{11-7} = imm{4-0}; // lsb
3271 let Inst{20-16} = imm{9-5}; // msb
3274 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3275 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3276 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3277 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3278 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3279 bf_inv_mask_imm:$imm))]>,
3280 Requires<[IsARM, HasV6T2]> {
3284 let Inst{27-21} = 0b0111110;
3285 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3286 let Inst{15-12} = Rd;
3287 let Inst{11-7} = imm{4-0}; // lsb
3288 let Inst{20-16} = imm{9-5}; // width
3292 // GNU as only supports this form of bfi (w/ 4 arguments)
3293 let isAsmParserOnly = 1 in
3294 def BFI4p : I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn,
3295 lsb_pos_imm:$lsb, width_imm:$width),
3296 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3297 "bfi", "\t$Rd, $Rn, $lsb, $width", "$src = $Rd",
3298 []>, Requires<[IsARM, HasV6T2]> {
3303 let Inst{27-21} = 0b0111110;
3304 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3305 let Inst{15-12} = Rd;
3306 let Inst{11-7} = lsb;
3307 let Inst{20-16} = width; // Custom encoder => lsb+width-1
3311 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3312 "mvn", "\t$Rd, $Rm",
3313 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
3317 let Inst{19-16} = 0b0000;
3318 let Inst{11-4} = 0b00000000;
3319 let Inst{15-12} = Rd;
3322 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3323 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3324 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
3328 let Inst{19-16} = 0b0000;
3329 let Inst{15-12} = Rd;
3330 let Inst{11-5} = shift{11-5};
3332 let Inst{3-0} = shift{3-0};
3334 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3335 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3336 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
3340 let Inst{19-16} = 0b0000;
3341 let Inst{15-12} = Rd;
3342 let Inst{11-8} = shift{11-8};
3344 let Inst{6-5} = shift{6-5};
3346 let Inst{3-0} = shift{3-0};
3348 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3349 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3350 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3351 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
3355 let Inst{19-16} = 0b0000;
3356 let Inst{15-12} = Rd;
3357 let Inst{11-0} = imm;
3360 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3361 (BICri GPR:$src, so_imm_not:$imm)>;
3363 //===----------------------------------------------------------------------===//
3364 // Multiply Instructions.
3366 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3367 string opc, string asm, list<dag> pattern>
3368 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3372 let Inst{19-16} = Rd;
3373 let Inst{11-8} = Rm;
3376 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3377 string opc, string asm, list<dag> pattern>
3378 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3383 let Inst{19-16} = RdHi;
3384 let Inst{15-12} = RdLo;
3385 let Inst{11-8} = Rm;
3389 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3390 // property. Remove them when it's possible to add those properties
3391 // on an individual MachineInstr, not just an instuction description.
3392 let isCommutable = 1 in {
3393 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3394 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3395 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
3396 Requires<[IsARM, HasV6]> {
3397 let Inst{15-12} = 0b0000;
3400 let Constraints = "@earlyclobber $Rd" in
3401 def MULv5: ARMPseudoExpand<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
3402 pred:$p, cc_out:$s),
3404 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))],
3405 (MUL GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3406 Requires<[IsARM, NoV6]>;
3409 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3410 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3411 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3412 Requires<[IsARM, HasV6]> {
3414 let Inst{15-12} = Ra;
3417 let Constraints = "@earlyclobber $Rd" in
3418 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3419 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3421 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3422 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3423 Requires<[IsARM, NoV6]>;
3425 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3426 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3427 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3428 Requires<[IsARM, HasV6T2]> {
3433 let Inst{19-16} = Rd;
3434 let Inst{15-12} = Ra;
3435 let Inst{11-8} = Rm;
3439 // Extra precision multiplies with low / high results
3440 let neverHasSideEffects = 1 in {
3441 let isCommutable = 1 in {
3442 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3443 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3444 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3445 Requires<[IsARM, HasV6]>;
3447 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3448 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3449 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3450 Requires<[IsARM, HasV6]>;
3452 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3453 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3454 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3456 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3457 Requires<[IsARM, NoV6]>;
3459 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3460 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3462 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3463 Requires<[IsARM, NoV6]>;
3467 // Multiply + accumulate
3468 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3469 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3470 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3471 Requires<[IsARM, HasV6]>;
3472 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3473 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3474 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3475 Requires<[IsARM, HasV6]>;
3477 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3478 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3479 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3480 Requires<[IsARM, HasV6]> {
3485 let Inst{19-16} = RdHi;
3486 let Inst{15-12} = RdLo;
3487 let Inst{11-8} = Rm;
3491 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3492 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3493 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3495 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3496 Requires<[IsARM, NoV6]>;
3497 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3498 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3500 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3501 Requires<[IsARM, NoV6]>;
3502 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3503 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3505 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3506 Requires<[IsARM, NoV6]>;
3509 } // neverHasSideEffects
3511 // Most significant word multiply
3512 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3513 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3514 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3515 Requires<[IsARM, HasV6]> {
3516 let Inst{15-12} = 0b1111;
3519 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3520 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3521 Requires<[IsARM, HasV6]> {
3522 let Inst{15-12} = 0b1111;
3525 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3526 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3527 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3528 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3529 Requires<[IsARM, HasV6]>;
3531 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3532 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3533 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3534 Requires<[IsARM, HasV6]>;
3536 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3537 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3538 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
3539 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
3540 Requires<[IsARM, HasV6]>;
3542 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3543 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3544 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3545 Requires<[IsARM, HasV6]>;
3547 multiclass AI_smul<string opc, PatFrag opnode> {
3548 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3549 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3550 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3551 (sext_inreg GPR:$Rm, i16)))]>,
3552 Requires<[IsARM, HasV5TE]>;
3554 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3555 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3556 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3557 (sra GPR:$Rm, (i32 16))))]>,
3558 Requires<[IsARM, HasV5TE]>;
3560 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3561 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3562 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3563 (sext_inreg GPR:$Rm, i16)))]>,
3564 Requires<[IsARM, HasV5TE]>;
3566 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3567 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3568 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3569 (sra GPR:$Rm, (i32 16))))]>,
3570 Requires<[IsARM, HasV5TE]>;
3572 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3573 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3574 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3575 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3576 Requires<[IsARM, HasV5TE]>;
3578 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3579 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3580 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3581 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3582 Requires<[IsARM, HasV5TE]>;
3586 multiclass AI_smla<string opc, PatFrag opnode> {
3587 let DecoderMethod = "DecodeSMLAInstruction" in {
3588 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3589 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3590 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3591 [(set GPRnopc:$Rd, (add GPR:$Ra,
3592 (opnode (sext_inreg GPRnopc:$Rn, i16),
3593 (sext_inreg GPRnopc:$Rm, i16))))]>,
3594 Requires<[IsARM, HasV5TE]>;
3596 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3597 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3598 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3600 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3601 (sra GPRnopc:$Rm, (i32 16)))))]>,
3602 Requires<[IsARM, HasV5TE]>;
3604 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3605 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3606 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3608 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3609 (sext_inreg GPRnopc:$Rm, i16))))]>,
3610 Requires<[IsARM, HasV5TE]>;
3612 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3613 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3614 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3616 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3617 (sra GPRnopc:$Rm, (i32 16)))))]>,
3618 Requires<[IsARM, HasV5TE]>;
3620 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3621 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3622 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3624 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3625 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3626 Requires<[IsARM, HasV5TE]>;
3628 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3629 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3630 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3632 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3633 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3634 Requires<[IsARM, HasV5TE]>;
3638 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3639 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3641 // Halfword multiply accumulate long: SMLAL<x><y>.
3642 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3643 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3644 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3645 Requires<[IsARM, HasV5TE]>;
3647 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3648 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3649 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3650 Requires<[IsARM, HasV5TE]>;
3652 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3653 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3654 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3655 Requires<[IsARM, HasV5TE]>;
3657 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3658 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3659 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3660 Requires<[IsARM, HasV5TE]>;
3662 // Helper class for AI_smld.
3663 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3664 InstrItinClass itin, string opc, string asm>
3665 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3668 let Inst{27-23} = 0b01110;
3669 let Inst{22} = long;
3670 let Inst{21-20} = 0b00;
3671 let Inst{11-8} = Rm;
3678 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3679 InstrItinClass itin, string opc, string asm>
3680 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3682 let Inst{15-12} = 0b1111;
3683 let Inst{19-16} = Rd;
3685 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3686 InstrItinClass itin, string opc, string asm>
3687 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3690 let Inst{19-16} = Rd;
3691 let Inst{15-12} = Ra;
3693 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3694 InstrItinClass itin, string opc, string asm>
3695 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3698 let Inst{19-16} = RdHi;
3699 let Inst{15-12} = RdLo;
3702 multiclass AI_smld<bit sub, string opc> {
3704 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3705 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3706 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3708 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3709 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3710 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3712 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3713 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3714 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3716 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3717 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3718 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3722 defm SMLA : AI_smld<0, "smla">;
3723 defm SMLS : AI_smld<1, "smls">;
3725 multiclass AI_sdml<bit sub, string opc> {
3727 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3728 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3729 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3730 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3733 defm SMUA : AI_sdml<0, "smua">;
3734 defm SMUS : AI_sdml<1, "smus">;
3736 //===----------------------------------------------------------------------===//
3737 // Misc. Arithmetic Instructions.
3740 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3741 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3742 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3744 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3745 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3746 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3747 Requires<[IsARM, HasV6T2]>;
3749 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3750 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3751 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3753 let AddedComplexity = 5 in
3754 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3755 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3756 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3757 Requires<[IsARM, HasV6]>;
3759 let AddedComplexity = 5 in
3760 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3761 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3762 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3763 Requires<[IsARM, HasV6]>;
3765 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3766 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3769 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
3770 (ins GPR:$Rn, GPR:$Rm, pkh_lsl_amt:$sh),
3771 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3772 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
3773 (and (shl GPR:$Rm, pkh_lsl_amt:$sh),
3775 Requires<[IsARM, HasV6]>;
3777 // Alternate cases for PKHBT where identities eliminate some nodes.
3778 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
3779 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
3780 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
3781 (PKHBT GPR:$Rn, GPR:$Rm, imm16_31:$sh)>;
3783 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3784 // will match the pattern below.
3785 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
3786 (ins GPR:$Rn, GPR:$Rm, pkh_asr_amt:$sh),
3787 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3788 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
3789 (and (sra GPR:$Rm, pkh_asr_amt:$sh),
3791 Requires<[IsARM, HasV6]>;
3793 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3794 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3795 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
3796 (PKHTB GPR:$src1, GPR:$src2, imm16_31:$sh)>;
3797 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
3798 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
3799 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$sh)>;
3801 //===----------------------------------------------------------------------===//
3802 // Comparison Instructions...
3805 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3806 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3807 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3809 // ARMcmpZ can re-use the above instruction definitions.
3810 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3811 (CMPri GPR:$src, so_imm:$imm)>;
3812 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3813 (CMPrr GPR:$src, GPR:$rhs)>;
3814 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
3815 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
3816 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
3817 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
3819 // FIXME: We have to be careful when using the CMN instruction and comparison
3820 // with 0. One would expect these two pieces of code should give identical
3836 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3837 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3838 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3839 // value of r0 and the carry bit (because the "carry bit" parameter to
3840 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3841 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3842 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3843 // parameter to AddWithCarry is defined as 0).
3845 // When x is 0 and unsigned:
3849 // ~x + 1 = 0x1 0000 0000
3850 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3852 // Therefore, we should disable CMN when comparing against zero, until we can
3853 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3854 // when it's a comparison which doesn't look at the 'carry' flag).
3856 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3858 // This is related to <rdar://problem/7569620>.
3860 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3861 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3863 // Note that TST/TEQ don't set all the same flags that CMP does!
3864 defm TST : AI1_cmp_irs<0b1000, "tst",
3865 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3866 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3867 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3868 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3869 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3871 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
3872 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3873 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
3875 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3876 // (CMNri GPR:$src, so_imm_neg:$imm)>;
3878 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3879 (CMNzri GPR:$src, so_imm_neg:$imm)>;
3881 // Pseudo i64 compares for some floating point compares.
3882 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3884 def BCCi64 : PseudoInst<(outs),
3885 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3887 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3889 def BCCZi64 : PseudoInst<(outs),
3890 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3891 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3892 } // usesCustomInserter
3895 // Conditional moves
3896 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3897 // a two-value operand where a dag node expects two operands. :(
3898 let neverHasSideEffects = 1 in {
3899 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3901 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3902 RegConstraint<"$false = $Rd">;
3903 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
3904 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
3906 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
3907 imm:$cc, CCR:$ccr))*/]>,
3908 RegConstraint<"$false = $Rd">;
3909 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
3910 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
3912 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
3913 imm:$cc, CCR:$ccr))*/]>,
3914 RegConstraint<"$false = $Rd">;
3917 let isMoveImm = 1 in
3918 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3919 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
3922 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3924 let isMoveImm = 1 in
3925 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3926 (ins GPR:$false, so_imm:$imm, pred:$p),
3928 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3929 RegConstraint<"$false = $Rd">;
3931 // Two instruction predicate mov immediate.
3932 let isMoveImm = 1 in
3933 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
3934 (ins GPR:$false, i32imm:$src, pred:$p),
3935 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3937 let isMoveImm = 1 in
3938 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
3939 (ins GPR:$false, so_imm:$imm, pred:$p),
3941 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3942 RegConstraint<"$false = $Rd">;
3943 } // neverHasSideEffects
3945 //===----------------------------------------------------------------------===//
3946 // Atomic operations intrinsics
3949 def MemBarrierOptOperand : AsmOperandClass {
3950 let Name = "MemBarrierOpt";
3951 let ParserMethod = "parseMemBarrierOptOperand";
3953 def memb_opt : Operand<i32> {
3954 let PrintMethod = "printMemBOption";
3955 let ParserMatchClass = MemBarrierOptOperand;
3956 let DecoderMethod = "DecodeMemBarrierOption";
3959 // memory barriers protect the atomic sequences
3960 let hasSideEffects = 1 in {
3961 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3962 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3963 Requires<[IsARM, HasDB]> {
3965 let Inst{31-4} = 0xf57ff05;
3966 let Inst{3-0} = opt;
3970 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3971 "dsb", "\t$opt", []>,
3972 Requires<[IsARM, HasDB]> {
3974 let Inst{31-4} = 0xf57ff04;
3975 let Inst{3-0} = opt;
3978 // ISB has only full system option
3979 def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3980 "isb", "\t$opt", []>,
3981 Requires<[IsARM, HasDB]> {
3983 let Inst{31-4} = 0xf57ff06;
3984 let Inst{3-0} = opt;
3987 let usesCustomInserter = 1 in {
3988 let Uses = [CPSR] in {
3989 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
3990 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3991 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
3992 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
3993 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3994 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
3995 def ATOMIC_LOAD_AND_I8 : PseudoInst<
3996 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3997 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
3998 def ATOMIC_LOAD_OR_I8 : PseudoInst<
3999 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4000 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4001 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4002 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4003 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4004 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4005 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4006 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4007 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4008 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4009 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4010 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4011 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4012 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4013 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4014 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4015 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4016 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4017 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4018 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4019 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4020 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4021 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4022 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4023 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4024 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4025 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4026 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4027 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4028 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4029 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4030 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4031 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4032 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4033 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4034 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4035 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4036 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4037 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4038 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4039 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4040 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4041 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4042 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4043 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4044 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4045 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4046 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4047 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4048 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4049 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4050 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4051 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4052 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4053 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4054 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4055 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4056 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4057 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4058 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4059 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4060 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4061 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4062 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4063 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4064 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4065 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4066 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4067 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4068 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4069 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4070 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4071 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4072 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4073 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4074 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4075 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4076 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4077 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4078 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4080 def ATOMIC_SWAP_I8 : PseudoInst<
4081 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4082 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4083 def ATOMIC_SWAP_I16 : PseudoInst<
4084 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4085 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4086 def ATOMIC_SWAP_I32 : PseudoInst<
4087 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4088 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4090 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4091 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4092 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4093 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4094 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4095 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4096 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4097 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4098 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4102 let mayLoad = 1 in {
4103 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4105 "ldrexb", "\t$Rt, $addr", []>;
4106 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4107 NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
4108 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4109 NoItinerary, "ldrex", "\t$Rt, $addr", []>;
4110 let hasExtraDefRegAllocReq = 1 in
4111 def LDREXD: AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2),(ins addr_offset_none:$addr),
4112 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []> {
4113 let DecoderMethod = "DecodeDoubleRegLoad";
4117 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4118 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4119 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
4120 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4121 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
4122 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4123 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
4126 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
4127 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4128 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr),
4129 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []> {
4130 let DecoderMethod = "DecodeDoubleRegStore";
4133 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
4134 Requires<[IsARM, HasV7]> {
4135 let Inst{31-0} = 0b11110101011111111111000000011111;
4138 // SWP/SWPB are deprecated in V6/V7.
4139 let mayLoad = 1, mayStore = 1 in {
4140 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
4142 def SWPB: AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
4146 //===----------------------------------------------------------------------===//
4147 // Coprocessor Instructions.
4150 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4151 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4152 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4153 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4154 imm:$CRm, imm:$opc2)]> {
4162 let Inst{3-0} = CRm;
4164 let Inst{7-5} = opc2;
4165 let Inst{11-8} = cop;
4166 let Inst{15-12} = CRd;
4167 let Inst{19-16} = CRn;
4168 let Inst{23-20} = opc1;
4171 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4172 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4173 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4174 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4175 imm:$CRm, imm:$opc2)]> {
4176 let Inst{31-28} = 0b1111;
4184 let Inst{3-0} = CRm;
4186 let Inst{7-5} = opc2;
4187 let Inst{11-8} = cop;
4188 let Inst{15-12} = CRd;
4189 let Inst{19-16} = CRn;
4190 let Inst{23-20} = opc1;
4193 class ACI<dag oops, dag iops, string opc, string asm,
4194 IndexMode im = IndexModeNone>
4195 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4197 let Inst{27-25} = 0b110;
4200 multiclass LdStCop<bits<4> op31_28, bit load, dag ops, string opc, string cond>{
4201 let DecoderNamespace = "Common" in {
4202 def _OFFSET : ACI<(outs),
4203 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
4204 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr"> {
4205 let Inst{31-28} = op31_28;
4206 let Inst{24} = 1; // P = 1
4207 let Inst{21} = 0; // W = 0
4208 let Inst{22} = 0; // D = 0
4209 let Inst{20} = load;
4210 let DecoderMethod = "DecodeCopMemInstruction";
4213 def _PRE : ACI<(outs),
4214 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
4215 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr!", IndexModePre> {
4216 let Inst{31-28} = op31_28;
4217 let Inst{24} = 1; // P = 1
4218 let Inst{21} = 1; // W = 1
4219 let Inst{22} = 0; // D = 0
4220 let Inst{20} = load;
4221 let DecoderMethod = "DecodeCopMemInstruction";
4224 def _POST : ACI<(outs),
4225 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
4226 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr", IndexModePost> {
4227 let Inst{31-28} = op31_28;
4228 let Inst{24} = 0; // P = 0
4229 let Inst{21} = 1; // W = 1
4230 let Inst{22} = 0; // D = 0
4231 let Inst{20} = load;
4232 let DecoderMethod = "DecodeCopMemInstruction";
4235 def _OPTION : ACI<(outs),
4236 !con((ins nohash_imm:$cop,nohash_imm:$CRd,GPR:$base, nohash_imm:$option),
4238 !strconcat(opc, cond), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
4239 let Inst{31-28} = op31_28;
4240 let Inst{24} = 0; // P = 0
4241 let Inst{23} = 1; // U = 1
4242 let Inst{21} = 0; // W = 0
4243 let Inst{22} = 0; // D = 0
4244 let Inst{20} = load;
4245 let DecoderMethod = "DecodeCopMemInstruction";
4248 def L_OFFSET : ACI<(outs),
4249 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
4250 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr"> {
4251 let Inst{31-28} = op31_28;
4252 let Inst{24} = 1; // P = 1
4253 let Inst{21} = 0; // W = 0
4254 let Inst{22} = 1; // D = 1
4255 let Inst{20} = load;
4256 let DecoderMethod = "DecodeCopMemInstruction";
4259 def L_PRE : ACI<(outs),
4260 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
4261 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr!",
4263 let Inst{31-28} = op31_28;
4264 let Inst{24} = 1; // P = 1
4265 let Inst{21} = 1; // W = 1
4266 let Inst{22} = 1; // D = 1
4267 let Inst{20} = load;
4268 let DecoderMethod = "DecodeCopMemInstruction";
4271 def L_POST : ACI<(outs),
4272 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addr_offset_none:$addr,
4273 postidx_imm8s4:$offset), ops),
4274 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr, $offset",
4276 let Inst{31-28} = op31_28;
4277 let Inst{24} = 0; // P = 0
4278 let Inst{21} = 1; // W = 1
4279 let Inst{22} = 1; // D = 1
4280 let Inst{20} = load;
4281 let DecoderMethod = "DecodeCopMemInstruction";
4284 def L_OPTION : ACI<(outs),
4285 !con((ins nohash_imm:$cop, nohash_imm:$CRd,GPR:$base,nohash_imm:$option),
4287 !strconcat(!strconcat(opc, "l"), cond),
4288 "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
4289 let Inst{31-28} = op31_28;
4290 let Inst{24} = 0; // P = 0
4291 let Inst{23} = 1; // U = 1
4292 let Inst{21} = 0; // W = 0
4293 let Inst{22} = 1; // D = 1
4294 let Inst{20} = load;
4295 let DecoderMethod = "DecodeCopMemInstruction";
4300 defm LDC : LdStCop<{?,?,?,?}, 1, (ins pred:$p), "ldc", "${p}">;
4301 defm LDC2 : LdStCop<0b1111, 1, (ins), "ldc2", "">;
4302 defm STC : LdStCop<{?,?,?,?}, 0, (ins pred:$p), "stc", "${p}">;
4303 defm STC2 : LdStCop<0b1111, 0, (ins), "stc2", "">;
4305 //===----------------------------------------------------------------------===//
4306 // Move between coprocessor and ARM core register.
4309 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4311 : ABI<0b1110, oops, iops, NoItinerary, opc,
4312 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4313 let Inst{20} = direction;
4323 let Inst{15-12} = Rt;
4324 let Inst{11-8} = cop;
4325 let Inst{23-21} = opc1;
4326 let Inst{7-5} = opc2;
4327 let Inst{3-0} = CRm;
4328 let Inst{19-16} = CRn;
4331 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4333 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4334 c_imm:$CRm, imm0_7:$opc2),
4335 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4336 imm:$CRm, imm:$opc2)]>;
4337 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4339 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4342 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4343 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4345 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4347 : ABXI<0b1110, oops, iops, NoItinerary,
4348 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4349 let Inst{31-28} = 0b1111;
4350 let Inst{20} = direction;
4360 let Inst{15-12} = Rt;
4361 let Inst{11-8} = cop;
4362 let Inst{23-21} = opc1;
4363 let Inst{7-5} = opc2;
4364 let Inst{3-0} = CRm;
4365 let Inst{19-16} = CRn;
4368 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4370 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4371 c_imm:$CRm, imm0_7:$opc2),
4372 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4373 imm:$CRm, imm:$opc2)]>;
4374 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4376 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4379 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4380 imm:$CRm, imm:$opc2),
4381 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4383 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4384 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4385 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
4386 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4387 let Inst{23-21} = 0b010;
4388 let Inst{20} = direction;
4396 let Inst{15-12} = Rt;
4397 let Inst{19-16} = Rt2;
4398 let Inst{11-8} = cop;
4399 let Inst{7-4} = opc1;
4400 let Inst{3-0} = CRm;
4403 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4404 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4406 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4408 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4409 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4410 GPR:$Rt, GPR:$Rt2, c_imm:$CRm), NoItinerary,
4411 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4412 let Inst{31-28} = 0b1111;
4413 let Inst{23-21} = 0b010;
4414 let Inst{20} = direction;
4422 let Inst{15-12} = Rt;
4423 let Inst{19-16} = Rt2;
4424 let Inst{11-8} = cop;
4425 let Inst{7-4} = opc1;
4426 let Inst{3-0} = CRm;
4429 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4430 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4432 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4434 //===----------------------------------------------------------------------===//
4435 // Move between special register and ARM core register
4438 // Move to ARM core register from Special Register
4439 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
4440 "mrs", "\t$Rd, apsr", []> {
4442 let Inst{23-16} = 0b00001111;
4443 let Inst{15-12} = Rd;
4444 let Inst{7-4} = 0b0000;
4447 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPR:$Rd, pred:$p)>, Requires<[IsARM]>;
4449 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
4450 "mrs", "\t$Rd, spsr", []> {
4452 let Inst{23-16} = 0b01001111;
4453 let Inst{15-12} = Rd;
4454 let Inst{7-4} = 0b0000;
4457 // Move from ARM core register to Special Register
4459 // No need to have both system and application versions, the encodings are the
4460 // same and the assembly parser has no way to distinguish between them. The mask
4461 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4462 // the mask with the fields to be accessed in the special register.
4463 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4464 "msr", "\t$mask, $Rn", []> {
4469 let Inst{22} = mask{4}; // R bit
4470 let Inst{21-20} = 0b10;
4471 let Inst{19-16} = mask{3-0};
4472 let Inst{15-12} = 0b1111;
4473 let Inst{11-4} = 0b00000000;
4477 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4478 "msr", "\t$mask, $a", []> {
4483 let Inst{22} = mask{4}; // R bit
4484 let Inst{21-20} = 0b10;
4485 let Inst{19-16} = mask{3-0};
4486 let Inst{15-12} = 0b1111;
4490 //===----------------------------------------------------------------------===//
4494 // __aeabi_read_tp preserves the registers r1-r3.
4495 // This is a pseudo inst so that we can get the encoding right,
4496 // complete with fixup for the aeabi_read_tp function.
4498 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4499 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4500 [(set R0, ARMthread_pointer)]>;
4503 //===----------------------------------------------------------------------===//
4504 // SJLJ Exception handling intrinsics
4505 // eh_sjlj_setjmp() is an instruction sequence to store the return
4506 // address and save #0 in R0 for the non-longjmp case.
4507 // Since by its nature we may be coming from some other function to get
4508 // here, and we're using the stack frame for the containing function to
4509 // save/restore registers, we can't keep anything live in regs across
4510 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4511 // when we get here from a longjmp(). We force everything out of registers
4512 // except for our own input by listing the relevant registers in Defs. By
4513 // doing so, we also cause the prologue/epilogue code to actively preserve
4514 // all of the callee-saved resgisters, which is exactly what we want.
4515 // A constant value is passed in $val, and we use the location as a scratch.
4517 // These are pseudo-instructions and are lowered to individual MC-insts, so
4518 // no encoding information is necessary.
4520 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4521 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ], hasSideEffects = 1, isBarrier = 1 in {
4522 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4524 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4525 Requires<[IsARM, HasVFP2]>;
4529 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4530 hasSideEffects = 1, isBarrier = 1 in {
4531 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4533 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4534 Requires<[IsARM, NoVFP]>;
4537 // FIXME: Non-Darwin version(s)
4538 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4539 Defs = [ R7, LR, SP ] in {
4540 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4542 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4543 Requires<[IsARM, IsDarwin]>;
4546 // eh.sjlj.dispatchsetup pseudo-instruction.
4547 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
4548 // handled when the pseudo is expanded (which happens before any passes
4549 // that need the instruction size).
4550 let isBarrier = 1, hasSideEffects = 1 in
4551 def Int_eh_sjlj_dispatchsetup :
4552 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
4553 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
4554 Requires<[IsDarwin]>;
4556 //===----------------------------------------------------------------------===//
4557 // Non-Instruction Patterns
4560 // ARMv4 indirect branch using (MOVr PC, dst)
4561 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4562 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4563 4, IIC_Br, [(brind GPR:$dst)],
4564 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4565 Requires<[IsARM, NoV4T]>;
4567 // Large immediate handling.
4569 // 32-bit immediate using two piece so_imms or movw + movt.
4570 // This is a single pseudo instruction, the benefit is that it can be remat'd
4571 // as a single unit instead of having to handle reg inputs.
4572 // FIXME: Remove this when we can do generalized remat.
4573 let isReMaterializable = 1, isMoveImm = 1 in
4574 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4575 [(set GPR:$dst, (arm_i32imm:$src))]>,
4578 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4579 // It also makes it possible to rematerialize the instructions.
4580 // FIXME: Remove this when we can do generalized remat and when machine licm
4581 // can properly the instructions.
4582 let isReMaterializable = 1 in {
4583 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4585 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4586 Requires<[IsARM, UseMovt]>;
4588 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4590 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4591 Requires<[IsARM, UseMovt]>;
4593 let AddedComplexity = 10 in
4594 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4596 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4597 Requires<[IsARM, UseMovt]>;
4598 } // isReMaterializable
4600 // ConstantPool, GlobalAddress, and JumpTable
4601 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4602 Requires<[IsARM, DontUseMovt]>;
4603 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4604 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4605 Requires<[IsARM, UseMovt]>;
4606 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4607 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4609 // TODO: add,sub,and, 3-instr forms?
4612 def : ARMPat<(ARMtcret tcGPR:$dst),
4613 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
4615 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
4616 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
4618 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
4619 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
4621 def : ARMPat<(ARMtcret tcGPR:$dst),
4622 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
4624 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
4625 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
4627 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
4628 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
4631 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
4632 Requires<[IsARM, IsNotDarwin]>;
4633 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
4634 Requires<[IsARM, IsDarwin]>;
4636 // zextload i1 -> zextload i8
4637 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4638 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4640 // extload -> zextload
4641 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4642 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4643 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4644 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4646 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4648 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4649 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4652 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4653 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4654 (SMULBB GPR:$a, GPR:$b)>;
4655 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4656 (SMULBB GPR:$a, GPR:$b)>;
4657 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4658 (sra GPR:$b, (i32 16))),
4659 (SMULBT GPR:$a, GPR:$b)>;
4660 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
4661 (SMULBT GPR:$a, GPR:$b)>;
4662 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4663 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4664 (SMULTB GPR:$a, GPR:$b)>;
4665 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
4666 (SMULTB GPR:$a, GPR:$b)>;
4667 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4669 (SMULWB GPR:$a, GPR:$b)>;
4670 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
4671 (SMULWB GPR:$a, GPR:$b)>;
4673 def : ARMV5TEPat<(add GPR:$acc,
4674 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4675 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4676 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4677 def : ARMV5TEPat<(add GPR:$acc,
4678 (mul sext_16_node:$a, sext_16_node:$b)),
4679 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4680 def : ARMV5TEPat<(add GPR:$acc,
4681 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4682 (sra GPR:$b, (i32 16)))),
4683 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4684 def : ARMV5TEPat<(add GPR:$acc,
4685 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
4686 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4687 def : ARMV5TEPat<(add GPR:$acc,
4688 (mul (sra GPR:$a, (i32 16)),
4689 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4690 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4691 def : ARMV5TEPat<(add GPR:$acc,
4692 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
4693 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4694 def : ARMV5TEPat<(add GPR:$acc,
4695 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4697 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4698 def : ARMV5TEPat<(add GPR:$acc,
4699 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
4700 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4703 // Pre-v7 uses MCR for synchronization barriers.
4704 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
4705 Requires<[IsARM, HasV6]>;
4707 // SXT/UXT with no rotate
4708 let AddedComplexity = 16 in {
4709 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
4710 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
4711 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
4712 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
4713 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
4714 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
4715 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
4718 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
4719 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
4721 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
4722 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
4723 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
4724 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
4726 // Atomic load/store patterns
4727 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
4728 (LDRBrs ldst_so_reg:$src)>;
4729 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
4730 (LDRBi12 addrmode_imm12:$src)>;
4731 def : ARMPat<(atomic_load_16 addrmode3:$src),
4732 (LDRH addrmode3:$src)>;
4733 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
4734 (LDRrs ldst_so_reg:$src)>;
4735 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
4736 (LDRi12 addrmode_imm12:$src)>;
4737 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
4738 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
4739 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
4740 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
4741 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
4742 (STRH GPR:$val, addrmode3:$ptr)>;
4743 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
4744 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
4745 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
4746 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
4749 //===----------------------------------------------------------------------===//
4753 include "ARMInstrThumb.td"
4755 //===----------------------------------------------------------------------===//
4759 include "ARMInstrThumb2.td"
4761 //===----------------------------------------------------------------------===//
4762 // Floating Point Support
4765 include "ARMInstrVFP.td"
4767 //===----------------------------------------------------------------------===//
4768 // Advanced SIMD (NEON) Support
4771 include "ARMInstrNEON.td"
4773 //===----------------------------------------------------------------------===//
4774 // Assembler aliases
4778 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
4779 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
4780 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
4782 // System instructions
4783 def : MnemonicAlias<"swi", "svc">;
4785 // Load / Store Multiple
4786 def : MnemonicAlias<"ldmfd", "ldm">;
4787 def : MnemonicAlias<"ldmia", "ldm">;
4788 def : MnemonicAlias<"stmfd", "stmdb">;
4789 def : MnemonicAlias<"stmia", "stm">;
4790 def : MnemonicAlias<"stmea", "stm">;
4792 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4793 // shift amount is zero (i.e., unspecified).
4794 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4795 (PKHBT GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>,
4796 Requires<[IsARM, HasV6]>;
4797 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4798 (PKHBT GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>,
4799 Requires<[IsARM, HasV6]>;
4801 // PUSH/POP aliases for STM/LDM
4802 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
4803 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4805 // RSB two-operand forms (optional explicit destination operand)
4806 def : ARMInstAlias<"rsb${s}${p} $Rdn, $imm",
4807 (RSBri GPR:$Rdn, GPR:$Rdn, so_imm:$imm, pred:$p, cc_out:$s)>;
4808 def : ARMInstAlias<"rsb${s}${p} $Rdn, $Rm",
4809 (RSBrr GPR:$Rdn, GPR:$Rdn, GPR:$Rm, pred:$p, cc_out:$s)>;
4810 def : ARMInstAlias<"rsb${s}${p} $Rdn, $shift",
4811 (RSBrsi GPR:$Rdn, GPR:$Rdn, so_reg_imm:$shift, pred:$p,
4813 def : ARMInstAlias<"rsb${s}${p} $Rdn, $shift",
4814 (RSBrsr GPR:$Rdn, GPR:$Rdn, so_reg_reg:$shift, pred:$p,
4816 // RSC two-operand forms (optional explicit destination operand)
4817 def : ARMInstAlias<"rsc${s}${p} $Rdn, $imm",
4818 (RSCri GPR:$Rdn, GPR:$Rdn, so_imm:$imm, pred:$p, cc_out:$s)>;
4819 def : ARMInstAlias<"rsc${s}${p} $Rdn, $Rm",
4820 (RSCrr GPR:$Rdn, GPR:$Rdn, GPR:$Rm, pred:$p, cc_out:$s)>;
4821 def : ARMInstAlias<"rsc${s}${p} $Rdn, $shift",
4822 (RSCrsi GPR:$Rdn, GPR:$Rdn, so_reg_imm:$shift, pred:$p,
4824 def : ARMInstAlias<"rsc${s}${p} $Rdn, $shift",
4825 (RSCrsr GPR:$Rdn, GPR:$Rdn, so_reg_reg:$shift, pred:$p,
4828 // SSAT/USAT optional shift operand.
4829 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4830 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4831 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4832 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4835 // Extend instruction optional rotate operand.
4836 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4837 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4838 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4839 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4840 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4841 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4842 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
4843 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4844 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
4845 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4846 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
4847 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4849 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4850 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4851 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4852 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4853 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4854 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4855 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
4856 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4857 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
4858 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4859 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
4860 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4864 def : MnemonicAlias<"rfefa", "rfeda">;
4865 def : MnemonicAlias<"rfeea", "rfedb">;
4866 def : MnemonicAlias<"rfefd", "rfeia">;
4867 def : MnemonicAlias<"rfeed", "rfeib">;
4868 def : MnemonicAlias<"rfe", "rfeia">;
4871 def : MnemonicAlias<"srsfa", "srsda">;
4872 def : MnemonicAlias<"srsea", "srsdb">;
4873 def : MnemonicAlias<"srsfd", "srsia">;
4874 def : MnemonicAlias<"srsed", "srsib">;
4875 def : MnemonicAlias<"srs", "srsia">;
4877 // LDRSBT/LDRHT/LDRSHT post-index offset if optional.
4878 // Note that the write-back output register is a dummy operand for MC (it's
4879 // only meaningful for codegen), so we just pass zero here.
4880 // FIXME: tblgen not cooperating with argument conversions.
4881 //def : InstAlias<"ldrsbt${p} $Rt, $addr",
4882 // (LDRSBTi GPR:$Rt, GPR:$Rt, addr_offset_none:$addr, 0,pred:$p)>;
4883 //def : InstAlias<"ldrht${p} $Rt, $addr",
4884 // (LDRHTi GPR:$Rt, GPR:$Rt, addr_offset_none:$addr, 0, pred:$p)>;
4885 //def : InstAlias<"ldrsht${p} $Rt, $addr",
4886 // (LDRSHTi GPR:$Rt, GPR:$Rt, addr_offset_none:$addr, 0, pred:$p)>;