1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
43 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
44 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
46 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
47 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
50 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
51 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
53 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
54 [SDNPHasChain, SDNPOutFlag]>;
55 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
56 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
58 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
59 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
60 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
61 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
62 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
63 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
65 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
66 [SDNPHasChain, SDNPOptInFlag]>;
68 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
70 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
73 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
74 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
76 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
78 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
81 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
84 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
85 [SDNPOutFlag,SDNPCommutative]>;
87 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
89 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
90 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
91 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
93 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
94 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", SDT_ARMEH_SJLJ_Setjmp>;
96 //===----------------------------------------------------------------------===//
97 // ARM Instruction Predicate Definitions.
99 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
100 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
101 def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
102 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">;
103 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
104 def HasV7 : Predicate<"Subtarget->hasV7Ops()">;
105 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">;
106 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">;
107 def HasNEON : Predicate<"Subtarget->hasNEON()">;
108 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
109 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
110 def IsThumb : Predicate<"Subtarget->isThumb()">;
111 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
112 def IsThumb2 : Predicate<"Subtarget->isThumb2()">;
113 def IsARM : Predicate<"!Subtarget->isThumb()">;
114 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
115 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
116 def CarryDefIsUnused : Predicate<"!N.getNode()->hasAnyUseOfValue(1)">;
117 def CarryDefIsUsed : Predicate<"N.getNode()->hasAnyUseOfValue(1)">;
119 //===----------------------------------------------------------------------===//
120 // ARM Flag Definitions.
122 class RegConstraint<string C> {
123 string Constraints = C;
126 //===----------------------------------------------------------------------===//
127 // ARM specific transformation functions and pattern fragments.
130 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
131 // so_imm_neg def below.
132 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
133 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
136 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
137 // so_imm_not def below.
138 def so_imm_not_XFORM : SDNodeXForm<imm, [{
139 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
142 // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
143 def rot_imm : PatLeaf<(i32 imm), [{
144 int32_t v = (int32_t)N->getZExtValue();
145 return v == 8 || v == 16 || v == 24;
148 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
149 def imm1_15 : PatLeaf<(i32 imm), [{
150 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
153 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
154 def imm16_31 : PatLeaf<(i32 imm), [{
155 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
160 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
161 }], so_imm_neg_XFORM>;
165 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
166 }], so_imm_not_XFORM>;
168 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
169 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
170 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
173 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
175 def bf_inv_mask_imm : Operand<i32>,
177 uint32_t v = (uint32_t)N->getZExtValue();
180 // there can be 1's on either or both "outsides", all the "inside"
182 unsigned int lsb = 0, msb = 31;
183 while (v & (1 << msb)) --msb;
184 while (v & (1 << lsb)) ++lsb;
185 for (unsigned int i = lsb; i <= msb; ++i) {
191 let PrintMethod = "printBitfieldInvMaskImmOperand";
194 /// Split a 32-bit immediate into two 16 bit parts.
195 def lo16 : SDNodeXForm<imm, [{
196 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
200 def hi16 : SDNodeXForm<imm, [{
201 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
204 def lo16AllZero : PatLeaf<(i32 imm), [{
205 // Returns true if all low 16-bits are 0.
206 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
209 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
211 def imm0_65535 : PatLeaf<(i32 imm), [{
212 return (uint32_t)N->getZExtValue() < 65536;
215 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
216 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
218 //===----------------------------------------------------------------------===//
219 // Operand Definitions.
223 def brtarget : Operand<OtherVT>;
225 // A list of registers separated by comma. Used by load/store multiple.
226 def reglist : Operand<i32> {
227 let PrintMethod = "printRegisterList";
230 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
231 def cpinst_operand : Operand<i32> {
232 let PrintMethod = "printCPInstOperand";
235 def jtblock_operand : Operand<i32> {
236 let PrintMethod = "printJTBlockOperand";
238 def jt2block_operand : Operand<i32> {
239 let PrintMethod = "printJT2BlockOperand";
243 def pclabel : Operand<i32> {
244 let PrintMethod = "printPCLabel";
247 // shifter_operand operands: so_reg and so_imm.
248 def so_reg : Operand<i32>, // reg reg imm
249 ComplexPattern<i32, 3, "SelectShifterOperandReg",
250 [shl,srl,sra,rotr]> {
251 let PrintMethod = "printSORegOperand";
252 let MIOperandInfo = (ops GPR, GPR, i32imm);
255 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
256 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
257 // represented in the imm field in the same 12-bit form that they are encoded
258 // into so_imm instructions: the 8-bit immediate is the least significant bits
259 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
260 def so_imm : Operand<i32>,
262 return ARM_AM::getSOImmVal(N->getZExtValue()) != -1;
264 let PrintMethod = "printSOImmOperand";
267 // Break so_imm's up into two pieces. This handles immediates with up to 16
268 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
269 // get the first/second pieces.
270 def so_imm2part : Operand<i32>,
272 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
274 let PrintMethod = "printSOImm2PartOperand";
277 def so_imm2part_1 : SDNodeXForm<imm, [{
278 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
279 return CurDAG->getTargetConstant(V, MVT::i32);
282 def so_imm2part_2 : SDNodeXForm<imm, [{
283 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
284 return CurDAG->getTargetConstant(V, MVT::i32);
287 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
288 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
289 return (int32_t)N->getZExtValue() < 32;
292 // Define ARM specific addressing modes.
294 // addrmode2 := reg +/- reg shop imm
295 // addrmode2 := reg +/- imm12
297 def addrmode2 : Operand<i32>,
298 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
299 let PrintMethod = "printAddrMode2Operand";
300 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
303 def am2offset : Operand<i32>,
304 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
305 let PrintMethod = "printAddrMode2OffsetOperand";
306 let MIOperandInfo = (ops GPR, i32imm);
309 // addrmode3 := reg +/- reg
310 // addrmode3 := reg +/- imm8
312 def addrmode3 : Operand<i32>,
313 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
314 let PrintMethod = "printAddrMode3Operand";
315 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
318 def am3offset : Operand<i32>,
319 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
320 let PrintMethod = "printAddrMode3OffsetOperand";
321 let MIOperandInfo = (ops GPR, i32imm);
324 // addrmode4 := reg, <mode|W>
326 def addrmode4 : Operand<i32>,
327 ComplexPattern<i32, 2, "SelectAddrMode4", []> {
328 let PrintMethod = "printAddrMode4Operand";
329 let MIOperandInfo = (ops GPR, i32imm);
332 // addrmode5 := reg +/- imm8*4
334 def addrmode5 : Operand<i32>,
335 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
336 let PrintMethod = "printAddrMode5Operand";
337 let MIOperandInfo = (ops GPR, i32imm);
340 // addrmode6 := reg with optional writeback
342 def addrmode6 : Operand<i32>,
343 ComplexPattern<i32, 3, "SelectAddrMode6", []> {
344 let PrintMethod = "printAddrMode6Operand";
345 let MIOperandInfo = (ops GPR:$addr, GPR:$upd, i32imm);
348 // addrmodepc := pc + reg
350 def addrmodepc : Operand<i32>,
351 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
352 let PrintMethod = "printAddrModePCOperand";
353 let MIOperandInfo = (ops GPR, i32imm);
356 def nohash_imm : Operand<i32> {
357 let PrintMethod = "printNoHashImmediate";
360 //===----------------------------------------------------------------------===//
362 include "ARMInstrFormats.td"
364 //===----------------------------------------------------------------------===//
365 // Multiclass helpers...
368 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
369 /// binop that produces a value.
370 multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
371 bit Commutable = 0> {
372 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
373 IIC_iALUi, opc, "\t$dst, $a, $b",
374 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
377 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
378 IIC_iALUr, opc, "\t$dst, $a, $b",
379 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
382 let isCommutable = Commutable;
384 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
385 IIC_iALUsr, opc, "\t$dst, $a, $b",
386 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
393 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
394 /// instruction modifies the CPSR register.
395 let Defs = [CPSR] in {
396 multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
397 bit Commutable = 0> {
398 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
399 IIC_iALUi, opc, "s\t$dst, $a, $b",
400 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
404 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
405 IIC_iALUr, opc, "s\t$dst, $a, $b",
406 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
407 let isCommutable = Commutable;
412 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
413 IIC_iALUsr, opc, "s\t$dst, $a, $b",
414 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
423 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
424 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
425 /// a explicit result, only implicitly set CPSR.
426 let Defs = [CPSR] in {
427 multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode,
428 bit Commutable = 0> {
429 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm, IIC_iCMPi,
431 [(opnode GPR:$a, so_imm:$b)]> {
435 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm, IIC_iCMPr,
437 [(opnode GPR:$a, GPR:$b)]> {
441 let isCommutable = Commutable;
443 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm, IIC_iCMPsr,
445 [(opnode GPR:$a, so_reg:$b)]> {
454 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
455 /// register and one whose operand is a register rotated by 8/16/24.
456 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
457 multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
458 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src),
459 IIC_iUNAr, opc, "\t$dst, $src",
460 [(set GPR:$dst, (opnode GPR:$src))]>,
461 Requires<[IsARM, HasV6]> {
462 let Inst{11-10} = 0b00;
463 let Inst{19-16} = 0b1111;
465 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src, i32imm:$rot),
466 IIC_iUNAsi, opc, "\t$dst, $src, ror $rot",
467 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>,
468 Requires<[IsARM, HasV6]> {
469 let Inst{19-16} = 0b1111;
473 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
474 /// register and one whose operand is a register rotated by 8/16/24.
475 multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
476 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
477 IIC_iALUr, opc, "\t$dst, $LHS, $RHS",
478 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
479 Requires<[IsARM, HasV6]> {
480 let Inst{11-10} = 0b00;
482 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
483 IIC_iALUsi, opc, "\t$dst, $LHS, $RHS, ror $rot",
484 [(set GPR:$dst, (opnode GPR:$LHS,
485 (rotr GPR:$RHS, rot_imm:$rot)))]>,
486 Requires<[IsARM, HasV6]>;
489 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
490 let Uses = [CPSR] in {
491 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
492 bit Commutable = 0> {
493 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
494 DPFrm, IIC_iALUi, opc, "\t$dst, $a, $b",
495 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
496 Requires<[IsARM, CarryDefIsUnused]> {
499 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
500 DPFrm, IIC_iALUr, opc, "\t$dst, $a, $b",
501 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
502 Requires<[IsARM, CarryDefIsUnused]> {
503 let isCommutable = Commutable;
507 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
508 DPSoRegFrm, IIC_iALUsr, opc, "\t$dst, $a, $b",
509 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
510 Requires<[IsARM, CarryDefIsUnused]> {
515 // Carry setting variants
516 def Sri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
517 DPFrm, IIC_iALUi, !strconcat(opc, "s\t$dst, $a, $b"),
518 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
519 Requires<[IsARM, CarryDefIsUsed]> {
524 def Srr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
525 DPFrm, IIC_iALUr, !strconcat(opc, "s\t$dst, $a, $b"),
526 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
527 Requires<[IsARM, CarryDefIsUsed]> {
533 def Srs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
534 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "s\t$dst, $a, $b"),
535 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
536 Requires<[IsARM, CarryDefIsUsed]> {
546 //===----------------------------------------------------------------------===//
548 //===----------------------------------------------------------------------===//
550 //===----------------------------------------------------------------------===//
551 // Miscellaneous Instructions.
554 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
555 /// the function. The first operand is the ID# for this instruction, the second
556 /// is the index into the MachineConstantPool that this is, the third is the
557 /// size in bytes of this constant pool entry.
558 let neverHasSideEffects = 1, isNotDuplicable = 1 in
559 def CONSTPOOL_ENTRY :
560 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
561 i32imm:$size), NoItinerary,
562 "${instid:label} ${cpidx:cpentry}", []>;
564 let Defs = [SP], Uses = [SP] in {
566 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
567 "@ ADJCALLSTACKUP $amt1",
568 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
570 def ADJCALLSTACKDOWN :
571 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
572 "@ ADJCALLSTACKDOWN $amt",
573 [(ARMcallseq_start timm:$amt)]>;
577 PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file), NoItinerary,
578 ".loc $file, $line, $col",
579 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
582 // Address computation and loads and stores in PIC mode.
583 let isNotDuplicable = 1 in {
584 def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
585 Pseudo, IIC_iALUr, "\n$cp:\n\tadd$p\t$dst, pc, $a",
586 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
588 let AddedComplexity = 10 in {
589 let canFoldAsLoad = 1 in
590 def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
591 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr$p\t$dst, $addr",
592 [(set GPR:$dst, (load addrmodepc:$addr))]>;
594 def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
595 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}h\t$dst, $addr",
596 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
598 def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
599 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}b\t$dst, $addr",
600 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
602 def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
603 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}sh\t$dst, $addr",
604 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
606 def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
607 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}sb\t$dst, $addr",
608 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
610 let AddedComplexity = 10 in {
611 def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
612 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr$p\t$src, $addr",
613 [(store GPR:$src, addrmodepc:$addr)]>;
615 def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
616 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr${p}h\t$src, $addr",
617 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
619 def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
620 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr${p}b\t$src, $addr",
621 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
623 } // isNotDuplicable = 1
626 // LEApcrel - Load a pc-relative address into a register without offending the
628 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
630 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, ($label-(",
631 "${:private}PCRELL${:uid}+8))\n"),
632 !strconcat("${:private}PCRELL${:uid}:\n\t",
633 "add$p\t$dst, pc, #${:private}PCRELV${:uid}")),
636 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
637 (ins i32imm:$label, nohash_imm:$id, pred:$p),
639 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, "
641 "${:private}PCRELL${:uid}+8))\n"),
642 !strconcat("${:private}PCRELL${:uid}:\n\t",
643 "add$p\t$dst, pc, #${:private}PCRELV${:uid}")),
648 //===----------------------------------------------------------------------===//
649 // Control Flow Instructions.
652 let isReturn = 1, isTerminator = 1, isBarrier = 1 in
653 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
654 "bx", "\tlr", [(ARMretflag)]> {
655 let Inst{7-4} = 0b0001;
656 let Inst{19-8} = 0b111111111111;
657 let Inst{27-20} = 0b00010010;
660 // FIXME: remove when we have a way to marking a MI with these properties.
661 // FIXME: Should pc be an implicit operand like PICADD, etc?
662 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
663 hasExtraDefRegAllocReq = 1 in
664 def LDM_RET : AXI4ld<(outs),
665 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
666 LdStMulFrm, IIC_Br, "ldm${p}${addr:submode}\t$addr, $wb",
669 // On non-Darwin platforms R9 is callee-saved.
671 Defs = [R0, R1, R2, R3, R12, LR,
672 D0, D1, D2, D3, D4, D5, D6, D7,
673 D16, D17, D18, D19, D20, D21, D22, D23,
674 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
675 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
676 IIC_Br, "bl\t${func:call}",
677 [(ARMcall tglobaladdr:$func)]>,
678 Requires<[IsARM, IsNotDarwin]>;
680 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
681 IIC_Br, "bl", "\t${func:call}",
682 [(ARMcall_pred tglobaladdr:$func)]>,
683 Requires<[IsARM, IsNotDarwin]>;
686 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
687 IIC_Br, "blx\t$func",
688 [(ARMcall GPR:$func)]>,
689 Requires<[IsARM, HasV5T, IsNotDarwin]> {
690 let Inst{7-4} = 0b0011;
691 let Inst{19-8} = 0b111111111111;
692 let Inst{27-20} = 0b00010010;
696 def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops),
697 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
698 [(ARMcall_nolink GPR:$func)]>,
699 Requires<[IsARM, IsNotDarwin]> {
700 let Inst{7-4} = 0b0001;
701 let Inst{19-8} = 0b111111111111;
702 let Inst{27-20} = 0b00010010;
706 // On Darwin R9 is call-clobbered.
708 Defs = [R0, R1, R2, R3, R9, R12, LR,
709 D0, D1, D2, D3, D4, D5, D6, D7,
710 D16, D17, D18, D19, D20, D21, D22, D23,
711 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
712 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
713 IIC_Br, "bl\t${func:call}",
714 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]>;
716 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
717 IIC_Br, "bl", "\t${func:call}",
718 [(ARMcall_pred tglobaladdr:$func)]>,
719 Requires<[IsARM, IsDarwin]>;
722 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
723 IIC_Br, "blx\t$func",
724 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
725 let Inst{7-4} = 0b0011;
726 let Inst{19-8} = 0b111111111111;
727 let Inst{27-20} = 0b00010010;
731 def BXr9 : ABXIx2<(outs), (ins GPR:$func, variable_ops),
732 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
733 [(ARMcall_nolink GPR:$func)]>, Requires<[IsARM, IsDarwin]> {
734 let Inst{7-4} = 0b0001;
735 let Inst{19-8} = 0b111111111111;
736 let Inst{27-20} = 0b00010010;
740 let isBranch = 1, isTerminator = 1 in {
741 // B is "predicable" since it can be xformed into a Bcc.
742 let isBarrier = 1 in {
743 let isPredicable = 1 in
744 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
745 "b\t$target", [(br bb:$target)]>;
747 let isNotDuplicable = 1, isIndirectBranch = 1 in {
748 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
749 IIC_Br, "mov\tpc, $target \n$jt",
750 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
751 let Inst{20} = 0; // S Bit
752 let Inst{24-21} = 0b1101;
753 let Inst{27-25} = 0b000;
755 def BR_JTm : JTI<(outs),
756 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
757 IIC_Br, "ldr\tpc, $target \n$jt",
758 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
760 let Inst{20} = 1; // L bit
761 let Inst{21} = 0; // W bit
762 let Inst{22} = 0; // B bit
763 let Inst{24} = 1; // P bit
764 let Inst{27-25} = 0b011;
766 def BR_JTadd : JTI<(outs),
767 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
768 IIC_Br, "add\tpc, $target, $idx \n$jt",
769 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
771 let Inst{20} = 0; // S bit
772 let Inst{24-21} = 0b0100;
773 let Inst{27-25} = 0b000;
775 } // isNotDuplicable = 1, isIndirectBranch = 1
778 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
779 // a two-value operand where a dag node expects two operands. :(
780 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
781 IIC_Br, "b", "\t$target",
782 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
785 //===----------------------------------------------------------------------===//
786 // Load / store Instructions.
790 let canFoldAsLoad = 1, isReMaterializable = 1 in
791 def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
792 "ldr", "\t$dst, $addr",
793 [(set GPR:$dst, (load addrmode2:$addr))]>;
795 // Special LDR for loads from non-pc-relative constpools.
796 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
797 def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
798 "ldr", "\t$dst, $addr", []>;
800 // Loads with zero extension
801 def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
802 IIC_iLoadr, "ldr", "h\t$dst, $addr",
803 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
805 def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
806 IIC_iLoadr, "ldr", "b\t$dst, $addr",
807 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
809 // Loads with sign extension
810 def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
811 IIC_iLoadr, "ldr", "sh\t$dst, $addr",
812 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
814 def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
815 IIC_iLoadr, "ldr", "sb\t$dst, $addr",
816 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
818 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
820 def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
821 IIC_iLoadr, "ldr", "d\t$dst1, $addr",
822 []>, Requires<[IsARM, HasV5TE]>;
825 def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
826 (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
827 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
829 def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
830 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoadru,
831 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
833 def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
834 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
835 "ldr", "h\t$dst, $addr!", "$addr.base = $base_wb", []>;
837 def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
838 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
839 "ldr", "h\t$dst, [$base], $offset", "$base = $base_wb", []>;
841 def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
842 (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
843 "ldr", "b\t$dst, $addr!", "$addr.base = $base_wb", []>;
845 def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
846 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoadru,
847 "ldr", "b\t$dst, [$base], $offset", "$base = $base_wb", []>;
849 def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
850 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
851 "ldr", "sh\t$dst, $addr!", "$addr.base = $base_wb", []>;
853 def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
854 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
855 "ldr", "sh\t$dst, [$base], $offset", "$base = $base_wb", []>;
857 def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
858 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
859 "ldr", "sb\t$dst, $addr!", "$addr.base = $base_wb", []>;
861 def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
862 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
863 "ldr", "sb\t$dst, [$base], $offset", "$base = $base_wb", []>;
867 def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
868 "str", "\t$src, $addr",
869 [(store GPR:$src, addrmode2:$addr)]>;
871 // Stores with truncate
872 def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, IIC_iStorer,
873 "str", "h\t$src, $addr",
874 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
876 def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
877 "str", "b\t$src, $addr",
878 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
881 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
882 def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
883 StMiscFrm, IIC_iStorer,
884 "str", "d\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
887 def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
888 (ins GPR:$src, GPR:$base, am2offset:$offset),
890 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
892 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
894 def STR_POST : AI2stwpo<(outs GPR:$base_wb),
895 (ins GPR:$src, GPR:$base,am2offset:$offset),
897 "str", "\t$src, [$base], $offset", "$base = $base_wb",
899 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
901 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
902 (ins GPR:$src, GPR:$base,am3offset:$offset),
903 StMiscFrm, IIC_iStoreru,
904 "str", "h\t$src, [$base, $offset]!", "$base = $base_wb",
906 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
908 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
909 (ins GPR:$src, GPR:$base,am3offset:$offset),
910 StMiscFrm, IIC_iStoreru,
911 "str", "h\t$src, [$base], $offset", "$base = $base_wb",
912 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
913 GPR:$base, am3offset:$offset))]>;
915 def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
916 (ins GPR:$src, GPR:$base,am2offset:$offset),
918 "str", "b\t$src, [$base, $offset]!", "$base = $base_wb",
919 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
920 GPR:$base, am2offset:$offset))]>;
922 def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
923 (ins GPR:$src, GPR:$base,am2offset:$offset),
925 "str", "b\t$src, [$base], $offset", "$base = $base_wb",
926 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
927 GPR:$base, am2offset:$offset))]>;
929 //===----------------------------------------------------------------------===//
930 // Load / store multiple Instructions.
933 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
934 def LDM : AXI4ld<(outs),
935 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
936 LdStMulFrm, IIC_iLoadm, "ldm${p}${addr:submode}\t$addr, $wb",
939 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
940 def STM : AXI4st<(outs),
941 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
942 LdStMulFrm, IIC_iStorem, "stm${p}${addr:submode}\t$addr, $wb",
945 //===----------------------------------------------------------------------===//
946 // Move Instructions.
949 let neverHasSideEffects = 1 in
950 def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
951 "mov", "\t$dst, $src", []>, UnaryDP {
956 def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src),
957 DPSoRegFrm, IIC_iMOVsr,
958 "mov", "\t$dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP {
964 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
965 def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm, IIC_iMOVi,
966 "mov", "\t$dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP {
970 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
971 def MOVi16 : AI1<0b1000, (outs GPR:$dst), (ins i32imm:$src),
973 "movw", "\t$dst, $src",
974 [(set GPR:$dst, imm0_65535:$src)]>,
975 Requires<[IsARM, HasV6T2]> {
980 let Constraints = "$src = $dst" in
981 def MOVTi16 : AI1<0b1010, (outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
983 "movt", "\t$dst, $imm",
985 (or (and GPR:$src, 0xffff),
986 lo16AllZero:$imm))]>, UnaryDP,
987 Requires<[IsARM, HasV6T2]> {
992 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
993 Requires<[IsARM, HasV6T2]>;
996 def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, IIC_iMOVsi,
997 "mov", "\t$dst, $src, rrx",
998 [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
1000 // These aren't really mov instructions, but we have to define them this way
1001 // due to flag operands.
1003 let Defs = [CPSR] in {
1004 def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
1005 IIC_iMOVsi, "mov", "s\t$dst, $src, lsr #1",
1006 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP;
1007 def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
1008 IIC_iMOVsi, "mov", "s\t$dst, $src, asr #1",
1009 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP;
1012 //===----------------------------------------------------------------------===//
1013 // Extend Instructions.
1018 defm SXTB : AI_unary_rrot<0b01101010,
1019 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
1020 defm SXTH : AI_unary_rrot<0b01101011,
1021 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
1023 defm SXTAB : AI_bin_rrot<0b01101010,
1024 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1025 defm SXTAH : AI_bin_rrot<0b01101011,
1026 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1028 // TODO: SXT(A){B|H}16
1032 let AddedComplexity = 16 in {
1033 defm UXTB : AI_unary_rrot<0b01101110,
1034 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
1035 defm UXTH : AI_unary_rrot<0b01101111,
1036 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1037 defm UXTB16 : AI_unary_rrot<0b01101100,
1038 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1040 def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1041 (UXTB16r_rot GPR:$Src, 24)>;
1042 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1043 (UXTB16r_rot GPR:$Src, 8)>;
1045 defm UXTAB : AI_bin_rrot<0b01101110, "uxtab",
1046 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1047 defm UXTAH : AI_bin_rrot<0b01101111, "uxtah",
1048 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1051 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
1052 //defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
1054 // TODO: UXT(A){B|H}16
1056 def SBFX : I<(outs GPR:$dst),
1057 (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1058 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1059 "sbfx", "\t$dst, $src, $lsb, $width", "", []>,
1060 Requires<[IsARM, HasV6T2]> {
1061 let Inst{27-21} = 0b0111101;
1062 let Inst{6-4} = 0b101;
1065 def UBFX : I<(outs GPR:$dst),
1066 (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1067 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1068 "ubfx", "\t$dst, $src, $lsb, $width", "", []>,
1069 Requires<[IsARM, HasV6T2]> {
1070 let Inst{27-21} = 0b0111111;
1071 let Inst{6-4} = 0b101;
1074 //===----------------------------------------------------------------------===//
1075 // Arithmetic Instructions.
1078 defm ADD : AsI1_bin_irs<0b0100, "add",
1079 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1080 defm SUB : AsI1_bin_irs<0b0010, "sub",
1081 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1083 // ADD and SUB with 's' bit set.
1084 defm ADDS : AI1_bin_s_irs<0b0100, "add",
1085 BinOpFrag<(addc node:$LHS, node:$RHS)>>;
1086 defm SUBS : AI1_bin_s_irs<0b0010, "sub",
1087 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1089 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
1090 BinOpFrag<(adde node:$LHS, node:$RHS)>, 1>;
1091 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
1092 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
1094 // These don't define reg/reg forms, because they are handled above.
1095 def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1096 IIC_iALUi, "rsb", "\t$dst, $a, $b",
1097 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]> {
1102 def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1103 IIC_iALUsr, "rsb", "\t$dst, $a, $b",
1104 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]> {
1111 // RSB with 's' bit set.
1112 let Defs = [CPSR] in {
1113 def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1114 IIC_iALUi, "rsb", "s\t$dst, $a, $b",
1115 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]> {
1119 def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1120 IIC_iALUsr, "rsb", "s\t$dst, $a, $b",
1121 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]> {
1129 let Uses = [CPSR] in {
1130 def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1131 DPFrm, IIC_iALUi, "rsc", "\t$dst, $a, $b",
1132 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
1133 Requires<[IsARM, CarryDefIsUnused]> {
1136 def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1137 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$dst, $a, $b",
1138 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
1139 Requires<[IsARM, CarryDefIsUnused]> {
1146 // FIXME: Allow these to be predicated.
1147 let Defs = [CPSR], Uses = [CPSR] in {
1148 def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1149 DPFrm, IIC_iALUi, "rscs\t$dst, $a, $b",
1150 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
1151 Requires<[IsARM, CarryDefIsUnused]> {
1155 def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1156 DPSoRegFrm, IIC_iALUsr, "rscs\t$dst, $a, $b",
1157 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
1158 Requires<[IsARM, CarryDefIsUnused]> {
1166 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1167 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
1168 (SUBri GPR:$src, so_imm_neg:$imm)>;
1170 //def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
1171 // (SUBSri GPR:$src, so_imm_neg:$imm)>;
1172 //def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
1173 // (SBCri GPR:$src, so_imm_neg:$imm)>;
1175 // Note: These are implemented in C++ code, because they have to generate
1176 // ADD/SUBrs instructions, which use a complex pattern that a xform function
1178 // (mul X, 2^n+1) -> (add (X << n), X)
1179 // (mul X, 2^n-1) -> (rsb X, (X << n))
1182 //===----------------------------------------------------------------------===//
1183 // Bitwise Instructions.
1186 defm AND : AsI1_bin_irs<0b0000, "and",
1187 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
1188 defm ORR : AsI1_bin_irs<0b1100, "orr",
1189 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
1190 defm EOR : AsI1_bin_irs<0b0001, "eor",
1191 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
1192 defm BIC : AsI1_bin_irs<0b1110, "bic",
1193 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1195 def BFC : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
1196 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1197 "bfc", "\t$dst, $imm", "$src = $dst",
1198 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
1199 Requires<[IsARM, HasV6T2]> {
1200 let Inst{27-21} = 0b0111110;
1201 let Inst{6-0} = 0b0011111;
1204 def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
1205 "mvn", "\t$dst, $src",
1206 [(set GPR:$dst, (not GPR:$src))]>, UnaryDP {
1209 def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
1210 IIC_iMOVsr, "mvn", "\t$dst, $src",
1211 [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP {
1215 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1216 def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
1217 IIC_iMOVi, "mvn", "\t$dst, $imm",
1218 [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP {
1222 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
1223 (BICri GPR:$src, so_imm_not:$imm)>;
1225 //===----------------------------------------------------------------------===//
1226 // Multiply Instructions.
1229 let isCommutable = 1 in
1230 def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1231 IIC_iMUL32, "mul", "\t$dst, $a, $b",
1232 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
1234 def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1235 IIC_iMAC32, "mla", "\t$dst, $a, $b, $c",
1236 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
1238 def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1239 IIC_iMAC32, "mls", "\t$dst, $a, $b, $c",
1240 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
1241 Requires<[IsARM, HasV6T2]>;
1243 // Extra precision multiplies with low / high results
1244 let neverHasSideEffects = 1 in {
1245 let isCommutable = 1 in {
1246 def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst),
1247 (ins GPR:$a, GPR:$b), IIC_iMUL64,
1248 "smull", "\t$ldst, $hdst, $a, $b", []>;
1250 def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst),
1251 (ins GPR:$a, GPR:$b), IIC_iMUL64,
1252 "umull", "\t$ldst, $hdst, $a, $b", []>;
1255 // Multiply + accumulate
1256 def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst),
1257 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1258 "smlal", "\t$ldst, $hdst, $a, $b", []>;
1260 def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst),
1261 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1262 "umlal", "\t$ldst, $hdst, $a, $b", []>;
1264 def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst),
1265 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1266 "umaal", "\t$ldst, $hdst, $a, $b", []>,
1267 Requires<[IsARM, HasV6]>;
1268 } // neverHasSideEffects
1270 // Most significant word multiply
1271 def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1272 IIC_iMUL32, "smmul", "\t$dst, $a, $b",
1273 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
1274 Requires<[IsARM, HasV6]> {
1275 let Inst{7-4} = 0b0001;
1276 let Inst{15-12} = 0b1111;
1279 def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1280 IIC_iMAC32, "smmla", "\t$dst, $a, $b, $c",
1281 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
1282 Requires<[IsARM, HasV6]> {
1283 let Inst{7-4} = 0b0001;
1287 def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1288 IIC_iMAC32, "smmls", "\t$dst, $a, $b, $c",
1289 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
1290 Requires<[IsARM, HasV6]> {
1291 let Inst{7-4} = 0b1101;
1294 multiclass AI_smul<string opc, PatFrag opnode> {
1295 def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1296 IIC_iMUL32, !strconcat(opc, "bb"), "\t$dst, $a, $b",
1297 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1298 (sext_inreg GPR:$b, i16)))]>,
1299 Requires<[IsARM, HasV5TE]> {
1304 def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1305 IIC_iMUL32, !strconcat(opc, "bt"), "\t$dst, $a, $b",
1306 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1307 (sra GPR:$b, (i32 16))))]>,
1308 Requires<[IsARM, HasV5TE]> {
1313 def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1314 IIC_iMUL32, !strconcat(opc, "tb"), "\t$dst, $a, $b",
1315 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1316 (sext_inreg GPR:$b, i16)))]>,
1317 Requires<[IsARM, HasV5TE]> {
1322 def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1323 IIC_iMUL32, !strconcat(opc, "tt"), "\t$dst, $a, $b",
1324 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1325 (sra GPR:$b, (i32 16))))]>,
1326 Requires<[IsARM, HasV5TE]> {
1331 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1332 IIC_iMUL16, !strconcat(opc, "wb"), "\t$dst, $a, $b",
1333 [(set GPR:$dst, (sra (opnode GPR:$a,
1334 (sext_inreg GPR:$b, i16)), (i32 16)))]>,
1335 Requires<[IsARM, HasV5TE]> {
1340 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1341 IIC_iMUL16, !strconcat(opc, "wt"), "\t$dst, $a, $b",
1342 [(set GPR:$dst, (sra (opnode GPR:$a,
1343 (sra GPR:$b, (i32 16))), (i32 16)))]>,
1344 Requires<[IsARM, HasV5TE]> {
1351 multiclass AI_smla<string opc, PatFrag opnode> {
1352 def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1353 IIC_iMAC16, !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
1354 [(set GPR:$dst, (add GPR:$acc,
1355 (opnode (sext_inreg GPR:$a, i16),
1356 (sext_inreg GPR:$b, i16))))]>,
1357 Requires<[IsARM, HasV5TE]> {
1362 def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1363 IIC_iMAC16, !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
1364 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1365 (sra GPR:$b, (i32 16)))))]>,
1366 Requires<[IsARM, HasV5TE]> {
1371 def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1372 IIC_iMAC16, !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
1373 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1374 (sext_inreg GPR:$b, i16))))]>,
1375 Requires<[IsARM, HasV5TE]> {
1380 def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1381 IIC_iMAC16, !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
1382 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1383 (sra GPR:$b, (i32 16)))))]>,
1384 Requires<[IsARM, HasV5TE]> {
1389 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1390 IIC_iMAC16, !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
1391 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1392 (sext_inreg GPR:$b, i16)), (i32 16))))]>,
1393 Requires<[IsARM, HasV5TE]> {
1398 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1399 IIC_iMAC16, !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
1400 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1401 (sra GPR:$b, (i32 16))), (i32 16))))]>,
1402 Requires<[IsARM, HasV5TE]> {
1408 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1409 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1411 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
1412 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1414 //===----------------------------------------------------------------------===//
1415 // Misc. Arithmetic Instructions.
1418 def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1419 "clz", "\t$dst, $src",
1420 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> {
1421 let Inst{7-4} = 0b0001;
1422 let Inst{11-8} = 0b1111;
1423 let Inst{19-16} = 0b1111;
1426 def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1427 "rev", "\t$dst, $src",
1428 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> {
1429 let Inst{7-4} = 0b0011;
1430 let Inst{11-8} = 0b1111;
1431 let Inst{19-16} = 0b1111;
1434 def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1435 "rev16", "\t$dst, $src",
1437 (or (and (srl GPR:$src, (i32 8)), 0xFF),
1438 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
1439 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
1440 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>,
1441 Requires<[IsARM, HasV6]> {
1442 let Inst{7-4} = 0b1011;
1443 let Inst{11-8} = 0b1111;
1444 let Inst{19-16} = 0b1111;
1447 def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1448 "revsh", "\t$dst, $src",
1451 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
1452 (shl GPR:$src, (i32 8))), i16))]>,
1453 Requires<[IsARM, HasV6]> {
1454 let Inst{7-4} = 0b1011;
1455 let Inst{11-8} = 0b1111;
1456 let Inst{19-16} = 0b1111;
1459 def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst),
1460 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1461 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, LSL $shamt",
1462 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1463 (and (shl GPR:$src2, (i32 imm:$shamt)),
1465 Requires<[IsARM, HasV6]> {
1466 let Inst{6-4} = 0b001;
1469 // Alternate cases for PKHBT where identities eliminate some nodes.
1470 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1471 (PKHBT GPR:$src1, GPR:$src2, 0)>;
1472 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1473 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1476 def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst),
1477 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1478 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, ASR $shamt",
1479 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1480 (and (sra GPR:$src2, imm16_31:$shamt),
1481 0xFFFF)))]>, Requires<[IsARM, HasV6]> {
1482 let Inst{6-4} = 0b101;
1485 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
1486 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1487 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
1488 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1489 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1490 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1491 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1493 //===----------------------------------------------------------------------===//
1494 // Comparison Instructions...
1497 defm CMP : AI1_cmp_irs<0b1010, "cmp",
1498 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1499 defm CMN : AI1_cmp_irs<0b1011, "cmn",
1500 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1502 // Note that TST/TEQ don't set all the same flags that CMP does!
1503 defm TST : AI1_cmp_irs<0b1000, "tst",
1504 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>, 1>;
1505 defm TEQ : AI1_cmp_irs<0b1001, "teq",
1506 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>, 1>;
1508 defm CMPz : AI1_cmp_irs<0b1010, "cmp",
1509 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
1510 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
1511 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
1513 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1514 (CMNri GPR:$src, so_imm_neg:$imm)>;
1516 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
1517 (CMNri GPR:$src, so_imm_neg:$imm)>;
1520 // Conditional moves
1521 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1522 // a two-value operand where a dag node expects two operands. :(
1523 def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
1524 IIC_iCMOVr, "mov", "\t$dst, $true",
1525 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1526 RegConstraint<"$false = $dst">, UnaryDP {
1531 def MOVCCs : AI1<0b1101, (outs GPR:$dst),
1532 (ins GPR:$false, so_reg:$true), DPSoRegFrm, IIC_iCMOVsr,
1533 "mov", "\t$dst, $true",
1534 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
1535 RegConstraint<"$false = $dst">, UnaryDP {
1541 def MOVCCi : AI1<0b1101, (outs GPR:$dst),
1542 (ins GPR:$false, so_imm:$true), DPFrm, IIC_iCMOVi,
1543 "mov", "\t$dst, $true",
1544 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1545 RegConstraint<"$false = $dst">, UnaryDP {
1550 //===----------------------------------------------------------------------===//
1554 // __aeabi_read_tp preserves the registers r1-r3.
1556 Defs = [R0, R12, LR, CPSR] in {
1557 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
1558 "bl\t__aeabi_read_tp",
1559 [(set R0, ARMthread_pointer)]>;
1562 //===----------------------------------------------------------------------===//
1563 // SJLJ Exception handling intrinsics
1564 // eh_sjlj_setjmp() is an instruction sequence to store the return
1565 // address and save #0 in R0 for the non-longjmp case.
1566 // Since by its nature we may be coming from some other function to get
1567 // here, and we're using the stack frame for the containing function to
1568 // save/restore registers, we can't keep anything live in regs across
1569 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
1570 // when we get here from a longjmp(). We force everthing out of registers
1571 // except for our own input by listing the relevant registers in Defs. By
1572 // doing so, we also cause the prologue/epilogue code to actively preserve
1573 // all of the callee-saved resgisters, which is exactly what we want.
1575 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
1576 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
1577 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
1579 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src),
1580 AddrModeNone, SizeSpecial, IndexModeNone,
1581 Pseudo, NoItinerary,
1582 "str\tsp, [$src, #+8] @ eh_setjmp begin\n\t"
1583 "add\tr12, pc, #8\n\t"
1584 "str\tr12, [$src, #+4]\n\t"
1586 "add\tpc, pc, #0\n\t"
1587 "mov\tr0, #1 @ eh_setjmp end", "",
1588 [(set R0, (ARMeh_sjlj_setjmp GPR:$src))]>;
1591 //===----------------------------------------------------------------------===//
1592 // Non-Instruction Patterns
1595 // ConstantPool, GlobalAddress, and JumpTable
1596 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>;
1597 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
1598 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1599 (LEApcrelJT tjumptable:$dst, imm:$id)>;
1601 // Large immediate handling.
1603 // Two piece so_imms.
1604 let isReMaterializable = 1 in
1605 def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src),
1607 "mov", "\t$dst, $src",
1608 [(set GPR:$dst, so_imm2part:$src)]>,
1609 Requires<[IsARM, NoV6T2]>;
1611 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
1612 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1613 (so_imm2part_2 imm:$RHS))>;
1614 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
1615 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1616 (so_imm2part_2 imm:$RHS))>;
1617 def : ARMPat<(add GPR:$LHS, so_imm2part:$RHS),
1618 (ADDri (ADDri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1619 (so_imm2part_2 imm:$RHS))>;
1620 def : ARMPat<(sub GPR:$LHS, so_imm2part:$RHS),
1621 (SUBri (SUBri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1622 (so_imm2part_2 imm:$RHS))>;
1624 // 32-bit immediate using movw + movt.
1625 // This is a single pseudo instruction, the benefit is that it can be remat'd
1626 // as a single unit instead of having to handle reg inputs.
1627 // FIXME: Remove this when we can do generalized remat.
1628 let isReMaterializable = 1 in
1629 def MOVi32imm : AI1x2<(outs GPR:$dst), (ins i32imm:$src), Pseudo, IIC_iMOVi,
1630 "movw", "\t$dst, ${src:lo16}\n\tmovt${p} $dst, ${src:hi16}",
1631 [(set GPR:$dst, (i32 imm:$src))]>,
1632 Requires<[IsARM, HasV6T2]>;
1634 // TODO: add,sub,and, 3-instr forms?
1638 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
1639 Requires<[IsARM, IsNotDarwin]>;
1640 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
1641 Requires<[IsARM, IsDarwin]>;
1643 // zextload i1 -> zextload i8
1644 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1646 // extload -> zextload
1647 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1648 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1649 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
1651 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
1652 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
1655 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1656 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1657 (SMULBB GPR:$a, GPR:$b)>;
1658 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
1659 (SMULBB GPR:$a, GPR:$b)>;
1660 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1661 (sra GPR:$b, (i32 16))),
1662 (SMULBT GPR:$a, GPR:$b)>;
1663 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
1664 (SMULBT GPR:$a, GPR:$b)>;
1665 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
1666 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1667 (SMULTB GPR:$a, GPR:$b)>;
1668 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
1669 (SMULTB GPR:$a, GPR:$b)>;
1670 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1672 (SMULWB GPR:$a, GPR:$b)>;
1673 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
1674 (SMULWB GPR:$a, GPR:$b)>;
1676 def : ARMV5TEPat<(add GPR:$acc,
1677 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1678 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1679 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1680 def : ARMV5TEPat<(add GPR:$acc,
1681 (mul sext_16_node:$a, sext_16_node:$b)),
1682 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1683 def : ARMV5TEPat<(add GPR:$acc,
1684 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1685 (sra GPR:$b, (i32 16)))),
1686 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1687 def : ARMV5TEPat<(add GPR:$acc,
1688 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
1689 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1690 def : ARMV5TEPat<(add GPR:$acc,
1691 (mul (sra GPR:$a, (i32 16)),
1692 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1693 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1694 def : ARMV5TEPat<(add GPR:$acc,
1695 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
1696 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1697 def : ARMV5TEPat<(add GPR:$acc,
1698 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1700 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1701 def : ARMV5TEPat<(add GPR:$acc,
1702 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
1703 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1705 //===----------------------------------------------------------------------===//
1709 include "ARMInstrThumb.td"
1711 //===----------------------------------------------------------------------===//
1715 include "ARMInstrThumb2.td"
1717 //===----------------------------------------------------------------------===//
1718 // Floating Point Support
1721 include "ARMInstrVFP.td"
1723 //===----------------------------------------------------------------------===//
1724 // Advanced SIMD (NEON) Support
1727 include "ARMInstrNEON.td"