1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisInt<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
68 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
70 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
71 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
75 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
76 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
77 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
79 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
80 [SDNPHasChain, SDNPOutGlue]>;
81 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
82 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
84 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
85 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
87 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
88 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
90 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
91 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
94 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
95 [SDNPHasChain, SDNPOptInGlue]>;
97 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
100 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
101 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
103 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
105 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
108 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
111 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
114 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
115 [SDNPOutGlue, SDNPCommutative]>;
117 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
119 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
120 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
121 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
123 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
124 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
125 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
126 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
127 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
128 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
129 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
132 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
134 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
136 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
137 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
139 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
141 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
142 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
145 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
147 //===----------------------------------------------------------------------===//
148 // ARM Instruction Predicate Definitions.
150 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
151 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
152 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
153 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
154 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
155 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
156 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
157 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
158 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
159 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
160 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
161 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
162 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
163 def HasFP16 : Predicate<"Subtarget->hasFP16()">, AssemblerPredicate;
164 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
165 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
167 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
169 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
171 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
172 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
173 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
174 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
175 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
176 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
177 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
178 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
180 // FIXME: Eventually this will be just "hasV6T2Ops".
181 def UseMovt : Predicate<"Subtarget->useMovt()">;
182 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
183 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
185 //===----------------------------------------------------------------------===//
186 // ARM Flag Definitions.
188 class RegConstraint<string C> {
189 string Constraints = C;
192 //===----------------------------------------------------------------------===//
193 // ARM specific transformation functions and pattern fragments.
196 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
197 // so_imm_neg def below.
198 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
199 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
202 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
203 // so_imm_not def below.
204 def so_imm_not_XFORM : SDNodeXForm<imm, [{
205 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
208 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
209 def imm1_15 : ImmLeaf<i32, [{
210 return (int32_t)Imm >= 1 && (int32_t)Imm < 16;
213 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
214 def imm16_31 : ImmLeaf<i32, [{
215 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
220 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
221 }], so_imm_neg_XFORM>;
225 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
226 }], so_imm_not_XFORM>;
228 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
229 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
230 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
233 /// Split a 32-bit immediate into two 16 bit parts.
234 def hi16 : SDNodeXForm<imm, [{
235 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
238 def lo16AllZero : PatLeaf<(i32 imm), [{
239 // Returns true if all low 16-bits are 0.
240 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
243 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
245 def imm0_65535 : ImmLeaf<i32, [{
246 return Imm >= 0 && Imm < 65536;
249 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
250 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
252 /// adde and sube predicates - True based on whether the carry flag output
253 /// will be needed or not.
254 def adde_dead_carry :
255 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
256 [{return !N->hasAnyUseOfValue(1);}]>;
257 def sube_dead_carry :
258 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
259 [{return !N->hasAnyUseOfValue(1);}]>;
260 def adde_live_carry :
261 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
262 [{return N->hasAnyUseOfValue(1);}]>;
263 def sube_live_carry :
264 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
265 [{return N->hasAnyUseOfValue(1);}]>;
267 // An 'and' node with a single use.
268 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
269 return N->hasOneUse();
272 // An 'xor' node with a single use.
273 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
274 return N->hasOneUse();
277 // An 'fmul' node with a single use.
278 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
279 return N->hasOneUse();
282 // An 'fadd' node which checks for single non-hazardous use.
283 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
284 return hasNoVMLxHazardUse(N);
287 // An 'fsub' node which checks for single non-hazardous use.
288 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
289 return hasNoVMLxHazardUse(N);
292 //===----------------------------------------------------------------------===//
293 // Operand Definitions.
297 // FIXME: rename brtarget to t2_brtarget
298 def brtarget : Operand<OtherVT> {
299 let EncoderMethod = "getBranchTargetOpValue";
302 // FIXME: get rid of this one?
303 def uncondbrtarget : Operand<OtherVT> {
304 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
307 // Branch target for ARM. Handles conditional/unconditional
308 def br_target : Operand<OtherVT> {
309 let EncoderMethod = "getARMBranchTargetOpValue";
313 // FIXME: rename bltarget to t2_bl_target?
314 def bltarget : Operand<i32> {
315 // Encoded the same as branch targets.
316 let EncoderMethod = "getBranchTargetOpValue";
319 // Call target for ARM. Handles conditional/unconditional
320 // FIXME: rename bl_target to t2_bltarget?
321 def bl_target : Operand<i32> {
322 // Encoded the same as branch targets.
323 let EncoderMethod = "getARMBranchTargetOpValue";
327 // A list of registers separated by comma. Used by load/store multiple.
328 def RegListAsmOperand : AsmOperandClass {
329 let Name = "RegList";
330 let SuperClasses = [];
333 def DPRRegListAsmOperand : AsmOperandClass {
334 let Name = "DPRRegList";
335 let SuperClasses = [];
338 def SPRRegListAsmOperand : AsmOperandClass {
339 let Name = "SPRRegList";
340 let SuperClasses = [];
343 def reglist : Operand<i32> {
344 let EncoderMethod = "getRegisterListOpValue";
345 let ParserMatchClass = RegListAsmOperand;
346 let PrintMethod = "printRegisterList";
349 def dpr_reglist : Operand<i32> {
350 let EncoderMethod = "getRegisterListOpValue";
351 let ParserMatchClass = DPRRegListAsmOperand;
352 let PrintMethod = "printRegisterList";
355 def spr_reglist : Operand<i32> {
356 let EncoderMethod = "getRegisterListOpValue";
357 let ParserMatchClass = SPRRegListAsmOperand;
358 let PrintMethod = "printRegisterList";
361 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
362 def cpinst_operand : Operand<i32> {
363 let PrintMethod = "printCPInstOperand";
367 def pclabel : Operand<i32> {
368 let PrintMethod = "printPCLabel";
371 // ADR instruction labels.
372 def adrlabel : Operand<i32> {
373 let EncoderMethod = "getAdrLabelOpValue";
376 def neon_vcvt_imm32 : Operand<i32> {
377 let EncoderMethod = "getNEONVcvtImm32OpValue";
380 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
381 def rot_imm : Operand<i32>, ImmLeaf<i32, [{
382 int32_t v = (int32_t)Imm;
383 return v == 8 || v == 16 || v == 24; }]> {
384 let EncoderMethod = "getRotImmOpValue";
387 def ShifterAsmOperand : AsmOperandClass {
388 let Name = "Shifter";
389 let SuperClasses = [];
392 // shift_imm: An integer that encodes a shift amount and the type of shift
393 // (currently either asr or lsl) using the same encoding used for the
394 // immediates in so_reg operands.
395 def shift_imm : Operand<i32> {
396 let PrintMethod = "printShiftImmOperand";
397 let ParserMatchClass = ShifterAsmOperand;
400 // shifter_operand operands: so_reg and so_imm.
401 def so_reg : Operand<i32>, // reg reg imm
402 ComplexPattern<i32, 3, "SelectShifterOperandReg",
403 [shl,srl,sra,rotr]> {
404 let EncoderMethod = "getSORegOpValue";
405 let PrintMethod = "printSORegOperand";
406 let MIOperandInfo = (ops GPR, GPR, shift_imm);
408 def shift_so_reg : Operand<i32>, // reg reg imm
409 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
410 [shl,srl,sra,rotr]> {
411 let EncoderMethod = "getSORegOpValue";
412 let PrintMethod = "printSORegOperand";
413 let MIOperandInfo = (ops GPR, GPR, shift_imm);
416 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
417 // 8-bit immediate rotated by an arbitrary number of bits.
418 def so_imm : Operand<i32>, ImmLeaf<i32, [{
419 return ARM_AM::getSOImmVal(Imm) != -1;
421 let EncoderMethod = "getSOImmOpValue";
422 let PrintMethod = "printSOImmOperand";
425 // Break so_imm's up into two pieces. This handles immediates with up to 16
426 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
427 // get the first/second pieces.
428 def so_imm2part : PatLeaf<(imm), [{
429 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
432 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
434 def arm_i32imm : PatLeaf<(imm), [{
435 if (Subtarget->hasV6T2Ops())
437 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
440 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
441 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
442 return Imm >= 0 && Imm < 32;
445 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
446 def imm0_31_m1 : Operand<i32>, ImmLeaf<i32, [{
447 return Imm >= 0 && Imm < 32;
449 let EncoderMethod = "getImmMinusOneOpValue";
452 // i32imm_hilo16 - For movt/movw - sets the MC Encoder method.
453 // The imm is split into imm{15-12}, imm{11-0}
455 def i32imm_hilo16 : Operand<i32> {
456 let EncoderMethod = "getHiLo16ImmOpValue";
459 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
461 def bf_inv_mask_imm : Operand<i32>,
463 return ARM::isBitFieldInvertedMask(N->getZExtValue());
465 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
466 let PrintMethod = "printBitfieldInvMaskImmOperand";
469 /// lsb_pos_imm - position of the lsb bit, used by BFI4p and t2BFI4p
470 def lsb_pos_imm : Operand<i32>, ImmLeaf<i32, [{
471 return isInt<5>(Imm);
474 /// width_imm - number of bits to be copied, used by BFI4p and t2BFI4p
475 def width_imm : Operand<i32>, ImmLeaf<i32, [{
476 return Imm > 0 && Imm <= 32;
478 let EncoderMethod = "getMsbOpValue";
481 def ssat_imm : Operand<i32>, ImmLeaf<i32, [{
482 return Imm > 0 && Imm <= 32;
484 let EncoderMethod = "getSsatBitPosValue";
487 // Define ARM specific addressing modes.
489 def MemMode2AsmOperand : AsmOperandClass {
490 let Name = "MemMode2";
491 let SuperClasses = [];
492 let ParserMethod = "tryParseMemMode2Operand";
495 def MemMode3AsmOperand : AsmOperandClass {
496 let Name = "MemMode3";
497 let SuperClasses = [];
498 let ParserMethod = "tryParseMemMode3Operand";
501 // addrmode_imm12 := reg +/- imm12
503 def addrmode_imm12 : Operand<i32>,
504 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
505 // 12-bit immediate operand. Note that instructions using this encode
506 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
507 // immediate values are as normal.
509 let EncoderMethod = "getAddrModeImm12OpValue";
510 let PrintMethod = "printAddrModeImm12Operand";
511 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
513 // ldst_so_reg := reg +/- reg shop imm
515 def ldst_so_reg : Operand<i32>,
516 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
517 let EncoderMethod = "getLdStSORegOpValue";
518 // FIXME: Simplify the printer
519 let PrintMethod = "printAddrMode2Operand";
520 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
523 // addrmode2 := reg +/- imm12
524 // := reg +/- reg shop imm
526 def addrmode2 : Operand<i32>,
527 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
528 let EncoderMethod = "getAddrMode2OpValue";
529 let PrintMethod = "printAddrMode2Operand";
530 let ParserMatchClass = MemMode2AsmOperand;
531 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
534 def am2offset : Operand<i32>,
535 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
536 [], [SDNPWantRoot]> {
537 let EncoderMethod = "getAddrMode2OffsetOpValue";
538 let PrintMethod = "printAddrMode2OffsetOperand";
539 let MIOperandInfo = (ops GPR, i32imm);
542 // addrmode3 := reg +/- reg
543 // addrmode3 := reg +/- imm8
545 def addrmode3 : Operand<i32>,
546 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
547 let EncoderMethod = "getAddrMode3OpValue";
548 let PrintMethod = "printAddrMode3Operand";
549 let ParserMatchClass = MemMode3AsmOperand;
550 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
553 def am3offset : Operand<i32>,
554 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
555 [], [SDNPWantRoot]> {
556 let EncoderMethod = "getAddrMode3OffsetOpValue";
557 let PrintMethod = "printAddrMode3OffsetOperand";
558 let MIOperandInfo = (ops GPR, i32imm);
561 // ldstm_mode := {ia, ib, da, db}
563 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
564 let EncoderMethod = "getLdStmModeOpValue";
565 let PrintMethod = "printLdStmModeOperand";
568 def MemMode5AsmOperand : AsmOperandClass {
569 let Name = "MemMode5";
570 let SuperClasses = [];
573 // addrmode5 := reg +/- imm8*4
575 def addrmode5 : Operand<i32>,
576 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
577 let PrintMethod = "printAddrMode5Operand";
578 let MIOperandInfo = (ops GPR:$base, i32imm);
579 let ParserMatchClass = MemMode5AsmOperand;
580 let EncoderMethod = "getAddrMode5OpValue";
583 // addrmode6 := reg with optional alignment
585 def addrmode6 : Operand<i32>,
586 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
587 let PrintMethod = "printAddrMode6Operand";
588 let MIOperandInfo = (ops GPR:$addr, i32imm);
589 let EncoderMethod = "getAddrMode6AddressOpValue";
592 def am6offset : Operand<i32>,
593 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
594 [], [SDNPWantRoot]> {
595 let PrintMethod = "printAddrMode6OffsetOperand";
596 let MIOperandInfo = (ops GPR);
597 let EncoderMethod = "getAddrMode6OffsetOpValue";
600 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
601 // (single element from one lane) for size 32.
602 def addrmode6oneL32 : Operand<i32>,
603 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
604 let PrintMethod = "printAddrMode6Operand";
605 let MIOperandInfo = (ops GPR:$addr, i32imm);
606 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
609 // Special version of addrmode6 to handle alignment encoding for VLD-dup
610 // instructions, specifically VLD4-dup.
611 def addrmode6dup : Operand<i32>,
612 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
613 let PrintMethod = "printAddrMode6Operand";
614 let MIOperandInfo = (ops GPR:$addr, i32imm);
615 let EncoderMethod = "getAddrMode6DupAddressOpValue";
618 // addrmodepc := pc + reg
620 def addrmodepc : Operand<i32>,
621 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
622 let PrintMethod = "printAddrModePCOperand";
623 let MIOperandInfo = (ops GPR, i32imm);
626 def MemMode7AsmOperand : AsmOperandClass {
627 let Name = "MemMode7";
628 let SuperClasses = [];
632 // Used by load/store exclusive instructions. Useful to enable right assembly
633 // parsing and printing. Not used for any codegen matching.
635 def addrmode7 : Operand<i32> {
636 let PrintMethod = "printAddrMode7Operand";
637 let MIOperandInfo = (ops GPR);
638 let ParserMatchClass = MemMode7AsmOperand;
641 def nohash_imm : Operand<i32> {
642 let PrintMethod = "printNoHashImmediate";
645 def CoprocNumAsmOperand : AsmOperandClass {
646 let Name = "CoprocNum";
647 let SuperClasses = [];
648 let ParserMethod = "tryParseCoprocNumOperand";
651 def CoprocRegAsmOperand : AsmOperandClass {
652 let Name = "CoprocReg";
653 let SuperClasses = [];
654 let ParserMethod = "tryParseCoprocRegOperand";
657 def p_imm : Operand<i32> {
658 let PrintMethod = "printPImmediate";
659 let ParserMatchClass = CoprocNumAsmOperand;
662 def c_imm : Operand<i32> {
663 let PrintMethod = "printCImmediate";
664 let ParserMatchClass = CoprocRegAsmOperand;
667 //===----------------------------------------------------------------------===//
669 include "ARMInstrFormats.td"
671 //===----------------------------------------------------------------------===//
672 // Multiclass helpers...
675 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
676 /// binop that produces a value.
677 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
678 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
679 PatFrag opnode, bit Commutable = 0> {
680 // The register-immediate version is re-materializable. This is useful
681 // in particular for taking the address of a local.
682 let isReMaterializable = 1 in {
683 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
684 iii, opc, "\t$Rd, $Rn, $imm",
685 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
690 let Inst{19-16} = Rn;
691 let Inst{15-12} = Rd;
692 let Inst{11-0} = imm;
695 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
696 iir, opc, "\t$Rd, $Rn, $Rm",
697 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
702 let isCommutable = Commutable;
703 let Inst{19-16} = Rn;
704 let Inst{15-12} = Rd;
705 let Inst{11-4} = 0b00000000;
708 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
709 iis, opc, "\t$Rd, $Rn, $shift",
710 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
715 let Inst{19-16} = Rn;
716 let Inst{15-12} = Rd;
717 let Inst{11-0} = shift;
721 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
722 /// instruction modifies the CPSR register.
723 let isCodeGenOnly = 1, Defs = [CPSR] in {
724 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
725 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
726 PatFrag opnode, bit Commutable = 0> {
727 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
728 iii, opc, "\t$Rd, $Rn, $imm",
729 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
735 let Inst{19-16} = Rn;
736 let Inst{15-12} = Rd;
737 let Inst{11-0} = imm;
739 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
740 iir, opc, "\t$Rd, $Rn, $Rm",
741 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
745 let isCommutable = Commutable;
748 let Inst{19-16} = Rn;
749 let Inst{15-12} = Rd;
750 let Inst{11-4} = 0b00000000;
753 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
754 iis, opc, "\t$Rd, $Rn, $shift",
755 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
761 let Inst{19-16} = Rn;
762 let Inst{15-12} = Rd;
763 let Inst{11-0} = shift;
768 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
769 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
770 /// a explicit result, only implicitly set CPSR.
771 let isCompare = 1, Defs = [CPSR] in {
772 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
773 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
774 PatFrag opnode, bit Commutable = 0> {
775 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
777 [(opnode GPR:$Rn, so_imm:$imm)]> {
782 let Inst{19-16} = Rn;
783 let Inst{15-12} = 0b0000;
784 let Inst{11-0} = imm;
786 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
788 [(opnode GPR:$Rn, GPR:$Rm)]> {
791 let isCommutable = Commutable;
794 let Inst{19-16} = Rn;
795 let Inst{15-12} = 0b0000;
796 let Inst{11-4} = 0b00000000;
799 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
800 opc, "\t$Rn, $shift",
801 [(opnode GPR:$Rn, so_reg:$shift)]> {
806 let Inst{19-16} = Rn;
807 let Inst{15-12} = 0b0000;
808 let Inst{11-0} = shift;
813 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
814 /// register and one whose operand is a register rotated by 8/16/24.
815 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
816 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
817 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
818 IIC_iEXTr, opc, "\t$Rd, $Rm",
819 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
820 Requires<[IsARM, HasV6]> {
823 let Inst{19-16} = 0b1111;
824 let Inst{15-12} = Rd;
825 let Inst{11-10} = 0b00;
828 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
829 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
830 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
831 Requires<[IsARM, HasV6]> {
835 let Inst{19-16} = 0b1111;
836 let Inst{15-12} = Rd;
837 let Inst{11-10} = rot;
842 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
843 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
844 IIC_iEXTr, opc, "\t$Rd, $Rm",
845 [/* For disassembly only; pattern left blank */]>,
846 Requires<[IsARM, HasV6]> {
847 let Inst{19-16} = 0b1111;
848 let Inst{11-10} = 0b00;
850 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
851 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
852 [/* For disassembly only; pattern left blank */]>,
853 Requires<[IsARM, HasV6]> {
855 let Inst{19-16} = 0b1111;
856 let Inst{11-10} = rot;
860 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
861 /// register and one whose operand is a register rotated by 8/16/24.
862 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
863 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
864 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
865 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
866 Requires<[IsARM, HasV6]> {
870 let Inst{19-16} = Rn;
871 let Inst{15-12} = Rd;
872 let Inst{11-10} = 0b00;
873 let Inst{9-4} = 0b000111;
876 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
878 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
879 [(set GPR:$Rd, (opnode GPR:$Rn,
880 (rotr GPR:$Rm, rot_imm:$rot)))]>,
881 Requires<[IsARM, HasV6]> {
886 let Inst{19-16} = Rn;
887 let Inst{15-12} = Rd;
888 let Inst{11-10} = rot;
889 let Inst{9-4} = 0b000111;
894 // For disassembly only.
895 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
896 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
897 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
898 [/* For disassembly only; pattern left blank */]>,
899 Requires<[IsARM, HasV6]> {
900 let Inst{11-10} = 0b00;
902 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
904 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
905 [/* For disassembly only; pattern left blank */]>,
906 Requires<[IsARM, HasV6]> {
909 let Inst{19-16} = Rn;
910 let Inst{11-10} = rot;
914 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
915 let Uses = [CPSR] in {
916 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
917 bit Commutable = 0> {
918 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
919 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
920 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
926 let Inst{15-12} = Rd;
927 let Inst{19-16} = Rn;
928 let Inst{11-0} = imm;
930 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
931 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
932 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
937 let Inst{11-4} = 0b00000000;
939 let isCommutable = Commutable;
941 let Inst{15-12} = Rd;
942 let Inst{19-16} = Rn;
944 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
945 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
946 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
952 let Inst{11-0} = shift;
953 let Inst{15-12} = Rd;
954 let Inst{19-16} = Rn;
959 // Carry setting variants
960 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
961 let usesCustomInserter = 1 in {
962 multiclass AI1_adde_sube_s_irs<PatFrag opnode, bit Commutable = 0> {
963 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
964 Size4Bytes, IIC_iALUi,
965 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>;
966 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
967 Size4Bytes, IIC_iALUr,
968 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
969 let isCommutable = Commutable;
971 def rs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
972 Size4Bytes, IIC_iALUsr,
973 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>;
977 let canFoldAsLoad = 1, isReMaterializable = 1 in {
978 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
979 InstrItinClass iir, PatFrag opnode> {
980 // Note: We use the complex addrmode_imm12 rather than just an input
981 // GPR and a constrained immediate so that we can use this to match
982 // frame index references and avoid matching constant pool references.
983 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
984 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
985 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
988 let Inst{23} = addr{12}; // U (add = ('U' == 1))
989 let Inst{19-16} = addr{16-13}; // Rn
990 let Inst{15-12} = Rt;
991 let Inst{11-0} = addr{11-0}; // imm12
993 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
994 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
995 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
998 let shift{4} = 0; // Inst{4} = 0
999 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1000 let Inst{19-16} = shift{16-13}; // Rn
1001 let Inst{15-12} = Rt;
1002 let Inst{11-0} = shift{11-0};
1007 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1008 InstrItinClass iir, PatFrag opnode> {
1009 // Note: We use the complex addrmode_imm12 rather than just an input
1010 // GPR and a constrained immediate so that we can use this to match
1011 // frame index references and avoid matching constant pool references.
1012 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1013 (ins GPR:$Rt, addrmode_imm12:$addr),
1014 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1015 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1018 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1019 let Inst{19-16} = addr{16-13}; // Rn
1020 let Inst{15-12} = Rt;
1021 let Inst{11-0} = addr{11-0}; // imm12
1023 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1024 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1025 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1028 let shift{4} = 0; // Inst{4} = 0
1029 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1030 let Inst{19-16} = shift{16-13}; // Rn
1031 let Inst{15-12} = Rt;
1032 let Inst{11-0} = shift{11-0};
1035 //===----------------------------------------------------------------------===//
1037 //===----------------------------------------------------------------------===//
1039 //===----------------------------------------------------------------------===//
1040 // Miscellaneous Instructions.
1043 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1044 /// the function. The first operand is the ID# for this instruction, the second
1045 /// is the index into the MachineConstantPool that this is, the third is the
1046 /// size in bytes of this constant pool entry.
1047 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1048 def CONSTPOOL_ENTRY :
1049 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1050 i32imm:$size), NoItinerary, []>;
1052 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1053 // from removing one half of the matched pairs. That breaks PEI, which assumes
1054 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1055 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1056 def ADJCALLSTACKUP :
1057 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1058 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1060 def ADJCALLSTACKDOWN :
1061 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1062 [(ARMcallseq_start timm:$amt)]>;
1065 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
1066 [/* For disassembly only; pattern left blank */]>,
1067 Requires<[IsARM, HasV6T2]> {
1068 let Inst{27-16} = 0b001100100000;
1069 let Inst{15-8} = 0b11110000;
1070 let Inst{7-0} = 0b00000000;
1073 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
1074 [/* For disassembly only; pattern left blank */]>,
1075 Requires<[IsARM, HasV6T2]> {
1076 let Inst{27-16} = 0b001100100000;
1077 let Inst{15-8} = 0b11110000;
1078 let Inst{7-0} = 0b00000001;
1081 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
1082 [/* For disassembly only; pattern left blank */]>,
1083 Requires<[IsARM, HasV6T2]> {
1084 let Inst{27-16} = 0b001100100000;
1085 let Inst{15-8} = 0b11110000;
1086 let Inst{7-0} = 0b00000010;
1089 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
1090 [/* For disassembly only; pattern left blank */]>,
1091 Requires<[IsARM, HasV6T2]> {
1092 let Inst{27-16} = 0b001100100000;
1093 let Inst{15-8} = 0b11110000;
1094 let Inst{7-0} = 0b00000011;
1097 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
1099 [/* For disassembly only; pattern left blank */]>,
1100 Requires<[IsARM, HasV6]> {
1105 let Inst{15-12} = Rd;
1106 let Inst{19-16} = Rn;
1107 let Inst{27-20} = 0b01101000;
1108 let Inst{7-4} = 0b1011;
1109 let Inst{11-8} = 0b1111;
1112 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1113 [/* For disassembly only; pattern left blank */]>,
1114 Requires<[IsARM, HasV6T2]> {
1115 let Inst{27-16} = 0b001100100000;
1116 let Inst{15-8} = 0b11110000;
1117 let Inst{7-0} = 0b00000100;
1120 // The i32imm operand $val can be used by a debugger to store more information
1121 // about the breakpoint.
1122 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
1123 [/* For disassembly only; pattern left blank */]>,
1126 let Inst{3-0} = val{3-0};
1127 let Inst{19-8} = val{15-4};
1128 let Inst{27-20} = 0b00010010;
1129 let Inst{7-4} = 0b0111;
1132 // Change Processor State is a system instruction -- for disassembly and
1134 // FIXME: Since the asm parser has currently no clean way to handle optional
1135 // operands, create 3 versions of the same instruction. Once there's a clean
1136 // framework to represent optional operands, change this behavior.
1137 class CPS<dag iops, string asm_ops>
1138 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1139 [/* For disassembly only; pattern left blank */]>, Requires<[IsARM]> {
1145 let Inst{31-28} = 0b1111;
1146 let Inst{27-20} = 0b00010000;
1147 let Inst{19-18} = imod;
1148 let Inst{17} = M; // Enabled if mode is set;
1150 let Inst{8-6} = iflags;
1152 let Inst{4-0} = mode;
1156 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
1157 "$imod\t$iflags, $mode">;
1158 let mode = 0, M = 0 in
1159 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1161 let imod = 0, iflags = 0, M = 1 in
1162 def CPS1p : CPS<(ins i32imm:$mode), "\t$mode">;
1164 // Preload signals the memory system of possible future data/instruction access.
1165 // These are for disassembly only.
1166 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1168 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1169 !strconcat(opc, "\t$addr"),
1170 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1173 let Inst{31-26} = 0b111101;
1174 let Inst{25} = 0; // 0 for immediate form
1175 let Inst{24} = data;
1176 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1177 let Inst{22} = read;
1178 let Inst{21-20} = 0b01;
1179 let Inst{19-16} = addr{16-13}; // Rn
1180 let Inst{15-12} = 0b1111;
1181 let Inst{11-0} = addr{11-0}; // imm12
1184 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1185 !strconcat(opc, "\t$shift"),
1186 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1188 let Inst{31-26} = 0b111101;
1189 let Inst{25} = 1; // 1 for register form
1190 let Inst{24} = data;
1191 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1192 let Inst{22} = read;
1193 let Inst{21-20} = 0b01;
1194 let Inst{19-16} = shift{16-13}; // Rn
1195 let Inst{15-12} = 0b1111;
1196 let Inst{11-0} = shift{11-0};
1200 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1201 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1202 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1204 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1206 [/* For disassembly only; pattern left blank */]>,
1209 let Inst{31-10} = 0b1111000100000001000000;
1214 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1215 [/* For disassembly only; pattern left blank */]>,
1216 Requires<[IsARM, HasV7]> {
1218 let Inst{27-4} = 0b001100100000111100001111;
1219 let Inst{3-0} = opt;
1222 // A5.4 Permanently UNDEFINED instructions.
1223 let isBarrier = 1, isTerminator = 1 in
1224 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1227 let Inst = 0xe7ffdefe;
1230 // Address computation and loads and stores in PIC mode.
1231 let isNotDuplicable = 1 in {
1232 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1233 Size4Bytes, IIC_iALUr,
1234 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1236 let AddedComplexity = 10 in {
1237 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1238 Size4Bytes, IIC_iLoad_r,
1239 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1241 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1242 Size4Bytes, IIC_iLoad_bh_r,
1243 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1245 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1246 Size4Bytes, IIC_iLoad_bh_r,
1247 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1249 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1250 Size4Bytes, IIC_iLoad_bh_r,
1251 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1253 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1254 Size4Bytes, IIC_iLoad_bh_r,
1255 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1257 let AddedComplexity = 10 in {
1258 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1259 Size4Bytes, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1261 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1262 Size4Bytes, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1263 addrmodepc:$addr)]>;
1265 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1266 Size4Bytes, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1268 } // isNotDuplicable = 1
1271 // LEApcrel - Load a pc-relative address into a register without offending the
1273 let neverHasSideEffects = 1, isReMaterializable = 1 in
1274 // The 'adr' mnemonic encodes differently if the label is before or after
1275 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1276 // know until then which form of the instruction will be used.
1277 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1278 MiscFrm, IIC_iALUi, "adr", "\t$Rd, #$label", []> {
1281 let Inst{27-25} = 0b001;
1283 let Inst{19-16} = 0b1111;
1284 let Inst{15-12} = Rd;
1285 let Inst{11-0} = label;
1287 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1288 Size4Bytes, IIC_iALUi, []>;
1290 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1291 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1292 Size4Bytes, IIC_iALUi, []>;
1294 //===----------------------------------------------------------------------===//
1295 // Control Flow Instructions.
1298 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1300 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1301 "bx", "\tlr", [(ARMretflag)]>,
1302 Requires<[IsARM, HasV4T]> {
1303 let Inst{27-0} = 0b0001001011111111111100011110;
1307 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1308 "mov", "\tpc, lr", [(ARMretflag)]>,
1309 Requires<[IsARM, NoV4T]> {
1310 let Inst{27-0} = 0b0001101000001111000000001110;
1314 // Indirect branches
1315 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1317 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1318 [(brind GPR:$dst)]>,
1319 Requires<[IsARM, HasV4T]> {
1321 let Inst{31-4} = 0b1110000100101111111111110001;
1322 let Inst{3-0} = dst;
1325 // For disassembly only.
1326 def BX_pred : AXI<(outs), (ins GPR:$dst, pred:$p), BrMiscFrm, IIC_Br,
1327 "bx$p\t$dst", [/* pattern left blank */]>,
1328 Requires<[IsARM, HasV4T]> {
1330 let Inst{27-4} = 0b000100101111111111110001;
1331 let Inst{3-0} = dst;
1335 // FIXME: We would really like to define this as a vanilla ARMPat like:
1336 // ARMPat<(brind GPR:$dst), (MOVr PC, GPR:$dst)>
1337 // With that, however, we can't set isBranch, isTerminator, etc..
1338 def MOVPCRX : ARMPseudoInst<(outs), (ins GPR:$dst),
1339 Size4Bytes, IIC_Br, [(brind GPR:$dst)]>,
1340 Requires<[IsARM, NoV4T]>;
1343 // All calls clobber the non-callee saved registers. SP is marked as
1344 // a use to prevent stack-pointer assignments that appear immediately
1345 // before calls from potentially appearing dead.
1347 // On non-Darwin platforms R9 is callee-saved.
1348 // FIXME: Do we really need a non-predicated version? If so, it should
1349 // at least be a pseudo instruction expanding to the predicated version
1350 // at MC lowering time.
1351 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1353 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1354 IIC_Br, "bl\t$func",
1355 [(ARMcall tglobaladdr:$func)]>,
1356 Requires<[IsARM, IsNotDarwin]> {
1357 let Inst{31-28} = 0b1110;
1359 let Inst{23-0} = func;
1362 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1363 IIC_Br, "bl", "\t$func",
1364 [(ARMcall_pred tglobaladdr:$func)]>,
1365 Requires<[IsARM, IsNotDarwin]> {
1367 let Inst{23-0} = func;
1371 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1372 IIC_Br, "blx\t$func",
1373 [(ARMcall GPR:$func)]>,
1374 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1376 let Inst{31-4} = 0b1110000100101111111111110011;
1377 let Inst{3-0} = func;
1380 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1381 IIC_Br, "blx", "\t$func",
1382 [(ARMcall_pred GPR:$func)]>,
1383 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1385 let Inst{27-4} = 0b000100101111111111110011;
1386 let Inst{3-0} = func;
1390 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1391 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1392 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1393 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1396 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1397 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1398 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1402 // On Darwin R9 is call-clobbered.
1403 // R7 is marked as a use to prevent frame-pointer assignments from being
1404 // moved above / below calls.
1405 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1406 Uses = [R7, SP] in {
1407 def BLr9 : ARMPseudoInst<(outs), (ins bltarget:$func, variable_ops),
1409 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]>;
1411 def BLr9_pred : ARMPseudoInst<(outs),
1412 (ins bltarget:$func, pred:$p, variable_ops),
1414 [(ARMcall_pred tglobaladdr:$func)]>,
1415 Requires<[IsARM, IsDarwin]>;
1418 def BLXr9 : ARMPseudoInst<(outs), (ins GPR:$func, variable_ops),
1420 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]>;
1422 def BLXr9_pred: ARMPseudoInst<(outs), (ins GPR:$func, pred:$p, variable_ops),
1424 [(ARMcall_pred GPR:$func)]>,
1425 Requires<[IsARM, HasV5T, IsDarwin]>;
1428 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1429 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1430 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1431 Requires<[IsARM, HasV4T, IsDarwin]>;
1434 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1435 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1436 Requires<[IsARM, NoV4T, IsDarwin]>;
1441 // FIXME: The Thumb versions of these should live in ARMInstrThumb.td
1442 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1444 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
1446 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1447 IIC_Br, []>, Requires<[IsDarwin]>;
1449 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1450 IIC_Br, []>, Requires<[IsDarwin]>;
1452 def TAILJMPd : ARMPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1454 []>, Requires<[IsARM, IsDarwin]>;
1456 def tTAILJMPd: tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1458 []>, Requires<[IsThumb, IsDarwin]>;
1460 def TAILJMPr : ARMPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1462 []>, Requires<[IsARM, IsDarwin]>;
1464 def tTAILJMPr : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1466 []>, Requires<[IsThumb, IsDarwin]>;
1469 // Non-Darwin versions (the difference is R9).
1470 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
1472 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1473 IIC_Br, []>, Requires<[IsNotDarwin]>;
1475 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1476 IIC_Br, []>, Requires<[IsNotDarwin]>;
1478 def TAILJMPdND : ARMPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1480 []>, Requires<[IsARM, IsNotDarwin]>;
1482 def tTAILJMPdND : tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1484 []>, Requires<[IsThumb, IsNotDarwin]>;
1486 def TAILJMPrND : ARMPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1488 []>, Requires<[IsARM, IsNotDarwin]>;
1489 def tTAILJMPrND : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1491 []>, Requires<[IsThumb, IsNotDarwin]>;
1495 let isBranch = 1, isTerminator = 1 in {
1496 // B is "predicable" since it's just a Bcc with an 'always' condition.
1497 let isBarrier = 1 in {
1498 let isPredicable = 1 in
1499 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1500 // should be sufficient.
1501 def B : ARMPseudoInst<(outs), (ins brtarget:$target), Size4Bytes, IIC_Br,
1504 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1505 def BR_JTr : ARMPseudoInst<(outs),
1506 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1507 SizeSpecial, IIC_Br,
1508 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1509 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1510 // into i12 and rs suffixed versions.
1511 def BR_JTm : ARMPseudoInst<(outs),
1512 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1513 SizeSpecial, IIC_Br,
1514 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1516 def BR_JTadd : ARMPseudoInst<(outs),
1517 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1518 SizeSpecial, IIC_Br,
1519 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1521 } // isNotDuplicable = 1, isIndirectBranch = 1
1524 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1525 // a two-value operand where a dag node expects two operands. :(
1526 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1527 IIC_Br, "b", "\t$target",
1528 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1530 let Inst{23-0} = target;
1534 // BLX (immediate) -- for disassembly only
1535 def BLXi : AXI<(outs), (ins br_target:$target), BrMiscFrm, NoItinerary,
1536 "blx\t$target", [/* pattern left blank */]>,
1537 Requires<[IsARM, HasV5T]> {
1538 let Inst{31-25} = 0b1111101;
1540 let Inst{23-0} = target{24-1};
1541 let Inst{24} = target{0};
1544 // Branch and Exchange Jazelle -- for disassembly only
1545 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1546 [/* For disassembly only; pattern left blank */]> {
1547 let Inst{23-20} = 0b0010;
1548 //let Inst{19-8} = 0xfff;
1549 let Inst{7-4} = 0b0010;
1552 // Secure Monitor Call is a system instruction -- for disassembly only
1553 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1554 [/* For disassembly only; pattern left blank */]> {
1556 let Inst{23-4} = 0b01100000000000000111;
1557 let Inst{3-0} = opt;
1560 // Supervisor Call (Software Interrupt) -- for disassembly only
1561 let isCall = 1, Uses = [SP] in {
1562 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1563 [/* For disassembly only; pattern left blank */]> {
1565 let Inst{23-0} = svc;
1568 def : MnemonicAlias<"swi", "svc">;
1570 // Store Return State is a system instruction -- for disassembly only
1571 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1572 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1573 NoItinerary, "srs${amode}\tsp!, $mode",
1574 [/* For disassembly only; pattern left blank */]> {
1575 let Inst{31-28} = 0b1111;
1576 let Inst{22-20} = 0b110; // W = 1
1577 let Inst{19-8} = 0xd05;
1578 let Inst{7-5} = 0b000;
1581 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1582 NoItinerary, "srs${amode}\tsp, $mode",
1583 [/* For disassembly only; pattern left blank */]> {
1584 let Inst{31-28} = 0b1111;
1585 let Inst{22-20} = 0b100; // W = 0
1586 let Inst{19-8} = 0xd05;
1587 let Inst{7-5} = 0b000;
1590 // Return From Exception is a system instruction -- for disassembly only
1591 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1592 NoItinerary, "rfe${amode}\t$base!",
1593 [/* For disassembly only; pattern left blank */]> {
1594 let Inst{31-28} = 0b1111;
1595 let Inst{22-20} = 0b011; // W = 1
1596 let Inst{15-0} = 0x0a00;
1599 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1600 NoItinerary, "rfe${amode}\t$base",
1601 [/* For disassembly only; pattern left blank */]> {
1602 let Inst{31-28} = 0b1111;
1603 let Inst{22-20} = 0b001; // W = 0
1604 let Inst{15-0} = 0x0a00;
1606 } // isCodeGenOnly = 1
1608 //===----------------------------------------------------------------------===//
1609 // Load / store Instructions.
1615 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1616 UnOpFrag<(load node:$Src)>>;
1617 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1618 UnOpFrag<(zextloadi8 node:$Src)>>;
1619 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1620 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1621 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1622 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1624 // Special LDR for loads from non-pc-relative constpools.
1625 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1626 isReMaterializable = 1 in
1627 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1628 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
1632 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1633 let Inst{19-16} = 0b1111;
1634 let Inst{15-12} = Rt;
1635 let Inst{11-0} = addr{11-0}; // imm12
1638 // Loads with zero extension
1639 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1640 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
1641 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
1643 // Loads with sign extension
1644 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1645 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
1646 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
1648 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1649 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
1650 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
1652 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1654 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
1655 (ins addrmode3:$addr), LdMiscFrm,
1656 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
1657 []>, Requires<[IsARM, HasV5TE]>;
1661 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
1662 def _PRE : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1663 (ins addrmode2:$addr), IndexModePre, LdFrm, itin,
1664 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1666 // {13} 1 == Rm, 0 == imm12
1670 let Inst{25} = addr{13};
1671 let Inst{23} = addr{12};
1672 let Inst{19-16} = addr{17-14};
1673 let Inst{11-0} = addr{11-0};
1674 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1676 def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1677 (ins GPR:$Rn, am2offset:$offset),
1678 IndexModePost, LdFrm, itin,
1679 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1680 // {13} 1 == Rm, 0 == imm12
1685 let Inst{25} = offset{13};
1686 let Inst{23} = offset{12};
1687 let Inst{19-16} = Rn;
1688 let Inst{11-0} = offset{11-0};
1692 let mayLoad = 1, neverHasSideEffects = 1 in {
1693 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
1694 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
1697 multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
1698 def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1699 (ins addrmode3:$addr), IndexModePre,
1701 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1703 let Inst{23} = addr{8}; // U bit
1704 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1705 let Inst{19-16} = addr{12-9}; // Rn
1706 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1707 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1709 def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1710 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1712 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1715 let Inst{23} = offset{8}; // U bit
1716 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1717 let Inst{19-16} = Rn;
1718 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1719 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1723 let mayLoad = 1, neverHasSideEffects = 1 in {
1724 defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
1725 defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
1726 defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
1727 let hasExtraDefRegAllocReq = 1 in {
1728 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
1729 (ins addrmode3:$addr), IndexModePre,
1730 LdMiscFrm, IIC_iLoad_d_ru,
1731 "ldrd", "\t$Rt, $Rt2, $addr!",
1732 "$addr.base = $Rn_wb", []> {
1734 let Inst{23} = addr{8}; // U bit
1735 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1736 let Inst{19-16} = addr{12-9}; // Rn
1737 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1738 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1740 def LDRD_POST: AI3ldstidx<0b1101, 0, 1, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
1741 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1742 LdMiscFrm, IIC_iLoad_d_ru,
1743 "ldrd", "\t$Rt, $Rt2, [$Rn], $offset",
1744 "$Rn = $Rn_wb", []> {
1747 let Inst{23} = offset{8}; // U bit
1748 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1749 let Inst{19-16} = Rn;
1750 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1751 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1753 } // hasExtraDefRegAllocReq = 1
1754 } // mayLoad = 1, neverHasSideEffects = 1
1756 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1757 let mayLoad = 1, neverHasSideEffects = 1 in {
1758 def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$base_wb),
1759 (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_ru,
1760 "ldrt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1762 // {13} 1 == Rm, 0 == imm12
1766 let Inst{25} = addr{13};
1767 let Inst{23} = addr{12};
1768 let Inst{21} = 1; // overwrite
1769 let Inst{19-16} = addr{17-14};
1770 let Inst{11-0} = addr{11-0};
1771 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1773 def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1774 (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_bh_ru,
1775 "ldrbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1777 // {13} 1 == Rm, 0 == imm12
1781 let Inst{25} = addr{13};
1782 let Inst{23} = addr{12};
1783 let Inst{21} = 1; // overwrite
1784 let Inst{19-16} = addr{17-14};
1785 let Inst{11-0} = addr{11-0};
1786 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1788 def LDRSBT : AI3ldstidxT<0b1101, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1789 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1790 "ldrsbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1791 let Inst{21} = 1; // overwrite
1793 def LDRHT : AI3ldstidxT<0b1011, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1794 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1795 "ldrht", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1796 let Inst{21} = 1; // overwrite
1798 def LDRSHT : AI3ldstidxT<0b1111, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1799 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1800 "ldrsht", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1801 let Inst{21} = 1; // overwrite
1807 // Stores with truncate
1808 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
1809 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
1810 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
1813 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1814 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
1815 StMiscFrm, IIC_iStore_d_r,
1816 "strd", "\t$Rt, $src2, $addr", []>, Requires<[IsARM, HasV5TE]>;
1819 def STR_PRE : AI2stridx<0, 1, (outs GPR:$Rn_wb),
1820 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1821 IndexModePre, StFrm, IIC_iStore_ru,
1822 "str", "\t$Rt, [$Rn, $offset]!",
1823 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1825 (pre_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1827 def STR_POST : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1828 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1829 IndexModePost, StFrm, IIC_iStore_ru,
1830 "str", "\t$Rt, [$Rn], $offset",
1831 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1833 (post_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1835 def STRB_PRE : AI2stridx<1, 1, (outs GPR:$Rn_wb),
1836 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1837 IndexModePre, StFrm, IIC_iStore_bh_ru,
1838 "strb", "\t$Rt, [$Rn, $offset]!",
1839 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1840 [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
1841 GPR:$Rn, am2offset:$offset))]>;
1842 def STRB_POST: AI2stridx<1, 0, (outs GPR:$Rn_wb),
1843 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1844 IndexModePost, StFrm, IIC_iStore_bh_ru,
1845 "strb", "\t$Rt, [$Rn], $offset",
1846 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1847 [(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
1848 GPR:$Rn, am2offset:$offset))]>;
1850 def STRH_PRE : AI3stridx<0b1011, 0, 1, (outs GPR:$Rn_wb),
1851 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1852 IndexModePre, StMiscFrm, IIC_iStore_ru,
1853 "strh", "\t$Rt, [$Rn, $offset]!",
1854 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1856 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
1858 def STRH_POST: AI3stridx<0b1011, 0, 0, (outs GPR:$Rn_wb),
1859 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1860 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
1861 "strh", "\t$Rt, [$Rn], $offset",
1862 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1863 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
1864 GPR:$Rn, am3offset:$offset))]>;
1866 // For disassembly only
1867 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1868 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1869 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1870 StMiscFrm, IIC_iStore_d_ru,
1871 "strd", "\t$src1, $src2, [$base, $offset]!",
1872 "$base = $base_wb", []>;
1874 // For disassembly only
1875 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1876 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1877 StMiscFrm, IIC_iStore_d_ru,
1878 "strd", "\t$src1, $src2, [$base], $offset",
1879 "$base = $base_wb", []>;
1880 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1882 // STRT, STRBT, and STRHT are for disassembly only.
1884 def STRT : AI2stridxT<0, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
1885 IndexModePost, StFrm, IIC_iStore_ru,
1886 "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
1887 [/* For disassembly only; pattern left blank */]> {
1888 let Inst{21} = 1; // overwrite
1889 let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
1892 def STRBT : AI2stridxT<1, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
1893 IndexModePost, StFrm, IIC_iStore_bh_ru,
1894 "strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
1895 [/* For disassembly only; pattern left blank */]> {
1896 let Inst{21} = 1; // overwrite
1897 let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
1900 def STRHT: AI3sthpo<(outs GPR:$base_wb), (ins GPR:$Rt, addrmode3:$addr),
1901 StMiscFrm, IIC_iStore_bh_ru,
1902 "strht", "\t$Rt, $addr", "$addr.base = $base_wb",
1903 [/* For disassembly only; pattern left blank */]> {
1904 let Inst{21} = 1; // overwrite
1905 let AsmMatchConverter = "CvtStWriteBackRegAddrMode3";
1908 //===----------------------------------------------------------------------===//
1909 // Load / store multiple Instructions.
1912 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
1913 InstrItinClass itin, InstrItinClass itin_upd> {
1915 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1916 IndexModeNone, f, itin,
1917 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
1918 let Inst{24-23} = 0b01; // Increment After
1919 let Inst{21} = 0; // No writeback
1920 let Inst{20} = L_bit;
1923 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1924 IndexModeUpd, f, itin_upd,
1925 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1926 let Inst{24-23} = 0b01; // Increment After
1927 let Inst{21} = 1; // Writeback
1928 let Inst{20} = L_bit;
1931 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1932 IndexModeNone, f, itin,
1933 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
1934 let Inst{24-23} = 0b00; // Decrement After
1935 let Inst{21} = 0; // No writeback
1936 let Inst{20} = L_bit;
1939 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1940 IndexModeUpd, f, itin_upd,
1941 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1942 let Inst{24-23} = 0b00; // Decrement After
1943 let Inst{21} = 1; // Writeback
1944 let Inst{20} = L_bit;
1947 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1948 IndexModeNone, f, itin,
1949 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
1950 let Inst{24-23} = 0b10; // Decrement Before
1951 let Inst{21} = 0; // No writeback
1952 let Inst{20} = L_bit;
1955 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1956 IndexModeUpd, f, itin_upd,
1957 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1958 let Inst{24-23} = 0b10; // Decrement Before
1959 let Inst{21} = 1; // Writeback
1960 let Inst{20} = L_bit;
1963 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1964 IndexModeNone, f, itin,
1965 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
1966 let Inst{24-23} = 0b11; // Increment Before
1967 let Inst{21} = 0; // No writeback
1968 let Inst{20} = L_bit;
1971 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1972 IndexModeUpd, f, itin_upd,
1973 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1974 let Inst{24-23} = 0b11; // Increment Before
1975 let Inst{21} = 1; // Writeback
1976 let Inst{20} = L_bit;
1980 let neverHasSideEffects = 1 in {
1982 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1983 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
1985 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1986 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
1988 } // neverHasSideEffects
1990 // Load / Store Multiple Mnemonic Aliases
1991 def : MnemonicAlias<"ldm", "ldmia">;
1992 def : MnemonicAlias<"stm", "stmia">;
1994 // FIXME: remove when we have a way to marking a MI with these properties.
1995 // FIXME: Should pc be an implicit operand like PICADD, etc?
1996 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1997 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1998 def LDMIA_RET : ARMPseudoInst<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
1999 reglist:$regs, variable_ops),
2000 Size4Bytes, IIC_iLoad_mBr, []>,
2001 RegConstraint<"$Rn = $wb">;
2003 //===----------------------------------------------------------------------===//
2004 // Move Instructions.
2007 let neverHasSideEffects = 1 in
2008 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2009 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2013 let Inst{19-16} = 0b0000;
2014 let Inst{11-4} = 0b00000000;
2017 let Inst{15-12} = Rd;
2020 // A version for the smaller set of tail call registers.
2021 let neverHasSideEffects = 1 in
2022 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2023 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2027 let Inst{11-4} = 0b00000000;
2030 let Inst{15-12} = Rd;
2033 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
2034 DPSoRegFrm, IIC_iMOVsr,
2035 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
2039 let Inst{15-12} = Rd;
2040 let Inst{19-16} = 0b0000;
2041 let Inst{11-0} = src;
2045 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2046 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2047 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2051 let Inst{15-12} = Rd;
2052 let Inst{19-16} = 0b0000;
2053 let Inst{11-0} = imm;
2056 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2057 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins i32imm_hilo16:$imm),
2059 "movw", "\t$Rd, $imm",
2060 [(set GPR:$Rd, imm0_65535:$imm)]>,
2061 Requires<[IsARM, HasV6T2]>, UnaryDP {
2064 let Inst{15-12} = Rd;
2065 let Inst{11-0} = imm{11-0};
2066 let Inst{19-16} = imm{15-12};
2071 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2072 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2074 let Constraints = "$src = $Rd" in {
2075 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, i32imm_hilo16:$imm),
2077 "movt", "\t$Rd, $imm",
2079 (or (and GPR:$src, 0xffff),
2080 lo16AllZero:$imm))]>, UnaryDP,
2081 Requires<[IsARM, HasV6T2]> {
2084 let Inst{15-12} = Rd;
2085 let Inst{11-0} = imm{11-0};
2086 let Inst{19-16} = imm{15-12};
2091 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2092 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2096 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2097 Requires<[IsARM, HasV6T2]>;
2099 let Uses = [CPSR] in
2100 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2101 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2104 // These aren't really mov instructions, but we have to define them this way
2105 // due to flag operands.
2107 let Defs = [CPSR] in {
2108 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2109 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2111 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2112 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2116 //===----------------------------------------------------------------------===//
2117 // Extend Instructions.
2122 defm SXTB : AI_ext_rrot<0b01101010,
2123 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2124 defm SXTH : AI_ext_rrot<0b01101011,
2125 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2127 defm SXTAB : AI_exta_rrot<0b01101010,
2128 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2129 defm SXTAH : AI_exta_rrot<0b01101011,
2130 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2132 // For disassembly only
2133 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2135 // For disassembly only
2136 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2140 let AddedComplexity = 16 in {
2141 defm UXTB : AI_ext_rrot<0b01101110,
2142 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2143 defm UXTH : AI_ext_rrot<0b01101111,
2144 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2145 defm UXTB16 : AI_ext_rrot<0b01101100,
2146 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2148 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2149 // The transformation should probably be done as a combiner action
2150 // instead so we can include a check for masking back in the upper
2151 // eight bits of the source into the lower eight bits of the result.
2152 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2153 // (UXTB16r_rot GPR:$Src, 24)>;
2154 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2155 (UXTB16r_rot GPR:$Src, 8)>;
2157 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2158 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2159 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2160 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2163 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2164 // For disassembly only
2165 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2168 def SBFX : I<(outs GPR:$Rd),
2169 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2170 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2171 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2172 Requires<[IsARM, HasV6T2]> {
2177 let Inst{27-21} = 0b0111101;
2178 let Inst{6-4} = 0b101;
2179 let Inst{20-16} = width;
2180 let Inst{15-12} = Rd;
2181 let Inst{11-7} = lsb;
2185 def UBFX : I<(outs GPR:$Rd),
2186 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2187 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2188 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2189 Requires<[IsARM, HasV6T2]> {
2194 let Inst{27-21} = 0b0111111;
2195 let Inst{6-4} = 0b101;
2196 let Inst{20-16} = width;
2197 let Inst{15-12} = Rd;
2198 let Inst{11-7} = lsb;
2202 //===----------------------------------------------------------------------===//
2203 // Arithmetic Instructions.
2206 defm ADD : AsI1_bin_irs<0b0100, "add",
2207 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2208 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
2209 defm SUB : AsI1_bin_irs<0b0010, "sub",
2210 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2211 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
2213 // ADD and SUB with 's' bit set.
2214 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
2215 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2216 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
2217 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
2218 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2219 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
2221 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
2222 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
2223 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
2224 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
2226 // ADC and SUBC with 's' bit set.
2227 let usesCustomInserter = 1 in {
2228 defm ADCS : AI1_adde_sube_s_irs<
2229 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
2230 defm SBCS : AI1_adde_sube_s_irs<
2231 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
2234 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2235 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
2236 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
2241 let Inst{15-12} = Rd;
2242 let Inst{19-16} = Rn;
2243 let Inst{11-0} = imm;
2246 // The reg/reg form is only defined for the disassembler; for codegen it is
2247 // equivalent to SUBrr.
2248 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2249 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
2250 [/* For disassembly only; pattern left blank */]> {
2254 let Inst{11-4} = 0b00000000;
2257 let Inst{15-12} = Rd;
2258 let Inst{19-16} = Rn;
2261 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2262 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2263 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
2268 let Inst{11-0} = shift;
2269 let Inst{15-12} = Rd;
2270 let Inst{19-16} = Rn;
2273 // RSB with 's' bit set.
2274 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
2275 let usesCustomInserter = 1 in {
2276 def RSBSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2277 Size4Bytes, IIC_iALUi,
2278 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]>;
2279 def RSBSrr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2280 Size4Bytes, IIC_iALUr,
2281 [/* For disassembly only; pattern left blank */]>;
2282 def RSBSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2283 Size4Bytes, IIC_iALUsr,
2284 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]>;
2287 let Uses = [CPSR] in {
2288 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2289 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2290 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2296 let Inst{15-12} = Rd;
2297 let Inst{19-16} = Rn;
2298 let Inst{11-0} = imm;
2300 // The reg/reg form is only defined for the disassembler; for codegen it is
2301 // equivalent to SUBrr.
2302 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2303 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2304 [/* For disassembly only; pattern left blank */]> {
2308 let Inst{11-4} = 0b00000000;
2311 let Inst{15-12} = Rd;
2312 let Inst{19-16} = Rn;
2314 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2315 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2316 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2322 let Inst{11-0} = shift;
2323 let Inst{15-12} = Rd;
2324 let Inst{19-16} = Rn;
2328 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
2329 let usesCustomInserter = 1, Uses = [CPSR] in {
2330 def RSCSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2331 Size4Bytes, IIC_iALUi,
2332 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>;
2333 def RSCSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2334 Size4Bytes, IIC_iALUsr,
2335 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>;
2338 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2339 // The assume-no-carry-in form uses the negation of the input since add/sub
2340 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2341 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2343 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2344 (SUBri GPR:$src, so_imm_neg:$imm)>;
2345 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2346 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2347 // The with-carry-in form matches bitwise not instead of the negation.
2348 // Effectively, the inverse interpretation of the carry flag already accounts
2349 // for part of the negation.
2350 def : ARMPat<(adde_dead_carry GPR:$src, so_imm_not:$imm),
2351 (SBCri GPR:$src, so_imm_not:$imm)>;
2352 def : ARMPat<(adde_live_carry GPR:$src, so_imm_not:$imm),
2353 (SBCSri GPR:$src, so_imm_not:$imm)>;
2355 // Note: These are implemented in C++ code, because they have to generate
2356 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2358 // (mul X, 2^n+1) -> (add (X << n), X)
2359 // (mul X, 2^n-1) -> (rsb X, (X << n))
2361 // ARM Arithmetic Instruction -- for disassembly only
2362 // GPR:$dst = GPR:$a op GPR:$b
2363 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2364 list<dag> pattern = [/* For disassembly only; pattern left blank */],
2365 dag iops = (ins GPR:$Rn, GPR:$Rm), string asm = "\t$Rd, $Rn, $Rm">
2366 : AI<(outs GPR:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
2370 let Inst{27-20} = op27_20;
2371 let Inst{11-4} = op11_4;
2372 let Inst{19-16} = Rn;
2373 let Inst{15-12} = Rd;
2377 // Saturating add/subtract -- for disassembly only
2379 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2380 [(set GPR:$Rd, (int_arm_qadd GPR:$Rm, GPR:$Rn))],
2381 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2382 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2383 [(set GPR:$Rd, (int_arm_qsub GPR:$Rm, GPR:$Rn))],
2384 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2385 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [], (ins GPR:$Rm, GPR:$Rn),
2387 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [], (ins GPR:$Rm, GPR:$Rn),
2390 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2391 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2392 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2393 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2394 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2395 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2396 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2397 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2398 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2399 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2400 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2401 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2403 // Signed/Unsigned add/subtract -- for disassembly only
2405 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2406 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2407 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2408 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2409 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2410 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2411 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2412 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2413 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2414 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2415 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2416 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2418 // Signed/Unsigned halving add/subtract -- for disassembly only
2420 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2421 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2422 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2423 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2424 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2425 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2426 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2427 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2428 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2429 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2430 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2431 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2433 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2435 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2436 MulFrm /* for convenience */, NoItinerary, "usad8",
2437 "\t$Rd, $Rn, $Rm", []>,
2438 Requires<[IsARM, HasV6]> {
2442 let Inst{27-20} = 0b01111000;
2443 let Inst{15-12} = 0b1111;
2444 let Inst{7-4} = 0b0001;
2445 let Inst{19-16} = Rd;
2446 let Inst{11-8} = Rm;
2449 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2450 MulFrm /* for convenience */, NoItinerary, "usada8",
2451 "\t$Rd, $Rn, $Rm, $Ra", []>,
2452 Requires<[IsARM, HasV6]> {
2457 let Inst{27-20} = 0b01111000;
2458 let Inst{7-4} = 0b0001;
2459 let Inst{19-16} = Rd;
2460 let Inst{15-12} = Ra;
2461 let Inst{11-8} = Rm;
2465 // Signed/Unsigned saturate -- for disassembly only
2467 def SSAT : AI<(outs GPR:$Rd), (ins ssat_imm:$sat_imm, GPR:$a, shift_imm:$sh),
2468 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2469 [/* For disassembly only; pattern left blank */]> {
2474 let Inst{27-21} = 0b0110101;
2475 let Inst{5-4} = 0b01;
2476 let Inst{20-16} = sat_imm;
2477 let Inst{15-12} = Rd;
2478 let Inst{11-7} = sh{7-3};
2479 let Inst{6} = sh{0};
2483 def SSAT16 : AI<(outs GPR:$Rd), (ins ssat_imm:$sat_imm, GPR:$Rn), SatFrm,
2484 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2485 [/* For disassembly only; pattern left blank */]> {
2489 let Inst{27-20} = 0b01101010;
2490 let Inst{11-4} = 0b11110011;
2491 let Inst{15-12} = Rd;
2492 let Inst{19-16} = sat_imm;
2496 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2497 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2498 [/* For disassembly only; pattern left blank */]> {
2503 let Inst{27-21} = 0b0110111;
2504 let Inst{5-4} = 0b01;
2505 let Inst{15-12} = Rd;
2506 let Inst{11-7} = sh{7-3};
2507 let Inst{6} = sh{0};
2508 let Inst{20-16} = sat_imm;
2512 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2513 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2514 [/* For disassembly only; pattern left blank */]> {
2518 let Inst{27-20} = 0b01101110;
2519 let Inst{11-4} = 0b11110011;
2520 let Inst{15-12} = Rd;
2521 let Inst{19-16} = sat_imm;
2525 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2526 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2528 //===----------------------------------------------------------------------===//
2529 // Bitwise Instructions.
2532 defm AND : AsI1_bin_irs<0b0000, "and",
2533 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2534 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2535 defm ORR : AsI1_bin_irs<0b1100, "orr",
2536 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2537 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2538 defm EOR : AsI1_bin_irs<0b0001, "eor",
2539 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2540 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2541 defm BIC : AsI1_bin_irs<0b1110, "bic",
2542 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2543 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2545 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2546 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2547 "bfc", "\t$Rd, $imm", "$src = $Rd",
2548 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2549 Requires<[IsARM, HasV6T2]> {
2552 let Inst{27-21} = 0b0111110;
2553 let Inst{6-0} = 0b0011111;
2554 let Inst{15-12} = Rd;
2555 let Inst{11-7} = imm{4-0}; // lsb
2556 let Inst{20-16} = imm{9-5}; // width
2559 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2560 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2561 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2562 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2563 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2564 bf_inv_mask_imm:$imm))]>,
2565 Requires<[IsARM, HasV6T2]> {
2569 let Inst{27-21} = 0b0111110;
2570 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2571 let Inst{15-12} = Rd;
2572 let Inst{11-7} = imm{4-0}; // lsb
2573 let Inst{20-16} = imm{9-5}; // width
2577 // GNU as only supports this form of bfi (w/ 4 arguments)
2578 let isAsmParserOnly = 1 in
2579 def BFI4p : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn,
2580 lsb_pos_imm:$lsb, width_imm:$width),
2581 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2582 "bfi", "\t$Rd, $Rn, $lsb, $width", "$src = $Rd",
2583 []>, Requires<[IsARM, HasV6T2]> {
2588 let Inst{27-21} = 0b0111110;
2589 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2590 let Inst{15-12} = Rd;
2591 let Inst{11-7} = lsb;
2592 let Inst{20-16} = width; // Custom encoder => lsb+width-1
2596 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2597 "mvn", "\t$Rd, $Rm",
2598 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2602 let Inst{19-16} = 0b0000;
2603 let Inst{11-4} = 0b00000000;
2604 let Inst{15-12} = Rd;
2607 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2608 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2609 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2613 let Inst{19-16} = 0b0000;
2614 let Inst{15-12} = Rd;
2615 let Inst{11-0} = shift;
2617 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2618 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2619 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2620 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2624 let Inst{19-16} = 0b0000;
2625 let Inst{15-12} = Rd;
2626 let Inst{11-0} = imm;
2629 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2630 (BICri GPR:$src, so_imm_not:$imm)>;
2632 //===----------------------------------------------------------------------===//
2633 // Multiply Instructions.
2635 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2636 string opc, string asm, list<dag> pattern>
2637 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2641 let Inst{19-16} = Rd;
2642 let Inst{11-8} = Rm;
2645 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2646 string opc, string asm, list<dag> pattern>
2647 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2652 let Inst{19-16} = RdHi;
2653 let Inst{15-12} = RdLo;
2654 let Inst{11-8} = Rm;
2658 let isCommutable = 1 in {
2659 let Constraints = "@earlyclobber $Rd" in
2660 def MULv5: ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
2661 pred:$p, cc_out:$s),
2662 Size4Bytes, IIC_iMUL32,
2663 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2664 Requires<[IsARM, NoV6]>;
2666 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2667 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2668 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2669 Requires<[IsARM, HasV6]> {
2670 let Inst{15-12} = 0b0000;
2674 let Constraints = "@earlyclobber $Rd" in
2675 def MLAv5: ARMPseudoInst<(outs GPR:$Rd),
2676 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
2677 Size4Bytes, IIC_iMAC32,
2678 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2679 Requires<[IsARM, NoV6]> {
2681 let Inst{15-12} = Ra;
2683 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2684 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2685 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2686 Requires<[IsARM, HasV6]> {
2688 let Inst{15-12} = Ra;
2691 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2692 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
2693 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
2694 Requires<[IsARM, HasV6T2]> {
2699 let Inst{19-16} = Rd;
2700 let Inst{15-12} = Ra;
2701 let Inst{11-8} = Rm;
2705 // Extra precision multiplies with low / high results
2707 let neverHasSideEffects = 1 in {
2708 let isCommutable = 1 in {
2709 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2710 def SMULLv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2711 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2712 Size4Bytes, IIC_iMUL64, []>,
2713 Requires<[IsARM, NoV6]>;
2715 def UMULLv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2716 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2717 Size4Bytes, IIC_iMUL64, []>,
2718 Requires<[IsARM, NoV6]>;
2721 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2722 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2723 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2724 Requires<[IsARM, HasV6]>;
2726 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2727 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2728 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2729 Requires<[IsARM, HasV6]>;
2732 // Multiply + accumulate
2733 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2734 def SMLALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2735 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2736 Size4Bytes, IIC_iMAC64, []>,
2737 Requires<[IsARM, NoV6]>;
2738 def UMLALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2739 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2740 Size4Bytes, IIC_iMAC64, []>,
2741 Requires<[IsARM, NoV6]>;
2742 def UMAALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2743 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2744 Size4Bytes, IIC_iMAC64, []>,
2745 Requires<[IsARM, NoV6]>;
2749 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2750 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2751 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2752 Requires<[IsARM, HasV6]>;
2753 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2754 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2755 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2756 Requires<[IsARM, HasV6]>;
2758 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2759 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2760 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2761 Requires<[IsARM, HasV6]> {
2766 let Inst{19-16} = RdLo;
2767 let Inst{15-12} = RdHi;
2768 let Inst{11-8} = Rm;
2771 } // neverHasSideEffects
2773 // Most significant word multiply
2774 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2775 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2776 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2777 Requires<[IsARM, HasV6]> {
2778 let Inst{15-12} = 0b1111;
2781 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2782 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2783 [/* For disassembly only; pattern left blank */]>,
2784 Requires<[IsARM, HasV6]> {
2785 let Inst{15-12} = 0b1111;
2788 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2789 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2790 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2791 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2792 Requires<[IsARM, HasV6]>;
2794 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2795 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2796 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2797 [/* For disassembly only; pattern left blank */]>,
2798 Requires<[IsARM, HasV6]>;
2800 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2801 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2802 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2803 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2804 Requires<[IsARM, HasV6]>;
2806 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2807 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2808 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2809 [/* For disassembly only; pattern left blank */]>,
2810 Requires<[IsARM, HasV6]>;
2812 multiclass AI_smul<string opc, PatFrag opnode> {
2813 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2814 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2815 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2816 (sext_inreg GPR:$Rm, i16)))]>,
2817 Requires<[IsARM, HasV5TE]>;
2819 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2820 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2821 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2822 (sra GPR:$Rm, (i32 16))))]>,
2823 Requires<[IsARM, HasV5TE]>;
2825 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2826 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2827 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2828 (sext_inreg GPR:$Rm, i16)))]>,
2829 Requires<[IsARM, HasV5TE]>;
2831 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2832 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2833 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2834 (sra GPR:$Rm, (i32 16))))]>,
2835 Requires<[IsARM, HasV5TE]>;
2837 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2838 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2839 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2840 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2841 Requires<[IsARM, HasV5TE]>;
2843 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2844 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2845 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2846 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2847 Requires<[IsARM, HasV5TE]>;
2851 multiclass AI_smla<string opc, PatFrag opnode> {
2852 def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
2853 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2854 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2855 [(set GPR:$Rd, (add GPR:$Ra,
2856 (opnode (sext_inreg GPR:$Rn, i16),
2857 (sext_inreg GPR:$Rm, i16))))]>,
2858 Requires<[IsARM, HasV5TE]>;
2860 def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd),
2861 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2862 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2863 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2864 (sra GPR:$Rm, (i32 16)))))]>,
2865 Requires<[IsARM, HasV5TE]>;
2867 def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd),
2868 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2869 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2870 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2871 (sext_inreg GPR:$Rm, i16))))]>,
2872 Requires<[IsARM, HasV5TE]>;
2874 def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
2875 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2876 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2877 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2878 (sra GPR:$Rm, (i32 16)))))]>,
2879 Requires<[IsARM, HasV5TE]>;
2881 def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd),
2882 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2883 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2884 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2885 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2886 Requires<[IsARM, HasV5TE]>;
2888 def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd),
2889 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2890 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2891 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2892 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2893 Requires<[IsARM, HasV5TE]>;
2896 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2897 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2899 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2900 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2901 (ins GPR:$Rn, GPR:$Rm),
2902 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2903 [/* For disassembly only; pattern left blank */]>,
2904 Requires<[IsARM, HasV5TE]>;
2906 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2907 (ins GPR:$Rn, GPR:$Rm),
2908 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2909 [/* For disassembly only; pattern left blank */]>,
2910 Requires<[IsARM, HasV5TE]>;
2912 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2913 (ins GPR:$Rn, GPR:$Rm),
2914 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2915 [/* For disassembly only; pattern left blank */]>,
2916 Requires<[IsARM, HasV5TE]>;
2918 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2919 (ins GPR:$Rn, GPR:$Rm),
2920 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2921 [/* For disassembly only; pattern left blank */]>,
2922 Requires<[IsARM, HasV5TE]>;
2924 // Helper class for AI_smld -- for disassembly only
2925 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2926 InstrItinClass itin, string opc, string asm>
2927 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2934 let Inst{21-20} = 0b00;
2935 let Inst{22} = long;
2936 let Inst{27-23} = 0b01110;
2937 let Inst{11-8} = Rm;
2940 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2941 InstrItinClass itin, string opc, string asm>
2942 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2944 let Inst{15-12} = 0b1111;
2945 let Inst{19-16} = Rd;
2947 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2948 InstrItinClass itin, string opc, string asm>
2949 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2951 let Inst{15-12} = Ra;
2953 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2954 InstrItinClass itin, string opc, string asm>
2955 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2958 let Inst{19-16} = RdHi;
2959 let Inst{15-12} = RdLo;
2962 multiclass AI_smld<bit sub, string opc> {
2964 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2965 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
2967 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2968 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
2970 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
2971 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2972 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
2974 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
2975 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2976 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
2980 defm SMLA : AI_smld<0, "smla">;
2981 defm SMLS : AI_smld<1, "smls">;
2983 multiclass AI_sdml<bit sub, string opc> {
2985 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2986 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
2987 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2988 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
2991 defm SMUA : AI_sdml<0, "smua">;
2992 defm SMUS : AI_sdml<1, "smus">;
2994 //===----------------------------------------------------------------------===//
2995 // Misc. Arithmetic Instructions.
2998 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
2999 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3000 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3002 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3003 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3004 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3005 Requires<[IsARM, HasV6T2]>;
3007 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3008 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3009 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3011 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3012 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3014 (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
3015 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
3016 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
3017 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
3018 Requires<[IsARM, HasV6]>;
3020 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3021 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3024 (or (srl GPR:$Rm, (i32 8)),
3025 (shl GPR:$Rm, (i32 8))), i16))]>,
3026 Requires<[IsARM, HasV6]>;
3028 def : ARMV6Pat<(sext_inreg (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
3029 (shl GPR:$Rm, (i32 8))), i16),
3032 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3033 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3036 // Need the AddedComplexity or else MOVs + REV would be chosen.
3037 let AddedComplexity = 5 in
3038 def : ARMV6Pat<(sra (bswap GPR:$Rm), (i32 16)), (REVSH GPR:$Rm)>;
3040 def lsl_shift_imm : SDNodeXForm<imm, [{
3041 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
3042 return CurDAG->getTargetConstant(Sh, MVT::i32);
3045 def lsl_amt : ImmLeaf<i32, [{
3046 return Imm > 0 && Imm < 32;
3049 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
3050 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3051 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3052 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
3053 (and (shl GPR:$Rm, lsl_amt:$sh),
3055 Requires<[IsARM, HasV6]>;
3057 // Alternate cases for PKHBT where identities eliminate some nodes.
3058 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
3059 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
3060 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
3061 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
3063 def asr_shift_imm : SDNodeXForm<imm, [{
3064 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
3065 return CurDAG->getTargetConstant(Sh, MVT::i32);
3068 def asr_amt : ImmLeaf<i32, [{
3069 return Imm > 0 && Imm <= 32;
3072 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3073 // will match the pattern below.
3074 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
3075 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3076 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3077 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
3078 (and (sra GPR:$Rm, asr_amt:$sh),
3080 Requires<[IsARM, HasV6]>;
3082 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3083 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3084 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
3085 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
3086 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
3087 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
3088 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
3090 //===----------------------------------------------------------------------===//
3091 // Comparison Instructions...
3094 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3095 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3096 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3098 // ARMcmpZ can re-use the above instruction definitions.
3099 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3100 (CMPri GPR:$src, so_imm:$imm)>;
3101 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3102 (CMPrr GPR:$src, GPR:$rhs)>;
3103 def : ARMPat<(ARMcmpZ GPR:$src, so_reg:$rhs),
3104 (CMPrs GPR:$src, so_reg:$rhs)>;
3106 // FIXME: We have to be careful when using the CMN instruction and comparison
3107 // with 0. One would expect these two pieces of code should give identical
3123 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3124 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3125 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3126 // value of r0 and the carry bit (because the "carry bit" parameter to
3127 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3128 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3129 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3130 // parameter to AddWithCarry is defined as 0).
3132 // When x is 0 and unsigned:
3136 // ~x + 1 = 0x1 0000 0000
3137 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3139 // Therefore, we should disable CMN when comparing against zero, until we can
3140 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3141 // when it's a comparison which doesn't look at the 'carry' flag).
3143 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3145 // This is related to <rdar://problem/7569620>.
3147 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3148 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3150 // Note that TST/TEQ don't set all the same flags that CMP does!
3151 defm TST : AI1_cmp_irs<0b1000, "tst",
3152 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3153 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3154 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3155 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3156 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3158 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
3159 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3160 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
3162 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3163 // (CMNri GPR:$src, so_imm_neg:$imm)>;
3165 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3166 (CMNzri GPR:$src, so_imm_neg:$imm)>;
3168 // Pseudo i64 compares for some floating point compares.
3169 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3171 def BCCi64 : PseudoInst<(outs),
3172 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3174 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3176 def BCCZi64 : PseudoInst<(outs),
3177 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3178 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3179 } // usesCustomInserter
3182 // Conditional moves
3183 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3184 // a two-value operand where a dag node expects two operands. :(
3185 let neverHasSideEffects = 1 in {
3186 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3187 Size4Bytes, IIC_iCMOVr,
3188 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3189 RegConstraint<"$false = $Rd">;
3190 def MOVCCs : ARMPseudoInst<(outs GPR:$Rd),
3191 (ins GPR:$false, so_reg:$shift, pred:$p),
3192 Size4Bytes, IIC_iCMOVsr,
3193 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
3194 RegConstraint<"$false = $Rd">;
3196 let isMoveImm = 1 in
3197 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3198 (ins GPR:$false, i32imm_hilo16:$imm, pred:$p),
3199 Size4Bytes, IIC_iMOVi,
3201 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3203 let isMoveImm = 1 in
3204 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3205 (ins GPR:$false, so_imm:$imm, pred:$p),
3206 Size4Bytes, IIC_iCMOVi,
3207 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3208 RegConstraint<"$false = $Rd">;
3210 // Two instruction predicate mov immediate.
3211 let isMoveImm = 1 in
3212 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
3213 (ins GPR:$false, i32imm:$src, pred:$p),
3214 Size8Bytes, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3216 let isMoveImm = 1 in
3217 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
3218 (ins GPR:$false, so_imm:$imm, pred:$p),
3219 Size4Bytes, IIC_iCMOVi,
3220 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3221 RegConstraint<"$false = $Rd">;
3222 } // neverHasSideEffects
3224 //===----------------------------------------------------------------------===//
3225 // Atomic operations intrinsics
3228 def memb_opt : Operand<i32> {
3229 let PrintMethod = "printMemBOption";
3230 let ParserMatchClass = MemBarrierOptOperand;
3233 // memory barriers protect the atomic sequences
3234 let hasSideEffects = 1 in {
3235 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3236 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3237 Requires<[IsARM, HasDB]> {
3239 let Inst{31-4} = 0xf57ff05;
3240 let Inst{3-0} = opt;
3244 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3246 [/* For disassembly only; pattern left blank */]>,
3247 Requires<[IsARM, HasDB]> {
3249 let Inst{31-4} = 0xf57ff04;
3250 let Inst{3-0} = opt;
3253 // ISB has only full system option -- for disassembly only
3254 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
3255 Requires<[IsARM, HasDB]> {
3256 let Inst{31-4} = 0xf57ff06;
3257 let Inst{3-0} = 0b1111;
3260 let usesCustomInserter = 1 in {
3261 let Uses = [CPSR] in {
3262 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
3263 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3264 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
3265 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
3266 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3267 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
3268 def ATOMIC_LOAD_AND_I8 : PseudoInst<
3269 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3270 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
3271 def ATOMIC_LOAD_OR_I8 : PseudoInst<
3272 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3273 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
3274 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
3275 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3276 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
3277 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
3278 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3279 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
3280 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
3281 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3282 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
3283 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
3284 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3285 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
3286 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
3287 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3288 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
3289 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
3290 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3291 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
3292 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
3293 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3294 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
3295 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
3296 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3297 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
3298 def ATOMIC_LOAD_AND_I16 : PseudoInst<
3299 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3300 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
3301 def ATOMIC_LOAD_OR_I16 : PseudoInst<
3302 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3303 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
3304 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
3305 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3306 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
3307 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
3308 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3309 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
3310 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
3311 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3312 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
3313 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
3314 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3315 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
3316 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
3317 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3318 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
3319 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
3320 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3321 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
3322 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
3323 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3324 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
3325 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
3326 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3327 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
3328 def ATOMIC_LOAD_AND_I32 : PseudoInst<
3329 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3330 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
3331 def ATOMIC_LOAD_OR_I32 : PseudoInst<
3332 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3333 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
3334 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
3335 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3336 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
3337 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
3338 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3339 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
3340 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
3341 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3342 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
3343 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
3344 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3345 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
3346 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
3347 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3348 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
3349 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
3350 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3351 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
3353 def ATOMIC_SWAP_I8 : PseudoInst<
3354 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3355 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3356 def ATOMIC_SWAP_I16 : PseudoInst<
3357 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3358 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3359 def ATOMIC_SWAP_I32 : PseudoInst<
3360 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3361 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3363 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3364 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3365 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3366 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3367 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3368 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3369 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3370 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3371 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3375 let mayLoad = 1 in {
3376 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3377 "ldrexb", "\t$Rt, $addr", []>;
3378 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3379 "ldrexh", "\t$Rt, $addr", []>;
3380 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3381 "ldrex", "\t$Rt, $addr", []>;
3382 let hasExtraDefRegAllocReq = 1 in
3383 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode7:$addr),
3384 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []>;
3387 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3388 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3389 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
3390 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3391 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
3392 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3393 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
3396 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
3397 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3398 (ins GPR:$Rt, GPR:$Rt2, addrmode7:$addr),
3399 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []>;
3401 // Clear-Exclusive is for disassembly only.
3402 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3403 [/* For disassembly only; pattern left blank */]>,
3404 Requires<[IsARM, HasV7]> {
3405 let Inst{31-0} = 0b11110101011111111111000000011111;
3408 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3409 let mayLoad = 1 in {
3410 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3411 [/* For disassembly only; pattern left blank */]>;
3412 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3413 [/* For disassembly only; pattern left blank */]>;
3416 //===----------------------------------------------------------------------===//
3417 // Coprocessor Instructions.
3420 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3421 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3422 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3423 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3424 imm:$CRm, imm:$opc2)]> {
3432 let Inst{3-0} = CRm;
3434 let Inst{7-5} = opc2;
3435 let Inst{11-8} = cop;
3436 let Inst{15-12} = CRd;
3437 let Inst{19-16} = CRn;
3438 let Inst{23-20} = opc1;
3441 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3442 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3443 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3444 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3445 imm:$CRm, imm:$opc2)]> {
3446 let Inst{31-28} = 0b1111;
3454 let Inst{3-0} = CRm;
3456 let Inst{7-5} = opc2;
3457 let Inst{11-8} = cop;
3458 let Inst{15-12} = CRd;
3459 let Inst{19-16} = CRn;
3460 let Inst{23-20} = opc1;
3463 class ACI<dag oops, dag iops, string opc, string asm,
3464 IndexMode im = IndexModeNone>
3465 : InoP<oops, iops, AddrModeNone, Size4Bytes, im, BrFrm, NoItinerary,
3466 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3467 let Inst{27-25} = 0b110;
3470 multiclass LdStCop<bits<4> op31_28, bit load, dag ops, string opc, string cond>{
3472 def _OFFSET : ACI<(outs),
3473 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3474 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr"> {
3475 let Inst{31-28} = op31_28;
3476 let Inst{24} = 1; // P = 1
3477 let Inst{21} = 0; // W = 0
3478 let Inst{22} = 0; // D = 0
3479 let Inst{20} = load;
3482 def _PRE : ACI<(outs),
3483 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3484 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr!", IndexModePre> {
3485 let Inst{31-28} = op31_28;
3486 let Inst{24} = 1; // P = 1
3487 let Inst{21} = 1; // W = 1
3488 let Inst{22} = 0; // D = 0
3489 let Inst{20} = load;
3492 def _POST : ACI<(outs),
3493 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3494 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr", IndexModePost> {
3495 let Inst{31-28} = op31_28;
3496 let Inst{24} = 0; // P = 0
3497 let Inst{21} = 1; // W = 1
3498 let Inst{22} = 0; // D = 0
3499 let Inst{20} = load;
3502 def _OPTION : ACI<(outs),
3503 !con((ins nohash_imm:$cop,nohash_imm:$CRd,GPR:$base, nohash_imm:$option),
3505 !strconcat(opc, cond), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3506 let Inst{31-28} = op31_28;
3507 let Inst{24} = 0; // P = 0
3508 let Inst{23} = 1; // U = 1
3509 let Inst{21} = 0; // W = 0
3510 let Inst{22} = 0; // D = 0
3511 let Inst{20} = load;
3514 def L_OFFSET : ACI<(outs),
3515 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3516 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr"> {
3517 let Inst{31-28} = op31_28;
3518 let Inst{24} = 1; // P = 1
3519 let Inst{21} = 0; // W = 0
3520 let Inst{22} = 1; // D = 1
3521 let Inst{20} = load;
3524 def L_PRE : ACI<(outs),
3525 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3526 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr!",
3528 let Inst{31-28} = op31_28;
3529 let Inst{24} = 1; // P = 1
3530 let Inst{21} = 1; // W = 1
3531 let Inst{22} = 1; // D = 1
3532 let Inst{20} = load;
3535 def L_POST : ACI<(outs),
3536 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3537 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr",
3539 let Inst{31-28} = op31_28;
3540 let Inst{24} = 0; // P = 0
3541 let Inst{21} = 1; // W = 1
3542 let Inst{22} = 1; // D = 1
3543 let Inst{20} = load;
3546 def L_OPTION : ACI<(outs),
3547 !con((ins nohash_imm:$cop, nohash_imm:$CRd,GPR:$base,nohash_imm:$option),
3549 !strconcat(!strconcat(opc, "l"), cond),
3550 "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3551 let Inst{31-28} = op31_28;
3552 let Inst{24} = 0; // P = 0
3553 let Inst{23} = 1; // U = 1
3554 let Inst{21} = 0; // W = 0
3555 let Inst{22} = 1; // D = 1
3556 let Inst{20} = load;
3560 defm LDC : LdStCop<{?,?,?,?}, 1, (ins pred:$p), "ldc", "${p}">;
3561 defm LDC2 : LdStCop<0b1111, 1, (ins), "ldc2", "">;
3562 defm STC : LdStCop<{?,?,?,?}, 0, (ins pred:$p), "stc", "${p}">;
3563 defm STC2 : LdStCop<0b1111, 0, (ins), "stc2", "">;
3565 //===----------------------------------------------------------------------===//
3566 // Move between coprocessor and ARM core register -- for disassembly only
3569 class MovRCopro<string opc, bit direction, dag oops, dag iops,
3571 : ABI<0b1110, oops, iops, NoItinerary, opc,
3572 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
3573 let Inst{20} = direction;
3583 let Inst{15-12} = Rt;
3584 let Inst{11-8} = cop;
3585 let Inst{23-21} = opc1;
3586 let Inst{7-5} = opc2;
3587 let Inst{3-0} = CRm;
3588 let Inst{19-16} = CRn;
3591 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
3593 (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn,
3594 c_imm:$CRm, i32imm:$opc2),
3595 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3596 imm:$CRm, imm:$opc2)]>;
3597 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
3599 (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn, c_imm:$CRm,
3602 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3603 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3605 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
3607 : ABXI<0b1110, oops, iops, NoItinerary,
3608 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
3609 let Inst{31-28} = 0b1111;
3610 let Inst{20} = direction;
3620 let Inst{15-12} = Rt;
3621 let Inst{11-8} = cop;
3622 let Inst{23-21} = opc1;
3623 let Inst{7-5} = opc2;
3624 let Inst{3-0} = CRm;
3625 let Inst{19-16} = CRn;
3628 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
3630 (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn,
3631 c_imm:$CRm, i32imm:$opc2),
3632 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3633 imm:$CRm, imm:$opc2)]>;
3634 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
3636 (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn, c_imm:$CRm,
3639 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
3640 imm:$CRm, imm:$opc2),
3641 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3643 class MovRRCopro<string opc, bit direction,
3644 list<dag> pattern = [/* For disassembly only */]>
3645 : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
3646 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3647 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
3648 let Inst{23-21} = 0b010;
3649 let Inst{20} = direction;
3657 let Inst{15-12} = Rt;
3658 let Inst{19-16} = Rt2;
3659 let Inst{11-8} = cop;
3660 let Inst{7-4} = opc1;
3661 let Inst{3-0} = CRm;
3664 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
3665 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3667 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
3669 class MovRRCopro2<string opc, bit direction,
3670 list<dag> pattern = [/* For disassembly only */]>
3671 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
3672 GPR:$Rt, GPR:$Rt2, c_imm:$CRm), NoItinerary,
3673 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3674 let Inst{31-28} = 0b1111;
3675 let Inst{23-21} = 0b010;
3676 let Inst{20} = direction;
3684 let Inst{15-12} = Rt;
3685 let Inst{19-16} = Rt2;
3686 let Inst{11-8} = cop;
3687 let Inst{7-4} = opc1;
3688 let Inst{3-0} = CRm;
3691 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
3692 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3694 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
3696 //===----------------------------------------------------------------------===//
3697 // Move between special register and ARM core register -- for disassembly only
3700 // Move to ARM core register from Special Register
3701 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3702 [/* For disassembly only; pattern left blank */]> {
3704 let Inst{23-16} = 0b00001111;
3705 let Inst{15-12} = Rd;
3706 let Inst{7-4} = 0b0000;
3709 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,"mrs","\t$Rd, spsr",
3710 [/* For disassembly only; pattern left blank */]> {
3712 let Inst{23-16} = 0b01001111;
3713 let Inst{15-12} = Rd;
3714 let Inst{7-4} = 0b0000;
3717 // Move from ARM core register to Special Register
3719 // No need to have both system and application versions, the encodings are the
3720 // same and the assembly parser has no way to distinguish between them. The mask
3721 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3722 // the mask with the fields to be accessed in the special register.
3723 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
3724 "msr", "\t$mask, $Rn",
3725 [/* For disassembly only; pattern left blank */]> {
3730 let Inst{22} = mask{4}; // R bit
3731 let Inst{21-20} = 0b10;
3732 let Inst{19-16} = mask{3-0};
3733 let Inst{15-12} = 0b1111;
3734 let Inst{11-4} = 0b00000000;
3738 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
3739 "msr", "\t$mask, $a",
3740 [/* For disassembly only; pattern left blank */]> {
3745 let Inst{22} = mask{4}; // R bit
3746 let Inst{21-20} = 0b10;
3747 let Inst{19-16} = mask{3-0};
3748 let Inst{15-12} = 0b1111;
3752 //===----------------------------------------------------------------------===//
3756 // __aeabi_read_tp preserves the registers r1-r3.
3757 // This is a pseudo inst so that we can get the encoding right,
3758 // complete with fixup for the aeabi_read_tp function.
3760 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
3761 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
3762 [(set R0, ARMthread_pointer)]>;
3765 //===----------------------------------------------------------------------===//
3766 // SJLJ Exception handling intrinsics
3767 // eh_sjlj_setjmp() is an instruction sequence to store the return
3768 // address and save #0 in R0 for the non-longjmp case.
3769 // Since by its nature we may be coming from some other function to get
3770 // here, and we're using the stack frame for the containing function to
3771 // save/restore registers, we can't keep anything live in regs across
3772 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3773 // when we get here from a longjmp(). We force everything out of registers
3774 // except for our own input by listing the relevant registers in Defs. By
3775 // doing so, we also cause the prologue/epilogue code to actively preserve
3776 // all of the callee-saved resgisters, which is exactly what we want.
3777 // A constant value is passed in $val, and we use the location as a scratch.
3779 // These are pseudo-instructions and are lowered to individual MC-insts, so
3780 // no encoding information is necessary.
3782 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
3783 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ], hasSideEffects = 1, isBarrier = 1 in {
3784 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3786 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3787 Requires<[IsARM, HasVFP2]>;
3791 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
3792 hasSideEffects = 1, isBarrier = 1 in {
3793 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3795 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3796 Requires<[IsARM, NoVFP]>;
3799 // FIXME: Non-Darwin version(s)
3800 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3801 Defs = [ R7, LR, SP ] in {
3802 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
3804 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3805 Requires<[IsARM, IsDarwin]>;
3808 // eh.sjlj.dispatchsetup pseudo-instruction.
3809 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3810 // handled when the pseudo is expanded (which happens before any passes
3811 // that need the instruction size).
3812 let isBarrier = 1, hasSideEffects = 1 in
3813 def Int_eh_sjlj_dispatchsetup :
3814 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
3815 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
3816 Requires<[IsDarwin]>;
3818 //===----------------------------------------------------------------------===//
3819 // Non-Instruction Patterns
3822 // Large immediate handling.
3824 // 32-bit immediate using two piece so_imms or movw + movt.
3825 // This is a single pseudo instruction, the benefit is that it can be remat'd
3826 // as a single unit instead of having to handle reg inputs.
3827 // FIXME: Remove this when we can do generalized remat.
3828 let isReMaterializable = 1, isMoveImm = 1 in
3829 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3830 [(set GPR:$dst, (arm_i32imm:$src))]>,
3833 // Pseudo instruction that combines movw + movt + add pc (if PIC).
3834 // It also makes it possible to rematerialize the instructions.
3835 // FIXME: Remove this when we can do generalized remat and when machine licm
3836 // can properly the instructions.
3837 let isReMaterializable = 1 in {
3838 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3840 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3841 Requires<[IsARM, UseMovt]>;
3843 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3845 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3846 Requires<[IsARM, UseMovt]>;
3848 let AddedComplexity = 10 in
3849 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3851 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
3852 Requires<[IsARM, UseMovt]>;
3853 } // isReMaterializable
3855 // ConstantPool, GlobalAddress, and JumpTable
3856 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3857 Requires<[IsARM, DontUseMovt]>;
3858 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3859 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3860 Requires<[IsARM, UseMovt]>;
3861 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3862 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3864 // TODO: add,sub,and, 3-instr forms?
3867 def : ARMPat<(ARMtcret tcGPR:$dst),
3868 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3870 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3871 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3873 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3874 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3876 def : ARMPat<(ARMtcret tcGPR:$dst),
3877 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3879 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3880 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3882 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3883 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3886 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3887 Requires<[IsARM, IsNotDarwin]>;
3888 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3889 Requires<[IsARM, IsDarwin]>;
3891 // zextload i1 -> zextload i8
3892 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3893 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3895 // extload -> zextload
3896 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3897 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3898 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3899 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3901 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3903 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3904 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3907 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3908 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3909 (SMULBB GPR:$a, GPR:$b)>;
3910 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3911 (SMULBB GPR:$a, GPR:$b)>;
3912 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3913 (sra GPR:$b, (i32 16))),
3914 (SMULBT GPR:$a, GPR:$b)>;
3915 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3916 (SMULBT GPR:$a, GPR:$b)>;
3917 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3918 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3919 (SMULTB GPR:$a, GPR:$b)>;
3920 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3921 (SMULTB GPR:$a, GPR:$b)>;
3922 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3924 (SMULWB GPR:$a, GPR:$b)>;
3925 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3926 (SMULWB GPR:$a, GPR:$b)>;
3928 def : ARMV5TEPat<(add GPR:$acc,
3929 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3930 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3931 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3932 def : ARMV5TEPat<(add GPR:$acc,
3933 (mul sext_16_node:$a, sext_16_node:$b)),
3934 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3935 def : ARMV5TEPat<(add GPR:$acc,
3936 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3937 (sra GPR:$b, (i32 16)))),
3938 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3939 def : ARMV5TEPat<(add GPR:$acc,
3940 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3941 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3942 def : ARMV5TEPat<(add GPR:$acc,
3943 (mul (sra GPR:$a, (i32 16)),
3944 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3945 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3946 def : ARMV5TEPat<(add GPR:$acc,
3947 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3948 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3949 def : ARMV5TEPat<(add GPR:$acc,
3950 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3952 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3953 def : ARMV5TEPat<(add GPR:$acc,
3954 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3955 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3958 // Pre-v7 uses MCR for synchronization barriers.
3959 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
3960 Requires<[IsARM, HasV6]>;
3963 //===----------------------------------------------------------------------===//
3967 include "ARMInstrThumb.td"
3969 //===----------------------------------------------------------------------===//
3973 include "ARMInstrThumb2.td"
3975 //===----------------------------------------------------------------------===//
3976 // Floating Point Support
3979 include "ARMInstrVFP.td"
3981 //===----------------------------------------------------------------------===//
3982 // Advanced SIMD (NEON) Support
3985 include "ARMInstrNEON.td"