1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 3,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
40 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
42 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
44 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
46 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
47 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
48 SDTCisVT<5, OtherVT>]>;
50 def SDT_ARMAnd : SDTypeProfile<1, 2,
51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
54 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
56 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
57 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
59 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
60 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
62 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
64 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
66 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
69 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
71 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def SDT_ARMVMAXNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
75 def SDT_ARMVMINNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
77 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
80 SDTCisInt<0>, SDTCisVT<1, i32>]>;
82 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
83 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
90 def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>,
91 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
92 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >;
93 def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
94 def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>;
97 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
98 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
99 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
101 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
102 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
103 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
104 [SDNPHasChain, SDNPSideEffect,
105 SDNPOptInGlue, SDNPOutGlue]>;
106 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
108 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
109 SDNPMayStore, SDNPMayLoad]>;
111 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
112 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
114 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
115 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
117 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
118 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
121 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
122 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
123 def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall,
124 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
125 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
128 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
129 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
131 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
133 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
136 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
139 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
142 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
145 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
146 [SDNPOutGlue, SDNPCommutative]>;
148 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
150 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
151 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
152 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
154 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
156 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
157 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
158 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
160 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
161 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
162 SDT_ARMEH_SJLJ_Setjmp,
163 [SDNPHasChain, SDNPSideEffect]>;
164 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
165 SDT_ARMEH_SJLJ_Longjmp,
166 [SDNPHasChain, SDNPSideEffect]>;
168 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
169 [SDNPHasChain, SDNPSideEffect]>;
170 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
171 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
173 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
175 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
176 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
178 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
180 def ARMvmaxnm : SDNode<"ARMISD::VMAXNM", SDT_ARMVMAXNM, []>;
181 def ARMvminnm : SDNode<"ARMISD::VMINNM", SDT_ARMVMINNM, []>;
183 //===----------------------------------------------------------------------===//
184 // ARM Instruction Predicate Definitions.
186 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
187 AssemblerPredicate<"HasV4TOps", "armv4t">;
188 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
189 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
190 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
191 AssemblerPredicate<"HasV5TEOps", "armv5te">;
192 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
193 AssemblerPredicate<"HasV6Ops", "armv6">;
194 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
195 def HasV6M : Predicate<"Subtarget->hasV6MOps()">,
196 AssemblerPredicate<"HasV6MOps",
197 "armv6m or armv6t2">;
198 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
199 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
200 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
201 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
202 AssemblerPredicate<"HasV7Ops", "armv7">;
203 def HasV8 : Predicate<"Subtarget->hasV8Ops()">,
204 AssemblerPredicate<"HasV8Ops", "armv8">;
205 def PreV8 : Predicate<"!Subtarget->hasV8Ops()">,
206 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">;
207 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
208 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
209 AssemblerPredicate<"FeatureVFP2", "VFP2">;
210 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
211 AssemblerPredicate<"FeatureVFP3", "VFP3">;
212 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
213 AssemblerPredicate<"FeatureVFP4", "VFP4">;
214 def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">,
215 AssemblerPredicate<"!FeatureVFPOnlySP",
216 "double precision VFP">;
217 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
218 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">;
219 def HasNEON : Predicate<"Subtarget->hasNEON()">,
220 AssemblerPredicate<"FeatureNEON", "NEON">;
221 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
222 AssemblerPredicate<"FeatureCrypto", "crypto">;
223 def HasCRC : Predicate<"Subtarget->hasCRC()">,
224 AssemblerPredicate<"FeatureCRC", "crc">;
225 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
226 AssemblerPredicate<"FeatureFP16","half-float">;
227 def HasDivide : Predicate<"Subtarget->hasDivide()">,
228 AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">;
229 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
230 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">;
231 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
232 AssemblerPredicate<"FeatureT2XtPk",
234 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
235 AssemblerPredicate<"FeatureDSPThumb2",
237 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
238 AssemblerPredicate<"FeatureDB",
240 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
241 AssemblerPredicate<"FeatureMP",
243 def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
244 AssemblerPredicate<"FeatureTrustZone",
246 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
247 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
248 def IsThumb : Predicate<"Subtarget->isThumb()">,
249 AssemblerPredicate<"ModeThumb", "thumb">;
250 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
251 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
252 AssemblerPredicate<"ModeThumb,FeatureThumb2",
254 def IsMClass : Predicate<"Subtarget->isMClass()">,
255 AssemblerPredicate<"FeatureMClass", "armv*m">;
256 def IsNotMClass : Predicate<"!Subtarget->isMClass()">,
257 AssemblerPredicate<"!FeatureMClass",
259 def IsARM : Predicate<"!Subtarget->isThumb()">,
260 AssemblerPredicate<"!ModeThumb", "arm-mode">;
261 def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
262 def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
263 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
264 def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
265 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
266 def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
268 // FIXME: Eventually this will be just "hasV6T2Ops".
269 def UseMovt : Predicate<"Subtarget->useMovt()">;
270 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
271 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
272 def UseMulOps : Predicate<"Subtarget->useMulOps()">;
274 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
275 // But only select them if more precision in FP computation is allowed.
276 // Do not use them for Darwin platforms.
277 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
278 " FPOpFusion::Fast) && "
279 "!Subtarget->isTargetDarwin()">;
280 def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion =="
281 " FPOpFusion::Fast &&"
282 " Subtarget->hasVFP4()) || "
283 "Subtarget->isTargetDarwin()">;
285 // VGETLNi32 is microcoded on Swift - prefer VMOV.
286 def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
287 def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
289 // VDUP.32 is microcoded on Swift - prefer VMOV.
290 def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
291 def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
293 // Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as
294 // this allows more effective execution domain optimization. See
295 // setExecutionDomain().
296 def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;
297 def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;
299 def IsLE : Predicate<"getTargetLowering()->isLittleEndian()">;
300 def IsBE : Predicate<"getTargetLowering()->isBigEndian()">;
302 //===----------------------------------------------------------------------===//
303 // ARM Flag Definitions.
305 class RegConstraint<string C> {
306 string Constraints = C;
309 //===----------------------------------------------------------------------===//
310 // ARM specific transformation functions and pattern fragments.
313 // imm_neg_XFORM - Return the negation of an i32 immediate value.
314 def imm_neg_XFORM : SDNodeXForm<imm, [{
315 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
318 // imm_not_XFORM - Return the complement of a i32 immediate value.
319 def imm_not_XFORM : SDNodeXForm<imm, [{
320 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
323 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
324 def imm16_31 : ImmLeaf<i32, [{
325 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
328 def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; }
329 def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
330 unsigned Value = -(unsigned)N->getZExtValue();
331 return Value && ARM_AM::getSOImmVal(Value) != -1;
333 let ParserMatchClass = so_imm_neg_asmoperand;
336 // Note: this pattern doesn't require an encoder method and such, as it's
337 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
338 // is handled by the destination instructions, which use so_imm.
339 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
340 def so_imm_not : Operand<i32>, PatLeaf<(imm), [{
341 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
343 let ParserMatchClass = so_imm_not_asmoperand;
346 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
347 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
348 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
351 /// Split a 32-bit immediate into two 16 bit parts.
352 def hi16 : SDNodeXForm<imm, [{
353 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
356 def lo16AllZero : PatLeaf<(i32 imm), [{
357 // Returns true if all low 16-bits are 0.
358 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
361 class BinOpWithFlagFrag<dag res> :
362 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
363 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
364 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
366 // An 'and' node with a single use.
367 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
368 return N->hasOneUse();
371 // An 'xor' node with a single use.
372 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
373 return N->hasOneUse();
376 // An 'fmul' node with a single use.
377 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
378 return N->hasOneUse();
381 // An 'fadd' node which checks for single non-hazardous use.
382 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
383 return hasNoVMLxHazardUse(N);
386 // An 'fsub' node which checks for single non-hazardous use.
387 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
388 return hasNoVMLxHazardUse(N);
391 //===----------------------------------------------------------------------===//
392 // Operand Definitions.
395 // Immediate operands with a shared generic asm render method.
396 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
399 // FIXME: rename brtarget to t2_brtarget
400 def brtarget : Operand<OtherVT> {
401 let EncoderMethod = "getBranchTargetOpValue";
402 let OperandType = "OPERAND_PCREL";
403 let DecoderMethod = "DecodeT2BROperand";
406 // FIXME: get rid of this one?
407 def uncondbrtarget : Operand<OtherVT> {
408 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
409 let OperandType = "OPERAND_PCREL";
412 // Branch target for ARM. Handles conditional/unconditional
413 def br_target : Operand<OtherVT> {
414 let EncoderMethod = "getARMBranchTargetOpValue";
415 let OperandType = "OPERAND_PCREL";
419 // FIXME: rename bltarget to t2_bl_target?
420 def bltarget : Operand<i32> {
421 // Encoded the same as branch targets.
422 let EncoderMethod = "getBranchTargetOpValue";
423 let OperandType = "OPERAND_PCREL";
426 // Call target for ARM. Handles conditional/unconditional
427 // FIXME: rename bl_target to t2_bltarget?
428 def bl_target : Operand<i32> {
429 let EncoderMethod = "getARMBLTargetOpValue";
430 let OperandType = "OPERAND_PCREL";
433 def blx_target : Operand<i32> {
434 let EncoderMethod = "getARMBLXTargetOpValue";
435 let OperandType = "OPERAND_PCREL";
438 // A list of registers separated by comma. Used by load/store multiple.
439 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
440 def reglist : Operand<i32> {
441 let EncoderMethod = "getRegisterListOpValue";
442 let ParserMatchClass = RegListAsmOperand;
443 let PrintMethod = "printRegisterList";
444 let DecoderMethod = "DecodeRegListOperand";
447 def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
449 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
450 def dpr_reglist : Operand<i32> {
451 let EncoderMethod = "getRegisterListOpValue";
452 let ParserMatchClass = DPRRegListAsmOperand;
453 let PrintMethod = "printRegisterList";
454 let DecoderMethod = "DecodeDPRRegListOperand";
457 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
458 def spr_reglist : Operand<i32> {
459 let EncoderMethod = "getRegisterListOpValue";
460 let ParserMatchClass = SPRRegListAsmOperand;
461 let PrintMethod = "printRegisterList";
462 let DecoderMethod = "DecodeSPRRegListOperand";
465 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
466 def cpinst_operand : Operand<i32> {
467 let PrintMethod = "printCPInstOperand";
471 def pclabel : Operand<i32> {
472 let PrintMethod = "printPCLabel";
475 // ADR instruction labels.
476 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
477 def adrlabel : Operand<i32> {
478 let EncoderMethod = "getAdrLabelOpValue";
479 let ParserMatchClass = AdrLabelAsmOperand;
480 let PrintMethod = "printAdrLabelOperand<0>";
483 def neon_vcvt_imm32 : Operand<i32> {
484 let EncoderMethod = "getNEONVcvtImm32OpValue";
485 let DecoderMethod = "DecodeVCVTImmOperand";
488 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
489 def rot_imm_XFORM: SDNodeXForm<imm, [{
490 switch (N->getZExtValue()){
492 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
493 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
494 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
495 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
498 def RotImmAsmOperand : AsmOperandClass {
500 let ParserMethod = "parseRotImm";
502 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
503 int32_t v = N->getZExtValue();
504 return v == 8 || v == 16 || v == 24; }],
506 let PrintMethod = "printRotImmOperand";
507 let ParserMatchClass = RotImmAsmOperand;
510 // shift_imm: An integer that encodes a shift amount and the type of shift
511 // (asr or lsl). The 6-bit immediate encodes as:
514 // {4-0} imm5 shift amount.
515 // asr #32 encoded as imm5 == 0.
516 def ShifterImmAsmOperand : AsmOperandClass {
517 let Name = "ShifterImm";
518 let ParserMethod = "parseShifterImm";
520 def shift_imm : Operand<i32> {
521 let PrintMethod = "printShiftImmOperand";
522 let ParserMatchClass = ShifterImmAsmOperand;
525 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
526 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
527 def so_reg_reg : Operand<i32>, // reg reg imm
528 ComplexPattern<i32, 3, "SelectRegShifterOperand",
529 [shl, srl, sra, rotr]> {
530 let EncoderMethod = "getSORegRegOpValue";
531 let PrintMethod = "printSORegRegOperand";
532 let DecoderMethod = "DecodeSORegRegOperand";
533 let ParserMatchClass = ShiftedRegAsmOperand;
534 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
537 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
538 def so_reg_imm : Operand<i32>, // reg imm
539 ComplexPattern<i32, 2, "SelectImmShifterOperand",
540 [shl, srl, sra, rotr]> {
541 let EncoderMethod = "getSORegImmOpValue";
542 let PrintMethod = "printSORegImmOperand";
543 let DecoderMethod = "DecodeSORegImmOperand";
544 let ParserMatchClass = ShiftedImmAsmOperand;
545 let MIOperandInfo = (ops GPR, i32imm);
548 // FIXME: Does this need to be distinct from so_reg?
549 def shift_so_reg_reg : Operand<i32>, // reg reg imm
550 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
551 [shl,srl,sra,rotr]> {
552 let EncoderMethod = "getSORegRegOpValue";
553 let PrintMethod = "printSORegRegOperand";
554 let DecoderMethod = "DecodeSORegRegOperand";
555 let ParserMatchClass = ShiftedRegAsmOperand;
556 let MIOperandInfo = (ops GPR, GPR, i32imm);
559 // FIXME: Does this need to be distinct from so_reg?
560 def shift_so_reg_imm : Operand<i32>, // reg reg imm
561 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
562 [shl,srl,sra,rotr]> {
563 let EncoderMethod = "getSORegImmOpValue";
564 let PrintMethod = "printSORegImmOperand";
565 let DecoderMethod = "DecodeSORegImmOperand";
566 let ParserMatchClass = ShiftedImmAsmOperand;
567 let MIOperandInfo = (ops GPR, i32imm);
571 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
572 // 8-bit immediate rotated by an arbitrary number of bits.
573 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
574 def so_imm : Operand<i32>, ImmLeaf<i32, [{
575 return ARM_AM::getSOImmVal(Imm) != -1;
577 let EncoderMethod = "getSOImmOpValue";
578 let ParserMatchClass = SOImmAsmOperand;
579 let DecoderMethod = "DecodeSOImmOperand";
582 // Break so_imm's up into two pieces. This handles immediates with up to 16
583 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
584 // get the first/second pieces.
585 def so_imm2part : PatLeaf<(imm), [{
586 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
589 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
591 def arm_i32imm : PatLeaf<(imm), [{
592 if (Subtarget->hasV6T2Ops())
594 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
597 /// imm0_1 predicate - Immediate in the range [0,1].
598 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
599 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
601 /// imm0_3 predicate - Immediate in the range [0,3].
602 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
603 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
605 /// imm0_7 predicate - Immediate in the range [0,7].
606 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
607 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
608 return Imm >= 0 && Imm < 8;
610 let ParserMatchClass = Imm0_7AsmOperand;
613 /// imm8 predicate - Immediate is exactly 8.
614 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
615 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
616 let ParserMatchClass = Imm8AsmOperand;
619 /// imm16 predicate - Immediate is exactly 16.
620 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
621 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
622 let ParserMatchClass = Imm16AsmOperand;
625 /// imm32 predicate - Immediate is exactly 32.
626 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
627 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
628 let ParserMatchClass = Imm32AsmOperand;
631 /// imm1_7 predicate - Immediate in the range [1,7].
632 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
633 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
634 let ParserMatchClass = Imm1_7AsmOperand;
637 /// imm1_15 predicate - Immediate in the range [1,15].
638 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
639 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
640 let ParserMatchClass = Imm1_15AsmOperand;
643 /// imm1_31 predicate - Immediate in the range [1,31].
644 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
645 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
646 let ParserMatchClass = Imm1_31AsmOperand;
649 /// imm0_15 predicate - Immediate in the range [0,15].
650 def Imm0_15AsmOperand: ImmAsmOperand {
651 let Name = "Imm0_15";
652 let DiagnosticType = "ImmRange0_15";
654 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
655 return Imm >= 0 && Imm < 16;
657 let ParserMatchClass = Imm0_15AsmOperand;
660 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
661 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
662 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
663 return Imm >= 0 && Imm < 32;
665 let ParserMatchClass = Imm0_31AsmOperand;
668 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
669 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
670 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
671 return Imm >= 0 && Imm < 32;
673 let ParserMatchClass = Imm0_32AsmOperand;
676 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
677 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
678 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
679 return Imm >= 0 && Imm < 64;
681 let ParserMatchClass = Imm0_63AsmOperand;
684 /// imm0_239 predicate - Immediate in the range [0,239].
685 def Imm0_239AsmOperand : ImmAsmOperand {
686 let Name = "Imm0_239";
687 let DiagnosticType = "ImmRange0_239";
689 def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> {
690 let ParserMatchClass = Imm0_239AsmOperand;
693 /// imm0_255 predicate - Immediate in the range [0,255].
694 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
695 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
696 let ParserMatchClass = Imm0_255AsmOperand;
699 /// imm0_65535 - An immediate is in the range [0.65535].
700 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
701 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
702 return Imm >= 0 && Imm < 65536;
704 let ParserMatchClass = Imm0_65535AsmOperand;
707 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
708 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
709 return -Imm >= 0 && -Imm < 65536;
712 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
713 // a relocatable expression.
715 // FIXME: This really needs a Thumb version separate from the ARM version.
716 // While the range is the same, and can thus use the same match class,
717 // the encoding is different so it should have a different encoder method.
718 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
719 def imm0_65535_expr : Operand<i32> {
720 let EncoderMethod = "getHiLo16ImmOpValue";
721 let ParserMatchClass = Imm0_65535ExprAsmOperand;
724 def Imm256_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm256_65535Expr"; }
725 def imm256_65535_expr : Operand<i32> {
726 let ParserMatchClass = Imm256_65535ExprAsmOperand;
729 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
730 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
731 def imm24b : Operand<i32>, ImmLeaf<i32, [{
732 return Imm >= 0 && Imm <= 0xffffff;
734 let ParserMatchClass = Imm24bitAsmOperand;
738 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
740 def BitfieldAsmOperand : AsmOperandClass {
741 let Name = "Bitfield";
742 let ParserMethod = "parseBitfield";
745 def bf_inv_mask_imm : Operand<i32>,
747 return ARM::isBitFieldInvertedMask(N->getZExtValue());
749 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
750 let PrintMethod = "printBitfieldInvMaskImmOperand";
751 let DecoderMethod = "DecodeBitfieldMaskOperand";
752 let ParserMatchClass = BitfieldAsmOperand;
755 def imm1_32_XFORM: SDNodeXForm<imm, [{
756 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
758 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
759 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
760 uint64_t Imm = N->getZExtValue();
761 return Imm > 0 && Imm <= 32;
764 let PrintMethod = "printImmPlusOneOperand";
765 let ParserMatchClass = Imm1_32AsmOperand;
768 def imm1_16_XFORM: SDNodeXForm<imm, [{
769 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
771 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
772 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
774 let PrintMethod = "printImmPlusOneOperand";
775 let ParserMatchClass = Imm1_16AsmOperand;
778 // Define ARM specific addressing modes.
779 // addrmode_imm12 := reg +/- imm12
781 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
782 class AddrMode_Imm12 : Operand<i32>,
783 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
784 // 12-bit immediate operand. Note that instructions using this encode
785 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
786 // immediate values are as normal.
788 let EncoderMethod = "getAddrModeImm12OpValue";
789 let DecoderMethod = "DecodeAddrModeImm12Operand";
790 let ParserMatchClass = MemImm12OffsetAsmOperand;
791 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
794 def addrmode_imm12 : AddrMode_Imm12 {
795 let PrintMethod = "printAddrModeImm12Operand<false>";
798 def addrmode_imm12_pre : AddrMode_Imm12 {
799 let PrintMethod = "printAddrModeImm12Operand<true>";
802 // ldst_so_reg := reg +/- reg shop imm
804 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
805 def ldst_so_reg : Operand<i32>,
806 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
807 let EncoderMethod = "getLdStSORegOpValue";
808 // FIXME: Simplify the printer
809 let PrintMethod = "printAddrMode2Operand";
810 let DecoderMethod = "DecodeSORegMemOperand";
811 let ParserMatchClass = MemRegOffsetAsmOperand;
812 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
815 // postidx_imm8 := +/- [0,255]
818 // {8} 1 is imm8 is non-negative. 0 otherwise.
819 // {7-0} [0,255] imm8 value.
820 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
821 def postidx_imm8 : Operand<i32> {
822 let PrintMethod = "printPostIdxImm8Operand";
823 let ParserMatchClass = PostIdxImm8AsmOperand;
824 let MIOperandInfo = (ops i32imm);
827 // postidx_imm8s4 := +/- [0,1020]
830 // {8} 1 is imm8 is non-negative. 0 otherwise.
831 // {7-0} [0,255] imm8 value, scaled by 4.
832 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
833 def postidx_imm8s4 : Operand<i32> {
834 let PrintMethod = "printPostIdxImm8s4Operand";
835 let ParserMatchClass = PostIdxImm8s4AsmOperand;
836 let MIOperandInfo = (ops i32imm);
840 // postidx_reg := +/- reg
842 def PostIdxRegAsmOperand : AsmOperandClass {
843 let Name = "PostIdxReg";
844 let ParserMethod = "parsePostIdxReg";
846 def postidx_reg : Operand<i32> {
847 let EncoderMethod = "getPostIdxRegOpValue";
848 let DecoderMethod = "DecodePostIdxReg";
849 let PrintMethod = "printPostIdxRegOperand";
850 let ParserMatchClass = PostIdxRegAsmOperand;
851 let MIOperandInfo = (ops GPRnopc, i32imm);
855 // addrmode2 := reg +/- imm12
856 // := reg +/- reg shop imm
858 // FIXME: addrmode2 should be refactored the rest of the way to always
859 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
860 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
861 def addrmode2 : Operand<i32>,
862 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
863 let EncoderMethod = "getAddrMode2OpValue";
864 let PrintMethod = "printAddrMode2Operand";
865 let ParserMatchClass = AddrMode2AsmOperand;
866 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
869 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
870 let Name = "PostIdxRegShifted";
871 let ParserMethod = "parsePostIdxReg";
873 def am2offset_reg : Operand<i32>,
874 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
875 [], [SDNPWantRoot]> {
876 let EncoderMethod = "getAddrMode2OffsetOpValue";
877 let PrintMethod = "printAddrMode2OffsetOperand";
878 // When using this for assembly, it's always as a post-index offset.
879 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
880 let MIOperandInfo = (ops GPRnopc, i32imm);
883 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
884 // the GPR is purely vestigal at this point.
885 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
886 def am2offset_imm : Operand<i32>,
887 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
888 [], [SDNPWantRoot]> {
889 let EncoderMethod = "getAddrMode2OffsetOpValue";
890 let PrintMethod = "printAddrMode2OffsetOperand";
891 let ParserMatchClass = AM2OffsetImmAsmOperand;
892 let MIOperandInfo = (ops GPRnopc, i32imm);
896 // addrmode3 := reg +/- reg
897 // addrmode3 := reg +/- imm8
899 // FIXME: split into imm vs. reg versions.
900 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
901 class AddrMode3 : Operand<i32>,
902 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
903 let EncoderMethod = "getAddrMode3OpValue";
904 let ParserMatchClass = AddrMode3AsmOperand;
905 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
908 def addrmode3 : AddrMode3
910 let PrintMethod = "printAddrMode3Operand<false>";
913 def addrmode3_pre : AddrMode3
915 let PrintMethod = "printAddrMode3Operand<true>";
918 // FIXME: split into imm vs. reg versions.
919 // FIXME: parser method to handle +/- register.
920 def AM3OffsetAsmOperand : AsmOperandClass {
921 let Name = "AM3Offset";
922 let ParserMethod = "parseAM3Offset";
924 def am3offset : Operand<i32>,
925 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
926 [], [SDNPWantRoot]> {
927 let EncoderMethod = "getAddrMode3OffsetOpValue";
928 let PrintMethod = "printAddrMode3OffsetOperand";
929 let ParserMatchClass = AM3OffsetAsmOperand;
930 let MIOperandInfo = (ops GPR, i32imm);
933 // ldstm_mode := {ia, ib, da, db}
935 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
936 let EncoderMethod = "getLdStmModeOpValue";
937 let PrintMethod = "printLdStmModeOperand";
940 // addrmode5 := reg +/- imm8*4
942 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
943 class AddrMode5 : Operand<i32>,
944 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
945 let EncoderMethod = "getAddrMode5OpValue";
946 let DecoderMethod = "DecodeAddrMode5Operand";
947 let ParserMatchClass = AddrMode5AsmOperand;
948 let MIOperandInfo = (ops GPR:$base, i32imm);
951 def addrmode5 : AddrMode5 {
952 let PrintMethod = "printAddrMode5Operand<false>";
955 def addrmode5_pre : AddrMode5 {
956 let PrintMethod = "printAddrMode5Operand<true>";
959 // addrmode6 := reg with optional alignment
961 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
962 def addrmode6 : Operand<i32>,
963 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
964 let PrintMethod = "printAddrMode6Operand";
965 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
966 let EncoderMethod = "getAddrMode6AddressOpValue";
967 let DecoderMethod = "DecodeAddrMode6Operand";
968 let ParserMatchClass = AddrMode6AsmOperand;
971 def am6offset : Operand<i32>,
972 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
973 [], [SDNPWantRoot]> {
974 let PrintMethod = "printAddrMode6OffsetOperand";
975 let MIOperandInfo = (ops GPR);
976 let EncoderMethod = "getAddrMode6OffsetOpValue";
977 let DecoderMethod = "DecodeGPRRegisterClass";
980 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
981 // (single element from one lane) for size 32.
982 def addrmode6oneL32 : Operand<i32>,
983 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
984 let PrintMethod = "printAddrMode6Operand";
985 let MIOperandInfo = (ops GPR:$addr, i32imm);
986 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
989 // Special version of addrmode6 to handle alignment encoding for VLD-dup
990 // instructions, specifically VLD4-dup.
991 def addrmode6dup : Operand<i32>,
992 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
993 let PrintMethod = "printAddrMode6Operand";
994 let MIOperandInfo = (ops GPR:$addr, i32imm);
995 let EncoderMethod = "getAddrMode6DupAddressOpValue";
996 // FIXME: This is close, but not quite right. The alignment specifier is
998 let ParserMatchClass = AddrMode6AsmOperand;
1001 // addrmodepc := pc + reg
1003 def addrmodepc : Operand<i32>,
1004 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
1005 let PrintMethod = "printAddrModePCOperand";
1006 let MIOperandInfo = (ops GPR, i32imm);
1009 // addr_offset_none := reg
1011 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
1012 def addr_offset_none : Operand<i32>,
1013 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
1014 let PrintMethod = "printAddrMode7Operand";
1015 let DecoderMethod = "DecodeAddrMode7Operand";
1016 let ParserMatchClass = MemNoOffsetAsmOperand;
1017 let MIOperandInfo = (ops GPR:$base);
1020 def nohash_imm : Operand<i32> {
1021 let PrintMethod = "printNoHashImmediate";
1024 def CoprocNumAsmOperand : AsmOperandClass {
1025 let Name = "CoprocNum";
1026 let ParserMethod = "parseCoprocNumOperand";
1028 def p_imm : Operand<i32> {
1029 let PrintMethod = "printPImmediate";
1030 let ParserMatchClass = CoprocNumAsmOperand;
1031 let DecoderMethod = "DecodeCoprocessor";
1034 def CoprocRegAsmOperand : AsmOperandClass {
1035 let Name = "CoprocReg";
1036 let ParserMethod = "parseCoprocRegOperand";
1038 def c_imm : Operand<i32> {
1039 let PrintMethod = "printCImmediate";
1040 let ParserMatchClass = CoprocRegAsmOperand;
1042 def CoprocOptionAsmOperand : AsmOperandClass {
1043 let Name = "CoprocOption";
1044 let ParserMethod = "parseCoprocOptionOperand";
1046 def coproc_option_imm : Operand<i32> {
1047 let PrintMethod = "printCoprocOptionImm";
1048 let ParserMatchClass = CoprocOptionAsmOperand;
1051 //===----------------------------------------------------------------------===//
1053 include "ARMInstrFormats.td"
1055 //===----------------------------------------------------------------------===//
1056 // Multiclass helpers...
1059 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
1060 /// binop that produces a value.
1061 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1062 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
1063 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1064 PatFrag opnode, bit Commutable = 0> {
1065 // The register-immediate version is re-materializable. This is useful
1066 // in particular for taking the address of a local.
1067 let isReMaterializable = 1 in {
1068 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1069 iii, opc, "\t$Rd, $Rn, $imm",
1070 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
1071 Sched<[WriteALU, ReadALU]> {
1076 let Inst{19-16} = Rn;
1077 let Inst{15-12} = Rd;
1078 let Inst{11-0} = imm;
1081 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1082 iir, opc, "\t$Rd, $Rn, $Rm",
1083 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1084 Sched<[WriteALU, ReadALU, ReadALU]> {
1089 let isCommutable = Commutable;
1090 let Inst{19-16} = Rn;
1091 let Inst{15-12} = Rd;
1092 let Inst{11-4} = 0b00000000;
1096 def rsi : AsI1<opcod, (outs GPR:$Rd),
1097 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1098 iis, opc, "\t$Rd, $Rn, $shift",
1099 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1100 Sched<[WriteALUsi, ReadALU]> {
1105 let Inst{19-16} = Rn;
1106 let Inst{15-12} = Rd;
1107 let Inst{11-5} = shift{11-5};
1109 let Inst{3-0} = shift{3-0};
1112 def rsr : AsI1<opcod, (outs GPR:$Rd),
1113 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1114 iis, opc, "\t$Rd, $Rn, $shift",
1115 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1116 Sched<[WriteALUsr, ReadALUsr]> {
1121 let Inst{19-16} = Rn;
1122 let Inst{15-12} = Rd;
1123 let Inst{11-8} = shift{11-8};
1125 let Inst{6-5} = shift{6-5};
1127 let Inst{3-0} = shift{3-0};
1131 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1132 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1133 /// it is equivalent to the AsI1_bin_irs counterpart.
1134 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1135 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1136 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1137 PatFrag opnode, bit Commutable = 0> {
1138 // The register-immediate version is re-materializable. This is useful
1139 // in particular for taking the address of a local.
1140 let isReMaterializable = 1 in {
1141 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1142 iii, opc, "\t$Rd, $Rn, $imm",
1143 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]>,
1144 Sched<[WriteALU, ReadALU]> {
1149 let Inst{19-16} = Rn;
1150 let Inst{15-12} = Rd;
1151 let Inst{11-0} = imm;
1154 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1155 iir, opc, "\t$Rd, $Rn, $Rm",
1156 [/* pattern left blank */]>,
1157 Sched<[WriteALU, ReadALU, ReadALU]> {
1161 let Inst{11-4} = 0b00000000;
1164 let Inst{15-12} = Rd;
1165 let Inst{19-16} = Rn;
1168 def rsi : AsI1<opcod, (outs GPR:$Rd),
1169 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1170 iis, opc, "\t$Rd, $Rn, $shift",
1171 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1172 Sched<[WriteALUsi, ReadALU]> {
1177 let Inst{19-16} = Rn;
1178 let Inst{15-12} = Rd;
1179 let Inst{11-5} = shift{11-5};
1181 let Inst{3-0} = shift{3-0};
1184 def rsr : AsI1<opcod, (outs GPR:$Rd),
1185 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1186 iis, opc, "\t$Rd, $Rn, $shift",
1187 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1188 Sched<[WriteALUsr, ReadALUsr]> {
1193 let Inst{19-16} = Rn;
1194 let Inst{15-12} = Rd;
1195 let Inst{11-8} = shift{11-8};
1197 let Inst{6-5} = shift{6-5};
1199 let Inst{3-0} = shift{3-0};
1203 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1205 /// These opcodes will be converted to the real non-S opcodes by
1206 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1207 let hasPostISelHook = 1, Defs = [CPSR] in {
1208 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1209 InstrItinClass iis, PatFrag opnode,
1210 bit Commutable = 0> {
1211 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1213 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>,
1214 Sched<[WriteALU, ReadALU]>;
1216 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1218 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1219 Sched<[WriteALU, ReadALU, ReadALU]> {
1220 let isCommutable = Commutable;
1222 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1223 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1225 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1226 so_reg_imm:$shift))]>,
1227 Sched<[WriteALUsi, ReadALU]>;
1229 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1230 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1232 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1233 so_reg_reg:$shift))]>,
1234 Sched<[WriteALUSsr, ReadALUsr]>;
1238 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1239 /// operands are reversed.
1240 let hasPostISelHook = 1, Defs = [CPSR] in {
1241 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1242 InstrItinClass iis, PatFrag opnode,
1243 bit Commutable = 0> {
1244 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1246 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>,
1247 Sched<[WriteALU, ReadALU]>;
1249 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1250 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1252 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1254 Sched<[WriteALUsi, ReadALU]>;
1256 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1257 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1259 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1261 Sched<[WriteALUSsr, ReadALUsr]>;
1265 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1266 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1267 /// a explicit result, only implicitly set CPSR.
1268 let isCompare = 1, Defs = [CPSR] in {
1269 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1270 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1271 PatFrag opnode, bit Commutable = 0> {
1272 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1274 [(opnode GPR:$Rn, so_imm:$imm)]>,
1275 Sched<[WriteCMP, ReadALU]> {
1280 let Inst{19-16} = Rn;
1281 let Inst{15-12} = 0b0000;
1282 let Inst{11-0} = imm;
1284 let Unpredictable{15-12} = 0b1111;
1286 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1288 [(opnode GPR:$Rn, GPR:$Rm)]>,
1289 Sched<[WriteCMP, ReadALU, ReadALU]> {
1292 let isCommutable = Commutable;
1295 let Inst{19-16} = Rn;
1296 let Inst{15-12} = 0b0000;
1297 let Inst{11-4} = 0b00000000;
1300 let Unpredictable{15-12} = 0b1111;
1302 def rsi : AI1<opcod, (outs),
1303 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1304 opc, "\t$Rn, $shift",
1305 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1306 Sched<[WriteCMPsi, ReadALU]> {
1311 let Inst{19-16} = Rn;
1312 let Inst{15-12} = 0b0000;
1313 let Inst{11-5} = shift{11-5};
1315 let Inst{3-0} = shift{3-0};
1317 let Unpredictable{15-12} = 0b1111;
1319 def rsr : AI1<opcod, (outs),
1320 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1321 opc, "\t$Rn, $shift",
1322 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
1323 Sched<[WriteCMPsr, ReadALU]> {
1328 let Inst{19-16} = Rn;
1329 let Inst{15-12} = 0b0000;
1330 let Inst{11-8} = shift{11-8};
1332 let Inst{6-5} = shift{6-5};
1334 let Inst{3-0} = shift{3-0};
1336 let Unpredictable{15-12} = 0b1111;
1342 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1343 /// register and one whose operand is a register rotated by 8/16/24.
1344 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1345 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1346 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1347 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1348 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1349 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1353 let Inst{19-16} = 0b1111;
1354 let Inst{15-12} = Rd;
1355 let Inst{11-10} = rot;
1359 class AI_ext_rrot_np<bits<8> opcod, string opc>
1360 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1361 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1362 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1364 let Inst{19-16} = 0b1111;
1365 let Inst{11-10} = rot;
1368 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1369 /// register and one whose operand is a register rotated by 8/16/24.
1370 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1371 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1372 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1373 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1374 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1375 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1380 let Inst{19-16} = Rn;
1381 let Inst{15-12} = Rd;
1382 let Inst{11-10} = rot;
1383 let Inst{9-4} = 0b000111;
1387 class AI_exta_rrot_np<bits<8> opcod, string opc>
1388 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1389 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1390 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1393 let Inst{19-16} = Rn;
1394 let Inst{11-10} = rot;
1397 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1398 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1399 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1400 bit Commutable = 0> {
1401 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1402 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1403 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1404 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1406 Sched<[WriteALU, ReadALU]> {
1411 let Inst{15-12} = Rd;
1412 let Inst{19-16} = Rn;
1413 let Inst{11-0} = imm;
1415 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1416 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1417 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1419 Sched<[WriteALU, ReadALU, ReadALU]> {
1423 let Inst{11-4} = 0b00000000;
1425 let isCommutable = Commutable;
1427 let Inst{15-12} = Rd;
1428 let Inst{19-16} = Rn;
1430 def rsi : AsI1<opcod, (outs GPR:$Rd),
1431 (ins GPR:$Rn, so_reg_imm:$shift),
1432 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1433 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1435 Sched<[WriteALUsi, ReadALU]> {
1440 let Inst{19-16} = Rn;
1441 let Inst{15-12} = Rd;
1442 let Inst{11-5} = shift{11-5};
1444 let Inst{3-0} = shift{3-0};
1446 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1447 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1448 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1449 [(set GPRnopc:$Rd, CPSR,
1450 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1452 Sched<[WriteALUsr, ReadALUsr]> {
1457 let Inst{19-16} = Rn;
1458 let Inst{15-12} = Rd;
1459 let Inst{11-8} = shift{11-8};
1461 let Inst{6-5} = shift{6-5};
1463 let Inst{3-0} = shift{3-0};
1468 /// AI1_rsc_irs - Define instructions and patterns for rsc
1469 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1470 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1471 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1472 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1473 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1474 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1476 Sched<[WriteALU, ReadALU]> {
1481 let Inst{15-12} = Rd;
1482 let Inst{19-16} = Rn;
1483 let Inst{11-0} = imm;
1485 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1486 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1487 [/* pattern left blank */]>,
1488 Sched<[WriteALU, ReadALU, ReadALU]> {
1492 let Inst{11-4} = 0b00000000;
1495 let Inst{15-12} = Rd;
1496 let Inst{19-16} = Rn;
1498 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1499 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1500 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1502 Sched<[WriteALUsi, ReadALU]> {
1507 let Inst{19-16} = Rn;
1508 let Inst{15-12} = Rd;
1509 let Inst{11-5} = shift{11-5};
1511 let Inst{3-0} = shift{3-0};
1513 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1514 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1515 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1517 Sched<[WriteALUsr, ReadALUsr]> {
1522 let Inst{19-16} = Rn;
1523 let Inst{15-12} = Rd;
1524 let Inst{11-8} = shift{11-8};
1526 let Inst{6-5} = shift{6-5};
1528 let Inst{3-0} = shift{3-0};
1533 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1534 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1535 InstrItinClass iir, PatFrag opnode> {
1536 // Note: We use the complex addrmode_imm12 rather than just an input
1537 // GPR and a constrained immediate so that we can use this to match
1538 // frame index references and avoid matching constant pool references.
1539 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1540 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1541 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1544 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1545 let Inst{19-16} = addr{16-13}; // Rn
1546 let Inst{15-12} = Rt;
1547 let Inst{11-0} = addr{11-0}; // imm12
1549 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1550 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1551 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1554 let shift{4} = 0; // Inst{4} = 0
1555 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1556 let Inst{19-16} = shift{16-13}; // Rn
1557 let Inst{15-12} = Rt;
1558 let Inst{11-0} = shift{11-0};
1563 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1564 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1565 InstrItinClass iir, PatFrag opnode> {
1566 // Note: We use the complex addrmode_imm12 rather than just an input
1567 // GPR and a constrained immediate so that we can use this to match
1568 // frame index references and avoid matching constant pool references.
1569 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1570 (ins addrmode_imm12:$addr),
1571 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1572 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1575 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1576 let Inst{19-16} = addr{16-13}; // Rn
1577 let Inst{15-12} = Rt;
1578 let Inst{11-0} = addr{11-0}; // imm12
1580 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1581 (ins ldst_so_reg:$shift),
1582 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1583 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1586 let shift{4} = 0; // Inst{4} = 0
1587 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1588 let Inst{19-16} = shift{16-13}; // Rn
1589 let Inst{15-12} = Rt;
1590 let Inst{11-0} = shift{11-0};
1596 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1597 InstrItinClass iir, PatFrag opnode> {
1598 // Note: We use the complex addrmode_imm12 rather than just an input
1599 // GPR and a constrained immediate so that we can use this to match
1600 // frame index references and avoid matching constant pool references.
1601 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1602 (ins GPR:$Rt, addrmode_imm12:$addr),
1603 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1604 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1607 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1608 let Inst{19-16} = addr{16-13}; // Rn
1609 let Inst{15-12} = Rt;
1610 let Inst{11-0} = addr{11-0}; // imm12
1612 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1613 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1614 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1617 let shift{4} = 0; // Inst{4} = 0
1618 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1619 let Inst{19-16} = shift{16-13}; // Rn
1620 let Inst{15-12} = Rt;
1621 let Inst{11-0} = shift{11-0};
1625 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1626 InstrItinClass iir, PatFrag opnode> {
1627 // Note: We use the complex addrmode_imm12 rather than just an input
1628 // GPR and a constrained immediate so that we can use this to match
1629 // frame index references and avoid matching constant pool references.
1630 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1631 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1632 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1633 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1636 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1637 let Inst{19-16} = addr{16-13}; // Rn
1638 let Inst{15-12} = Rt;
1639 let Inst{11-0} = addr{11-0}; // imm12
1641 def rs : AI2ldst<0b011, 0, isByte, (outs),
1642 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1643 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1644 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1647 let shift{4} = 0; // Inst{4} = 0
1648 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1649 let Inst{19-16} = shift{16-13}; // Rn
1650 let Inst{15-12} = Rt;
1651 let Inst{11-0} = shift{11-0};
1656 //===----------------------------------------------------------------------===//
1658 //===----------------------------------------------------------------------===//
1660 //===----------------------------------------------------------------------===//
1661 // Miscellaneous Instructions.
1664 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1665 /// the function. The first operand is the ID# for this instruction, the second
1666 /// is the index into the MachineConstantPool that this is, the third is the
1667 /// size in bytes of this constant pool entry.
1668 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1669 def CONSTPOOL_ENTRY :
1670 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1671 i32imm:$size), NoItinerary, []>;
1673 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1674 // from removing one half of the matched pairs. That breaks PEI, which assumes
1675 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1676 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1677 def ADJCALLSTACKUP :
1678 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1679 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1681 def ADJCALLSTACKDOWN :
1682 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1683 [(ARMcallseq_start timm:$amt)]>;
1686 def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary,
1687 "hint", "\t$imm", []>, Requires<[IsARM, HasV6]> {
1689 let Inst{27-8} = 0b00110010000011110000;
1690 let Inst{7-0} = imm;
1693 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1694 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1695 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1696 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1697 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1698 def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
1700 def : Pat<(int_arm_sevl), (HINT 5)>;
1702 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1703 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1708 let Inst{15-12} = Rd;
1709 let Inst{19-16} = Rn;
1710 let Inst{27-20} = 0b01101000;
1711 let Inst{7-4} = 0b1011;
1712 let Inst{11-8} = 0b1111;
1713 let Unpredictable{11-8} = 0b1111;
1716 // The 16-bit operand $val can be used by a debugger to store more information
1717 // about the breakpoint.
1718 def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1719 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1721 let Inst{3-0} = val{3-0};
1722 let Inst{19-8} = val{15-4};
1723 let Inst{27-20} = 0b00010010;
1724 let Inst{31-28} = 0xe; // AL
1725 let Inst{7-4} = 0b0111;
1728 def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1729 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> {
1731 let Inst{3-0} = val{3-0};
1732 let Inst{19-8} = val{15-4};
1733 let Inst{27-20} = 0b00010000;
1734 let Inst{31-28} = 0xe; // AL
1735 let Inst{7-4} = 0b0111;
1738 // Change Processor State
1739 // FIXME: We should use InstAlias to handle the optional operands.
1740 class CPS<dag iops, string asm_ops>
1741 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1742 []>, Requires<[IsARM]> {
1748 let Inst{31-28} = 0b1111;
1749 let Inst{27-20} = 0b00010000;
1750 let Inst{19-18} = imod;
1751 let Inst{17} = M; // Enabled if mode is set;
1752 let Inst{16-9} = 0b00000000;
1753 let Inst{8-6} = iflags;
1755 let Inst{4-0} = mode;
1758 let DecoderMethod = "DecodeCPSInstruction" in {
1760 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1761 "$imod\t$iflags, $mode">;
1762 let mode = 0, M = 0 in
1763 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1765 let imod = 0, iflags = 0, M = 1 in
1766 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1769 // Preload signals the memory system of possible future data/instruction access.
1770 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1772 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1773 !strconcat(opc, "\t$addr"),
1774 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>,
1775 Sched<[WritePreLd]> {
1778 let Inst{31-26} = 0b111101;
1779 let Inst{25} = 0; // 0 for immediate form
1780 let Inst{24} = data;
1781 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1782 let Inst{22} = read;
1783 let Inst{21-20} = 0b01;
1784 let Inst{19-16} = addr{16-13}; // Rn
1785 let Inst{15-12} = 0b1111;
1786 let Inst{11-0} = addr{11-0}; // imm12
1789 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1790 !strconcat(opc, "\t$shift"),
1791 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>,
1792 Sched<[WritePreLd]> {
1794 let Inst{31-26} = 0b111101;
1795 let Inst{25} = 1; // 1 for register form
1796 let Inst{24} = data;
1797 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1798 let Inst{22} = read;
1799 let Inst{21-20} = 0b01;
1800 let Inst{19-16} = shift{16-13}; // Rn
1801 let Inst{15-12} = 0b1111;
1802 let Inst{11-0} = shift{11-0};
1807 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1808 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1809 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1811 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1812 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> {
1814 let Inst{31-10} = 0b1111000100000001000000;
1819 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1820 []>, Requires<[IsARM, HasV7]> {
1822 let Inst{27-4} = 0b001100100000111100001111;
1823 let Inst{3-0} = opt;
1827 * A5.4 Permanently UNDEFINED instructions.
1829 * For most targets use UDF #65006, for which the OS will generate SIGTRAP.
1830 * Other UDF encodings generate SIGILL.
1832 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
1834 * 1110 0111 1111 iiii iiii iiii 1111 iiii
1836 * 1101 1110 iiii iiii
1837 * It uses the following encoding:
1838 * 1110 0111 1111 1110 1101 1110 1111 0000
1839 * - In ARM: UDF #60896;
1840 * - In Thumb: UDF #254 followed by a branch-to-self.
1842 let isBarrier = 1, isTerminator = 1 in
1843 def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
1845 Requires<[IsARM,UseNaClTrap]> {
1846 let Inst = 0xe7fedef0;
1848 let isBarrier = 1, isTerminator = 1 in
1849 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1851 Requires<[IsARM,DontUseNaClTrap]> {
1852 let Inst = 0xe7ffdefe;
1855 // Address computation and loads and stores in PIC mode.
1856 let isNotDuplicable = 1 in {
1857 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1859 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
1860 Sched<[WriteALU, ReadALU]>;
1862 let AddedComplexity = 10 in {
1863 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1865 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1867 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1869 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1871 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1873 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1875 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1877 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1879 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1881 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1883 let AddedComplexity = 10 in {
1884 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1885 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1887 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1888 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1889 addrmodepc:$addr)]>;
1891 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1892 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1894 } // isNotDuplicable = 1
1897 // LEApcrel - Load a pc-relative address into a register without offending the
1899 let neverHasSideEffects = 1, isReMaterializable = 1 in
1900 // The 'adr' mnemonic encodes differently if the label is before or after
1901 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1902 // know until then which form of the instruction will be used.
1903 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1904 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
1905 Sched<[WriteALU, ReadALU]> {
1908 let Inst{27-25} = 0b001;
1910 let Inst{23-22} = label{13-12};
1913 let Inst{19-16} = 0b1111;
1914 let Inst{15-12} = Rd;
1915 let Inst{11-0} = label{11-0};
1918 let hasSideEffects = 1 in {
1919 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1920 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1922 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1923 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1924 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1927 //===----------------------------------------------------------------------===//
1928 // Control Flow Instructions.
1931 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1933 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1934 "bx", "\tlr", [(ARMretflag)]>,
1935 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
1936 let Inst{27-0} = 0b0001001011111111111100011110;
1940 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1941 "mov", "\tpc, lr", [(ARMretflag)]>,
1942 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> {
1943 let Inst{27-0} = 0b0001101000001111000000001110;
1946 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets
1947 // the user-space one).
1948 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p),
1950 [(ARMintretflag imm:$offset)]>;
1953 // Indirect branches
1954 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1956 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1957 [(brind GPR:$dst)]>,
1958 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
1960 let Inst{31-4} = 0b1110000100101111111111110001;
1961 let Inst{3-0} = dst;
1964 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1965 "bx", "\t$dst", [/* pattern left blank */]>,
1966 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
1968 let Inst{27-4} = 0b000100101111111111110001;
1969 let Inst{3-0} = dst;
1973 // SP is marked as a use to prevent stack-pointer assignments that appear
1974 // immediately before calls from potentially appearing dead.
1976 // FIXME: Do we really need a non-predicated version? If so, it should
1977 // at least be a pseudo instruction expanding to the predicated version
1978 // at MC lowering time.
1979 Defs = [LR], Uses = [SP] in {
1980 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
1981 IIC_Br, "bl\t$func",
1982 [(ARMcall tglobaladdr:$func)]>,
1983 Requires<[IsARM]>, Sched<[WriteBrL]> {
1984 let Inst{31-28} = 0b1110;
1986 let Inst{23-0} = func;
1987 let DecoderMethod = "DecodeBranchImmInstruction";
1990 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
1991 IIC_Br, "bl", "\t$func",
1992 [(ARMcall_pred tglobaladdr:$func)]>,
1993 Requires<[IsARM]>, Sched<[WriteBrL]> {
1995 let Inst{23-0} = func;
1996 let DecoderMethod = "DecodeBranchImmInstruction";
2000 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
2001 IIC_Br, "blx\t$func",
2002 [(ARMcall GPR:$func)]>,
2003 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2005 let Inst{31-4} = 0b1110000100101111111111110011;
2006 let Inst{3-0} = func;
2009 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
2010 IIC_Br, "blx", "\t$func",
2011 [(ARMcall_pred GPR:$func)]>,
2012 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2014 let Inst{27-4} = 0b000100101111111111110011;
2015 let Inst{3-0} = func;
2019 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
2020 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2021 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2022 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>;
2025 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2026 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2027 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
2029 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
2030 // return stack predictor.
2031 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
2032 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
2033 Requires<[IsARM]>, Sched<[WriteBr]>;
2036 let isBranch = 1, isTerminator = 1 in {
2037 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2038 // a two-value operand where a dag node expects two operands. :(
2039 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2040 IIC_Br, "b", "\t$target",
2041 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>,
2044 let Inst{23-0} = target;
2045 let DecoderMethod = "DecodeBranchImmInstruction";
2048 let isBarrier = 1 in {
2049 // B is "predicable" since it's just a Bcc with an 'always' condition.
2050 let isPredicable = 1 in
2051 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2052 // should be sufficient.
2053 // FIXME: Is B really a Barrier? That doesn't seem right.
2054 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2055 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>,
2058 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2059 def BR_JTr : ARMPseudoInst<(outs),
2060 (ins GPR:$target, i32imm:$jt, i32imm:$id),
2062 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>,
2064 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2065 // into i12 and rs suffixed versions.
2066 def BR_JTm : ARMPseudoInst<(outs),
2067 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
2069 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
2070 imm:$id)]>, Sched<[WriteBrTbl]>;
2071 def BR_JTadd : ARMPseudoInst<(outs),
2072 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
2074 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
2075 imm:$id)]>, Sched<[WriteBrTbl]>;
2076 } // isNotDuplicable = 1, isIndirectBranch = 1
2082 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2083 "blx\t$target", []>,
2084 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2085 let Inst{31-25} = 0b1111101;
2087 let Inst{23-0} = target{24-1};
2088 let Inst{24} = target{0};
2091 // Branch and Exchange Jazelle
2092 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2093 [/* pattern left blank */]>, Sched<[WriteBr]> {
2095 let Inst{23-20} = 0b0010;
2096 let Inst{19-8} = 0xfff;
2097 let Inst{7-4} = 0b0010;
2098 let Inst{3-0} = func;
2103 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
2104 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>,
2107 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>,
2110 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
2112 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2113 Requires<[IsARM]>, Sched<[WriteBr]>;
2115 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
2117 (BX GPR:$dst)>, Sched<[WriteBr]>,
2121 // Secure Monitor Call is a system instruction.
2122 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2123 []>, Requires<[IsARM, HasTrustZone]> {
2125 let Inst{23-4} = 0b01100000000000000111;
2126 let Inst{3-0} = opt;
2129 // Supervisor Call (Software Interrupt)
2130 let isCall = 1, Uses = [SP] in {
2131 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>,
2134 let Inst{23-0} = svc;
2138 // Store Return State
2139 class SRSI<bit wb, string asm>
2140 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2141 NoItinerary, asm, "", []> {
2143 let Inst{31-28} = 0b1111;
2144 let Inst{27-25} = 0b100;
2148 let Inst{19-16} = 0b1101; // SP
2149 let Inst{15-5} = 0b00000101000;
2150 let Inst{4-0} = mode;
2153 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2154 let Inst{24-23} = 0;
2156 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2157 let Inst{24-23} = 0;
2159 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2160 let Inst{24-23} = 0b10;
2162 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2163 let Inst{24-23} = 0b10;
2165 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2166 let Inst{24-23} = 0b01;
2168 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2169 let Inst{24-23} = 0b01;
2171 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2172 let Inst{24-23} = 0b11;
2174 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2175 let Inst{24-23} = 0b11;
2178 def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
2179 def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
2181 def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
2182 def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
2184 def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
2185 def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
2187 def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
2188 def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
2190 // Return From Exception
2191 class RFEI<bit wb, string asm>
2192 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2193 NoItinerary, asm, "", []> {
2195 let Inst{31-28} = 0b1111;
2196 let Inst{27-25} = 0b100;
2200 let Inst{19-16} = Rn;
2201 let Inst{15-0} = 0xa00;
2204 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2205 let Inst{24-23} = 0;
2207 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2208 let Inst{24-23} = 0;
2210 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2211 let Inst{24-23} = 0b10;
2213 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2214 let Inst{24-23} = 0b10;
2216 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2217 let Inst{24-23} = 0b01;
2219 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2220 let Inst{24-23} = 0b01;
2222 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2223 let Inst{24-23} = 0b11;
2225 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2226 let Inst{24-23} = 0b11;
2229 //===----------------------------------------------------------------------===//
2230 // Load / Store Instructions.
2236 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2237 UnOpFrag<(load node:$Src)>>;
2238 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2239 UnOpFrag<(zextloadi8 node:$Src)>>;
2240 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2241 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2242 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2243 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2245 // Special LDR for loads from non-pc-relative constpools.
2246 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2247 isReMaterializable = 1, isCodeGenOnly = 1 in
2248 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2249 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2253 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2254 let Inst{19-16} = 0b1111;
2255 let Inst{15-12} = Rt;
2256 let Inst{11-0} = addr{11-0}; // imm12
2259 // Loads with zero extension
2260 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2261 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2262 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2264 // Loads with sign extension
2265 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2266 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2267 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2269 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2270 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2271 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2273 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2275 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2276 (ins addrmode3:$addr), LdMiscFrm,
2277 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2278 []>, Requires<[IsARM, HasV5TE]>;
2281 def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2282 NoItinerary, "lda", "\t$Rt, $addr", []>;
2283 def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2284 NoItinerary, "ldab", "\t$Rt, $addr", []>;
2285 def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2286 NoItinerary, "ldah", "\t$Rt, $addr", []>;
2289 multiclass AI2_ldridx<bit isByte, string opc,
2290 InstrItinClass iii, InstrItinClass iir> {
2291 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2292 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii,
2293 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2296 let Inst{23} = addr{12};
2297 let Inst{19-16} = addr{16-13};
2298 let Inst{11-0} = addr{11-0};
2299 let DecoderMethod = "DecodeLDRPreImm";
2302 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2303 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2304 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2307 let Inst{23} = addr{12};
2308 let Inst{19-16} = addr{16-13};
2309 let Inst{11-0} = addr{11-0};
2311 let DecoderMethod = "DecodeLDRPreReg";
2314 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2315 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2316 IndexModePost, LdFrm, iir,
2317 opc, "\t$Rt, $addr, $offset",
2318 "$addr.base = $Rn_wb", []> {
2324 let Inst{23} = offset{12};
2325 let Inst{19-16} = addr;
2326 let Inst{11-0} = offset{11-0};
2329 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2332 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2333 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2334 IndexModePost, LdFrm, iii,
2335 opc, "\t$Rt, $addr, $offset",
2336 "$addr.base = $Rn_wb", []> {
2342 let Inst{23} = offset{12};
2343 let Inst{19-16} = addr;
2344 let Inst{11-0} = offset{11-0};
2346 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2351 let mayLoad = 1, neverHasSideEffects = 1 in {
2352 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2353 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2354 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2355 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2358 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2359 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2360 (ins addrmode3_pre:$addr), IndexModePre,
2362 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2364 let Inst{23} = addr{8}; // U bit
2365 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2366 let Inst{19-16} = addr{12-9}; // Rn
2367 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2368 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2369 let DecoderMethod = "DecodeAddrMode3Instruction";
2371 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2372 (ins addr_offset_none:$addr, am3offset:$offset),
2373 IndexModePost, LdMiscFrm, itin,
2374 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2378 let Inst{23} = offset{8}; // U bit
2379 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2380 let Inst{19-16} = addr;
2381 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2382 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2383 let DecoderMethod = "DecodeAddrMode3Instruction";
2387 let mayLoad = 1, neverHasSideEffects = 1 in {
2388 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2389 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2390 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2391 let hasExtraDefRegAllocReq = 1 in {
2392 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2393 (ins addrmode3_pre:$addr), IndexModePre,
2394 LdMiscFrm, IIC_iLoad_d_ru,
2395 "ldrd", "\t$Rt, $Rt2, $addr!",
2396 "$addr.base = $Rn_wb", []> {
2398 let Inst{23} = addr{8}; // U bit
2399 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2400 let Inst{19-16} = addr{12-9}; // Rn
2401 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2402 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2403 let DecoderMethod = "DecodeAddrMode3Instruction";
2405 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2406 (ins addr_offset_none:$addr, am3offset:$offset),
2407 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2408 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2409 "$addr.base = $Rn_wb", []> {
2412 let Inst{23} = offset{8}; // U bit
2413 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2414 let Inst{19-16} = addr;
2415 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2416 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2417 let DecoderMethod = "DecodeAddrMode3Instruction";
2419 } // hasExtraDefRegAllocReq = 1
2420 } // mayLoad = 1, neverHasSideEffects = 1
2422 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2423 let mayLoad = 1, neverHasSideEffects = 1 in {
2424 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2425 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2426 IndexModePost, LdFrm, IIC_iLoad_ru,
2427 "ldrt", "\t$Rt, $addr, $offset",
2428 "$addr.base = $Rn_wb", []> {
2434 let Inst{23} = offset{12};
2435 let Inst{21} = 1; // overwrite
2436 let Inst{19-16} = addr;
2437 let Inst{11-5} = offset{11-5};
2439 let Inst{3-0} = offset{3-0};
2440 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2443 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2444 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2445 IndexModePost, LdFrm, IIC_iLoad_ru,
2446 "ldrt", "\t$Rt, $addr, $offset",
2447 "$addr.base = $Rn_wb", []> {
2453 let Inst{23} = offset{12};
2454 let Inst{21} = 1; // overwrite
2455 let Inst{19-16} = addr;
2456 let Inst{11-0} = offset{11-0};
2457 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2460 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2461 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2462 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2463 "ldrbt", "\t$Rt, $addr, $offset",
2464 "$addr.base = $Rn_wb", []> {
2470 let Inst{23} = offset{12};
2471 let Inst{21} = 1; // overwrite
2472 let Inst{19-16} = addr;
2473 let Inst{11-5} = offset{11-5};
2475 let Inst{3-0} = offset{3-0};
2476 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2479 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2480 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2481 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2482 "ldrbt", "\t$Rt, $addr, $offset",
2483 "$addr.base = $Rn_wb", []> {
2489 let Inst{23} = offset{12};
2490 let Inst{21} = 1; // overwrite
2491 let Inst{19-16} = addr;
2492 let Inst{11-0} = offset{11-0};
2493 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2496 multiclass AI3ldrT<bits<4> op, string opc> {
2497 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2498 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2499 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2500 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2502 let Inst{23} = offset{8};
2504 let Inst{11-8} = offset{7-4};
2505 let Inst{3-0} = offset{3-0};
2507 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2508 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2509 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2510 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2512 let Inst{23} = Rm{4};
2515 let Unpredictable{11-8} = 0b1111;
2516 let Inst{3-0} = Rm{3-0};
2517 let DecoderMethod = "DecodeLDR";
2521 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2522 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2523 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2528 // Stores with truncate
2529 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2530 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2531 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2534 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2535 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2536 StMiscFrm, IIC_iStore_d_r,
2537 "strd", "\t$Rt, $src2, $addr", []>,
2538 Requires<[IsARM, HasV5TE]> {
2543 multiclass AI2_stridx<bit isByte, string opc,
2544 InstrItinClass iii, InstrItinClass iir> {
2545 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2546 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
2548 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2551 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2552 let Inst{19-16} = addr{16-13}; // Rn
2553 let Inst{11-0} = addr{11-0}; // imm12
2554 let DecoderMethod = "DecodeSTRPreImm";
2557 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2558 (ins GPR:$Rt, ldst_so_reg:$addr),
2559 IndexModePre, StFrm, iir,
2560 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2563 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2564 let Inst{19-16} = addr{16-13}; // Rn
2565 let Inst{11-0} = addr{11-0};
2566 let Inst{4} = 0; // Inst{4} = 0
2567 let DecoderMethod = "DecodeSTRPreReg";
2569 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2570 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2571 IndexModePost, StFrm, iir,
2572 opc, "\t$Rt, $addr, $offset",
2573 "$addr.base = $Rn_wb", []> {
2579 let Inst{23} = offset{12};
2580 let Inst{19-16} = addr;
2581 let Inst{11-0} = offset{11-0};
2584 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2587 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2588 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2589 IndexModePost, StFrm, iii,
2590 opc, "\t$Rt, $addr, $offset",
2591 "$addr.base = $Rn_wb", []> {
2597 let Inst{23} = offset{12};
2598 let Inst{19-16} = addr;
2599 let Inst{11-0} = offset{11-0};
2601 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2605 let mayStore = 1, neverHasSideEffects = 1 in {
2606 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2607 // IIC_iStore_siu depending on whether it the offset register is shifted.
2608 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2609 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2612 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2613 am2offset_reg:$offset),
2614 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2615 am2offset_reg:$offset)>;
2616 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2617 am2offset_imm:$offset),
2618 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2619 am2offset_imm:$offset)>;
2620 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2621 am2offset_reg:$offset),
2622 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2623 am2offset_reg:$offset)>;
2624 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2625 am2offset_imm:$offset),
2626 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2627 am2offset_imm:$offset)>;
2629 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2630 // put the patterns on the instruction definitions directly as ISel wants
2631 // the address base and offset to be separate operands, not a single
2632 // complex operand like we represent the instructions themselves. The
2633 // pseudos map between the two.
2634 let usesCustomInserter = 1,
2635 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2636 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2637 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2640 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2641 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2642 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2645 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2646 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2647 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2650 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2651 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2652 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2655 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2656 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2657 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2660 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2665 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2666 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
2667 StMiscFrm, IIC_iStore_bh_ru,
2668 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2670 let Inst{23} = addr{8}; // U bit
2671 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2672 let Inst{19-16} = addr{12-9}; // Rn
2673 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2674 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2675 let DecoderMethod = "DecodeAddrMode3Instruction";
2678 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2679 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2680 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2681 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2682 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2683 addr_offset_none:$addr,
2684 am3offset:$offset))]> {
2687 let Inst{23} = offset{8}; // U bit
2688 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2689 let Inst{19-16} = addr;
2690 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2691 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2692 let DecoderMethod = "DecodeAddrMode3Instruction";
2695 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2696 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2697 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
2698 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2699 "strd", "\t$Rt, $Rt2, $addr!",
2700 "$addr.base = $Rn_wb", []> {
2702 let Inst{23} = addr{8}; // U bit
2703 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2704 let Inst{19-16} = addr{12-9}; // Rn
2705 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2706 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2707 let DecoderMethod = "DecodeAddrMode3Instruction";
2710 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2711 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2713 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2714 "strd", "\t$Rt, $Rt2, $addr, $offset",
2715 "$addr.base = $Rn_wb", []> {
2718 let Inst{23} = offset{8}; // U bit
2719 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2720 let Inst{19-16} = addr;
2721 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2722 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2723 let DecoderMethod = "DecodeAddrMode3Instruction";
2725 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2727 // STRT, STRBT, and STRHT
2729 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2730 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2731 IndexModePost, StFrm, IIC_iStore_bh_ru,
2732 "strbt", "\t$Rt, $addr, $offset",
2733 "$addr.base = $Rn_wb", []> {
2739 let Inst{23} = offset{12};
2740 let Inst{21} = 1; // overwrite
2741 let Inst{19-16} = addr;
2742 let Inst{11-5} = offset{11-5};
2744 let Inst{3-0} = offset{3-0};
2745 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2748 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2749 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2750 IndexModePost, StFrm, IIC_iStore_bh_ru,
2751 "strbt", "\t$Rt, $addr, $offset",
2752 "$addr.base = $Rn_wb", []> {
2758 let Inst{23} = offset{12};
2759 let Inst{21} = 1; // overwrite
2760 let Inst{19-16} = addr;
2761 let Inst{11-0} = offset{11-0};
2762 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2765 let mayStore = 1, neverHasSideEffects = 1 in {
2766 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2767 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2768 IndexModePost, StFrm, IIC_iStore_ru,
2769 "strt", "\t$Rt, $addr, $offset",
2770 "$addr.base = $Rn_wb", []> {
2776 let Inst{23} = offset{12};
2777 let Inst{21} = 1; // overwrite
2778 let Inst{19-16} = addr;
2779 let Inst{11-5} = offset{11-5};
2781 let Inst{3-0} = offset{3-0};
2782 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2785 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2786 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2787 IndexModePost, StFrm, IIC_iStore_ru,
2788 "strt", "\t$Rt, $addr, $offset",
2789 "$addr.base = $Rn_wb", []> {
2795 let Inst{23} = offset{12};
2796 let Inst{21} = 1; // overwrite
2797 let Inst{19-16} = addr;
2798 let Inst{11-0} = offset{11-0};
2799 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2804 multiclass AI3strT<bits<4> op, string opc> {
2805 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2806 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2807 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2808 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2810 let Inst{23} = offset{8};
2812 let Inst{11-8} = offset{7-4};
2813 let Inst{3-0} = offset{3-0};
2815 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2816 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2817 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2818 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2820 let Inst{23} = Rm{4};
2823 let Inst{3-0} = Rm{3-0};
2828 defm STRHT : AI3strT<0b1011, "strht">;
2830 def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
2831 NoItinerary, "stl", "\t$Rt, $addr", []>;
2832 def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
2833 NoItinerary, "stlb", "\t$Rt, $addr", []>;
2834 def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
2835 NoItinerary, "stlh", "\t$Rt, $addr", []>;
2837 //===----------------------------------------------------------------------===//
2838 // Load / store multiple Instructions.
2841 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
2842 InstrItinClass itin, InstrItinClass itin_upd> {
2843 // IA is the default, so no need for an explicit suffix on the
2844 // mnemonic here. Without it is the canonical spelling.
2846 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2847 IndexModeNone, f, itin,
2848 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
2849 let Inst{24-23} = 0b01; // Increment After
2850 let Inst{22} = P_bit;
2851 let Inst{21} = 0; // No writeback
2852 let Inst{20} = L_bit;
2855 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2856 IndexModeUpd, f, itin_upd,
2857 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2858 let Inst{24-23} = 0b01; // Increment After
2859 let Inst{22} = P_bit;
2860 let Inst{21} = 1; // Writeback
2861 let Inst{20} = L_bit;
2863 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2866 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2867 IndexModeNone, f, itin,
2868 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
2869 let Inst{24-23} = 0b00; // Decrement After
2870 let Inst{22} = P_bit;
2871 let Inst{21} = 0; // No writeback
2872 let Inst{20} = L_bit;
2875 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2876 IndexModeUpd, f, itin_upd,
2877 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2878 let Inst{24-23} = 0b00; // Decrement After
2879 let Inst{22} = P_bit;
2880 let Inst{21} = 1; // Writeback
2881 let Inst{20} = L_bit;
2883 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2886 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2887 IndexModeNone, f, itin,
2888 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
2889 let Inst{24-23} = 0b10; // Decrement Before
2890 let Inst{22} = P_bit;
2891 let Inst{21} = 0; // No writeback
2892 let Inst{20} = L_bit;
2895 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2896 IndexModeUpd, f, itin_upd,
2897 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2898 let Inst{24-23} = 0b10; // Decrement Before
2899 let Inst{22} = P_bit;
2900 let Inst{21} = 1; // Writeback
2901 let Inst{20} = L_bit;
2903 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2906 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2907 IndexModeNone, f, itin,
2908 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
2909 let Inst{24-23} = 0b11; // Increment Before
2910 let Inst{22} = P_bit;
2911 let Inst{21} = 0; // No writeback
2912 let Inst{20} = L_bit;
2915 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2916 IndexModeUpd, f, itin_upd,
2917 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2918 let Inst{24-23} = 0b11; // Increment Before
2919 let Inst{22} = P_bit;
2920 let Inst{21} = 1; // Writeback
2921 let Inst{20} = L_bit;
2923 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2927 let neverHasSideEffects = 1 in {
2929 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2930 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
2933 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2934 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
2937 } // neverHasSideEffects
2939 // FIXME: remove when we have a way to marking a MI with these properties.
2940 // FIXME: Should pc be an implicit operand like PICADD, etc?
2941 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2942 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2943 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2944 reglist:$regs, variable_ops),
2945 4, IIC_iLoad_mBr, [],
2946 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2947 RegConstraint<"$Rn = $wb">;
2949 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2950 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
2953 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2954 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
2959 //===----------------------------------------------------------------------===//
2960 // Move Instructions.
2963 let neverHasSideEffects = 1 in
2964 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2965 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
2969 let Inst{19-16} = 0b0000;
2970 let Inst{11-4} = 0b00000000;
2973 let Inst{15-12} = Rd;
2976 // A version for the smaller set of tail call registers.
2977 let neverHasSideEffects = 1 in
2978 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2979 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
2983 let Inst{11-4} = 0b00000000;
2986 let Inst{15-12} = Rd;
2989 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2990 DPSoRegRegFrm, IIC_iMOVsr,
2991 "mov", "\t$Rd, $src",
2992 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
2996 let Inst{15-12} = Rd;
2997 let Inst{19-16} = 0b0000;
2998 let Inst{11-8} = src{11-8};
3000 let Inst{6-5} = src{6-5};
3002 let Inst{3-0} = src{3-0};
3006 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3007 DPSoRegImmFrm, IIC_iMOVsr,
3008 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
3009 UnaryDP, Sched<[WriteALU]> {
3012 let Inst{15-12} = Rd;
3013 let Inst{19-16} = 0b0000;
3014 let Inst{11-5} = src{11-5};
3016 let Inst{3-0} = src{3-0};
3020 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3021 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
3022 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP,
3027 let Inst{15-12} = Rd;
3028 let Inst{19-16} = 0b0000;
3029 let Inst{11-0} = imm;
3032 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3033 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3035 "movw", "\t$Rd, $imm",
3036 [(set GPR:$Rd, imm0_65535:$imm)]>,
3037 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
3040 let Inst{15-12} = Rd;
3041 let Inst{11-0} = imm{11-0};
3042 let Inst{19-16} = imm{15-12};
3045 let DecoderMethod = "DecodeArmMOVTWInstruction";
3048 def : InstAlias<"mov${p} $Rd, $imm",
3049 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3052 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3053 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3056 let Constraints = "$src = $Rd" in {
3057 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3058 (ins GPR:$src, imm0_65535_expr:$imm),
3060 "movt", "\t$Rd, $imm",
3062 (or (and GPR:$src, 0xffff),
3063 lo16AllZero:$imm))]>, UnaryDP,
3064 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
3067 let Inst{15-12} = Rd;
3068 let Inst{11-0} = imm{11-0};
3069 let Inst{19-16} = imm{15-12};
3072 let DecoderMethod = "DecodeArmMOVTWInstruction";
3075 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3076 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3081 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3082 Requires<[IsARM, HasV6T2]>;
3084 let Uses = [CPSR] in
3085 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3086 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3087 Requires<[IsARM]>, Sched<[WriteALU]>;
3089 // These aren't really mov instructions, but we have to define them this way
3090 // due to flag operands.
3092 let Defs = [CPSR] in {
3093 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3094 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3095 Sched<[WriteALU]>, Requires<[IsARM]>;
3096 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3097 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3098 Sched<[WriteALU]>, Requires<[IsARM]>;
3101 //===----------------------------------------------------------------------===//
3102 // Extend Instructions.
3107 def SXTB : AI_ext_rrot<0b01101010,
3108 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3109 def SXTH : AI_ext_rrot<0b01101011,
3110 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3112 def SXTAB : AI_exta_rrot<0b01101010,
3113 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3114 def SXTAH : AI_exta_rrot<0b01101011,
3115 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3117 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3119 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3123 let AddedComplexity = 16 in {
3124 def UXTB : AI_ext_rrot<0b01101110,
3125 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3126 def UXTH : AI_ext_rrot<0b01101111,
3127 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3128 def UXTB16 : AI_ext_rrot<0b01101100,
3129 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3131 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3132 // The transformation should probably be done as a combiner action
3133 // instead so we can include a check for masking back in the upper
3134 // eight bits of the source into the lower eight bits of the result.
3135 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3136 // (UXTB16r_rot GPR:$Src, 3)>;
3137 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3138 (UXTB16 GPR:$Src, 1)>;
3140 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3141 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3142 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3143 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3146 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3147 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3150 def SBFX : I<(outs GPRnopc:$Rd),
3151 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3152 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3153 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3154 Requires<[IsARM, HasV6T2]> {
3159 let Inst{27-21} = 0b0111101;
3160 let Inst{6-4} = 0b101;
3161 let Inst{20-16} = width;
3162 let Inst{15-12} = Rd;
3163 let Inst{11-7} = lsb;
3167 def UBFX : I<(outs GPR:$Rd),
3168 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3169 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3170 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3171 Requires<[IsARM, HasV6T2]> {
3176 let Inst{27-21} = 0b0111111;
3177 let Inst{6-4} = 0b101;
3178 let Inst{20-16} = width;
3179 let Inst{15-12} = Rd;
3180 let Inst{11-7} = lsb;
3184 //===----------------------------------------------------------------------===//
3185 // Arithmetic Instructions.
3188 defm ADD : AsI1_bin_irs<0b0100, "add",
3189 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3190 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3191 defm SUB : AsI1_bin_irs<0b0010, "sub",
3192 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3193 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3195 // ADD and SUB with 's' bit set.
3197 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3198 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3199 // AdjustInstrPostInstrSelection where we determine whether or not to
3200 // set the "s" bit based on CPSR liveness.
3202 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3203 // support for an optional CPSR definition that corresponds to the DAG
3204 // node's second value. We can then eliminate the implicit def of CPSR.
3205 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3206 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3207 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3208 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3210 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3211 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3212 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3213 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3215 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3216 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3217 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3219 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3220 // CPSR and the implicit def of CPSR is not needed.
3221 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3222 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3224 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3225 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3227 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3228 // The assume-no-carry-in form uses the negation of the input since add/sub
3229 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3230 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3232 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3233 (SUBri GPR:$src, so_imm_neg:$imm)>;
3234 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3235 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3237 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3238 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3239 Requires<[IsARM, HasV6T2]>;
3240 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3241 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3242 Requires<[IsARM, HasV6T2]>;
3244 // The with-carry-in form matches bitwise not instead of the negation.
3245 // Effectively, the inverse interpretation of the carry flag already accounts
3246 // for part of the negation.
3247 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3248 (SBCri GPR:$src, so_imm_not:$imm)>;
3249 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3250 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>;
3252 // Note: These are implemented in C++ code, because they have to generate
3253 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3255 // (mul X, 2^n+1) -> (add (X << n), X)
3256 // (mul X, 2^n-1) -> (rsb X, (X << n))
3258 // ARM Arithmetic Instruction
3259 // GPR:$dst = GPR:$a op GPR:$b
3260 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3261 list<dag> pattern = [],
3262 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3263 string asm = "\t$Rd, $Rn, $Rm">
3264 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
3265 Sched<[WriteALU, ReadALU, ReadALU]> {
3269 let Inst{27-20} = op27_20;
3270 let Inst{11-4} = op11_4;
3271 let Inst{19-16} = Rn;
3272 let Inst{15-12} = Rd;
3275 let Unpredictable{11-8} = 0b1111;
3278 // Saturating add/subtract
3280 let DecoderMethod = "DecodeQADDInstruction" in
3281 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3282 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3283 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3285 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3286 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3287 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3288 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3289 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3291 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3292 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3295 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3296 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3297 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3298 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3299 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3300 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3301 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3302 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3303 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3304 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3305 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3306 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3308 // Signed/Unsigned add/subtract
3310 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3311 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3312 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3313 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3314 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3315 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3316 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3317 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3318 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3319 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3320 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3321 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3323 // Signed/Unsigned halving add/subtract
3325 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3326 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3327 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3328 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3329 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3330 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3331 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3332 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3333 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3334 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3335 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3336 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3338 // Unsigned Sum of Absolute Differences [and Accumulate].
3340 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3341 MulFrm /* for convenience */, NoItinerary, "usad8",
3342 "\t$Rd, $Rn, $Rm", []>,
3343 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
3347 let Inst{27-20} = 0b01111000;
3348 let Inst{15-12} = 0b1111;
3349 let Inst{7-4} = 0b0001;
3350 let Inst{19-16} = Rd;
3351 let Inst{11-8} = Rm;
3354 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3355 MulFrm /* for convenience */, NoItinerary, "usada8",
3356 "\t$Rd, $Rn, $Rm, $Ra", []>,
3357 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
3362 let Inst{27-20} = 0b01111000;
3363 let Inst{7-4} = 0b0001;
3364 let Inst{19-16} = Rd;
3365 let Inst{15-12} = Ra;
3366 let Inst{11-8} = Rm;
3370 // Signed/Unsigned saturate
3372 def SSAT : AI<(outs GPRnopc:$Rd),
3373 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3374 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3379 let Inst{27-21} = 0b0110101;
3380 let Inst{5-4} = 0b01;
3381 let Inst{20-16} = sat_imm;
3382 let Inst{15-12} = Rd;
3383 let Inst{11-7} = sh{4-0};
3384 let Inst{6} = sh{5};
3388 def SSAT16 : AI<(outs GPRnopc:$Rd),
3389 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3390 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3394 let Inst{27-20} = 0b01101010;
3395 let Inst{11-4} = 0b11110011;
3396 let Inst{15-12} = Rd;
3397 let Inst{19-16} = sat_imm;
3401 def USAT : AI<(outs GPRnopc:$Rd),
3402 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3403 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3408 let Inst{27-21} = 0b0110111;
3409 let Inst{5-4} = 0b01;
3410 let Inst{15-12} = Rd;
3411 let Inst{11-7} = sh{4-0};
3412 let Inst{6} = sh{5};
3413 let Inst{20-16} = sat_imm;
3417 def USAT16 : AI<(outs GPRnopc:$Rd),
3418 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3419 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3423 let Inst{27-20} = 0b01101110;
3424 let Inst{11-4} = 0b11110011;
3425 let Inst{15-12} = Rd;
3426 let Inst{19-16} = sat_imm;
3430 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3431 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3432 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3433 (USAT imm:$pos, GPRnopc:$a, 0)>;
3435 //===----------------------------------------------------------------------===//
3436 // Bitwise Instructions.
3439 defm AND : AsI1_bin_irs<0b0000, "and",
3440 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3441 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3442 defm ORR : AsI1_bin_irs<0b1100, "orr",
3443 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3444 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3445 defm EOR : AsI1_bin_irs<0b0001, "eor",
3446 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3447 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3448 defm BIC : AsI1_bin_irs<0b1110, "bic",
3449 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3450 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3452 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3453 // like in the actual instruction encoding. The complexity of mapping the mask
3454 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3455 // instruction description.
3456 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3457 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3458 "bfc", "\t$Rd, $imm", "$src = $Rd",
3459 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3460 Requires<[IsARM, HasV6T2]> {
3463 let Inst{27-21} = 0b0111110;
3464 let Inst{6-0} = 0b0011111;
3465 let Inst{15-12} = Rd;
3466 let Inst{11-7} = imm{4-0}; // lsb
3467 let Inst{20-16} = imm{9-5}; // msb
3470 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3471 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3472 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3473 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3474 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3475 bf_inv_mask_imm:$imm))]>,
3476 Requires<[IsARM, HasV6T2]> {
3480 let Inst{27-21} = 0b0111110;
3481 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3482 let Inst{15-12} = Rd;
3483 let Inst{11-7} = imm{4-0}; // lsb
3484 let Inst{20-16} = imm{9-5}; // width
3488 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3489 "mvn", "\t$Rd, $Rm",
3490 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
3494 let Inst{19-16} = 0b0000;
3495 let Inst{11-4} = 0b00000000;
3496 let Inst{15-12} = Rd;
3499 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3500 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3501 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
3506 let Inst{19-16} = 0b0000;
3507 let Inst{15-12} = Rd;
3508 let Inst{11-5} = shift{11-5};
3510 let Inst{3-0} = shift{3-0};
3512 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3513 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3514 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
3519 let Inst{19-16} = 0b0000;
3520 let Inst{15-12} = Rd;
3521 let Inst{11-8} = shift{11-8};
3523 let Inst{6-5} = shift{6-5};
3525 let Inst{3-0} = shift{3-0};
3527 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3528 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3529 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3530 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
3534 let Inst{19-16} = 0b0000;
3535 let Inst{15-12} = Rd;
3536 let Inst{11-0} = imm;
3539 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3540 (BICri GPR:$src, so_imm_not:$imm)>;
3542 //===----------------------------------------------------------------------===//
3543 // Multiply Instructions.
3545 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3546 string opc, string asm, list<dag> pattern>
3547 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3551 let Inst{19-16} = Rd;
3552 let Inst{11-8} = Rm;
3555 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3556 string opc, string asm, list<dag> pattern>
3557 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3562 let Inst{19-16} = RdHi;
3563 let Inst{15-12} = RdLo;
3564 let Inst{11-8} = Rm;
3567 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3568 string opc, string asm, list<dag> pattern>
3569 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3574 let Inst{19-16} = RdHi;
3575 let Inst{15-12} = RdLo;
3576 let Inst{11-8} = Rm;
3580 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3581 // property. Remove them when it's possible to add those properties
3582 // on an individual MachineInstr, not just an instruction description.
3583 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3584 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3585 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3586 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3587 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3588 Requires<[IsARM, HasV6]> {
3589 let Inst{15-12} = 0b0000;
3590 let Unpredictable{15-12} = 0b1111;
3593 let Constraints = "@earlyclobber $Rd" in
3594 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3595 pred:$p, cc_out:$s),
3597 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3598 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3599 Requires<[IsARM, NoV6, UseMulOps]>;
3602 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3603 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3604 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3605 Requires<[IsARM, HasV6, UseMulOps]> {
3607 let Inst{15-12} = Ra;
3610 let Constraints = "@earlyclobber $Rd" in
3611 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3612 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3614 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3615 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3616 Requires<[IsARM, NoV6]>;
3618 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3619 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3620 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3621 Requires<[IsARM, HasV6T2, UseMulOps]> {
3626 let Inst{19-16} = Rd;
3627 let Inst{15-12} = Ra;
3628 let Inst{11-8} = Rm;
3632 // Extra precision multiplies with low / high results
3633 let neverHasSideEffects = 1 in {
3634 let isCommutable = 1 in {
3635 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3636 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3637 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3638 Requires<[IsARM, HasV6]>;
3640 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3641 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3642 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3643 Requires<[IsARM, HasV6]>;
3645 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3646 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3647 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3649 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3650 Requires<[IsARM, NoV6]>;
3652 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3653 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3655 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3656 Requires<[IsARM, NoV6]>;
3660 // Multiply + accumulate
3661 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3662 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3663 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3664 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3665 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3666 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3667 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3668 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3670 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3671 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3672 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3673 Requires<[IsARM, HasV6]> {
3678 let Inst{19-16} = RdHi;
3679 let Inst{15-12} = RdLo;
3680 let Inst{11-8} = Rm;
3684 let Constraints = "$RLo = $RdLo,$RHi = $RdHi" in {
3685 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3686 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3688 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3689 pred:$p, cc_out:$s)>,
3690 Requires<[IsARM, NoV6]>;
3691 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3692 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3694 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3695 pred:$p, cc_out:$s)>,
3696 Requires<[IsARM, NoV6]>;
3699 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3700 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3701 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3703 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3704 Requires<[IsARM, NoV6]>;
3707 } // neverHasSideEffects
3709 // Most significant word multiply
3710 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3711 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3712 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3713 Requires<[IsARM, HasV6]> {
3714 let Inst{15-12} = 0b1111;
3717 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3718 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3719 Requires<[IsARM, HasV6]> {
3720 let Inst{15-12} = 0b1111;
3723 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3724 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3725 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3726 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3727 Requires<[IsARM, HasV6, UseMulOps]>;
3729 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3730 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3731 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3732 Requires<[IsARM, HasV6]>;
3734 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3735 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3736 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3737 Requires<[IsARM, HasV6, UseMulOps]>;
3739 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3740 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3741 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3742 Requires<[IsARM, HasV6]>;
3744 multiclass AI_smul<string opc, PatFrag opnode> {
3745 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3746 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3747 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3748 (sext_inreg GPR:$Rm, i16)))]>,
3749 Requires<[IsARM, HasV5TE]>;
3751 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3752 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3753 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3754 (sra GPR:$Rm, (i32 16))))]>,
3755 Requires<[IsARM, HasV5TE]>;
3757 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3758 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3759 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3760 (sext_inreg GPR:$Rm, i16)))]>,
3761 Requires<[IsARM, HasV5TE]>;
3763 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3764 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3765 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3766 (sra GPR:$Rm, (i32 16))))]>,
3767 Requires<[IsARM, HasV5TE]>;
3769 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3770 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3771 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3772 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3773 Requires<[IsARM, HasV5TE]>;
3775 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3776 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3777 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3778 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3779 Requires<[IsARM, HasV5TE]>;
3783 multiclass AI_smla<string opc, PatFrag opnode> {
3784 let DecoderMethod = "DecodeSMLAInstruction" in {
3785 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3786 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3787 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3788 [(set GPRnopc:$Rd, (add GPR:$Ra,
3789 (opnode (sext_inreg GPRnopc:$Rn, i16),
3790 (sext_inreg GPRnopc:$Rm, i16))))]>,
3791 Requires<[IsARM, HasV5TE, UseMulOps]>;
3793 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3794 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3795 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3797 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3798 (sra GPRnopc:$Rm, (i32 16)))))]>,
3799 Requires<[IsARM, HasV5TE, UseMulOps]>;
3801 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3802 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3803 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3805 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3806 (sext_inreg GPRnopc:$Rm, i16))))]>,
3807 Requires<[IsARM, HasV5TE, UseMulOps]>;
3809 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3810 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3811 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3813 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3814 (sra GPRnopc:$Rm, (i32 16)))))]>,
3815 Requires<[IsARM, HasV5TE, UseMulOps]>;
3817 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3818 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3819 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3821 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3822 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3823 Requires<[IsARM, HasV5TE, UseMulOps]>;
3825 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3826 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3827 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3829 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3830 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3831 Requires<[IsARM, HasV5TE, UseMulOps]>;
3835 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3836 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3838 // Halfword multiply accumulate long: SMLAL<x><y>.
3839 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3840 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3841 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3842 Requires<[IsARM, HasV5TE]>;
3844 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3845 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3846 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3847 Requires<[IsARM, HasV5TE]>;
3849 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3850 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3851 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3852 Requires<[IsARM, HasV5TE]>;
3854 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3855 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3856 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3857 Requires<[IsARM, HasV5TE]>;
3859 // Helper class for AI_smld.
3860 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3861 InstrItinClass itin, string opc, string asm>
3862 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3865 let Inst{27-23} = 0b01110;
3866 let Inst{22} = long;
3867 let Inst{21-20} = 0b00;
3868 let Inst{11-8} = Rm;
3875 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3876 InstrItinClass itin, string opc, string asm>
3877 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3879 let Inst{15-12} = 0b1111;
3880 let Inst{19-16} = Rd;
3882 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3883 InstrItinClass itin, string opc, string asm>
3884 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3887 let Inst{19-16} = Rd;
3888 let Inst{15-12} = Ra;
3890 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3891 InstrItinClass itin, string opc, string asm>
3892 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3895 let Inst{19-16} = RdHi;
3896 let Inst{15-12} = RdLo;
3899 multiclass AI_smld<bit sub, string opc> {
3901 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3902 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3903 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3905 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3906 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3907 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3909 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3910 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3911 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3913 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3914 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3915 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3919 defm SMLA : AI_smld<0, "smla">;
3920 defm SMLS : AI_smld<1, "smls">;
3922 multiclass AI_sdml<bit sub, string opc> {
3924 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3925 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3926 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3927 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3930 defm SMUA : AI_sdml<0, "smua">;
3931 defm SMUS : AI_sdml<1, "smus">;
3933 //===----------------------------------------------------------------------===//
3934 // Division Instructions (ARMv7-A with virtualization extension)
3936 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3937 "sdiv", "\t$Rd, $Rn, $Rm",
3938 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
3939 Requires<[IsARM, HasDivideInARM]>;
3941 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3942 "udiv", "\t$Rd, $Rn, $Rm",
3943 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
3944 Requires<[IsARM, HasDivideInARM]>;
3946 //===----------------------------------------------------------------------===//
3947 // Misc. Arithmetic Instructions.
3950 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3951 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3952 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
3955 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3956 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3957 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3958 Requires<[IsARM, HasV6T2]>,
3961 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3962 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3963 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
3966 let AddedComplexity = 5 in
3967 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3968 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3969 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3970 Requires<[IsARM, HasV6]>,
3973 let AddedComplexity = 5 in
3974 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3975 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3976 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3977 Requires<[IsARM, HasV6]>,
3980 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3981 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3984 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3985 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3986 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3987 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3988 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3990 Requires<[IsARM, HasV6]>,
3991 Sched<[WriteALUsi, ReadALU]>;
3993 // Alternate cases for PKHBT where identities eliminate some nodes.
3994 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3995 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
3996 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
3997 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
3999 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
4000 // will match the pattern below.
4001 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
4002 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
4003 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
4004 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
4005 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
4007 Requires<[IsARM, HasV6]>,
4008 Sched<[WriteALUsi, ReadALU]>;
4010 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
4011 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
4012 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
4013 // pkhtb src1, src2, asr (17..31).
4014 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4015 (srl GPRnopc:$src2, imm16:$sh)),
4016 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>;
4017 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4018 (sra GPRnopc:$src2, imm16_31:$sh)),
4019 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
4020 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4021 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
4022 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
4024 //===----------------------------------------------------------------------===//
4028 // + CRC32{B,H,W} 0x04C11DB7
4029 // + CRC32C{B,H,W} 0x1EDC6F41
4032 class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
4033 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary,
4034 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
4035 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>,
4036 Requires<[IsARM, HasV8, HasCRC]> {
4041 let Inst{31-28} = 0b1110;
4042 let Inst{27-23} = 0b00010;
4043 let Inst{22-21} = sz;
4045 let Inst{19-16} = Rn;
4046 let Inst{15-12} = Rd;
4047 let Inst{11-10} = 0b00;
4050 let Inst{7-4} = 0b0100;
4053 let Unpredictable{11-8} = 0b1101;
4056 def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>;
4057 def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>;
4058 def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>;
4059 def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>;
4060 def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>;
4061 def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>;
4063 //===----------------------------------------------------------------------===//
4064 // Comparison Instructions...
4067 defm CMP : AI1_cmp_irs<0b1010, "cmp",
4068 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
4069 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
4071 // ARMcmpZ can re-use the above instruction definitions.
4072 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
4073 (CMPri GPR:$src, so_imm:$imm)>;
4074 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4075 (CMPrr GPR:$src, GPR:$rhs)>;
4076 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4077 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4078 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4079 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4081 // CMN register-integer
4082 let isCompare = 1, Defs = [CPSR] in {
4083 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi,
4084 "cmn", "\t$Rn, $imm",
4085 [(ARMcmn GPR:$Rn, so_imm:$imm)]>,
4086 Sched<[WriteCMP, ReadALU]> {
4091 let Inst{19-16} = Rn;
4092 let Inst{15-12} = 0b0000;
4093 let Inst{11-0} = imm;
4095 let Unpredictable{15-12} = 0b1111;
4098 // CMN register-register/shift
4099 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4100 "cmn", "\t$Rn, $Rm",
4101 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4102 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4105 let isCommutable = 1;
4108 let Inst{19-16} = Rn;
4109 let Inst{15-12} = 0b0000;
4110 let Inst{11-4} = 0b00000000;
4113 let Unpredictable{15-12} = 0b1111;
4116 def CMNzrsi : AI1<0b1011, (outs),
4117 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4118 "cmn", "\t$Rn, $shift",
4119 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4120 GPR:$Rn, so_reg_imm:$shift)]>,
4121 Sched<[WriteCMPsi, ReadALU]> {
4126 let Inst{19-16} = Rn;
4127 let Inst{15-12} = 0b0000;
4128 let Inst{11-5} = shift{11-5};
4130 let Inst{3-0} = shift{3-0};
4132 let Unpredictable{15-12} = 0b1111;
4135 def CMNzrsr : AI1<0b1011, (outs),
4136 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4137 "cmn", "\t$Rn, $shift",
4138 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4139 GPRnopc:$Rn, so_reg_reg:$shift)]>,
4140 Sched<[WriteCMPsr, ReadALU]> {
4145 let Inst{19-16} = Rn;
4146 let Inst{15-12} = 0b0000;
4147 let Inst{11-8} = shift{11-8};
4149 let Inst{6-5} = shift{6-5};
4151 let Inst{3-0} = shift{3-0};
4153 let Unpredictable{15-12} = 0b1111;
4158 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
4159 (CMNri GPR:$src, so_imm_neg:$imm)>;
4161 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
4162 (CMNri GPR:$src, so_imm_neg:$imm)>;
4164 // Note that TST/TEQ don't set all the same flags that CMP does!
4165 defm TST : AI1_cmp_irs<0b1000, "tst",
4166 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4167 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
4168 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4169 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4170 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4172 // Pseudo i64 compares for some floating point compares.
4173 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4175 def BCCi64 : PseudoInst<(outs),
4176 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4178 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
4181 def BCCZi64 : PseudoInst<(outs),
4182 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4183 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
4185 } // usesCustomInserter
4188 // Conditional moves
4189 let neverHasSideEffects = 1 in {
4191 let isCommutable = 1, isSelect = 1 in
4192 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
4193 (ins GPR:$false, GPR:$Rm, cmovpred:$p),
4195 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
4197 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4199 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4200 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p),
4203 (ARMcmov GPR:$false, so_reg_imm:$shift,
4205 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4206 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4207 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p),
4209 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4211 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4214 let isMoveImm = 1 in
4216 : ARMPseudoInst<(outs GPR:$Rd),
4217 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
4219 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm,
4221 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
4224 let isMoveImm = 1 in
4225 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4226 (ins GPR:$false, so_imm:$imm, cmovpred:$p),
4228 [(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm,
4230 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4232 // Two instruction predicate mov immediate.
4233 let isMoveImm = 1 in
4235 : ARMPseudoInst<(outs GPR:$Rd),
4236 (ins GPR:$false, i32imm:$src, cmovpred:$p),
4238 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
4240 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4242 let isMoveImm = 1 in
4243 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4244 (ins GPR:$false, so_imm:$imm, cmovpred:$p),
4246 [(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm,
4248 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4250 } // neverHasSideEffects
4253 //===----------------------------------------------------------------------===//
4254 // Atomic operations intrinsics
4257 def MemBarrierOptOperand : AsmOperandClass {
4258 let Name = "MemBarrierOpt";
4259 let ParserMethod = "parseMemBarrierOptOperand";
4261 def memb_opt : Operand<i32> {
4262 let PrintMethod = "printMemBOption";
4263 let ParserMatchClass = MemBarrierOptOperand;
4264 let DecoderMethod = "DecodeMemBarrierOption";
4267 def InstSyncBarrierOptOperand : AsmOperandClass {
4268 let Name = "InstSyncBarrierOpt";
4269 let ParserMethod = "parseInstSyncBarrierOptOperand";
4271 def instsyncb_opt : Operand<i32> {
4272 let PrintMethod = "printInstSyncBOption";
4273 let ParserMatchClass = InstSyncBarrierOptOperand;
4274 let DecoderMethod = "DecodeInstSyncBarrierOption";
4277 // memory barriers protect the atomic sequences
4278 let hasSideEffects = 1 in {
4279 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4280 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>,
4281 Requires<[IsARM, HasDB]> {
4283 let Inst{31-4} = 0xf57ff05;
4284 let Inst{3-0} = opt;
4288 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4289 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>,
4290 Requires<[IsARM, HasDB]> {
4292 let Inst{31-4} = 0xf57ff04;
4293 let Inst{3-0} = opt;
4296 // ISB has only full system option
4297 def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary,
4298 "isb", "\t$opt", []>,
4299 Requires<[IsARM, HasDB]> {
4301 let Inst{31-4} = 0xf57ff06;
4302 let Inst{3-0} = opt;
4305 let usesCustomInserter = 1, Defs = [CPSR] in {
4307 // Pseudo instruction that combines movs + predicated rsbmi
4308 // to implement integer ABS
4309 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4311 // Atomic pseudo-insts which will be lowered to ldrex/strex loops.
4312 // (64-bit pseudos use a hand-written selection code).
4313 let mayLoad = 1, mayStore = 1 in {
4314 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4316 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4318 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4320 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4322 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4324 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4326 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4328 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4330 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4332 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4334 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4336 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4338 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4340 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4342 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4344 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4346 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4348 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4350 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4352 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4354 def ATOMIC_SWAP_I8 : PseudoInst<
4356 (ins GPR:$ptr, GPR:$new, i32imm:$ordering),
4358 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4360 (ins GPR:$ptr, GPR:$old, GPR:$new, i32imm:$ordering),
4362 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4364 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4366 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4368 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4370 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4372 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4374 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4376 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4378 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4380 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4382 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4384 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4386 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4388 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4390 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4392 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4394 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4396 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4398 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4400 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4402 def ATOMIC_SWAP_I16 : PseudoInst<
4404 (ins GPR:$ptr, GPR:$new, i32imm:$ordering),
4406 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4408 (ins GPR:$ptr, GPR:$old, GPR:$new, i32imm:$ordering),
4410 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4412 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4414 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4416 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4418 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4420 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4422 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4424 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4426 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4428 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4430 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4432 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4434 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4436 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4438 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4440 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4442 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4444 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4446 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4448 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4450 def ATOMIC_SWAP_I32 : PseudoInst<
4452 (ins GPR:$ptr, GPR:$new, i32imm:$ordering),
4454 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4456 (ins GPR:$ptr, GPR:$old, GPR:$new, i32imm:$ordering),
4458 def ATOMIC_LOAD_ADD_I64 : PseudoInst<
4459 (outs GPR:$dst1, GPR:$dst2),
4460 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4462 def ATOMIC_LOAD_SUB_I64 : PseudoInst<
4463 (outs GPR:$dst1, GPR:$dst2),
4464 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4466 def ATOMIC_LOAD_AND_I64 : PseudoInst<
4467 (outs GPR:$dst1, GPR:$dst2),
4468 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4470 def ATOMIC_LOAD_OR_I64 : PseudoInst<
4471 (outs GPR:$dst1, GPR:$dst2),
4472 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4474 def ATOMIC_LOAD_XOR_I64 : PseudoInst<
4475 (outs GPR:$dst1, GPR:$dst2),
4476 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4478 def ATOMIC_LOAD_NAND_I64 : PseudoInst<
4479 (outs GPR:$dst1, GPR:$dst2),
4480 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4482 def ATOMIC_LOAD_MIN_I64 : PseudoInst<
4483 (outs GPR:$dst1, GPR:$dst2),
4484 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4486 def ATOMIC_LOAD_MAX_I64 : PseudoInst<
4487 (outs GPR:$dst1, GPR:$dst2),
4488 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4490 def ATOMIC_LOAD_UMIN_I64 : PseudoInst<
4491 (outs GPR:$dst1, GPR:$dst2),
4492 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4494 def ATOMIC_LOAD_UMAX_I64 : PseudoInst<
4495 (outs GPR:$dst1, GPR:$dst2),
4496 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4498 def ATOMIC_SWAP_I64 : PseudoInst<
4499 (outs GPR:$dst1, GPR:$dst2),
4500 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4502 def ATOMIC_CMP_SWAP_I64 : PseudoInst<
4503 (outs GPR:$dst1, GPR:$dst2),
4504 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
4505 GPR:$set1, GPR:$set2, i32imm:$ordering),
4509 def ATOMIC_LOAD_I64 : PseudoInst<
4510 (outs GPR:$dst1, GPR:$dst2),
4511 (ins GPR:$addr, i32imm:$ordering),
4514 def ATOMIC_STORE_I64 : PseudoInst<
4515 (outs GPR:$dst1, GPR:$dst2),
4516 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4520 let usesCustomInserter = 1 in {
4521 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4522 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4524 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4527 def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4528 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4531 def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4532 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4535 def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4536 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4539 def strex_1 : PatFrag<(ops node:$val, node:$ptr),
4540 (int_arm_strex node:$val, node:$ptr), [{
4541 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4544 def strex_2 : PatFrag<(ops node:$val, node:$ptr),
4545 (int_arm_strex node:$val, node:$ptr), [{
4546 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4549 def strex_4 : PatFrag<(ops node:$val, node:$ptr),
4550 (int_arm_strex node:$val, node:$ptr), [{
4551 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4554 let mayLoad = 1 in {
4555 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4556 NoItinerary, "ldrexb", "\t$Rt, $addr",
4557 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
4558 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4559 NoItinerary, "ldrexh", "\t$Rt, $addr",
4560 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
4561 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4562 NoItinerary, "ldrex", "\t$Rt, $addr",
4563 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>;
4564 let hasExtraDefRegAllocReq = 1 in
4565 def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4566 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
4567 let DecoderMethod = "DecodeDoubleRegLoad";
4570 def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4571 NoItinerary, "ldaexb", "\t$Rt, $addr", []>;
4572 def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4573 NoItinerary, "ldaexh", "\t$Rt, $addr", []>;
4574 def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4575 NoItinerary, "ldaex", "\t$Rt, $addr", []>;
4576 let hasExtraDefRegAllocReq = 1 in
4577 def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4578 NoItinerary, "ldaexd", "\t$Rt, $addr", []> {
4579 let DecoderMethod = "DecodeDoubleRegLoad";
4583 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4584 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4585 NoItinerary, "strexb", "\t$Rd, $Rt, $addr",
4586 [(set GPR:$Rd, (strex_1 GPR:$Rt, addr_offset_none:$addr))]>;
4587 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4588 NoItinerary, "strexh", "\t$Rd, $Rt, $addr",
4589 [(set GPR:$Rd, (strex_2 GPR:$Rt, addr_offset_none:$addr))]>;
4590 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4591 NoItinerary, "strex", "\t$Rd, $Rt, $addr",
4592 [(set GPR:$Rd, (strex_4 GPR:$Rt, addr_offset_none:$addr))]>;
4593 let hasExtraSrcRegAllocReq = 1 in
4594 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4595 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4596 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4597 let DecoderMethod = "DecodeDoubleRegStore";
4599 def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4600 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr",
4602 def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4603 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr",
4605 def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4606 NoItinerary, "stlex", "\t$Rd, $Rt, $addr",
4608 let hasExtraSrcRegAllocReq = 1 in
4609 def STLEXD : AIstlex<0b01, (outs GPR:$Rd),
4610 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4611 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> {
4612 let DecoderMethod = "DecodeDoubleRegStore";
4616 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
4618 Requires<[IsARM, HasV7]> {
4619 let Inst{31-0} = 0b11110101011111111111000000011111;
4622 def : ARMPat<(and (ldrex_1 addr_offset_none:$addr), 0xff),
4623 (LDREXB addr_offset_none:$addr)>;
4624 def : ARMPat<(and (ldrex_2 addr_offset_none:$addr), 0xffff),
4625 (LDREXH addr_offset_none:$addr)>;
4626 def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4627 (STREXB GPR:$Rt, addr_offset_none:$addr)>;
4628 def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4629 (STREXH GPR:$Rt, addr_offset_none:$addr)>;
4631 class acquiring_load<PatFrag base>
4632 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
4633 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4634 return Ordering == Acquire || Ordering == SequentiallyConsistent;
4637 def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
4638 def atomic_load_acquire_16 : acquiring_load<atomic_load_16>;
4639 def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
4641 class releasing_store<PatFrag base>
4642 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
4643 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4644 return Ordering == Release || Ordering == SequentiallyConsistent;
4647 def atomic_store_release_8 : releasing_store<atomic_store_8>;
4648 def atomic_store_release_16 : releasing_store<atomic_store_16>;
4649 def atomic_store_release_32 : releasing_store<atomic_store_32>;
4651 let AddedComplexity = 8 in {
4652 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>;
4653 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>;
4654 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>;
4655 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>;
4656 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>;
4657 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>;
4660 // SWP/SWPB are deprecated in V6/V7.
4661 let mayLoad = 1, mayStore = 1 in {
4662 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4663 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>,
4665 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4666 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>,
4670 //===----------------------------------------------------------------------===//
4671 // Coprocessor Instructions.
4674 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4675 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4676 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4677 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4678 imm:$CRm, imm:$opc2)]>,
4687 let Inst{3-0} = CRm;
4689 let Inst{7-5} = opc2;
4690 let Inst{11-8} = cop;
4691 let Inst{15-12} = CRd;
4692 let Inst{19-16} = CRn;
4693 let Inst{23-20} = opc1;
4696 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4697 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4698 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4699 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4700 imm:$CRm, imm:$opc2)]>,
4702 let Inst{31-28} = 0b1111;
4710 let Inst{3-0} = CRm;
4712 let Inst{7-5} = opc2;
4713 let Inst{11-8} = cop;
4714 let Inst{15-12} = CRd;
4715 let Inst{19-16} = CRn;
4716 let Inst{23-20} = opc1;
4719 class ACI<dag oops, dag iops, string opc, string asm,
4720 IndexMode im = IndexModeNone>
4721 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4723 let Inst{27-25} = 0b110;
4725 class ACInoP<dag oops, dag iops, string opc, string asm,
4726 IndexMode im = IndexModeNone>
4727 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4729 let Inst{31-28} = 0b1111;
4730 let Inst{27-25} = 0b110;
4732 multiclass LdStCop<bit load, bit Dbit, string asm> {
4733 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4734 asm, "\t$cop, $CRd, $addr"> {
4738 let Inst{24} = 1; // P = 1
4739 let Inst{23} = addr{8};
4740 let Inst{22} = Dbit;
4741 let Inst{21} = 0; // W = 0
4742 let Inst{20} = load;
4743 let Inst{19-16} = addr{12-9};
4744 let Inst{15-12} = CRd;
4745 let Inst{11-8} = cop;
4746 let Inst{7-0} = addr{7-0};
4747 let DecoderMethod = "DecodeCopMemInstruction";
4749 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4750 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4754 let Inst{24} = 1; // P = 1
4755 let Inst{23} = addr{8};
4756 let Inst{22} = Dbit;
4757 let Inst{21} = 1; // W = 1
4758 let Inst{20} = load;
4759 let Inst{19-16} = addr{12-9};
4760 let Inst{15-12} = CRd;
4761 let Inst{11-8} = cop;
4762 let Inst{7-0} = addr{7-0};
4763 let DecoderMethod = "DecodeCopMemInstruction";
4765 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4766 postidx_imm8s4:$offset),
4767 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4772 let Inst{24} = 0; // P = 0
4773 let Inst{23} = offset{8};
4774 let Inst{22} = Dbit;
4775 let Inst{21} = 1; // W = 1
4776 let Inst{20} = load;
4777 let Inst{19-16} = addr;
4778 let Inst{15-12} = CRd;
4779 let Inst{11-8} = cop;
4780 let Inst{7-0} = offset{7-0};
4781 let DecoderMethod = "DecodeCopMemInstruction";
4783 def _OPTION : ACI<(outs),
4784 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4785 coproc_option_imm:$option),
4786 asm, "\t$cop, $CRd, $addr, $option"> {
4791 let Inst{24} = 0; // P = 0
4792 let Inst{23} = 1; // U = 1
4793 let Inst{22} = Dbit;
4794 let Inst{21} = 0; // W = 0
4795 let Inst{20} = load;
4796 let Inst{19-16} = addr;
4797 let Inst{15-12} = CRd;
4798 let Inst{11-8} = cop;
4799 let Inst{7-0} = option;
4800 let DecoderMethod = "DecodeCopMemInstruction";
4803 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4804 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4805 asm, "\t$cop, $CRd, $addr"> {
4809 let Inst{24} = 1; // P = 1
4810 let Inst{23} = addr{8};
4811 let Inst{22} = Dbit;
4812 let Inst{21} = 0; // W = 0
4813 let Inst{20} = load;
4814 let Inst{19-16} = addr{12-9};
4815 let Inst{15-12} = CRd;
4816 let Inst{11-8} = cop;
4817 let Inst{7-0} = addr{7-0};
4818 let DecoderMethod = "DecodeCopMemInstruction";
4820 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4821 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4825 let Inst{24} = 1; // P = 1
4826 let Inst{23} = addr{8};
4827 let Inst{22} = Dbit;
4828 let Inst{21} = 1; // W = 1
4829 let Inst{20} = load;
4830 let Inst{19-16} = addr{12-9};
4831 let Inst{15-12} = CRd;
4832 let Inst{11-8} = cop;
4833 let Inst{7-0} = addr{7-0};
4834 let DecoderMethod = "DecodeCopMemInstruction";
4836 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4837 postidx_imm8s4:$offset),
4838 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4843 let Inst{24} = 0; // P = 0
4844 let Inst{23} = offset{8};
4845 let Inst{22} = Dbit;
4846 let Inst{21} = 1; // W = 1
4847 let Inst{20} = load;
4848 let Inst{19-16} = addr;
4849 let Inst{15-12} = CRd;
4850 let Inst{11-8} = cop;
4851 let Inst{7-0} = offset{7-0};
4852 let DecoderMethod = "DecodeCopMemInstruction";
4854 def _OPTION : ACInoP<(outs),
4855 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4856 coproc_option_imm:$option),
4857 asm, "\t$cop, $CRd, $addr, $option"> {
4862 let Inst{24} = 0; // P = 0
4863 let Inst{23} = 1; // U = 1
4864 let Inst{22} = Dbit;
4865 let Inst{21} = 0; // W = 0
4866 let Inst{20} = load;
4867 let Inst{19-16} = addr;
4868 let Inst{15-12} = CRd;
4869 let Inst{11-8} = cop;
4870 let Inst{7-0} = option;
4871 let DecoderMethod = "DecodeCopMemInstruction";
4875 defm LDC : LdStCop <1, 0, "ldc">;
4876 defm LDCL : LdStCop <1, 1, "ldcl">;
4877 defm STC : LdStCop <0, 0, "stc">;
4878 defm STCL : LdStCop <0, 1, "stcl">;
4879 defm LDC2 : LdSt2Cop<1, 0, "ldc2">, Requires<[PreV8]>;
4880 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">, Requires<[PreV8]>;
4881 defm STC2 : LdSt2Cop<0, 0, "stc2">, Requires<[PreV8]>;
4882 defm STC2L : LdSt2Cop<0, 1, "stc2l">, Requires<[PreV8]>;
4884 //===----------------------------------------------------------------------===//
4885 // Move between coprocessor and ARM core register.
4888 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4890 : ABI<0b1110, oops, iops, NoItinerary, opc,
4891 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4892 let Inst{20} = direction;
4902 let Inst{15-12} = Rt;
4903 let Inst{11-8} = cop;
4904 let Inst{23-21} = opc1;
4905 let Inst{7-5} = opc2;
4906 let Inst{3-0} = CRm;
4907 let Inst{19-16} = CRn;
4910 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4912 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4913 c_imm:$CRm, imm0_7:$opc2),
4914 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4915 imm:$CRm, imm:$opc2)]>,
4916 ComplexDeprecationPredicate<"MCR">;
4917 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4918 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4919 c_imm:$CRm, 0, pred:$p)>;
4920 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4921 (outs GPRwithAPSR:$Rt),
4922 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4924 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4925 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4926 c_imm:$CRm, 0, pred:$p)>;
4928 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4929 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4931 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4933 : ABXI<0b1110, oops, iops, NoItinerary,
4934 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4935 let Inst{31-24} = 0b11111110;
4936 let Inst{20} = direction;
4946 let Inst{15-12} = Rt;
4947 let Inst{11-8} = cop;
4948 let Inst{23-21} = opc1;
4949 let Inst{7-5} = opc2;
4950 let Inst{3-0} = CRm;
4951 let Inst{19-16} = CRn;
4954 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4956 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4957 c_imm:$CRm, imm0_7:$opc2),
4958 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4959 imm:$CRm, imm:$opc2)]>,
4961 def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm",
4962 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4964 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4965 (outs GPRwithAPSR:$Rt),
4966 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4969 def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm",
4970 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4973 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4974 imm:$CRm, imm:$opc2),
4975 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4977 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4978 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4979 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
4980 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4981 let Inst{23-21} = 0b010;
4982 let Inst{20} = direction;
4990 let Inst{15-12} = Rt;
4991 let Inst{19-16} = Rt2;
4992 let Inst{11-8} = cop;
4993 let Inst{7-4} = opc1;
4994 let Inst{3-0} = CRm;
4997 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4998 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
4999 GPRnopc:$Rt2, imm:$CRm)]>;
5000 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
5002 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
5003 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5004 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
5005 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>,
5007 let Inst{31-28} = 0b1111;
5008 let Inst{23-21} = 0b010;
5009 let Inst{20} = direction;
5017 let Inst{15-12} = Rt;
5018 let Inst{19-16} = Rt2;
5019 let Inst{11-8} = cop;
5020 let Inst{7-4} = opc1;
5021 let Inst{3-0} = CRm;
5023 let DecoderMethod = "DecodeMRRC2";
5026 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
5027 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
5028 GPRnopc:$Rt2, imm:$CRm)]>;
5029 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
5031 //===----------------------------------------------------------------------===//
5032 // Move between special register and ARM core register
5035 // Move to ARM core register from Special Register
5036 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5037 "mrs", "\t$Rd, apsr", []> {
5039 let Inst{23-16} = 0b00001111;
5040 let Unpredictable{19-17} = 0b111;
5042 let Inst{15-12} = Rd;
5044 let Inst{11-0} = 0b000000000000;
5045 let Unpredictable{11-0} = 0b110100001111;
5048 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
5051 // The MRSsys instruction is the MRS instruction from the ARM ARM,
5052 // section B9.3.9, with the R bit set to 1.
5053 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5054 "mrs", "\t$Rd, spsr", []> {
5056 let Inst{23-16} = 0b01001111;
5057 let Unpredictable{19-16} = 0b1111;
5059 let Inst{15-12} = Rd;
5061 let Inst{11-0} = 0b000000000000;
5062 let Unpredictable{11-0} = 0b110100001111;
5065 // Move from ARM core register to Special Register
5067 // No need to have both system and application versions, the encodings are the
5068 // same and the assembly parser has no way to distinguish between them. The mask
5069 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
5070 // the mask with the fields to be accessed in the special register.
5071 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
5072 "msr", "\t$mask, $Rn", []> {
5077 let Inst{22} = mask{4}; // R bit
5078 let Inst{21-20} = 0b10;
5079 let Inst{19-16} = mask{3-0};
5080 let Inst{15-12} = 0b1111;
5081 let Inst{11-4} = 0b00000000;
5085 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
5086 "msr", "\t$mask, $a", []> {
5091 let Inst{22} = mask{4}; // R bit
5092 let Inst{21-20} = 0b10;
5093 let Inst{19-16} = mask{3-0};
5094 let Inst{15-12} = 0b1111;
5098 //===----------------------------------------------------------------------===//
5102 // __aeabi_read_tp preserves the registers r1-r3.
5103 // This is a pseudo inst so that we can get the encoding right,
5104 // complete with fixup for the aeabi_read_tp function.
5106 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
5107 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
5108 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
5111 //===----------------------------------------------------------------------===//
5112 // SJLJ Exception handling intrinsics
5113 // eh_sjlj_setjmp() is an instruction sequence to store the return
5114 // address and save #0 in R0 for the non-longjmp case.
5115 // Since by its nature we may be coming from some other function to get
5116 // here, and we're using the stack frame for the containing function to
5117 // save/restore registers, we can't keep anything live in regs across
5118 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
5119 // when we get here from a longjmp(). We force everything out of registers
5120 // except for our own input by listing the relevant registers in Defs. By
5121 // doing so, we also cause the prologue/epilogue code to actively preserve
5122 // all of the callee-saved resgisters, which is exactly what we want.
5123 // A constant value is passed in $val, and we use the location as a scratch.
5125 // These are pseudo-instructions and are lowered to individual MC-insts, so
5126 // no encoding information is necessary.
5128 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
5129 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
5130 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5131 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5133 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5134 Requires<[IsARM, HasVFP2]>;
5138 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
5139 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5140 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5142 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5143 Requires<[IsARM, NoVFP]>;
5146 // FIXME: Non-IOS version(s)
5147 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
5148 Defs = [ R7, LR, SP ] in {
5149 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
5151 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
5152 Requires<[IsARM, IsIOS]>;
5155 // eh.sjlj.dispatchsetup pseudo-instruction.
5156 // This pseudo is used for both ARM and Thumb. Any differences are handled when
5157 // the pseudo is expanded (which happens before any passes that need the
5158 // instruction size).
5159 let isBarrier = 1 in
5160 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
5163 //===----------------------------------------------------------------------===//
5164 // Non-Instruction Patterns
5167 // ARMv4 indirect branch using (MOVr PC, dst)
5168 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
5169 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
5170 4, IIC_Br, [(brind GPR:$dst)],
5171 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
5172 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
5174 // Large immediate handling.
5176 // 32-bit immediate using two piece so_imms or movw + movt.
5177 // This is a single pseudo instruction, the benefit is that it can be remat'd
5178 // as a single unit instead of having to handle reg inputs.
5179 // FIXME: Remove this when we can do generalized remat.
5180 let isReMaterializable = 1, isMoveImm = 1 in
5181 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
5182 [(set GPR:$dst, (arm_i32imm:$src))]>,
5185 // Pseudo instruction that combines movw + movt + add pc (if PIC).
5186 // It also makes it possible to rematerialize the instructions.
5187 // FIXME: Remove this when we can do generalized remat and when machine licm
5188 // can properly the instructions.
5189 let isReMaterializable = 1 in {
5190 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5192 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
5193 Requires<[IsARM, UseMovt]>;
5195 let AddedComplexity = 10 in
5196 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5198 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5199 Requires<[IsARM, UseMovt]>;
5200 } // isReMaterializable
5202 // ConstantPool, GlobalAddress, and JumpTable
5203 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
5204 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
5205 Requires<[IsARM, UseMovt]>;
5206 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
5207 (LEApcrelJT tjumptable:$dst, imm:$id)>;
5209 // TODO: add,sub,and, 3-instr forms?
5211 // Tail calls. These patterns also apply to Thumb mode.
5212 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
5213 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
5214 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
5217 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
5218 def : ARMPat<(ARMcall_nolink texternalsym:$func),
5219 (BMOVPCB_CALL texternalsym:$func)>;
5221 // zextload i1 -> zextload i8
5222 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5223 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5225 // extload -> zextload
5226 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5227 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5228 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5229 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5231 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
5233 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
5234 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
5237 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5238 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5239 (SMULBB GPR:$a, GPR:$b)>;
5240 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
5241 (SMULBB GPR:$a, GPR:$b)>;
5242 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5243 (sra GPR:$b, (i32 16))),
5244 (SMULBT GPR:$a, GPR:$b)>;
5245 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
5246 (SMULBT GPR:$a, GPR:$b)>;
5247 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
5248 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5249 (SMULTB GPR:$a, GPR:$b)>;
5250 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
5251 (SMULTB GPR:$a, GPR:$b)>;
5252 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
5254 (SMULWB GPR:$a, GPR:$b)>;
5255 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
5256 (SMULWB GPR:$a, GPR:$b)>;
5258 def : ARMV5MOPat<(add GPR:$acc,
5259 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5260 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5261 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5262 def : ARMV5MOPat<(add GPR:$acc,
5263 (mul sext_16_node:$a, sext_16_node:$b)),
5264 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5265 def : ARMV5MOPat<(add GPR:$acc,
5266 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5267 (sra GPR:$b, (i32 16)))),
5268 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5269 def : ARMV5MOPat<(add GPR:$acc,
5270 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
5271 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5272 def : ARMV5MOPat<(add GPR:$acc,
5273 (mul (sra GPR:$a, (i32 16)),
5274 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5275 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5276 def : ARMV5MOPat<(add GPR:$acc,
5277 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
5278 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5279 def : ARMV5MOPat<(add GPR:$acc,
5280 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
5282 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
5283 def : ARMV5MOPat<(add GPR:$acc,
5284 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
5285 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
5288 // Pre-v7 uses MCR for synchronization barriers.
5289 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
5290 Requires<[IsARM, HasV6]>;
5292 // SXT/UXT with no rotate
5293 let AddedComplexity = 16 in {
5294 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5295 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
5296 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
5297 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
5298 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
5299 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
5300 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5303 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5304 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5306 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5307 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5308 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5309 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5311 // Atomic load/store patterns
5312 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
5313 (LDRBrs ldst_so_reg:$src)>;
5314 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
5315 (LDRBi12 addrmode_imm12:$src)>;
5316 def : ARMPat<(atomic_load_16 addrmode3:$src),
5317 (LDRH addrmode3:$src)>;
5318 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5319 (LDRrs ldst_so_reg:$src)>;
5320 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5321 (LDRi12 addrmode_imm12:$src)>;
5322 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5323 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5324 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5325 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5326 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5327 (STRH GPR:$val, addrmode3:$ptr)>;
5328 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5329 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5330 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5331 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5334 //===----------------------------------------------------------------------===//
5338 include "ARMInstrThumb.td"
5340 //===----------------------------------------------------------------------===//
5344 include "ARMInstrThumb2.td"
5346 //===----------------------------------------------------------------------===//
5347 // Floating Point Support
5350 include "ARMInstrVFP.td"
5352 //===----------------------------------------------------------------------===//
5353 // Advanced SIMD (NEON) Support
5356 include "ARMInstrNEON.td"
5358 //===----------------------------------------------------------------------===//
5359 // Assembler aliases
5363 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5364 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5365 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5367 // System instructions
5368 def : MnemonicAlias<"swi", "svc">;
5370 // Load / Store Multiple
5371 def : MnemonicAlias<"ldmfd", "ldm">;
5372 def : MnemonicAlias<"ldmia", "ldm">;
5373 def : MnemonicAlias<"ldmea", "ldmdb">;
5374 def : MnemonicAlias<"stmfd", "stmdb">;
5375 def : MnemonicAlias<"stmia", "stm">;
5376 def : MnemonicAlias<"stmea", "stm">;
5378 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5379 // shift amount is zero (i.e., unspecified).
5380 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5381 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5382 Requires<[IsARM, HasV6]>;
5383 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5384 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5385 Requires<[IsARM, HasV6]>;
5387 // PUSH/POP aliases for STM/LDM
5388 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5389 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5391 // SSAT/USAT optional shift operand.
5392 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5393 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5394 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5395 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5398 // Extend instruction optional rotate operand.
5399 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5400 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5401 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5402 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5403 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5404 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5405 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5406 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5407 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5408 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5409 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5410 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5412 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5413 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5414 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5415 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5416 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5417 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5418 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5419 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5420 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5421 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5422 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5423 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5427 def : MnemonicAlias<"rfefa", "rfeda">;
5428 def : MnemonicAlias<"rfeea", "rfedb">;
5429 def : MnemonicAlias<"rfefd", "rfeia">;
5430 def : MnemonicAlias<"rfeed", "rfeib">;
5431 def : MnemonicAlias<"rfe", "rfeia">;
5434 def : MnemonicAlias<"srsfa", "srsib">;
5435 def : MnemonicAlias<"srsea", "srsia">;
5436 def : MnemonicAlias<"srsfd", "srsdb">;
5437 def : MnemonicAlias<"srsed", "srsda">;
5438 def : MnemonicAlias<"srs", "srsia">;
5441 def : MnemonicAlias<"qsubaddx", "qsax">;
5443 def : MnemonicAlias<"saddsubx", "sasx">;
5444 // SHASX == SHADDSUBX
5445 def : MnemonicAlias<"shaddsubx", "shasx">;
5446 // SHSAX == SHSUBADDX
5447 def : MnemonicAlias<"shsubaddx", "shsax">;
5449 def : MnemonicAlias<"ssubaddx", "ssax">;
5451 def : MnemonicAlias<"uaddsubx", "uasx">;
5452 // UHASX == UHADDSUBX
5453 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5454 // UHSAX == UHSUBADDX
5455 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5456 // UQASX == UQADDSUBX
5457 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5458 // UQSAX == UQSUBADDX
5459 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5461 def : MnemonicAlias<"usubaddx", "usax">;
5463 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5465 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5466 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5467 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5468 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5469 // Same for AND <--> BIC
5470 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5471 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5472 pred:$p, cc_out:$s)>;
5473 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5474 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5475 pred:$p, cc_out:$s)>;
5476 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5477 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5478 pred:$p, cc_out:$s)>;
5479 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5480 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5481 pred:$p, cc_out:$s)>;
5483 // Likewise, "add Rd, so_imm_neg" -> sub
5484 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5485 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5486 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5487 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5488 // Same for CMP <--> CMN via so_imm_neg
5489 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5490 (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5491 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5492 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5494 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5495 // LSR, ROR, and RRX instructions.
5496 // FIXME: We need C++ parser hooks to map the alias to the MOV
5497 // encoding. It seems we should be able to do that sort of thing
5498 // in tblgen, but it could get ugly.
5499 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5500 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5501 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5503 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5504 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5506 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5507 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5509 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5510 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5513 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5514 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
5515 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5516 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5517 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5519 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5520 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5522 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5523 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5525 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5526 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5530 // "neg" is and alias for "rsb rd, rn, #0"
5531 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5532 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5534 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5535 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5536 Requires<[IsARM, NoV6]>;
5538 // UMULL/SMULL are available on all arches, but the instruction definitions
5539 // need difference constraints pre-v6. Use these aliases for the assembly
5540 // parsing on pre-v6.
5541 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5542 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5543 Requires<[IsARM, NoV6]>;
5544 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5545 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5546 Requires<[IsARM, NoV6]>;
5548 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5550 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>,
5551 ComplexDeprecationPredicate<"IT">;