1 //===-- ARMInstrNEON.td - NEON support for ARM -------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // NEON-specific Operands.
17 //===----------------------------------------------------------------------===//
18 def nModImm : Operand<i32> {
19 let PrintMethod = "printNEONModImmOperand";
22 def nImmSplatI8AsmOperand : AsmOperandClass { let Name = "NEONi8splat"; }
23 def nImmSplatI8 : Operand<i32> {
24 let PrintMethod = "printNEONModImmOperand";
25 let ParserMatchClass = nImmSplatI8AsmOperand;
27 def nImmSplatI16AsmOperand : AsmOperandClass { let Name = "NEONi16splat"; }
28 def nImmSplatI16 : Operand<i32> {
29 let PrintMethod = "printNEONModImmOperand";
30 let ParserMatchClass = nImmSplatI16AsmOperand;
32 def nImmSplatI32AsmOperand : AsmOperandClass { let Name = "NEONi32splat"; }
33 def nImmSplatI32 : Operand<i32> {
34 let PrintMethod = "printNEONModImmOperand";
35 let ParserMatchClass = nImmSplatI32AsmOperand;
37 def nImmVMOVI32AsmOperand : AsmOperandClass { let Name = "NEONi32vmov"; }
38 def nImmVMOVI32 : Operand<i32> {
39 let PrintMethod = "printNEONModImmOperand";
40 let ParserMatchClass = nImmVMOVI32AsmOperand;
42 def nImmVMOVI32NegAsmOperand : AsmOperandClass { let Name = "NEONi32vmovNeg"; }
43 def nImmVMOVI32Neg : Operand<i32> {
44 let PrintMethod = "printNEONModImmOperand";
45 let ParserMatchClass = nImmVMOVI32NegAsmOperand;
47 def nImmVMOVF32 : Operand<i32> {
48 let PrintMethod = "printFPImmOperand";
49 let ParserMatchClass = FPImmOperand;
51 def nImmSplatI64AsmOperand : AsmOperandClass { let Name = "NEONi64splat"; }
52 def nImmSplatI64 : Operand<i32> {
53 let PrintMethod = "printNEONModImmOperand";
54 let ParserMatchClass = nImmSplatI64AsmOperand;
57 def VectorIndex8Operand : AsmOperandClass { let Name = "VectorIndex8"; }
58 def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; }
59 def VectorIndex32Operand : AsmOperandClass { let Name = "VectorIndex32"; }
60 def VectorIndex8 : Operand<i32>, ImmLeaf<i32, [{
61 return ((uint64_t)Imm) < 8;
63 let ParserMatchClass = VectorIndex8Operand;
64 let PrintMethod = "printVectorIndex";
65 let MIOperandInfo = (ops i32imm);
67 def VectorIndex16 : Operand<i32>, ImmLeaf<i32, [{
68 return ((uint64_t)Imm) < 4;
70 let ParserMatchClass = VectorIndex16Operand;
71 let PrintMethod = "printVectorIndex";
72 let MIOperandInfo = (ops i32imm);
74 def VectorIndex32 : Operand<i32>, ImmLeaf<i32, [{
75 return ((uint64_t)Imm) < 2;
77 let ParserMatchClass = VectorIndex32Operand;
78 let PrintMethod = "printVectorIndex";
79 let MIOperandInfo = (ops i32imm);
82 // Register list of one D register.
83 def VecListOneDAsmOperand : AsmOperandClass {
84 let Name = "VecListOneD";
85 let ParserMethod = "parseVectorList";
86 let RenderMethod = "addVecListOperands";
88 def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> {
89 let ParserMatchClass = VecListOneDAsmOperand;
91 // Register list of two sequential D registers.
92 def VecListDPairAsmOperand : AsmOperandClass {
93 let Name = "VecListDPair";
94 let ParserMethod = "parseVectorList";
95 let RenderMethod = "addVecListOperands";
97 def VecListDPair : RegisterOperand<DPair, "printVectorListTwo"> {
98 let ParserMatchClass = VecListDPairAsmOperand;
100 // Register list of three sequential D registers.
101 def VecListThreeDAsmOperand : AsmOperandClass {
102 let Name = "VecListThreeD";
103 let ParserMethod = "parseVectorList";
104 let RenderMethod = "addVecListOperands";
106 def VecListThreeD : RegisterOperand<DPR, "printVectorListThree"> {
107 let ParserMatchClass = VecListThreeDAsmOperand;
109 // Register list of four sequential D registers.
110 def VecListFourDAsmOperand : AsmOperandClass {
111 let Name = "VecListFourD";
112 let ParserMethod = "parseVectorList";
113 let RenderMethod = "addVecListOperands";
115 def VecListFourD : RegisterOperand<DPR, "printVectorListFour"> {
116 let ParserMatchClass = VecListFourDAsmOperand;
118 // Register list of two D registers spaced by 2 (two sequential Q registers).
119 def VecListDPairSpacedAsmOperand : AsmOperandClass {
120 let Name = "VecListDPairSpaced";
121 let ParserMethod = "parseVectorList";
122 let RenderMethod = "addVecListOperands";
124 def VecListDPairSpaced : RegisterOperand<DPair, "printVectorListTwoSpaced"> {
125 let ParserMatchClass = VecListDPairSpacedAsmOperand;
127 // Register list of three D registers spaced by 2 (three Q registers).
128 def VecListThreeQAsmOperand : AsmOperandClass {
129 let Name = "VecListThreeQ";
130 let ParserMethod = "parseVectorList";
131 let RenderMethod = "addVecListOperands";
133 def VecListThreeQ : RegisterOperand<DPR, "printVectorListThreeSpaced"> {
134 let ParserMatchClass = VecListThreeQAsmOperand;
136 // Register list of three D registers spaced by 2 (three Q registers).
137 def VecListFourQAsmOperand : AsmOperandClass {
138 let Name = "VecListFourQ";
139 let ParserMethod = "parseVectorList";
140 let RenderMethod = "addVecListOperands";
142 def VecListFourQ : RegisterOperand<DPR, "printVectorListFourSpaced"> {
143 let ParserMatchClass = VecListFourQAsmOperand;
146 // Register list of one D register, with "all lanes" subscripting.
147 def VecListOneDAllLanesAsmOperand : AsmOperandClass {
148 let Name = "VecListOneDAllLanes";
149 let ParserMethod = "parseVectorList";
150 let RenderMethod = "addVecListOperands";
152 def VecListOneDAllLanes : RegisterOperand<DPR, "printVectorListOneAllLanes"> {
153 let ParserMatchClass = VecListOneDAllLanesAsmOperand;
155 // Register list of two D registers, with "all lanes" subscripting.
156 def VecListDPairAllLanesAsmOperand : AsmOperandClass {
157 let Name = "VecListDPairAllLanes";
158 let ParserMethod = "parseVectorList";
159 let RenderMethod = "addVecListOperands";
161 def VecListDPairAllLanes : RegisterOperand<DPair,
162 "printVectorListTwoAllLanes"> {
163 let ParserMatchClass = VecListDPairAllLanesAsmOperand;
165 // Register list of two D registers spaced by 2 (two sequential Q registers).
166 def VecListDPairSpacedAllLanesAsmOperand : AsmOperandClass {
167 let Name = "VecListDPairSpacedAllLanes";
168 let ParserMethod = "parseVectorList";
169 let RenderMethod = "addVecListOperands";
171 def VecListDPairSpacedAllLanes : RegisterOperand<DPair,
172 "printVectorListTwoSpacedAllLanes"> {
173 let ParserMatchClass = VecListDPairSpacedAllLanesAsmOperand;
175 // Register list of three D registers, with "all lanes" subscripting.
176 def VecListThreeDAllLanesAsmOperand : AsmOperandClass {
177 let Name = "VecListThreeDAllLanes";
178 let ParserMethod = "parseVectorList";
179 let RenderMethod = "addVecListOperands";
181 def VecListThreeDAllLanes : RegisterOperand<DPR,
182 "printVectorListThreeAllLanes"> {
183 let ParserMatchClass = VecListThreeDAllLanesAsmOperand;
185 // Register list of three D registers spaced by 2 (three sequential Q regs).
186 def VecListThreeQAllLanesAsmOperand : AsmOperandClass {
187 let Name = "VecListThreeQAllLanes";
188 let ParserMethod = "parseVectorList";
189 let RenderMethod = "addVecListOperands";
191 def VecListThreeQAllLanes : RegisterOperand<DPR,
192 "printVectorListThreeSpacedAllLanes"> {
193 let ParserMatchClass = VecListThreeQAllLanesAsmOperand;
195 // Register list of four D registers, with "all lanes" subscripting.
196 def VecListFourDAllLanesAsmOperand : AsmOperandClass {
197 let Name = "VecListFourDAllLanes";
198 let ParserMethod = "parseVectorList";
199 let RenderMethod = "addVecListOperands";
201 def VecListFourDAllLanes : RegisterOperand<DPR, "printVectorListFourAllLanes"> {
202 let ParserMatchClass = VecListFourDAllLanesAsmOperand;
204 // Register list of four D registers spaced by 2 (four sequential Q regs).
205 def VecListFourQAllLanesAsmOperand : AsmOperandClass {
206 let Name = "VecListFourQAllLanes";
207 let ParserMethod = "parseVectorList";
208 let RenderMethod = "addVecListOperands";
210 def VecListFourQAllLanes : RegisterOperand<DPR,
211 "printVectorListFourSpacedAllLanes"> {
212 let ParserMatchClass = VecListFourQAllLanesAsmOperand;
216 // Register list of one D register, with byte lane subscripting.
217 def VecListOneDByteIndexAsmOperand : AsmOperandClass {
218 let Name = "VecListOneDByteIndexed";
219 let ParserMethod = "parseVectorList";
220 let RenderMethod = "addVecListIndexedOperands";
222 def VecListOneDByteIndexed : Operand<i32> {
223 let ParserMatchClass = VecListOneDByteIndexAsmOperand;
224 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
226 // ...with half-word lane subscripting.
227 def VecListOneDHWordIndexAsmOperand : AsmOperandClass {
228 let Name = "VecListOneDHWordIndexed";
229 let ParserMethod = "parseVectorList";
230 let RenderMethod = "addVecListIndexedOperands";
232 def VecListOneDHWordIndexed : Operand<i32> {
233 let ParserMatchClass = VecListOneDHWordIndexAsmOperand;
234 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
236 // ...with word lane subscripting.
237 def VecListOneDWordIndexAsmOperand : AsmOperandClass {
238 let Name = "VecListOneDWordIndexed";
239 let ParserMethod = "parseVectorList";
240 let RenderMethod = "addVecListIndexedOperands";
242 def VecListOneDWordIndexed : Operand<i32> {
243 let ParserMatchClass = VecListOneDWordIndexAsmOperand;
244 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
247 // Register list of two D registers with byte lane subscripting.
248 def VecListTwoDByteIndexAsmOperand : AsmOperandClass {
249 let Name = "VecListTwoDByteIndexed";
250 let ParserMethod = "parseVectorList";
251 let RenderMethod = "addVecListIndexedOperands";
253 def VecListTwoDByteIndexed : Operand<i32> {
254 let ParserMatchClass = VecListTwoDByteIndexAsmOperand;
255 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
257 // ...with half-word lane subscripting.
258 def VecListTwoDHWordIndexAsmOperand : AsmOperandClass {
259 let Name = "VecListTwoDHWordIndexed";
260 let ParserMethod = "parseVectorList";
261 let RenderMethod = "addVecListIndexedOperands";
263 def VecListTwoDHWordIndexed : Operand<i32> {
264 let ParserMatchClass = VecListTwoDHWordIndexAsmOperand;
265 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
267 // ...with word lane subscripting.
268 def VecListTwoDWordIndexAsmOperand : AsmOperandClass {
269 let Name = "VecListTwoDWordIndexed";
270 let ParserMethod = "parseVectorList";
271 let RenderMethod = "addVecListIndexedOperands";
273 def VecListTwoDWordIndexed : Operand<i32> {
274 let ParserMatchClass = VecListTwoDWordIndexAsmOperand;
275 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
277 // Register list of two Q registers with half-word lane subscripting.
278 def VecListTwoQHWordIndexAsmOperand : AsmOperandClass {
279 let Name = "VecListTwoQHWordIndexed";
280 let ParserMethod = "parseVectorList";
281 let RenderMethod = "addVecListIndexedOperands";
283 def VecListTwoQHWordIndexed : Operand<i32> {
284 let ParserMatchClass = VecListTwoQHWordIndexAsmOperand;
285 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
287 // ...with word lane subscripting.
288 def VecListTwoQWordIndexAsmOperand : AsmOperandClass {
289 let Name = "VecListTwoQWordIndexed";
290 let ParserMethod = "parseVectorList";
291 let RenderMethod = "addVecListIndexedOperands";
293 def VecListTwoQWordIndexed : Operand<i32> {
294 let ParserMatchClass = VecListTwoQWordIndexAsmOperand;
295 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
299 // Register list of three D registers with byte lane subscripting.
300 def VecListThreeDByteIndexAsmOperand : AsmOperandClass {
301 let Name = "VecListThreeDByteIndexed";
302 let ParserMethod = "parseVectorList";
303 let RenderMethod = "addVecListIndexedOperands";
305 def VecListThreeDByteIndexed : Operand<i32> {
306 let ParserMatchClass = VecListThreeDByteIndexAsmOperand;
307 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
309 // ...with half-word lane subscripting.
310 def VecListThreeDHWordIndexAsmOperand : AsmOperandClass {
311 let Name = "VecListThreeDHWordIndexed";
312 let ParserMethod = "parseVectorList";
313 let RenderMethod = "addVecListIndexedOperands";
315 def VecListThreeDHWordIndexed : Operand<i32> {
316 let ParserMatchClass = VecListThreeDHWordIndexAsmOperand;
317 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
319 // ...with word lane subscripting.
320 def VecListThreeDWordIndexAsmOperand : AsmOperandClass {
321 let Name = "VecListThreeDWordIndexed";
322 let ParserMethod = "parseVectorList";
323 let RenderMethod = "addVecListIndexedOperands";
325 def VecListThreeDWordIndexed : Operand<i32> {
326 let ParserMatchClass = VecListThreeDWordIndexAsmOperand;
327 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
329 // Register list of three Q registers with half-word lane subscripting.
330 def VecListThreeQHWordIndexAsmOperand : AsmOperandClass {
331 let Name = "VecListThreeQHWordIndexed";
332 let ParserMethod = "parseVectorList";
333 let RenderMethod = "addVecListIndexedOperands";
335 def VecListThreeQHWordIndexed : Operand<i32> {
336 let ParserMatchClass = VecListThreeQHWordIndexAsmOperand;
337 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
339 // ...with word lane subscripting.
340 def VecListThreeQWordIndexAsmOperand : AsmOperandClass {
341 let Name = "VecListThreeQWordIndexed";
342 let ParserMethod = "parseVectorList";
343 let RenderMethod = "addVecListIndexedOperands";
345 def VecListThreeQWordIndexed : Operand<i32> {
346 let ParserMatchClass = VecListThreeQWordIndexAsmOperand;
347 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
350 // Register list of four D registers with byte lane subscripting.
351 def VecListFourDByteIndexAsmOperand : AsmOperandClass {
352 let Name = "VecListFourDByteIndexed";
353 let ParserMethod = "parseVectorList";
354 let RenderMethod = "addVecListIndexedOperands";
356 def VecListFourDByteIndexed : Operand<i32> {
357 let ParserMatchClass = VecListFourDByteIndexAsmOperand;
358 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
360 // ...with half-word lane subscripting.
361 def VecListFourDHWordIndexAsmOperand : AsmOperandClass {
362 let Name = "VecListFourDHWordIndexed";
363 let ParserMethod = "parseVectorList";
364 let RenderMethod = "addVecListIndexedOperands";
366 def VecListFourDHWordIndexed : Operand<i32> {
367 let ParserMatchClass = VecListFourDHWordIndexAsmOperand;
368 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
370 // ...with word lane subscripting.
371 def VecListFourDWordIndexAsmOperand : AsmOperandClass {
372 let Name = "VecListFourDWordIndexed";
373 let ParserMethod = "parseVectorList";
374 let RenderMethod = "addVecListIndexedOperands";
376 def VecListFourDWordIndexed : Operand<i32> {
377 let ParserMatchClass = VecListFourDWordIndexAsmOperand;
378 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
380 // Register list of four Q registers with half-word lane subscripting.
381 def VecListFourQHWordIndexAsmOperand : AsmOperandClass {
382 let Name = "VecListFourQHWordIndexed";
383 let ParserMethod = "parseVectorList";
384 let RenderMethod = "addVecListIndexedOperands";
386 def VecListFourQHWordIndexed : Operand<i32> {
387 let ParserMatchClass = VecListFourQHWordIndexAsmOperand;
388 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
390 // ...with word lane subscripting.
391 def VecListFourQWordIndexAsmOperand : AsmOperandClass {
392 let Name = "VecListFourQWordIndexed";
393 let ParserMethod = "parseVectorList";
394 let RenderMethod = "addVecListIndexedOperands";
396 def VecListFourQWordIndexed : Operand<i32> {
397 let ParserMatchClass = VecListFourQWordIndexAsmOperand;
398 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
401 def dword_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
402 return cast<LoadSDNode>(N)->getAlignment() >= 8;
404 def dword_alignedstore : PatFrag<(ops node:$val, node:$ptr),
405 (store node:$val, node:$ptr), [{
406 return cast<StoreSDNode>(N)->getAlignment() >= 8;
408 def word_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
409 return cast<LoadSDNode>(N)->getAlignment() == 4;
411 def word_alignedstore : PatFrag<(ops node:$val, node:$ptr),
412 (store node:$val, node:$ptr), [{
413 return cast<StoreSDNode>(N)->getAlignment() == 4;
415 def hword_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
416 return cast<LoadSDNode>(N)->getAlignment() == 2;
418 def hword_alignedstore : PatFrag<(ops node:$val, node:$ptr),
419 (store node:$val, node:$ptr), [{
420 return cast<StoreSDNode>(N)->getAlignment() == 2;
422 def byte_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
423 return cast<LoadSDNode>(N)->getAlignment() == 1;
425 def byte_alignedstore : PatFrag<(ops node:$val, node:$ptr),
426 (store node:$val, node:$ptr), [{
427 return cast<StoreSDNode>(N)->getAlignment() == 1;
429 def non_word_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
430 return cast<LoadSDNode>(N)->getAlignment() < 4;
432 def non_word_alignedstore : PatFrag<(ops node:$val, node:$ptr),
433 (store node:$val, node:$ptr), [{
434 return cast<StoreSDNode>(N)->getAlignment() < 4;
437 //===----------------------------------------------------------------------===//
438 // NEON-specific DAG Nodes.
439 //===----------------------------------------------------------------------===//
441 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
442 def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
444 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
445 def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
446 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
447 def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
448 def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
449 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
450 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
451 def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
452 def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
453 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
454 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
456 // Types for vector shift by immediates. The "SHX" version is for long and
457 // narrow operations where the source and destination vectors have different
458 // types. The "SHINS" version is for shift and insert operations.
459 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
461 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
463 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
464 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
466 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
467 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
468 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
469 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
470 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
471 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
472 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
474 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
475 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
476 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
478 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
479 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
480 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
481 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
482 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
483 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
485 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
486 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
487 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
489 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
490 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
492 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
494 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
495 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
497 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
498 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
499 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
500 def NEONvmovFPImm : SDNode<"ARMISD::VMOVFPIMM", SDTARMVMOVIMM>;
502 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
504 def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
505 def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
507 def NEONvbsl : SDNode<"ARMISD::VBSL",
508 SDTypeProfile<1, 3, [SDTCisVec<0>,
511 SDTCisSameAs<0, 3>]>>;
513 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
515 // VDUPLANE can produce a quad-register result from a double-register source,
516 // so the result is not constrained to match the source.
517 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
518 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
521 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
522 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
523 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
525 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
526 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
527 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
528 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
530 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
532 SDTCisSameAs<0, 3>]>;
533 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
534 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
535 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
537 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
538 SDTCisSameAs<1, 2>]>;
539 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
540 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
542 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
543 SDTCisSameAs<0, 2>]>;
544 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
545 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
547 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
548 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
549 unsigned EltBits = 0;
550 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
551 return (EltBits == 32 && EltVal == 0);
554 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
555 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
556 unsigned EltBits = 0;
557 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
558 return (EltBits == 8 && EltVal == 0xff);
561 //===----------------------------------------------------------------------===//
562 // NEON load / store instructions
563 //===----------------------------------------------------------------------===//
565 // Use VLDM to load a Q register as a D register pair.
566 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
568 : PseudoVFPLdStM<(outs DPair:$dst), (ins GPR:$Rn),
570 [(set DPair:$dst, (v2f64 (load GPR:$Rn)))]>;
572 // Use VSTM to store a Q register as a D register pair.
573 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
575 : PseudoVFPLdStM<(outs), (ins DPair:$src, GPR:$Rn),
577 [(store (v2f64 DPair:$src), GPR:$Rn)]>;
579 // Classes for VLD* pseudo-instructions with multi-register operands.
580 // These are expanded to real instructions after register allocation.
581 class VLDQPseudo<InstrItinClass itin>
582 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
583 class VLDQWBPseudo<InstrItinClass itin>
584 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
585 (ins addrmode6:$addr, am6offset:$offset), itin,
587 class VLDQWBfixedPseudo<InstrItinClass itin>
588 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
589 (ins addrmode6:$addr), itin,
591 class VLDQWBregisterPseudo<InstrItinClass itin>
592 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
593 (ins addrmode6:$addr, rGPR:$offset), itin,
596 class VLDQQPseudo<InstrItinClass itin>
597 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
598 class VLDQQWBPseudo<InstrItinClass itin>
599 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
600 (ins addrmode6:$addr, am6offset:$offset), itin,
602 class VLDQQWBfixedPseudo<InstrItinClass itin>
603 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
604 (ins addrmode6:$addr), itin,
606 class VLDQQWBregisterPseudo<InstrItinClass itin>
607 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
608 (ins addrmode6:$addr, rGPR:$offset), itin,
612 class VLDQQQQPseudo<InstrItinClass itin>
613 : PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src),itin,
615 class VLDQQQQWBPseudo<InstrItinClass itin>
616 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
617 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
618 "$addr.addr = $wb, $src = $dst">;
620 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
622 // VLD1 : Vector Load (multiple single elements)
623 class VLD1D<bits<4> op7_4, string Dt>
624 : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd),
625 (ins addrmode6:$Rn), IIC_VLD1,
626 "vld1", Dt, "$Vd, $Rn", "", []> {
629 let DecoderMethod = "DecodeVLDST1Instruction";
631 class VLD1Q<bits<4> op7_4, string Dt>
632 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd),
633 (ins addrmode6:$Rn), IIC_VLD1x2,
634 "vld1", Dt, "$Vd, $Rn", "", []> {
636 let Inst{5-4} = Rn{5-4};
637 let DecoderMethod = "DecodeVLDST1Instruction";
640 def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
641 def VLD1d16 : VLD1D<{0,1,0,?}, "16">;
642 def VLD1d32 : VLD1D<{1,0,0,?}, "32">;
643 def VLD1d64 : VLD1D<{1,1,0,?}, "64">;
645 def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;
646 def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
647 def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
648 def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
650 // ...with address register writeback:
651 multiclass VLD1DWB<bits<4> op7_4, string Dt> {
652 def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
653 (ins addrmode6:$Rn), IIC_VLD1u,
654 "vld1", Dt, "$Vd, $Rn!",
655 "$Rn.addr = $wb", []> {
656 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
658 let DecoderMethod = "DecodeVLDST1Instruction";
660 def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
661 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1u,
662 "vld1", Dt, "$Vd, $Rn, $Rm",
663 "$Rn.addr = $wb", []> {
665 let DecoderMethod = "DecodeVLDST1Instruction";
668 multiclass VLD1QWB<bits<4> op7_4, string Dt> {
669 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
670 (ins addrmode6:$Rn), IIC_VLD1x2u,
671 "vld1", Dt, "$Vd, $Rn!",
672 "$Rn.addr = $wb", []> {
673 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
674 let Inst{5-4} = Rn{5-4};
675 let DecoderMethod = "DecodeVLDST1Instruction";
677 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
678 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
679 "vld1", Dt, "$Vd, $Rn, $Rm",
680 "$Rn.addr = $wb", []> {
681 let Inst{5-4} = Rn{5-4};
682 let DecoderMethod = "DecodeVLDST1Instruction";
686 defm VLD1d8wb : VLD1DWB<{0,0,0,?}, "8">;
687 defm VLD1d16wb : VLD1DWB<{0,1,0,?}, "16">;
688 defm VLD1d32wb : VLD1DWB<{1,0,0,?}, "32">;
689 defm VLD1d64wb : VLD1DWB<{1,1,0,?}, "64">;
690 defm VLD1q8wb : VLD1QWB<{0,0,?,?}, "8">;
691 defm VLD1q16wb : VLD1QWB<{0,1,?,?}, "16">;
692 defm VLD1q32wb : VLD1QWB<{1,0,?,?}, "32">;
693 defm VLD1q64wb : VLD1QWB<{1,1,?,?}, "64">;
695 // ...with 3 registers
696 class VLD1D3<bits<4> op7_4, string Dt>
697 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd),
698 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
699 "$Vd, $Rn", "", []> {
702 let DecoderMethod = "DecodeVLDST1Instruction";
704 multiclass VLD1D3WB<bits<4> op7_4, string Dt> {
705 def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
706 (ins addrmode6:$Rn), IIC_VLD1x2u,
707 "vld1", Dt, "$Vd, $Rn!",
708 "$Rn.addr = $wb", []> {
709 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
711 let DecoderMethod = "DecodeVLDST1Instruction";
713 def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
714 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
715 "vld1", Dt, "$Vd, $Rn, $Rm",
716 "$Rn.addr = $wb", []> {
718 let DecoderMethod = "DecodeVLDST1Instruction";
722 def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
723 def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;
724 def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;
725 def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;
727 defm VLD1d8Twb : VLD1D3WB<{0,0,0,?}, "8">;
728 defm VLD1d16Twb : VLD1D3WB<{0,1,0,?}, "16">;
729 defm VLD1d32Twb : VLD1D3WB<{1,0,0,?}, "32">;
730 defm VLD1d64Twb : VLD1D3WB<{1,1,0,?}, "64">;
732 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
733 def VLD1d64TPseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD1x3>;
734 def VLD1d64TPseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD1x3>;
736 // ...with 4 registers
737 class VLD1D4<bits<4> op7_4, string Dt>
738 : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd),
739 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
740 "$Vd, $Rn", "", []> {
742 let Inst{5-4} = Rn{5-4};
743 let DecoderMethod = "DecodeVLDST1Instruction";
745 multiclass VLD1D4WB<bits<4> op7_4, string Dt> {
746 def _fixed : NLdSt<0,0b10,0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb),
747 (ins addrmode6:$Rn), IIC_VLD1x2u,
748 "vld1", Dt, "$Vd, $Rn!",
749 "$Rn.addr = $wb", []> {
750 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
751 let Inst{5-4} = Rn{5-4};
752 let DecoderMethod = "DecodeVLDST1Instruction";
754 def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb),
755 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
756 "vld1", Dt, "$Vd, $Rn, $Rm",
757 "$Rn.addr = $wb", []> {
758 let Inst{5-4} = Rn{5-4};
759 let DecoderMethod = "DecodeVLDST1Instruction";
763 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
764 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;
765 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;
766 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;
768 defm VLD1d8Qwb : VLD1D4WB<{0,0,?,?}, "8">;
769 defm VLD1d16Qwb : VLD1D4WB<{0,1,?,?}, "16">;
770 defm VLD1d32Qwb : VLD1D4WB<{1,0,?,?}, "32">;
771 defm VLD1d64Qwb : VLD1D4WB<{1,1,?,?}, "64">;
773 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
774 def VLD1d64QPseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD1x4>;
775 def VLD1d64QPseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD1x4>;
777 // VLD2 : Vector Load (multiple 2-element structures)
778 class VLD2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
780 : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd),
781 (ins addrmode6:$Rn), itin,
782 "vld2", Dt, "$Vd, $Rn", "", []> {
784 let Inst{5-4} = Rn{5-4};
785 let DecoderMethod = "DecodeVLDST2Instruction";
788 def VLD2d8 : VLD2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2>;
789 def VLD2d16 : VLD2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2>;
790 def VLD2d32 : VLD2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2>;
792 def VLD2q8 : VLD2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2>;
793 def VLD2q16 : VLD2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2>;
794 def VLD2q32 : VLD2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2>;
796 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
797 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
798 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
800 // ...with address register writeback:
801 multiclass VLD2WB<bits<4> op11_8, bits<4> op7_4, string Dt,
802 RegisterOperand VdTy, InstrItinClass itin> {
803 def _fixed : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
804 (ins addrmode6:$Rn), itin,
805 "vld2", Dt, "$Vd, $Rn!",
806 "$Rn.addr = $wb", []> {
807 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
808 let Inst{5-4} = Rn{5-4};
809 let DecoderMethod = "DecodeVLDST2Instruction";
811 def _register : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
812 (ins addrmode6:$Rn, rGPR:$Rm), itin,
813 "vld2", Dt, "$Vd, $Rn, $Rm",
814 "$Rn.addr = $wb", []> {
815 let Inst{5-4} = Rn{5-4};
816 let DecoderMethod = "DecodeVLDST2Instruction";
820 defm VLD2d8wb : VLD2WB<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2u>;
821 defm VLD2d16wb : VLD2WB<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2u>;
822 defm VLD2d32wb : VLD2WB<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2u>;
824 defm VLD2q8wb : VLD2WB<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2u>;
825 defm VLD2q16wb : VLD2WB<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2u>;
826 defm VLD2q32wb : VLD2WB<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2u>;
828 def VLD2q8PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
829 def VLD2q16PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
830 def VLD2q32PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
831 def VLD2q8PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
832 def VLD2q16PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
833 def VLD2q32PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
835 // ...with double-spaced registers
836 def VLD2b8 : VLD2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2>;
837 def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2>;
838 def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2>;
839 defm VLD2b8wb : VLD2WB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2u>;
840 defm VLD2b16wb : VLD2WB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2u>;
841 defm VLD2b32wb : VLD2WB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2u>;
843 // VLD3 : Vector Load (multiple 3-element structures)
844 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
845 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
846 (ins addrmode6:$Rn), IIC_VLD3,
847 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
850 let DecoderMethod = "DecodeVLDST3Instruction";
853 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
854 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
855 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
857 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
858 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
859 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
861 // ...with address register writeback:
862 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
863 : NLdSt<0, 0b10, op11_8, op7_4,
864 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
865 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
866 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
867 "$Rn.addr = $wb", []> {
869 let DecoderMethod = "DecodeVLDST3Instruction";
872 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
873 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
874 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
876 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
877 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
878 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
880 // ...with double-spaced registers:
881 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
882 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
883 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
884 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
885 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
886 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
888 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
889 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
890 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
892 // ...alternate versions to be allocated odd register numbers:
893 def VLD3q8oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
894 def VLD3q16oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
895 def VLD3q32oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
897 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
898 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
899 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
901 // VLD4 : Vector Load (multiple 4-element structures)
902 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
903 : NLdSt<0, 0b10, op11_8, op7_4,
904 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
905 (ins addrmode6:$Rn), IIC_VLD4,
906 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
908 let Inst{5-4} = Rn{5-4};
909 let DecoderMethod = "DecodeVLDST4Instruction";
912 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
913 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
914 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
916 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
917 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
918 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
920 // ...with address register writeback:
921 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
922 : NLdSt<0, 0b10, op11_8, op7_4,
923 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
924 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u,
925 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
926 "$Rn.addr = $wb", []> {
927 let Inst{5-4} = Rn{5-4};
928 let DecoderMethod = "DecodeVLDST4Instruction";
931 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
932 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
933 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
935 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
936 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
937 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
939 // ...with double-spaced registers:
940 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
941 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
942 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
943 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
944 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
945 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
947 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
948 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
949 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
951 // ...alternate versions to be allocated odd register numbers:
952 def VLD4q8oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
953 def VLD4q16oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
954 def VLD4q32oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
956 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
957 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
958 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
960 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
962 // Classes for VLD*LN pseudo-instructions with multi-register operands.
963 // These are expanded to real instructions after register allocation.
964 class VLDQLNPseudo<InstrItinClass itin>
965 : PseudoNLdSt<(outs QPR:$dst),
966 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
967 itin, "$src = $dst">;
968 class VLDQLNWBPseudo<InstrItinClass itin>
969 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
970 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
971 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
972 class VLDQQLNPseudo<InstrItinClass itin>
973 : PseudoNLdSt<(outs QQPR:$dst),
974 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
975 itin, "$src = $dst">;
976 class VLDQQLNWBPseudo<InstrItinClass itin>
977 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
978 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
979 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
980 class VLDQQQQLNPseudo<InstrItinClass itin>
981 : PseudoNLdSt<(outs QQQQPR:$dst),
982 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
983 itin, "$src = $dst">;
984 class VLDQQQQLNWBPseudo<InstrItinClass itin>
985 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
986 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
987 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
989 // VLD1LN : Vector Load (single element to one lane)
990 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
992 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
993 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
994 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
996 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
997 (i32 (LoadOp addrmode6:$Rn)),
1000 let DecoderMethod = "DecodeVLD1LN";
1002 class VLD1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1004 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
1005 (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane),
1006 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
1008 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
1009 (i32 (LoadOp addrmode6oneL32:$Rn)),
1012 let DecoderMethod = "DecodeVLD1LN";
1014 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
1015 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
1016 (i32 (LoadOp addrmode6:$addr)),
1020 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
1021 let Inst{7-5} = lane{2-0};
1023 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
1024 let Inst{7-6} = lane{1-0};
1025 let Inst{5-4} = Rn{5-4};
1027 def VLD1LNd32 : VLD1LN32<0b1000, {?,0,?,?}, "32", v2i32, load> {
1028 let Inst{7} = lane{0};
1029 let Inst{5-4} = Rn{5-4};
1032 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
1033 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
1034 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
1036 def : Pat<(vector_insert (v2f32 DPR:$src),
1037 (f32 (load addrmode6:$addr)), imm:$lane),
1038 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1039 def : Pat<(vector_insert (v4f32 QPR:$src),
1040 (f32 (load addrmode6:$addr)), imm:$lane),
1041 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1043 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1045 // ...with address register writeback:
1046 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1047 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
1048 (ins addrmode6:$Rn, am6offset:$Rm,
1049 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
1050 "\\{$Vd[$lane]\\}, $Rn$Rm",
1051 "$src = $Vd, $Rn.addr = $wb", []> {
1052 let DecoderMethod = "DecodeVLD1LN";
1055 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
1056 let Inst{7-5} = lane{2-0};
1058 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
1059 let Inst{7-6} = lane{1-0};
1060 let Inst{4} = Rn{4};
1062 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
1063 let Inst{7} = lane{0};
1064 let Inst{5} = Rn{4};
1065 let Inst{4} = Rn{4};
1068 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
1069 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
1070 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
1072 // VLD2LN : Vector Load (single 2-element structure to one lane)
1073 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1074 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
1075 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
1076 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
1077 "$src1 = $Vd, $src2 = $dst2", []> {
1079 let Inst{4} = Rn{4};
1080 let DecoderMethod = "DecodeVLD2LN";
1083 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
1084 let Inst{7-5} = lane{2-0};
1086 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
1087 let Inst{7-6} = lane{1-0};
1089 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
1090 let Inst{7} = lane{0};
1093 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
1094 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
1095 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
1097 // ...with double-spaced registers:
1098 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
1099 let Inst{7-6} = lane{1-0};
1101 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
1102 let Inst{7} = lane{0};
1105 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
1106 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
1108 // ...with address register writeback:
1109 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1110 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
1111 (ins addrmode6:$Rn, am6offset:$Rm,
1112 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
1113 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
1114 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
1115 let Inst{4} = Rn{4};
1116 let DecoderMethod = "DecodeVLD2LN";
1119 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
1120 let Inst{7-5} = lane{2-0};
1122 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
1123 let Inst{7-6} = lane{1-0};
1125 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
1126 let Inst{7} = lane{0};
1129 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
1130 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
1131 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
1133 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
1134 let Inst{7-6} = lane{1-0};
1136 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
1137 let Inst{7} = lane{0};
1140 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
1141 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
1143 // VLD3LN : Vector Load (single 3-element structure to one lane)
1144 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1145 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1146 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
1147 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
1148 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
1149 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
1151 let DecoderMethod = "DecodeVLD3LN";
1154 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
1155 let Inst{7-5} = lane{2-0};
1157 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
1158 let Inst{7-6} = lane{1-0};
1160 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
1161 let Inst{7} = lane{0};
1164 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1165 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1166 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1168 // ...with double-spaced registers:
1169 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
1170 let Inst{7-6} = lane{1-0};
1172 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
1173 let Inst{7} = lane{0};
1176 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
1177 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
1179 // ...with address register writeback:
1180 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1181 : NLdStLn<1, 0b10, op11_8, op7_4,
1182 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1183 (ins addrmode6:$Rn, am6offset:$Rm,
1184 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1185 IIC_VLD3lnu, "vld3", Dt,
1186 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
1187 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
1189 let DecoderMethod = "DecodeVLD3LN";
1192 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
1193 let Inst{7-5} = lane{2-0};
1195 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
1196 let Inst{7-6} = lane{1-0};
1198 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
1199 let Inst{7} = lane{0};
1202 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1203 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1204 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1206 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
1207 let Inst{7-6} = lane{1-0};
1209 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
1210 let Inst{7} = lane{0};
1213 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
1214 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
1216 // VLD4LN : Vector Load (single 4-element structure to one lane)
1217 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1218 : NLdStLn<1, 0b10, op11_8, op7_4,
1219 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1220 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
1221 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
1222 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
1223 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
1225 let Inst{4} = Rn{4};
1226 let DecoderMethod = "DecodeVLD4LN";
1229 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
1230 let Inst{7-5} = lane{2-0};
1232 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
1233 let Inst{7-6} = lane{1-0};
1235 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
1236 let Inst{7} = lane{0};
1237 let Inst{5} = Rn{5};
1240 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1241 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1242 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1244 // ...with double-spaced registers:
1245 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
1246 let Inst{7-6} = lane{1-0};
1248 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
1249 let Inst{7} = lane{0};
1250 let Inst{5} = Rn{5};
1253 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
1254 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
1256 // ...with address register writeback:
1257 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1258 : NLdStLn<1, 0b10, op11_8, op7_4,
1259 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1260 (ins addrmode6:$Rn, am6offset:$Rm,
1261 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1262 IIC_VLD4lnu, "vld4", Dt,
1263 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
1264 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
1266 let Inst{4} = Rn{4};
1267 let DecoderMethod = "DecodeVLD4LN" ;
1270 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
1271 let Inst{7-5} = lane{2-0};
1273 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
1274 let Inst{7-6} = lane{1-0};
1276 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
1277 let Inst{7} = lane{0};
1278 let Inst{5} = Rn{5};
1281 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1282 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1283 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1285 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
1286 let Inst{7-6} = lane{1-0};
1288 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
1289 let Inst{7} = lane{0};
1290 let Inst{5} = Rn{5};
1293 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
1294 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
1296 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1298 // VLD1DUP : Vector Load (single element to all lanes)
1299 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
1300 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd),
1301 (ins addrmode6dup:$Rn),
1302 IIC_VLD1dup, "vld1", Dt, "$Vd, $Rn", "",
1303 [(set VecListOneDAllLanes:$Vd,
1304 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
1306 let Inst{4} = Rn{4};
1307 let DecoderMethod = "DecodeVLD1DupInstruction";
1309 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
1310 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;
1311 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;
1313 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1314 (VLD1DUPd32 addrmode6:$addr)>;
1316 class VLD1QDUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
1317 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListDPairAllLanes:$Vd),
1318 (ins addrmode6dup:$Rn), IIC_VLD1dup,
1319 "vld1", Dt, "$Vd, $Rn", "",
1320 [(set VecListDPairAllLanes:$Vd,
1321 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
1323 let Inst{4} = Rn{4};
1324 let DecoderMethod = "DecodeVLD1DupInstruction";
1327 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8", v16i8, extloadi8>;
1328 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16", v8i16, extloadi16>;
1329 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32", v4i32, load>;
1331 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1332 (VLD1DUPq32 addrmode6:$addr)>;
1334 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1335 // ...with address register writeback:
1336 multiclass VLD1DUPWB<bits<4> op7_4, string Dt> {
1337 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1338 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1339 (ins addrmode6dup:$Rn), IIC_VLD1dupu,
1340 "vld1", Dt, "$Vd, $Rn!",
1341 "$Rn.addr = $wb", []> {
1342 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1343 let Inst{4} = Rn{4};
1344 let DecoderMethod = "DecodeVLD1DupInstruction";
1346 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1347 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1348 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1349 "vld1", Dt, "$Vd, $Rn, $Rm",
1350 "$Rn.addr = $wb", []> {
1351 let Inst{4} = Rn{4};
1352 let DecoderMethod = "DecodeVLD1DupInstruction";
1355 multiclass VLD1QDUPWB<bits<4> op7_4, string Dt> {
1356 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1357 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
1358 (ins addrmode6dup:$Rn), IIC_VLD1dupu,
1359 "vld1", Dt, "$Vd, $Rn!",
1360 "$Rn.addr = $wb", []> {
1361 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1362 let Inst{4} = Rn{4};
1363 let DecoderMethod = "DecodeVLD1DupInstruction";
1365 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1366 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
1367 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1368 "vld1", Dt, "$Vd, $Rn, $Rm",
1369 "$Rn.addr = $wb", []> {
1370 let Inst{4} = Rn{4};
1371 let DecoderMethod = "DecodeVLD1DupInstruction";
1375 defm VLD1DUPd8wb : VLD1DUPWB<{0,0,0,0}, "8">;
1376 defm VLD1DUPd16wb : VLD1DUPWB<{0,1,0,?}, "16">;
1377 defm VLD1DUPd32wb : VLD1DUPWB<{1,0,0,?}, "32">;
1379 defm VLD1DUPq8wb : VLD1QDUPWB<{0,0,1,0}, "8">;
1380 defm VLD1DUPq16wb : VLD1QDUPWB<{0,1,1,?}, "16">;
1381 defm VLD1DUPq32wb : VLD1QDUPWB<{1,0,1,?}, "32">;
1383 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
1384 class VLD2DUP<bits<4> op7_4, string Dt, RegisterOperand VdTy>
1385 : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd),
1386 (ins addrmode6dup:$Rn), IIC_VLD2dup,
1387 "vld2", Dt, "$Vd, $Rn", "", []> {
1389 let Inst{4} = Rn{4};
1390 let DecoderMethod = "DecodeVLD2DupInstruction";
1393 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListDPairAllLanes>;
1394 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes>;
1395 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes>;
1397 // ...with double-spaced registers
1398 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListDPairSpacedAllLanes>;
1399 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListDPairSpacedAllLanes>;
1400 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListDPairSpacedAllLanes>;
1402 // ...with address register writeback:
1403 multiclass VLD2DUPWB<bits<4> op7_4, string Dt, RegisterOperand VdTy> {
1404 def _fixed : NLdSt<1, 0b10, 0b1101, op7_4,
1405 (outs VdTy:$Vd, GPR:$wb),
1406 (ins addrmode6dup:$Rn), IIC_VLD2dupu,
1407 "vld2", Dt, "$Vd, $Rn!",
1408 "$Rn.addr = $wb", []> {
1409 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1410 let Inst{4} = Rn{4};
1411 let DecoderMethod = "DecodeVLD2DupInstruction";
1413 def _register : NLdSt<1, 0b10, 0b1101, op7_4,
1414 (outs VdTy:$Vd, GPR:$wb),
1415 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD2dupu,
1416 "vld2", Dt, "$Vd, $Rn, $Rm",
1417 "$Rn.addr = $wb", []> {
1418 let Inst{4} = Rn{4};
1419 let DecoderMethod = "DecodeVLD2DupInstruction";
1423 defm VLD2DUPd8wb : VLD2DUPWB<{0,0,0,0}, "8", VecListDPairAllLanes>;
1424 defm VLD2DUPd16wb : VLD2DUPWB<{0,1,0,?}, "16", VecListDPairAllLanes>;
1425 defm VLD2DUPd32wb : VLD2DUPWB<{1,0,0,?}, "32", VecListDPairAllLanes>;
1427 defm VLD2DUPd8x2wb : VLD2DUPWB<{0,0,1,0}, "8", VecListDPairSpacedAllLanes>;
1428 defm VLD2DUPd16x2wb : VLD2DUPWB<{0,1,1,?}, "16", VecListDPairSpacedAllLanes>;
1429 defm VLD2DUPd32x2wb : VLD2DUPWB<{1,0,1,?}, "32", VecListDPairSpacedAllLanes>;
1431 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
1432 class VLD3DUP<bits<4> op7_4, string Dt>
1433 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1434 (ins addrmode6dup:$Rn), IIC_VLD3dup,
1435 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
1438 let DecoderMethod = "DecodeVLD3DupInstruction";
1441 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
1442 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
1443 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
1445 def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1446 def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1447 def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1449 // ...with double-spaced registers (not used for codegen):
1450 def VLD3DUPq8 : VLD3DUP<{0,0,1,?}, "8">;
1451 def VLD3DUPq16 : VLD3DUP<{0,1,1,?}, "16">;
1452 def VLD3DUPq32 : VLD3DUP<{1,0,1,?}, "32">;
1454 // ...with address register writeback:
1455 class VLD3DUPWB<bits<4> op7_4, string Dt>
1456 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1457 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu,
1458 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
1459 "$Rn.addr = $wb", []> {
1461 let DecoderMethod = "DecodeVLD3DupInstruction";
1464 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;
1465 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">;
1466 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">;
1468 def VLD3DUPq8_UPD : VLD3DUPWB<{0,0,1,0}, "8">;
1469 def VLD3DUPq16_UPD : VLD3DUPWB<{0,1,1,?}, "16">;
1470 def VLD3DUPq32_UPD : VLD3DUPWB<{1,0,1,?}, "32">;
1472 def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1473 def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1474 def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1476 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1477 class VLD4DUP<bits<4> op7_4, string Dt>
1478 : NLdSt<1, 0b10, 0b1111, op7_4,
1479 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1480 (ins addrmode6dup:$Rn), IIC_VLD4dup,
1481 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
1483 let Inst{4} = Rn{4};
1484 let DecoderMethod = "DecodeVLD4DupInstruction";
1487 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1488 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1489 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1491 def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1492 def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1493 def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1495 // ...with double-spaced registers (not used for codegen):
1496 def VLD4DUPq8 : VLD4DUP<{0,0,1,?}, "8">;
1497 def VLD4DUPq16 : VLD4DUP<{0,1,1,?}, "16">;
1498 def VLD4DUPq32 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1500 // ...with address register writeback:
1501 class VLD4DUPWB<bits<4> op7_4, string Dt>
1502 : NLdSt<1, 0b10, 0b1111, op7_4,
1503 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1504 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
1505 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
1506 "$Rn.addr = $wb", []> {
1507 let Inst{4} = Rn{4};
1508 let DecoderMethod = "DecodeVLD4DupInstruction";
1511 def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">;
1512 def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">;
1513 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1515 def VLD4DUPq8_UPD : VLD4DUPWB<{0,0,1,0}, "8">;
1516 def VLD4DUPq16_UPD : VLD4DUPWB<{0,1,1,?}, "16">;
1517 def VLD4DUPq32_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1519 def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1520 def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1521 def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1523 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1525 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1527 // Classes for VST* pseudo-instructions with multi-register operands.
1528 // These are expanded to real instructions after register allocation.
1529 class VSTQPseudo<InstrItinClass itin>
1530 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1531 class VSTQWBPseudo<InstrItinClass itin>
1532 : PseudoNLdSt<(outs GPR:$wb),
1533 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1534 "$addr.addr = $wb">;
1535 class VSTQWBfixedPseudo<InstrItinClass itin>
1536 : PseudoNLdSt<(outs GPR:$wb),
1537 (ins addrmode6:$addr, QPR:$src), itin,
1538 "$addr.addr = $wb">;
1539 class VSTQWBregisterPseudo<InstrItinClass itin>
1540 : PseudoNLdSt<(outs GPR:$wb),
1541 (ins addrmode6:$addr, rGPR:$offset, QPR:$src), itin,
1542 "$addr.addr = $wb">;
1543 class VSTQQPseudo<InstrItinClass itin>
1544 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
1545 class VSTQQWBPseudo<InstrItinClass itin>
1546 : PseudoNLdSt<(outs GPR:$wb),
1547 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
1548 "$addr.addr = $wb">;
1549 class VSTQQWBfixedPseudo<InstrItinClass itin>
1550 : PseudoNLdSt<(outs GPR:$wb),
1551 (ins addrmode6:$addr, QQPR:$src), itin,
1552 "$addr.addr = $wb">;
1553 class VSTQQWBregisterPseudo<InstrItinClass itin>
1554 : PseudoNLdSt<(outs GPR:$wb),
1555 (ins addrmode6:$addr, rGPR:$offset, QQPR:$src), itin,
1556 "$addr.addr = $wb">;
1558 class VSTQQQQPseudo<InstrItinClass itin>
1559 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src), itin, "">;
1560 class VSTQQQQWBPseudo<InstrItinClass itin>
1561 : PseudoNLdSt<(outs GPR:$wb),
1562 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
1563 "$addr.addr = $wb">;
1565 // VST1 : Vector Store (multiple single elements)
1566 class VST1D<bits<4> op7_4, string Dt>
1567 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, VecListOneD:$Vd),
1568 IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []> {
1570 let Inst{4} = Rn{4};
1571 let DecoderMethod = "DecodeVLDST1Instruction";
1573 class VST1Q<bits<4> op7_4, string Dt>
1574 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$Rn, VecListDPair:$Vd),
1575 IIC_VST1x2, "vst1", Dt, "$Vd, $Rn", "", []> {
1577 let Inst{5-4} = Rn{5-4};
1578 let DecoderMethod = "DecodeVLDST1Instruction";
1581 def VST1d8 : VST1D<{0,0,0,?}, "8">;
1582 def VST1d16 : VST1D<{0,1,0,?}, "16">;
1583 def VST1d32 : VST1D<{1,0,0,?}, "32">;
1584 def VST1d64 : VST1D<{1,1,0,?}, "64">;
1586 def VST1q8 : VST1Q<{0,0,?,?}, "8">;
1587 def VST1q16 : VST1Q<{0,1,?,?}, "16">;
1588 def VST1q32 : VST1Q<{1,0,?,?}, "32">;
1589 def VST1q64 : VST1Q<{1,1,?,?}, "64">;
1591 // ...with address register writeback:
1592 multiclass VST1DWB<bits<4> op7_4, string Dt> {
1593 def _fixed : NLdSt<0,0b00, 0b0111,op7_4, (outs GPR:$wb),
1594 (ins addrmode6:$Rn, VecListOneD:$Vd), IIC_VLD1u,
1595 "vst1", Dt, "$Vd, $Rn!",
1596 "$Rn.addr = $wb", []> {
1597 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1598 let Inst{4} = Rn{4};
1599 let DecoderMethod = "DecodeVLDST1Instruction";
1601 def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb),
1602 (ins addrmode6:$Rn, rGPR:$Rm, VecListOneD:$Vd),
1604 "vst1", Dt, "$Vd, $Rn, $Rm",
1605 "$Rn.addr = $wb", []> {
1606 let Inst{4} = Rn{4};
1607 let DecoderMethod = "DecodeVLDST1Instruction";
1610 multiclass VST1QWB<bits<4> op7_4, string Dt> {
1611 def _fixed : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1612 (ins addrmode6:$Rn, VecListDPair:$Vd), IIC_VLD1x2u,
1613 "vst1", Dt, "$Vd, $Rn!",
1614 "$Rn.addr = $wb", []> {
1615 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1616 let Inst{5-4} = Rn{5-4};
1617 let DecoderMethod = "DecodeVLDST1Instruction";
1619 def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1620 (ins addrmode6:$Rn, rGPR:$Rm, VecListDPair:$Vd),
1622 "vst1", Dt, "$Vd, $Rn, $Rm",
1623 "$Rn.addr = $wb", []> {
1624 let Inst{5-4} = Rn{5-4};
1625 let DecoderMethod = "DecodeVLDST1Instruction";
1629 defm VST1d8wb : VST1DWB<{0,0,0,?}, "8">;
1630 defm VST1d16wb : VST1DWB<{0,1,0,?}, "16">;
1631 defm VST1d32wb : VST1DWB<{1,0,0,?}, "32">;
1632 defm VST1d64wb : VST1DWB<{1,1,0,?}, "64">;
1634 defm VST1q8wb : VST1QWB<{0,0,?,?}, "8">;
1635 defm VST1q16wb : VST1QWB<{0,1,?,?}, "16">;
1636 defm VST1q32wb : VST1QWB<{1,0,?,?}, "32">;
1637 defm VST1q64wb : VST1QWB<{1,1,?,?}, "64">;
1639 // ...with 3 registers
1640 class VST1D3<bits<4> op7_4, string Dt>
1641 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1642 (ins addrmode6:$Rn, VecListThreeD:$Vd),
1643 IIC_VST1x3, "vst1", Dt, "$Vd, $Rn", "", []> {
1645 let Inst{4} = Rn{4};
1646 let DecoderMethod = "DecodeVLDST1Instruction";
1648 multiclass VST1D3WB<bits<4> op7_4, string Dt> {
1649 def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1650 (ins addrmode6:$Rn, VecListThreeD:$Vd), IIC_VLD1x3u,
1651 "vst1", Dt, "$Vd, $Rn!",
1652 "$Rn.addr = $wb", []> {
1653 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1654 let Inst{5-4} = Rn{5-4};
1655 let DecoderMethod = "DecodeVLDST1Instruction";
1657 def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1658 (ins addrmode6:$Rn, rGPR:$Rm, VecListThreeD:$Vd),
1660 "vst1", Dt, "$Vd, $Rn, $Rm",
1661 "$Rn.addr = $wb", []> {
1662 let Inst{5-4} = Rn{5-4};
1663 let DecoderMethod = "DecodeVLDST1Instruction";
1667 def VST1d8T : VST1D3<{0,0,0,?}, "8">;
1668 def VST1d16T : VST1D3<{0,1,0,?}, "16">;
1669 def VST1d32T : VST1D3<{1,0,0,?}, "32">;
1670 def VST1d64T : VST1D3<{1,1,0,?}, "64">;
1672 defm VST1d8Twb : VST1D3WB<{0,0,0,?}, "8">;
1673 defm VST1d16Twb : VST1D3WB<{0,1,0,?}, "16">;
1674 defm VST1d32Twb : VST1D3WB<{1,0,0,?}, "32">;
1675 defm VST1d64Twb : VST1D3WB<{1,1,0,?}, "64">;
1677 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
1678 def VST1d64TPseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST1x3u>;
1679 def VST1d64TPseudoWB_register : VSTQQWBPseudo<IIC_VST1x3u>;
1681 // ...with 4 registers
1682 class VST1D4<bits<4> op7_4, string Dt>
1683 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1684 (ins addrmode6:$Rn, VecListFourD:$Vd),
1685 IIC_VST1x4, "vst1", Dt, "$Vd, $Rn", "",
1688 let Inst{5-4} = Rn{5-4};
1689 let DecoderMethod = "DecodeVLDST1Instruction";
1691 multiclass VST1D4WB<bits<4> op7_4, string Dt> {
1692 def _fixed : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1693 (ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1x4u,
1694 "vst1", Dt, "$Vd, $Rn!",
1695 "$Rn.addr = $wb", []> {
1696 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1697 let Inst{5-4} = Rn{5-4};
1698 let DecoderMethod = "DecodeVLDST1Instruction";
1700 def _register : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1701 (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1703 "vst1", Dt, "$Vd, $Rn, $Rm",
1704 "$Rn.addr = $wb", []> {
1705 let Inst{5-4} = Rn{5-4};
1706 let DecoderMethod = "DecodeVLDST1Instruction";
1710 def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
1711 def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
1712 def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
1713 def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
1715 defm VST1d8Qwb : VST1D4WB<{0,0,?,?}, "8">;
1716 defm VST1d16Qwb : VST1D4WB<{0,1,?,?}, "16">;
1717 defm VST1d32Qwb : VST1D4WB<{1,0,?,?}, "32">;
1718 defm VST1d64Qwb : VST1D4WB<{1,1,?,?}, "64">;
1720 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
1721 def VST1d64QPseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST1x4u>;
1722 def VST1d64QPseudoWB_register : VSTQQWBPseudo<IIC_VST1x4u>;
1724 // VST2 : Vector Store (multiple 2-element structures)
1725 class VST2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
1726 InstrItinClass itin>
1727 : NLdSt<0, 0b00, op11_8, op7_4, (outs), (ins addrmode6:$Rn, VdTy:$Vd),
1728 itin, "vst2", Dt, "$Vd, $Rn", "", []> {
1730 let Inst{5-4} = Rn{5-4};
1731 let DecoderMethod = "DecodeVLDST2Instruction";
1734 def VST2d8 : VST2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VST2>;
1735 def VST2d16 : VST2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VST2>;
1736 def VST2d32 : VST2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VST2>;
1738 def VST2q8 : VST2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VST2x2>;
1739 def VST2q16 : VST2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VST2x2>;
1740 def VST2q32 : VST2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VST2x2>;
1742 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
1743 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
1744 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
1746 // ...with address register writeback:
1747 multiclass VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt,
1748 RegisterOperand VdTy> {
1749 def _fixed : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1750 (ins addrmode6:$Rn, VdTy:$Vd), IIC_VLD1u,
1751 "vst2", Dt, "$Vd, $Rn!",
1752 "$Rn.addr = $wb", []> {
1753 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1754 let Inst{5-4} = Rn{5-4};
1755 let DecoderMethod = "DecodeVLDST2Instruction";
1757 def _register : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1758 (ins addrmode6:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u,
1759 "vst2", Dt, "$Vd, $Rn, $Rm",
1760 "$Rn.addr = $wb", []> {
1761 let Inst{5-4} = Rn{5-4};
1762 let DecoderMethod = "DecodeVLDST2Instruction";
1765 multiclass VST2QWB<bits<4> op7_4, string Dt> {
1766 def _fixed : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1767 (ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1u,
1768 "vst2", Dt, "$Vd, $Rn!",
1769 "$Rn.addr = $wb", []> {
1770 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1771 let Inst{5-4} = Rn{5-4};
1772 let DecoderMethod = "DecodeVLDST2Instruction";
1774 def _register : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1775 (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1777 "vst2", Dt, "$Vd, $Rn, $Rm",
1778 "$Rn.addr = $wb", []> {
1779 let Inst{5-4} = Rn{5-4};
1780 let DecoderMethod = "DecodeVLDST2Instruction";
1784 defm VST2d8wb : VST2DWB<0b1000, {0,0,?,?}, "8", VecListDPair>;
1785 defm VST2d16wb : VST2DWB<0b1000, {0,1,?,?}, "16", VecListDPair>;
1786 defm VST2d32wb : VST2DWB<0b1000, {1,0,?,?}, "32", VecListDPair>;
1788 defm VST2q8wb : VST2QWB<{0,0,?,?}, "8">;
1789 defm VST2q16wb : VST2QWB<{0,1,?,?}, "16">;
1790 defm VST2q32wb : VST2QWB<{1,0,?,?}, "32">;
1792 def VST2q8PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1793 def VST2q16PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1794 def VST2q32PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1795 def VST2q8PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1796 def VST2q16PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1797 def VST2q32PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1799 // ...with double-spaced registers
1800 def VST2b8 : VST2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VST2>;
1801 def VST2b16 : VST2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VST2>;
1802 def VST2b32 : VST2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VST2>;
1803 defm VST2b8wb : VST2DWB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced>;
1804 defm VST2b16wb : VST2DWB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced>;
1805 defm VST2b32wb : VST2DWB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced>;
1807 // VST3 : Vector Store (multiple 3-element structures)
1808 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1809 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1810 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1811 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1813 let Inst{4} = Rn{4};
1814 let DecoderMethod = "DecodeVLDST3Instruction";
1817 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1818 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1819 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
1821 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1822 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1823 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
1825 // ...with address register writeback:
1826 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1827 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1828 (ins addrmode6:$Rn, am6offset:$Rm,
1829 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1830 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1831 "$Rn.addr = $wb", []> {
1832 let Inst{4} = Rn{4};
1833 let DecoderMethod = "DecodeVLDST3Instruction";
1836 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1837 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1838 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
1840 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1841 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1842 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1844 // ...with double-spaced registers:
1845 def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1846 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1847 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1848 def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1849 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1850 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
1852 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1853 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1854 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1856 // ...alternate versions to be allocated odd register numbers:
1857 def VST3q8oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1858 def VST3q16oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1859 def VST3q32oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1861 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1862 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1863 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1865 // VST4 : Vector Store (multiple 4-element structures)
1866 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1867 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1868 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1869 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1872 let Inst{5-4} = Rn{5-4};
1873 let DecoderMethod = "DecodeVLDST4Instruction";
1876 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1877 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1878 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
1880 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1881 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1882 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
1884 // ...with address register writeback:
1885 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1886 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1887 (ins addrmode6:$Rn, am6offset:$Rm,
1888 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1889 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1890 "$Rn.addr = $wb", []> {
1891 let Inst{5-4} = Rn{5-4};
1892 let DecoderMethod = "DecodeVLDST4Instruction";
1895 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
1896 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
1897 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
1899 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1900 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1901 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1903 // ...with double-spaced registers:
1904 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
1905 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
1906 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
1907 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
1908 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
1909 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
1911 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1912 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1913 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1915 // ...alternate versions to be allocated odd register numbers:
1916 def VST4q8oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1917 def VST4q16oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1918 def VST4q32oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1920 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1921 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1922 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1924 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1926 // Classes for VST*LN pseudo-instructions with multi-register operands.
1927 // These are expanded to real instructions after register allocation.
1928 class VSTQLNPseudo<InstrItinClass itin>
1929 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1931 class VSTQLNWBPseudo<InstrItinClass itin>
1932 : PseudoNLdSt<(outs GPR:$wb),
1933 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1934 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1935 class VSTQQLNPseudo<InstrItinClass itin>
1936 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1938 class VSTQQLNWBPseudo<InstrItinClass itin>
1939 : PseudoNLdSt<(outs GPR:$wb),
1940 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1941 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1942 class VSTQQQQLNPseudo<InstrItinClass itin>
1943 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1945 class VSTQQQQLNWBPseudo<InstrItinClass itin>
1946 : PseudoNLdSt<(outs GPR:$wb),
1947 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1948 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1950 // VST1LN : Vector Store (single element from one lane)
1951 class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1952 PatFrag StoreOp, SDNode ExtractOp, Operand AddrMode>
1953 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1954 (ins AddrMode:$Rn, DPR:$Vd, nohash_imm:$lane),
1955 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1956 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), AddrMode:$Rn)]> {
1958 let DecoderMethod = "DecodeVST1LN";
1960 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1961 : VSTQLNPseudo<IIC_VST1ln> {
1962 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1966 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
1967 NEONvgetlaneu, addrmode6> {
1968 let Inst{7-5} = lane{2-0};
1970 def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
1971 NEONvgetlaneu, addrmode6> {
1972 let Inst{7-6} = lane{1-0};
1973 let Inst{4} = Rn{4};
1976 def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt,
1978 let Inst{7} = lane{0};
1979 let Inst{5-4} = Rn{5-4};
1982 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
1983 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
1984 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
1986 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
1987 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1988 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
1989 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1991 // ...with address register writeback:
1992 class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1993 PatFrag StoreOp, SDNode ExtractOp, Operand AdrMode>
1994 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1995 (ins AdrMode:$Rn, am6offset:$Rm,
1996 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
1997 "\\{$Vd[$lane]\\}, $Rn$Rm",
1999 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
2000 AdrMode:$Rn, am6offset:$Rm))]> {
2001 let DecoderMethod = "DecodeVST1LN";
2003 class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
2004 : VSTQLNWBPseudo<IIC_VST1lnu> {
2005 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
2006 addrmode6:$addr, am6offset:$offset))];
2009 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8,
2010 NEONvgetlaneu, addrmode6> {
2011 let Inst{7-5} = lane{2-0};
2013 def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16", v4i16, post_truncsti16,
2014 NEONvgetlaneu, addrmode6> {
2015 let Inst{7-6} = lane{1-0};
2016 let Inst{4} = Rn{4};
2018 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32", v2i32, post_store,
2019 extractelt, addrmode6oneL32> {
2020 let Inst{7} = lane{0};
2021 let Inst{5-4} = Rn{5-4};
2024 def VST1LNq8Pseudo_UPD : VST1QLNWBPseudo<v16i8, post_truncsti8, NEONvgetlaneu>;
2025 def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,NEONvgetlaneu>;
2026 def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
2028 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2030 // VST2LN : Vector Store (single 2-element structure from one lane)
2031 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2032 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2033 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
2034 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
2037 let Inst{4} = Rn{4};
2038 let DecoderMethod = "DecodeVST2LN";
2041 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
2042 let Inst{7-5} = lane{2-0};
2044 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
2045 let Inst{7-6} = lane{1-0};
2047 def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
2048 let Inst{7} = lane{0};
2051 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
2052 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
2053 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
2055 // ...with double-spaced registers:
2056 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
2057 let Inst{7-6} = lane{1-0};
2058 let Inst{4} = Rn{4};
2060 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
2061 let Inst{7} = lane{0};
2062 let Inst{4} = Rn{4};
2065 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
2066 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
2068 // ...with address register writeback:
2069 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2070 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2071 (ins addrmode6:$Rn, am6offset:$Rm,
2072 DPR:$Vd, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
2073 "\\{$Vd[$lane], $src2[$lane]\\}, $Rn$Rm",
2074 "$Rn.addr = $wb", []> {
2075 let Inst{4} = Rn{4};
2076 let DecoderMethod = "DecodeVST2LN";
2079 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
2080 let Inst{7-5} = lane{2-0};
2082 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
2083 let Inst{7-6} = lane{1-0};
2085 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
2086 let Inst{7} = lane{0};
2089 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2090 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2091 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2093 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
2094 let Inst{7-6} = lane{1-0};
2096 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
2097 let Inst{7} = lane{0};
2100 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
2101 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
2103 // VST3LN : Vector Store (single 3-element structure from one lane)
2104 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2105 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2106 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
2107 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
2108 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
2110 let DecoderMethod = "DecodeVST3LN";
2113 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
2114 let Inst{7-5} = lane{2-0};
2116 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
2117 let Inst{7-6} = lane{1-0};
2119 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
2120 let Inst{7} = lane{0};
2123 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2124 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2125 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2127 // ...with double-spaced registers:
2128 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
2129 let Inst{7-6} = lane{1-0};
2131 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
2132 let Inst{7} = lane{0};
2135 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
2136 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
2138 // ...with address register writeback:
2139 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2140 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2141 (ins addrmode6:$Rn, am6offset:$Rm,
2142 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
2143 IIC_VST3lnu, "vst3", Dt,
2144 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
2145 "$Rn.addr = $wb", []> {
2146 let DecoderMethod = "DecodeVST3LN";
2149 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
2150 let Inst{7-5} = lane{2-0};
2152 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
2153 let Inst{7-6} = lane{1-0};
2155 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
2156 let Inst{7} = lane{0};
2159 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2160 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2161 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2163 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
2164 let Inst{7-6} = lane{1-0};
2166 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
2167 let Inst{7} = lane{0};
2170 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
2171 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
2173 // VST4LN : Vector Store (single 4-element structure from one lane)
2174 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2175 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2176 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
2177 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
2178 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
2181 let Inst{4} = Rn{4};
2182 let DecoderMethod = "DecodeVST4LN";
2185 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
2186 let Inst{7-5} = lane{2-0};
2188 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
2189 let Inst{7-6} = lane{1-0};
2191 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
2192 let Inst{7} = lane{0};
2193 let Inst{5} = Rn{5};
2196 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2197 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2198 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2200 // ...with double-spaced registers:
2201 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
2202 let Inst{7-6} = lane{1-0};
2204 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
2205 let Inst{7} = lane{0};
2206 let Inst{5} = Rn{5};
2209 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
2210 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
2212 // ...with address register writeback:
2213 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2214 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2215 (ins addrmode6:$Rn, am6offset:$Rm,
2216 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
2217 IIC_VST4lnu, "vst4", Dt,
2218 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
2219 "$Rn.addr = $wb", []> {
2220 let Inst{4} = Rn{4};
2221 let DecoderMethod = "DecodeVST4LN";
2224 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
2225 let Inst{7-5} = lane{2-0};
2227 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
2228 let Inst{7-6} = lane{1-0};
2230 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
2231 let Inst{7} = lane{0};
2232 let Inst{5} = Rn{5};
2235 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2236 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2237 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2239 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
2240 let Inst{7-6} = lane{1-0};
2242 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
2243 let Inst{7} = lane{0};
2244 let Inst{5} = Rn{5};
2247 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
2248 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
2250 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2252 // Use vld1/vst1 for unaligned f64 load / store
2253 def : Pat<(f64 (hword_alignedload addrmode6:$addr)),
2254 (VLD1d16 addrmode6:$addr)>, Requires<[IsLE]>;
2255 def : Pat<(hword_alignedstore (f64 DPR:$value), addrmode6:$addr),
2256 (VST1d16 addrmode6:$addr, DPR:$value)>, Requires<[IsLE]>;
2257 def : Pat<(f64 (byte_alignedload addrmode6:$addr)),
2258 (VLD1d8 addrmode6:$addr)>, Requires<[IsLE]>;
2259 def : Pat<(byte_alignedstore (f64 DPR:$value), addrmode6:$addr),
2260 (VST1d8 addrmode6:$addr, DPR:$value)>, Requires<[IsLE]>;
2261 def : Pat<(f64 (non_word_alignedload addrmode6:$addr)),
2262 (VLD1d64 addrmode6:$addr)>, Requires<[IsBE]>;
2263 def : Pat<(non_word_alignedstore (f64 DPR:$value), addrmode6:$addr),
2264 (VST1d64 addrmode6:$addr, DPR:$value)>, Requires<[IsBE]>;
2266 // Use vld1/vst1 for Q and QQ. Also use them for unaligned v2f64
2267 // load / store if it's legal.
2268 def : Pat<(v2f64 (dword_alignedload addrmode6:$addr)),
2269 (VLD1q64 addrmode6:$addr)>;
2270 def : Pat<(dword_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2271 (VST1q64 addrmode6:$addr, QPR:$value)>;
2272 def : Pat<(v2f64 (word_alignedload addrmode6:$addr)),
2273 (VLD1q32 addrmode6:$addr)>;
2274 def : Pat<(word_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2275 (VST1q32 addrmode6:$addr, QPR:$value)>;
2276 def : Pat<(v2f64 (hword_alignedload addrmode6:$addr)),
2277 (VLD1q16 addrmode6:$addr)>, Requires<[IsLE]>;
2278 def : Pat<(hword_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2279 (VST1q16 addrmode6:$addr, QPR:$value)>, Requires<[IsLE]>;
2280 def : Pat<(v2f64 (byte_alignedload addrmode6:$addr)),
2281 (VLD1q8 addrmode6:$addr)>, Requires<[IsLE]>;
2282 def : Pat<(byte_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2283 (VST1q8 addrmode6:$addr, QPR:$value)>, Requires<[IsLE]>;
2285 //===----------------------------------------------------------------------===//
2286 // NEON pattern fragments
2287 //===----------------------------------------------------------------------===//
2289 // Extract D sub-registers of Q registers.
2290 def DSubReg_i8_reg : SDNodeXForm<imm, [{
2291 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2292 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
2294 def DSubReg_i16_reg : SDNodeXForm<imm, [{
2295 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2296 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
2298 def DSubReg_i32_reg : SDNodeXForm<imm, [{
2299 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2300 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
2302 def DSubReg_f64_reg : SDNodeXForm<imm, [{
2303 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2304 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
2307 // Extract S sub-registers of Q/D registers.
2308 def SSubReg_f32_reg : SDNodeXForm<imm, [{
2309 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
2310 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
2313 // Translate lane numbers from Q registers to D subregs.
2314 def SubReg_i8_lane : SDNodeXForm<imm, [{
2315 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
2317 def SubReg_i16_lane : SDNodeXForm<imm, [{
2318 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
2320 def SubReg_i32_lane : SDNodeXForm<imm, [{
2321 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
2324 //===----------------------------------------------------------------------===//
2325 // Instruction Classes
2326 //===----------------------------------------------------------------------===//
2328 // Basic 2-register operations: double- and quad-register.
2329 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2330 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
2331 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2332 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2333 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
2334 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
2335 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2336 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
2337 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2338 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2339 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
2340 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
2342 // Basic 2-register intrinsics, both double- and quad-register.
2343 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2344 bits<2> op17_16, bits<5> op11_7, bit op4,
2345 InstrItinClass itin, string OpcodeStr, string Dt,
2346 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2347 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2348 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2349 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2350 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2351 bits<2> op17_16, bits<5> op11_7, bit op4,
2352 InstrItinClass itin, string OpcodeStr, string Dt,
2353 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2354 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2355 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2356 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2358 // Same as above, but not predicated.
2359 class N2VDIntnp<bits<2> op17_16, bits<3> op10_8, bit op7,
2360 InstrItinClass itin, string OpcodeStr, string Dt,
2361 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2362 : N2Vnp<0b10, op17_16, op10_8, op7, 0, (outs DPR:$Vd), (ins DPR:$Vm),
2363 itin, OpcodeStr, Dt, ResTy, OpTy,
2364 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2366 class N2VQIntnp<bits<2> op17_16, bits<3> op10_8, bit op7,
2367 InstrItinClass itin, string OpcodeStr, string Dt,
2368 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2369 : N2Vnp<0b10, op17_16, op10_8, op7, 1, (outs QPR:$Vd), (ins QPR:$Vm),
2370 itin, OpcodeStr, Dt, ResTy, OpTy,
2371 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2373 // Similar to NV2VQIntnp with some more encoding bits exposed (crypto).
2374 class N2VQIntXnp<bits<2> op19_18, bits<2> op17_16, bits<3> op10_8, bit op6,
2375 bit op7, InstrItinClass itin, string OpcodeStr, string Dt,
2376 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2377 : N2Vnp<op19_18, op17_16, op10_8, op7, op6, (outs QPR:$Vd), (ins QPR:$Vm),
2378 itin, OpcodeStr, Dt, ResTy, OpTy,
2379 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2381 // Same as N2VQIntXnp but with Vd as a src register.
2382 class N2VQIntX2np<bits<2> op19_18, bits<2> op17_16, bits<3> op10_8, bit op6,
2383 bit op7, InstrItinClass itin, string OpcodeStr, string Dt,
2384 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2385 : N2Vnp<op19_18, op17_16, op10_8, op7, op6,
2386 (outs QPR:$Vd), (ins QPR:$src, QPR:$Vm),
2387 itin, OpcodeStr, Dt, ResTy, OpTy,
2388 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vm))))]> {
2389 let Constraints = "$src = $Vd";
2392 // Narrow 2-register operations.
2393 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2394 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2395 InstrItinClass itin, string OpcodeStr, string Dt,
2396 ValueType TyD, ValueType TyQ, SDNode OpNode>
2397 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2398 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2399 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
2401 // Narrow 2-register intrinsics.
2402 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2403 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2404 InstrItinClass itin, string OpcodeStr, string Dt,
2405 ValueType TyD, ValueType TyQ, SDPatternOperator IntOp>
2406 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2407 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2408 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
2410 // Long 2-register operations (currently only used for VMOVL).
2411 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2412 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2413 InstrItinClass itin, string OpcodeStr, string Dt,
2414 ValueType TyQ, ValueType TyD, SDNode OpNode>
2415 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2416 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2417 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
2419 // Long 2-register intrinsics.
2420 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2421 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2422 InstrItinClass itin, string OpcodeStr, string Dt,
2423 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp>
2424 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2425 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2426 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
2428 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
2429 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
2430 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
2431 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
2432 OpcodeStr, Dt, "$Vd, $Vm",
2433 "$src1 = $Vd, $src2 = $Vm", []>;
2434 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
2435 InstrItinClass itin, string OpcodeStr, string Dt>
2436 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
2437 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
2438 "$src1 = $Vd, $src2 = $Vm", []>;
2440 // Basic 3-register operations: double- and quad-register.
2441 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2442 InstrItinClass itin, string OpcodeStr, string Dt,
2443 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2444 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2445 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2446 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2447 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2448 // All of these have a two-operand InstAlias.
2449 let TwoOperandAliasConstraint = "$Vn = $Vd";
2450 let isCommutable = Commutable;
2452 // Same as N3VD but no data type.
2453 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2454 InstrItinClass itin, string OpcodeStr,
2455 ValueType ResTy, ValueType OpTy,
2456 SDNode OpNode, bit Commutable>
2457 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
2458 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2459 OpcodeStr, "$Vd, $Vn, $Vm", "",
2460 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
2461 // All of these have a two-operand InstAlias.
2462 let TwoOperandAliasConstraint = "$Vn = $Vd";
2463 let isCommutable = Commutable;
2466 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
2467 InstrItinClass itin, string OpcodeStr, string Dt,
2468 ValueType Ty, SDNode ShOp>
2469 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2470 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2471 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2473 (Ty (ShOp (Ty DPR:$Vn),
2474 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
2475 // All of these have a two-operand InstAlias.
2476 let TwoOperandAliasConstraint = "$Vn = $Vd";
2477 let isCommutable = 0;
2479 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
2480 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2481 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2482 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2483 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane","",
2485 (Ty (ShOp (Ty DPR:$Vn),
2486 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2487 // All of these have a two-operand InstAlias.
2488 let TwoOperandAliasConstraint = "$Vn = $Vd";
2489 let isCommutable = 0;
2492 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2493 InstrItinClass itin, string OpcodeStr, string Dt,
2494 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2495 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2496 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2497 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2498 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2499 // All of these have a two-operand InstAlias.
2500 let TwoOperandAliasConstraint = "$Vn = $Vd";
2501 let isCommutable = Commutable;
2503 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2504 InstrItinClass itin, string OpcodeStr,
2505 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2506 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
2507 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2508 OpcodeStr, "$Vd, $Vn, $Vm", "",
2509 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
2510 // All of these have a two-operand InstAlias.
2511 let TwoOperandAliasConstraint = "$Vn = $Vd";
2512 let isCommutable = Commutable;
2514 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
2515 InstrItinClass itin, string OpcodeStr, string Dt,
2516 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2517 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2518 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2519 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2520 [(set (ResTy QPR:$Vd),
2521 (ResTy (ShOp (ResTy QPR:$Vn),
2522 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2524 // All of these have a two-operand InstAlias.
2525 let TwoOperandAliasConstraint = "$Vn = $Vd";
2526 let isCommutable = 0;
2528 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
2529 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2530 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2531 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2532 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane", "",
2533 [(set (ResTy QPR:$Vd),
2534 (ResTy (ShOp (ResTy QPR:$Vn),
2535 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2537 // All of these have a two-operand InstAlias.
2538 let TwoOperandAliasConstraint = "$Vn = $Vd";
2539 let isCommutable = 0;
2542 // Basic 3-register intrinsics, both double- and quad-register.
2543 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2544 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2545 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp, bit Commutable>
2546 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2547 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
2548 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2549 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2550 // All of these have a two-operand InstAlias.
2551 let TwoOperandAliasConstraint = "$Vn = $Vd";
2552 let isCommutable = Commutable;
2555 class N3VDIntnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2556 bit op4, Format f, InstrItinClass itin, string OpcodeStr,
2557 string Dt, ValueType ResTy, ValueType OpTy,
2558 SDPatternOperator IntOp, bit Commutable>
2559 : N3Vnp<op27_23, op21_20, op11_8, op6, op4,
2560 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, OpcodeStr, Dt,
2561 ResTy, OpTy, IntOp, Commutable,
2562 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2564 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2565 string OpcodeStr, string Dt, ValueType Ty, SDPatternOperator IntOp>
2566 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2567 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2568 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2570 (Ty (IntOp (Ty DPR:$Vn),
2571 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2573 let isCommutable = 0;
2576 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2577 string OpcodeStr, string Dt, ValueType Ty, SDPatternOperator IntOp>
2578 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2579 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2580 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2582 (Ty (IntOp (Ty DPR:$Vn),
2583 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2584 let isCommutable = 0;
2586 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2587 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2588 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2589 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2590 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
2591 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2592 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
2593 let TwoOperandAliasConstraint = "$Vm = $Vd";
2594 let isCommutable = 0;
2597 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2598 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2599 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp, bit Commutable>
2600 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2601 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
2602 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2603 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2604 // All of these have a two-operand InstAlias.
2605 let TwoOperandAliasConstraint = "$Vn = $Vd";
2606 let isCommutable = Commutable;
2609 class N3VQIntnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2610 bit op4, Format f, InstrItinClass itin, string OpcodeStr,
2611 string Dt, ValueType ResTy, ValueType OpTy,
2612 SDPatternOperator IntOp, bit Commutable>
2613 : N3Vnp<op27_23, op21_20, op11_8, op6, op4,
2614 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin, OpcodeStr, Dt,
2615 ResTy, OpTy, IntOp, Commutable,
2616 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2618 // Same as N3VQIntnp but with Vd as a src register.
2619 class N3VQInt3np<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2620 bit op4, Format f, InstrItinClass itin, string OpcodeStr,
2621 string Dt, ValueType ResTy, ValueType OpTy,
2622 SDPatternOperator IntOp, bit Commutable>
2623 : N3Vnp<op27_23, op21_20, op11_8, op6, op4,
2624 (outs QPR:$Vd), (ins QPR:$src, QPR:$Vn, QPR:$Vm), f, itin, OpcodeStr,
2625 Dt, ResTy, OpTy, IntOp, Commutable,
2626 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vn),
2627 (OpTy QPR:$Vm))))]> {
2628 let Constraints = "$src = $Vd";
2631 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2632 string OpcodeStr, string Dt,
2633 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2634 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2635 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2636 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2637 [(set (ResTy QPR:$Vd),
2638 (ResTy (IntOp (ResTy QPR:$Vn),
2639 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2641 let isCommutable = 0;
2643 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2644 string OpcodeStr, string Dt,
2645 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2646 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2647 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2648 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2649 [(set (ResTy QPR:$Vd),
2650 (ResTy (IntOp (ResTy QPR:$Vn),
2651 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2653 let isCommutable = 0;
2655 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2656 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2657 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2658 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2659 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
2660 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2661 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
2662 let TwoOperandAliasConstraint = "$Vm = $Vd";
2663 let isCommutable = 0;
2666 // Multiply-Add/Sub operations: double- and quad-register.
2667 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2668 InstrItinClass itin, string OpcodeStr, string Dt,
2669 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode>
2670 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2671 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2672 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2673 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2674 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
2676 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2677 string OpcodeStr, string Dt,
2678 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
2679 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2681 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2683 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2685 (Ty (ShOp (Ty DPR:$src1),
2687 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2689 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2690 string OpcodeStr, string Dt,
2691 ValueType Ty, SDNode MulOp, SDNode ShOp>
2692 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2694 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2696 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2698 (Ty (ShOp (Ty DPR:$src1),
2700 (Ty (NEONvduplane (Ty DPR_8:$Vm),
2703 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2704 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
2705 SDPatternOperator MulOp, SDPatternOperator OpNode>
2706 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2707 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2708 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2709 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2710 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
2711 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2712 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2713 SDPatternOperator MulOp, SDPatternOperator ShOp>
2714 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2716 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2718 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2719 [(set (ResTy QPR:$Vd),
2720 (ResTy (ShOp (ResTy QPR:$src1),
2721 (ResTy (MulOp QPR:$Vn,
2722 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2724 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2725 string OpcodeStr, string Dt,
2726 ValueType ResTy, ValueType OpTy,
2727 SDNode MulOp, SDNode ShOp>
2728 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2730 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2732 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2733 [(set (ResTy QPR:$Vd),
2734 (ResTy (ShOp (ResTy QPR:$src1),
2735 (ResTy (MulOp QPR:$Vn,
2736 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2739 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
2740 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2741 InstrItinClass itin, string OpcodeStr, string Dt,
2742 ValueType Ty, SDPatternOperator IntOp, SDNode OpNode>
2743 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2744 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2745 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2746 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2747 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
2748 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2749 InstrItinClass itin, string OpcodeStr, string Dt,
2750 ValueType Ty, SDPatternOperator IntOp, SDNode OpNode>
2751 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2752 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2753 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2754 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2755 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2757 // Neon 3-argument intrinsics, both double- and quad-register.
2758 // The destination register is also used as the first source operand register.
2759 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2760 InstrItinClass itin, string OpcodeStr, string Dt,
2761 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2762 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2763 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2764 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2765 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2766 (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2767 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2768 InstrItinClass itin, string OpcodeStr, string Dt,
2769 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2770 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2771 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2772 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2773 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2774 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2776 // Long Multiply-Add/Sub operations.
2777 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2778 InstrItinClass itin, string OpcodeStr, string Dt,
2779 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2780 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2781 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2782 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2783 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2784 (TyQ (MulOp (TyD DPR:$Vn),
2785 (TyD DPR:$Vm)))))]>;
2786 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2787 InstrItinClass itin, string OpcodeStr, string Dt,
2788 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2789 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2790 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2792 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2794 (OpNode (TyQ QPR:$src1),
2795 (TyQ (MulOp (TyD DPR:$Vn),
2796 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),
2798 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2799 InstrItinClass itin, string OpcodeStr, string Dt,
2800 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2801 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2802 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2804 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2806 (OpNode (TyQ QPR:$src1),
2807 (TyQ (MulOp (TyD DPR:$Vn),
2808 (TyD (NEONvduplane (TyD DPR_8:$Vm),
2811 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
2812 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2813 InstrItinClass itin, string OpcodeStr, string Dt,
2814 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp,
2816 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2817 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2818 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2819 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2820 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2821 (TyD DPR:$Vm)))))))]>;
2823 // Neon Long 3-argument intrinsic. The destination register is
2824 // a quad-register and is also used as the first source operand register.
2825 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2826 InstrItinClass itin, string OpcodeStr, string Dt,
2827 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp>
2828 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2829 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2830 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2832 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2833 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2834 string OpcodeStr, string Dt,
2835 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2836 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2838 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2840 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2841 [(set (ResTy QPR:$Vd),
2842 (ResTy (IntOp (ResTy QPR:$src1),
2844 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2846 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2847 InstrItinClass itin, string OpcodeStr, string Dt,
2848 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2849 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2851 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2853 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2854 [(set (ResTy QPR:$Vd),
2855 (ResTy (IntOp (ResTy QPR:$src1),
2857 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2860 // Narrowing 3-register intrinsics.
2861 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2862 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
2863 SDPatternOperator IntOp, bit Commutable>
2864 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2865 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2866 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2867 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2868 let isCommutable = Commutable;
2871 // Long 3-register operations.
2872 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2873 InstrItinClass itin, string OpcodeStr, string Dt,
2874 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
2875 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2876 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2877 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2878 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2879 let isCommutable = Commutable;
2882 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2883 InstrItinClass itin, string OpcodeStr, string Dt,
2884 ValueType TyQ, ValueType TyD, SDNode OpNode>
2885 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2886 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2887 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2889 (TyQ (OpNode (TyD DPR:$Vn),
2890 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
2891 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2892 InstrItinClass itin, string OpcodeStr, string Dt,
2893 ValueType TyQ, ValueType TyD, SDNode OpNode>
2894 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2895 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2896 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2898 (TyQ (OpNode (TyD DPR:$Vn),
2899 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
2901 // Long 3-register operations with explicitly extended operands.
2902 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2903 InstrItinClass itin, string OpcodeStr, string Dt,
2904 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
2906 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2907 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2908 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2909 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
2910 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2911 let isCommutable = Commutable;
2914 // Long 3-register intrinsics with explicit extend (VABDL).
2915 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2916 InstrItinClass itin, string OpcodeStr, string Dt,
2917 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp,
2919 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2920 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2921 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2922 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2923 (TyD DPR:$Vm))))))]> {
2924 let isCommutable = Commutable;
2927 // Long 3-register intrinsics.
2928 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2929 InstrItinClass itin, string OpcodeStr, string Dt,
2930 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, bit Commutable>
2931 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2932 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2933 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2934 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2935 let isCommutable = Commutable;
2938 // Same as above, but not predicated.
2939 class N3VLIntnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2940 bit op4, InstrItinClass itin, string OpcodeStr,
2941 string Dt, ValueType ResTy, ValueType OpTy,
2942 SDPatternOperator IntOp, bit Commutable>
2943 : N3Vnp<op27_23, op21_20, op11_8, op6, op4,
2944 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, OpcodeStr, Dt,
2945 ResTy, OpTy, IntOp, Commutable,
2946 [(set QPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2948 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2949 string OpcodeStr, string Dt,
2950 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2951 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2952 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2953 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2954 [(set (ResTy QPR:$Vd),
2955 (ResTy (IntOp (OpTy DPR:$Vn),
2956 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2958 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2959 InstrItinClass itin, string OpcodeStr, string Dt,
2960 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2961 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2962 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2963 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2964 [(set (ResTy QPR:$Vd),
2965 (ResTy (IntOp (OpTy DPR:$Vn),
2966 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2969 // Wide 3-register operations.
2970 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2971 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
2972 SDNode OpNode, SDNode ExtOp, bit Commutable>
2973 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2974 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
2975 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2976 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
2977 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2978 // All of these have a two-operand InstAlias.
2979 let TwoOperandAliasConstraint = "$Vn = $Vd";
2980 let isCommutable = Commutable;
2983 // Pairwise long 2-register intrinsics, both double- and quad-register.
2984 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2985 bits<2> op17_16, bits<5> op11_7, bit op4,
2986 string OpcodeStr, string Dt,
2987 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2988 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2989 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2990 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2991 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2992 bits<2> op17_16, bits<5> op11_7, bit op4,
2993 string OpcodeStr, string Dt,
2994 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2995 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2996 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2997 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2999 // Pairwise long 2-register accumulate intrinsics,
3000 // both double- and quad-register.
3001 // The destination register is also used as the first source operand register.
3002 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
3003 bits<2> op17_16, bits<5> op11_7, bit op4,
3004 string OpcodeStr, string Dt,
3005 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
3006 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
3007 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
3008 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
3009 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
3010 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
3011 bits<2> op17_16, bits<5> op11_7, bit op4,
3012 string OpcodeStr, string Dt,
3013 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
3014 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
3015 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
3016 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
3017 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
3019 // Shift by immediate,
3020 // both double- and quad-register.
3021 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3022 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3023 Format f, InstrItinClass itin, Operand ImmTy,
3024 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
3025 : N2VImm<op24, op23, op11_8, op7, 0, op4,
3026 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
3027 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3028 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
3029 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3030 Format f, InstrItinClass itin, Operand ImmTy,
3031 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
3032 : N2VImm<op24, op23, op11_8, op7, 1, op4,
3033 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
3034 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3035 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
3038 // Long shift by immediate.
3039 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
3040 string OpcodeStr, string Dt,
3041 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode>
3042 : N2VImm<op24, op23, op11_8, op7, op6, op4,
3043 (outs QPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), N2RegVShLFrm,
3044 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3045 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm),
3046 (i32 imm:$SIMM))))]>;
3048 // Narrow shift by immediate.
3049 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
3050 InstrItinClass itin, string OpcodeStr, string Dt,
3051 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode>
3052 : N2VImm<op24, op23, op11_8, op7, op6, op4,
3053 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
3054 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3055 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
3056 (i32 imm:$SIMM))))]>;
3058 // Shift right by immediate and accumulate,
3059 // both double- and quad-register.
3060 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3061 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3062 Operand ImmTy, string OpcodeStr, string Dt,
3063 ValueType Ty, SDNode ShOp>
3064 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
3065 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
3066 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3067 [(set DPR:$Vd, (Ty (add DPR:$src1,
3068 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
3069 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3070 Operand ImmTy, string OpcodeStr, string Dt,
3071 ValueType Ty, SDNode ShOp>
3072 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
3073 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
3074 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3075 [(set QPR:$Vd, (Ty (add QPR:$src1,
3076 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
3079 // Shift by immediate and insert,
3080 // both double- and quad-register.
3081 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3082 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3083 Operand ImmTy, Format f, string OpcodeStr, string Dt,
3084 ValueType Ty,SDNode ShOp>
3085 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
3086 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiD,
3087 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3088 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
3089 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3090 Operand ImmTy, Format f, string OpcodeStr, string Dt,
3091 ValueType Ty,SDNode ShOp>
3092 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
3093 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiQ,
3094 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3095 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
3098 // Convert, with fractional bits immediate,
3099 // both double- and quad-register.
3100 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3101 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
3102 SDPatternOperator IntOp>
3103 : N2VImm<op24, op23, op11_8, op7, 0, op4,
3104 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
3105 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3106 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
3107 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3108 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
3109 SDPatternOperator IntOp>
3110 : N2VImm<op24, op23, op11_8, op7, 1, op4,
3111 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
3112 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3113 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
3115 //===----------------------------------------------------------------------===//
3117 //===----------------------------------------------------------------------===//
3119 // Abbreviations used in multiclass suffixes:
3120 // Q = quarter int (8 bit) elements
3121 // H = half int (16 bit) elements
3122 // S = single int (32 bit) elements
3123 // D = double int (64 bit) elements
3125 // Neon 2-register vector operations and intrinsics.
3127 // Neon 2-register comparisons.
3128 // source operand element sizes of 8, 16 and 32 bits:
3129 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3130 bits<5> op11_7, bit op4, string opc, string Dt,
3131 string asm, SDNode OpNode> {
3132 // 64-bit vector types.
3133 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
3134 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3135 opc, !strconcat(Dt, "8"), asm, "",
3136 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
3137 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
3138 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3139 opc, !strconcat(Dt, "16"), asm, "",
3140 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>;
3141 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
3142 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3143 opc, !strconcat(Dt, "32"), asm, "",
3144 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>;
3145 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
3146 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3147 opc, "f32", asm, "",
3148 [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> {
3149 let Inst{10} = 1; // overwrite F = 1
3152 // 128-bit vector types.
3153 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
3154 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3155 opc, !strconcat(Dt, "8"), asm, "",
3156 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
3157 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
3158 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3159 opc, !strconcat(Dt, "16"), asm, "",
3160 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
3161 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
3162 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3163 opc, !strconcat(Dt, "32"), asm, "",
3164 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
3165 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
3166 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3167 opc, "f32", asm, "",
3168 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
3169 let Inst{10} = 1; // overwrite F = 1
3174 // Neon 2-register vector intrinsics,
3175 // element sizes of 8, 16 and 32 bits:
3176 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3177 bits<5> op11_7, bit op4,
3178 InstrItinClass itinD, InstrItinClass itinQ,
3179 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3180 // 64-bit vector types.
3181 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3182 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
3183 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3184 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
3185 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3186 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
3188 // 128-bit vector types.
3189 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3190 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
3191 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3192 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
3193 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3194 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
3198 // Neon Narrowing 2-register vector operations,
3199 // source operand element sizes of 16, 32 and 64 bits:
3200 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3201 bits<5> op11_7, bit op6, bit op4,
3202 InstrItinClass itin, string OpcodeStr, string Dt,
3204 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
3205 itin, OpcodeStr, !strconcat(Dt, "16"),
3206 v8i8, v8i16, OpNode>;
3207 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3208 itin, OpcodeStr, !strconcat(Dt, "32"),
3209 v4i16, v4i32, OpNode>;
3210 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
3211 itin, OpcodeStr, !strconcat(Dt, "64"),
3212 v2i32, v2i64, OpNode>;
3215 // Neon Narrowing 2-register vector intrinsics,
3216 // source operand element sizes of 16, 32 and 64 bits:
3217 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3218 bits<5> op11_7, bit op6, bit op4,
3219 InstrItinClass itin, string OpcodeStr, string Dt,
3220 SDPatternOperator IntOp> {
3221 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
3222 itin, OpcodeStr, !strconcat(Dt, "16"),
3223 v8i8, v8i16, IntOp>;
3224 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3225 itin, OpcodeStr, !strconcat(Dt, "32"),
3226 v4i16, v4i32, IntOp>;
3227 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
3228 itin, OpcodeStr, !strconcat(Dt, "64"),
3229 v2i32, v2i64, IntOp>;
3233 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
3234 // source operand element sizes of 16, 32 and 64 bits:
3235 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
3236 string OpcodeStr, string Dt, SDNode OpNode> {
3237 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3238 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
3239 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3240 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
3241 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3242 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
3246 // Neon 3-register vector operations.
3248 // First with only element sizes of 8, 16 and 32 bits:
3249 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3250 InstrItinClass itinD16, InstrItinClass itinD32,
3251 InstrItinClass itinQ16, InstrItinClass itinQ32,
3252 string OpcodeStr, string Dt,
3253 SDNode OpNode, bit Commutable = 0> {
3254 // 64-bit vector types.
3255 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
3256 OpcodeStr, !strconcat(Dt, "8"),
3257 v8i8, v8i8, OpNode, Commutable>;
3258 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
3259 OpcodeStr, !strconcat(Dt, "16"),
3260 v4i16, v4i16, OpNode, Commutable>;
3261 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
3262 OpcodeStr, !strconcat(Dt, "32"),
3263 v2i32, v2i32, OpNode, Commutable>;
3265 // 128-bit vector types.
3266 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
3267 OpcodeStr, !strconcat(Dt, "8"),
3268 v16i8, v16i8, OpNode, Commutable>;
3269 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
3270 OpcodeStr, !strconcat(Dt, "16"),
3271 v8i16, v8i16, OpNode, Commutable>;
3272 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
3273 OpcodeStr, !strconcat(Dt, "32"),
3274 v4i32, v4i32, OpNode, Commutable>;
3277 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, SDNode ShOp> {
3278 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, "i16", v4i16, ShOp>;
3279 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, "i32", v2i32, ShOp>;
3280 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, "i16", v8i16, v4i16, ShOp>;
3281 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, "i32",
3282 v4i32, v2i32, ShOp>;
3285 // ....then also with element size 64 bits:
3286 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3287 InstrItinClass itinD, InstrItinClass itinQ,
3288 string OpcodeStr, string Dt,
3289 SDNode OpNode, bit Commutable = 0>
3290 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
3291 OpcodeStr, Dt, OpNode, Commutable> {
3292 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
3293 OpcodeStr, !strconcat(Dt, "64"),
3294 v1i64, v1i64, OpNode, Commutable>;
3295 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
3296 OpcodeStr, !strconcat(Dt, "64"),
3297 v2i64, v2i64, OpNode, Commutable>;
3301 // Neon 3-register vector intrinsics.
3303 // First with only element sizes of 16 and 32 bits:
3304 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3305 InstrItinClass itinD16, InstrItinClass itinD32,
3306 InstrItinClass itinQ16, InstrItinClass itinQ32,
3307 string OpcodeStr, string Dt,
3308 SDPatternOperator IntOp, bit Commutable = 0> {
3309 // 64-bit vector types.
3310 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
3311 OpcodeStr, !strconcat(Dt, "16"),
3312 v4i16, v4i16, IntOp, Commutable>;
3313 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
3314 OpcodeStr, !strconcat(Dt, "32"),
3315 v2i32, v2i32, IntOp, Commutable>;
3317 // 128-bit vector types.
3318 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3319 OpcodeStr, !strconcat(Dt, "16"),
3320 v8i16, v8i16, IntOp, Commutable>;
3321 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3322 OpcodeStr, !strconcat(Dt, "32"),
3323 v4i32, v4i32, IntOp, Commutable>;
3325 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3326 InstrItinClass itinD16, InstrItinClass itinD32,
3327 InstrItinClass itinQ16, InstrItinClass itinQ32,
3328 string OpcodeStr, string Dt,
3329 SDPatternOperator IntOp> {
3330 // 64-bit vector types.
3331 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
3332 OpcodeStr, !strconcat(Dt, "16"),
3333 v4i16, v4i16, IntOp>;
3334 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
3335 OpcodeStr, !strconcat(Dt, "32"),
3336 v2i32, v2i32, IntOp>;
3338 // 128-bit vector types.
3339 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3340 OpcodeStr, !strconcat(Dt, "16"),
3341 v8i16, v8i16, IntOp>;
3342 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3343 OpcodeStr, !strconcat(Dt, "32"),
3344 v4i32, v4i32, IntOp>;
3347 multiclass N3VIntSL_HS<bits<4> op11_8,
3348 InstrItinClass itinD16, InstrItinClass itinD32,
3349 InstrItinClass itinQ16, InstrItinClass itinQ32,
3350 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3351 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
3352 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
3353 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
3354 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
3355 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
3356 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
3357 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
3358 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
3361 // ....then also with element size of 8 bits:
3362 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3363 InstrItinClass itinD16, InstrItinClass itinD32,
3364 InstrItinClass itinQ16, InstrItinClass itinQ32,
3365 string OpcodeStr, string Dt,
3366 SDPatternOperator IntOp, bit Commutable = 0>
3367 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3368 OpcodeStr, Dt, IntOp, Commutable> {
3369 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
3370 OpcodeStr, !strconcat(Dt, "8"),
3371 v8i8, v8i8, IntOp, Commutable>;
3372 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
3373 OpcodeStr, !strconcat(Dt, "8"),
3374 v16i8, v16i8, IntOp, Commutable>;
3376 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3377 InstrItinClass itinD16, InstrItinClass itinD32,
3378 InstrItinClass itinQ16, InstrItinClass itinQ32,
3379 string OpcodeStr, string Dt,
3380 SDPatternOperator IntOp>
3381 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3382 OpcodeStr, Dt, IntOp> {
3383 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
3384 OpcodeStr, !strconcat(Dt, "8"),
3386 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
3387 OpcodeStr, !strconcat(Dt, "8"),
3388 v16i8, v16i8, IntOp>;
3392 // ....then also with element size of 64 bits:
3393 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3394 InstrItinClass itinD16, InstrItinClass itinD32,
3395 InstrItinClass itinQ16, InstrItinClass itinQ32,
3396 string OpcodeStr, string Dt,
3397 SDPatternOperator IntOp, bit Commutable = 0>
3398 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3399 OpcodeStr, Dt, IntOp, Commutable> {
3400 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
3401 OpcodeStr, !strconcat(Dt, "64"),
3402 v1i64, v1i64, IntOp, Commutable>;
3403 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3404 OpcodeStr, !strconcat(Dt, "64"),
3405 v2i64, v2i64, IntOp, Commutable>;
3407 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3408 InstrItinClass itinD16, InstrItinClass itinD32,
3409 InstrItinClass itinQ16, InstrItinClass itinQ32,
3410 string OpcodeStr, string Dt,
3411 SDPatternOperator IntOp>
3412 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3413 OpcodeStr, Dt, IntOp> {
3414 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
3415 OpcodeStr, !strconcat(Dt, "64"),
3416 v1i64, v1i64, IntOp>;
3417 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3418 OpcodeStr, !strconcat(Dt, "64"),
3419 v2i64, v2i64, IntOp>;
3422 // Neon Narrowing 3-register vector intrinsics,
3423 // source operand element sizes of 16, 32 and 64 bits:
3424 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3425 string OpcodeStr, string Dt,
3426 SDPatternOperator IntOp, bit Commutable = 0> {
3427 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
3428 OpcodeStr, !strconcat(Dt, "16"),
3429 v8i8, v8i16, IntOp, Commutable>;
3430 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
3431 OpcodeStr, !strconcat(Dt, "32"),
3432 v4i16, v4i32, IntOp, Commutable>;
3433 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
3434 OpcodeStr, !strconcat(Dt, "64"),
3435 v2i32, v2i64, IntOp, Commutable>;
3439 // Neon Long 3-register vector operations.
3441 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3442 InstrItinClass itin16, InstrItinClass itin32,
3443 string OpcodeStr, string Dt,
3444 SDNode OpNode, bit Commutable = 0> {
3445 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
3446 OpcodeStr, !strconcat(Dt, "8"),
3447 v8i16, v8i8, OpNode, Commutable>;
3448 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
3449 OpcodeStr, !strconcat(Dt, "16"),
3450 v4i32, v4i16, OpNode, Commutable>;
3451 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
3452 OpcodeStr, !strconcat(Dt, "32"),
3453 v2i64, v2i32, OpNode, Commutable>;
3456 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
3457 InstrItinClass itin, string OpcodeStr, string Dt,
3459 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
3460 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
3461 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
3462 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
3465 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3466 InstrItinClass itin16, InstrItinClass itin32,
3467 string OpcodeStr, string Dt,
3468 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3469 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
3470 OpcodeStr, !strconcat(Dt, "8"),
3471 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3472 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
3473 OpcodeStr, !strconcat(Dt, "16"),
3474 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3475 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
3476 OpcodeStr, !strconcat(Dt, "32"),
3477 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3480 // Neon Long 3-register vector intrinsics.
3482 // First with only element sizes of 16 and 32 bits:
3483 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3484 InstrItinClass itin16, InstrItinClass itin32,
3485 string OpcodeStr, string Dt,
3486 SDPatternOperator IntOp, bit Commutable = 0> {
3487 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
3488 OpcodeStr, !strconcat(Dt, "16"),
3489 v4i32, v4i16, IntOp, Commutable>;
3490 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
3491 OpcodeStr, !strconcat(Dt, "32"),
3492 v2i64, v2i32, IntOp, Commutable>;
3495 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
3496 InstrItinClass itin, string OpcodeStr, string Dt,
3497 SDPatternOperator IntOp> {
3498 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
3499 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3500 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
3501 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3504 // ....then also with element size of 8 bits:
3505 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3506 InstrItinClass itin16, InstrItinClass itin32,
3507 string OpcodeStr, string Dt,
3508 SDPatternOperator IntOp, bit Commutable = 0>
3509 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
3510 IntOp, Commutable> {
3511 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
3512 OpcodeStr, !strconcat(Dt, "8"),
3513 v8i16, v8i8, IntOp, Commutable>;
3516 // ....with explicit extend (VABDL).
3517 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3518 InstrItinClass itin, string OpcodeStr, string Dt,
3519 SDPatternOperator IntOp, SDNode ExtOp, bit Commutable = 0> {
3520 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
3521 OpcodeStr, !strconcat(Dt, "8"),
3522 v8i16, v8i8, IntOp, ExtOp, Commutable>;
3523 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
3524 OpcodeStr, !strconcat(Dt, "16"),
3525 v4i32, v4i16, IntOp, ExtOp, Commutable>;
3526 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
3527 OpcodeStr, !strconcat(Dt, "32"),
3528 v2i64, v2i32, IntOp, ExtOp, Commutable>;
3532 // Neon Wide 3-register vector intrinsics,
3533 // source operand element sizes of 8, 16 and 32 bits:
3534 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3535 string OpcodeStr, string Dt,
3536 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3537 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
3538 OpcodeStr, !strconcat(Dt, "8"),
3539 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3540 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
3541 OpcodeStr, !strconcat(Dt, "16"),
3542 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3543 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
3544 OpcodeStr, !strconcat(Dt, "32"),
3545 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3549 // Neon Multiply-Op vector operations,
3550 // element sizes of 8, 16 and 32 bits:
3551 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3552 InstrItinClass itinD16, InstrItinClass itinD32,
3553 InstrItinClass itinQ16, InstrItinClass itinQ32,
3554 string OpcodeStr, string Dt, SDNode OpNode> {
3555 // 64-bit vector types.
3556 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
3557 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
3558 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
3559 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
3560 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
3561 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
3563 // 128-bit vector types.
3564 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
3565 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
3566 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
3567 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
3568 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
3569 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
3572 multiclass N3VMulOpSL_HS<bits<4> op11_8,
3573 InstrItinClass itinD16, InstrItinClass itinD32,
3574 InstrItinClass itinQ16, InstrItinClass itinQ32,
3575 string OpcodeStr, string Dt, SDNode ShOp> {
3576 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
3577 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
3578 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
3579 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
3580 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
3581 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
3583 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
3584 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
3588 // Neon Intrinsic-Op vector operations,
3589 // element sizes of 8, 16 and 32 bits:
3590 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3591 InstrItinClass itinD, InstrItinClass itinQ,
3592 string OpcodeStr, string Dt, SDPatternOperator IntOp,
3594 // 64-bit vector types.
3595 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
3596 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
3597 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
3598 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
3599 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
3600 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
3602 // 128-bit vector types.
3603 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
3604 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
3605 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
3606 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
3607 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
3608 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
3611 // Neon 3-argument intrinsics,
3612 // element sizes of 8, 16 and 32 bits:
3613 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3614 InstrItinClass itinD, InstrItinClass itinQ,
3615 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3616 // 64-bit vector types.
3617 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
3618 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
3619 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
3620 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
3621 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
3622 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
3624 // 128-bit vector types.
3625 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
3626 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
3627 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
3628 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
3629 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
3630 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
3634 // Neon Long Multiply-Op vector operations,
3635 // element sizes of 8, 16 and 32 bits:
3636 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3637 InstrItinClass itin16, InstrItinClass itin32,
3638 string OpcodeStr, string Dt, SDNode MulOp,
3640 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
3641 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
3642 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
3643 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
3644 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
3645 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3648 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
3649 string Dt, SDNode MulOp, SDNode OpNode> {
3650 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
3651 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
3652 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
3653 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3657 // Neon Long 3-argument intrinsics.
3659 // First with only element sizes of 16 and 32 bits:
3660 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3661 InstrItinClass itin16, InstrItinClass itin32,
3662 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3663 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
3664 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3665 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
3666 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3669 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
3670 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3671 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
3672 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
3673 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
3674 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3677 // ....then also with element size of 8 bits:
3678 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3679 InstrItinClass itin16, InstrItinClass itin32,
3680 string OpcodeStr, string Dt, SDPatternOperator IntOp>
3681 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
3682 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
3683 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
3686 // ....with explicit extend (VABAL).
3687 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3688 InstrItinClass itin, string OpcodeStr, string Dt,
3689 SDPatternOperator IntOp, SDNode ExtOp, SDNode OpNode> {
3690 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
3691 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
3692 IntOp, ExtOp, OpNode>;
3693 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
3694 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
3695 IntOp, ExtOp, OpNode>;
3696 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
3697 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
3698 IntOp, ExtOp, OpNode>;
3702 // Neon Pairwise long 2-register intrinsics,
3703 // element sizes of 8, 16 and 32 bits:
3704 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3705 bits<5> op11_7, bit op4,
3706 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3707 // 64-bit vector types.
3708 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3709 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3710 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3711 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3712 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3713 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3715 // 128-bit vector types.
3716 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3717 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3718 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3719 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3720 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3721 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3725 // Neon Pairwise long 2-register accumulate intrinsics,
3726 // element sizes of 8, 16 and 32 bits:
3727 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3728 bits<5> op11_7, bit op4,
3729 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3730 // 64-bit vector types.
3731 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3732 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3733 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3734 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3735 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3736 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3738 // 128-bit vector types.
3739 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3740 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3741 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3742 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3743 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3744 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3748 // Neon 2-register vector shift by immediate,
3749 // with f of either N2RegVShLFrm or N2RegVShRFrm
3750 // element sizes of 8, 16, 32 and 64 bits:
3751 multiclass N2VShL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3752 InstrItinClass itin, string OpcodeStr, string Dt,
3754 // 64-bit vector types.
3755 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3756 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3757 let Inst{21-19} = 0b001; // imm6 = 001xxx
3759 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3760 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3761 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3763 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3764 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3765 let Inst{21} = 0b1; // imm6 = 1xxxxx
3767 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3768 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3771 // 128-bit vector types.
3772 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3773 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3774 let Inst{21-19} = 0b001; // imm6 = 001xxx
3776 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3777 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3778 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3780 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3781 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3782 let Inst{21} = 0b1; // imm6 = 1xxxxx
3784 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3785 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3788 multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3789 InstrItinClass itin, string OpcodeStr, string Dt,
3790 string baseOpc, SDNode OpNode> {
3791 // 64-bit vector types.
3792 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3793 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3794 let Inst{21-19} = 0b001; // imm6 = 001xxx
3796 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3797 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3798 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3800 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3801 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3802 let Inst{21} = 0b1; // imm6 = 1xxxxx
3804 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3805 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3808 // 128-bit vector types.
3809 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3810 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3811 let Inst{21-19} = 0b001; // imm6 = 001xxx
3813 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3814 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3815 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3817 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3818 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3819 let Inst{21} = 0b1; // imm6 = 1xxxxx
3821 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3822 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3826 // Neon Shift-Accumulate vector operations,
3827 // element sizes of 8, 16, 32 and 64 bits:
3828 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3829 string OpcodeStr, string Dt, SDNode ShOp> {
3830 // 64-bit vector types.
3831 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3832 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
3833 let Inst{21-19} = 0b001; // imm6 = 001xxx
3835 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3836 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
3837 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3839 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3840 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
3841 let Inst{21} = 0b1; // imm6 = 1xxxxx
3843 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3844 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
3847 // 128-bit vector types.
3848 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3849 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
3850 let Inst{21-19} = 0b001; // imm6 = 001xxx
3852 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3853 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
3854 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3856 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3857 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
3858 let Inst{21} = 0b1; // imm6 = 1xxxxx
3860 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3861 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
3865 // Neon Shift-Insert vector operations,
3866 // with f of either N2RegVShLFrm or N2RegVShRFrm
3867 // element sizes of 8, 16, 32 and 64 bits:
3868 multiclass N2VShInsL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3870 // 64-bit vector types.
3871 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3872 N2RegVShLFrm, OpcodeStr, "8", v8i8, NEONvsli> {
3873 let Inst{21-19} = 0b001; // imm6 = 001xxx
3875 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3876 N2RegVShLFrm, OpcodeStr, "16", v4i16, NEONvsli> {
3877 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3879 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3880 N2RegVShLFrm, OpcodeStr, "32", v2i32, NEONvsli> {
3881 let Inst{21} = 0b1; // imm6 = 1xxxxx
3883 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, i32imm,
3884 N2RegVShLFrm, OpcodeStr, "64", v1i64, NEONvsli>;
3887 // 128-bit vector types.
3888 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3889 N2RegVShLFrm, OpcodeStr, "8", v16i8, NEONvsli> {
3890 let Inst{21-19} = 0b001; // imm6 = 001xxx
3892 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3893 N2RegVShLFrm, OpcodeStr, "16", v8i16, NEONvsli> {
3894 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3896 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3897 N2RegVShLFrm, OpcodeStr, "32", v4i32, NEONvsli> {
3898 let Inst{21} = 0b1; // imm6 = 1xxxxx
3900 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, i32imm,
3901 N2RegVShLFrm, OpcodeStr, "64", v2i64, NEONvsli>;
3904 multiclass N2VShInsR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3906 // 64-bit vector types.
3907 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3908 N2RegVShRFrm, OpcodeStr, "8", v8i8, NEONvsri> {
3909 let Inst{21-19} = 0b001; // imm6 = 001xxx
3911 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3912 N2RegVShRFrm, OpcodeStr, "16", v4i16, NEONvsri> {
3913 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3915 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3916 N2RegVShRFrm, OpcodeStr, "32", v2i32, NEONvsri> {
3917 let Inst{21} = 0b1; // imm6 = 1xxxxx
3919 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3920 N2RegVShRFrm, OpcodeStr, "64", v1i64, NEONvsri>;
3923 // 128-bit vector types.
3924 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3925 N2RegVShRFrm, OpcodeStr, "8", v16i8, NEONvsri> {
3926 let Inst{21-19} = 0b001; // imm6 = 001xxx
3928 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3929 N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsri> {
3930 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3932 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3933 N2RegVShRFrm, OpcodeStr, "32", v4i32, NEONvsri> {
3934 let Inst{21} = 0b1; // imm6 = 1xxxxx
3936 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3937 N2RegVShRFrm, OpcodeStr, "64", v2i64, NEONvsri>;
3941 // Neon Shift Long operations,
3942 // element sizes of 8, 16, 32 bits:
3943 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3944 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
3945 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3946 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, imm1_7, OpNode> {
3947 let Inst{21-19} = 0b001; // imm6 = 001xxx
3949 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3950 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, imm1_15, OpNode> {
3951 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3953 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3954 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, imm1_31, OpNode> {
3955 let Inst{21} = 0b1; // imm6 = 1xxxxx
3959 // Neon Shift Narrow operations,
3960 // element sizes of 16, 32, 64 bits:
3961 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3962 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
3964 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3965 OpcodeStr, !strconcat(Dt, "16"),
3966 v8i8, v8i16, shr_imm8, OpNode> {
3967 let Inst{21-19} = 0b001; // imm6 = 001xxx
3969 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3970 OpcodeStr, !strconcat(Dt, "32"),
3971 v4i16, v4i32, shr_imm16, OpNode> {
3972 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3974 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3975 OpcodeStr, !strconcat(Dt, "64"),
3976 v2i32, v2i64, shr_imm32, OpNode> {
3977 let Inst{21} = 0b1; // imm6 = 1xxxxx
3981 //===----------------------------------------------------------------------===//
3982 // Instruction Definitions.
3983 //===----------------------------------------------------------------------===//
3985 // Vector Add Operations.
3987 // VADD : Vector Add (integer and floating-point)
3988 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
3990 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
3991 v2f32, v2f32, fadd, 1>;
3992 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
3993 v4f32, v4f32, fadd, 1>;
3994 // VADDL : Vector Add Long (Q = D + D)
3995 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3996 "vaddl", "s", add, sext, 1>;
3997 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3998 "vaddl", "u", add, zext, 1>;
3999 // VADDW : Vector Add Wide (Q = Q + D)
4000 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
4001 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
4002 // VHADD : Vector Halving Add
4003 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
4004 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4005 "vhadd", "s", int_arm_neon_vhadds, 1>;
4006 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
4007 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4008 "vhadd", "u", int_arm_neon_vhaddu, 1>;
4009 // VRHADD : Vector Rounding Halving Add
4010 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
4011 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4012 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
4013 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
4014 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4015 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
4016 // VQADD : Vector Saturating Add
4017 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
4018 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4019 "vqadd", "s", int_arm_neon_vqadds, 1>;
4020 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
4021 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4022 "vqadd", "u", int_arm_neon_vqaddu, 1>;
4023 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
4024 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i", null_frag, 1>;
4025 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
4026 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
4027 int_arm_neon_vraddhn, 1>;
4029 def : Pat<(v8i8 (trunc (NEONvshru (add (v8i16 QPR:$Vn), QPR:$Vm), 8))),
4030 (VADDHNv8i8 QPR:$Vn, QPR:$Vm)>;
4031 def : Pat<(v4i16 (trunc (NEONvshru (add (v4i32 QPR:$Vn), QPR:$Vm), 16))),
4032 (VADDHNv4i16 QPR:$Vn, QPR:$Vm)>;
4033 def : Pat<(v2i32 (trunc (NEONvshru (add (v2i64 QPR:$Vn), QPR:$Vm), 32))),
4034 (VADDHNv2i32 QPR:$Vn, QPR:$Vm)>;
4036 // Vector Multiply Operations.
4038 // VMUL : Vector Multiply (integer, polynomial and floating-point)
4039 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
4040 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
4041 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
4042 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
4043 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
4044 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
4045 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
4046 v2f32, v2f32, fmul, 1>;
4047 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
4048 v4f32, v4f32, fmul, 1>;
4049 defm VMULsl : N3VSL_HS<0b1000, "vmul", mul>;
4050 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
4051 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
4054 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
4055 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
4056 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
4057 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4058 (DSubReg_i16_reg imm:$lane))),
4059 (SubReg_i16_lane imm:$lane)))>;
4060 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
4061 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
4062 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
4063 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4064 (DSubReg_i32_reg imm:$lane))),
4065 (SubReg_i32_lane imm:$lane)))>;
4066 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
4067 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
4068 (v4f32 (VMULslfq (v4f32 QPR:$src1),
4069 (v2f32 (EXTRACT_SUBREG QPR:$src2,
4070 (DSubReg_i32_reg imm:$lane))),
4071 (SubReg_i32_lane imm:$lane)))>;
4074 def : Pat<(v2f32 (fmul DPR:$Rn, (NEONvdup (f32 SPR:$Rm)))),
4076 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0),
4078 def : Pat<(v4f32 (fmul QPR:$Rn, (NEONvdup (f32 SPR:$Rm)))),
4080 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0),
4084 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
4085 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
4086 IIC_VMULi16Q, IIC_VMULi32Q,
4087 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
4088 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
4089 IIC_VMULi16Q, IIC_VMULi32Q,
4090 "vqdmulh", "s", int_arm_neon_vqdmulh>;
4091 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
4092 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
4094 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
4095 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4096 (DSubReg_i16_reg imm:$lane))),
4097 (SubReg_i16_lane imm:$lane)))>;
4098 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
4099 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
4101 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
4102 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4103 (DSubReg_i32_reg imm:$lane))),
4104 (SubReg_i32_lane imm:$lane)))>;
4106 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
4107 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
4108 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
4109 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
4110 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
4111 IIC_VMULi16Q, IIC_VMULi32Q,
4112 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
4113 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
4114 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
4116 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
4117 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4118 (DSubReg_i16_reg imm:$lane))),
4119 (SubReg_i16_lane imm:$lane)))>;
4120 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
4121 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
4123 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
4124 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4125 (DSubReg_i32_reg imm:$lane))),
4126 (SubReg_i32_lane imm:$lane)))>;
4128 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
4129 let PostEncoderMethod = "NEONThumb2DataIPostEncoder",
4130 DecoderNamespace = "NEONData" in {
4131 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
4132 "vmull", "s", NEONvmulls, 1>;
4133 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
4134 "vmull", "u", NEONvmullu, 1>;
4135 def VMULLp8 : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
4136 v8i16, v8i8, int_arm_neon_vmullp, 1>;
4137 def VMULLp64 : N3VLIntnp<0b00101, 0b10, 0b1110, 0, 0, NoItinerary,
4138 "vmull", "p64", v2i64, v1i64, int_arm_neon_vmullp, 1>,
4139 Requires<[HasV8, HasCrypto]>;
4141 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
4142 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
4144 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
4145 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
4146 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
4147 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
4148 "vqdmull", "s", int_arm_neon_vqdmull>;
4150 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
4152 // VMLA : Vector Multiply Accumulate (integer and floating-point)
4153 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
4154 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
4155 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
4156 v2f32, fmul_su, fadd_mlx>,
4157 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4158 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
4159 v4f32, fmul_su, fadd_mlx>,
4160 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4161 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
4162 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
4163 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
4164 v2f32, fmul_su, fadd_mlx>,
4165 Requires<[HasNEON, UseFPVMLx]>;
4166 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
4167 v4f32, v2f32, fmul_su, fadd_mlx>,
4168 Requires<[HasNEON, UseFPVMLx]>;
4170 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
4171 (mul (v8i16 QPR:$src2),
4172 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4173 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
4174 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4175 (DSubReg_i16_reg imm:$lane))),
4176 (SubReg_i16_lane imm:$lane)))>;
4178 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
4179 (mul (v4i32 QPR:$src2),
4180 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4181 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
4182 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4183 (DSubReg_i32_reg imm:$lane))),
4184 (SubReg_i32_lane imm:$lane)))>;
4186 def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1),
4187 (fmul_su (v4f32 QPR:$src2),
4188 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
4189 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
4191 (v2f32 (EXTRACT_SUBREG QPR:$src3,
4192 (DSubReg_i32_reg imm:$lane))),
4193 (SubReg_i32_lane imm:$lane)))>,
4194 Requires<[HasNEON, UseFPVMLx]>;
4196 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
4197 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
4198 "vmlal", "s", NEONvmulls, add>;
4199 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
4200 "vmlal", "u", NEONvmullu, add>;
4202 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
4203 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
4205 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
4206 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
4207 "vqdmlal", "s", null_frag>;
4208 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", null_frag>;
4210 def : Pat<(v4i32 (int_arm_neon_vqadds (v4i32 QPR:$src1),
4211 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4212 (v4i16 DPR:$Vm))))),
4213 (VQDMLALv4i32 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4214 def : Pat<(v2i64 (int_arm_neon_vqadds (v2i64 QPR:$src1),
4215 (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn),
4216 (v2i32 DPR:$Vm))))),
4217 (VQDMLALv2i64 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4218 def : Pat<(v4i32 (int_arm_neon_vqadds (v4i32 QPR:$src1),
4219 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4220 (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm),
4222 (VQDMLALslv4i16 QPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane)>;
4223 def : Pat<(v2i64 (int_arm_neon_vqadds (v2i64 QPR:$src1),
4224 (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn),
4225 (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm),
4227 (VQDMLALslv2i32 QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane)>;
4229 // VMLS : Vector Multiply Subtract (integer and floating-point)
4230 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
4231 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
4232 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
4233 v2f32, fmul_su, fsub_mlx>,
4234 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4235 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
4236 v4f32, fmul_su, fsub_mlx>,
4237 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4238 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
4239 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
4240 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
4241 v2f32, fmul_su, fsub_mlx>,
4242 Requires<[HasNEON, UseFPVMLx]>;
4243 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
4244 v4f32, v2f32, fmul_su, fsub_mlx>,
4245 Requires<[HasNEON, UseFPVMLx]>;
4247 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
4248 (mul (v8i16 QPR:$src2),
4249 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4250 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
4251 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4252 (DSubReg_i16_reg imm:$lane))),
4253 (SubReg_i16_lane imm:$lane)))>;
4255 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
4256 (mul (v4i32 QPR:$src2),
4257 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4258 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
4259 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4260 (DSubReg_i32_reg imm:$lane))),
4261 (SubReg_i32_lane imm:$lane)))>;
4263 def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1),
4264 (fmul_su (v4f32 QPR:$src2),
4265 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
4266 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
4267 (v2f32 (EXTRACT_SUBREG QPR:$src3,
4268 (DSubReg_i32_reg imm:$lane))),
4269 (SubReg_i32_lane imm:$lane)))>,
4270 Requires<[HasNEON, UseFPVMLx]>;
4272 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
4273 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
4274 "vmlsl", "s", NEONvmulls, sub>;
4275 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
4276 "vmlsl", "u", NEONvmullu, sub>;
4278 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
4279 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
4281 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
4282 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
4283 "vqdmlsl", "s", null_frag>;
4284 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", null_frag>;
4286 def : Pat<(v4i32 (int_arm_neon_vqsubs (v4i32 QPR:$src1),
4287 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4288 (v4i16 DPR:$Vm))))),
4289 (VQDMLSLv4i32 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4290 def : Pat<(v2i64 (int_arm_neon_vqsubs (v2i64 QPR:$src1),
4291 (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn),
4292 (v2i32 DPR:$Vm))))),
4293 (VQDMLSLv2i64 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4294 def : Pat<(v4i32 (int_arm_neon_vqsubs (v4i32 QPR:$src1),
4295 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4296 (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm),
4298 (VQDMLSLslv4i16 QPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane)>;
4299 def : Pat<(v2i64 (int_arm_neon_vqsubs (v2i64 QPR:$src1),
4300 (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn),
4301 (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm),
4303 (VQDMLSLslv2i32 QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane)>;
4305 // Fused Vector Multiply-Accumulate and Fused Multiply-Subtract Operations.
4306 def VFMAfd : N3VDMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACD, "vfma", "f32",
4307 v2f32, fmul_su, fadd_mlx>,
4308 Requires<[HasNEON,HasVFP4,UseFusedMAC]>;
4310 def VFMAfq : N3VQMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACQ, "vfma", "f32",
4311 v4f32, fmul_su, fadd_mlx>,
4312 Requires<[HasNEON,HasVFP4,UseFusedMAC]>;
4314 // Fused Vector Multiply Subtract (floating-point)
4315 def VFMSfd : N3VDMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACD, "vfms", "f32",
4316 v2f32, fmul_su, fsub_mlx>,
4317 Requires<[HasNEON,HasVFP4,UseFusedMAC]>;
4318 def VFMSfq : N3VQMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACQ, "vfms", "f32",
4319 v4f32, fmul_su, fsub_mlx>,
4320 Requires<[HasNEON,HasVFP4,UseFusedMAC]>;
4322 // Match @llvm.fma.* intrinsics
4323 def : Pat<(v2f32 (fma DPR:$Vn, DPR:$Vm, DPR:$src1)),
4324 (VFMAfd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4325 Requires<[HasVFP4]>;
4326 def : Pat<(v4f32 (fma QPR:$Vn, QPR:$Vm, QPR:$src1)),
4327 (VFMAfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4328 Requires<[HasVFP4]>;
4329 def : Pat<(v2f32 (fma (fneg DPR:$Vn), DPR:$Vm, DPR:$src1)),
4330 (VFMSfd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4331 Requires<[HasVFP4]>;
4332 def : Pat<(v4f32 (fma (fneg QPR:$Vn), QPR:$Vm, QPR:$src1)),
4333 (VFMSfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4334 Requires<[HasVFP4]>;
4336 // Vector Subtract Operations.
4338 // VSUB : Vector Subtract (integer and floating-point)
4339 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
4340 "vsub", "i", sub, 0>;
4341 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
4342 v2f32, v2f32, fsub, 0>;
4343 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
4344 v4f32, v4f32, fsub, 0>;
4345 // VSUBL : Vector Subtract Long (Q = D - D)
4346 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
4347 "vsubl", "s", sub, sext, 0>;
4348 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
4349 "vsubl", "u", sub, zext, 0>;
4350 // VSUBW : Vector Subtract Wide (Q = Q - D)
4351 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
4352 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
4353 // VHSUB : Vector Halving Subtract
4354 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
4355 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4356 "vhsub", "s", int_arm_neon_vhsubs, 0>;
4357 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
4358 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4359 "vhsub", "u", int_arm_neon_vhsubu, 0>;
4360 // VQSUB : Vector Saturing Subtract
4361 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
4362 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4363 "vqsub", "s", int_arm_neon_vqsubs, 0>;
4364 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
4365 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4366 "vqsub", "u", int_arm_neon_vqsubu, 0>;
4367 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
4368 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i", null_frag, 0>;
4369 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
4370 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
4371 int_arm_neon_vrsubhn, 0>;
4373 def : Pat<(v8i8 (trunc (NEONvshru (sub (v8i16 QPR:$Vn), QPR:$Vm), 8))),
4374 (VSUBHNv8i8 QPR:$Vn, QPR:$Vm)>;
4375 def : Pat<(v4i16 (trunc (NEONvshru (sub (v4i32 QPR:$Vn), QPR:$Vm), 16))),
4376 (VSUBHNv4i16 QPR:$Vn, QPR:$Vm)>;
4377 def : Pat<(v2i32 (trunc (NEONvshru (sub (v2i64 QPR:$Vn), QPR:$Vm), 32))),
4378 (VSUBHNv2i32 QPR:$Vn, QPR:$Vm)>;
4380 // Vector Comparisons.
4382 // VCEQ : Vector Compare Equal
4383 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4384 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
4385 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
4387 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
4390 let TwoOperandAliasConstraint = "$Vm = $Vd" in
4391 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
4392 "$Vd, $Vm, #0", NEONvceqz>;
4394 // VCGE : Vector Compare Greater Than or Equal
4395 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4396 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
4397 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4398 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
4399 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
4401 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
4404 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
4405 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
4406 "$Vd, $Vm, #0", NEONvcgez>;
4407 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
4408 "$Vd, $Vm, #0", NEONvclez>;
4411 // VCGT : Vector Compare Greater Than
4412 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4413 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
4414 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4415 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
4416 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
4418 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
4421 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
4422 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
4423 "$Vd, $Vm, #0", NEONvcgtz>;
4424 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
4425 "$Vd, $Vm, #0", NEONvcltz>;
4428 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
4429 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
4430 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
4431 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
4432 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
4433 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
4434 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
4435 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
4436 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
4437 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
4438 // VTST : Vector Test Bits
4439 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
4440 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
4442 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vn, $Vm",
4443 (VACGTd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
4444 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vn, $Vm",
4445 (VACGTq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
4446 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vn, $Vm",
4447 (VACGEd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
4448 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vn, $Vm",
4449 (VACGEq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
4451 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vm",
4452 (VACGTd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
4453 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vm",
4454 (VACGTq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
4455 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vm",
4456 (VACGEd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
4457 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vm",
4458 (VACGEq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
4460 // Vector Bitwise Operations.
4462 def vnotd : PatFrag<(ops node:$in),
4463 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
4464 def vnotq : PatFrag<(ops node:$in),
4465 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
4468 // VAND : Vector Bitwise AND
4469 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
4470 v2i32, v2i32, and, 1>;
4471 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
4472 v4i32, v4i32, and, 1>;
4474 // VEOR : Vector Bitwise Exclusive OR
4475 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
4476 v2i32, v2i32, xor, 1>;
4477 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
4478 v4i32, v4i32, xor, 1>;
4480 // VORR : Vector Bitwise OR
4481 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
4482 v2i32, v2i32, or, 1>;
4483 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
4484 v4i32, v4i32, or, 1>;
4486 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
4487 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4489 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4491 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4492 let Inst{9} = SIMM{9};
4495 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
4496 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4498 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4500 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4501 let Inst{10-9} = SIMM{10-9};
4504 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
4505 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4507 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4509 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4510 let Inst{9} = SIMM{9};
4513 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
4514 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4516 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4518 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4519 let Inst{10-9} = SIMM{10-9};
4523 // VBIC : Vector Bitwise Bit Clear (AND NOT)
4524 let TwoOperandAliasConstraint = "$Vn = $Vd" in {
4525 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4526 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
4527 "vbic", "$Vd, $Vn, $Vm", "",
4528 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
4529 (vnotd DPR:$Vm))))]>;
4530 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4531 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4532 "vbic", "$Vd, $Vn, $Vm", "",
4533 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
4534 (vnotq QPR:$Vm))))]>;
4537 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
4538 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4540 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4542 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4543 let Inst{9} = SIMM{9};
4546 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
4547 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4549 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4551 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4552 let Inst{10-9} = SIMM{10-9};
4555 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
4556 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4558 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4560 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4561 let Inst{9} = SIMM{9};
4564 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
4565 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4567 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4569 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4570 let Inst{10-9} = SIMM{10-9};
4573 // VORN : Vector Bitwise OR NOT
4574 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
4575 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
4576 "vorn", "$Vd, $Vn, $Vm", "",
4577 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
4578 (vnotd DPR:$Vm))))]>;
4579 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
4580 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4581 "vorn", "$Vd, $Vn, $Vm", "",
4582 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
4583 (vnotq QPR:$Vm))))]>;
4585 // VMVN : Vector Bitwise NOT (Immediate)
4587 let isReMaterializable = 1 in {
4589 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
4590 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4591 "vmvn", "i16", "$Vd, $SIMM", "",
4592 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
4593 let Inst{9} = SIMM{9};
4596 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
4597 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4598 "vmvn", "i16", "$Vd, $SIMM", "",
4599 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
4600 let Inst{9} = SIMM{9};
4603 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
4604 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4605 "vmvn", "i32", "$Vd, $SIMM", "",
4606 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
4607 let Inst{11-8} = SIMM{11-8};
4610 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
4611 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4612 "vmvn", "i32", "$Vd, $SIMM", "",
4613 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
4614 let Inst{11-8} = SIMM{11-8};
4618 // VMVN : Vector Bitwise NOT
4619 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
4620 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
4621 "vmvn", "$Vd, $Vm", "",
4622 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
4623 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
4624 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
4625 "vmvn", "$Vd, $Vm", "",
4626 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
4627 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
4628 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
4630 // VBSL : Vector Bitwise Select
4631 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4632 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4633 N3RegFrm, IIC_VCNTiD,
4634 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4636 (v2i32 (NEONvbsl DPR:$src1, DPR:$Vn, DPR:$Vm)))]>;
4637 def : Pat<(v8i8 (int_arm_neon_vbsl (v8i8 DPR:$src1),
4638 (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))),
4639 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4640 Requires<[HasNEON]>;
4641 def : Pat<(v4i16 (int_arm_neon_vbsl (v4i16 DPR:$src1),
4642 (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))),
4643 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4644 Requires<[HasNEON]>;
4645 def : Pat<(v2i32 (int_arm_neon_vbsl (v2i32 DPR:$src1),
4646 (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))),
4647 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4648 Requires<[HasNEON]>;
4649 def : Pat<(v2f32 (int_arm_neon_vbsl (v2f32 DPR:$src1),
4650 (v2f32 DPR:$Vn), (v2f32 DPR:$Vm))),
4651 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4652 Requires<[HasNEON]>;
4653 def : Pat<(v1i64 (int_arm_neon_vbsl (v1i64 DPR:$src1),
4654 (v1i64 DPR:$Vn), (v1i64 DPR:$Vm))),
4655 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4656 Requires<[HasNEON]>;
4658 def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
4659 (and DPR:$Vm, (vnotd DPR:$Vd)))),
4660 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>,
4661 Requires<[HasNEON]>;
4663 def : Pat<(v1i64 (or (and DPR:$Vn, DPR:$Vd),
4664 (and DPR:$Vm, (vnotd DPR:$Vd)))),
4665 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>,
4666 Requires<[HasNEON]>;
4668 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4669 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4670 N3RegFrm, IIC_VCNTiQ,
4671 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4673 (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>;
4675 def : Pat<(v16i8 (int_arm_neon_vbsl (v16i8 QPR:$src1),
4676 (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))),
4677 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4678 Requires<[HasNEON]>;
4679 def : Pat<(v8i16 (int_arm_neon_vbsl (v8i16 QPR:$src1),
4680 (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))),
4681 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4682 Requires<[HasNEON]>;
4683 def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 QPR:$src1),
4684 (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))),
4685 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4686 Requires<[HasNEON]>;
4687 def : Pat<(v4f32 (int_arm_neon_vbsl (v4f32 QPR:$src1),
4688 (v4f32 QPR:$Vn), (v4f32 QPR:$Vm))),
4689 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4690 Requires<[HasNEON]>;
4691 def : Pat<(v2i64 (int_arm_neon_vbsl (v2i64 QPR:$src1),
4692 (v2i64 QPR:$Vn), (v2i64 QPR:$Vm))),
4693 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4694 Requires<[HasNEON]>;
4696 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
4697 (and QPR:$Vm, (vnotq QPR:$Vd)))),
4698 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>,
4699 Requires<[HasNEON]>;
4700 def : Pat<(v2i64 (or (and QPR:$Vn, QPR:$Vd),
4701 (and QPR:$Vm, (vnotq QPR:$Vd)))),
4702 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>,
4703 Requires<[HasNEON]>;
4705 // VBIF : Vector Bitwise Insert if False
4706 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
4707 // FIXME: This instruction's encoding MAY NOT BE correct.
4708 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
4709 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4710 N3RegFrm, IIC_VBINiD,
4711 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4713 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
4714 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4715 N3RegFrm, IIC_VBINiQ,
4716 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4719 // VBIT : Vector Bitwise Insert if True
4720 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
4721 // FIXME: This instruction's encoding MAY NOT BE correct.
4722 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
4723 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4724 N3RegFrm, IIC_VBINiD,
4725 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4727 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
4728 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4729 N3RegFrm, IIC_VBINiQ,
4730 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4733 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
4734 // for equivalent operations with different register constraints; it just
4737 // Vector Absolute Differences.
4739 // VABD : Vector Absolute Difference
4740 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
4741 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4742 "vabd", "s", int_arm_neon_vabds, 1>;
4743 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
4744 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4745 "vabd", "u", int_arm_neon_vabdu, 1>;
4746 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
4747 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
4748 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
4749 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
4751 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
4752 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
4753 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
4754 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
4755 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
4757 // VABA : Vector Absolute Difference and Accumulate
4758 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4759 "vaba", "s", int_arm_neon_vabds, add>;
4760 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4761 "vaba", "u", int_arm_neon_vabdu, add>;
4763 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
4764 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
4765 "vabal", "s", int_arm_neon_vabds, zext, add>;
4766 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
4767 "vabal", "u", int_arm_neon_vabdu, zext, add>;
4769 // Vector Maximum and Minimum.
4771 // VMAX : Vector Maximum
4772 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
4773 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4774 "vmax", "s", int_arm_neon_vmaxs, 1>;
4775 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
4776 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4777 "vmax", "u", int_arm_neon_vmaxu, 1>;
4778 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
4780 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
4781 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4783 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
4786 let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
4787 def VMAXNMND : N3VDIntnp<0b00110, 0b00, 0b1111, 0, 1,
4788 N3RegFrm, NoItinerary, "vmaxnm", "f32",
4789 v2f32, v2f32, int_arm_neon_vmaxnm, 1>,
4790 Requires<[HasV8, HasNEON]>;
4791 def VMAXNMNQ : N3VQIntnp<0b00110, 0b00, 0b1111, 1, 1,
4792 N3RegFrm, NoItinerary, "vmaxnm", "f32",
4793 v4f32, v4f32, int_arm_neon_vmaxnm, 1>,
4794 Requires<[HasV8, HasNEON]>;
4797 // VMIN : Vector Minimum
4798 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
4799 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4800 "vmin", "s", int_arm_neon_vmins, 1>;
4801 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
4802 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4803 "vmin", "u", int_arm_neon_vminu, 1>;
4804 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
4806 v2f32, v2f32, int_arm_neon_vmins, 1>;
4807 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4809 v4f32, v4f32, int_arm_neon_vmins, 1>;
4812 let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
4813 def VMINNMND : N3VDIntnp<0b00110, 0b10, 0b1111, 0, 1,
4814 N3RegFrm, NoItinerary, "vminnm", "f32",
4815 v2f32, v2f32, int_arm_neon_vminnm, 1>,
4816 Requires<[HasV8, HasNEON]>;
4817 def VMINNMNQ : N3VQIntnp<0b00110, 0b10, 0b1111, 1, 1,
4818 N3RegFrm, NoItinerary, "vminnm", "f32",
4819 v4f32, v4f32, int_arm_neon_vminnm, 1>,
4820 Requires<[HasV8, HasNEON]>;
4823 // Vector Pairwise Operations.
4825 // VPADD : Vector Pairwise Add
4826 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4828 v8i8, v8i8, int_arm_neon_vpadd, 0>;
4829 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4831 v4i16, v4i16, int_arm_neon_vpadd, 0>;
4832 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4834 v2i32, v2i32, int_arm_neon_vpadd, 0>;
4835 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
4836 IIC_VPBIND, "vpadd", "f32",
4837 v2f32, v2f32, int_arm_neon_vpadd, 0>;
4839 // VPADDL : Vector Pairwise Add Long
4840 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
4841 int_arm_neon_vpaddls>;
4842 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
4843 int_arm_neon_vpaddlu>;
4845 // VPADAL : Vector Pairwise Add and Accumulate Long
4846 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
4847 int_arm_neon_vpadals>;
4848 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
4849 int_arm_neon_vpadalu>;
4851 // VPMAX : Vector Pairwise Maximum
4852 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4853 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
4854 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4855 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
4856 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4857 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
4858 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4859 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
4860 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4861 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
4862 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4863 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
4864 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
4865 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
4867 // VPMIN : Vector Pairwise Minimum
4868 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4869 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
4870 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4871 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
4872 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4873 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
4874 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4875 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
4876 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4877 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
4878 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4879 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
4880 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
4881 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
4883 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
4885 // VRECPE : Vector Reciprocal Estimate
4886 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4887 IIC_VUNAD, "vrecpe", "u32",
4888 v2i32, v2i32, int_arm_neon_vrecpe>;
4889 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4890 IIC_VUNAQ, "vrecpe", "u32",
4891 v4i32, v4i32, int_arm_neon_vrecpe>;
4892 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4893 IIC_VUNAD, "vrecpe", "f32",
4894 v2f32, v2f32, int_arm_neon_vrecpe>;
4895 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4896 IIC_VUNAQ, "vrecpe", "f32",
4897 v4f32, v4f32, int_arm_neon_vrecpe>;
4899 // VRECPS : Vector Reciprocal Step
4900 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4901 IIC_VRECSD, "vrecps", "f32",
4902 v2f32, v2f32, int_arm_neon_vrecps, 1>;
4903 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4904 IIC_VRECSQ, "vrecps", "f32",
4905 v4f32, v4f32, int_arm_neon_vrecps, 1>;
4907 // VRSQRTE : Vector Reciprocal Square Root Estimate
4908 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4909 IIC_VUNAD, "vrsqrte", "u32",
4910 v2i32, v2i32, int_arm_neon_vrsqrte>;
4911 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4912 IIC_VUNAQ, "vrsqrte", "u32",
4913 v4i32, v4i32, int_arm_neon_vrsqrte>;
4914 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4915 IIC_VUNAD, "vrsqrte", "f32",
4916 v2f32, v2f32, int_arm_neon_vrsqrte>;
4917 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4918 IIC_VUNAQ, "vrsqrte", "f32",
4919 v4f32, v4f32, int_arm_neon_vrsqrte>;
4921 // VRSQRTS : Vector Reciprocal Square Root Step
4922 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4923 IIC_VRECSD, "vrsqrts", "f32",
4924 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
4925 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4926 IIC_VRECSQ, "vrsqrts", "f32",
4927 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
4931 // VSHL : Vector Shift
4932 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
4933 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4934 "vshl", "s", int_arm_neon_vshifts>;
4935 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
4936 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4937 "vshl", "u", int_arm_neon_vshiftu>;
4939 // VSHL : Vector Shift Left (Immediate)
4940 defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
4942 // VSHR : Vector Shift Right (Immediate)
4943 defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", "VSHRs",
4945 defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", "VSHRu",
4948 // VSHLL : Vector Shift Left Long
4949 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
4950 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
4952 // VSHLL : Vector Shift Left Long (with maximum shift count)
4953 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
4954 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
4955 ValueType OpTy, Operand ImmTy, SDNode OpNode>
4956 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
4957 ResTy, OpTy, ImmTy, OpNode> {
4958 let Inst{21-16} = op21_16;
4959 let DecoderMethod = "DecodeVSHLMaxInstruction";
4961 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
4962 v8i16, v8i8, imm8, NEONvshlli>;
4963 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
4964 v4i32, v4i16, imm16, NEONvshlli>;
4965 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
4966 v2i64, v2i32, imm32, NEONvshlli>;
4968 // VSHRN : Vector Shift Right and Narrow
4969 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
4972 // VRSHL : Vector Rounding Shift
4973 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
4974 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4975 "vrshl", "s", int_arm_neon_vrshifts>;
4976 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
4977 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4978 "vrshl", "u", int_arm_neon_vrshiftu>;
4979 // VRSHR : Vector Rounding Shift Right
4980 defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", "VRSHRs",
4982 defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", "VRSHRu",
4985 // VRSHRN : Vector Rounding Shift Right and Narrow
4986 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
4989 // VQSHL : Vector Saturating Shift
4990 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
4991 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4992 "vqshl", "s", int_arm_neon_vqshifts>;
4993 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
4994 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4995 "vqshl", "u", int_arm_neon_vqshiftu>;
4996 // VQSHL : Vector Saturating Shift Left (Immediate)
4997 defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls>;
4998 defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu>;
5000 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
5001 defm VQSHLsu : N2VShL_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu>;
5003 // VQSHRN : Vector Saturating Shift Right and Narrow
5004 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
5006 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
5009 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
5010 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
5013 // VQRSHL : Vector Saturating Rounding Shift
5014 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
5015 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5016 "vqrshl", "s", int_arm_neon_vqrshifts>;
5017 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
5018 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5019 "vqrshl", "u", int_arm_neon_vqrshiftu>;
5021 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
5022 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
5024 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
5027 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
5028 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
5031 // VSRA : Vector Shift Right and Accumulate
5032 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
5033 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
5034 // VRSRA : Vector Rounding Shift Right and Accumulate
5035 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
5036 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
5038 // VSLI : Vector Shift Left and Insert
5039 defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">;
5041 // VSRI : Vector Shift Right and Insert
5042 defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;
5044 // Vector Absolute and Saturating Absolute.
5046 // VABS : Vector Absolute Value
5047 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
5048 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
5050 def VABSfd : N2VD<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
5052 v2f32, v2f32, fabs>;
5053 def VABSfq : N2VQ<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
5055 v4f32, v4f32, fabs>;
5057 def : Pat<(xor (v2i32 (bitconvert (v8i8 (NEONvshrs DPR:$src, (i32 7))))),
5058 (v2i32 (bitconvert (v8i8 (add DPR:$src,
5059 (NEONvshrs DPR:$src, (i32 7))))))),
5060 (VABSv8i8 DPR:$src)>;
5061 def : Pat<(xor (v2i32 (bitconvert (v4i16 (NEONvshrs DPR:$src, (i32 15))))),
5062 (v2i32 (bitconvert (v4i16 (add DPR:$src,
5063 (NEONvshrs DPR:$src, (i32 15))))))),
5064 (VABSv4i16 DPR:$src)>;
5065 def : Pat<(xor (v2i32 (NEONvshrs DPR:$src, (i32 31))),
5066 (v2i32 (add DPR:$src, (NEONvshrs DPR:$src, (i32 31))))),
5067 (VABSv2i32 DPR:$src)>;
5068 def : Pat<(xor (v4i32 (bitconvert (v16i8 (NEONvshrs QPR:$src, (i32 7))))),
5069 (v4i32 (bitconvert (v16i8 (add QPR:$src,
5070 (NEONvshrs QPR:$src, (i32 7))))))),
5071 (VABSv16i8 QPR:$src)>;
5072 def : Pat<(xor (v4i32 (bitconvert (v8i16 (NEONvshrs QPR:$src, (i32 15))))),
5073 (v4i32 (bitconvert (v8i16 (add QPR:$src,
5074 (NEONvshrs QPR:$src, (i32 15))))))),
5075 (VABSv8i16 QPR:$src)>;
5076 def : Pat<(xor (v4i32 (NEONvshrs QPR:$src, (i32 31))),
5077 (v4i32 (add QPR:$src, (NEONvshrs QPR:$src, (i32 31))))),
5078 (VABSv4i32 QPR:$src)>;
5080 def : Pat<(v2f32 (int_arm_neon_vabs (v2f32 DPR:$src))), (VABSfd DPR:$src)>;
5081 def : Pat<(v4f32 (int_arm_neon_vabs (v4f32 QPR:$src))), (VABSfq QPR:$src)>;
5083 // VQABS : Vector Saturating Absolute Value
5084 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
5085 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
5086 int_arm_neon_vqabs>;
5090 def vnegd : PatFrag<(ops node:$in),
5091 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
5092 def vnegq : PatFrag<(ops node:$in),
5093 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
5095 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
5096 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
5097 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
5098 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
5099 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
5100 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
5101 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
5102 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
5104 // VNEG : Vector Negate (integer)
5105 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
5106 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
5107 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
5108 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
5109 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
5110 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
5112 // VNEG : Vector Negate (floating-point)
5113 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
5114 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
5115 "vneg", "f32", "$Vd, $Vm", "",
5116 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
5117 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
5118 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
5119 "vneg", "f32", "$Vd, $Vm", "",
5120 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
5122 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
5123 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
5124 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
5125 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
5126 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
5127 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
5129 // VQNEG : Vector Saturating Negate
5130 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
5131 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
5132 int_arm_neon_vqneg>;
5134 // Vector Bit Counting Operations.
5136 // VCLS : Vector Count Leading Sign Bits
5137 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
5138 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
5140 // VCLZ : Vector Count Leading Zeros
5141 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
5142 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
5144 // VCNT : Vector Count One Bits
5145 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
5146 IIC_VCNTiD, "vcnt", "8",
5148 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
5149 IIC_VCNTiQ, "vcnt", "8",
5150 v16i8, v16i8, ctpop>;
5153 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
5154 (outs DPR:$Vd, DPR:$Vm), (ins DPR:$in1, DPR:$in2),
5155 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
5157 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
5158 (outs QPR:$Vd, QPR:$Vm), (ins QPR:$in1, QPR:$in2),
5159 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
5162 // Vector Move Operations.
5164 // VMOV : Vector Move (Register)
5165 def : NEONInstAlias<"vmov${p} $Vd, $Vm",
5166 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
5167 def : NEONInstAlias<"vmov${p} $Vd, $Vm",
5168 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
5170 // VMOV : Vector Move (Immediate)
5172 let isReMaterializable = 1 in {
5173 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
5174 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
5175 "vmov", "i8", "$Vd, $SIMM", "",
5176 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
5177 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
5178 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
5179 "vmov", "i8", "$Vd, $SIMM", "",
5180 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
5182 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
5183 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
5184 "vmov", "i16", "$Vd, $SIMM", "",
5185 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
5186 let Inst{9} = SIMM{9};
5189 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
5190 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
5191 "vmov", "i16", "$Vd, $SIMM", "",
5192 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
5193 let Inst{9} = SIMM{9};
5196 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
5197 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
5198 "vmov", "i32", "$Vd, $SIMM", "",
5199 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
5200 let Inst{11-8} = SIMM{11-8};
5203 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
5204 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
5205 "vmov", "i32", "$Vd, $SIMM", "",
5206 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
5207 let Inst{11-8} = SIMM{11-8};
5210 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
5211 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
5212 "vmov", "i64", "$Vd, $SIMM", "",
5213 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
5214 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
5215 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
5216 "vmov", "i64", "$Vd, $SIMM", "",
5217 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
5219 def VMOVv2f32 : N1ModImm<1, 0b000, 0b1111, 0, 0, 0, 1, (outs DPR:$Vd),
5220 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
5221 "vmov", "f32", "$Vd, $SIMM", "",
5222 [(set DPR:$Vd, (v2f32 (NEONvmovFPImm timm:$SIMM)))]>;
5223 def VMOVv4f32 : N1ModImm<1, 0b000, 0b1111, 0, 1, 0, 1, (outs QPR:$Vd),
5224 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
5225 "vmov", "f32", "$Vd, $SIMM", "",
5226 [(set QPR:$Vd, (v4f32 (NEONvmovFPImm timm:$SIMM)))]>;
5227 } // isReMaterializable
5229 // VMOV : Vector Get Lane (move scalar to ARM core register)
5231 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
5232 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
5233 IIC_VMOVSI, "vmov", "s8", "$R, $V$lane",
5234 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
5236 let Inst{21} = lane{2};
5237 let Inst{6-5} = lane{1-0};
5239 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
5240 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
5241 IIC_VMOVSI, "vmov", "s16", "$R, $V$lane",
5242 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
5244 let Inst{21} = lane{1};
5245 let Inst{6} = lane{0};
5247 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
5248 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
5249 IIC_VMOVSI, "vmov", "u8", "$R, $V$lane",
5250 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
5252 let Inst{21} = lane{2};
5253 let Inst{6-5} = lane{1-0};
5255 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
5256 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
5257 IIC_VMOVSI, "vmov", "u16", "$R, $V$lane",
5258 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
5260 let Inst{21} = lane{1};
5261 let Inst{6} = lane{0};
5263 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
5264 (outs GPR:$R), (ins DPR:$V, VectorIndex32:$lane),
5265 IIC_VMOVSI, "vmov", "32", "$R, $V$lane",
5266 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
5268 Requires<[HasNEON, HasFastVGETLNi32]> {
5269 let Inst{21} = lane{0};
5271 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
5272 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
5273 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
5274 (DSubReg_i8_reg imm:$lane))),
5275 (SubReg_i8_lane imm:$lane))>;
5276 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
5277 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
5278 (DSubReg_i16_reg imm:$lane))),
5279 (SubReg_i16_lane imm:$lane))>;
5280 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
5281 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
5282 (DSubReg_i8_reg imm:$lane))),
5283 (SubReg_i8_lane imm:$lane))>;
5284 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
5285 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
5286 (DSubReg_i16_reg imm:$lane))),
5287 (SubReg_i16_lane imm:$lane))>;
5288 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
5289 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
5290 (DSubReg_i32_reg imm:$lane))),
5291 (SubReg_i32_lane imm:$lane))>,
5292 Requires<[HasNEON, HasFastVGETLNi32]>;
5293 def : Pat<(extractelt (v2i32 DPR:$src), imm:$lane),
5295 (i32 (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane))), GPR)>,
5296 Requires<[HasNEON, HasSlowVGETLNi32]>;
5297 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
5299 (i32 (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane))), GPR)>,
5300 Requires<[HasNEON, HasSlowVGETLNi32]>;
5301 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
5302 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
5303 (SSubReg_f32_reg imm:$src2))>;
5304 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
5305 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
5306 (SSubReg_f32_reg imm:$src2))>;
5307 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
5308 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
5309 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
5310 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
5313 // VMOV : Vector Set Lane (move ARM core register to scalar)
5315 let Constraints = "$src1 = $V" in {
5316 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
5317 (ins DPR:$src1, GPR:$R, VectorIndex8:$lane),
5318 IIC_VMOVISL, "vmov", "8", "$V$lane, $R",
5319 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
5320 GPR:$R, imm:$lane))]> {
5321 let Inst{21} = lane{2};
5322 let Inst{6-5} = lane{1-0};
5324 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
5325 (ins DPR:$src1, GPR:$R, VectorIndex16:$lane),
5326 IIC_VMOVISL, "vmov", "16", "$V$lane, $R",
5327 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
5328 GPR:$R, imm:$lane))]> {
5329 let Inst{21} = lane{1};
5330 let Inst{6} = lane{0};
5332 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
5333 (ins DPR:$src1, GPR:$R, VectorIndex32:$lane),
5334 IIC_VMOVISL, "vmov", "32", "$V$lane, $R",
5335 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
5336 GPR:$R, imm:$lane))]> {
5337 let Inst{21} = lane{0};
5340 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
5341 (v16i8 (INSERT_SUBREG QPR:$src1,
5342 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
5343 (DSubReg_i8_reg imm:$lane))),
5344 GPR:$src2, (SubReg_i8_lane imm:$lane))),
5345 (DSubReg_i8_reg imm:$lane)))>;
5346 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
5347 (v8i16 (INSERT_SUBREG QPR:$src1,
5348 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
5349 (DSubReg_i16_reg imm:$lane))),
5350 GPR:$src2, (SubReg_i16_lane imm:$lane))),
5351 (DSubReg_i16_reg imm:$lane)))>;
5352 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
5353 (v4i32 (INSERT_SUBREG QPR:$src1,
5354 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
5355 (DSubReg_i32_reg imm:$lane))),
5356 GPR:$src2, (SubReg_i32_lane imm:$lane))),
5357 (DSubReg_i32_reg imm:$lane)))>;
5359 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
5360 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
5361 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
5362 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
5363 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
5364 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
5366 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
5367 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
5368 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
5369 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
5371 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
5372 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
5373 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
5374 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
5375 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
5376 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
5378 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
5379 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5380 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
5381 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5382 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
5383 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5385 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
5386 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
5387 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
5389 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
5390 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
5391 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
5393 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
5394 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
5395 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
5398 // VDUP : Vector Duplicate (from ARM core register to all elements)
5400 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
5401 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
5402 IIC_VMOVIS, "vdup", Dt, "$V, $R",
5403 [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
5404 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
5405 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
5406 IIC_VMOVIS, "vdup", Dt, "$V, $R",
5407 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
5409 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
5410 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
5411 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>,
5412 Requires<[HasNEON, HasFastVDUP32]>;
5413 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
5414 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
5415 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
5417 // NEONvdup patterns for uarchs with fast VDUP.32.
5418 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32d GPR:$R)>,
5419 Requires<[HasNEON,HasFastVDUP32]>;
5420 def : Pat<(v4f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32q GPR:$R)>;
5422 // NEONvdup patterns for uarchs with slow VDUP.32 - use VMOVDRR instead.
5423 def : Pat<(v2i32 (NEONvdup (i32 GPR:$R))), (VMOVDRR GPR:$R, GPR:$R)>,
5424 Requires<[HasNEON,HasSlowVDUP32]>;
5425 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VMOVDRR GPR:$R, GPR:$R)>,
5426 Requires<[HasNEON,HasSlowVDUP32]>;
5428 // VDUP : Vector Duplicate Lane (from scalar to all elements)
5430 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
5431 ValueType Ty, Operand IdxTy>
5432 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
5433 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm$lane",
5434 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
5436 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
5437 ValueType ResTy, ValueType OpTy, Operand IdxTy>
5438 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
5439 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm$lane",
5440 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
5441 VectorIndex32:$lane)))]>;
5443 // Inst{19-16} is partially specified depending on the element size.
5445 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8, VectorIndex8> {
5447 let Inst{19-17} = lane{2-0};
5449 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16, VectorIndex16> {
5451 let Inst{19-18} = lane{1-0};
5453 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32, VectorIndex32> {
5455 let Inst{19} = lane{0};
5457 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8, VectorIndex8> {
5459 let Inst{19-17} = lane{2-0};
5461 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16, VectorIndex16> {
5463 let Inst{19-18} = lane{1-0};
5465 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32, VectorIndex32> {
5467 let Inst{19} = lane{0};
5470 def : Pat<(v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
5471 (VDUPLN32d DPR:$Vm, imm:$lane)>;
5473 def : Pat<(v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
5474 (VDUPLN32q DPR:$Vm, imm:$lane)>;
5476 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
5477 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
5478 (DSubReg_i8_reg imm:$lane))),
5479 (SubReg_i8_lane imm:$lane)))>;
5480 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
5481 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
5482 (DSubReg_i16_reg imm:$lane))),
5483 (SubReg_i16_lane imm:$lane)))>;
5484 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
5485 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
5486 (DSubReg_i32_reg imm:$lane))),
5487 (SubReg_i32_lane imm:$lane)))>;
5488 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
5489 (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src,
5490 (DSubReg_i32_reg imm:$lane))),
5491 (SubReg_i32_lane imm:$lane)))>;
5493 def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
5494 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
5495 def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
5496 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
5498 // VMOVN : Vector Narrowing Move
5499 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
5500 "vmovn", "i", trunc>;
5501 // VQMOVN : Vector Saturating Narrowing Move
5502 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
5503 "vqmovn", "s", int_arm_neon_vqmovns>;
5504 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
5505 "vqmovn", "u", int_arm_neon_vqmovnu>;
5506 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
5507 "vqmovun", "s", int_arm_neon_vqmovnsu>;
5508 // VMOVL : Vector Lengthening Move
5509 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
5510 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
5511 def : Pat<(v8i16 (anyext (v8i8 DPR:$Vm))), (VMOVLuv8i16 DPR:$Vm)>;
5512 def : Pat<(v4i32 (anyext (v4i16 DPR:$Vm))), (VMOVLuv4i32 DPR:$Vm)>;
5513 def : Pat<(v2i64 (anyext (v2i32 DPR:$Vm))), (VMOVLuv2i64 DPR:$Vm)>;
5515 // Vector Conversions.
5517 // VCVT : Vector Convert Between Floating-Point and Integers
5518 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
5519 v2i32, v2f32, fp_to_sint>;
5520 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
5521 v2i32, v2f32, fp_to_uint>;
5522 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
5523 v2f32, v2i32, sint_to_fp>;
5524 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
5525 v2f32, v2i32, uint_to_fp>;
5527 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
5528 v4i32, v4f32, fp_to_sint>;
5529 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
5530 v4i32, v4f32, fp_to_uint>;
5531 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
5532 v4f32, v4i32, sint_to_fp>;
5533 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
5534 v4f32, v4i32, uint_to_fp>;
5537 multiclass VCVT_FPI<string op, bits<3> op10_8, SDPatternOperator IntS,
5538 SDPatternOperator IntU> {
5539 let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
5540 def SD : N2VDIntnp<0b11, op10_8, 0, NoItinerary, !strconcat("vcvt", op),
5541 "s32.f32", v2i32, v2f32, IntS>, Requires<[HasV8, HasNEON]>;
5542 def SQ : N2VQIntnp<0b11, op10_8, 0, NoItinerary, !strconcat("vcvt", op),
5543 "s32.f32", v4i32, v4f32, IntS>, Requires<[HasV8, HasNEON]>;
5544 def UD : N2VDIntnp<0b11, op10_8, 1, NoItinerary, !strconcat("vcvt", op),
5545 "u32.f32", v2i32, v2f32, IntU>, Requires<[HasV8, HasNEON]>;
5546 def UQ : N2VQIntnp<0b11, op10_8, 1, NoItinerary, !strconcat("vcvt", op),
5547 "u32.f32", v4i32, v4f32, IntU>, Requires<[HasV8, HasNEON]>;
5551 defm VCVTAN : VCVT_FPI<"a", 0b000, int_arm_neon_vcvtas, int_arm_neon_vcvtau>;
5552 defm VCVTNN : VCVT_FPI<"n", 0b001, int_arm_neon_vcvtns, int_arm_neon_vcvtnu>;
5553 defm VCVTPN : VCVT_FPI<"p", 0b010, int_arm_neon_vcvtps, int_arm_neon_vcvtpu>;
5554 defm VCVTMN : VCVT_FPI<"m", 0b011, int_arm_neon_vcvtms, int_arm_neon_vcvtmu>;
5556 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
5557 let DecoderMethod = "DecodeVCVTD" in {
5558 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
5559 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
5560 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
5561 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
5562 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
5563 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
5564 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
5565 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
5568 let DecoderMethod = "DecodeVCVTQ" in {
5569 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
5570 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
5571 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
5572 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
5573 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
5574 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
5575 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
5576 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
5579 def : NEONInstAlias<"vcvt${p}.s32.f32 $Dd, $Dm, #0",
5580 (VCVTf2sd DPR:$Dd, DPR:$Dm, pred:$p)>;
5581 def : NEONInstAlias<"vcvt${p}.u32.f32 $Dd, $Dm, #0",
5582 (VCVTf2ud DPR:$Dd, DPR:$Dm, pred:$p)>;
5583 def : NEONInstAlias<"vcvt${p}.f32.s32 $Dd, $Dm, #0",
5584 (VCVTs2fd DPR:$Dd, DPR:$Dm, pred:$p)>;
5585 def : NEONInstAlias<"vcvt${p}.f32.u32 $Dd, $Dm, #0",
5586 (VCVTu2fd DPR:$Dd, DPR:$Dm, pred:$p)>;
5588 def : NEONInstAlias<"vcvt${p}.s32.f32 $Qd, $Qm, #0",
5589 (VCVTf2sq QPR:$Qd, QPR:$Qm, pred:$p)>;
5590 def : NEONInstAlias<"vcvt${p}.u32.f32 $Qd, $Qm, #0",
5591 (VCVTf2uq QPR:$Qd, QPR:$Qm, pred:$p)>;
5592 def : NEONInstAlias<"vcvt${p}.f32.s32 $Qd, $Qm, #0",
5593 (VCVTs2fq QPR:$Qd, QPR:$Qm, pred:$p)>;
5594 def : NEONInstAlias<"vcvt${p}.f32.u32 $Qd, $Qm, #0",
5595 (VCVTu2fq QPR:$Qd, QPR:$Qm, pred:$p)>;
5598 // VCVT : Vector Convert Between Half-Precision and Single-Precision.
5599 def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
5600 IIC_VUNAQ, "vcvt", "f16.f32",
5601 v4i16, v4f32, int_arm_neon_vcvtfp2hf>,
5602 Requires<[HasNEON, HasFP16]>;
5603 def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
5604 IIC_VUNAQ, "vcvt", "f32.f16",
5605 v4f32, v4i16, int_arm_neon_vcvthf2fp>,
5606 Requires<[HasNEON, HasFP16]>;
5610 // VREV64 : Vector Reverse elements within 64-bit doublewords
5612 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5613 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
5614 (ins DPR:$Vm), IIC_VMOVD,
5615 OpcodeStr, Dt, "$Vd, $Vm", "",
5616 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
5617 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5618 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
5619 (ins QPR:$Vm), IIC_VMOVQ,
5620 OpcodeStr, Dt, "$Vd, $Vm", "",
5621 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
5623 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
5624 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
5625 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
5626 def : Pat<(v2f32 (NEONvrev64 (v2f32 DPR:$Vm))), (VREV64d32 DPR:$Vm)>;
5628 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
5629 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
5630 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
5631 def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>;
5633 // VREV32 : Vector Reverse elements within 32-bit words
5635 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5636 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
5637 (ins DPR:$Vm), IIC_VMOVD,
5638 OpcodeStr, Dt, "$Vd, $Vm", "",
5639 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
5640 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5641 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
5642 (ins QPR:$Vm), IIC_VMOVQ,
5643 OpcodeStr, Dt, "$Vd, $Vm", "",
5644 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
5646 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
5647 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
5649 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
5650 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
5652 // VREV16 : Vector Reverse elements within 16-bit halfwords
5654 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5655 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
5656 (ins DPR:$Vm), IIC_VMOVD,
5657 OpcodeStr, Dt, "$Vd, $Vm", "",
5658 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
5659 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5660 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
5661 (ins QPR:$Vm), IIC_VMOVQ,
5662 OpcodeStr, Dt, "$Vd, $Vm", "",
5663 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
5665 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
5666 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
5668 // Other Vector Shuffles.
5670 // Aligned extractions: really just dropping registers
5672 class AlignedVEXTq<ValueType DestTy, ValueType SrcTy, SDNodeXForm LaneCVT>
5673 : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))),
5674 (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>;
5676 def : AlignedVEXTq<v8i8, v16i8, DSubReg_i8_reg>;
5678 def : AlignedVEXTq<v4i16, v8i16, DSubReg_i16_reg>;
5680 def : AlignedVEXTq<v2i32, v4i32, DSubReg_i32_reg>;
5682 def : AlignedVEXTq<v1i64, v2i64, DSubReg_f64_reg>;
5684 def : AlignedVEXTq<v2f32, v4f32, DSubReg_i32_reg>;
5687 // VEXT : Vector Extract
5690 // All of these have a two-operand InstAlias.
5691 let TwoOperandAliasConstraint = "$Vn = $Vd" in {
5692 class VEXTd<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
5693 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
5694 (ins DPR:$Vn, DPR:$Vm, immTy:$index), NVExtFrm,
5695 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
5696 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
5697 (Ty DPR:$Vm), imm:$index)))]> {
5700 let Inst{10-8} = index{2-0};
5703 class VEXTq<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
5704 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
5705 (ins QPR:$Vn, QPR:$Vm, imm0_15:$index), NVExtFrm,
5706 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
5707 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
5708 (Ty QPR:$Vm), imm:$index)))]> {
5710 let Inst{11-8} = index{3-0};
5714 def VEXTd8 : VEXTd<"vext", "8", v8i8, imm0_7> {
5715 let Inst{10-8} = index{2-0};
5717 def VEXTd16 : VEXTd<"vext", "16", v4i16, imm0_3> {
5718 let Inst{10-9} = index{1-0};
5721 def VEXTd32 : VEXTd<"vext", "32", v2i32, imm0_1> {
5722 let Inst{10} = index{0};
5723 let Inst{9-8} = 0b00;
5725 def : Pat<(v2f32 (NEONvext (v2f32 DPR:$Vn),
5728 (VEXTd32 DPR:$Vn, DPR:$Vm, imm:$index)>;
5730 def VEXTq8 : VEXTq<"vext", "8", v16i8, imm0_15> {
5731 let Inst{11-8} = index{3-0};
5733 def VEXTq16 : VEXTq<"vext", "16", v8i16, imm0_7> {
5734 let Inst{11-9} = index{2-0};
5737 def VEXTq32 : VEXTq<"vext", "32", v4i32, imm0_3> {
5738 let Inst{11-10} = index{1-0};
5739 let Inst{9-8} = 0b00;
5741 def VEXTq64 : VEXTq<"vext", "64", v2i64, imm0_1> {
5742 let Inst{11} = index{0};
5743 let Inst{10-8} = 0b000;
5745 def : Pat<(v4f32 (NEONvext (v4f32 QPR:$Vn),
5748 (VEXTq32 QPR:$Vn, QPR:$Vm, imm:$index)>;
5750 // VTRN : Vector Transpose
5752 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
5753 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
5754 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
5756 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
5757 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
5758 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
5760 // VUZP : Vector Unzip (Deinterleave)
5762 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
5763 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
5764 // vuzp.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
5765 def : NEONInstAlias<"vuzp${p}.32 $Dd, $Dm",
5766 (VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p)>;
5768 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
5769 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
5770 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
5772 // VZIP : Vector Zip (Interleave)
5774 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
5775 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
5776 // vzip.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
5777 def : NEONInstAlias<"vzip${p}.32 $Dd, $Dm",
5778 (VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p)>;
5780 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
5781 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
5782 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
5784 // Vector Table Lookup and Table Extension.
5786 // VTBL : Vector Table Lookup
5787 let DecoderMethod = "DecodeTBLInstruction" in {
5789 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
5790 (ins VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
5791 "vtbl", "8", "$Vd, $Vn, $Vm", "",
5792 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 VecListOneD:$Vn, DPR:$Vm)))]>;
5793 let hasExtraSrcRegAllocReq = 1 in {
5795 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
5796 (ins VecListDPair:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB2,
5797 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5799 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
5800 (ins VecListThreeD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB3,
5801 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5803 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
5804 (ins VecListFourD:$Vn, DPR:$Vm),
5806 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5807 } // hasExtraSrcRegAllocReq = 1
5810 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
5812 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
5814 // VTBX : Vector Table Extension
5816 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
5817 (ins DPR:$orig, VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
5818 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd",
5819 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
5820 DPR:$orig, VecListOneD:$Vn, DPR:$Vm)))]>;
5821 let hasExtraSrcRegAllocReq = 1 in {
5823 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
5824 (ins DPR:$orig, VecListDPair:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
5825 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd", []>;
5827 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
5828 (ins DPR:$orig, VecListThreeD:$Vn, DPR:$Vm),
5829 NVTBLFrm, IIC_VTBX3,
5830 "vtbx", "8", "$Vd, $Vn, $Vm",
5833 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd),
5834 (ins DPR:$orig, VecListFourD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
5835 "vtbx", "8", "$Vd, $Vn, $Vm",
5837 } // hasExtraSrcRegAllocReq = 1
5840 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
5841 IIC_VTBX3, "$orig = $dst", []>;
5843 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
5844 IIC_VTBX4, "$orig = $dst", []>;
5845 } // DecoderMethod = "DecodeTBLInstruction"
5847 // VRINT : Vector Rounding
5848 multiclass VRINT_FPI<string op, bits<3> op9_7, SDPatternOperator Int> {
5849 let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
5850 def D : N2VDIntnp<0b10, 0b100, 0, NoItinerary,
5851 !strconcat("vrint", op), "f32",
5852 v2f32, v2f32, Int>, Requires<[HasV8, HasNEON]> {
5853 let Inst{9-7} = op9_7;
5855 def Q : N2VQIntnp<0b10, 0b100, 0, NoItinerary,
5856 !strconcat("vrint", op), "f32",
5857 v4f32, v4f32, Int>, Requires<[HasV8, HasNEON]> {
5858 let Inst{9-7} = op9_7;
5862 def : NEONInstAlias<!strconcat("vrint", op, ".f32.f32\t$Dd, $Dm"),
5863 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm)>;
5864 def : NEONInstAlias<!strconcat("vrint", op, ".f32.f32\t$Qd, $Qm"),
5865 (!cast<Instruction>(NAME#"Q") QPR:$Qd, QPR:$Qm)>;
5868 defm VRINTNN : VRINT_FPI<"n", 0b000, int_arm_neon_vrintn>;
5869 defm VRINTXN : VRINT_FPI<"x", 0b001, int_arm_neon_vrintx>;
5870 defm VRINTAN : VRINT_FPI<"a", 0b010, int_arm_neon_vrinta>;
5871 defm VRINTZN : VRINT_FPI<"z", 0b011, int_arm_neon_vrintz>;
5872 defm VRINTMN : VRINT_FPI<"m", 0b101, int_arm_neon_vrintm>;
5873 defm VRINTPN : VRINT_FPI<"p", 0b111, int_arm_neon_vrintp>;
5875 // Cryptography instructions
5876 let PostEncoderMethod = "NEONThumb2DataIPostEncoder",
5877 DecoderNamespace = "v8Crypto" in {
5878 class AES<string op, bit op7, bit op6, SDPatternOperator Int>
5879 : N2VQIntXnp<0b00, 0b00, 0b011, op6, op7, NoItinerary,
5880 !strconcat("aes", op), "8", v16i8, v16i8, Int>,
5881 Requires<[HasV8, HasCrypto]>;
5882 class AES2Op<string op, bit op7, bit op6, SDPatternOperator Int>
5883 : N2VQIntX2np<0b00, 0b00, 0b011, op6, op7, NoItinerary,
5884 !strconcat("aes", op), "8", v16i8, v16i8, Int>,
5885 Requires<[HasV8, HasCrypto]>;
5886 class N2SHA<string op, bits<2> op17_16, bits<3> op10_8, bit op7, bit op6,
5887 SDPatternOperator Int>
5888 : N2VQIntXnp<0b10, op17_16, op10_8, op6, op7, NoItinerary,
5889 !strconcat("sha", op), "32", v4i32, v4i32, Int>,
5890 Requires<[HasV8, HasCrypto]>;
5891 class N2SHA2Op<string op, bits<2> op17_16, bits<3> op10_8, bit op7, bit op6,
5892 SDPatternOperator Int>
5893 : N2VQIntX2np<0b10, op17_16, op10_8, op6, op7, NoItinerary,
5894 !strconcat("sha", op), "32", v4i32, v4i32, Int>,
5895 Requires<[HasV8, HasCrypto]>;
5896 class N3SHA3Op<string op, bits<5> op27_23, bits<2> op21_20, SDPatternOperator Int>
5897 : N3VQInt3np<op27_23, op21_20, 0b1100, 1, 0, N3RegFrm, NoItinerary,
5898 !strconcat("sha", op), "32", v4i32, v4i32, Int, 0>,
5899 Requires<[HasV8, HasCrypto]>;
5902 def AESD : AES2Op<"d", 0, 1, int_arm_neon_aesd>;
5903 def AESE : AES2Op<"e", 0, 0, int_arm_neon_aese>;
5904 def AESIMC : AES<"imc", 1, 1, int_arm_neon_aesimc>;
5905 def AESMC : AES<"mc", 1, 0, int_arm_neon_aesmc>;
5907 def SHA1H : N2SHA<"1h", 0b01, 0b010, 1, 1, int_arm_neon_sha1h>;
5908 def SHA1SU1 : N2SHA2Op<"1su1", 0b10, 0b011, 1, 0, int_arm_neon_sha1su1>;
5909 def SHA256SU0 : N2SHA2Op<"256su0", 0b10, 0b011, 1, 1, int_arm_neon_sha256su0>;
5910 def SHA1C : N3SHA3Op<"1c", 0b00100, 0b00, int_arm_neon_sha1c>;
5911 def SHA1M : N3SHA3Op<"1m", 0b00100, 0b10, int_arm_neon_sha1m>;
5912 def SHA1P : N3SHA3Op<"1p", 0b00100, 0b01, int_arm_neon_sha1p>;
5913 def SHA1SU0 : N3SHA3Op<"1su0", 0b00100, 0b11, int_arm_neon_sha1su0>;
5914 def SHA256H : N3SHA3Op<"256h", 0b00110, 0b00, int_arm_neon_sha256h>;
5915 def SHA256H2 : N3SHA3Op<"256h2", 0b00110, 0b01, int_arm_neon_sha256h2>;
5916 def SHA256SU1 : N3SHA3Op<"256su1", 0b00110, 0b10, int_arm_neon_sha256su1>;
5918 //===----------------------------------------------------------------------===//
5919 // NEON instructions for single-precision FP math
5920 //===----------------------------------------------------------------------===//
5922 class N2VSPat<SDNode OpNode, NeonI Inst>
5923 : NEONFPPat<(f32 (OpNode SPR:$a)),
5925 (v2f32 (COPY_TO_REGCLASS (Inst
5927 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5928 SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>;
5930 class N3VSPat<SDNode OpNode, NeonI Inst>
5931 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
5933 (v2f32 (COPY_TO_REGCLASS (Inst
5935 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5938 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5939 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
5941 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
5942 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
5944 (v2f32 (COPY_TO_REGCLASS (Inst
5946 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5949 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5952 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5953 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
5955 def : N3VSPat<fadd, VADDfd>;
5956 def : N3VSPat<fsub, VSUBfd>;
5957 def : N3VSPat<fmul, VMULfd>;
5958 def : N3VSMulOpPat<fmul, fadd, VMLAfd>,
5959 Requires<[HasNEON, UseNEONForFP, UseFPVMLx, DontUseFusedMAC]>;
5960 def : N3VSMulOpPat<fmul, fsub, VMLSfd>,
5961 Requires<[HasNEON, UseNEONForFP, UseFPVMLx, DontUseFusedMAC]>;
5962 def : N3VSMulOpPat<fmul, fadd, VFMAfd>,
5963 Requires<[HasVFP4, UseNEONForFP, UseFusedMAC]>;
5964 def : N3VSMulOpPat<fmul, fsub, VFMSfd>,
5965 Requires<[HasVFP4, UseNEONForFP, UseFusedMAC]>;
5966 def : N2VSPat<fabs, VABSfd>;
5967 def : N2VSPat<fneg, VNEGfd>;
5968 def : N3VSPat<NEONfmax, VMAXfd>;
5969 def : N3VSPat<NEONfmin, VMINfd>;
5970 def : N2VSPat<arm_ftosi, VCVTf2sd>;
5971 def : N2VSPat<arm_ftoui, VCVTf2ud>;
5972 def : N2VSPat<arm_sitof, VCVTs2fd>;
5973 def : N2VSPat<arm_uitof, VCVTu2fd>;
5975 // Prefer VMOVDRR for i32 -> f32 bitcasts, it can write all DPR registers.
5976 def : Pat<(f32 (bitconvert GPR:$a)),
5977 (EXTRACT_SUBREG (VMOVDRR GPR:$a, GPR:$a), ssub_0)>,
5978 Requires<[HasNEON, DontUseVMOVSR]>;
5980 //===----------------------------------------------------------------------===//
5981 // Non-Instruction Patterns
5982 //===----------------------------------------------------------------------===//
5985 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
5986 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
5987 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
5988 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
5989 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
5990 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
5991 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
5992 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
5993 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
5994 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
5995 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
5996 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
5997 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
5998 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
5999 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
6000 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
6001 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
6002 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
6003 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
6004 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
6005 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
6006 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
6007 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
6008 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
6009 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
6010 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
6011 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
6012 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
6013 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
6014 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
6016 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
6017 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
6018 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
6019 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
6020 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
6021 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
6022 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
6023 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
6024 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
6025 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
6026 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
6027 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
6028 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
6029 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
6030 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
6031 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
6032 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
6033 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
6034 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
6035 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
6036 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
6037 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
6038 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
6039 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
6040 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
6041 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
6042 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
6043 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
6044 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
6045 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
6047 // Fold extracting an element out of a v2i32 into a vfp register.
6048 def : Pat<(f32 (bitconvert (i32 (extractelt (v2i32 DPR:$src), imm:$lane)))),
6049 (f32 (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))>;
6051 // Vector lengthening move with load, matching extending loads.
6053 // extload, zextload and sextload for a standard lengthening load. Example:
6054 // Lengthen_Single<"8", "i16", "8"> =
6055 // Pat<(v8i16 (extloadvi8 addrmode6:$addr))
6056 // (VMOVLuv8i16 (VLD1d8 addrmode6:$addr,
6057 // (f64 (IMPLICIT_DEF)), (i32 0)))>;
6058 multiclass Lengthen_Single<string DestLanes, string DestTy, string SrcTy> {
6059 let AddedComplexity = 10 in {
6060 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6061 (!cast<PatFrag>("extloadvi" # SrcTy) addrmode6:$addr)),
6062 (!cast<Instruction>("VMOVLuv" # DestLanes # DestTy)
6063 (!cast<Instruction>("VLD1d" # SrcTy) addrmode6:$addr))>;
6065 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6066 (!cast<PatFrag>("zextloadvi" # SrcTy) addrmode6:$addr)),
6067 (!cast<Instruction>("VMOVLuv" # DestLanes # DestTy)
6068 (!cast<Instruction>("VLD1d" # SrcTy) addrmode6:$addr))>;
6070 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6071 (!cast<PatFrag>("sextloadvi" # SrcTy) addrmode6:$addr)),
6072 (!cast<Instruction>("VMOVLsv" # DestLanes # DestTy)
6073 (!cast<Instruction>("VLD1d" # SrcTy) addrmode6:$addr))>;
6077 // extload, zextload and sextload for a lengthening load which only uses
6078 // half the lanes available. Example:
6079 // Lengthen_HalfSingle<"4", "i16", "8", "i16", "i8"> =
6080 // Pat<(v4i16 (extloadvi8 addrmode6oneL32:$addr)),
6081 // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr,
6082 // (f64 (IMPLICIT_DEF)), (i32 0))),
6084 multiclass Lengthen_HalfSingle<string DestLanes, string DestTy, string SrcTy,
6085 string InsnLanes, string InsnTy> {
6086 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6087 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)),
6088 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
6089 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6091 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6092 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)),
6093 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
6094 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6096 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6097 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)),
6098 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # InsnLanes # InsnTy)
6099 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6103 // extload, zextload and sextload for a lengthening load followed by another
6104 // lengthening load, to quadruple the initial length.
6106 // Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32"> =
6107 // Pat<(v4i32 (extloadvi8 addrmode6oneL32:$addr))
6108 // (EXTRACT_SUBREG (VMOVLuv4i32
6109 // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr,
6110 // (f64 (IMPLICIT_DEF)),
6114 multiclass Lengthen_Double<string DestLanes, string DestTy, string SrcTy,
6115 string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
6117 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6118 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)),
6119 (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6120 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6121 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6123 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6124 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)),
6125 (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6126 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6127 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6129 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6130 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)),
6131 (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
6132 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
6133 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6137 // extload, zextload and sextload for a lengthening load followed by another
6138 // lengthening load, to quadruple the initial length, but which ends up only
6139 // requiring half the available lanes (a 64-bit outcome instead of a 128-bit).
6141 // Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32"> =
6142 // Pat<(v2i32 (extloadvi8 addrmode6:$addr))
6143 // (EXTRACT_SUBREG (VMOVLuv4i32
6144 // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd16 addrmode6:$addr,
6145 // (f64 (IMPLICIT_DEF)), (i32 0))),
6148 multiclass Lengthen_HalfDouble<string DestLanes, string DestTy, string SrcTy,
6149 string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
6151 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6152 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6:$addr)),
6153 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6154 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6155 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6158 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6159 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6:$addr)),
6160 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6161 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6162 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6165 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6166 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6:$addr)),
6167 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
6168 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
6169 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6174 defm : Lengthen_Single<"8", "i16", "8">; // v8i8 -> v8i16
6175 defm : Lengthen_Single<"4", "i32", "16">; // v4i16 -> v4i32
6176 defm : Lengthen_Single<"2", "i64", "32">; // v2i32 -> v2i64
6178 defm : Lengthen_HalfSingle<"4", "i16", "i8", "8", "i16">; // v4i8 -> v4i16
6179 defm : Lengthen_HalfSingle<"2", "i32", "i16", "4", "i32">; // v2i16 -> v2i32
6181 // Double lengthening - v4i8 -> v4i16 -> v4i32
6182 defm : Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32">;
6183 // v2i8 -> v2i16 -> v2i32
6184 defm : Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32">;
6185 // v2i16 -> v2i32 -> v2i64
6186 defm : Lengthen_Double<"2", "i64", "i16", "4", "i32", "2", "i64">;
6188 // Triple lengthening - v2i8 -> v2i16 -> v2i32 -> v2i64
6189 def : Pat<(v2i64 (extloadvi8 addrmode6:$addr)),
6190 (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
6191 (VLD1LNd16 addrmode6:$addr,
6192 (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
6193 def : Pat<(v2i64 (zextloadvi8 addrmode6:$addr)),
6194 (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
6195 (VLD1LNd16 addrmode6:$addr,
6196 (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
6197 def : Pat<(v2i64 (sextloadvi8 addrmode6:$addr)),
6198 (VMOVLsv2i64 (EXTRACT_SUBREG (VMOVLsv4i32 (EXTRACT_SUBREG (VMOVLsv8i16
6199 (VLD1LNd16 addrmode6:$addr,
6200 (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
6202 //===----------------------------------------------------------------------===//
6203 // Assembler aliases
6206 def : VFP2InstAlias<"fmdhr${p} $Dd, $Rn",
6207 (VSETLNi32 DPR:$Dd, GPR:$Rn, 1, pred:$p)>;
6208 def : VFP2InstAlias<"fmdlr${p} $Dd, $Rn",
6209 (VSETLNi32 DPR:$Dd, GPR:$Rn, 0, pred:$p)>;
6211 // VAND/VBIC/VEOR/VORR accept but do not require a type suffix.
6212 defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
6213 (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6214 defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
6215 (VANDq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6216 defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
6217 (VBICd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6218 defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
6219 (VBICq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6220 defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
6221 (VEORd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6222 defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
6223 (VEORq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6224 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
6225 (VORRd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6226 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
6227 (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6228 // ... two-operand aliases
6229 defm : NEONDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",
6230 (VANDd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6231 defm : NEONDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",
6232 (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6233 defm : NEONDTAnyInstAlias<"veor${p}", "$Vdn, $Vm",
6234 (VEORd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6235 defm : NEONDTAnyInstAlias<"veor${p}", "$Vdn, $Vm",
6236 (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6237 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
6238 (VORRd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6239 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
6240 (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6242 // VLD1 single-lane pseudo-instructions. These need special handling for
6243 // the lane index that an InstAlias can't handle, so we use these instead.
6244 def VLD1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr",
6245 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6246 def VLD1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr",
6247 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6248 def VLD1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr",
6249 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6251 def VLD1LNdWB_fixed_Asm_8 :
6252 NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr!",
6253 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6254 def VLD1LNdWB_fixed_Asm_16 :
6255 NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr!",
6256 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6257 def VLD1LNdWB_fixed_Asm_32 :
6258 NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr!",
6259 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6260 def VLD1LNdWB_register_Asm_8 :
6261 NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr, $Rm",
6262 (ins VecListOneDByteIndexed:$list, addrmode6:$addr,
6263 rGPR:$Rm, pred:$p)>;
6264 def VLD1LNdWB_register_Asm_16 :
6265 NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr, $Rm",
6266 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr,
6267 rGPR:$Rm, pred:$p)>;
6268 def VLD1LNdWB_register_Asm_32 :
6269 NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr, $Rm",
6270 (ins VecListOneDWordIndexed:$list, addrmode6:$addr,
6271 rGPR:$Rm, pred:$p)>;
6274 // VST1 single-lane pseudo-instructions. These need special handling for
6275 // the lane index that an InstAlias can't handle, so we use these instead.
6276 def VST1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr",
6277 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6278 def VST1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr",
6279 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6280 def VST1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr",
6281 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6283 def VST1LNdWB_fixed_Asm_8 :
6284 NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr!",
6285 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6286 def VST1LNdWB_fixed_Asm_16 :
6287 NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr!",
6288 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6289 def VST1LNdWB_fixed_Asm_32 :
6290 NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr!",
6291 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6292 def VST1LNdWB_register_Asm_8 :
6293 NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr, $Rm",
6294 (ins VecListOneDByteIndexed:$list, addrmode6:$addr,
6295 rGPR:$Rm, pred:$p)>;
6296 def VST1LNdWB_register_Asm_16 :
6297 NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr, $Rm",
6298 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr,
6299 rGPR:$Rm, pred:$p)>;
6300 def VST1LNdWB_register_Asm_32 :
6301 NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr, $Rm",
6302 (ins VecListOneDWordIndexed:$list, addrmode6:$addr,
6303 rGPR:$Rm, pred:$p)>;
6305 // VLD2 single-lane pseudo-instructions. These need special handling for
6306 // the lane index that an InstAlias can't handle, so we use these instead.
6307 def VLD2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr",
6308 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6309 def VLD2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr",
6310 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6311 def VLD2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr",
6312 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6313 def VLD2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr",
6314 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6315 def VLD2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr",
6316 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6318 def VLD2LNdWB_fixed_Asm_8 :
6319 NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr!",
6320 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6321 def VLD2LNdWB_fixed_Asm_16 :
6322 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!",
6323 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6324 def VLD2LNdWB_fixed_Asm_32 :
6325 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!",
6326 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6327 def VLD2LNqWB_fixed_Asm_16 :
6328 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!",
6329 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6330 def VLD2LNqWB_fixed_Asm_32 :
6331 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!",
6332 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6333 def VLD2LNdWB_register_Asm_8 :
6334 NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr, $Rm",
6335 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr,
6336 rGPR:$Rm, pred:$p)>;
6337 def VLD2LNdWB_register_Asm_16 :
6338 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm",
6339 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr,
6340 rGPR:$Rm, pred:$p)>;
6341 def VLD2LNdWB_register_Asm_32 :
6342 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm",
6343 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr,
6344 rGPR:$Rm, pred:$p)>;
6345 def VLD2LNqWB_register_Asm_16 :
6346 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm",
6347 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr,
6348 rGPR:$Rm, pred:$p)>;
6349 def VLD2LNqWB_register_Asm_32 :
6350 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm",
6351 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr,
6352 rGPR:$Rm, pred:$p)>;
6355 // VST2 single-lane pseudo-instructions. These need special handling for
6356 // the lane index that an InstAlias can't handle, so we use these instead.
6357 def VST2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr",
6358 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6359 def VST2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr",
6360 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6361 def VST2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr",
6362 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6363 def VST2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr",
6364 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6365 def VST2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr",
6366 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6368 def VST2LNdWB_fixed_Asm_8 :
6369 NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr!",
6370 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6371 def VST2LNdWB_fixed_Asm_16 :
6372 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!",
6373 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6374 def VST2LNdWB_fixed_Asm_32 :
6375 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!",
6376 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6377 def VST2LNqWB_fixed_Asm_16 :
6378 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!",
6379 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6380 def VST2LNqWB_fixed_Asm_32 :
6381 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!",
6382 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6383 def VST2LNdWB_register_Asm_8 :
6384 NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr, $Rm",
6385 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr,
6386 rGPR:$Rm, pred:$p)>;
6387 def VST2LNdWB_register_Asm_16 :
6388 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm",
6389 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr,
6390 rGPR:$Rm, pred:$p)>;
6391 def VST2LNdWB_register_Asm_32 :
6392 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm",
6393 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr,
6394 rGPR:$Rm, pred:$p)>;
6395 def VST2LNqWB_register_Asm_16 :
6396 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm",
6397 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr,
6398 rGPR:$Rm, pred:$p)>;
6399 def VST2LNqWB_register_Asm_32 :
6400 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm",
6401 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr,
6402 rGPR:$Rm, pred:$p)>;
6404 // VLD3 all-lanes pseudo-instructions. These need special handling for
6405 // the lane index that an InstAlias can't handle, so we use these instead.
6406 def VLD3DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6407 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6408 def VLD3DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6409 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6410 def VLD3DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6411 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6412 def VLD3DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6413 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6414 def VLD3DUPqAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6415 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6416 def VLD3DUPqAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6417 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6419 def VLD3DUPdWB_fixed_Asm_8 :
6420 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6421 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6422 def VLD3DUPdWB_fixed_Asm_16 :
6423 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6424 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6425 def VLD3DUPdWB_fixed_Asm_32 :
6426 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6427 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6428 def VLD3DUPqWB_fixed_Asm_8 :
6429 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6430 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6431 def VLD3DUPqWB_fixed_Asm_16 :
6432 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6433 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6434 def VLD3DUPqWB_fixed_Asm_32 :
6435 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6436 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6437 def VLD3DUPdWB_register_Asm_8 :
6438 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6439 (ins VecListThreeDAllLanes:$list, addrmode6:$addr,
6440 rGPR:$Rm, pred:$p)>;
6441 def VLD3DUPdWB_register_Asm_16 :
6442 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6443 (ins VecListThreeDAllLanes:$list, addrmode6:$addr,
6444 rGPR:$Rm, pred:$p)>;
6445 def VLD3DUPdWB_register_Asm_32 :
6446 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6447 (ins VecListThreeDAllLanes:$list, addrmode6:$addr,
6448 rGPR:$Rm, pred:$p)>;
6449 def VLD3DUPqWB_register_Asm_8 :
6450 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6451 (ins VecListThreeQAllLanes:$list, addrmode6:$addr,
6452 rGPR:$Rm, pred:$p)>;
6453 def VLD3DUPqWB_register_Asm_16 :
6454 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6455 (ins VecListThreeQAllLanes:$list, addrmode6:$addr,
6456 rGPR:$Rm, pred:$p)>;
6457 def VLD3DUPqWB_register_Asm_32 :
6458 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6459 (ins VecListThreeQAllLanes:$list, addrmode6:$addr,
6460 rGPR:$Rm, pred:$p)>;
6463 // VLD3 single-lane pseudo-instructions. These need special handling for
6464 // the lane index that an InstAlias can't handle, so we use these instead.
6465 def VLD3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6466 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6467 def VLD3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6468 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6469 def VLD3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6470 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6471 def VLD3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6472 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6473 def VLD3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6474 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6476 def VLD3LNdWB_fixed_Asm_8 :
6477 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6478 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6479 def VLD3LNdWB_fixed_Asm_16 :
6480 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6481 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6482 def VLD3LNdWB_fixed_Asm_32 :
6483 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6484 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6485 def VLD3LNqWB_fixed_Asm_16 :
6486 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6487 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6488 def VLD3LNqWB_fixed_Asm_32 :
6489 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6490 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6491 def VLD3LNdWB_register_Asm_8 :
6492 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6493 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr,
6494 rGPR:$Rm, pred:$p)>;
6495 def VLD3LNdWB_register_Asm_16 :
6496 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6497 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr,
6498 rGPR:$Rm, pred:$p)>;
6499 def VLD3LNdWB_register_Asm_32 :
6500 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6501 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr,
6502 rGPR:$Rm, pred:$p)>;
6503 def VLD3LNqWB_register_Asm_16 :
6504 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6505 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr,
6506 rGPR:$Rm, pred:$p)>;
6507 def VLD3LNqWB_register_Asm_32 :
6508 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6509 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr,
6510 rGPR:$Rm, pred:$p)>;
6512 // VLD3 multiple structure pseudo-instructions. These need special handling for
6513 // the vector operands that the normal instructions don't yet model.
6514 // FIXME: Remove these when the register classes and instructions are updated.
6515 def VLD3dAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6516 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6517 def VLD3dAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6518 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6519 def VLD3dAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6520 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6521 def VLD3qAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6522 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6523 def VLD3qAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6524 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6525 def VLD3qAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6526 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6528 def VLD3dWB_fixed_Asm_8 :
6529 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6530 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6531 def VLD3dWB_fixed_Asm_16 :
6532 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6533 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6534 def VLD3dWB_fixed_Asm_32 :
6535 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6536 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6537 def VLD3qWB_fixed_Asm_8 :
6538 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6539 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6540 def VLD3qWB_fixed_Asm_16 :
6541 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6542 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6543 def VLD3qWB_fixed_Asm_32 :
6544 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6545 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6546 def VLD3dWB_register_Asm_8 :
6547 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6548 (ins VecListThreeD:$list, addrmode6:$addr,
6549 rGPR:$Rm, pred:$p)>;
6550 def VLD3dWB_register_Asm_16 :
6551 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6552 (ins VecListThreeD:$list, addrmode6:$addr,
6553 rGPR:$Rm, pred:$p)>;
6554 def VLD3dWB_register_Asm_32 :
6555 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6556 (ins VecListThreeD:$list, addrmode6:$addr,
6557 rGPR:$Rm, pred:$p)>;
6558 def VLD3qWB_register_Asm_8 :
6559 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6560 (ins VecListThreeQ:$list, addrmode6:$addr,
6561 rGPR:$Rm, pred:$p)>;
6562 def VLD3qWB_register_Asm_16 :
6563 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6564 (ins VecListThreeQ:$list, addrmode6:$addr,
6565 rGPR:$Rm, pred:$p)>;
6566 def VLD3qWB_register_Asm_32 :
6567 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6568 (ins VecListThreeQ:$list, addrmode6:$addr,
6569 rGPR:$Rm, pred:$p)>;
6571 // VST3 single-lane pseudo-instructions. These need special handling for
6572 // the lane index that an InstAlias can't handle, so we use these instead.
6573 def VST3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6574 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6575 def VST3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6576 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6577 def VST3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6578 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6579 def VST3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6580 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6581 def VST3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6582 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6584 def VST3LNdWB_fixed_Asm_8 :
6585 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6586 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6587 def VST3LNdWB_fixed_Asm_16 :
6588 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6589 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6590 def VST3LNdWB_fixed_Asm_32 :
6591 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6592 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6593 def VST3LNqWB_fixed_Asm_16 :
6594 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6595 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6596 def VST3LNqWB_fixed_Asm_32 :
6597 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6598 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6599 def VST3LNdWB_register_Asm_8 :
6600 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6601 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr,
6602 rGPR:$Rm, pred:$p)>;
6603 def VST3LNdWB_register_Asm_16 :
6604 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6605 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr,
6606 rGPR:$Rm, pred:$p)>;
6607 def VST3LNdWB_register_Asm_32 :
6608 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6609 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr,
6610 rGPR:$Rm, pred:$p)>;
6611 def VST3LNqWB_register_Asm_16 :
6612 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6613 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr,
6614 rGPR:$Rm, pred:$p)>;
6615 def VST3LNqWB_register_Asm_32 :
6616 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6617 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr,
6618 rGPR:$Rm, pred:$p)>;
6621 // VST3 multiple structure pseudo-instructions. These need special handling for
6622 // the vector operands that the normal instructions don't yet model.
6623 // FIXME: Remove these when the register classes and instructions are updated.
6624 def VST3dAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6625 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6626 def VST3dAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6627 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6628 def VST3dAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6629 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6630 def VST3qAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6631 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6632 def VST3qAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6633 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6634 def VST3qAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6635 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6637 def VST3dWB_fixed_Asm_8 :
6638 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6639 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6640 def VST3dWB_fixed_Asm_16 :
6641 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6642 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6643 def VST3dWB_fixed_Asm_32 :
6644 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6645 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6646 def VST3qWB_fixed_Asm_8 :
6647 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6648 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6649 def VST3qWB_fixed_Asm_16 :
6650 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6651 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6652 def VST3qWB_fixed_Asm_32 :
6653 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6654 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6655 def VST3dWB_register_Asm_8 :
6656 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6657 (ins VecListThreeD:$list, addrmode6:$addr,
6658 rGPR:$Rm, pred:$p)>;
6659 def VST3dWB_register_Asm_16 :
6660 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6661 (ins VecListThreeD:$list, addrmode6:$addr,
6662 rGPR:$Rm, pred:$p)>;
6663 def VST3dWB_register_Asm_32 :
6664 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6665 (ins VecListThreeD:$list, addrmode6:$addr,
6666 rGPR:$Rm, pred:$p)>;
6667 def VST3qWB_register_Asm_8 :
6668 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6669 (ins VecListThreeQ:$list, addrmode6:$addr,
6670 rGPR:$Rm, pred:$p)>;
6671 def VST3qWB_register_Asm_16 :
6672 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6673 (ins VecListThreeQ:$list, addrmode6:$addr,
6674 rGPR:$Rm, pred:$p)>;
6675 def VST3qWB_register_Asm_32 :
6676 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6677 (ins VecListThreeQ:$list, addrmode6:$addr,
6678 rGPR:$Rm, pred:$p)>;
6680 // VLD4 all-lanes pseudo-instructions. These need special handling for
6681 // the lane index that an InstAlias can't handle, so we use these instead.
6682 def VLD4DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6683 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6684 def VLD4DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6685 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6686 def VLD4DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6687 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6688 def VLD4DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6689 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6690 def VLD4DUPqAsm_16: NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6691 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6692 def VLD4DUPqAsm_32: NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6693 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6695 def VLD4DUPdWB_fixed_Asm_8 :
6696 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6697 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6698 def VLD4DUPdWB_fixed_Asm_16 :
6699 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6700 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6701 def VLD4DUPdWB_fixed_Asm_32 :
6702 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6703 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6704 def VLD4DUPqWB_fixed_Asm_8 :
6705 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6706 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6707 def VLD4DUPqWB_fixed_Asm_16 :
6708 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6709 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6710 def VLD4DUPqWB_fixed_Asm_32 :
6711 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6712 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6713 def VLD4DUPdWB_register_Asm_8 :
6714 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6715 (ins VecListFourDAllLanes:$list, addrmode6:$addr,
6716 rGPR:$Rm, pred:$p)>;
6717 def VLD4DUPdWB_register_Asm_16 :
6718 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6719 (ins VecListFourDAllLanes:$list, addrmode6:$addr,
6720 rGPR:$Rm, pred:$p)>;
6721 def VLD4DUPdWB_register_Asm_32 :
6722 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6723 (ins VecListFourDAllLanes:$list, addrmode6:$addr,
6724 rGPR:$Rm, pred:$p)>;
6725 def VLD4DUPqWB_register_Asm_8 :
6726 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6727 (ins VecListFourQAllLanes:$list, addrmode6:$addr,
6728 rGPR:$Rm, pred:$p)>;
6729 def VLD4DUPqWB_register_Asm_16 :
6730 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6731 (ins VecListFourQAllLanes:$list, addrmode6:$addr,
6732 rGPR:$Rm, pred:$p)>;
6733 def VLD4DUPqWB_register_Asm_32 :
6734 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6735 (ins VecListFourQAllLanes:$list, addrmode6:$addr,
6736 rGPR:$Rm, pred:$p)>;
6739 // VLD4 single-lane pseudo-instructions. These need special handling for
6740 // the lane index that an InstAlias can't handle, so we use these instead.
6741 def VLD4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6742 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6743 def VLD4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6744 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6745 def VLD4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6746 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6747 def VLD4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6748 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6749 def VLD4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6750 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6752 def VLD4LNdWB_fixed_Asm_8 :
6753 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6754 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6755 def VLD4LNdWB_fixed_Asm_16 :
6756 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6757 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6758 def VLD4LNdWB_fixed_Asm_32 :
6759 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6760 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6761 def VLD4LNqWB_fixed_Asm_16 :
6762 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6763 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6764 def VLD4LNqWB_fixed_Asm_32 :
6765 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6766 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6767 def VLD4LNdWB_register_Asm_8 :
6768 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6769 (ins VecListFourDByteIndexed:$list, addrmode6:$addr,
6770 rGPR:$Rm, pred:$p)>;
6771 def VLD4LNdWB_register_Asm_16 :
6772 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6773 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr,
6774 rGPR:$Rm, pred:$p)>;
6775 def VLD4LNdWB_register_Asm_32 :
6776 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6777 (ins VecListFourDWordIndexed:$list, addrmode6:$addr,
6778 rGPR:$Rm, pred:$p)>;
6779 def VLD4LNqWB_register_Asm_16 :
6780 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6781 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr,
6782 rGPR:$Rm, pred:$p)>;
6783 def VLD4LNqWB_register_Asm_32 :
6784 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6785 (ins VecListFourQWordIndexed:$list, addrmode6:$addr,
6786 rGPR:$Rm, pred:$p)>;
6790 // VLD4 multiple structure pseudo-instructions. These need special handling for
6791 // the vector operands that the normal instructions don't yet model.
6792 // FIXME: Remove these when the register classes and instructions are updated.
6793 def VLD4dAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6794 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6795 def VLD4dAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6796 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6797 def VLD4dAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6798 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6799 def VLD4qAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6800 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6801 def VLD4qAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6802 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6803 def VLD4qAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6804 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6806 def VLD4dWB_fixed_Asm_8 :
6807 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6808 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6809 def VLD4dWB_fixed_Asm_16 :
6810 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6811 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6812 def VLD4dWB_fixed_Asm_32 :
6813 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6814 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6815 def VLD4qWB_fixed_Asm_8 :
6816 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6817 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6818 def VLD4qWB_fixed_Asm_16 :
6819 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6820 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6821 def VLD4qWB_fixed_Asm_32 :
6822 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6823 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6824 def VLD4dWB_register_Asm_8 :
6825 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6826 (ins VecListFourD:$list, addrmode6:$addr,
6827 rGPR:$Rm, pred:$p)>;
6828 def VLD4dWB_register_Asm_16 :
6829 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6830 (ins VecListFourD:$list, addrmode6:$addr,
6831 rGPR:$Rm, pred:$p)>;
6832 def VLD4dWB_register_Asm_32 :
6833 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6834 (ins VecListFourD:$list, addrmode6:$addr,
6835 rGPR:$Rm, pred:$p)>;
6836 def VLD4qWB_register_Asm_8 :
6837 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6838 (ins VecListFourQ:$list, addrmode6:$addr,
6839 rGPR:$Rm, pred:$p)>;
6840 def VLD4qWB_register_Asm_16 :
6841 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6842 (ins VecListFourQ:$list, addrmode6:$addr,
6843 rGPR:$Rm, pred:$p)>;
6844 def VLD4qWB_register_Asm_32 :
6845 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6846 (ins VecListFourQ:$list, addrmode6:$addr,
6847 rGPR:$Rm, pred:$p)>;
6849 // VST4 single-lane pseudo-instructions. These need special handling for
6850 // the lane index that an InstAlias can't handle, so we use these instead.
6851 def VST4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
6852 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6853 def VST4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
6854 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6855 def VST4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
6856 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6857 def VST4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
6858 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6859 def VST4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
6860 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6862 def VST4LNdWB_fixed_Asm_8 :
6863 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
6864 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6865 def VST4LNdWB_fixed_Asm_16 :
6866 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
6867 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6868 def VST4LNdWB_fixed_Asm_32 :
6869 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
6870 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6871 def VST4LNqWB_fixed_Asm_16 :
6872 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
6873 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6874 def VST4LNqWB_fixed_Asm_32 :
6875 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
6876 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6877 def VST4LNdWB_register_Asm_8 :
6878 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
6879 (ins VecListFourDByteIndexed:$list, addrmode6:$addr,
6880 rGPR:$Rm, pred:$p)>;
6881 def VST4LNdWB_register_Asm_16 :
6882 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
6883 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr,
6884 rGPR:$Rm, pred:$p)>;
6885 def VST4LNdWB_register_Asm_32 :
6886 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
6887 (ins VecListFourDWordIndexed:$list, addrmode6:$addr,
6888 rGPR:$Rm, pred:$p)>;
6889 def VST4LNqWB_register_Asm_16 :
6890 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
6891 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr,
6892 rGPR:$Rm, pred:$p)>;
6893 def VST4LNqWB_register_Asm_32 :
6894 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
6895 (ins VecListFourQWordIndexed:$list, addrmode6:$addr,
6896 rGPR:$Rm, pred:$p)>;
6899 // VST4 multiple structure pseudo-instructions. These need special handling for
6900 // the vector operands that the normal instructions don't yet model.
6901 // FIXME: Remove these when the register classes and instructions are updated.
6902 def VST4dAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
6903 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6904 def VST4dAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
6905 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6906 def VST4dAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
6907 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6908 def VST4qAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
6909 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6910 def VST4qAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
6911 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6912 def VST4qAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
6913 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6915 def VST4dWB_fixed_Asm_8 :
6916 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
6917 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6918 def VST4dWB_fixed_Asm_16 :
6919 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
6920 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6921 def VST4dWB_fixed_Asm_32 :
6922 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
6923 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6924 def VST4qWB_fixed_Asm_8 :
6925 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
6926 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6927 def VST4qWB_fixed_Asm_16 :
6928 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
6929 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6930 def VST4qWB_fixed_Asm_32 :
6931 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
6932 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6933 def VST4dWB_register_Asm_8 :
6934 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
6935 (ins VecListFourD:$list, addrmode6:$addr,
6936 rGPR:$Rm, pred:$p)>;
6937 def VST4dWB_register_Asm_16 :
6938 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
6939 (ins VecListFourD:$list, addrmode6:$addr,
6940 rGPR:$Rm, pred:$p)>;
6941 def VST4dWB_register_Asm_32 :
6942 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
6943 (ins VecListFourD:$list, addrmode6:$addr,
6944 rGPR:$Rm, pred:$p)>;
6945 def VST4qWB_register_Asm_8 :
6946 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
6947 (ins VecListFourQ:$list, addrmode6:$addr,
6948 rGPR:$Rm, pred:$p)>;
6949 def VST4qWB_register_Asm_16 :
6950 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
6951 (ins VecListFourQ:$list, addrmode6:$addr,
6952 rGPR:$Rm, pred:$p)>;
6953 def VST4qWB_register_Asm_32 :
6954 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
6955 (ins VecListFourQ:$list, addrmode6:$addr,
6956 rGPR:$Rm, pred:$p)>;
6958 // VMOV/VMVN takes an optional datatype suffix
6959 defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
6960 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
6961 defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
6962 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
6964 defm : NEONDTAnyInstAlias<"vmvn${p}", "$Vd, $Vm",
6965 (VMVNd DPR:$Vd, DPR:$Vm, pred:$p)>;
6966 defm : NEONDTAnyInstAlias<"vmvn${p}", "$Vd, $Vm",
6967 (VMVNq QPR:$Vd, QPR:$Vm, pred:$p)>;
6969 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
6970 // D-register versions.
6971 def : NEONInstAlias<"vcle${p}.s8 $Dd, $Dn, $Dm",
6972 (VCGEsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6973 def : NEONInstAlias<"vcle${p}.s16 $Dd, $Dn, $Dm",
6974 (VCGEsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6975 def : NEONInstAlias<"vcle${p}.s32 $Dd, $Dn, $Dm",
6976 (VCGEsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6977 def : NEONInstAlias<"vcle${p}.u8 $Dd, $Dn, $Dm",
6978 (VCGEuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6979 def : NEONInstAlias<"vcle${p}.u16 $Dd, $Dn, $Dm",
6980 (VCGEuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6981 def : NEONInstAlias<"vcle${p}.u32 $Dd, $Dn, $Dm",
6982 (VCGEuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6983 def : NEONInstAlias<"vcle${p}.f32 $Dd, $Dn, $Dm",
6984 (VCGEfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6985 // Q-register versions.
6986 def : NEONInstAlias<"vcle${p}.s8 $Qd, $Qn, $Qm",
6987 (VCGEsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6988 def : NEONInstAlias<"vcle${p}.s16 $Qd, $Qn, $Qm",
6989 (VCGEsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6990 def : NEONInstAlias<"vcle${p}.s32 $Qd, $Qn, $Qm",
6991 (VCGEsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6992 def : NEONInstAlias<"vcle${p}.u8 $Qd, $Qn, $Qm",
6993 (VCGEuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6994 def : NEONInstAlias<"vcle${p}.u16 $Qd, $Qn, $Qm",
6995 (VCGEuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6996 def : NEONInstAlias<"vcle${p}.u32 $Qd, $Qn, $Qm",
6997 (VCGEuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6998 def : NEONInstAlias<"vcle${p}.f32 $Qd, $Qn, $Qm",
6999 (VCGEfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7001 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
7002 // D-register versions.
7003 def : NEONInstAlias<"vclt${p}.s8 $Dd, $Dn, $Dm",
7004 (VCGTsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7005 def : NEONInstAlias<"vclt${p}.s16 $Dd, $Dn, $Dm",
7006 (VCGTsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7007 def : NEONInstAlias<"vclt${p}.s32 $Dd, $Dn, $Dm",
7008 (VCGTsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7009 def : NEONInstAlias<"vclt${p}.u8 $Dd, $Dn, $Dm",
7010 (VCGTuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7011 def : NEONInstAlias<"vclt${p}.u16 $Dd, $Dn, $Dm",
7012 (VCGTuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7013 def : NEONInstAlias<"vclt${p}.u32 $Dd, $Dn, $Dm",
7014 (VCGTuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7015 def : NEONInstAlias<"vclt${p}.f32 $Dd, $Dn, $Dm",
7016 (VCGTfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7017 // Q-register versions.
7018 def : NEONInstAlias<"vclt${p}.s8 $Qd, $Qn, $Qm",
7019 (VCGTsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7020 def : NEONInstAlias<"vclt${p}.s16 $Qd, $Qn, $Qm",
7021 (VCGTsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7022 def : NEONInstAlias<"vclt${p}.s32 $Qd, $Qn, $Qm",
7023 (VCGTsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7024 def : NEONInstAlias<"vclt${p}.u8 $Qd, $Qn, $Qm",
7025 (VCGTuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7026 def : NEONInstAlias<"vclt${p}.u16 $Qd, $Qn, $Qm",
7027 (VCGTuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7028 def : NEONInstAlias<"vclt${p}.u32 $Qd, $Qn, $Qm",
7029 (VCGTuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7030 def : NEONInstAlias<"vclt${p}.f32 $Qd, $Qn, $Qm",
7031 (VCGTfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7033 // VSWP allows, but does not require, a type suffix.
7034 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
7035 (VSWPd DPR:$Vd, DPR:$Vm, pred:$p)>;
7036 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
7037 (VSWPq QPR:$Vd, QPR:$Vm, pred:$p)>;
7039 // VBIF, VBIT, and VBSL allow, but do not require, a type suffix.
7040 defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm",
7041 (VBIFd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
7042 defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm",
7043 (VBITd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
7044 defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm",
7045 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
7046 defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm",
7047 (VBIFq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
7048 defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm",
7049 (VBITq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
7050 defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm",
7051 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
7053 // "vmov Rd, #-imm" can be handled via "vmvn".
7054 def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
7055 (VMVNv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
7056 def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
7057 (VMVNv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
7058 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
7059 (VMOVv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
7060 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
7061 (VMOVv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
7063 // 'gas' compatibility aliases for quad-word instructions. Strictly speaking,
7064 // these should restrict to just the Q register variants, but the register
7065 // classes are enough to match correctly regardless, so we keep it simple
7066 // and just use MnemonicAlias.
7067 def : NEONMnemonicAlias<"vbicq", "vbic">;
7068 def : NEONMnemonicAlias<"vandq", "vand">;
7069 def : NEONMnemonicAlias<"veorq", "veor">;
7070 def : NEONMnemonicAlias<"vorrq", "vorr">;
7072 def : NEONMnemonicAlias<"vmovq", "vmov">;
7073 def : NEONMnemonicAlias<"vmvnq", "vmvn">;
7074 // Explicit versions for floating point so that the FPImm variants get
7075 // handled early. The parser gets confused otherwise.
7076 def : NEONMnemonicAlias<"vmovq.f32", "vmov.f32">;
7077 def : NEONMnemonicAlias<"vmovq.f64", "vmov.f64">;
7079 def : NEONMnemonicAlias<"vaddq", "vadd">;
7080 def : NEONMnemonicAlias<"vsubq", "vsub">;
7082 def : NEONMnemonicAlias<"vminq", "vmin">;
7083 def : NEONMnemonicAlias<"vmaxq", "vmax">;
7085 def : NEONMnemonicAlias<"vmulq", "vmul">;
7087 def : NEONMnemonicAlias<"vabsq", "vabs">;
7089 def : NEONMnemonicAlias<"vshlq", "vshl">;
7090 def : NEONMnemonicAlias<"vshrq", "vshr">;
7092 def : NEONMnemonicAlias<"vcvtq", "vcvt">;
7094 def : NEONMnemonicAlias<"vcleq", "vcle">;
7095 def : NEONMnemonicAlias<"vceqq", "vceq">;
7097 def : NEONMnemonicAlias<"vzipq", "vzip">;
7098 def : NEONMnemonicAlias<"vswpq", "vswp">;
7100 def : NEONMnemonicAlias<"vrecpeq.f32", "vrecpe.f32">;
7101 def : NEONMnemonicAlias<"vrecpeq.u32", "vrecpe.u32">;
7104 // Alias for loading floating point immediates that aren't representable
7105 // using the vmov.f32 encoding but the bitpattern is representable using
7106 // the .i32 encoding.
7107 def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
7108 (VMOVv4i32 QPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;
7109 def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
7110 (VMOVv2i32 DPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;