1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // NEON-specific Operands.
17 //===----------------------------------------------------------------------===//
18 def nModImm : Operand<i32> {
19 let PrintMethod = "printNEONModImmOperand";
22 def nImmSplatI8AsmOperand : AsmOperandClass { let Name = "NEONi8splat"; }
23 def nImmSplatI8 : Operand<i32> {
24 let PrintMethod = "printNEONModImmOperand";
25 let ParserMatchClass = nImmSplatI8AsmOperand;
27 def nImmSplatI16AsmOperand : AsmOperandClass { let Name = "NEONi16splat"; }
28 def nImmSplatI16 : Operand<i32> {
29 let PrintMethod = "printNEONModImmOperand";
30 let ParserMatchClass = nImmSplatI16AsmOperand;
32 def nImmSplatI32AsmOperand : AsmOperandClass { let Name = "NEONi32splat"; }
33 def nImmSplatI32 : Operand<i32> {
34 let PrintMethod = "printNEONModImmOperand";
35 let ParserMatchClass = nImmSplatI32AsmOperand;
37 def nImmVMOVI32AsmOperand : AsmOperandClass { let Name = "NEONi32vmov"; }
38 def nImmVMOVI32 : Operand<i32> {
39 let PrintMethod = "printNEONModImmOperand";
40 let ParserMatchClass = nImmVMOVI32AsmOperand;
42 def nImmVMOVI32NegAsmOperand : AsmOperandClass { let Name = "NEONi32vmovNeg"; }
43 def nImmVMOVI32Neg : Operand<i32> {
44 let PrintMethod = "printNEONModImmOperand";
45 let ParserMatchClass = nImmVMOVI32NegAsmOperand;
47 def nImmVMOVF32 : Operand<i32> {
48 let PrintMethod = "printFPImmOperand";
49 let ParserMatchClass = FPImmOperand;
51 def nImmSplatI64AsmOperand : AsmOperandClass { let Name = "NEONi64splat"; }
52 def nImmSplatI64 : Operand<i32> {
53 let PrintMethod = "printNEONModImmOperand";
54 let ParserMatchClass = nImmSplatI64AsmOperand;
57 def VectorIndex8Operand : AsmOperandClass { let Name = "VectorIndex8"; }
58 def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; }
59 def VectorIndex32Operand : AsmOperandClass { let Name = "VectorIndex32"; }
60 def VectorIndex8 : Operand<i32>, ImmLeaf<i32, [{
61 return ((uint64_t)Imm) < 8;
63 let ParserMatchClass = VectorIndex8Operand;
64 let PrintMethod = "printVectorIndex";
65 let MIOperandInfo = (ops i32imm);
67 def VectorIndex16 : Operand<i32>, ImmLeaf<i32, [{
68 return ((uint64_t)Imm) < 4;
70 let ParserMatchClass = VectorIndex16Operand;
71 let PrintMethod = "printVectorIndex";
72 let MIOperandInfo = (ops i32imm);
74 def VectorIndex32 : Operand<i32>, ImmLeaf<i32, [{
75 return ((uint64_t)Imm) < 2;
77 let ParserMatchClass = VectorIndex32Operand;
78 let PrintMethod = "printVectorIndex";
79 let MIOperandInfo = (ops i32imm);
82 // Register list of one D register.
83 def VecListOneDAsmOperand : AsmOperandClass {
84 let Name = "VecListOneD";
85 let ParserMethod = "parseVectorList";
86 let RenderMethod = "addVecListOperands";
88 def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> {
89 let ParserMatchClass = VecListOneDAsmOperand;
91 // Register list of two sequential D registers.
92 def VecListTwoDAsmOperand : AsmOperandClass {
93 let Name = "VecListTwoD";
94 let ParserMethod = "parseVectorList";
95 let RenderMethod = "addVecListOperands";
97 def VecListTwoD : RegisterOperand<DPR, "printVectorListTwo"> {
98 let ParserMatchClass = VecListTwoDAsmOperand;
100 // Register list of three sequential D registers.
101 def VecListThreeDAsmOperand : AsmOperandClass {
102 let Name = "VecListThreeD";
103 let ParserMethod = "parseVectorList";
104 let RenderMethod = "addVecListOperands";
106 def VecListThreeD : RegisterOperand<DPR, "printVectorListThree"> {
107 let ParserMatchClass = VecListThreeDAsmOperand;
109 // Register list of four sequential D registers.
110 def VecListFourDAsmOperand : AsmOperandClass {
111 let Name = "VecListFourD";
112 let ParserMethod = "parseVectorList";
113 let RenderMethod = "addVecListOperands";
115 def VecListFourD : RegisterOperand<DPR, "printVectorListFour"> {
116 let ParserMatchClass = VecListFourDAsmOperand;
118 // Register list of two D registers spaced by 2 (two sequential Q registers).
119 def VecListTwoQAsmOperand : AsmOperandClass {
120 let Name = "VecListTwoQ";
121 let ParserMethod = "parseVectorList";
122 let RenderMethod = "addVecListOperands";
124 def VecListTwoQ : RegisterOperand<DPR, "printVectorListTwoSpaced"> {
125 let ParserMatchClass = VecListTwoQAsmOperand;
128 // Register list of one D register, with "all lanes" subscripting.
129 def VecListOneDAllLanesAsmOperand : AsmOperandClass {
130 let Name = "VecListOneDAllLanes";
131 let ParserMethod = "parseVectorList";
132 let RenderMethod = "addVecListOperands";
134 def VecListOneDAllLanes : RegisterOperand<DPR, "printVectorListOneAllLanes"> {
135 let ParserMatchClass = VecListOneDAllLanesAsmOperand;
137 // Register list of two D registers, with "all lanes" subscripting.
138 def VecListTwoDAllLanesAsmOperand : AsmOperandClass {
139 let Name = "VecListTwoDAllLanes";
140 let ParserMethod = "parseVectorList";
141 let RenderMethod = "addVecListOperands";
143 def VecListTwoDAllLanes : RegisterOperand<DPR, "printVectorListTwoAllLanes"> {
144 let ParserMatchClass = VecListTwoDAllLanesAsmOperand;
146 // Register list of two D registers spaced by 2 (two sequential Q registers).
147 def VecListTwoQAllLanesAsmOperand : AsmOperandClass {
148 let Name = "VecListTwoQAllLanes";
149 let ParserMethod = "parseVectorList";
150 let RenderMethod = "addVecListOperands";
152 def VecListTwoQAllLanes : RegisterOperand<DPR,
153 "printVectorListTwoSpacedAllLanes"> {
154 let ParserMatchClass = VecListTwoQAllLanesAsmOperand;
157 // Register list of one D register, with byte lane subscripting.
158 def VecListOneDByteIndexAsmOperand : AsmOperandClass {
159 let Name = "VecListOneDByteIndexed";
160 let ParserMethod = "parseVectorList";
161 let RenderMethod = "addVecListIndexedOperands";
163 def VecListOneDByteIndexed : Operand<i32> {
164 let ParserMatchClass = VecListOneDByteIndexAsmOperand;
165 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
167 // ...with half-word lane subscripting.
168 def VecListOneDHWordIndexAsmOperand : AsmOperandClass {
169 let Name = "VecListOneDHWordIndexed";
170 let ParserMethod = "parseVectorList";
171 let RenderMethod = "addVecListIndexedOperands";
173 def VecListOneDHWordIndexed : Operand<i32> {
174 let ParserMatchClass = VecListOneDHWordIndexAsmOperand;
175 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
177 // ...with word lane subscripting.
178 def VecListOneDWordIndexAsmOperand : AsmOperandClass {
179 let Name = "VecListOneDWordIndexed";
180 let ParserMethod = "parseVectorList";
181 let RenderMethod = "addVecListIndexedOperands";
183 def VecListOneDWordIndexed : Operand<i32> {
184 let ParserMatchClass = VecListOneDWordIndexAsmOperand;
185 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
187 // Register list of two D registers with byte lane subscripting.
188 def VecListTwoDByteIndexAsmOperand : AsmOperandClass {
189 let Name = "VecListTwoDByteIndexed";
190 let ParserMethod = "parseVectorList";
191 let RenderMethod = "addVecListIndexedOperands";
193 def VecListTwoDByteIndexed : Operand<i32> {
194 let ParserMatchClass = VecListTwoDByteIndexAsmOperand;
195 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
197 // ...with half-word lane subscripting.
198 def VecListTwoDHWordIndexAsmOperand : AsmOperandClass {
199 let Name = "VecListTwoDHWordIndexed";
200 let ParserMethod = "parseVectorList";
201 let RenderMethod = "addVecListIndexedOperands";
203 def VecListTwoDHWordIndexed : Operand<i32> {
204 let ParserMatchClass = VecListTwoDHWordIndexAsmOperand;
205 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
207 // ...with word lane subscripting.
208 def VecListTwoDWordIndexAsmOperand : AsmOperandClass {
209 let Name = "VecListTwoDWordIndexed";
210 let ParserMethod = "parseVectorList";
211 let RenderMethod = "addVecListIndexedOperands";
213 def VecListTwoDWordIndexed : Operand<i32> {
214 let ParserMatchClass = VecListTwoDWordIndexAsmOperand;
215 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
217 // Register list of two Q registers with half-word lane subscripting.
218 def VecListTwoQHWordIndexAsmOperand : AsmOperandClass {
219 let Name = "VecListTwoQHWordIndexed";
220 let ParserMethod = "parseVectorList";
221 let RenderMethod = "addVecListIndexedOperands";
223 def VecListTwoQHWordIndexed : Operand<i32> {
224 let ParserMatchClass = VecListTwoQHWordIndexAsmOperand;
225 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
227 // ...with word lane subscripting.
228 def VecListTwoQWordIndexAsmOperand : AsmOperandClass {
229 let Name = "VecListTwoQWordIndexed";
230 let ParserMethod = "parseVectorList";
231 let RenderMethod = "addVecListIndexedOperands";
233 def VecListTwoQWordIndexed : Operand<i32> {
234 let ParserMatchClass = VecListTwoQWordIndexAsmOperand;
235 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
238 //===----------------------------------------------------------------------===//
239 // NEON-specific DAG Nodes.
240 //===----------------------------------------------------------------------===//
242 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
243 def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
245 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
246 def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
247 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
248 def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
249 def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
250 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
251 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
252 def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
253 def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
254 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
255 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
257 // Types for vector shift by immediates. The "SHX" version is for long and
258 // narrow operations where the source and destination vectors have different
259 // types. The "SHINS" version is for shift and insert operations.
260 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
262 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
264 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
265 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
267 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
268 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
269 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
270 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
271 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
272 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
273 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
275 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
276 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
277 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
279 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
280 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
281 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
282 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
283 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
284 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
286 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
287 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
288 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
290 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
291 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
293 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
295 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
296 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
298 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
299 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
300 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
301 def NEONvmovFPImm : SDNode<"ARMISD::VMOVFPIMM", SDTARMVMOVIMM>;
303 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
305 def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
306 def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
308 def NEONvbsl : SDNode<"ARMISD::VBSL",
309 SDTypeProfile<1, 3, [SDTCisVec<0>,
312 SDTCisSameAs<0, 3>]>>;
314 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
316 // VDUPLANE can produce a quad-register result from a double-register source,
317 // so the result is not constrained to match the source.
318 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
319 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
322 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
323 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
324 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
326 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
327 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
328 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
329 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
331 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
333 SDTCisSameAs<0, 3>]>;
334 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
335 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
336 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
338 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
339 SDTCisSameAs<1, 2>]>;
340 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
341 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
343 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
344 SDTCisSameAs<0, 2>]>;
345 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
346 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
348 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
349 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
350 unsigned EltBits = 0;
351 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
352 return (EltBits == 32 && EltVal == 0);
355 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
356 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
357 unsigned EltBits = 0;
358 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
359 return (EltBits == 8 && EltVal == 0xff);
362 //===----------------------------------------------------------------------===//
363 // NEON load / store instructions
364 //===----------------------------------------------------------------------===//
366 // Use VLDM to load a Q register as a D register pair.
367 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
369 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
371 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
373 // Use VSTM to store a Q register as a D register pair.
374 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
376 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
378 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
380 // Classes for VLD* pseudo-instructions with multi-register operands.
381 // These are expanded to real instructions after register allocation.
382 class VLDQPseudo<InstrItinClass itin>
383 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
384 class VLDQWBPseudo<InstrItinClass itin>
385 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
386 (ins addrmode6:$addr, am6offset:$offset), itin,
388 class VLDQWBfixedPseudo<InstrItinClass itin>
389 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
390 (ins addrmode6:$addr), itin,
392 class VLDQWBregisterPseudo<InstrItinClass itin>
393 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
394 (ins addrmode6:$addr, rGPR:$offset), itin,
397 class VLDQQPseudo<InstrItinClass itin>
398 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
399 class VLDQQWBPseudo<InstrItinClass itin>
400 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
401 (ins addrmode6:$addr, am6offset:$offset), itin,
403 class VLDQQWBfixedPseudo<InstrItinClass itin>
404 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
405 (ins addrmode6:$addr), itin,
407 class VLDQQWBregisterPseudo<InstrItinClass itin>
408 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
409 (ins addrmode6:$addr, rGPR:$offset), itin,
413 class VLDQQQQPseudo<InstrItinClass itin>
414 : PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src),itin,
416 class VLDQQQQWBPseudo<InstrItinClass itin>
417 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
418 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
419 "$addr.addr = $wb, $src = $dst">;
421 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
423 // VLD1 : Vector Load (multiple single elements)
424 class VLD1D<bits<4> op7_4, string Dt>
425 : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd),
426 (ins addrmode6:$Rn), IIC_VLD1,
427 "vld1", Dt, "$Vd, $Rn", "", []> {
430 let DecoderMethod = "DecodeVLDInstruction";
432 class VLD1Q<bits<4> op7_4, string Dt>
433 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd),
434 (ins addrmode6:$Rn), IIC_VLD1x2,
435 "vld1", Dt, "$Vd, $Rn", "", []> {
437 let Inst{5-4} = Rn{5-4};
438 let DecoderMethod = "DecodeVLDInstruction";
441 def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
442 def VLD1d16 : VLD1D<{0,1,0,?}, "16">;
443 def VLD1d32 : VLD1D<{1,0,0,?}, "32">;
444 def VLD1d64 : VLD1D<{1,1,0,?}, "64">;
446 def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;
447 def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
448 def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
449 def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
451 def VLD1q8Pseudo : VLDQPseudo<IIC_VLD1x2>;
452 def VLD1q16Pseudo : VLDQPseudo<IIC_VLD1x2>;
453 def VLD1q32Pseudo : VLDQPseudo<IIC_VLD1x2>;
454 def VLD1q64Pseudo : VLDQPseudo<IIC_VLD1x2>;
456 // ...with address register writeback:
457 multiclass VLD1DWB<bits<4> op7_4, string Dt> {
458 def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
459 (ins addrmode6:$Rn), IIC_VLD1u,
460 "vld1", Dt, "$Vd, $Rn!",
461 "$Rn.addr = $wb", []> {
462 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
464 let DecoderMethod = "DecodeVLDInstruction";
465 let AsmMatchConverter = "cvtVLDwbFixed";
467 def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
468 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1u,
469 "vld1", Dt, "$Vd, $Rn, $Rm",
470 "$Rn.addr = $wb", []> {
472 let DecoderMethod = "DecodeVLDInstruction";
473 let AsmMatchConverter = "cvtVLDwbRegister";
476 multiclass VLD1QWB<bits<4> op7_4, string Dt> {
477 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd, GPR:$wb),
478 (ins addrmode6:$Rn), IIC_VLD1x2u,
479 "vld1", Dt, "$Vd, $Rn!",
480 "$Rn.addr = $wb", []> {
481 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
482 let Inst{5-4} = Rn{5-4};
483 let DecoderMethod = "DecodeVLDInstruction";
484 let AsmMatchConverter = "cvtVLDwbFixed";
486 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd, GPR:$wb),
487 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
488 "vld1", Dt, "$Vd, $Rn, $Rm",
489 "$Rn.addr = $wb", []> {
490 let Inst{5-4} = Rn{5-4};
491 let DecoderMethod = "DecodeVLDInstruction";
492 let AsmMatchConverter = "cvtVLDwbRegister";
496 defm VLD1d8wb : VLD1DWB<{0,0,0,?}, "8">;
497 defm VLD1d16wb : VLD1DWB<{0,1,0,?}, "16">;
498 defm VLD1d32wb : VLD1DWB<{1,0,0,?}, "32">;
499 defm VLD1d64wb : VLD1DWB<{1,1,0,?}, "64">;
500 defm VLD1q8wb : VLD1QWB<{0,0,?,?}, "8">;
501 defm VLD1q16wb : VLD1QWB<{0,1,?,?}, "16">;
502 defm VLD1q32wb : VLD1QWB<{1,0,?,?}, "32">;
503 defm VLD1q64wb : VLD1QWB<{1,1,?,?}, "64">;
505 def VLD1q8PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
506 def VLD1q16PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
507 def VLD1q32PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
508 def VLD1q64PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
509 def VLD1q8PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
510 def VLD1q16PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
511 def VLD1q32PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
512 def VLD1q64PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
514 // ...with 3 registers
515 class VLD1D3<bits<4> op7_4, string Dt>
516 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd),
517 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
518 "$Vd, $Rn", "", []> {
521 let DecoderMethod = "DecodeVLDInstruction";
523 multiclass VLD1D3WB<bits<4> op7_4, string Dt> {
524 def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
525 (ins addrmode6:$Rn), IIC_VLD1x2u,
526 "vld1", Dt, "$Vd, $Rn!",
527 "$Rn.addr = $wb", []> {
528 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
530 let DecoderMethod = "DecodeVLDInstruction";
531 let AsmMatchConverter = "cvtVLDwbFixed";
533 def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
534 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
535 "vld1", Dt, "$Vd, $Rn, $Rm",
536 "$Rn.addr = $wb", []> {
538 let DecoderMethod = "DecodeVLDInstruction";
539 let AsmMatchConverter = "cvtVLDwbRegister";
543 def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
544 def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;
545 def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;
546 def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;
548 defm VLD1d8Twb : VLD1D3WB<{0,0,0,?}, "8">;
549 defm VLD1d16Twb : VLD1D3WB<{0,1,0,?}, "16">;
550 defm VLD1d32Twb : VLD1D3WB<{1,0,0,?}, "32">;
551 defm VLD1d64Twb : VLD1D3WB<{1,1,0,?}, "64">;
553 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
555 // ...with 4 registers
556 class VLD1D4<bits<4> op7_4, string Dt>
557 : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd),
558 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
559 "$Vd, $Rn", "", []> {
561 let Inst{5-4} = Rn{5-4};
562 let DecoderMethod = "DecodeVLDInstruction";
564 multiclass VLD1D4WB<bits<4> op7_4, string Dt> {
565 def _fixed : NLdSt<0,0b10,0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb),
566 (ins addrmode6:$Rn), IIC_VLD1x2u,
567 "vld1", Dt, "$Vd, $Rn!",
568 "$Rn.addr = $wb", []> {
569 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
570 let Inst{5-4} = Rn{5-4};
571 let DecoderMethod = "DecodeVLDInstruction";
572 let AsmMatchConverter = "cvtVLDwbFixed";
574 def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb),
575 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
576 "vld1", Dt, "$Vd, $Rn, $Rm",
577 "$Rn.addr = $wb", []> {
578 let Inst{5-4} = Rn{5-4};
579 let DecoderMethod = "DecodeVLDInstruction";
580 let AsmMatchConverter = "cvtVLDwbRegister";
584 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
585 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;
586 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;
587 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;
589 defm VLD1d8Qwb : VLD1D4WB<{0,0,?,?}, "8">;
590 defm VLD1d16Qwb : VLD1D4WB<{0,1,?,?}, "16">;
591 defm VLD1d32Qwb : VLD1D4WB<{1,0,?,?}, "32">;
592 defm VLD1d64Qwb : VLD1D4WB<{1,1,?,?}, "64">;
594 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
596 // VLD2 : Vector Load (multiple 2-element structures)
597 class VLD2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
599 : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd),
600 (ins addrmode6:$Rn), itin,
601 "vld2", Dt, "$Vd, $Rn", "", []> {
603 let Inst{5-4} = Rn{5-4};
604 let DecoderMethod = "DecodeVLDInstruction";
607 def VLD2d8 : VLD2<0b1000, {0,0,?,?}, "8", VecListTwoD, IIC_VLD2>;
608 def VLD2d16 : VLD2<0b1000, {0,1,?,?}, "16", VecListTwoD, IIC_VLD2>;
609 def VLD2d32 : VLD2<0b1000, {1,0,?,?}, "32", VecListTwoD, IIC_VLD2>;
611 def VLD2q8 : VLD2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2>;
612 def VLD2q16 : VLD2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2>;
613 def VLD2q32 : VLD2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2>;
615 def VLD2d8Pseudo : VLDQPseudo<IIC_VLD2>;
616 def VLD2d16Pseudo : VLDQPseudo<IIC_VLD2>;
617 def VLD2d32Pseudo : VLDQPseudo<IIC_VLD2>;
619 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
620 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
621 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
623 // ...with address register writeback:
624 multiclass VLD2WB<bits<4> op11_8, bits<4> op7_4, string Dt,
625 RegisterOperand VdTy, InstrItinClass itin> {
626 def _fixed : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
627 (ins addrmode6:$Rn), itin,
628 "vld2", Dt, "$Vd, $Rn!",
629 "$Rn.addr = $wb", []> {
630 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
631 let Inst{5-4} = Rn{5-4};
632 let DecoderMethod = "DecodeVLDInstruction";
633 let AsmMatchConverter = "cvtVLDwbFixed";
635 def _register : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
636 (ins addrmode6:$Rn, rGPR:$Rm), itin,
637 "vld2", Dt, "$Vd, $Rn, $Rm",
638 "$Rn.addr = $wb", []> {
639 let Inst{5-4} = Rn{5-4};
640 let DecoderMethod = "DecodeVLDInstruction";
641 let AsmMatchConverter = "cvtVLDwbRegister";
645 defm VLD2d8wb : VLD2WB<0b1000, {0,0,?,?}, "8", VecListTwoD, IIC_VLD2u>;
646 defm VLD2d16wb : VLD2WB<0b1000, {0,1,?,?}, "16", VecListTwoD, IIC_VLD2u>;
647 defm VLD2d32wb : VLD2WB<0b1000, {1,0,?,?}, "32", VecListTwoD, IIC_VLD2u>;
649 defm VLD2q8wb : VLD2WB<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2u>;
650 defm VLD2q16wb : VLD2WB<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2u>;
651 defm VLD2q32wb : VLD2WB<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2u>;
653 def VLD2d8PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD2u>;
654 def VLD2d16PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD2u>;
655 def VLD2d32PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD2u>;
656 def VLD2d8PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD2u>;
657 def VLD2d16PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD2u>;
658 def VLD2d32PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD2u>;
660 def VLD2q8PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
661 def VLD2q16PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
662 def VLD2q32PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
663 def VLD2q8PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
664 def VLD2q16PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
665 def VLD2q32PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
667 // ...with double-spaced registers
668 def VLD2b8 : VLD2<0b1001, {0,0,?,?}, "8", VecListTwoQ, IIC_VLD2>;
669 def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListTwoQ, IIC_VLD2>;
670 def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListTwoQ, IIC_VLD2>;
671 defm VLD2b8wb : VLD2WB<0b1001, {0,0,?,?}, "8", VecListTwoQ, IIC_VLD2u>;
672 defm VLD2b16wb : VLD2WB<0b1001, {0,1,?,?}, "16", VecListTwoQ, IIC_VLD2u>;
673 defm VLD2b32wb : VLD2WB<0b1001, {1,0,?,?}, "32", VecListTwoQ, IIC_VLD2u>;
675 // VLD3 : Vector Load (multiple 3-element structures)
676 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
677 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
678 (ins addrmode6:$Rn), IIC_VLD3,
679 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
682 let DecoderMethod = "DecodeVLDInstruction";
685 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
686 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
687 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
689 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
690 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
691 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
693 // ...with address register writeback:
694 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
695 : NLdSt<0, 0b10, op11_8, op7_4,
696 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
697 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
698 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
699 "$Rn.addr = $wb", []> {
701 let DecoderMethod = "DecodeVLDInstruction";
704 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
705 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
706 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
708 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
709 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
710 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
712 // ...with double-spaced registers:
713 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
714 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
715 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
716 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
717 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
718 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
720 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
721 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
722 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
724 // ...alternate versions to be allocated odd register numbers:
725 def VLD3q8oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
726 def VLD3q16oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
727 def VLD3q32oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
729 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
730 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
731 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
733 // VLD4 : Vector Load (multiple 4-element structures)
734 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
735 : NLdSt<0, 0b10, op11_8, op7_4,
736 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
737 (ins addrmode6:$Rn), IIC_VLD4,
738 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
740 let Inst{5-4} = Rn{5-4};
741 let DecoderMethod = "DecodeVLDInstruction";
744 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
745 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
746 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
748 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
749 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
750 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
752 // ...with address register writeback:
753 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
754 : NLdSt<0, 0b10, op11_8, op7_4,
755 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
756 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u,
757 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
758 "$Rn.addr = $wb", []> {
759 let Inst{5-4} = Rn{5-4};
760 let DecoderMethod = "DecodeVLDInstruction";
763 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
764 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
765 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
767 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
768 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
769 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
771 // ...with double-spaced registers:
772 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
773 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
774 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
775 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
776 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
777 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
779 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
780 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
781 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
783 // ...alternate versions to be allocated odd register numbers:
784 def VLD4q8oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
785 def VLD4q16oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
786 def VLD4q32oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
788 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
789 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
790 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
792 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
794 // Classes for VLD*LN pseudo-instructions with multi-register operands.
795 // These are expanded to real instructions after register allocation.
796 class VLDQLNPseudo<InstrItinClass itin>
797 : PseudoNLdSt<(outs QPR:$dst),
798 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
799 itin, "$src = $dst">;
800 class VLDQLNWBPseudo<InstrItinClass itin>
801 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
802 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
803 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
804 class VLDQQLNPseudo<InstrItinClass itin>
805 : PseudoNLdSt<(outs QQPR:$dst),
806 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
807 itin, "$src = $dst">;
808 class VLDQQLNWBPseudo<InstrItinClass itin>
809 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
810 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
811 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
812 class VLDQQQQLNPseudo<InstrItinClass itin>
813 : PseudoNLdSt<(outs QQQQPR:$dst),
814 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
815 itin, "$src = $dst">;
816 class VLDQQQQLNWBPseudo<InstrItinClass itin>
817 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
818 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
819 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
821 // VLD1LN : Vector Load (single element to one lane)
822 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
824 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
825 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
826 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
828 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
829 (i32 (LoadOp addrmode6:$Rn)),
832 let DecoderMethod = "DecodeVLD1LN";
834 class VLD1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
836 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
837 (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane),
838 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
840 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
841 (i32 (LoadOp addrmode6oneL32:$Rn)),
844 let DecoderMethod = "DecodeVLD1LN";
846 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
847 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
848 (i32 (LoadOp addrmode6:$addr)),
852 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
853 let Inst{7-5} = lane{2-0};
855 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
856 let Inst{7-6} = lane{1-0};
857 let Inst{5-4} = Rn{5-4};
859 def VLD1LNd32 : VLD1LN32<0b1000, {?,0,?,?}, "32", v2i32, load> {
860 let Inst{7} = lane{0};
861 let Inst{5-4} = Rn{5-4};
864 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
865 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
866 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
868 def : Pat<(vector_insert (v2f32 DPR:$src),
869 (f32 (load addrmode6:$addr)), imm:$lane),
870 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
871 def : Pat<(vector_insert (v4f32 QPR:$src),
872 (f32 (load addrmode6:$addr)), imm:$lane),
873 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
875 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
877 // ...with address register writeback:
878 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
879 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
880 (ins addrmode6:$Rn, am6offset:$Rm,
881 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
882 "\\{$Vd[$lane]\\}, $Rn$Rm",
883 "$src = $Vd, $Rn.addr = $wb", []> {
884 let DecoderMethod = "DecodeVLD1LN";
887 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
888 let Inst{7-5} = lane{2-0};
890 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
891 let Inst{7-6} = lane{1-0};
894 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
895 let Inst{7} = lane{0};
900 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
901 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
902 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
904 // VLD2LN : Vector Load (single 2-element structure to one lane)
905 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
906 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
907 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
908 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
909 "$src1 = $Vd, $src2 = $dst2", []> {
912 let DecoderMethod = "DecodeVLD2LN";
915 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
916 let Inst{7-5} = lane{2-0};
918 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
919 let Inst{7-6} = lane{1-0};
921 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
922 let Inst{7} = lane{0};
925 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
926 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
927 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
929 // ...with double-spaced registers:
930 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
931 let Inst{7-6} = lane{1-0};
933 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
934 let Inst{7} = lane{0};
937 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
938 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
940 // ...with address register writeback:
941 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
942 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
943 (ins addrmode6:$Rn, am6offset:$Rm,
944 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
945 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
946 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
948 let DecoderMethod = "DecodeVLD2LN";
951 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
952 let Inst{7-5} = lane{2-0};
954 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
955 let Inst{7-6} = lane{1-0};
957 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
958 let Inst{7} = lane{0};
961 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
962 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
963 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
965 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
966 let Inst{7-6} = lane{1-0};
968 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
969 let Inst{7} = lane{0};
972 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
973 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
975 // VLD3LN : Vector Load (single 3-element structure to one lane)
976 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
977 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
978 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
979 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
980 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
981 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
983 let DecoderMethod = "DecodeVLD3LN";
986 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
987 let Inst{7-5} = lane{2-0};
989 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
990 let Inst{7-6} = lane{1-0};
992 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
993 let Inst{7} = lane{0};
996 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
997 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
998 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1000 // ...with double-spaced registers:
1001 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
1002 let Inst{7-6} = lane{1-0};
1004 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
1005 let Inst{7} = lane{0};
1008 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
1009 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
1011 // ...with address register writeback:
1012 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1013 : NLdStLn<1, 0b10, op11_8, op7_4,
1014 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1015 (ins addrmode6:$Rn, am6offset:$Rm,
1016 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1017 IIC_VLD3lnu, "vld3", Dt,
1018 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
1019 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
1021 let DecoderMethod = "DecodeVLD3LN";
1024 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
1025 let Inst{7-5} = lane{2-0};
1027 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
1028 let Inst{7-6} = lane{1-0};
1030 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
1031 let Inst{7} = lane{0};
1034 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1035 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1036 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1038 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
1039 let Inst{7-6} = lane{1-0};
1041 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
1042 let Inst{7} = lane{0};
1045 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
1046 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
1048 // VLD4LN : Vector Load (single 4-element structure to one lane)
1049 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1050 : NLdStLn<1, 0b10, op11_8, op7_4,
1051 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1052 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
1053 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
1054 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
1055 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
1057 let Inst{4} = Rn{4};
1058 let DecoderMethod = "DecodeVLD4LN";
1061 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
1062 let Inst{7-5} = lane{2-0};
1064 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
1065 let Inst{7-6} = lane{1-0};
1067 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
1068 let Inst{7} = lane{0};
1069 let Inst{5} = Rn{5};
1072 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1073 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1074 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1076 // ...with double-spaced registers:
1077 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
1078 let Inst{7-6} = lane{1-0};
1080 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
1081 let Inst{7} = lane{0};
1082 let Inst{5} = Rn{5};
1085 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
1086 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
1088 // ...with address register writeback:
1089 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1090 : NLdStLn<1, 0b10, op11_8, op7_4,
1091 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1092 (ins addrmode6:$Rn, am6offset:$Rm,
1093 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1094 IIC_VLD4lnu, "vld4", Dt,
1095 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
1096 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
1098 let Inst{4} = Rn{4};
1099 let DecoderMethod = "DecodeVLD4LN" ;
1102 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
1103 let Inst{7-5} = lane{2-0};
1105 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
1106 let Inst{7-6} = lane{1-0};
1108 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
1109 let Inst{7} = lane{0};
1110 let Inst{5} = Rn{5};
1113 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1114 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1115 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1117 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
1118 let Inst{7-6} = lane{1-0};
1120 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
1121 let Inst{7} = lane{0};
1122 let Inst{5} = Rn{5};
1125 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
1126 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
1128 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1130 // VLD1DUP : Vector Load (single element to all lanes)
1131 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
1132 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd),
1133 (ins addrmode6dup:$Rn),
1134 IIC_VLD1dup, "vld1", Dt, "$Vd, $Rn", "",
1135 [(set VecListOneDAllLanes:$Vd,
1136 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
1138 let Inst{4} = Rn{4};
1139 let DecoderMethod = "DecodeVLD1DupInstruction";
1141 class VLD1QDUPPseudo<ValueType Ty, PatFrag LoadOp> : VLDQPseudo<IIC_VLD1dup> {
1142 let Pattern = [(set QPR:$dst,
1143 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$addr)))))];
1146 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
1147 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;
1148 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;
1150 def VLD1DUPq8Pseudo : VLD1QDUPPseudo<v16i8, extloadi8>;
1151 def VLD1DUPq16Pseudo : VLD1QDUPPseudo<v8i16, extloadi16>;
1152 def VLD1DUPq32Pseudo : VLD1QDUPPseudo<v4i32, load>;
1154 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1155 (VLD1DUPd32 addrmode6:$addr)>;
1156 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1157 (VLD1DUPq32Pseudo addrmode6:$addr)>;
1159 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1161 class VLD1QDUP<bits<4> op7_4, string Dt>
1162 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListTwoDAllLanes:$Vd),
1163 (ins addrmode6dup:$Rn), IIC_VLD1dup,
1164 "vld1", Dt, "$Vd, $Rn", "", []> {
1166 let Inst{4} = Rn{4};
1167 let DecoderMethod = "DecodeVLD1DupInstruction";
1170 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8">;
1171 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16">;
1172 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32">;
1174 // ...with address register writeback:
1175 multiclass VLD1DUPWB<bits<4> op7_4, string Dt> {
1176 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1177 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1178 (ins addrmode6dup:$Rn), IIC_VLD1dupu,
1179 "vld1", Dt, "$Vd, $Rn!",
1180 "$Rn.addr = $wb", []> {
1181 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1182 let Inst{4} = Rn{4};
1183 let DecoderMethod = "DecodeVLD1DupInstruction";
1184 let AsmMatchConverter = "cvtVLDwbFixed";
1186 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1187 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1188 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1189 "vld1", Dt, "$Vd, $Rn, $Rm",
1190 "$Rn.addr = $wb", []> {
1191 let Inst{4} = Rn{4};
1192 let DecoderMethod = "DecodeVLD1DupInstruction";
1193 let AsmMatchConverter = "cvtVLDwbRegister";
1196 multiclass VLD1QDUPWB<bits<4> op7_4, string Dt> {
1197 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1198 (outs VecListTwoDAllLanes:$Vd, GPR:$wb),
1199 (ins addrmode6dup:$Rn), IIC_VLD1dupu,
1200 "vld1", Dt, "$Vd, $Rn!",
1201 "$Rn.addr = $wb", []> {
1202 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1203 let Inst{4} = Rn{4};
1204 let DecoderMethod = "DecodeVLD1DupInstruction";
1205 let AsmMatchConverter = "cvtVLDwbFixed";
1207 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1208 (outs VecListTwoDAllLanes:$Vd, GPR:$wb),
1209 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1210 "vld1", Dt, "$Vd, $Rn, $Rm",
1211 "$Rn.addr = $wb", []> {
1212 let Inst{4} = Rn{4};
1213 let DecoderMethod = "DecodeVLD1DupInstruction";
1214 let AsmMatchConverter = "cvtVLDwbRegister";
1218 defm VLD1DUPd8wb : VLD1DUPWB<{0,0,0,0}, "8">;
1219 defm VLD1DUPd16wb : VLD1DUPWB<{0,1,0,?}, "16">;
1220 defm VLD1DUPd32wb : VLD1DUPWB<{1,0,0,?}, "32">;
1222 defm VLD1DUPq8wb : VLD1QDUPWB<{0,0,1,0}, "8">;
1223 defm VLD1DUPq16wb : VLD1QDUPWB<{0,1,1,?}, "16">;
1224 defm VLD1DUPq32wb : VLD1QDUPWB<{1,0,1,?}, "32">;
1226 def VLD1DUPq8PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1dupu>;
1227 def VLD1DUPq16PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1dupu>;
1228 def VLD1DUPq32PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1dupu>;
1229 def VLD1DUPq8PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1dupu>;
1230 def VLD1DUPq16PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1dupu>;
1231 def VLD1DUPq32PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1dupu>;
1233 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
1234 class VLD2DUP<bits<4> op7_4, string Dt, RegisterOperand VdTy>
1235 : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd),
1236 (ins addrmode6dup:$Rn), IIC_VLD2dup,
1237 "vld2", Dt, "$Vd, $Rn", "", []> {
1239 let Inst{4} = Rn{4};
1240 let DecoderMethod = "DecodeVLD2DupInstruction";
1243 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListTwoDAllLanes>;
1244 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListTwoDAllLanes>;
1245 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListTwoDAllLanes>;
1247 def VLD2DUPd8Pseudo : VLDQPseudo<IIC_VLD2dup>;
1248 def VLD2DUPd16Pseudo : VLDQPseudo<IIC_VLD2dup>;
1249 def VLD2DUPd32Pseudo : VLDQPseudo<IIC_VLD2dup>;
1251 // ...with double-spaced registers (not used for codegen):
1252 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListTwoQAllLanes>;
1253 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListTwoQAllLanes>;
1254 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListTwoQAllLanes>;
1256 // ...with address register writeback:
1257 multiclass VLD2DUPWB<bits<4> op7_4, string Dt, RegisterOperand VdTy> {
1258 def _fixed : NLdSt<1, 0b10, 0b1101, op7_4,
1259 (outs VdTy:$Vd, GPR:$wb),
1260 (ins addrmode6dup:$Rn), IIC_VLD2dupu,
1261 "vld2", Dt, "$Vd, $Rn!",
1262 "$Rn.addr = $wb", []> {
1263 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1264 let Inst{4} = Rn{4};
1265 let DecoderMethod = "DecodeVLD2DupInstruction";
1266 let AsmMatchConverter = "cvtVLDwbFixed";
1268 def _register : NLdSt<1, 0b10, 0b1101, op7_4,
1269 (outs VdTy:$Vd, GPR:$wb),
1270 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD2dupu,
1271 "vld2", Dt, "$Vd, $Rn, $Rm",
1272 "$Rn.addr = $wb", []> {
1273 let Inst{4} = Rn{4};
1274 let DecoderMethod = "DecodeVLD2DupInstruction";
1275 let AsmMatchConverter = "cvtVLDwbRegister";
1279 defm VLD2DUPd8wb : VLD2DUPWB<{0,0,0,0}, "8", VecListTwoDAllLanes>;
1280 defm VLD2DUPd16wb : VLD2DUPWB<{0,1,0,?}, "16", VecListTwoDAllLanes>;
1281 defm VLD2DUPd32wb : VLD2DUPWB<{1,0,0,?}, "32", VecListTwoDAllLanes>;
1283 defm VLD2DUPd8x2wb : VLD2DUPWB<{0,0,1,0}, "8", VecListTwoQAllLanes>;
1284 defm VLD2DUPd16x2wb : VLD2DUPWB<{0,1,1,?}, "16", VecListTwoQAllLanes>;
1285 defm VLD2DUPd32x2wb : VLD2DUPWB<{1,0,1,?}, "32", VecListTwoQAllLanes>;
1287 def VLD2DUPd8PseudoWB_fixed : VLDQWBfixedPseudo <IIC_VLD2dupu>;
1288 def VLD2DUPd8PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD2dupu>;
1289 def VLD2DUPd16PseudoWB_fixed : VLDQWBfixedPseudo <IIC_VLD2dupu>;
1290 def VLD2DUPd16PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD2dupu>;
1291 def VLD2DUPd32PseudoWB_fixed : VLDQWBfixedPseudo <IIC_VLD2dupu>;
1292 def VLD2DUPd32PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD2dupu>;
1294 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
1295 class VLD3DUP<bits<4> op7_4, string Dt>
1296 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1297 (ins addrmode6dup:$Rn), IIC_VLD3dup,
1298 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
1301 let DecoderMethod = "DecodeVLD3DupInstruction";
1304 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
1305 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
1306 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
1308 def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1309 def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1310 def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1312 // ...with double-spaced registers (not used for codegen):
1313 def VLD3DUPd8x2 : VLD3DUP<{0,0,1,?}, "8">;
1314 def VLD3DUPd16x2 : VLD3DUP<{0,1,1,?}, "16">;
1315 def VLD3DUPd32x2 : VLD3DUP<{1,0,1,?}, "32">;
1317 // ...with address register writeback:
1318 class VLD3DUPWB<bits<4> op7_4, string Dt>
1319 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1320 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu,
1321 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
1322 "$Rn.addr = $wb", []> {
1324 let DecoderMethod = "DecodeVLD3DupInstruction";
1327 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;
1328 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">;
1329 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">;
1331 def VLD3DUPd8x2_UPD : VLD3DUPWB<{0,0,1,0}, "8">;
1332 def VLD3DUPd16x2_UPD : VLD3DUPWB<{0,1,1,?}, "16">;
1333 def VLD3DUPd32x2_UPD : VLD3DUPWB<{1,0,1,?}, "32">;
1335 def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1336 def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1337 def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1339 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1340 class VLD4DUP<bits<4> op7_4, string Dt>
1341 : NLdSt<1, 0b10, 0b1111, op7_4,
1342 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1343 (ins addrmode6dup:$Rn), IIC_VLD4dup,
1344 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
1346 let Inst{4} = Rn{4};
1347 let DecoderMethod = "DecodeVLD4DupInstruction";
1350 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1351 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1352 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1354 def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1355 def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1356 def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1358 // ...with double-spaced registers (not used for codegen):
1359 def VLD4DUPd8x2 : VLD4DUP<{0,0,1,?}, "8">;
1360 def VLD4DUPd16x2 : VLD4DUP<{0,1,1,?}, "16">;
1361 def VLD4DUPd32x2 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1363 // ...with address register writeback:
1364 class VLD4DUPWB<bits<4> op7_4, string Dt>
1365 : NLdSt<1, 0b10, 0b1111, op7_4,
1366 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1367 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
1368 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
1369 "$Rn.addr = $wb", []> {
1370 let Inst{4} = Rn{4};
1371 let DecoderMethod = "DecodeVLD4DupInstruction";
1374 def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">;
1375 def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">;
1376 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1378 def VLD4DUPd8x2_UPD : VLD4DUPWB<{0,0,1,0}, "8">;
1379 def VLD4DUPd16x2_UPD : VLD4DUPWB<{0,1,1,?}, "16">;
1380 def VLD4DUPd32x2_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1382 def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1383 def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1384 def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1386 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1388 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1390 // Classes for VST* pseudo-instructions with multi-register operands.
1391 // These are expanded to real instructions after register allocation.
1392 class VSTQPseudo<InstrItinClass itin>
1393 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1394 class VSTQWBPseudo<InstrItinClass itin>
1395 : PseudoNLdSt<(outs GPR:$wb),
1396 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1397 "$addr.addr = $wb">;
1398 class VSTQWBfixedPseudo<InstrItinClass itin>
1399 : PseudoNLdSt<(outs GPR:$wb),
1400 (ins addrmode6:$addr, QPR:$src), itin,
1401 "$addr.addr = $wb">;
1402 class VSTQWBregisterPseudo<InstrItinClass itin>
1403 : PseudoNLdSt<(outs GPR:$wb),
1404 (ins addrmode6:$addr, rGPR:$offset, QPR:$src), itin,
1405 "$addr.addr = $wb">;
1406 class VSTQQPseudo<InstrItinClass itin>
1407 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
1408 class VSTQQWBPseudo<InstrItinClass itin>
1409 : PseudoNLdSt<(outs GPR:$wb),
1410 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
1411 "$addr.addr = $wb">;
1412 class VSTQQQQPseudo<InstrItinClass itin>
1413 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src), itin, "">;
1414 class VSTQQQQWBPseudo<InstrItinClass itin>
1415 : PseudoNLdSt<(outs GPR:$wb),
1416 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
1417 "$addr.addr = $wb">;
1419 // VST1 : Vector Store (multiple single elements)
1420 class VST1D<bits<4> op7_4, string Dt>
1421 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, VecListOneD:$Vd),
1422 IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []> {
1424 let Inst{4} = Rn{4};
1425 let DecoderMethod = "DecodeVSTInstruction";
1427 class VST1Q<bits<4> op7_4, string Dt>
1428 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$Rn, VecListTwoD:$Vd),
1429 IIC_VST1x2, "vst1", Dt, "$Vd, $Rn", "", []> {
1431 let Inst{5-4} = Rn{5-4};
1432 let DecoderMethod = "DecodeVSTInstruction";
1435 def VST1d8 : VST1D<{0,0,0,?}, "8">;
1436 def VST1d16 : VST1D<{0,1,0,?}, "16">;
1437 def VST1d32 : VST1D<{1,0,0,?}, "32">;
1438 def VST1d64 : VST1D<{1,1,0,?}, "64">;
1440 def VST1q8 : VST1Q<{0,0,?,?}, "8">;
1441 def VST1q16 : VST1Q<{0,1,?,?}, "16">;
1442 def VST1q32 : VST1Q<{1,0,?,?}, "32">;
1443 def VST1q64 : VST1Q<{1,1,?,?}, "64">;
1445 def VST1q8Pseudo : VSTQPseudo<IIC_VST1x2>;
1446 def VST1q16Pseudo : VSTQPseudo<IIC_VST1x2>;
1447 def VST1q32Pseudo : VSTQPseudo<IIC_VST1x2>;
1448 def VST1q64Pseudo : VSTQPseudo<IIC_VST1x2>;
1450 // ...with address register writeback:
1451 multiclass VST1DWB<bits<4> op7_4, string Dt> {
1452 def _fixed : NLdSt<0,0b00, 0b0111,op7_4, (outs GPR:$wb),
1453 (ins addrmode6:$Rn, VecListOneD:$Vd), IIC_VLD1u,
1454 "vst1", Dt, "$Vd, $Rn!",
1455 "$Rn.addr = $wb", []> {
1456 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1457 let Inst{4} = Rn{4};
1458 let DecoderMethod = "DecodeVSTInstruction";
1459 let AsmMatchConverter = "cvtVSTwbFixed";
1461 def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb),
1462 (ins addrmode6:$Rn, rGPR:$Rm, VecListOneD:$Vd),
1464 "vst1", Dt, "$Vd, $Rn, $Rm",
1465 "$Rn.addr = $wb", []> {
1466 let Inst{4} = Rn{4};
1467 let DecoderMethod = "DecodeVSTInstruction";
1468 let AsmMatchConverter = "cvtVSTwbRegister";
1471 multiclass VST1QWB<bits<4> op7_4, string Dt> {
1472 def _fixed : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1473 (ins addrmode6:$Rn, VecListTwoD:$Vd), IIC_VLD1x2u,
1474 "vst1", Dt, "$Vd, $Rn!",
1475 "$Rn.addr = $wb", []> {
1476 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1477 let Inst{5-4} = Rn{5-4};
1478 let DecoderMethod = "DecodeVSTInstruction";
1479 let AsmMatchConverter = "cvtVSTwbFixed";
1481 def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1482 (ins addrmode6:$Rn, rGPR:$Rm, VecListTwoD:$Vd),
1484 "vst1", Dt, "$Vd, $Rn, $Rm",
1485 "$Rn.addr = $wb", []> {
1486 let Inst{5-4} = Rn{5-4};
1487 let DecoderMethod = "DecodeVSTInstruction";
1488 let AsmMatchConverter = "cvtVSTwbRegister";
1492 defm VST1d8wb : VST1DWB<{0,0,0,?}, "8">;
1493 defm VST1d16wb : VST1DWB<{0,1,0,?}, "16">;
1494 defm VST1d32wb : VST1DWB<{1,0,0,?}, "32">;
1495 defm VST1d64wb : VST1DWB<{1,1,0,?}, "64">;
1497 defm VST1q8wb : VST1QWB<{0,0,?,?}, "8">;
1498 defm VST1q16wb : VST1QWB<{0,1,?,?}, "16">;
1499 defm VST1q32wb : VST1QWB<{1,0,?,?}, "32">;
1500 defm VST1q64wb : VST1QWB<{1,1,?,?}, "64">;
1502 def VST1q8PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST1x2u>;
1503 def VST1q16PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST1x2u>;
1504 def VST1q32PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST1x2u>;
1505 def VST1q64PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST1x2u>;
1506 def VST1q8PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>;
1507 def VST1q16PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>;
1508 def VST1q32PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>;
1509 def VST1q64PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>;
1511 // ...with 3 registers
1512 class VST1D3<bits<4> op7_4, string Dt>
1513 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1514 (ins addrmode6:$Rn, VecListThreeD:$Vd),
1515 IIC_VST1x3, "vst1", Dt, "$Vd, $Rn", "", []> {
1517 let Inst{4} = Rn{4};
1518 let DecoderMethod = "DecodeVSTInstruction";
1520 multiclass VST1D3WB<bits<4> op7_4, string Dt> {
1521 def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1522 (ins addrmode6:$Rn, VecListThreeD:$Vd), IIC_VLD1x3u,
1523 "vst1", Dt, "$Vd, $Rn!",
1524 "$Rn.addr = $wb", []> {
1525 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1526 let Inst{5-4} = Rn{5-4};
1527 let DecoderMethod = "DecodeVSTInstruction";
1528 let AsmMatchConverter = "cvtVSTwbFixed";
1530 def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1531 (ins addrmode6:$Rn, rGPR:$Rm, VecListThreeD:$Vd),
1533 "vst1", Dt, "$Vd, $Rn, $Rm",
1534 "$Rn.addr = $wb", []> {
1535 let Inst{5-4} = Rn{5-4};
1536 let DecoderMethod = "DecodeVSTInstruction";
1537 let AsmMatchConverter = "cvtVSTwbRegister";
1541 def VST1d8T : VST1D3<{0,0,0,?}, "8">;
1542 def VST1d16T : VST1D3<{0,1,0,?}, "16">;
1543 def VST1d32T : VST1D3<{1,0,0,?}, "32">;
1544 def VST1d64T : VST1D3<{1,1,0,?}, "64">;
1546 defm VST1d8Twb : VST1D3WB<{0,0,0,?}, "8">;
1547 defm VST1d16Twb : VST1D3WB<{0,1,0,?}, "16">;
1548 defm VST1d32Twb : VST1D3WB<{1,0,0,?}, "32">;
1549 defm VST1d64Twb : VST1D3WB<{1,1,0,?}, "64">;
1551 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
1552 def VST1d64TPseudoWB_fixed : VSTQQWBPseudo<IIC_VST1x3u>;
1553 def VST1d64TPseudoWB_register : VSTQQWBPseudo<IIC_VST1x3u>;
1555 // ...with 4 registers
1556 class VST1D4<bits<4> op7_4, string Dt>
1557 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1558 (ins addrmode6:$Rn, VecListFourD:$Vd),
1559 IIC_VST1x4, "vst1", Dt, "$Vd, $Rn", "",
1562 let Inst{5-4} = Rn{5-4};
1563 let DecoderMethod = "DecodeVSTInstruction";
1565 multiclass VST1D4WB<bits<4> op7_4, string Dt> {
1566 def _fixed : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1567 (ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1x4u,
1568 "vst1", Dt, "$Vd, $Rn!",
1569 "$Rn.addr = $wb", []> {
1570 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1571 let Inst{5-4} = Rn{5-4};
1572 let DecoderMethod = "DecodeVSTInstruction";
1573 let AsmMatchConverter = "cvtVSTwbFixed";
1575 def _register : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1576 (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1578 "vst1", Dt, "$Vd, $Rn, $Rm",
1579 "$Rn.addr = $wb", []> {
1580 let Inst{5-4} = Rn{5-4};
1581 let DecoderMethod = "DecodeVSTInstruction";
1582 let AsmMatchConverter = "cvtVSTwbRegister";
1586 def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
1587 def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
1588 def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
1589 def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
1591 defm VST1d8Qwb : VST1D4WB<{0,0,?,?}, "8">;
1592 defm VST1d16Qwb : VST1D4WB<{0,1,?,?}, "16">;
1593 defm VST1d32Qwb : VST1D4WB<{1,0,?,?}, "32">;
1594 defm VST1d64Qwb : VST1D4WB<{1,1,?,?}, "64">;
1596 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
1597 def VST1d64QPseudoWB_fixed : VSTQQWBPseudo<IIC_VST1x4u>;
1598 def VST1d64QPseudoWB_register : VSTQQWBPseudo<IIC_VST1x4u>;
1600 // VST2 : Vector Store (multiple 2-element structures)
1601 class VST2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
1602 InstrItinClass itin>
1603 : NLdSt<0, 0b00, op11_8, op7_4, (outs), (ins addrmode6:$Rn, VdTy:$Vd),
1604 itin, "vst2", Dt, "$Vd, $Rn", "", []> {
1606 let Inst{5-4} = Rn{5-4};
1607 let DecoderMethod = "DecodeVSTInstruction";
1610 def VST2d8 : VST2<0b1000, {0,0,?,?}, "8", VecListTwoD, IIC_VST2>;
1611 def VST2d16 : VST2<0b1000, {0,1,?,?}, "16", VecListTwoD, IIC_VST2>;
1612 def VST2d32 : VST2<0b1000, {1,0,?,?}, "32", VecListTwoD, IIC_VST2>;
1614 def VST2q8 : VST2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VST2x2>;
1615 def VST2q16 : VST2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VST2x2>;
1616 def VST2q32 : VST2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VST2x2>;
1618 def VST2d8Pseudo : VSTQPseudo<IIC_VST2>;
1619 def VST2d16Pseudo : VSTQPseudo<IIC_VST2>;
1620 def VST2d32Pseudo : VSTQPseudo<IIC_VST2>;
1622 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
1623 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
1624 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
1626 // ...with address register writeback:
1627 multiclass VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt,
1628 RegisterOperand VdTy> {
1629 def _fixed : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1630 (ins addrmode6:$Rn, VdTy:$Vd), IIC_VLD1u,
1631 "vst2", Dt, "$Vd, $Rn!",
1632 "$Rn.addr = $wb", []> {
1633 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1634 let Inst{5-4} = Rn{5-4};
1635 let DecoderMethod = "DecodeVSTInstruction";
1636 let AsmMatchConverter = "cvtVSTwbFixed";
1638 def _register : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1639 (ins addrmode6:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u,
1640 "vst2", Dt, "$Vd, $Rn, $Rm",
1641 "$Rn.addr = $wb", []> {
1642 let Inst{5-4} = Rn{5-4};
1643 let DecoderMethod = "DecodeVSTInstruction";
1644 let AsmMatchConverter = "cvtVSTwbRegister";
1647 multiclass VST2QWB<bits<4> op7_4, string Dt> {
1648 def _fixed : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1649 (ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1u,
1650 "vst2", Dt, "$Vd, $Rn!",
1651 "$Rn.addr = $wb", []> {
1652 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1653 let Inst{5-4} = Rn{5-4};
1654 let DecoderMethod = "DecodeVSTInstruction";
1655 let AsmMatchConverter = "cvtVSTwbFixed";
1657 def _register : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1658 (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1660 "vst2", Dt, "$Vd, $Rn, $Rm",
1661 "$Rn.addr = $wb", []> {
1662 let Inst{5-4} = Rn{5-4};
1663 let DecoderMethod = "DecodeVSTInstruction";
1664 let AsmMatchConverter = "cvtVSTwbRegister";
1668 defm VST2d8wb : VST2DWB<0b1000, {0,0,?,?}, "8", VecListTwoD>;
1669 defm VST2d16wb : VST2DWB<0b1000, {0,1,?,?}, "16", VecListTwoD>;
1670 defm VST2d32wb : VST2DWB<0b1000, {1,0,?,?}, "32", VecListTwoD>;
1672 defm VST2q8wb : VST2QWB<{0,0,?,?}, "8">;
1673 defm VST2q16wb : VST2QWB<{0,1,?,?}, "16">;
1674 defm VST2q32wb : VST2QWB<{1,0,?,?}, "32">;
1676 def VST2d8PseudoWB_fixed : VSTQWBPseudo<IIC_VST2u>;
1677 def VST2d16PseudoWB_fixed : VSTQWBPseudo<IIC_VST2u>;
1678 def VST2d32PseudoWB_fixed : VSTQWBPseudo<IIC_VST2u>;
1679 def VST2d8PseudoWB_register : VSTQWBPseudo<IIC_VST2u>;
1680 def VST2d16PseudoWB_register : VSTQWBPseudo<IIC_VST2u>;
1681 def VST2d32PseudoWB_register : VSTQWBPseudo<IIC_VST2u>;
1683 def VST2q8PseudoWB_fixed : VSTQQWBPseudo<IIC_VST2x2u>;
1684 def VST2q16PseudoWB_fixed : VSTQQWBPseudo<IIC_VST2x2u>;
1685 def VST2q32PseudoWB_fixed : VSTQQWBPseudo<IIC_VST2x2u>;
1686 def VST2q8PseudoWB_register : VSTQQWBPseudo<IIC_VST2x2u>;
1687 def VST2q16PseudoWB_register : VSTQQWBPseudo<IIC_VST2x2u>;
1688 def VST2q32PseudoWB_register : VSTQQWBPseudo<IIC_VST2x2u>;
1690 // ...with double-spaced registers
1691 def VST2b8 : VST2<0b1001, {0,0,?,?}, "8", VecListTwoQ, IIC_VST2>;
1692 def VST2b16 : VST2<0b1001, {0,1,?,?}, "16", VecListTwoQ, IIC_VST2>;
1693 def VST2b32 : VST2<0b1001, {1,0,?,?}, "32", VecListTwoQ, IIC_VST2>;
1694 defm VST2b8wb : VST2DWB<0b1001, {0,0,?,?}, "8", VecListTwoQ>;
1695 defm VST2b16wb : VST2DWB<0b1001, {0,1,?,?}, "16", VecListTwoQ>;
1696 defm VST2b32wb : VST2DWB<0b1001, {1,0,?,?}, "32", VecListTwoQ>;
1698 // VST3 : Vector Store (multiple 3-element structures)
1699 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1700 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1701 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1702 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1704 let Inst{4} = Rn{4};
1705 let DecoderMethod = "DecodeVSTInstruction";
1708 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1709 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1710 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
1712 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1713 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1714 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
1716 // ...with address register writeback:
1717 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1718 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1719 (ins addrmode6:$Rn, am6offset:$Rm,
1720 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1721 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1722 "$Rn.addr = $wb", []> {
1723 let Inst{4} = Rn{4};
1724 let DecoderMethod = "DecodeVSTInstruction";
1727 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1728 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1729 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
1731 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1732 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1733 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1735 // ...with double-spaced registers:
1736 def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1737 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1738 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1739 def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1740 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1741 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
1743 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1744 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1745 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1747 // ...alternate versions to be allocated odd register numbers:
1748 def VST3q8oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1749 def VST3q16oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1750 def VST3q32oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1752 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1753 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1754 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1756 // VST4 : Vector Store (multiple 4-element structures)
1757 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1758 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1759 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1760 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1763 let Inst{5-4} = Rn{5-4};
1764 let DecoderMethod = "DecodeVSTInstruction";
1767 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1768 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1769 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
1771 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1772 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1773 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
1775 // ...with address register writeback:
1776 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1777 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1778 (ins addrmode6:$Rn, am6offset:$Rm,
1779 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1780 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1781 "$Rn.addr = $wb", []> {
1782 let Inst{5-4} = Rn{5-4};
1783 let DecoderMethod = "DecodeVSTInstruction";
1786 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
1787 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
1788 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
1790 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1791 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1792 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1794 // ...with double-spaced registers:
1795 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
1796 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
1797 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
1798 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
1799 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
1800 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
1802 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1803 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1804 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1806 // ...alternate versions to be allocated odd register numbers:
1807 def VST4q8oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1808 def VST4q16oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1809 def VST4q32oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1811 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1812 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1813 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1815 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1817 // Classes for VST*LN pseudo-instructions with multi-register operands.
1818 // These are expanded to real instructions after register allocation.
1819 class VSTQLNPseudo<InstrItinClass itin>
1820 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1822 class VSTQLNWBPseudo<InstrItinClass itin>
1823 : PseudoNLdSt<(outs GPR:$wb),
1824 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1825 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1826 class VSTQQLNPseudo<InstrItinClass itin>
1827 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1829 class VSTQQLNWBPseudo<InstrItinClass itin>
1830 : PseudoNLdSt<(outs GPR:$wb),
1831 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1832 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1833 class VSTQQQQLNPseudo<InstrItinClass itin>
1834 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1836 class VSTQQQQLNWBPseudo<InstrItinClass itin>
1837 : PseudoNLdSt<(outs GPR:$wb),
1838 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1839 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1841 // VST1LN : Vector Store (single element from one lane)
1842 class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1843 PatFrag StoreOp, SDNode ExtractOp>
1844 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1845 (ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane),
1846 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1847 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6:$Rn)]> {
1849 let DecoderMethod = "DecodeVST1LN";
1851 class VST1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1852 PatFrag StoreOp, SDNode ExtractOp>
1853 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1854 (ins addrmode6oneL32:$Rn, DPR:$Vd, nohash_imm:$lane),
1855 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1856 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6oneL32:$Rn)]>{
1858 let DecoderMethod = "DecodeVST1LN";
1860 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1861 : VSTQLNPseudo<IIC_VST1ln> {
1862 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1866 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
1868 let Inst{7-5} = lane{2-0};
1870 def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
1872 let Inst{7-6} = lane{1-0};
1873 let Inst{4} = Rn{5};
1876 def VST1LNd32 : VST1LN32<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt> {
1877 let Inst{7} = lane{0};
1878 let Inst{5-4} = Rn{5-4};
1881 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
1882 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
1883 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
1885 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
1886 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1887 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
1888 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1890 // ...with address register writeback:
1891 class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1892 PatFrag StoreOp, SDNode ExtractOp>
1893 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1894 (ins addrmode6:$Rn, am6offset:$Rm,
1895 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
1896 "\\{$Vd[$lane]\\}, $Rn$Rm",
1898 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
1899 addrmode6:$Rn, am6offset:$Rm))]> {
1900 let DecoderMethod = "DecodeVST1LN";
1902 class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1903 : VSTQLNWBPseudo<IIC_VST1lnu> {
1904 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1905 addrmode6:$addr, am6offset:$offset))];
1908 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8,
1910 let Inst{7-5} = lane{2-0};
1912 def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16", v4i16, post_truncsti16,
1914 let Inst{7-6} = lane{1-0};
1915 let Inst{4} = Rn{5};
1917 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32", v2i32, post_store,
1919 let Inst{7} = lane{0};
1920 let Inst{5-4} = Rn{5-4};
1923 def VST1LNq8Pseudo_UPD : VST1QLNWBPseudo<v16i8, post_truncsti8, NEONvgetlaneu>;
1924 def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,NEONvgetlaneu>;
1925 def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
1927 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1929 // VST2LN : Vector Store (single 2-element structure from one lane)
1930 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1931 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1932 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
1933 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
1936 let Inst{4} = Rn{4};
1937 let DecoderMethod = "DecodeVST2LN";
1940 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
1941 let Inst{7-5} = lane{2-0};
1943 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
1944 let Inst{7-6} = lane{1-0};
1946 def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
1947 let Inst{7} = lane{0};
1950 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1951 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1952 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1954 // ...with double-spaced registers:
1955 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
1956 let Inst{7-6} = lane{1-0};
1957 let Inst{4} = Rn{4};
1959 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
1960 let Inst{7} = lane{0};
1961 let Inst{4} = Rn{4};
1964 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1965 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1967 // ...with address register writeback:
1968 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1969 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1970 (ins addrmode6:$Rn, am6offset:$Rm,
1971 DPR:$Vd, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
1972 "\\{$Vd[$lane], $src2[$lane]\\}, $Rn$Rm",
1973 "$Rn.addr = $wb", []> {
1974 let Inst{4} = Rn{4};
1975 let DecoderMethod = "DecodeVST2LN";
1978 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
1979 let Inst{7-5} = lane{2-0};
1981 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
1982 let Inst{7-6} = lane{1-0};
1984 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
1985 let Inst{7} = lane{0};
1988 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1989 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1990 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1992 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
1993 let Inst{7-6} = lane{1-0};
1995 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
1996 let Inst{7} = lane{0};
1999 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
2000 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
2002 // VST3LN : Vector Store (single 3-element structure from one lane)
2003 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2004 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2005 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
2006 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
2007 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
2009 let DecoderMethod = "DecodeVST3LN";
2012 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
2013 let Inst{7-5} = lane{2-0};
2015 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
2016 let Inst{7-6} = lane{1-0};
2018 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
2019 let Inst{7} = lane{0};
2022 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2023 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2024 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2026 // ...with double-spaced registers:
2027 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
2028 let Inst{7-6} = lane{1-0};
2030 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
2031 let Inst{7} = lane{0};
2034 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
2035 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
2037 // ...with address register writeback:
2038 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2039 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2040 (ins addrmode6:$Rn, am6offset:$Rm,
2041 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
2042 IIC_VST3lnu, "vst3", Dt,
2043 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
2044 "$Rn.addr = $wb", []> {
2045 let DecoderMethod = "DecodeVST3LN";
2048 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
2049 let Inst{7-5} = lane{2-0};
2051 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
2052 let Inst{7-6} = lane{1-0};
2054 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
2055 let Inst{7} = lane{0};
2058 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2059 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2060 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2062 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
2063 let Inst{7-6} = lane{1-0};
2065 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
2066 let Inst{7} = lane{0};
2069 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
2070 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
2072 // VST4LN : Vector Store (single 4-element structure from one lane)
2073 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2074 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2075 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
2076 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
2077 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
2080 let Inst{4} = Rn{4};
2081 let DecoderMethod = "DecodeVST4LN";
2084 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
2085 let Inst{7-5} = lane{2-0};
2087 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
2088 let Inst{7-6} = lane{1-0};
2090 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
2091 let Inst{7} = lane{0};
2092 let Inst{5} = Rn{5};
2095 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2096 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2097 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2099 // ...with double-spaced registers:
2100 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
2101 let Inst{7-6} = lane{1-0};
2103 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
2104 let Inst{7} = lane{0};
2105 let Inst{5} = Rn{5};
2108 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
2109 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
2111 // ...with address register writeback:
2112 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2113 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2114 (ins addrmode6:$Rn, am6offset:$Rm,
2115 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
2116 IIC_VST4lnu, "vst4", Dt,
2117 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
2118 "$Rn.addr = $wb", []> {
2119 let Inst{4} = Rn{4};
2120 let DecoderMethod = "DecodeVST4LN";
2123 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
2124 let Inst{7-5} = lane{2-0};
2126 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
2127 let Inst{7-6} = lane{1-0};
2129 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
2130 let Inst{7} = lane{0};
2131 let Inst{5} = Rn{5};
2134 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2135 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2136 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2138 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
2139 let Inst{7-6} = lane{1-0};
2141 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
2142 let Inst{7} = lane{0};
2143 let Inst{5} = Rn{5};
2146 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
2147 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
2149 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2152 //===----------------------------------------------------------------------===//
2153 // NEON pattern fragments
2154 //===----------------------------------------------------------------------===//
2156 // Extract D sub-registers of Q registers.
2157 def DSubReg_i8_reg : SDNodeXForm<imm, [{
2158 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2159 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
2161 def DSubReg_i16_reg : SDNodeXForm<imm, [{
2162 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2163 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
2165 def DSubReg_i32_reg : SDNodeXForm<imm, [{
2166 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2167 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
2169 def DSubReg_f64_reg : SDNodeXForm<imm, [{
2170 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2171 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
2174 // Extract S sub-registers of Q/D registers.
2175 def SSubReg_f32_reg : SDNodeXForm<imm, [{
2176 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
2177 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
2180 // Translate lane numbers from Q registers to D subregs.
2181 def SubReg_i8_lane : SDNodeXForm<imm, [{
2182 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
2184 def SubReg_i16_lane : SDNodeXForm<imm, [{
2185 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
2187 def SubReg_i32_lane : SDNodeXForm<imm, [{
2188 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
2191 //===----------------------------------------------------------------------===//
2192 // Instruction Classes
2193 //===----------------------------------------------------------------------===//
2195 // Basic 2-register operations: double- and quad-register.
2196 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2197 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
2198 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2199 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2200 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
2201 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
2202 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2203 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
2204 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2205 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2206 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
2207 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
2209 // Basic 2-register intrinsics, both double- and quad-register.
2210 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2211 bits<2> op17_16, bits<5> op11_7, bit op4,
2212 InstrItinClass itin, string OpcodeStr, string Dt,
2213 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2214 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2215 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2216 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2217 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2218 bits<2> op17_16, bits<5> op11_7, bit op4,
2219 InstrItinClass itin, string OpcodeStr, string Dt,
2220 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2221 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2222 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2223 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2225 // Narrow 2-register operations.
2226 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2227 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2228 InstrItinClass itin, string OpcodeStr, string Dt,
2229 ValueType TyD, ValueType TyQ, SDNode OpNode>
2230 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2231 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2232 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
2234 // Narrow 2-register intrinsics.
2235 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2236 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2237 InstrItinClass itin, string OpcodeStr, string Dt,
2238 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
2239 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2240 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2241 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
2243 // Long 2-register operations (currently only used for VMOVL).
2244 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2245 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2246 InstrItinClass itin, string OpcodeStr, string Dt,
2247 ValueType TyQ, ValueType TyD, SDNode OpNode>
2248 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2249 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2250 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
2252 // Long 2-register intrinsics.
2253 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2254 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2255 InstrItinClass itin, string OpcodeStr, string Dt,
2256 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
2257 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2258 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2259 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
2261 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
2262 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
2263 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
2264 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
2265 OpcodeStr, Dt, "$Vd, $Vm",
2266 "$src1 = $Vd, $src2 = $Vm", []>;
2267 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
2268 InstrItinClass itin, string OpcodeStr, string Dt>
2269 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
2270 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
2271 "$src1 = $Vd, $src2 = $Vm", []>;
2273 // Basic 3-register operations: double- and quad-register.
2274 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2275 InstrItinClass itin, string OpcodeStr, string Dt,
2276 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2277 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2278 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2279 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2280 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2281 let isCommutable = Commutable;
2283 // Same as N3VD but no data type.
2284 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2285 InstrItinClass itin, string OpcodeStr,
2286 ValueType ResTy, ValueType OpTy,
2287 SDNode OpNode, bit Commutable>
2288 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
2289 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2290 OpcodeStr, "$Vd, $Vn, $Vm", "",
2291 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
2292 let isCommutable = Commutable;
2295 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
2296 InstrItinClass itin, string OpcodeStr, string Dt,
2297 ValueType Ty, SDNode ShOp>
2298 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2299 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2300 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2302 (Ty (ShOp (Ty DPR:$Vn),
2303 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
2304 let isCommutable = 0;
2306 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
2307 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2308 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2309 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2310 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane","",
2312 (Ty (ShOp (Ty DPR:$Vn),
2313 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2314 let isCommutable = 0;
2317 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2318 InstrItinClass itin, string OpcodeStr, string Dt,
2319 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2320 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2321 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2322 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2323 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2324 let isCommutable = Commutable;
2326 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2327 InstrItinClass itin, string OpcodeStr,
2328 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2329 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
2330 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2331 OpcodeStr, "$Vd, $Vn, $Vm", "",
2332 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
2333 let isCommutable = Commutable;
2335 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
2336 InstrItinClass itin, string OpcodeStr, string Dt,
2337 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2338 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2339 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2340 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2341 [(set (ResTy QPR:$Vd),
2342 (ResTy (ShOp (ResTy QPR:$Vn),
2343 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2345 let isCommutable = 0;
2347 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
2348 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2349 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2350 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2351 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane", "",
2352 [(set (ResTy QPR:$Vd),
2353 (ResTy (ShOp (ResTy QPR:$Vn),
2354 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2356 let isCommutable = 0;
2359 // Basic 3-register intrinsics, both double- and quad-register.
2360 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2361 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2362 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
2363 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2364 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
2365 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2366 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2367 let isCommutable = Commutable;
2369 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2370 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
2371 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2372 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2373 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2375 (Ty (IntOp (Ty DPR:$Vn),
2376 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2378 let isCommutable = 0;
2380 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2381 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
2382 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2383 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2384 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2386 (Ty (IntOp (Ty DPR:$Vn),
2387 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2388 let isCommutable = 0;
2390 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2391 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2392 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2393 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2394 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
2395 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2396 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
2397 let isCommutable = 0;
2400 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2401 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2402 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
2403 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2404 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
2405 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2406 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2407 let isCommutable = Commutable;
2409 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2410 string OpcodeStr, string Dt,
2411 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2412 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2413 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2414 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2415 [(set (ResTy QPR:$Vd),
2416 (ResTy (IntOp (ResTy QPR:$Vn),
2417 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2419 let isCommutable = 0;
2421 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2422 string OpcodeStr, string Dt,
2423 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2424 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2425 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2426 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2427 [(set (ResTy QPR:$Vd),
2428 (ResTy (IntOp (ResTy QPR:$Vn),
2429 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2431 let isCommutable = 0;
2433 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2434 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2435 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2436 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2437 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
2438 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2439 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
2440 let isCommutable = 0;
2443 // Multiply-Add/Sub operations: double- and quad-register.
2444 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2445 InstrItinClass itin, string OpcodeStr, string Dt,
2446 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode>
2447 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2448 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2449 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2450 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2451 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
2453 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2454 string OpcodeStr, string Dt,
2455 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
2456 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2458 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2460 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2462 (Ty (ShOp (Ty DPR:$src1),
2464 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2466 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2467 string OpcodeStr, string Dt,
2468 ValueType Ty, SDNode MulOp, SDNode ShOp>
2469 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2471 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2473 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2475 (Ty (ShOp (Ty DPR:$src1),
2477 (Ty (NEONvduplane (Ty DPR_8:$Vm),
2480 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2481 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
2482 SDPatternOperator MulOp, SDPatternOperator OpNode>
2483 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2484 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2485 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2486 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2487 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
2488 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2489 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2490 SDPatternOperator MulOp, SDPatternOperator ShOp>
2491 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2493 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2495 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2496 [(set (ResTy QPR:$Vd),
2497 (ResTy (ShOp (ResTy QPR:$src1),
2498 (ResTy (MulOp QPR:$Vn,
2499 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2501 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2502 string OpcodeStr, string Dt,
2503 ValueType ResTy, ValueType OpTy,
2504 SDNode MulOp, SDNode ShOp>
2505 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2507 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2509 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2510 [(set (ResTy QPR:$Vd),
2511 (ResTy (ShOp (ResTy QPR:$src1),
2512 (ResTy (MulOp QPR:$Vn,
2513 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2516 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
2517 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2518 InstrItinClass itin, string OpcodeStr, string Dt,
2519 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2520 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2521 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2522 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2523 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2524 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
2525 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2526 InstrItinClass itin, string OpcodeStr, string Dt,
2527 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2528 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2529 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2530 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2531 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2532 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2534 // Neon 3-argument intrinsics, both double- and quad-register.
2535 // The destination register is also used as the first source operand register.
2536 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2537 InstrItinClass itin, string OpcodeStr, string Dt,
2538 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2539 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2540 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2541 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2542 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2543 (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2544 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2545 InstrItinClass itin, string OpcodeStr, string Dt,
2546 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2547 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2548 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2549 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2550 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2551 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2553 // Long Multiply-Add/Sub operations.
2554 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2555 InstrItinClass itin, string OpcodeStr, string Dt,
2556 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2557 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2558 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2559 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2560 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2561 (TyQ (MulOp (TyD DPR:$Vn),
2562 (TyD DPR:$Vm)))))]>;
2563 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2564 InstrItinClass itin, string OpcodeStr, string Dt,
2565 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2566 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2567 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2569 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2571 (OpNode (TyQ QPR:$src1),
2572 (TyQ (MulOp (TyD DPR:$Vn),
2573 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),
2575 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2576 InstrItinClass itin, string OpcodeStr, string Dt,
2577 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2578 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2579 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2581 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2583 (OpNode (TyQ QPR:$src1),
2584 (TyQ (MulOp (TyD DPR:$Vn),
2585 (TyD (NEONvduplane (TyD DPR_8:$Vm),
2588 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
2589 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2590 InstrItinClass itin, string OpcodeStr, string Dt,
2591 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2593 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2594 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2595 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2596 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2597 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2598 (TyD DPR:$Vm)))))))]>;
2600 // Neon Long 3-argument intrinsic. The destination register is
2601 // a quad-register and is also used as the first source operand register.
2602 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2603 InstrItinClass itin, string OpcodeStr, string Dt,
2604 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
2605 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2606 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2607 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2609 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2610 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2611 string OpcodeStr, string Dt,
2612 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2613 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2615 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2617 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2618 [(set (ResTy QPR:$Vd),
2619 (ResTy (IntOp (ResTy QPR:$src1),
2621 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2623 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2624 InstrItinClass itin, string OpcodeStr, string Dt,
2625 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2626 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2628 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2630 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2631 [(set (ResTy QPR:$Vd),
2632 (ResTy (IntOp (ResTy QPR:$src1),
2634 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2637 // Narrowing 3-register intrinsics.
2638 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2639 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
2640 Intrinsic IntOp, bit Commutable>
2641 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2642 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2643 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2644 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2645 let isCommutable = Commutable;
2648 // Long 3-register operations.
2649 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2650 InstrItinClass itin, string OpcodeStr, string Dt,
2651 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
2652 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2653 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2654 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2655 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2656 let isCommutable = Commutable;
2658 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2659 InstrItinClass itin, string OpcodeStr, string Dt,
2660 ValueType TyQ, ValueType TyD, SDNode OpNode>
2661 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2662 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2663 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2665 (TyQ (OpNode (TyD DPR:$Vn),
2666 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
2667 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2668 InstrItinClass itin, string OpcodeStr, string Dt,
2669 ValueType TyQ, ValueType TyD, SDNode OpNode>
2670 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2671 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2672 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2674 (TyQ (OpNode (TyD DPR:$Vn),
2675 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
2677 // Long 3-register operations with explicitly extended operands.
2678 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2679 InstrItinClass itin, string OpcodeStr, string Dt,
2680 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
2682 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2683 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2684 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2685 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
2686 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2687 let isCommutable = Commutable;
2690 // Long 3-register intrinsics with explicit extend (VABDL).
2691 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2692 InstrItinClass itin, string OpcodeStr, string Dt,
2693 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2695 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2696 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2697 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2698 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2699 (TyD DPR:$Vm))))))]> {
2700 let isCommutable = Commutable;
2703 // Long 3-register intrinsics.
2704 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2705 InstrItinClass itin, string OpcodeStr, string Dt,
2706 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
2707 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2708 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2709 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2710 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2711 let isCommutable = Commutable;
2713 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2714 string OpcodeStr, string Dt,
2715 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2716 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2717 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2718 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2719 [(set (ResTy QPR:$Vd),
2720 (ResTy (IntOp (OpTy DPR:$Vn),
2721 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2723 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2724 InstrItinClass itin, string OpcodeStr, string Dt,
2725 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2726 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2727 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2728 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2729 [(set (ResTy QPR:$Vd),
2730 (ResTy (IntOp (OpTy DPR:$Vn),
2731 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2734 // Wide 3-register operations.
2735 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2736 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
2737 SDNode OpNode, SDNode ExtOp, bit Commutable>
2738 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2739 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
2740 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2741 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
2742 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2743 let isCommutable = Commutable;
2746 // Pairwise long 2-register intrinsics, both double- and quad-register.
2747 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2748 bits<2> op17_16, bits<5> op11_7, bit op4,
2749 string OpcodeStr, string Dt,
2750 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2751 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2752 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2753 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2754 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2755 bits<2> op17_16, bits<5> op11_7, bit op4,
2756 string OpcodeStr, string Dt,
2757 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2758 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2759 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2760 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2762 // Pairwise long 2-register accumulate intrinsics,
2763 // both double- and quad-register.
2764 // The destination register is also used as the first source operand register.
2765 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2766 bits<2> op17_16, bits<5> op11_7, bit op4,
2767 string OpcodeStr, string Dt,
2768 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2769 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
2770 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
2771 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2772 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
2773 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2774 bits<2> op17_16, bits<5> op11_7, bit op4,
2775 string OpcodeStr, string Dt,
2776 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2777 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
2778 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
2779 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2780 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
2782 // Shift by immediate,
2783 // both double- and quad-register.
2784 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2785 Format f, InstrItinClass itin, Operand ImmTy,
2786 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2787 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2788 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
2789 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2790 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
2791 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2792 Format f, InstrItinClass itin, Operand ImmTy,
2793 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2794 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2795 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
2796 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2797 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
2799 // Long shift by immediate.
2800 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2801 string OpcodeStr, string Dt,
2802 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode>
2803 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2804 (outs QPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), N2RegVShLFrm,
2805 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2806 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm),
2807 (i32 imm:$SIMM))))]>;
2809 // Narrow shift by immediate.
2810 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2811 InstrItinClass itin, string OpcodeStr, string Dt,
2812 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode>
2813 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2814 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
2815 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2816 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
2817 (i32 imm:$SIMM))))]>;
2819 // Shift right by immediate and accumulate,
2820 // both double- and quad-register.
2821 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2822 Operand ImmTy, string OpcodeStr, string Dt,
2823 ValueType Ty, SDNode ShOp>
2824 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2825 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2826 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2827 [(set DPR:$Vd, (Ty (add DPR:$src1,
2828 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
2829 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2830 Operand ImmTy, string OpcodeStr, string Dt,
2831 ValueType Ty, SDNode ShOp>
2832 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2833 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2834 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2835 [(set QPR:$Vd, (Ty (add QPR:$src1,
2836 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
2838 // Shift by immediate and insert,
2839 // both double- and quad-register.
2840 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2841 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2842 ValueType Ty,SDNode ShOp>
2843 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2844 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiD,
2845 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2846 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
2847 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2848 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2849 ValueType Ty,SDNode ShOp>
2850 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2851 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiQ,
2852 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2853 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
2855 // Convert, with fractional bits immediate,
2856 // both double- and quad-register.
2857 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2858 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2860 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2861 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2862 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2863 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
2864 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2865 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2867 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2868 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2869 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2870 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
2872 //===----------------------------------------------------------------------===//
2874 //===----------------------------------------------------------------------===//
2876 // Abbreviations used in multiclass suffixes:
2877 // Q = quarter int (8 bit) elements
2878 // H = half int (16 bit) elements
2879 // S = single int (32 bit) elements
2880 // D = double int (64 bit) elements
2882 // Neon 2-register vector operations and intrinsics.
2884 // Neon 2-register comparisons.
2885 // source operand element sizes of 8, 16 and 32 bits:
2886 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2887 bits<5> op11_7, bit op4, string opc, string Dt,
2888 string asm, SDNode OpNode> {
2889 // 64-bit vector types.
2890 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
2891 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2892 opc, !strconcat(Dt, "8"), asm, "",
2893 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
2894 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
2895 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2896 opc, !strconcat(Dt, "16"), asm, "",
2897 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>;
2898 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2899 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2900 opc, !strconcat(Dt, "32"), asm, "",
2901 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>;
2902 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2903 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2904 opc, "f32", asm, "",
2905 [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> {
2906 let Inst{10} = 1; // overwrite F = 1
2909 // 128-bit vector types.
2910 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
2911 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2912 opc, !strconcat(Dt, "8"), asm, "",
2913 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
2914 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
2915 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2916 opc, !strconcat(Dt, "16"), asm, "",
2917 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
2918 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2919 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2920 opc, !strconcat(Dt, "32"), asm, "",
2921 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
2922 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2923 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2924 opc, "f32", asm, "",
2925 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
2926 let Inst{10} = 1; // overwrite F = 1
2931 // Neon 2-register vector intrinsics,
2932 // element sizes of 8, 16 and 32 bits:
2933 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2934 bits<5> op11_7, bit op4,
2935 InstrItinClass itinD, InstrItinClass itinQ,
2936 string OpcodeStr, string Dt, Intrinsic IntOp> {
2937 // 64-bit vector types.
2938 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2939 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2940 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2941 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
2942 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2943 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
2945 // 128-bit vector types.
2946 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2947 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
2948 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2949 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
2950 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2951 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
2955 // Neon Narrowing 2-register vector operations,
2956 // source operand element sizes of 16, 32 and 64 bits:
2957 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2958 bits<5> op11_7, bit op6, bit op4,
2959 InstrItinClass itin, string OpcodeStr, string Dt,
2961 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2962 itin, OpcodeStr, !strconcat(Dt, "16"),
2963 v8i8, v8i16, OpNode>;
2964 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2965 itin, OpcodeStr, !strconcat(Dt, "32"),
2966 v4i16, v4i32, OpNode>;
2967 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2968 itin, OpcodeStr, !strconcat(Dt, "64"),
2969 v2i32, v2i64, OpNode>;
2972 // Neon Narrowing 2-register vector intrinsics,
2973 // source operand element sizes of 16, 32 and 64 bits:
2974 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2975 bits<5> op11_7, bit op6, bit op4,
2976 InstrItinClass itin, string OpcodeStr, string Dt,
2978 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2979 itin, OpcodeStr, !strconcat(Dt, "16"),
2980 v8i8, v8i16, IntOp>;
2981 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2982 itin, OpcodeStr, !strconcat(Dt, "32"),
2983 v4i16, v4i32, IntOp>;
2984 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2985 itin, OpcodeStr, !strconcat(Dt, "64"),
2986 v2i32, v2i64, IntOp>;
2990 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
2991 // source operand element sizes of 16, 32 and 64 bits:
2992 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
2993 string OpcodeStr, string Dt, SDNode OpNode> {
2994 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2995 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
2996 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2997 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2998 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2999 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
3003 // Neon 3-register vector operations.
3005 // First with only element sizes of 8, 16 and 32 bits:
3006 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3007 InstrItinClass itinD16, InstrItinClass itinD32,
3008 InstrItinClass itinQ16, InstrItinClass itinQ32,
3009 string OpcodeStr, string Dt,
3010 SDNode OpNode, bit Commutable = 0> {
3011 // 64-bit vector types.
3012 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
3013 OpcodeStr, !strconcat(Dt, "8"),
3014 v8i8, v8i8, OpNode, Commutable>;
3015 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
3016 OpcodeStr, !strconcat(Dt, "16"),
3017 v4i16, v4i16, OpNode, Commutable>;
3018 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
3019 OpcodeStr, !strconcat(Dt, "32"),
3020 v2i32, v2i32, OpNode, Commutable>;
3022 // 128-bit vector types.
3023 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
3024 OpcodeStr, !strconcat(Dt, "8"),
3025 v16i8, v16i8, OpNode, Commutable>;
3026 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
3027 OpcodeStr, !strconcat(Dt, "16"),
3028 v8i16, v8i16, OpNode, Commutable>;
3029 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
3030 OpcodeStr, !strconcat(Dt, "32"),
3031 v4i32, v4i32, OpNode, Commutable>;
3034 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, SDNode ShOp> {
3035 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, "i16", v4i16, ShOp>;
3036 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, "i32", v2i32, ShOp>;
3037 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, "i16", v8i16, v4i16, ShOp>;
3038 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, "i32",
3039 v4i32, v2i32, ShOp>;
3042 // ....then also with element size 64 bits:
3043 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3044 InstrItinClass itinD, InstrItinClass itinQ,
3045 string OpcodeStr, string Dt,
3046 SDNode OpNode, bit Commutable = 0>
3047 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
3048 OpcodeStr, Dt, OpNode, Commutable> {
3049 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
3050 OpcodeStr, !strconcat(Dt, "64"),
3051 v1i64, v1i64, OpNode, Commutable>;
3052 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
3053 OpcodeStr, !strconcat(Dt, "64"),
3054 v2i64, v2i64, OpNode, Commutable>;
3058 // Neon 3-register vector intrinsics.
3060 // First with only element sizes of 16 and 32 bits:
3061 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3062 InstrItinClass itinD16, InstrItinClass itinD32,
3063 InstrItinClass itinQ16, InstrItinClass itinQ32,
3064 string OpcodeStr, string Dt,
3065 Intrinsic IntOp, bit Commutable = 0> {
3066 // 64-bit vector types.
3067 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
3068 OpcodeStr, !strconcat(Dt, "16"),
3069 v4i16, v4i16, IntOp, Commutable>;
3070 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
3071 OpcodeStr, !strconcat(Dt, "32"),
3072 v2i32, v2i32, IntOp, Commutable>;
3074 // 128-bit vector types.
3075 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3076 OpcodeStr, !strconcat(Dt, "16"),
3077 v8i16, v8i16, IntOp, Commutable>;
3078 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3079 OpcodeStr, !strconcat(Dt, "32"),
3080 v4i32, v4i32, IntOp, Commutable>;
3082 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3083 InstrItinClass itinD16, InstrItinClass itinD32,
3084 InstrItinClass itinQ16, InstrItinClass itinQ32,
3085 string OpcodeStr, string Dt,
3087 // 64-bit vector types.
3088 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
3089 OpcodeStr, !strconcat(Dt, "16"),
3090 v4i16, v4i16, IntOp>;
3091 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
3092 OpcodeStr, !strconcat(Dt, "32"),
3093 v2i32, v2i32, IntOp>;
3095 // 128-bit vector types.
3096 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3097 OpcodeStr, !strconcat(Dt, "16"),
3098 v8i16, v8i16, IntOp>;
3099 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3100 OpcodeStr, !strconcat(Dt, "32"),
3101 v4i32, v4i32, IntOp>;
3104 multiclass N3VIntSL_HS<bits<4> op11_8,
3105 InstrItinClass itinD16, InstrItinClass itinD32,
3106 InstrItinClass itinQ16, InstrItinClass itinQ32,
3107 string OpcodeStr, string Dt, Intrinsic IntOp> {
3108 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
3109 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
3110 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
3111 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
3112 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
3113 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
3114 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
3115 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
3118 // ....then also with element size of 8 bits:
3119 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3120 InstrItinClass itinD16, InstrItinClass itinD32,
3121 InstrItinClass itinQ16, InstrItinClass itinQ32,
3122 string OpcodeStr, string Dt,
3123 Intrinsic IntOp, bit Commutable = 0>
3124 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3125 OpcodeStr, Dt, IntOp, Commutable> {
3126 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
3127 OpcodeStr, !strconcat(Dt, "8"),
3128 v8i8, v8i8, IntOp, Commutable>;
3129 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
3130 OpcodeStr, !strconcat(Dt, "8"),
3131 v16i8, v16i8, IntOp, Commutable>;
3133 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3134 InstrItinClass itinD16, InstrItinClass itinD32,
3135 InstrItinClass itinQ16, InstrItinClass itinQ32,
3136 string OpcodeStr, string Dt,
3138 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3139 OpcodeStr, Dt, IntOp> {
3140 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
3141 OpcodeStr, !strconcat(Dt, "8"),
3143 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
3144 OpcodeStr, !strconcat(Dt, "8"),
3145 v16i8, v16i8, IntOp>;
3149 // ....then also with element size of 64 bits:
3150 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3151 InstrItinClass itinD16, InstrItinClass itinD32,
3152 InstrItinClass itinQ16, InstrItinClass itinQ32,
3153 string OpcodeStr, string Dt,
3154 Intrinsic IntOp, bit Commutable = 0>
3155 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3156 OpcodeStr, Dt, IntOp, Commutable> {
3157 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
3158 OpcodeStr, !strconcat(Dt, "64"),
3159 v1i64, v1i64, IntOp, Commutable>;
3160 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3161 OpcodeStr, !strconcat(Dt, "64"),
3162 v2i64, v2i64, IntOp, Commutable>;
3164 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3165 InstrItinClass itinD16, InstrItinClass itinD32,
3166 InstrItinClass itinQ16, InstrItinClass itinQ32,
3167 string OpcodeStr, string Dt,
3169 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3170 OpcodeStr, Dt, IntOp> {
3171 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
3172 OpcodeStr, !strconcat(Dt, "64"),
3173 v1i64, v1i64, IntOp>;
3174 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3175 OpcodeStr, !strconcat(Dt, "64"),
3176 v2i64, v2i64, IntOp>;
3179 // Neon Narrowing 3-register vector intrinsics,
3180 // source operand element sizes of 16, 32 and 64 bits:
3181 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3182 string OpcodeStr, string Dt,
3183 Intrinsic IntOp, bit Commutable = 0> {
3184 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
3185 OpcodeStr, !strconcat(Dt, "16"),
3186 v8i8, v8i16, IntOp, Commutable>;
3187 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
3188 OpcodeStr, !strconcat(Dt, "32"),
3189 v4i16, v4i32, IntOp, Commutable>;
3190 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
3191 OpcodeStr, !strconcat(Dt, "64"),
3192 v2i32, v2i64, IntOp, Commutable>;
3196 // Neon Long 3-register vector operations.
3198 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3199 InstrItinClass itin16, InstrItinClass itin32,
3200 string OpcodeStr, string Dt,
3201 SDNode OpNode, bit Commutable = 0> {
3202 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
3203 OpcodeStr, !strconcat(Dt, "8"),
3204 v8i16, v8i8, OpNode, Commutable>;
3205 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
3206 OpcodeStr, !strconcat(Dt, "16"),
3207 v4i32, v4i16, OpNode, Commutable>;
3208 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
3209 OpcodeStr, !strconcat(Dt, "32"),
3210 v2i64, v2i32, OpNode, Commutable>;
3213 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
3214 InstrItinClass itin, string OpcodeStr, string Dt,
3216 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
3217 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
3218 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
3219 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
3222 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3223 InstrItinClass itin16, InstrItinClass itin32,
3224 string OpcodeStr, string Dt,
3225 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3226 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
3227 OpcodeStr, !strconcat(Dt, "8"),
3228 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3229 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
3230 OpcodeStr, !strconcat(Dt, "16"),
3231 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3232 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
3233 OpcodeStr, !strconcat(Dt, "32"),
3234 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3237 // Neon Long 3-register vector intrinsics.
3239 // First with only element sizes of 16 and 32 bits:
3240 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3241 InstrItinClass itin16, InstrItinClass itin32,
3242 string OpcodeStr, string Dt,
3243 Intrinsic IntOp, bit Commutable = 0> {
3244 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
3245 OpcodeStr, !strconcat(Dt, "16"),
3246 v4i32, v4i16, IntOp, Commutable>;
3247 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
3248 OpcodeStr, !strconcat(Dt, "32"),
3249 v2i64, v2i32, IntOp, Commutable>;
3252 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
3253 InstrItinClass itin, string OpcodeStr, string Dt,
3255 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
3256 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3257 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
3258 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3261 // ....then also with element size of 8 bits:
3262 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3263 InstrItinClass itin16, InstrItinClass itin32,
3264 string OpcodeStr, string Dt,
3265 Intrinsic IntOp, bit Commutable = 0>
3266 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
3267 IntOp, Commutable> {
3268 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
3269 OpcodeStr, !strconcat(Dt, "8"),
3270 v8i16, v8i8, IntOp, Commutable>;
3273 // ....with explicit extend (VABDL).
3274 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3275 InstrItinClass itin, string OpcodeStr, string Dt,
3276 Intrinsic IntOp, SDNode ExtOp, bit Commutable = 0> {
3277 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
3278 OpcodeStr, !strconcat(Dt, "8"),
3279 v8i16, v8i8, IntOp, ExtOp, Commutable>;
3280 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
3281 OpcodeStr, !strconcat(Dt, "16"),
3282 v4i32, v4i16, IntOp, ExtOp, Commutable>;
3283 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
3284 OpcodeStr, !strconcat(Dt, "32"),
3285 v2i64, v2i32, IntOp, ExtOp, Commutable>;
3289 // Neon Wide 3-register vector intrinsics,
3290 // source operand element sizes of 8, 16 and 32 bits:
3291 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3292 string OpcodeStr, string Dt,
3293 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3294 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
3295 OpcodeStr, !strconcat(Dt, "8"),
3296 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3297 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
3298 OpcodeStr, !strconcat(Dt, "16"),
3299 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3300 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
3301 OpcodeStr, !strconcat(Dt, "32"),
3302 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3306 // Neon Multiply-Op vector operations,
3307 // element sizes of 8, 16 and 32 bits:
3308 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3309 InstrItinClass itinD16, InstrItinClass itinD32,
3310 InstrItinClass itinQ16, InstrItinClass itinQ32,
3311 string OpcodeStr, string Dt, SDNode OpNode> {
3312 // 64-bit vector types.
3313 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
3314 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
3315 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
3316 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
3317 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
3318 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
3320 // 128-bit vector types.
3321 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
3322 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
3323 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
3324 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
3325 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
3326 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
3329 multiclass N3VMulOpSL_HS<bits<4> op11_8,
3330 InstrItinClass itinD16, InstrItinClass itinD32,
3331 InstrItinClass itinQ16, InstrItinClass itinQ32,
3332 string OpcodeStr, string Dt, SDNode ShOp> {
3333 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
3334 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
3335 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
3336 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
3337 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
3338 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
3340 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
3341 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
3345 // Neon Intrinsic-Op vector operations,
3346 // element sizes of 8, 16 and 32 bits:
3347 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3348 InstrItinClass itinD, InstrItinClass itinQ,
3349 string OpcodeStr, string Dt, Intrinsic IntOp,
3351 // 64-bit vector types.
3352 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
3353 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
3354 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
3355 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
3356 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
3357 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
3359 // 128-bit vector types.
3360 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
3361 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
3362 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
3363 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
3364 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
3365 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
3368 // Neon 3-argument intrinsics,
3369 // element sizes of 8, 16 and 32 bits:
3370 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3371 InstrItinClass itinD, InstrItinClass itinQ,
3372 string OpcodeStr, string Dt, Intrinsic IntOp> {
3373 // 64-bit vector types.
3374 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
3375 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
3376 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
3377 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
3378 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
3379 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
3381 // 128-bit vector types.
3382 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
3383 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
3384 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
3385 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
3386 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
3387 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
3391 // Neon Long Multiply-Op vector operations,
3392 // element sizes of 8, 16 and 32 bits:
3393 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3394 InstrItinClass itin16, InstrItinClass itin32,
3395 string OpcodeStr, string Dt, SDNode MulOp,
3397 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
3398 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
3399 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
3400 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
3401 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
3402 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3405 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
3406 string Dt, SDNode MulOp, SDNode OpNode> {
3407 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
3408 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
3409 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
3410 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3414 // Neon Long 3-argument intrinsics.
3416 // First with only element sizes of 16 and 32 bits:
3417 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3418 InstrItinClass itin16, InstrItinClass itin32,
3419 string OpcodeStr, string Dt, Intrinsic IntOp> {
3420 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
3421 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3422 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
3423 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3426 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
3427 string OpcodeStr, string Dt, Intrinsic IntOp> {
3428 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
3429 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
3430 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
3431 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3434 // ....then also with element size of 8 bits:
3435 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3436 InstrItinClass itin16, InstrItinClass itin32,
3437 string OpcodeStr, string Dt, Intrinsic IntOp>
3438 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
3439 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
3440 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
3443 // ....with explicit extend (VABAL).
3444 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3445 InstrItinClass itin, string OpcodeStr, string Dt,
3446 Intrinsic IntOp, SDNode ExtOp, SDNode OpNode> {
3447 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
3448 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
3449 IntOp, ExtOp, OpNode>;
3450 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
3451 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
3452 IntOp, ExtOp, OpNode>;
3453 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
3454 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
3455 IntOp, ExtOp, OpNode>;
3459 // Neon Pairwise long 2-register intrinsics,
3460 // element sizes of 8, 16 and 32 bits:
3461 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3462 bits<5> op11_7, bit op4,
3463 string OpcodeStr, string Dt, Intrinsic IntOp> {
3464 // 64-bit vector types.
3465 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3466 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3467 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3468 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3469 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3470 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3472 // 128-bit vector types.
3473 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3474 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3475 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3476 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3477 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3478 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3482 // Neon Pairwise long 2-register accumulate intrinsics,
3483 // element sizes of 8, 16 and 32 bits:
3484 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3485 bits<5> op11_7, bit op4,
3486 string OpcodeStr, string Dt, Intrinsic IntOp> {
3487 // 64-bit vector types.
3488 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3489 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3490 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3491 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3492 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3493 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3495 // 128-bit vector types.
3496 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3497 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3498 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3499 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3500 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3501 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3505 // Neon 2-register vector shift by immediate,
3506 // with f of either N2RegVShLFrm or N2RegVShRFrm
3507 // element sizes of 8, 16, 32 and 64 bits:
3508 multiclass N2VShL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3509 InstrItinClass itin, string OpcodeStr, string Dt,
3511 // 64-bit vector types.
3512 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3513 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3514 let Inst{21-19} = 0b001; // imm6 = 001xxx
3516 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3517 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3518 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3520 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3521 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3522 let Inst{21} = 0b1; // imm6 = 1xxxxx
3524 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3525 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3528 // 128-bit vector types.
3529 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3530 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3531 let Inst{21-19} = 0b001; // imm6 = 001xxx
3533 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3534 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3535 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3537 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3538 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3539 let Inst{21} = 0b1; // imm6 = 1xxxxx
3541 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3542 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3545 multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3546 InstrItinClass itin, string OpcodeStr, string Dt,
3548 // 64-bit vector types.
3549 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3550 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3551 let Inst{21-19} = 0b001; // imm6 = 001xxx
3553 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3554 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3555 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3557 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3558 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3559 let Inst{21} = 0b1; // imm6 = 1xxxxx
3561 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3562 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3565 // 128-bit vector types.
3566 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3567 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3568 let Inst{21-19} = 0b001; // imm6 = 001xxx
3570 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3571 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3572 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3574 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3575 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3576 let Inst{21} = 0b1; // imm6 = 1xxxxx
3578 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3579 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3583 // Neon Shift-Accumulate vector operations,
3584 // element sizes of 8, 16, 32 and 64 bits:
3585 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3586 string OpcodeStr, string Dt, SDNode ShOp> {
3587 // 64-bit vector types.
3588 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3589 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
3590 let Inst{21-19} = 0b001; // imm6 = 001xxx
3592 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3593 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
3594 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3596 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3597 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
3598 let Inst{21} = 0b1; // imm6 = 1xxxxx
3600 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3601 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
3604 // 128-bit vector types.
3605 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3606 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
3607 let Inst{21-19} = 0b001; // imm6 = 001xxx
3609 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3610 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
3611 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3613 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3614 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
3615 let Inst{21} = 0b1; // imm6 = 1xxxxx
3617 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3618 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
3622 // Neon Shift-Insert vector operations,
3623 // with f of either N2RegVShLFrm or N2RegVShRFrm
3624 // element sizes of 8, 16, 32 and 64 bits:
3625 multiclass N2VShInsL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3627 // 64-bit vector types.
3628 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3629 N2RegVShLFrm, OpcodeStr, "8", v8i8, NEONvsli> {
3630 let Inst{21-19} = 0b001; // imm6 = 001xxx
3632 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3633 N2RegVShLFrm, OpcodeStr, "16", v4i16, NEONvsli> {
3634 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3636 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3637 N2RegVShLFrm, OpcodeStr, "32", v2i32, NEONvsli> {
3638 let Inst{21} = 0b1; // imm6 = 1xxxxx
3640 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, i32imm,
3641 N2RegVShLFrm, OpcodeStr, "64", v1i64, NEONvsli>;
3644 // 128-bit vector types.
3645 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3646 N2RegVShLFrm, OpcodeStr, "8", v16i8, NEONvsli> {
3647 let Inst{21-19} = 0b001; // imm6 = 001xxx
3649 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3650 N2RegVShLFrm, OpcodeStr, "16", v8i16, NEONvsli> {
3651 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3653 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3654 N2RegVShLFrm, OpcodeStr, "32", v4i32, NEONvsli> {
3655 let Inst{21} = 0b1; // imm6 = 1xxxxx
3657 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, i32imm,
3658 N2RegVShLFrm, OpcodeStr, "64", v2i64, NEONvsli>;
3661 multiclass N2VShInsR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3663 // 64-bit vector types.
3664 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3665 N2RegVShRFrm, OpcodeStr, "8", v8i8, NEONvsri> {
3666 let Inst{21-19} = 0b001; // imm6 = 001xxx
3668 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3669 N2RegVShRFrm, OpcodeStr, "16", v4i16, NEONvsri> {
3670 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3672 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3673 N2RegVShRFrm, OpcodeStr, "32", v2i32, NEONvsri> {
3674 let Inst{21} = 0b1; // imm6 = 1xxxxx
3676 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3677 N2RegVShRFrm, OpcodeStr, "64", v1i64, NEONvsri>;
3680 // 128-bit vector types.
3681 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3682 N2RegVShRFrm, OpcodeStr, "8", v16i8, NEONvsri> {
3683 let Inst{21-19} = 0b001; // imm6 = 001xxx
3685 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3686 N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsri> {
3687 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3689 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3690 N2RegVShRFrm, OpcodeStr, "32", v4i32, NEONvsri> {
3691 let Inst{21} = 0b1; // imm6 = 1xxxxx
3693 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3694 N2RegVShRFrm, OpcodeStr, "64", v2i64, NEONvsri>;
3698 // Neon Shift Long operations,
3699 // element sizes of 8, 16, 32 bits:
3700 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3701 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
3702 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3703 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, imm1_7, OpNode> {
3704 let Inst{21-19} = 0b001; // imm6 = 001xxx
3706 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3707 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, imm1_15, OpNode> {
3708 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3710 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3711 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, imm1_31, OpNode> {
3712 let Inst{21} = 0b1; // imm6 = 1xxxxx
3716 // Neon Shift Narrow operations,
3717 // element sizes of 16, 32, 64 bits:
3718 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3719 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
3721 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3722 OpcodeStr, !strconcat(Dt, "16"),
3723 v8i8, v8i16, shr_imm8, OpNode> {
3724 let Inst{21-19} = 0b001; // imm6 = 001xxx
3726 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3727 OpcodeStr, !strconcat(Dt, "32"),
3728 v4i16, v4i32, shr_imm16, OpNode> {
3729 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3731 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3732 OpcodeStr, !strconcat(Dt, "64"),
3733 v2i32, v2i64, shr_imm32, OpNode> {
3734 let Inst{21} = 0b1; // imm6 = 1xxxxx
3738 //===----------------------------------------------------------------------===//
3739 // Instruction Definitions.
3740 //===----------------------------------------------------------------------===//
3742 // Vector Add Operations.
3744 // VADD : Vector Add (integer and floating-point)
3745 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
3747 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
3748 v2f32, v2f32, fadd, 1>;
3749 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
3750 v4f32, v4f32, fadd, 1>;
3751 // VADDL : Vector Add Long (Q = D + D)
3752 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3753 "vaddl", "s", add, sext, 1>;
3754 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3755 "vaddl", "u", add, zext, 1>;
3756 // VADDW : Vector Add Wide (Q = Q + D)
3757 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
3758 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
3759 // VHADD : Vector Halving Add
3760 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
3761 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3762 "vhadd", "s", int_arm_neon_vhadds, 1>;
3763 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
3764 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3765 "vhadd", "u", int_arm_neon_vhaddu, 1>;
3766 // VRHADD : Vector Rounding Halving Add
3767 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
3768 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3769 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
3770 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
3771 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3772 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
3773 // VQADD : Vector Saturating Add
3774 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
3775 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3776 "vqadd", "s", int_arm_neon_vqadds, 1>;
3777 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
3778 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3779 "vqadd", "u", int_arm_neon_vqaddu, 1>;
3780 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
3781 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
3782 int_arm_neon_vaddhn, 1>;
3783 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
3784 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
3785 int_arm_neon_vraddhn, 1>;
3787 // Vector Multiply Operations.
3789 // VMUL : Vector Multiply (integer, polynomial and floating-point)
3790 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
3791 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
3792 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
3793 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
3794 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
3795 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
3796 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
3797 v2f32, v2f32, fmul, 1>;
3798 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
3799 v4f32, v4f32, fmul, 1>;
3800 defm VMULsl : N3VSL_HS<0b1000, "vmul", mul>;
3801 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
3802 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
3805 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
3806 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
3807 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
3808 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3809 (DSubReg_i16_reg imm:$lane))),
3810 (SubReg_i16_lane imm:$lane)))>;
3811 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
3812 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
3813 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
3814 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3815 (DSubReg_i32_reg imm:$lane))),
3816 (SubReg_i32_lane imm:$lane)))>;
3817 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
3818 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
3819 (v4f32 (VMULslfq (v4f32 QPR:$src1),
3820 (v2f32 (EXTRACT_SUBREG QPR:$src2,
3821 (DSubReg_i32_reg imm:$lane))),
3822 (SubReg_i32_lane imm:$lane)))>;
3824 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
3825 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
3826 IIC_VMULi16Q, IIC_VMULi32Q,
3827 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
3828 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
3829 IIC_VMULi16Q, IIC_VMULi32Q,
3830 "vqdmulh", "s", int_arm_neon_vqdmulh>;
3831 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
3832 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3834 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
3835 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3836 (DSubReg_i16_reg imm:$lane))),
3837 (SubReg_i16_lane imm:$lane)))>;
3838 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
3839 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3841 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
3842 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3843 (DSubReg_i32_reg imm:$lane))),
3844 (SubReg_i32_lane imm:$lane)))>;
3846 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
3847 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
3848 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
3849 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
3850 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
3851 IIC_VMULi16Q, IIC_VMULi32Q,
3852 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
3853 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
3854 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3856 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
3857 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3858 (DSubReg_i16_reg imm:$lane))),
3859 (SubReg_i16_lane imm:$lane)))>;
3860 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
3861 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3863 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
3864 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3865 (DSubReg_i32_reg imm:$lane))),
3866 (SubReg_i32_lane imm:$lane)))>;
3868 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
3869 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3870 "vmull", "s", NEONvmulls, 1>;
3871 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3872 "vmull", "u", NEONvmullu, 1>;
3873 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
3874 v8i16, v8i8, int_arm_neon_vmullp, 1>;
3875 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
3876 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
3878 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
3879 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
3880 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
3881 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
3882 "vqdmull", "s", int_arm_neon_vqdmull>;
3884 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
3886 // VMLA : Vector Multiply Accumulate (integer and floating-point)
3887 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3888 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3889 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
3890 v2f32, fmul_su, fadd_mlx>,
3891 Requires<[HasNEON, UseFPVMLx]>;
3892 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
3893 v4f32, fmul_su, fadd_mlx>,
3894 Requires<[HasNEON, UseFPVMLx]>;
3895 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
3896 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3897 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
3898 v2f32, fmul_su, fadd_mlx>,
3899 Requires<[HasNEON, UseFPVMLx]>;
3900 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
3901 v4f32, v2f32, fmul_su, fadd_mlx>,
3902 Requires<[HasNEON, UseFPVMLx]>;
3904 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
3905 (mul (v8i16 QPR:$src2),
3906 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3907 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3908 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3909 (DSubReg_i16_reg imm:$lane))),
3910 (SubReg_i16_lane imm:$lane)))>;
3912 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
3913 (mul (v4i32 QPR:$src2),
3914 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3915 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3916 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3917 (DSubReg_i32_reg imm:$lane))),
3918 (SubReg_i32_lane imm:$lane)))>;
3920 def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1),
3921 (fmul_su (v4f32 QPR:$src2),
3922 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3923 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
3925 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3926 (DSubReg_i32_reg imm:$lane))),
3927 (SubReg_i32_lane imm:$lane)))>,
3928 Requires<[HasNEON, UseFPVMLx]>;
3930 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
3931 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3932 "vmlal", "s", NEONvmulls, add>;
3933 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3934 "vmlal", "u", NEONvmullu, add>;
3936 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
3937 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
3939 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
3940 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3941 "vqdmlal", "s", int_arm_neon_vqdmlal>;
3942 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
3944 // VMLS : Vector Multiply Subtract (integer and floating-point)
3945 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3946 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3947 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
3948 v2f32, fmul_su, fsub_mlx>,
3949 Requires<[HasNEON, UseFPVMLx]>;
3950 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
3951 v4f32, fmul_su, fsub_mlx>,
3952 Requires<[HasNEON, UseFPVMLx]>;
3953 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
3954 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3955 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
3956 v2f32, fmul_su, fsub_mlx>,
3957 Requires<[HasNEON, UseFPVMLx]>;
3958 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
3959 v4f32, v2f32, fmul_su, fsub_mlx>,
3960 Requires<[HasNEON, UseFPVMLx]>;
3962 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
3963 (mul (v8i16 QPR:$src2),
3964 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3965 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3966 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3967 (DSubReg_i16_reg imm:$lane))),
3968 (SubReg_i16_lane imm:$lane)))>;
3970 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
3971 (mul (v4i32 QPR:$src2),
3972 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3973 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3974 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3975 (DSubReg_i32_reg imm:$lane))),
3976 (SubReg_i32_lane imm:$lane)))>;
3978 def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1),
3979 (fmul_su (v4f32 QPR:$src2),
3980 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3981 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
3982 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3983 (DSubReg_i32_reg imm:$lane))),
3984 (SubReg_i32_lane imm:$lane)))>,
3985 Requires<[HasNEON, UseFPVMLx]>;
3987 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
3988 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3989 "vmlsl", "s", NEONvmulls, sub>;
3990 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3991 "vmlsl", "u", NEONvmullu, sub>;
3993 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
3994 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
3996 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
3997 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
3998 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3999 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
4001 // Vector Subtract Operations.
4003 // VSUB : Vector Subtract (integer and floating-point)
4004 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
4005 "vsub", "i", sub, 0>;
4006 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
4007 v2f32, v2f32, fsub, 0>;
4008 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
4009 v4f32, v4f32, fsub, 0>;
4010 // VSUBL : Vector Subtract Long (Q = D - D)
4011 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
4012 "vsubl", "s", sub, sext, 0>;
4013 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
4014 "vsubl", "u", sub, zext, 0>;
4015 // VSUBW : Vector Subtract Wide (Q = Q - D)
4016 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
4017 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
4018 // VHSUB : Vector Halving Subtract
4019 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
4020 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4021 "vhsub", "s", int_arm_neon_vhsubs, 0>;
4022 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
4023 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4024 "vhsub", "u", int_arm_neon_vhsubu, 0>;
4025 // VQSUB : Vector Saturing Subtract
4026 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
4027 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4028 "vqsub", "s", int_arm_neon_vqsubs, 0>;
4029 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
4030 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4031 "vqsub", "u", int_arm_neon_vqsubu, 0>;
4032 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
4033 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
4034 int_arm_neon_vsubhn, 0>;
4035 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
4036 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
4037 int_arm_neon_vrsubhn, 0>;
4039 // Vector Comparisons.
4041 // VCEQ : Vector Compare Equal
4042 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4043 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
4044 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
4046 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
4049 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
4050 "$Vd, $Vm, #0", NEONvceqz>;
4052 // VCGE : Vector Compare Greater Than or Equal
4053 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4054 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
4055 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4056 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
4057 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
4059 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
4062 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
4063 "$Vd, $Vm, #0", NEONvcgez>;
4064 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
4065 "$Vd, $Vm, #0", NEONvclez>;
4067 // VCGT : Vector Compare Greater Than
4068 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4069 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
4070 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4071 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
4072 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
4074 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
4077 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
4078 "$Vd, $Vm, #0", NEONvcgtz>;
4079 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
4080 "$Vd, $Vm, #0", NEONvcltz>;
4082 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
4083 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
4084 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
4085 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
4086 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
4087 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
4088 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
4089 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
4090 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
4091 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
4092 // VTST : Vector Test Bits
4093 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
4094 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
4096 // Vector Bitwise Operations.
4098 def vnotd : PatFrag<(ops node:$in),
4099 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
4100 def vnotq : PatFrag<(ops node:$in),
4101 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
4104 // VAND : Vector Bitwise AND
4105 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
4106 v2i32, v2i32, and, 1>;
4107 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
4108 v4i32, v4i32, and, 1>;
4110 // VEOR : Vector Bitwise Exclusive OR
4111 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
4112 v2i32, v2i32, xor, 1>;
4113 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
4114 v4i32, v4i32, xor, 1>;
4116 // VORR : Vector Bitwise OR
4117 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
4118 v2i32, v2i32, or, 1>;
4119 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
4120 v4i32, v4i32, or, 1>;
4122 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
4123 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4125 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4127 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4128 let Inst{9} = SIMM{9};
4131 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
4132 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4134 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4136 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4137 let Inst{10-9} = SIMM{10-9};
4140 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
4141 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4143 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4145 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4146 let Inst{9} = SIMM{9};
4149 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
4150 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4152 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4154 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4155 let Inst{10-9} = SIMM{10-9};
4159 // VBIC : Vector Bitwise Bit Clear (AND NOT)
4160 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4161 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
4162 "vbic", "$Vd, $Vn, $Vm", "",
4163 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
4164 (vnotd DPR:$Vm))))]>;
4165 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4166 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4167 "vbic", "$Vd, $Vn, $Vm", "",
4168 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
4169 (vnotq QPR:$Vm))))]>;
4171 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
4172 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4174 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4176 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4177 let Inst{9} = SIMM{9};
4180 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
4181 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4183 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4185 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4186 let Inst{10-9} = SIMM{10-9};
4189 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
4190 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4192 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4194 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4195 let Inst{9} = SIMM{9};
4198 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
4199 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4201 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4203 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4204 let Inst{10-9} = SIMM{10-9};
4207 // VORN : Vector Bitwise OR NOT
4208 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
4209 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
4210 "vorn", "$Vd, $Vn, $Vm", "",
4211 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
4212 (vnotd DPR:$Vm))))]>;
4213 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
4214 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4215 "vorn", "$Vd, $Vn, $Vm", "",
4216 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
4217 (vnotq QPR:$Vm))))]>;
4219 // VMVN : Vector Bitwise NOT (Immediate)
4221 let isReMaterializable = 1 in {
4223 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
4224 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4225 "vmvn", "i16", "$Vd, $SIMM", "",
4226 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
4227 let Inst{9} = SIMM{9};
4230 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
4231 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4232 "vmvn", "i16", "$Vd, $SIMM", "",
4233 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
4234 let Inst{9} = SIMM{9};
4237 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
4238 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4239 "vmvn", "i32", "$Vd, $SIMM", "",
4240 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
4241 let Inst{11-8} = SIMM{11-8};
4244 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
4245 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4246 "vmvn", "i32", "$Vd, $SIMM", "",
4247 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
4248 let Inst{11-8} = SIMM{11-8};
4252 // VMVN : Vector Bitwise NOT
4253 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
4254 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
4255 "vmvn", "$Vd, $Vm", "",
4256 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
4257 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
4258 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
4259 "vmvn", "$Vd, $Vm", "",
4260 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
4261 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
4262 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
4264 // VBSL : Vector Bitwise Select
4265 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4266 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4267 N3RegFrm, IIC_VCNTiD,
4268 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4270 (v2i32 (NEONvbsl DPR:$src1, DPR:$Vn, DPR:$Vm)))]>;
4272 def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
4273 (and DPR:$Vm, (vnotd DPR:$Vd)))),
4274 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>;
4276 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4277 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4278 N3RegFrm, IIC_VCNTiQ,
4279 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4281 (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>;
4283 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
4284 (and QPR:$Vm, (vnotq QPR:$Vd)))),
4285 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
4287 // VBIF : Vector Bitwise Insert if False
4288 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
4289 // FIXME: This instruction's encoding MAY NOT BE correct.
4290 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
4291 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4292 N3RegFrm, IIC_VBINiD,
4293 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4295 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
4296 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4297 N3RegFrm, IIC_VBINiQ,
4298 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4301 // VBIT : Vector Bitwise Insert if True
4302 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
4303 // FIXME: This instruction's encoding MAY NOT BE correct.
4304 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
4305 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4306 N3RegFrm, IIC_VBINiD,
4307 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4309 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
4310 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4311 N3RegFrm, IIC_VBINiQ,
4312 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4315 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
4316 // for equivalent operations with different register constraints; it just
4319 // Vector Absolute Differences.
4321 // VABD : Vector Absolute Difference
4322 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
4323 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4324 "vabd", "s", int_arm_neon_vabds, 1>;
4325 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
4326 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4327 "vabd", "u", int_arm_neon_vabdu, 1>;
4328 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
4329 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
4330 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
4331 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
4333 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
4334 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
4335 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
4336 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
4337 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
4339 // VABA : Vector Absolute Difference and Accumulate
4340 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4341 "vaba", "s", int_arm_neon_vabds, add>;
4342 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4343 "vaba", "u", int_arm_neon_vabdu, add>;
4345 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
4346 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
4347 "vabal", "s", int_arm_neon_vabds, zext, add>;
4348 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
4349 "vabal", "u", int_arm_neon_vabdu, zext, add>;
4351 // Vector Maximum and Minimum.
4353 // VMAX : Vector Maximum
4354 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
4355 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4356 "vmax", "s", int_arm_neon_vmaxs, 1>;
4357 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
4358 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4359 "vmax", "u", int_arm_neon_vmaxu, 1>;
4360 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
4362 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
4363 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4365 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
4367 // VMIN : Vector Minimum
4368 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
4369 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4370 "vmin", "s", int_arm_neon_vmins, 1>;
4371 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
4372 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4373 "vmin", "u", int_arm_neon_vminu, 1>;
4374 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
4376 v2f32, v2f32, int_arm_neon_vmins, 1>;
4377 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4379 v4f32, v4f32, int_arm_neon_vmins, 1>;
4381 // Vector Pairwise Operations.
4383 // VPADD : Vector Pairwise Add
4384 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4386 v8i8, v8i8, int_arm_neon_vpadd, 0>;
4387 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4389 v4i16, v4i16, int_arm_neon_vpadd, 0>;
4390 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4392 v2i32, v2i32, int_arm_neon_vpadd, 0>;
4393 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
4394 IIC_VPBIND, "vpadd", "f32",
4395 v2f32, v2f32, int_arm_neon_vpadd, 0>;
4397 // VPADDL : Vector Pairwise Add Long
4398 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
4399 int_arm_neon_vpaddls>;
4400 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
4401 int_arm_neon_vpaddlu>;
4403 // VPADAL : Vector Pairwise Add and Accumulate Long
4404 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
4405 int_arm_neon_vpadals>;
4406 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
4407 int_arm_neon_vpadalu>;
4409 // VPMAX : Vector Pairwise Maximum
4410 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4411 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
4412 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4413 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
4414 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4415 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
4416 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4417 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
4418 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4419 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
4420 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4421 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
4422 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
4423 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
4425 // VPMIN : Vector Pairwise Minimum
4426 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4427 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
4428 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4429 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
4430 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4431 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
4432 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4433 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
4434 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4435 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
4436 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4437 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
4438 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
4439 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
4441 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
4443 // VRECPE : Vector Reciprocal Estimate
4444 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4445 IIC_VUNAD, "vrecpe", "u32",
4446 v2i32, v2i32, int_arm_neon_vrecpe>;
4447 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4448 IIC_VUNAQ, "vrecpe", "u32",
4449 v4i32, v4i32, int_arm_neon_vrecpe>;
4450 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4451 IIC_VUNAD, "vrecpe", "f32",
4452 v2f32, v2f32, int_arm_neon_vrecpe>;
4453 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4454 IIC_VUNAQ, "vrecpe", "f32",
4455 v4f32, v4f32, int_arm_neon_vrecpe>;
4457 // VRECPS : Vector Reciprocal Step
4458 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4459 IIC_VRECSD, "vrecps", "f32",
4460 v2f32, v2f32, int_arm_neon_vrecps, 1>;
4461 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4462 IIC_VRECSQ, "vrecps", "f32",
4463 v4f32, v4f32, int_arm_neon_vrecps, 1>;
4465 // VRSQRTE : Vector Reciprocal Square Root Estimate
4466 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4467 IIC_VUNAD, "vrsqrte", "u32",
4468 v2i32, v2i32, int_arm_neon_vrsqrte>;
4469 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4470 IIC_VUNAQ, "vrsqrte", "u32",
4471 v4i32, v4i32, int_arm_neon_vrsqrte>;
4472 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4473 IIC_VUNAD, "vrsqrte", "f32",
4474 v2f32, v2f32, int_arm_neon_vrsqrte>;
4475 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4476 IIC_VUNAQ, "vrsqrte", "f32",
4477 v4f32, v4f32, int_arm_neon_vrsqrte>;
4479 // VRSQRTS : Vector Reciprocal Square Root Step
4480 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4481 IIC_VRECSD, "vrsqrts", "f32",
4482 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
4483 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4484 IIC_VRECSQ, "vrsqrts", "f32",
4485 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
4489 // VSHL : Vector Shift
4490 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
4491 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4492 "vshl", "s", int_arm_neon_vshifts>;
4493 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
4494 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4495 "vshl", "u", int_arm_neon_vshiftu>;
4497 // VSHL : Vector Shift Left (Immediate)
4498 defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
4500 // VSHR : Vector Shift Right (Immediate)
4501 defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s",NEONvshrs>;
4502 defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u",NEONvshru>;
4504 // VSHLL : Vector Shift Left Long
4505 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
4506 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
4508 // VSHLL : Vector Shift Left Long (with maximum shift count)
4509 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
4510 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
4511 ValueType OpTy, Operand ImmTy, SDNode OpNode>
4512 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
4513 ResTy, OpTy, ImmTy, OpNode> {
4514 let Inst{21-16} = op21_16;
4515 let DecoderMethod = "DecodeVSHLMaxInstruction";
4517 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
4518 v8i16, v8i8, imm8, NEONvshlli>;
4519 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
4520 v4i32, v4i16, imm16, NEONvshlli>;
4521 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
4522 v2i64, v2i32, imm32, NEONvshlli>;
4524 // VSHRN : Vector Shift Right and Narrow
4525 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
4528 // VRSHL : Vector Rounding Shift
4529 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
4530 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4531 "vrshl", "s", int_arm_neon_vrshifts>;
4532 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
4533 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4534 "vrshl", "u", int_arm_neon_vrshiftu>;
4535 // VRSHR : Vector Rounding Shift Right
4536 defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s",NEONvrshrs>;
4537 defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u",NEONvrshru>;
4539 // VRSHRN : Vector Rounding Shift Right and Narrow
4540 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
4543 // VQSHL : Vector Saturating Shift
4544 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
4545 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4546 "vqshl", "s", int_arm_neon_vqshifts>;
4547 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
4548 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4549 "vqshl", "u", int_arm_neon_vqshiftu>;
4550 // VQSHL : Vector Saturating Shift Left (Immediate)
4551 defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls>;
4552 defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu>;
4554 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
4555 defm VQSHLsu : N2VShL_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu>;
4557 // VQSHRN : Vector Saturating Shift Right and Narrow
4558 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
4560 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
4563 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
4564 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
4567 // VQRSHL : Vector Saturating Rounding Shift
4568 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
4569 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4570 "vqrshl", "s", int_arm_neon_vqrshifts>;
4571 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
4572 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4573 "vqrshl", "u", int_arm_neon_vqrshiftu>;
4575 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
4576 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
4578 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
4581 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
4582 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
4585 // VSRA : Vector Shift Right and Accumulate
4586 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
4587 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
4588 // VRSRA : Vector Rounding Shift Right and Accumulate
4589 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
4590 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
4592 // VSLI : Vector Shift Left and Insert
4593 defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">;
4595 // VSRI : Vector Shift Right and Insert
4596 defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;
4598 // Vector Absolute and Saturating Absolute.
4600 // VABS : Vector Absolute Value
4601 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
4602 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
4604 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4605 IIC_VUNAD, "vabs", "f32",
4606 v2f32, v2f32, int_arm_neon_vabs>;
4607 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4608 IIC_VUNAQ, "vabs", "f32",
4609 v4f32, v4f32, int_arm_neon_vabs>;
4611 // VQABS : Vector Saturating Absolute Value
4612 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
4613 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
4614 int_arm_neon_vqabs>;
4618 def vnegd : PatFrag<(ops node:$in),
4619 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
4620 def vnegq : PatFrag<(ops node:$in),
4621 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
4623 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4624 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
4625 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
4626 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
4627 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4628 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
4629 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
4630 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
4632 // VNEG : Vector Negate (integer)
4633 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
4634 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
4635 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
4636 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
4637 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
4638 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
4640 // VNEG : Vector Negate (floating-point)
4641 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
4642 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
4643 "vneg", "f32", "$Vd, $Vm", "",
4644 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
4645 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
4646 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
4647 "vneg", "f32", "$Vd, $Vm", "",
4648 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
4650 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
4651 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
4652 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
4653 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
4654 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
4655 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
4657 // VQNEG : Vector Saturating Negate
4658 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
4659 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
4660 int_arm_neon_vqneg>;
4662 // Vector Bit Counting Operations.
4664 // VCLS : Vector Count Leading Sign Bits
4665 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
4666 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
4668 // VCLZ : Vector Count Leading Zeros
4669 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
4670 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
4672 // VCNT : Vector Count One Bits
4673 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4674 IIC_VCNTiD, "vcnt", "8",
4675 v8i8, v8i8, int_arm_neon_vcnt>;
4676 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4677 IIC_VCNTiQ, "vcnt", "8",
4678 v16i8, v16i8, int_arm_neon_vcnt>;
4681 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
4682 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
4683 "vswp", "$Vd, $Vm", "", []>;
4684 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
4685 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
4686 "vswp", "$Vd, $Vm", "", []>;
4688 // Vector Move Operations.
4690 // VMOV : Vector Move (Register)
4691 def : InstAlias<"vmov${p} $Vd, $Vm",
4692 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
4693 def : InstAlias<"vmov${p} $Vd, $Vm",
4694 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
4696 // VMOV : Vector Move (Immediate)
4698 let isReMaterializable = 1 in {
4699 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
4700 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
4701 "vmov", "i8", "$Vd, $SIMM", "",
4702 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
4703 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
4704 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
4705 "vmov", "i8", "$Vd, $SIMM", "",
4706 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
4708 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
4709 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4710 "vmov", "i16", "$Vd, $SIMM", "",
4711 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
4712 let Inst{9} = SIMM{9};
4715 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
4716 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4717 "vmov", "i16", "$Vd, $SIMM", "",
4718 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
4719 let Inst{9} = SIMM{9};
4722 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
4723 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4724 "vmov", "i32", "$Vd, $SIMM", "",
4725 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
4726 let Inst{11-8} = SIMM{11-8};
4729 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
4730 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4731 "vmov", "i32", "$Vd, $SIMM", "",
4732 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
4733 let Inst{11-8} = SIMM{11-8};
4736 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
4737 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
4738 "vmov", "i64", "$Vd, $SIMM", "",
4739 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
4740 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
4741 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
4742 "vmov", "i64", "$Vd, $SIMM", "",
4743 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
4745 def VMOVv2f32 : N1ModImm<1, 0b000, 0b1111, 0, 0, 0, 1, (outs DPR:$Vd),
4746 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
4747 "vmov", "f32", "$Vd, $SIMM", "",
4748 [(set DPR:$Vd, (v2f32 (NEONvmovFPImm timm:$SIMM)))]>;
4749 def VMOVv4f32 : N1ModImm<1, 0b000, 0b1111, 0, 1, 0, 1, (outs QPR:$Vd),
4750 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
4751 "vmov", "f32", "$Vd, $SIMM", "",
4752 [(set QPR:$Vd, (v4f32 (NEONvmovFPImm timm:$SIMM)))]>;
4753 } // isReMaterializable
4755 // VMOV : Vector Get Lane (move scalar to ARM core register)
4757 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
4758 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
4759 IIC_VMOVSI, "vmov", "s8", "$R, $V$lane",
4760 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
4762 let Inst{21} = lane{2};
4763 let Inst{6-5} = lane{1-0};
4765 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
4766 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
4767 IIC_VMOVSI, "vmov", "s16", "$R, $V$lane",
4768 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
4770 let Inst{21} = lane{1};
4771 let Inst{6} = lane{0};
4773 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
4774 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
4775 IIC_VMOVSI, "vmov", "u8", "$R, $V$lane",
4776 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
4778 let Inst{21} = lane{2};
4779 let Inst{6-5} = lane{1-0};
4781 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
4782 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
4783 IIC_VMOVSI, "vmov", "u16", "$R, $V$lane",
4784 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
4786 let Inst{21} = lane{1};
4787 let Inst{6} = lane{0};
4789 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
4790 (outs GPR:$R), (ins DPR:$V, VectorIndex32:$lane),
4791 IIC_VMOVSI, "vmov", "32", "$R, $V$lane",
4792 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
4794 let Inst{21} = lane{0};
4796 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
4797 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
4798 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4799 (DSubReg_i8_reg imm:$lane))),
4800 (SubReg_i8_lane imm:$lane))>;
4801 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
4802 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4803 (DSubReg_i16_reg imm:$lane))),
4804 (SubReg_i16_lane imm:$lane))>;
4805 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
4806 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4807 (DSubReg_i8_reg imm:$lane))),
4808 (SubReg_i8_lane imm:$lane))>;
4809 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
4810 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4811 (DSubReg_i16_reg imm:$lane))),
4812 (SubReg_i16_lane imm:$lane))>;
4813 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
4814 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
4815 (DSubReg_i32_reg imm:$lane))),
4816 (SubReg_i32_lane imm:$lane))>;
4817 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
4818 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
4819 (SSubReg_f32_reg imm:$src2))>;
4820 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
4821 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
4822 (SSubReg_f32_reg imm:$src2))>;
4823 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
4824 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4825 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
4826 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4829 // VMOV : Vector Set Lane (move ARM core register to scalar)
4831 let Constraints = "$src1 = $V" in {
4832 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
4833 (ins DPR:$src1, GPR:$R, VectorIndex8:$lane),
4834 IIC_VMOVISL, "vmov", "8", "$V$lane, $R",
4835 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
4836 GPR:$R, imm:$lane))]> {
4837 let Inst{21} = lane{2};
4838 let Inst{6-5} = lane{1-0};
4840 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
4841 (ins DPR:$src1, GPR:$R, VectorIndex16:$lane),
4842 IIC_VMOVISL, "vmov", "16", "$V$lane, $R",
4843 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
4844 GPR:$R, imm:$lane))]> {
4845 let Inst{21} = lane{1};
4846 let Inst{6} = lane{0};
4848 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
4849 (ins DPR:$src1, GPR:$R, VectorIndex32:$lane),
4850 IIC_VMOVISL, "vmov", "32", "$V$lane, $R",
4851 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
4852 GPR:$R, imm:$lane))]> {
4853 let Inst{21} = lane{0};
4856 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
4857 (v16i8 (INSERT_SUBREG QPR:$src1,
4858 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
4859 (DSubReg_i8_reg imm:$lane))),
4860 GPR:$src2, (SubReg_i8_lane imm:$lane))),
4861 (DSubReg_i8_reg imm:$lane)))>;
4862 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
4863 (v8i16 (INSERT_SUBREG QPR:$src1,
4864 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
4865 (DSubReg_i16_reg imm:$lane))),
4866 GPR:$src2, (SubReg_i16_lane imm:$lane))),
4867 (DSubReg_i16_reg imm:$lane)))>;
4868 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
4869 (v4i32 (INSERT_SUBREG QPR:$src1,
4870 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
4871 (DSubReg_i32_reg imm:$lane))),
4872 GPR:$src2, (SubReg_i32_lane imm:$lane))),
4873 (DSubReg_i32_reg imm:$lane)))>;
4875 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
4876 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
4877 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4878 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
4879 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
4880 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4882 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4883 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4884 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4885 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4887 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
4888 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4889 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
4890 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
4891 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
4892 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4894 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
4895 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4896 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
4897 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4898 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
4899 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4901 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
4902 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4903 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4905 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
4906 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
4907 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4909 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
4910 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4911 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4914 // VDUP : Vector Duplicate (from ARM core register to all elements)
4916 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4917 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
4918 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4919 [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4920 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4921 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
4922 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4923 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4925 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
4926 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
4927 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
4928 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
4929 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
4930 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
4932 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32d GPR:$R)>;
4933 def : Pat<(v4f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32q GPR:$R)>;
4935 // VDUP : Vector Duplicate Lane (from scalar to all elements)
4937 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
4938 ValueType Ty, Operand IdxTy>
4939 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
4940 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm$lane",
4941 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
4943 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
4944 ValueType ResTy, ValueType OpTy, Operand IdxTy>
4945 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
4946 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm$lane",
4947 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
4948 VectorIndex32:$lane)))]>;
4950 // Inst{19-16} is partially specified depending on the element size.
4952 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8, VectorIndex8> {
4954 let Inst{19-17} = lane{2-0};
4956 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16, VectorIndex16> {
4958 let Inst{19-18} = lane{1-0};
4960 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32, VectorIndex32> {
4962 let Inst{19} = lane{0};
4964 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8, VectorIndex8> {
4966 let Inst{19-17} = lane{2-0};
4968 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16, VectorIndex16> {
4970 let Inst{19-18} = lane{1-0};
4972 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32, VectorIndex32> {
4974 let Inst{19} = lane{0};
4977 def : Pat<(v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
4978 (VDUPLN32d DPR:$Vm, imm:$lane)>;
4980 def : Pat<(v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
4981 (VDUPLN32q DPR:$Vm, imm:$lane)>;
4983 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
4984 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
4985 (DSubReg_i8_reg imm:$lane))),
4986 (SubReg_i8_lane imm:$lane)))>;
4987 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
4988 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
4989 (DSubReg_i16_reg imm:$lane))),
4990 (SubReg_i16_lane imm:$lane)))>;
4991 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
4992 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
4993 (DSubReg_i32_reg imm:$lane))),
4994 (SubReg_i32_lane imm:$lane)))>;
4995 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
4996 (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src,
4997 (DSubReg_i32_reg imm:$lane))),
4998 (SubReg_i32_lane imm:$lane)))>;
5000 def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
5001 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
5002 def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
5003 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
5005 // VMOVN : Vector Narrowing Move
5006 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
5007 "vmovn", "i", trunc>;
5008 // VQMOVN : Vector Saturating Narrowing Move
5009 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
5010 "vqmovn", "s", int_arm_neon_vqmovns>;
5011 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
5012 "vqmovn", "u", int_arm_neon_vqmovnu>;
5013 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
5014 "vqmovun", "s", int_arm_neon_vqmovnsu>;
5015 // VMOVL : Vector Lengthening Move
5016 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
5017 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
5019 // Vector Conversions.
5021 // VCVT : Vector Convert Between Floating-Point and Integers
5022 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
5023 v2i32, v2f32, fp_to_sint>;
5024 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
5025 v2i32, v2f32, fp_to_uint>;
5026 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
5027 v2f32, v2i32, sint_to_fp>;
5028 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
5029 v2f32, v2i32, uint_to_fp>;
5031 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
5032 v4i32, v4f32, fp_to_sint>;
5033 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
5034 v4i32, v4f32, fp_to_uint>;
5035 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
5036 v4f32, v4i32, sint_to_fp>;
5037 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
5038 v4f32, v4i32, uint_to_fp>;
5040 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
5041 let DecoderMethod = "DecodeVCVTD" in {
5042 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
5043 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
5044 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
5045 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
5046 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
5047 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
5048 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
5049 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
5052 let DecoderMethod = "DecodeVCVTQ" in {
5053 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
5054 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
5055 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
5056 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
5057 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
5058 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
5059 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
5060 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
5063 // VCVT : Vector Convert Between Half-Precision and Single-Precision.
5064 def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
5065 IIC_VUNAQ, "vcvt", "f16.f32",
5066 v4i16, v4f32, int_arm_neon_vcvtfp2hf>,
5067 Requires<[HasNEON, HasFP16]>;
5068 def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
5069 IIC_VUNAQ, "vcvt", "f32.f16",
5070 v4f32, v4i16, int_arm_neon_vcvthf2fp>,
5071 Requires<[HasNEON, HasFP16]>;
5075 // VREV64 : Vector Reverse elements within 64-bit doublewords
5077 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5078 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
5079 (ins DPR:$Vm), IIC_VMOVD,
5080 OpcodeStr, Dt, "$Vd, $Vm", "",
5081 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
5082 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5083 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
5084 (ins QPR:$Vm), IIC_VMOVQ,
5085 OpcodeStr, Dt, "$Vd, $Vm", "",
5086 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
5088 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
5089 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
5090 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
5091 def : Pat<(v2f32 (NEONvrev64 (v2f32 DPR:$Vm))), (VREV64d32 DPR:$Vm)>;
5093 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
5094 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
5095 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
5096 def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>;
5098 // VREV32 : Vector Reverse elements within 32-bit words
5100 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5101 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
5102 (ins DPR:$Vm), IIC_VMOVD,
5103 OpcodeStr, Dt, "$Vd, $Vm", "",
5104 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
5105 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5106 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
5107 (ins QPR:$Vm), IIC_VMOVQ,
5108 OpcodeStr, Dt, "$Vd, $Vm", "",
5109 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
5111 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
5112 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
5114 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
5115 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
5117 // VREV16 : Vector Reverse elements within 16-bit halfwords
5119 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5120 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
5121 (ins DPR:$Vm), IIC_VMOVD,
5122 OpcodeStr, Dt, "$Vd, $Vm", "",
5123 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
5124 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5125 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
5126 (ins QPR:$Vm), IIC_VMOVQ,
5127 OpcodeStr, Dt, "$Vd, $Vm", "",
5128 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
5130 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
5131 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
5133 // Other Vector Shuffles.
5135 // Aligned extractions: really just dropping registers
5137 class AlignedVEXTq<ValueType DestTy, ValueType SrcTy, SDNodeXForm LaneCVT>
5138 : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))),
5139 (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>;
5141 def : AlignedVEXTq<v8i8, v16i8, DSubReg_i8_reg>;
5143 def : AlignedVEXTq<v4i16, v8i16, DSubReg_i16_reg>;
5145 def : AlignedVEXTq<v2i32, v4i32, DSubReg_i32_reg>;
5147 def : AlignedVEXTq<v1i64, v2i64, DSubReg_f64_reg>;
5149 def : AlignedVEXTq<v2f32, v4f32, DSubReg_i32_reg>;
5152 // VEXT : Vector Extract
5154 class VEXTd<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
5155 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
5156 (ins DPR:$Vn, DPR:$Vm, immTy:$index), NVExtFrm,
5157 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
5158 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
5159 (Ty DPR:$Vm), imm:$index)))]> {
5161 let Inst{11-8} = index{3-0};
5164 class VEXTq<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
5165 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
5166 (ins QPR:$Vn, QPR:$Vm, imm0_15:$index), NVExtFrm,
5167 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
5168 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
5169 (Ty QPR:$Vm), imm:$index)))]> {
5171 let Inst{11-8} = index{3-0};
5174 def VEXTd8 : VEXTd<"vext", "8", v8i8, imm0_7> {
5175 let Inst{11-8} = index{3-0};
5177 def VEXTd16 : VEXTd<"vext", "16", v4i16, imm0_3> {
5178 let Inst{11-9} = index{2-0};
5181 def VEXTd32 : VEXTd<"vext", "32", v2i32, imm0_1> {
5182 let Inst{11-10} = index{1-0};
5183 let Inst{9-8} = 0b00;
5185 def : Pat<(v2f32 (NEONvext (v2f32 DPR:$Vn),
5188 (VEXTd32 DPR:$Vn, DPR:$Vm, imm:$index)>;
5190 def VEXTq8 : VEXTq<"vext", "8", v16i8, imm0_15> {
5191 let Inst{11-8} = index{3-0};
5193 def VEXTq16 : VEXTq<"vext", "16", v8i16, imm0_7> {
5194 let Inst{11-9} = index{2-0};
5197 def VEXTq32 : VEXTq<"vext", "32", v4i32, imm0_3> {
5198 let Inst{11-10} = index{1-0};
5199 let Inst{9-8} = 0b00;
5201 def VEXTq64 : VEXTq<"vext", "64", v2i64, imm0_1> {
5202 let Inst{11} = index{0};
5203 let Inst{10-8} = 0b000;
5205 def : Pat<(v4f32 (NEONvext (v4f32 QPR:$Vn),
5208 (VEXTq32 QPR:$Vn, QPR:$Vm, imm:$index)>;
5210 // VTRN : Vector Transpose
5212 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
5213 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
5214 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
5216 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
5217 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
5218 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
5220 // VUZP : Vector Unzip (Deinterleave)
5222 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
5223 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
5224 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
5226 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
5227 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
5228 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
5230 // VZIP : Vector Zip (Interleave)
5232 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
5233 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
5234 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
5236 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
5237 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
5238 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
5240 // Vector Table Lookup and Table Extension.
5242 // VTBL : Vector Table Lookup
5243 let DecoderMethod = "DecodeTBLInstruction" in {
5245 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
5246 (ins VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
5247 "vtbl", "8", "$Vd, $Vn, $Vm", "",
5248 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 VecListOneD:$Vn, DPR:$Vm)))]>;
5249 let hasExtraSrcRegAllocReq = 1 in {
5251 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
5252 (ins VecListTwoD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB2,
5253 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5255 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
5256 (ins VecListThreeD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB3,
5257 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5259 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
5260 (ins VecListFourD:$Vn, DPR:$Vm),
5262 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5263 } // hasExtraSrcRegAllocReq = 1
5266 : PseudoNeonI<(outs DPR:$dst), (ins QPR:$tbl, DPR:$src), IIC_VTB2, "", []>;
5268 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
5270 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
5272 // VTBX : Vector Table Extension
5274 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
5275 (ins DPR:$orig, VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
5276 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd",
5277 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
5278 DPR:$orig, VecListOneD:$Vn, DPR:$Vm)))]>;
5279 let hasExtraSrcRegAllocReq = 1 in {
5281 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
5282 (ins DPR:$orig, VecListTwoD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
5283 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd", []>;
5285 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
5286 (ins DPR:$orig, VecListThreeD:$Vn, DPR:$Vm),
5287 NVTBLFrm, IIC_VTBX3,
5288 "vtbx", "8", "$Vd, $Vn, $Vm",
5291 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd),
5292 (ins DPR:$orig, VecListFourD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
5293 "vtbx", "8", "$Vd, $Vn, $Vm",
5295 } // hasExtraSrcRegAllocReq = 1
5298 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QPR:$tbl, DPR:$src),
5299 IIC_VTBX2, "$orig = $dst", []>;
5301 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
5302 IIC_VTBX3, "$orig = $dst", []>;
5304 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
5305 IIC_VTBX4, "$orig = $dst", []>;
5306 } // DecoderMethod = "DecodeTBLInstruction"
5308 //===----------------------------------------------------------------------===//
5309 // NEON instructions for single-precision FP math
5310 //===----------------------------------------------------------------------===//
5312 class N2VSPat<SDNode OpNode, NeonI Inst>
5313 : NEONFPPat<(f32 (OpNode SPR:$a)),
5315 (v2f32 (COPY_TO_REGCLASS (Inst
5317 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5318 SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>;
5320 class N3VSPat<SDNode OpNode, NeonI Inst>
5321 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
5323 (v2f32 (COPY_TO_REGCLASS (Inst
5325 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5328 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5329 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
5331 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
5332 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
5334 (v2f32 (COPY_TO_REGCLASS (Inst
5336 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5339 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5342 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5343 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
5345 def : N3VSPat<fadd, VADDfd>;
5346 def : N3VSPat<fsub, VSUBfd>;
5347 def : N3VSPat<fmul, VMULfd>;
5348 def : N3VSMulOpPat<fmul, fadd, VMLAfd>,
5349 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
5350 def : N3VSMulOpPat<fmul, fsub, VMLSfd>,
5351 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
5352 def : N2VSPat<fabs, VABSfd>;
5353 def : N2VSPat<fneg, VNEGfd>;
5354 def : N3VSPat<NEONfmax, VMAXfd>;
5355 def : N3VSPat<NEONfmin, VMINfd>;
5356 def : N2VSPat<arm_ftosi, VCVTf2sd>;
5357 def : N2VSPat<arm_ftoui, VCVTf2ud>;
5358 def : N2VSPat<arm_sitof, VCVTs2fd>;
5359 def : N2VSPat<arm_uitof, VCVTu2fd>;
5361 //===----------------------------------------------------------------------===//
5362 // Non-Instruction Patterns
5363 //===----------------------------------------------------------------------===//
5366 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
5367 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
5368 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
5369 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
5370 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
5371 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
5372 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
5373 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
5374 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
5375 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
5376 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
5377 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
5378 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
5379 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
5380 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
5381 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
5382 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
5383 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
5384 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
5385 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
5386 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
5387 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
5388 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
5389 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
5390 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
5391 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
5392 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
5393 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
5394 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
5395 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
5397 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
5398 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
5399 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
5400 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
5401 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
5402 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
5403 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
5404 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
5405 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
5406 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
5407 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
5408 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
5409 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
5410 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
5411 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
5412 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
5413 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
5414 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
5415 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
5416 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
5417 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
5418 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
5419 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
5420 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
5421 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
5422 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
5423 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
5424 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
5425 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
5426 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
5429 //===----------------------------------------------------------------------===//
5430 // Assembler aliases
5433 def : VFP2InstAlias<"fmdhr${p} $Dd, $Rn",
5434 (VSETLNi32 DPR:$Dd, GPR:$Rn, 1, pred:$p)>;
5435 def : VFP2InstAlias<"fmdlr${p} $Dd, $Rn",
5436 (VSETLNi32 DPR:$Dd, GPR:$Rn, 0, pred:$p)>;
5439 // VADD two-operand aliases.
5440 def : NEONInstAlias<"vadd${p}.i8 $Vdn, $Vm",
5441 (VADDv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5442 def : NEONInstAlias<"vadd${p}.i16 $Vdn, $Vm",
5443 (VADDv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5444 def : NEONInstAlias<"vadd${p}.i32 $Vdn, $Vm",
5445 (VADDv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5446 def : NEONInstAlias<"vadd${p}.i64 $Vdn, $Vm",
5447 (VADDv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5449 def : NEONInstAlias<"vadd${p}.i8 $Vdn, $Vm",
5450 (VADDv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5451 def : NEONInstAlias<"vadd${p}.i16 $Vdn, $Vm",
5452 (VADDv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5453 def : NEONInstAlias<"vadd${p}.i32 $Vdn, $Vm",
5454 (VADDv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5455 def : NEONInstAlias<"vadd${p}.i64 $Vdn, $Vm",
5456 (VADDv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5458 def : NEONInstAlias<"vadd${p}.f32 $Vdn, $Vm",
5459 (VADDfd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5460 def : NEONInstAlias<"vadd${p}.f32 $Vdn, $Vm",
5461 (VADDfq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5463 // VSUB two-operand aliases.
5464 def : NEONInstAlias<"vsub${p}.i8 $Vdn, $Vm",
5465 (VSUBv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5466 def : NEONInstAlias<"vsub${p}.i16 $Vdn, $Vm",
5467 (VSUBv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5468 def : NEONInstAlias<"vsub${p}.i32 $Vdn, $Vm",
5469 (VSUBv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5470 def : NEONInstAlias<"vsub${p}.i64 $Vdn, $Vm",
5471 (VSUBv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5473 def : NEONInstAlias<"vsub${p}.i8 $Vdn, $Vm",
5474 (VSUBv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5475 def : NEONInstAlias<"vsub${p}.i16 $Vdn, $Vm",
5476 (VSUBv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5477 def : NEONInstAlias<"vsub${p}.i32 $Vdn, $Vm",
5478 (VSUBv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5479 def : NEONInstAlias<"vsub${p}.i64 $Vdn, $Vm",
5480 (VSUBv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5482 def : NEONInstAlias<"vsub${p}.f32 $Vdn, $Vm",
5483 (VSUBfd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5484 def : NEONInstAlias<"vsub${p}.f32 $Vdn, $Vm",
5485 (VSUBfq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5487 // VADDW two-operand aliases.
5488 def : NEONInstAlias<"vaddw${p}.s8 $Vdn, $Vm",
5489 (VADDWsv8i16 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
5490 def : NEONInstAlias<"vaddw${p}.s16 $Vdn, $Vm",
5491 (VADDWsv4i32 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
5492 def : NEONInstAlias<"vaddw${p}.s32 $Vdn, $Vm",
5493 (VADDWsv2i64 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
5494 def : NEONInstAlias<"vaddw${p}.u8 $Vdn, $Vm",
5495 (VADDWuv8i16 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
5496 def : NEONInstAlias<"vaddw${p}.u16 $Vdn, $Vm",
5497 (VADDWuv4i32 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
5498 def : NEONInstAlias<"vaddw${p}.u32 $Vdn, $Vm",
5499 (VADDWuv2i64 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
5501 // VAND/VBIC/VEOR/VORR accept but do not require a type suffix.
5502 defm : VFPDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
5503 (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
5504 defm : VFPDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
5505 (VANDq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
5506 defm : VFPDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
5507 (VBICd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
5508 defm : VFPDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
5509 (VBICq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
5510 defm : VFPDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
5511 (VEORd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
5512 defm : VFPDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
5513 (VEORq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
5514 defm : VFPDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
5515 (VORRd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
5516 defm : VFPDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
5517 (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
5518 // ... two-operand aliases
5519 def : NEONInstAlias<"vand${p} $Vdn, $Vm",
5520 (VANDd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5521 def : NEONInstAlias<"vand${p} $Vdn, $Vm",
5522 (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5523 def : NEONInstAlias<"vbic${p} $Vdn, $Vm",
5524 (VBICd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5525 def : NEONInstAlias<"vbic${p} $Vdn, $Vm",
5526 (VBICq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5527 def : NEONInstAlias<"veor${p} $Vdn, $Vm",
5528 (VEORd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5529 def : NEONInstAlias<"veor${p} $Vdn, $Vm",
5530 (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5531 def : NEONInstAlias<"vorr${p} $Vdn, $Vm",
5532 (VORRd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5533 def : NEONInstAlias<"vorr${p} $Vdn, $Vm",
5534 (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5536 defm : VFPDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",
5537 (VANDd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5538 defm : VFPDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",
5539 (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5540 defm : VFPDTAnyInstAlias<"veor${p}", "$Vdn, $Vm",
5541 (VEORd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5542 defm : VFPDTAnyInstAlias<"veor${p}", "$Vdn, $Vm",
5543 (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5544 defm : VFPDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
5545 (VORRd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5546 defm : VFPDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
5547 (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5549 // VMUL two-operand aliases.
5550 def : NEONInstAlias<"vmul${p}.p8 $Qdn, $Qm",
5551 (VMULpq QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>;
5552 def : NEONInstAlias<"vmul${p}.i8 $Qdn, $Qm",
5553 (VMULv16i8 QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>;
5554 def : NEONInstAlias<"vmul${p}.i16 $Qdn, $Qm",
5555 (VMULv8i16 QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>;
5556 def : NEONInstAlias<"vmul${p}.i32 $Qdn, $Qm",
5557 (VMULv4i32 QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>;
5559 def : NEONInstAlias<"vmul${p}.p8 $Ddn, $Dm",
5560 (VMULpd DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>;
5561 def : NEONInstAlias<"vmul${p}.i8 $Ddn, $Dm",
5562 (VMULv8i8 DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>;
5563 def : NEONInstAlias<"vmul${p}.i16 $Ddn, $Dm",
5564 (VMULv4i16 DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>;
5565 def : NEONInstAlias<"vmul${p}.i32 $Ddn, $Dm",
5566 (VMULv2i32 DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>;
5568 def : NEONInstAlias<"vmul${p}.f32 $Qdn, $Qm",
5569 (VMULfq QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>;
5570 def : NEONInstAlias<"vmul${p}.f32 $Ddn, $Dm",
5571 (VMULfd DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>;
5573 def : NEONInstAlias<"vmul${p}.i16 $Ddn, $Dm$lane",
5574 (VMULslv4i16 DPR:$Ddn, DPR:$Ddn, DPR_8:$Dm,
5575 VectorIndex16:$lane, pred:$p)>;
5576 def : NEONInstAlias<"vmul${p}.i16 $Qdn, $Dm$lane",
5577 (VMULslv8i16 QPR:$Qdn, QPR:$Qdn, DPR_8:$Dm,
5578 VectorIndex16:$lane, pred:$p)>;
5580 def : NEONInstAlias<"vmul${p}.i32 $Ddn, $Dm$lane",
5581 (VMULslv2i32 DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm,
5582 VectorIndex32:$lane, pred:$p)>;
5583 def : NEONInstAlias<"vmul${p}.i32 $Qdn, $Dm$lane",
5584 (VMULslv4i32 QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm,
5585 VectorIndex32:$lane, pred:$p)>;
5587 def : NEONInstAlias<"vmul${p}.f32 $Ddn, $Dm$lane",
5588 (VMULslfd DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm,
5589 VectorIndex32:$lane, pred:$p)>;
5590 def : NEONInstAlias<"vmul${p}.f32 $Qdn, $Dm$lane",
5591 (VMULslfq QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm,
5592 VectorIndex32:$lane, pred:$p)>;
5594 // VQADD (register) two-operand aliases.
5595 def : NEONInstAlias<"vqadd${p}.s8 $Vdn, $Vm",
5596 (VQADDsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5597 def : NEONInstAlias<"vqadd${p}.s16 $Vdn, $Vm",
5598 (VQADDsv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5599 def : NEONInstAlias<"vqadd${p}.s32 $Vdn, $Vm",
5600 (VQADDsv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5601 def : NEONInstAlias<"vqadd${p}.s64 $Vdn, $Vm",
5602 (VQADDsv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5603 def : NEONInstAlias<"vqadd${p}.u8 $Vdn, $Vm",
5604 (VQADDuv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5605 def : NEONInstAlias<"vqadd${p}.u16 $Vdn, $Vm",
5606 (VQADDuv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5607 def : NEONInstAlias<"vqadd${p}.u32 $Vdn, $Vm",
5608 (VQADDuv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5609 def : NEONInstAlias<"vqadd${p}.u64 $Vdn, $Vm",
5610 (VQADDuv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5612 def : NEONInstAlias<"vqadd${p}.s8 $Vdn, $Vm",
5613 (VQADDsv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5614 def : NEONInstAlias<"vqadd${p}.s16 $Vdn, $Vm",
5615 (VQADDsv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5616 def : NEONInstAlias<"vqadd${p}.s32 $Vdn, $Vm",
5617 (VQADDsv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5618 def : NEONInstAlias<"vqadd${p}.s64 $Vdn, $Vm",
5619 (VQADDsv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5620 def : NEONInstAlias<"vqadd${p}.u8 $Vdn, $Vm",
5621 (VQADDuv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5622 def : NEONInstAlias<"vqadd${p}.u16 $Vdn, $Vm",
5623 (VQADDuv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5624 def : NEONInstAlias<"vqadd${p}.u32 $Vdn, $Vm",
5625 (VQADDuv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5626 def : NEONInstAlias<"vqadd${p}.u64 $Vdn, $Vm",
5627 (VQADDuv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5629 // VSHL (immediate) two-operand aliases.
5630 def : NEONInstAlias<"vshl${p}.i8 $Vdn, $imm",
5631 (VSHLiv8i8 DPR:$Vdn, DPR:$Vdn, imm0_7:$imm, pred:$p)>;
5632 def : NEONInstAlias<"vshl${p}.i16 $Vdn, $imm",
5633 (VSHLiv4i16 DPR:$Vdn, DPR:$Vdn, imm0_15:$imm, pred:$p)>;
5634 def : NEONInstAlias<"vshl${p}.i32 $Vdn, $imm",
5635 (VSHLiv2i32 DPR:$Vdn, DPR:$Vdn, imm0_31:$imm, pred:$p)>;
5636 def : NEONInstAlias<"vshl${p}.i64 $Vdn, $imm",
5637 (VSHLiv1i64 DPR:$Vdn, DPR:$Vdn, imm0_63:$imm, pred:$p)>;
5639 def : NEONInstAlias<"vshl${p}.i8 $Vdn, $imm",
5640 (VSHLiv16i8 QPR:$Vdn, QPR:$Vdn, imm0_7:$imm, pred:$p)>;
5641 def : NEONInstAlias<"vshl${p}.i16 $Vdn, $imm",
5642 (VSHLiv8i16 QPR:$Vdn, QPR:$Vdn, imm0_15:$imm, pred:$p)>;
5643 def : NEONInstAlias<"vshl${p}.i32 $Vdn, $imm",
5644 (VSHLiv4i32 QPR:$Vdn, QPR:$Vdn, imm0_31:$imm, pred:$p)>;
5645 def : NEONInstAlias<"vshl${p}.i64 $Vdn, $imm",
5646 (VSHLiv2i64 QPR:$Vdn, QPR:$Vdn, imm0_63:$imm, pred:$p)>;
5648 // VSHL (register) two-operand aliases.
5649 def : NEONInstAlias<"vshl${p}.s8 $Vdn, $Vm",
5650 (VSHLsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5651 def : NEONInstAlias<"vshl${p}.s16 $Vdn, $Vm",
5652 (VSHLsv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5653 def : NEONInstAlias<"vshl${p}.s32 $Vdn, $Vm",
5654 (VSHLsv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5655 def : NEONInstAlias<"vshl${p}.s64 $Vdn, $Vm",
5656 (VSHLsv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5657 def : NEONInstAlias<"vshl${p}.u8 $Vdn, $Vm",
5658 (VSHLuv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5659 def : NEONInstAlias<"vshl${p}.u16 $Vdn, $Vm",
5660 (VSHLuv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5661 def : NEONInstAlias<"vshl${p}.u32 $Vdn, $Vm",
5662 (VSHLuv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5663 def : NEONInstAlias<"vshl${p}.u64 $Vdn, $Vm",
5664 (VSHLuv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5666 def : NEONInstAlias<"vshl${p}.s8 $Vdn, $Vm",
5667 (VSHLsv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5668 def : NEONInstAlias<"vshl${p}.s16 $Vdn, $Vm",
5669 (VSHLsv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5670 def : NEONInstAlias<"vshl${p}.s32 $Vdn, $Vm",
5671 (VSHLsv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5672 def : NEONInstAlias<"vshl${p}.s64 $Vdn, $Vm",
5673 (VSHLsv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5674 def : NEONInstAlias<"vshl${p}.u8 $Vdn, $Vm",
5675 (VSHLuv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5676 def : NEONInstAlias<"vshl${p}.u16 $Vdn, $Vm",
5677 (VSHLuv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5678 def : NEONInstAlias<"vshl${p}.u32 $Vdn, $Vm",
5679 (VSHLuv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5680 def : NEONInstAlias<"vshl${p}.u64 $Vdn, $Vm",
5681 (VSHLuv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5683 // VSHL (immediate) two-operand aliases.
5684 def : NEONInstAlias<"vshr${p}.s8 $Vdn, $imm",
5685 (VSHRsv8i8 DPR:$Vdn, DPR:$Vdn, shr_imm8:$imm, pred:$p)>;
5686 def : NEONInstAlias<"vshr${p}.s16 $Vdn, $imm",
5687 (VSHRsv4i16 DPR:$Vdn, DPR:$Vdn, shr_imm16:$imm, pred:$p)>;
5688 def : NEONInstAlias<"vshr${p}.s32 $Vdn, $imm",
5689 (VSHRsv2i32 DPR:$Vdn, DPR:$Vdn, shr_imm32:$imm, pred:$p)>;
5690 def : NEONInstAlias<"vshr${p}.s64 $Vdn, $imm",
5691 (VSHRsv1i64 DPR:$Vdn, DPR:$Vdn, shr_imm64:$imm, pred:$p)>;
5693 def : NEONInstAlias<"vshr${p}.s8 $Vdn, $imm",
5694 (VSHRsv16i8 QPR:$Vdn, QPR:$Vdn, shr_imm8:$imm, pred:$p)>;
5695 def : NEONInstAlias<"vshr${p}.s16 $Vdn, $imm",
5696 (VSHRsv8i16 QPR:$Vdn, QPR:$Vdn, shr_imm16:$imm, pred:$p)>;
5697 def : NEONInstAlias<"vshr${p}.s32 $Vdn, $imm",
5698 (VSHRsv4i32 QPR:$Vdn, QPR:$Vdn, shr_imm32:$imm, pred:$p)>;
5699 def : NEONInstAlias<"vshr${p}.s64 $Vdn, $imm",
5700 (VSHRsv2i64 QPR:$Vdn, QPR:$Vdn, shr_imm64:$imm, pred:$p)>;
5702 def : NEONInstAlias<"vshr${p}.u8 $Vdn, $imm",
5703 (VSHRuv8i8 DPR:$Vdn, DPR:$Vdn, shr_imm8:$imm, pred:$p)>;
5704 def : NEONInstAlias<"vshr${p}.u16 $Vdn, $imm",
5705 (VSHRuv4i16 DPR:$Vdn, DPR:$Vdn, shr_imm16:$imm, pred:$p)>;
5706 def : NEONInstAlias<"vshr${p}.u32 $Vdn, $imm",
5707 (VSHRuv2i32 DPR:$Vdn, DPR:$Vdn, shr_imm32:$imm, pred:$p)>;
5708 def : NEONInstAlias<"vshr${p}.u64 $Vdn, $imm",
5709 (VSHRuv1i64 DPR:$Vdn, DPR:$Vdn, shr_imm64:$imm, pred:$p)>;
5711 def : NEONInstAlias<"vshr${p}.u8 $Vdn, $imm",
5712 (VSHRuv16i8 QPR:$Vdn, QPR:$Vdn, shr_imm8:$imm, pred:$p)>;
5713 def : NEONInstAlias<"vshr${p}.u16 $Vdn, $imm",
5714 (VSHRuv8i16 QPR:$Vdn, QPR:$Vdn, shr_imm16:$imm, pred:$p)>;
5715 def : NEONInstAlias<"vshr${p}.u32 $Vdn, $imm",
5716 (VSHRuv4i32 QPR:$Vdn, QPR:$Vdn, shr_imm32:$imm, pred:$p)>;
5717 def : NEONInstAlias<"vshr${p}.u64 $Vdn, $imm",
5718 (VSHRuv2i64 QPR:$Vdn, QPR:$Vdn, shr_imm64:$imm, pred:$p)>;
5720 // VLD1 single-lane pseudo-instructions. These need special handling for
5721 // the lane index that an InstAlias can't handle, so we use these instead.
5722 defm VLD1LNdAsm : NEONDT8AsmPseudoInst<"vld1${p}", "$list, $addr",
5723 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5724 defm VLD1LNdAsm : NEONDT16AsmPseudoInst<"vld1${p}", "$list, $addr",
5725 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5726 defm VLD1LNdAsm : NEONDT32AsmPseudoInst<"vld1${p}", "$list, $addr",
5727 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5729 defm VLD1LNdWB_fixed_Asm : NEONDT8AsmPseudoInst<"vld1${p}", "$list, $addr!",
5730 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5731 defm VLD1LNdWB_fixed_Asm : NEONDT16AsmPseudoInst<"vld1${p}", "$list, $addr!",
5732 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5733 defm VLD1LNdWB_fixed_Asm : NEONDT32AsmPseudoInst<"vld1${p}", "$list, $addr!",
5734 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5735 defm VLD1LNdWB_register_Asm :
5736 NEONDT8AsmPseudoInst<"vld1${p}", "$list, $addr, $Rm",
5737 (ins VecListOneDByteIndexed:$list, addrmode6:$addr,
5738 rGPR:$Rm, pred:$p)>;
5739 defm VLD1LNdWB_register_Asm :
5740 NEONDT16AsmPseudoInst<"vld1${p}", "$list, $addr, $Rm",
5741 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr,
5742 rGPR:$Rm, pred:$p)>;
5743 defm VLD1LNdWB_register_Asm :
5744 NEONDT32AsmPseudoInst<"vld1${p}", "$list, $addr, $Rm",
5745 (ins VecListOneDWordIndexed:$list, addrmode6:$addr,
5746 rGPR:$Rm, pred:$p)>;
5749 // VST1 single-lane pseudo-instructions. These need special handling for
5750 // the lane index that an InstAlias can't handle, so we use these instead.
5751 defm VST1LNdAsm : NEONDT8AsmPseudoInst<"vst1${p}", "$list, $addr",
5752 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5753 defm VST1LNdAsm : NEONDT16AsmPseudoInst<"vst1${p}", "$list, $addr",
5754 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5755 defm VST1LNdAsm : NEONDT32AsmPseudoInst<"vst1${p}", "$list, $addr",
5756 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5758 defm VST1LNdWB_fixed_Asm : NEONDT8AsmPseudoInst<"vst1${p}", "$list, $addr!",
5759 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5760 defm VST1LNdWB_fixed_Asm : NEONDT16AsmPseudoInst<"vst1${p}", "$list, $addr!",
5761 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5762 defm VST1LNdWB_fixed_Asm : NEONDT32AsmPseudoInst<"vst1${p}", "$list, $addr!",
5763 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5764 defm VST1LNdWB_register_Asm :
5765 NEONDT8AsmPseudoInst<"vst1${p}", "$list, $addr, $Rm",
5766 (ins VecListOneDByteIndexed:$list, addrmode6:$addr,
5767 rGPR:$Rm, pred:$p)>;
5768 defm VST1LNdWB_register_Asm :
5769 NEONDT16AsmPseudoInst<"vst1${p}", "$list, $addr, $Rm",
5770 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr,
5771 rGPR:$Rm, pred:$p)>;
5772 defm VST1LNdWB_register_Asm :
5773 NEONDT32AsmPseudoInst<"vst1${p}", "$list, $addr, $Rm",
5774 (ins VecListOneDWordIndexed:$list, addrmode6:$addr,
5775 rGPR:$Rm, pred:$p)>;
5777 // VLD2 single-lane pseudo-instructions. These need special handling for
5778 // the lane index that an InstAlias can't handle, so we use these instead.
5779 defm VLD2LNdAsm : NEONDT8AsmPseudoInst<"vld2${p}", "$list, $addr",
5780 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5781 defm VLD2LNdAsm : NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr",
5782 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5783 defm VLD2LNdAsm : NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr",
5784 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5785 defm VLD2LNqAsm : NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr",
5786 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5787 defm VLD2LNqAsm : NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr",
5788 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5790 defm VLD2LNdWB_fixed_Asm : NEONDT8AsmPseudoInst<"vld2${p}", "$list, $addr!",
5791 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5792 defm VLD2LNdWB_fixed_Asm : NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr!",
5793 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5794 defm VLD2LNdWB_fixed_Asm : NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr!",
5795 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5796 defm VLD2LNqWB_fixed_Asm : NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr!",
5797 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5798 defm VLD2LNqWB_fixed_Asm : NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr!",
5799 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5800 defm VLD2LNdWB_register_Asm :
5801 NEONDT8AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm",
5802 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr,
5803 rGPR:$Rm, pred:$p)>;
5804 defm VLD2LNdWB_register_Asm :
5805 NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm",
5806 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr,
5807 rGPR:$Rm, pred:$p)>;
5808 defm VLD2LNdWB_register_Asm :
5809 NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm",
5810 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr,
5811 rGPR:$Rm, pred:$p)>;
5812 defm VLD2LNqWB_register_Asm :
5813 NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm",
5814 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr,
5815 rGPR:$Rm, pred:$p)>;
5816 defm VLD2LNqWB_register_Asm :
5817 NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm",
5818 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr,
5819 rGPR:$Rm, pred:$p)>;
5822 // VST2 single-lane pseudo-instructions. These need special handling for
5823 // the lane index that an InstAlias can't handle, so we use these instead.
5824 defm VST2LNdAsm : NEONDT8AsmPseudoInst<"vst2${p}", "$list, $addr",
5825 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5826 defm VST2LNdAsm : NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr",
5827 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5828 defm VST2LNdAsm : NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr",
5829 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5830 defm VST2LNqAsm : NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr",
5831 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5832 defm VST2LNqAsm : NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr",
5833 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5835 defm VST2LNdWB_fixed_Asm : NEONDT8AsmPseudoInst<"vst2${p}", "$list, $addr!",
5836 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5837 defm VST2LNdWB_fixed_Asm : NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr!",
5838 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5839 defm VST2LNdWB_fixed_Asm : NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr!",
5840 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5841 defm VST2LNqWB_fixed_Asm : NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr!",
5842 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5843 defm VST2LNqWB_fixed_Asm : NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr!",
5844 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5845 defm VST2LNdWB_register_Asm :
5846 NEONDT8AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm",
5847 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr,
5848 rGPR:$Rm, pred:$p)>;
5849 defm VST2LNdWB_register_Asm :
5850 NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm",
5851 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr,
5852 rGPR:$Rm, pred:$p)>;
5853 defm VST2LNdWB_register_Asm :
5854 NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm",
5855 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr,
5856 rGPR:$Rm, pred:$p)>;
5857 defm VST2LNqWB_register_Asm :
5858 NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm",
5859 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr,
5860 rGPR:$Rm, pred:$p)>;
5861 defm VST2LNqWB_register_Asm :
5862 NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm",
5863 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr,
5864 rGPR:$Rm, pred:$p)>;
5866 // VMOV takes an optional datatype suffix
5867 defm : VFPDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
5868 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
5869 defm : VFPDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
5870 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
5872 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
5873 // D-register versions.
5874 def : NEONInstAlias<"vcle${p}.s8 $Dd, $Dn, $Dm",
5875 (VCGEsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5876 def : NEONInstAlias<"vcle${p}.s16 $Dd, $Dn, $Dm",
5877 (VCGEsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5878 def : NEONInstAlias<"vcle${p}.s32 $Dd, $Dn, $Dm",
5879 (VCGEsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5880 def : NEONInstAlias<"vcle${p}.u8 $Dd, $Dn, $Dm",
5881 (VCGEuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5882 def : NEONInstAlias<"vcle${p}.u16 $Dd, $Dn, $Dm",
5883 (VCGEuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5884 def : NEONInstAlias<"vcle${p}.u32 $Dd, $Dn, $Dm",
5885 (VCGEuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5886 def : NEONInstAlias<"vcle${p}.f32 $Dd, $Dn, $Dm",
5887 (VCGEfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5888 // Q-register versions.
5889 def : NEONInstAlias<"vcle${p}.s8 $Qd, $Qn, $Qm",
5890 (VCGEsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5891 def : NEONInstAlias<"vcle${p}.s16 $Qd, $Qn, $Qm",
5892 (VCGEsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5893 def : NEONInstAlias<"vcle${p}.s32 $Qd, $Qn, $Qm",
5894 (VCGEsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5895 def : NEONInstAlias<"vcle${p}.u8 $Qd, $Qn, $Qm",
5896 (VCGEuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5897 def : NEONInstAlias<"vcle${p}.u16 $Qd, $Qn, $Qm",
5898 (VCGEuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5899 def : NEONInstAlias<"vcle${p}.u32 $Qd, $Qn, $Qm",
5900 (VCGEuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5901 def : NEONInstAlias<"vcle${p}.f32 $Qd, $Qn, $Qm",
5902 (VCGEfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5904 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
5905 // D-register versions.
5906 def : NEONInstAlias<"vclt${p}.s8 $Dd, $Dn, $Dm",
5907 (VCGTsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5908 def : NEONInstAlias<"vclt${p}.s16 $Dd, $Dn, $Dm",
5909 (VCGTsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5910 def : NEONInstAlias<"vclt${p}.s32 $Dd, $Dn, $Dm",
5911 (VCGTsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5912 def : NEONInstAlias<"vclt${p}.u8 $Dd, $Dn, $Dm",
5913 (VCGTuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5914 def : NEONInstAlias<"vclt${p}.u16 $Dd, $Dn, $Dm",
5915 (VCGTuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5916 def : NEONInstAlias<"vclt${p}.u32 $Dd, $Dn, $Dm",
5917 (VCGTuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5918 def : NEONInstAlias<"vclt${p}.f32 $Dd, $Dn, $Dm",
5919 (VCGTfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5920 // Q-register versions.
5921 def : NEONInstAlias<"vclt${p}.s8 $Qd, $Qn, $Qm",
5922 (VCGTsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5923 def : NEONInstAlias<"vclt${p}.s16 $Qd, $Qn, $Qm",
5924 (VCGTsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5925 def : NEONInstAlias<"vclt${p}.s32 $Qd, $Qn, $Qm",
5926 (VCGTsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5927 def : NEONInstAlias<"vclt${p}.u8 $Qd, $Qn, $Qm",
5928 (VCGTuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5929 def : NEONInstAlias<"vclt${p}.u16 $Qd, $Qn, $Qm",
5930 (VCGTuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5931 def : NEONInstAlias<"vclt${p}.u32 $Qd, $Qn, $Qm",
5932 (VCGTuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5933 def : NEONInstAlias<"vclt${p}.f32 $Qd, $Qn, $Qm",
5934 (VCGTfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5936 // Two-operand variants for VEXT
5937 def : NEONInstAlias<"vext${p}.8 $Vdn, $Vm, $imm",
5938 (VEXTd8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_7:$imm, pred:$p)>;
5939 def : NEONInstAlias<"vext${p}.16 $Vdn, $Vm, $imm",
5940 (VEXTd16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_3:$imm, pred:$p)>;
5941 def : NEONInstAlias<"vext${p}.32 $Vdn, $Vm, $imm",
5942 (VEXTd32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_1:$imm, pred:$p)>;
5944 def : NEONInstAlias<"vext${p}.8 $Vdn, $Vm, $imm",
5945 (VEXTq8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_15:$imm, pred:$p)>;
5946 def : NEONInstAlias<"vext${p}.16 $Vdn, $Vm, $imm",
5947 (VEXTq16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_7:$imm, pred:$p)>;
5948 def : NEONInstAlias<"vext${p}.32 $Vdn, $Vm, $imm",
5949 (VEXTq32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_3:$imm, pred:$p)>;
5950 def : NEONInstAlias<"vext${p}.64 $Vdn, $Vm, $imm",
5951 (VEXTq64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_1:$imm, pred:$p)>;
5953 // Two-operand variants for VQDMULH
5954 def : NEONInstAlias<"vqdmulh${p}.s16 $Vdn, $Vm",
5955 (VQDMULHv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5956 def : NEONInstAlias<"vqdmulh${p}.s32 $Vdn, $Vm",
5957 (VQDMULHv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5959 def : NEONInstAlias<"vqdmulh${p}.s16 $Vdn, $Vm",
5960 (VQDMULHv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5961 def : NEONInstAlias<"vqdmulh${p}.s32 $Vdn, $Vm",
5962 (VQDMULHv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5964 // Two-operand variants for VMAX.
5965 def : NEONInstAlias<"vmax${p}.s8 $Vdn, $Vm",
5966 (VMAXsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5967 def : NEONInstAlias<"vmax${p}.s16 $Vdn, $Vm",
5968 (VMAXsv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5969 def : NEONInstAlias<"vmax${p}.s32 $Vdn, $Vm",
5970 (VMAXsv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5971 def : NEONInstAlias<"vmax${p}.u8 $Vdn, $Vm",
5972 (VMAXuv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5973 def : NEONInstAlias<"vmax${p}.u16 $Vdn, $Vm",
5974 (VMAXuv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5975 def : NEONInstAlias<"vmax${p}.u32 $Vdn, $Vm",
5976 (VMAXuv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5977 def : NEONInstAlias<"vmax${p}.f32 $Vdn, $Vm",
5978 (VMAXfd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5980 def : NEONInstAlias<"vmax${p}.s8 $Vdn, $Vm",
5981 (VMAXsv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5982 def : NEONInstAlias<"vmax${p}.s16 $Vdn, $Vm",
5983 (VMAXsv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5984 def : NEONInstAlias<"vmax${p}.s32 $Vdn, $Vm",
5985 (VMAXsv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5986 def : NEONInstAlias<"vmax${p}.u8 $Vdn, $Vm",
5987 (VMAXuv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5988 def : NEONInstAlias<"vmax${p}.u16 $Vdn, $Vm",
5989 (VMAXuv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5990 def : NEONInstAlias<"vmax${p}.u32 $Vdn, $Vm",
5991 (VMAXuv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5992 def : NEONInstAlias<"vmax${p}.f32 $Vdn, $Vm",
5993 (VMAXfq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5995 // Two-operand variants for VMIN.
5996 def : NEONInstAlias<"vmin${p}.s8 $Vdn, $Vm",
5997 (VMINsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5998 def : NEONInstAlias<"vmin${p}.s16 $Vdn, $Vm",
5999 (VMINsv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6000 def : NEONInstAlias<"vmin${p}.s32 $Vdn, $Vm",
6001 (VMINsv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6002 def : NEONInstAlias<"vmin${p}.u8 $Vdn, $Vm",
6003 (VMINuv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6004 def : NEONInstAlias<"vmin${p}.u16 $Vdn, $Vm",
6005 (VMINuv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6006 def : NEONInstAlias<"vmin${p}.u32 $Vdn, $Vm",
6007 (VMINuv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6008 def : NEONInstAlias<"vmin${p}.f32 $Vdn, $Vm",
6009 (VMINfd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6011 def : NEONInstAlias<"vmin${p}.s8 $Vdn, $Vm",
6012 (VMINsv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6013 def : NEONInstAlias<"vmin${p}.s16 $Vdn, $Vm",
6014 (VMINsv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6015 def : NEONInstAlias<"vmin${p}.s32 $Vdn, $Vm",
6016 (VMINsv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6017 def : NEONInstAlias<"vmin${p}.u8 $Vdn, $Vm",
6018 (VMINuv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6019 def : NEONInstAlias<"vmin${p}.u16 $Vdn, $Vm",
6020 (VMINuv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6021 def : NEONInstAlias<"vmin${p}.u32 $Vdn, $Vm",
6022 (VMINuv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6023 def : NEONInstAlias<"vmin${p}.f32 $Vdn, $Vm",
6024 (VMINfq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6026 // Two-operand variants for VPADD.
6027 def : NEONInstAlias<"vpadd${p}.i8 $Vdn, $Vm",
6028 (VPADDi8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6029 def : NEONInstAlias<"vpadd${p}.i16 $Vdn, $Vm",
6030 (VPADDi16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6031 def : NEONInstAlias<"vpadd${p}.i32 $Vdn, $Vm",
6032 (VPADDi32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6033 def : NEONInstAlias<"vpadd${p}.f32 $Vdn, $Vm",
6034 (VPADDf DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6036 // VSWP allows, but does not require, a type suffix.
6037 defm : VFPDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
6038 (VSWPd DPR:$Vd, DPR:$Vm, pred:$p)>;
6039 defm : VFPDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
6040 (VSWPq QPR:$Vd, QPR:$Vm, pred:$p)>;
6042 // "vmov Rd, #-imm" can be handled via "vmvn".
6043 def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
6044 (VMVNv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
6045 def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
6046 (VMVNv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
6047 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
6048 (VMOVv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
6049 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
6050 (VMOVv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
6052 // 'gas' compatibility aliases for quad-word instructions. Strictly speaking,
6053 // these should restrict to just the Q register variants, but the register
6054 // classes are enough to match correctly regardless, so we keep it simple
6055 // and just use MnemonicAlias.
6056 def : NEONMnemonicAlias<"vbicq", "vbic">;
6057 def : NEONMnemonicAlias<"vandq", "vand">;
6058 def : NEONMnemonicAlias<"veorq", "veor">;
6059 def : NEONMnemonicAlias<"vorrq", "vorr">;
6061 def : NEONMnemonicAlias<"vmovq", "vmov">;
6062 def : NEONMnemonicAlias<"vmvnq", "vmvn">;
6063 // Explicit versions for floating point so that the FPImm variants get
6064 // handled early. The parser gets confused otherwise.
6065 def : NEONMnemonicAlias<"vmovq.f32", "vmov.f32">;
6066 def : NEONMnemonicAlias<"vmovq.f64", "vmov.f64">;
6068 def : NEONMnemonicAlias<"vaddq", "vadd">;
6069 def : NEONMnemonicAlias<"vsubq", "vsub">;
6071 def : NEONMnemonicAlias<"vminq", "vmin">;
6072 def : NEONMnemonicAlias<"vmaxq", "vmax">;
6074 def : NEONMnemonicAlias<"vmulq", "vmul">;
6076 def : NEONMnemonicAlias<"vabsq", "vabs">;
6078 def : NEONMnemonicAlias<"vshlq", "vshl">;
6079 def : NEONMnemonicAlias<"vshrq", "vshr">;
6081 def : NEONMnemonicAlias<"vcvtq", "vcvt">;
6083 def : NEONMnemonicAlias<"vcleq", "vcle">;
6084 def : NEONMnemonicAlias<"vceqq", "vceq">;
6086 def : NEONMnemonicAlias<"vzipq", "vzip">;
6087 def : NEONMnemonicAlias<"vswpq", "vswp">;
6089 def : NEONMnemonicAlias<"vrecpeq.f32", "vrecpe.f32">;
6090 def : NEONMnemonicAlias<"vrecpeq.u32", "vrecpe.u32">;