1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
70 // VDUPLANE can produce a quad-register result from a double-register source,
71 // so the result is not constrained to match the source.
72 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
73 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
76 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
77 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
78 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
80 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
81 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
82 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
83 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
85 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
86 SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>]>;
87 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
88 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
89 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
91 //===----------------------------------------------------------------------===//
92 // NEON operand definitions
93 //===----------------------------------------------------------------------===//
95 // addrmode_neonldstm := reg
97 /* TODO: Take advantage of vldm.
98 def addrmode_neonldstm : Operand<i32>,
99 ComplexPattern<i32, 2, "SelectAddrModeNeonLdStM", []> {
100 let PrintMethod = "printAddrNeonLdStMOperand";
101 let MIOperandInfo = (ops GPR, i32imm);
105 def h8imm : Operand<i8> {
106 let PrintMethod = "printHex8ImmOperand";
108 def h16imm : Operand<i16> {
109 let PrintMethod = "printHex16ImmOperand";
111 def h32imm : Operand<i32> {
112 let PrintMethod = "printHex32ImmOperand";
114 def h64imm : Operand<i64> {
115 let PrintMethod = "printHex64ImmOperand";
118 //===----------------------------------------------------------------------===//
119 // NEON load / store instructions
120 //===----------------------------------------------------------------------===//
122 /* TODO: Take advantage of vldm.
123 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
124 def VLDMD : NI<(outs),
125 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
127 "vldm${addr:submode} ${addr:base}, $dst1",
129 let Inst{27-25} = 0b110;
131 let Inst{11-9} = 0b101;
134 def VLDMS : NI<(outs),
135 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
137 "vldm${addr:submode} ${addr:base}, $dst1",
139 let Inst{27-25} = 0b110;
141 let Inst{11-9} = 0b101;
146 // Use vldmia to load a Q register as a D register pair.
147 def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr),
149 "vldmia\t$addr, ${dst:dregpair}",
150 [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]> {
151 let Inst{27-25} = 0b110;
152 let Inst{24} = 0; // P bit
153 let Inst{23} = 1; // U bit
155 let Inst{11-9} = 0b101;
158 // Use vstmia to store a Q register as a D register pair.
159 def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr),
161 "vstmia\t$addr, ${src:dregpair}",
162 [(store (v2f64 QPR:$src), addrmode4:$addr)]> {
163 let Inst{27-25} = 0b110;
164 let Inst{24} = 0; // P bit
165 let Inst{23} = 1; // U bit
167 let Inst{11-9} = 0b101;
170 // VLD1 : Vector Load (multiple single elements)
171 class VLD1D<bits<4> op7_4, string OpcodeStr, ValueType Ty, Intrinsic IntOp>
172 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst), (ins addrmode6:$addr), IIC_VLD1,
173 !strconcat(OpcodeStr, "\t\\{$dst\\}, $addr"), "",
174 [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
175 class VLD1Q<bits<4> op7_4, string OpcodeStr, ValueType Ty, Intrinsic IntOp>
176 : NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst), (ins addrmode6:$addr), IIC_VLD1,
177 !strconcat(OpcodeStr, "\t${dst:dregpair}, $addr"), "",
178 [(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
180 def VLD1d8 : VLD1D<0b0000, "vld1.8", v8i8, int_arm_neon_vld1>;
181 def VLD1d16 : VLD1D<0b0100, "vld1.16", v4i16, int_arm_neon_vld1>;
182 def VLD1d32 : VLD1D<0b1000, "vld1.32", v2i32, int_arm_neon_vld1>;
183 def VLD1df : VLD1D<0b1000, "vld1.32", v2f32, int_arm_neon_vld1>;
184 def VLD1d64 : VLD1D<0b1100, "vld1.64", v1i64, int_arm_neon_vld1>;
186 def VLD1q8 : VLD1Q<0b0000, "vld1.8", v16i8, int_arm_neon_vld1>;
187 def VLD1q16 : VLD1Q<0b0100, "vld1.16", v8i16, int_arm_neon_vld1>;
188 def VLD1q32 : VLD1Q<0b1000, "vld1.32", v4i32, int_arm_neon_vld1>;
189 def VLD1qf : VLD1Q<0b1000, "vld1.32", v4f32, int_arm_neon_vld1>;
190 def VLD1q64 : VLD1Q<0b1100, "vld1.64", v2i64, int_arm_neon_vld1>;
192 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
194 // VLD2 : Vector Load (multiple 2-element structures)
195 class VLD2D<bits<4> op7_4, string OpcodeStr>
196 : NLdSt<0,0b10,0b1000,op7_4, (outs DPR:$dst1, DPR:$dst2),
197 (ins addrmode6:$addr), IIC_VLD2,
198 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2\\}, $addr"), "", []>;
199 class VLD2Q<bits<4> op7_4, string OpcodeStr>
200 : NLdSt<0,0b10,0b0011,op7_4,
201 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
202 (ins addrmode6:$addr), IIC_VLD2,
203 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"),
206 def VLD2d8 : VLD2D<0b0000, "vld2.8">;
207 def VLD2d16 : VLD2D<0b0100, "vld2.16">;
208 def VLD2d32 : VLD2D<0b1000, "vld2.32">;
209 def VLD2d64 : NLdSt<0,0b10,0b1010,0b1100, (outs DPR:$dst1, DPR:$dst2),
210 (ins addrmode6:$addr), IIC_VLD1,
211 "vld1.64\t\\{$dst1,$dst2\\}, $addr", "", []>;
213 def VLD2q8 : VLD2Q<0b0000, "vld2.8">;
214 def VLD2q16 : VLD2Q<0b0100, "vld2.16">;
215 def VLD2q32 : VLD2Q<0b1000, "vld2.32">;
217 // VLD3 : Vector Load (multiple 3-element structures)
218 class VLD3D<bits<4> op7_4, string OpcodeStr>
219 : NLdSt<0,0b10,0b0100,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
220 (ins addrmode6:$addr), IIC_VLD3,
221 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"), "", []>;
222 class VLD3WB<bits<4> op7_4, string OpcodeStr>
223 : NLdSt<0,0b10,0b0101,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
224 (ins addrmode6:$addr), IIC_VLD3,
225 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"),
226 "$addr.addr = $wb", []>;
228 def VLD3d8 : VLD3D<0b0000, "vld3.8">;
229 def VLD3d16 : VLD3D<0b0100, "vld3.16">;
230 def VLD3d32 : VLD3D<0b1000, "vld3.32">;
231 def VLD3d64 : NLdSt<0,0b10,0b0110,0b1100,
232 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
233 (ins addrmode6:$addr), IIC_VLD1,
234 "vld1.64\t\\{$dst1,$dst2,$dst3\\}, $addr", "", []>;
236 // vld3 to double-spaced even registers.
237 def VLD3q8a : VLD3WB<0b0000, "vld3.8">;
238 def VLD3q16a : VLD3WB<0b0100, "vld3.16">;
239 def VLD3q32a : VLD3WB<0b1000, "vld3.32">;
241 // vld3 to double-spaced odd registers.
242 def VLD3q8b : VLD3WB<0b0000, "vld3.8">;
243 def VLD3q16b : VLD3WB<0b0100, "vld3.16">;
244 def VLD3q32b : VLD3WB<0b1000, "vld3.32">;
246 // VLD4 : Vector Load (multiple 4-element structures)
247 class VLD4D<bits<4> op7_4, string OpcodeStr>
248 : NLdSt<0,0b10,0b0000,op7_4,
249 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
250 (ins addrmode6:$addr), IIC_VLD4,
251 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"),
253 class VLD4WB<bits<4> op7_4, string OpcodeStr>
254 : NLdSt<0,0b10,0b0001,op7_4,
255 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
256 (ins addrmode6:$addr), IIC_VLD4,
257 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"),
258 "$addr.addr = $wb", []>;
260 def VLD4d8 : VLD4D<0b0000, "vld4.8">;
261 def VLD4d16 : VLD4D<0b0100, "vld4.16">;
262 def VLD4d32 : VLD4D<0b1000, "vld4.32">;
263 def VLD4d64 : NLdSt<0,0b10,0b0010,0b1100,
264 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
265 (ins addrmode6:$addr), IIC_VLD1,
266 "vld1.64\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr", "", []>;
268 // vld4 to double-spaced even registers.
269 def VLD4q8a : VLD4WB<0b0000, "vld4.8">;
270 def VLD4q16a : VLD4WB<0b0100, "vld4.16">;
271 def VLD4q32a : VLD4WB<0b1000, "vld4.32">;
273 // vld4 to double-spaced odd registers.
274 def VLD4q8b : VLD4WB<0b0000, "vld4.8">;
275 def VLD4q16b : VLD4WB<0b0100, "vld4.16">;
276 def VLD4q32b : VLD4WB<0b1000, "vld4.32">;
278 // VLD1LN : Vector Load (single element to one lane)
279 // FIXME: Not yet implemented.
281 // VLD2LN : Vector Load (single 2-element structure to one lane)
282 class VLD2LN<bits<4> op11_8, string OpcodeStr>
283 : NLdStLN<1,0b10,op11_8, (outs DPR:$dst1, DPR:$dst2),
284 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
286 !strconcat(OpcodeStr, "\t\\{$dst1[$lane],$dst2[$lane]\\}, $addr"),
287 "$src1 = $dst1, $src2 = $dst2", []>;
289 // vld2 to single-spaced registers.
290 def VLD2LNd8 : VLD2LN<0b0001, "vld2.8">;
291 def VLD2LNd16 : VLD2LN<0b0101, "vld2.16"> {
294 def VLD2LNd32 : VLD2LN<0b1001, "vld2.32"> {
298 // vld2 to double-spaced even registers.
299 def VLD2LNq16a: VLD2LN<0b0101, "vld2.16"> {
302 def VLD2LNq32a: VLD2LN<0b1001, "vld2.32"> {
306 // vld2 to double-spaced odd registers.
307 def VLD2LNq16b: VLD2LN<0b0101, "vld2.16"> {
310 def VLD2LNq32b: VLD2LN<0b1001, "vld2.32"> {
314 // VLD3LN : Vector Load (single 3-element structure to one lane)
315 class VLD3LN<bits<4> op11_8, string OpcodeStr>
316 : NLdStLN<1,0b10,op11_8, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
317 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
318 nohash_imm:$lane), IIC_VLD3,
319 !strconcat(OpcodeStr,
320 "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane]\\}, $addr"),
321 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
323 // vld3 to single-spaced registers.
324 def VLD3LNd8 : VLD3LN<0b0010, "vld3.8"> {
327 def VLD3LNd16 : VLD3LN<0b0110, "vld3.16"> {
328 let Inst{5-4} = 0b00;
330 def VLD3LNd32 : VLD3LN<0b1010, "vld3.32"> {
331 let Inst{6-4} = 0b000;
334 // vld3 to double-spaced even registers.
335 def VLD3LNq16a: VLD3LN<0b0110, "vld3.16"> {
336 let Inst{5-4} = 0b10;
338 def VLD3LNq32a: VLD3LN<0b1010, "vld3.32"> {
339 let Inst{6-4} = 0b100;
342 // vld3 to double-spaced odd registers.
343 def VLD3LNq16b: VLD3LN<0b0110, "vld3.16"> {
344 let Inst{5-4} = 0b10;
346 def VLD3LNq32b: VLD3LN<0b1010, "vld3.32"> {
347 let Inst{6-4} = 0b100;
350 // VLD4LN : Vector Load (single 4-element structure to one lane)
351 class VLD4LN<bits<4> op11_8, string OpcodeStr>
352 : NLdStLN<1,0b10,op11_8,
353 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
354 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
355 nohash_imm:$lane), IIC_VLD4,
356 !strconcat(OpcodeStr,
357 "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane],$dst4[$lane]\\}, $addr"),
358 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
360 // vld4 to single-spaced registers.
361 def VLD4LNd8 : VLD4LN<0b0011, "vld4.8">;
362 def VLD4LNd16 : VLD4LN<0b0111, "vld4.16"> {
365 def VLD4LNd32 : VLD4LN<0b1011, "vld4.32"> {
369 // vld4 to double-spaced even registers.
370 def VLD4LNq16a: VLD4LN<0b0111, "vld4.16"> {
373 def VLD4LNq32a: VLD4LN<0b1011, "vld4.32"> {
377 // vld4 to double-spaced odd registers.
378 def VLD4LNq16b: VLD4LN<0b0111, "vld4.16"> {
381 def VLD4LNq32b: VLD4LN<0b1011, "vld4.32"> {
385 // VLD1DUP : Vector Load (single element to all lanes)
386 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
387 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
388 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
389 // FIXME: Not yet implemented.
390 } // mayLoad = 1, hasExtraDefRegAllocReq = 1
392 // VST1 : Vector Store (multiple single elements)
393 class VST1D<bits<4> op7_4, string OpcodeStr, ValueType Ty, Intrinsic IntOp>
394 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src), IIC_VST,
395 !strconcat(OpcodeStr, "\t\\{$src\\}, $addr"), "",
396 [(IntOp addrmode6:$addr, (Ty DPR:$src))]>;
397 class VST1Q<bits<4> op7_4, string OpcodeStr, ValueType Ty, Intrinsic IntOp>
398 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$addr, QPR:$src), IIC_VST,
399 !strconcat(OpcodeStr, "\t${src:dregpair}, $addr"), "",
400 [(IntOp addrmode6:$addr, (Ty QPR:$src))]>;
402 let hasExtraSrcRegAllocReq = 1 in {
403 def VST1d8 : VST1D<0b0000, "vst1.8", v8i8, int_arm_neon_vst1>;
404 def VST1d16 : VST1D<0b0100, "vst1.16", v4i16, int_arm_neon_vst1>;
405 def VST1d32 : VST1D<0b1000, "vst1.32", v2i32, int_arm_neon_vst1>;
406 def VST1df : VST1D<0b1000, "vst1.32", v2f32, int_arm_neon_vst1>;
407 def VST1d64 : VST1D<0b1100, "vst1.64", v1i64, int_arm_neon_vst1>;
409 def VST1q8 : VST1Q<0b0000, "vst1.8", v16i8, int_arm_neon_vst1>;
410 def VST1q16 : VST1Q<0b0100, "vst1.16", v8i16, int_arm_neon_vst1>;
411 def VST1q32 : VST1Q<0b1000, "vst1.32", v4i32, int_arm_neon_vst1>;
412 def VST1qf : VST1Q<0b1000, "vst1.32", v4f32, int_arm_neon_vst1>;
413 def VST1q64 : VST1Q<0b1100, "vst1.64", v2i64, int_arm_neon_vst1>;
414 } // hasExtraSrcRegAllocReq
416 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
418 // VST2 : Vector Store (multiple 2-element structures)
419 class VST2D<bits<4> op7_4, string OpcodeStr>
420 : NLdSt<0,0b00,0b1000,op7_4, (outs),
421 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
422 !strconcat(OpcodeStr, "\t\\{$src1,$src2\\}, $addr"), "", []>;
423 class VST2Q<bits<4> op7_4, string OpcodeStr>
424 : NLdSt<0,0b00,0b0011,op7_4, (outs),
425 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
427 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"),
430 def VST2d8 : VST2D<0b0000, "vst2.8">;
431 def VST2d16 : VST2D<0b0100, "vst2.16">;
432 def VST2d32 : VST2D<0b1000, "vst2.32">;
433 def VST2d64 : NLdSt<0,0b00,0b1010,0b1100, (outs),
434 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
435 "vst1.64\t\\{$src1,$src2\\}, $addr", "", []>;
437 def VST2q8 : VST2Q<0b0000, "vst2.8">;
438 def VST2q16 : VST2Q<0b0100, "vst2.16">;
439 def VST2q32 : VST2Q<0b1000, "vst2.32">;
441 // VST3 : Vector Store (multiple 3-element structures)
442 class VST3D<bits<4> op7_4, string OpcodeStr>
443 : NLdSt<0,0b00,0b0100,op7_4, (outs),
444 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
445 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"), "", []>;
446 class VST3WB<bits<4> op7_4, string OpcodeStr>
447 : NLdSt<0,0b00,0b0101,op7_4, (outs GPR:$wb),
448 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
449 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"),
450 "$addr.addr = $wb", []>;
452 def VST3d8 : VST3D<0b0000, "vst3.8">;
453 def VST3d16 : VST3D<0b0100, "vst3.16">;
454 def VST3d32 : VST3D<0b1000, "vst3.32">;
455 def VST3d64 : NLdSt<0,0b00,0b0110,0b1100, (outs),
456 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
458 "vst1.64\t\\{$src1,$src2,$src3\\}, $addr", "", []>;
460 // vst3 to double-spaced even registers.
461 def VST3q8a : VST3WB<0b0000, "vst3.8">;
462 def VST3q16a : VST3WB<0b0100, "vst3.16">;
463 def VST3q32a : VST3WB<0b1000, "vst3.32">;
465 // vst3 to double-spaced odd registers.
466 def VST3q8b : VST3WB<0b0000, "vst3.8">;
467 def VST3q16b : VST3WB<0b0100, "vst3.16">;
468 def VST3q32b : VST3WB<0b1000, "vst3.32">;
470 // VST4 : Vector Store (multiple 4-element structures)
471 class VST4D<bits<4> op7_4, string OpcodeStr>
472 : NLdSt<0,0b00,0b0000,op7_4, (outs),
473 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
475 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"),
477 class VST4WB<bits<4> op7_4, string OpcodeStr>
478 : NLdSt<0,0b00,0b0001,op7_4, (outs GPR:$wb),
479 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
481 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"),
482 "$addr.addr = $wb", []>;
484 def VST4d8 : VST4D<0b0000, "vst4.8">;
485 def VST4d16 : VST4D<0b0100, "vst4.16">;
486 def VST4d32 : VST4D<0b1000, "vst4.32">;
487 def VST4d64 : NLdSt<0,0b00,0b0010,0b1100, (outs),
488 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
490 "vst1.64\t\\{$src1,$src2,$src3,$src4\\}, $addr", "", []>;
492 // vst4 to double-spaced even registers.
493 def VST4q8a : VST4WB<0b0000, "vst4.8">;
494 def VST4q16a : VST4WB<0b0100, "vst4.16">;
495 def VST4q32a : VST4WB<0b1000, "vst4.32">;
497 // vst4 to double-spaced odd registers.
498 def VST4q8b : VST4WB<0b0000, "vst4.8">;
499 def VST4q16b : VST4WB<0b0100, "vst4.16">;
500 def VST4q32b : VST4WB<0b1000, "vst4.32">;
502 // VST1LN : Vector Store (single element from one lane)
503 // FIXME: Not yet implemented.
505 // VST2LN : Vector Store (single 2-element structure from one lane)
506 class VST2LN<bits<4> op11_8, string OpcodeStr>
507 : NLdStLN<1,0b00,op11_8, (outs),
508 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
510 !strconcat(OpcodeStr, "\t\\{$src1[$lane],$src2[$lane]\\}, $addr"),
513 // vst2 to single-spaced registers.
514 def VST2LNd8 : VST2LN<0b0001, "vst2.8">;
515 def VST2LNd16 : VST2LN<0b0101, "vst2.16"> {
518 def VST2LNd32 : VST2LN<0b1001, "vst2.32"> {
522 // vst2 to double-spaced even registers.
523 def VST2LNq16a: VST2LN<0b0101, "vst2.16"> {
526 def VST2LNq32a: VST2LN<0b1001, "vst2.32"> {
530 // vst2 to double-spaced odd registers.
531 def VST2LNq16b: VST2LN<0b0101, "vst2.16"> {
534 def VST2LNq32b: VST2LN<0b1001, "vst2.32"> {
538 // VST3LN : Vector Store (single 3-element structure from one lane)
539 class VST3LN<bits<4> op11_8, string OpcodeStr>
540 : NLdStLN<1,0b00,op11_8, (outs),
541 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
542 nohash_imm:$lane), IIC_VST,
543 !strconcat(OpcodeStr,
544 "\t\\{$src1[$lane],$src2[$lane],$src3[$lane]\\}, $addr"), "", []>;
546 // vst3 to single-spaced registers.
547 def VST3LNd8 : VST3LN<0b0010, "vst3.8"> {
550 def VST3LNd16 : VST3LN<0b0110, "vst3.16"> {
551 let Inst{5-4} = 0b00;
553 def VST3LNd32 : VST3LN<0b1010, "vst3.32"> {
554 let Inst{6-4} = 0b000;
557 // vst3 to double-spaced even registers.
558 def VST3LNq16a: VST3LN<0b0110, "vst3.16"> {
559 let Inst{5-4} = 0b10;
561 def VST3LNq32a: VST3LN<0b1010, "vst3.32"> {
562 let Inst{6-4} = 0b100;
565 // vst3 to double-spaced odd registers.
566 def VST3LNq16b: VST3LN<0b0110, "vst3.16"> {
567 let Inst{5-4} = 0b10;
569 def VST3LNq32b: VST3LN<0b1010, "vst3.32"> {
570 let Inst{6-4} = 0b100;
573 // VST4LN : Vector Store (single 4-element structure from one lane)
574 class VST4LN<bits<4> op11_8, string OpcodeStr>
575 : NLdStLN<1,0b00,op11_8, (outs),
576 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
577 nohash_imm:$lane), IIC_VST,
578 !strconcat(OpcodeStr,
579 "\t\\{$src1[$lane],$src2[$lane],$src3[$lane],$src4[$lane]\\}, $addr"),
582 // vst4 to single-spaced registers.
583 def VST4LNd8 : VST4LN<0b0011, "vst4.8">;
584 def VST4LNd16 : VST4LN<0b0111, "vst4.16"> {
587 def VST4LNd32 : VST4LN<0b1011, "vst4.32"> {
591 // vst4 to double-spaced even registers.
592 def VST4LNq16a: VST4LN<0b0111, "vst4.16"> {
595 def VST4LNq32a: VST4LN<0b1011, "vst4.32"> {
599 // vst4 to double-spaced odd registers.
600 def VST4LNq16b: VST4LN<0b0111, "vst4.16"> {
603 def VST4LNq32b: VST4LN<0b1011, "vst4.32"> {
607 } // mayStore = 1, hasExtraSrcRegAllocReq = 1
610 //===----------------------------------------------------------------------===//
611 // NEON pattern fragments
612 //===----------------------------------------------------------------------===//
614 // Extract D sub-registers of Q registers.
615 // (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
616 def DSubReg_i8_reg : SDNodeXForm<imm, [{
617 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
619 def DSubReg_i16_reg : SDNodeXForm<imm, [{
620 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
622 def DSubReg_i32_reg : SDNodeXForm<imm, [{
623 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
625 def DSubReg_f64_reg : SDNodeXForm<imm, [{
626 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
628 def DSubReg_f64_other_reg : SDNodeXForm<imm, [{
629 return CurDAG->getTargetConstant(5 + (1 - N->getZExtValue()), MVT::i32);
632 // Extract S sub-registers of Q/D registers.
633 // (arm_ssubreg_0 is 1; arm_ssubreg_1 is 2; etc.)
634 def SSubReg_f32_reg : SDNodeXForm<imm, [{
635 return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32);
638 // Translate lane numbers from Q registers to D subregs.
639 def SubReg_i8_lane : SDNodeXForm<imm, [{
640 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
642 def SubReg_i16_lane : SDNodeXForm<imm, [{
643 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
645 def SubReg_i32_lane : SDNodeXForm<imm, [{
646 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
649 //===----------------------------------------------------------------------===//
650 // Instruction Classes
651 //===----------------------------------------------------------------------===//
653 // Basic 2-register operations, both double- and quad-register.
654 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
655 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
656 ValueType ResTy, ValueType OpTy, SDNode OpNode>
657 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
658 (ins DPR:$src), IIC_VUNAD, !strconcat(OpcodeStr, "\t$dst, $src"), "",
659 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
660 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
661 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
662 ValueType ResTy, ValueType OpTy, SDNode OpNode>
663 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
664 (ins QPR:$src), IIC_VUNAQ, !strconcat(OpcodeStr, "\t$dst, $src"), "",
665 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
667 // Basic 2-register operations, scalar single-precision.
668 class N2VDs<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
669 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
670 ValueType ResTy, ValueType OpTy, SDNode OpNode>
671 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
672 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
673 IIC_VUNAD, !strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
675 class N2VDsPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
676 : NEONFPPat<(ResTy (OpNode SPR:$a)),
678 (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
681 // Basic 2-register intrinsics, both double- and quad-register.
682 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
683 bits<2> op17_16, bits<5> op11_7, bit op4,
684 InstrItinClass itin, string OpcodeStr,
685 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
686 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
687 (ins DPR:$src), itin, !strconcat(OpcodeStr, "\t$dst, $src"), "",
688 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
689 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
690 bits<2> op17_16, bits<5> op11_7, bit op4,
691 InstrItinClass itin, string OpcodeStr,
692 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
693 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
694 (ins QPR:$src), itin, !strconcat(OpcodeStr, "\t$dst, $src"), "",
695 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
697 // Basic 2-register intrinsics, scalar single-precision
698 class N2VDInts<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
699 bits<2> op17_16, bits<5> op11_7, bit op4,
700 InstrItinClass itin, string OpcodeStr,
701 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
702 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
703 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), itin,
704 !strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
706 class N2VDIntsPat<SDNode OpNode, NeonI Inst>
707 : NEONFPPat<(f32 (OpNode SPR:$a)),
709 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
712 // Narrow 2-register intrinsics.
713 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
714 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
715 InstrItinClass itin, string OpcodeStr,
716 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
717 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
718 (ins QPR:$src), itin, !strconcat(OpcodeStr, "\t$dst, $src"), "",
719 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
721 // Long 2-register intrinsics (currently only used for VMOVL).
722 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
723 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
724 InstrItinClass itin, string OpcodeStr,
725 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
726 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$dst),
727 (ins DPR:$src), itin, !strconcat(OpcodeStr, "\t$dst, $src"), "",
728 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
730 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
731 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr>
732 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
733 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
734 !strconcat(OpcodeStr, "\t$dst1, $dst2"),
735 "$src1 = $dst1, $src2 = $dst2", []>;
736 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
737 InstrItinClass itin, string OpcodeStr>
738 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
739 (ins QPR:$src1, QPR:$src2), itin,
740 !strconcat(OpcodeStr, "\t$dst1, $dst2"),
741 "$src1 = $dst1, $src2 = $dst2", []>;
743 // Basic 3-register operations, both double- and quad-register.
744 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
745 InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy,
746 SDNode OpNode, bit Commutable>
747 : N3V<op24, op23, op21_20, op11_8, 0, op4,
748 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
749 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
750 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
751 let isCommutable = Commutable;
753 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
754 InstrItinClass itin, string OpcodeStr, ValueType Ty, SDNode ShOp>
755 : N3V<0, 1, op21_20, op11_8, 1, 0,
756 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
757 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
759 (Ty (ShOp (Ty DPR:$src1),
760 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
762 let isCommutable = 0;
764 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
765 string OpcodeStr, ValueType Ty, SDNode ShOp>
766 : N3V<0, 1, op21_20, op11_8, 1, 0,
767 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
769 !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
771 (Ty (ShOp (Ty DPR:$src1),
772 (Ty (NEONvduplane (Ty DPR_8:$src2),
774 let isCommutable = 0;
777 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
778 InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy,
779 SDNode OpNode, bit Commutable>
780 : N3V<op24, op23, op21_20, op11_8, 1, op4,
781 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
782 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
783 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
784 let isCommutable = Commutable;
786 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
787 InstrItinClass itin, string OpcodeStr,
788 ValueType ResTy, ValueType OpTy, SDNode ShOp>
789 : N3V<1, 1, op21_20, op11_8, 1, 0,
790 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
791 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
792 [(set (ResTy QPR:$dst),
793 (ResTy (ShOp (ResTy QPR:$src1),
794 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
796 let isCommutable = 0;
798 class N3VQSL16<bits<2> op21_20, bits<4> op11_8,
799 string OpcodeStr, ValueType ResTy, ValueType OpTy, SDNode ShOp>
800 : N3V<1, 1, op21_20, op11_8, 1, 0,
801 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
803 !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
804 [(set (ResTy QPR:$dst),
805 (ResTy (ShOp (ResTy QPR:$src1),
806 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
808 let isCommutable = 0;
811 // Basic 3-register operations, scalar single-precision
812 class N3VDs<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
813 string OpcodeStr, ValueType ResTy, ValueType OpTy,
814 SDNode OpNode, bit Commutable>
815 : N3V<op24, op23, op21_20, op11_8, 0, op4,
816 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), IIC_VBIND,
817 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", []> {
818 let isCommutable = Commutable;
820 class N3VDsPat<SDNode OpNode, NeonI Inst>
821 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
823 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
824 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
827 // Basic 3-register intrinsics, both double- and quad-register.
828 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
829 InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy,
830 Intrinsic IntOp, bit Commutable>
831 : N3V<op24, op23, op21_20, op11_8, 0, op4,
832 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
833 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
834 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
835 let isCommutable = Commutable;
837 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
838 string OpcodeStr, ValueType Ty, Intrinsic IntOp>
839 : N3V<0, 1, op21_20, op11_8, 1, 0,
840 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
841 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
843 (Ty (IntOp (Ty DPR:$src1),
844 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
846 let isCommutable = 0;
848 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
849 string OpcodeStr, ValueType Ty, Intrinsic IntOp>
850 : N3V<0, 1, op21_20, op11_8, 1, 0,
851 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
852 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
854 (Ty (IntOp (Ty DPR:$src1),
855 (Ty (NEONvduplane (Ty DPR_8:$src2),
857 let isCommutable = 0;
860 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
861 InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy,
862 Intrinsic IntOp, bit Commutable>
863 : N3V<op24, op23, op21_20, op11_8, 1, op4,
864 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
865 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
866 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
867 let isCommutable = Commutable;
869 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
870 string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
871 : N3V<1, 1, op21_20, op11_8, 1, 0,
872 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
873 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
874 [(set (ResTy QPR:$dst),
875 (ResTy (IntOp (ResTy QPR:$src1),
876 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
878 let isCommutable = 0;
880 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
881 string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
882 : N3V<1, 1, op21_20, op11_8, 1, 0,
883 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
884 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
885 [(set (ResTy QPR:$dst),
886 (ResTy (IntOp (ResTy QPR:$src1),
887 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
889 let isCommutable = 0;
892 // Multiply-Add/Sub operations, both double- and quad-register.
893 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
894 InstrItinClass itin, string OpcodeStr,
895 ValueType Ty, SDNode MulOp, SDNode OpNode>
896 : N3V<op24, op23, op21_20, op11_8, 0, op4,
897 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin,
898 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
899 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
900 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
901 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
902 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode ShOp>
903 : N3V<0, 1, op21_20, op11_8, 1, 0,
905 (ins DPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
906 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
908 (Ty (ShOp (Ty DPR:$src1),
909 (Ty (MulOp DPR:$src2,
910 (Ty (NEONvduplane (Ty DPR_VFP2:$src3),
912 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
913 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode ShOp>
914 : N3V<0, 1, op21_20, op11_8, 1, 0,
916 (ins DPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
917 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
919 (Ty (ShOp (Ty DPR:$src1),
920 (Ty (MulOp DPR:$src2,
921 (Ty (NEONvduplane (Ty DPR_8:$src3),
924 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
925 InstrItinClass itin, string OpcodeStr, ValueType Ty,
926 SDNode MulOp, SDNode OpNode>
927 : N3V<op24, op23, op21_20, op11_8, 1, op4,
928 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin,
929 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
930 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
931 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
932 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
933 string OpcodeStr, ValueType ResTy, ValueType OpTy,
934 SDNode MulOp, SDNode ShOp>
935 : N3V<1, 1, op21_20, op11_8, 1, 0,
937 (ins QPR:$src1, QPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
938 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
939 [(set (ResTy QPR:$dst),
940 (ResTy (ShOp (ResTy QPR:$src1),
941 (ResTy (MulOp QPR:$src2,
942 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src3),
944 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
945 string OpcodeStr, ValueType ResTy, ValueType OpTy,
946 SDNode MulOp, SDNode ShOp>
947 : N3V<1, 1, op21_20, op11_8, 1, 0,
949 (ins QPR:$src1, QPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
950 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
951 [(set (ResTy QPR:$dst),
952 (ResTy (ShOp (ResTy QPR:$src1),
953 (ResTy (MulOp QPR:$src2,
954 (ResTy (NEONvduplane (OpTy DPR_8:$src3),
957 // Multiply-Add/Sub operations, scalar single-precision
958 class N3VDMulOps<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
959 InstrItinClass itin, string OpcodeStr,
960 ValueType Ty, SDNode MulOp, SDNode OpNode>
961 : N3V<op24, op23, op21_20, op11_8, 0, op4,
962 (outs DPR_VFP2:$dst),
963 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), itin,
964 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", []>;
966 class N3VDMulOpsPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
967 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
969 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$acc, arm_ssubreg_0),
970 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
971 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
974 // Neon 3-argument intrinsics, both double- and quad-register.
975 // The destination register is also used as the first source operand register.
976 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
977 InstrItinClass itin, string OpcodeStr,
978 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
979 : N3V<op24, op23, op21_20, op11_8, 0, op4,
980 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin,
981 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
982 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
983 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
984 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
985 InstrItinClass itin, string OpcodeStr,
986 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
987 : N3V<op24, op23, op21_20, op11_8, 1, op4,
988 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin,
989 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
990 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
991 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
993 // Neon Long 3-argument intrinsic. The destination register is
994 // a quad-register and is also used as the first source operand register.
995 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
996 InstrItinClass itin, string OpcodeStr,
997 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
998 : N3V<op24, op23, op21_20, op11_8, 0, op4,
999 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), itin,
1000 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
1002 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
1003 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1004 string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1005 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1007 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
1008 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
1009 [(set (ResTy QPR:$dst),
1010 (ResTy (IntOp (ResTy QPR:$src1),
1012 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src3),
1014 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1015 string OpcodeStr, ValueType ResTy, ValueType OpTy,
1017 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1019 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
1020 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
1021 [(set (ResTy QPR:$dst),
1022 (ResTy (IntOp (ResTy QPR:$src1),
1024 (OpTy (NEONvduplane (OpTy DPR_8:$src3),
1028 // Narrowing 3-register intrinsics.
1029 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1030 string OpcodeStr, ValueType TyD, ValueType TyQ,
1031 Intrinsic IntOp, bit Commutable>
1032 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1033 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VBINi4D,
1034 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
1035 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
1036 let isCommutable = Commutable;
1039 // Long 3-register intrinsics.
1040 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1041 InstrItinClass itin, string OpcodeStr, ValueType TyQ, ValueType TyD,
1042 Intrinsic IntOp, bit Commutable>
1043 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1044 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
1045 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
1046 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
1047 let isCommutable = Commutable;
1049 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1050 string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1051 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1052 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1053 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
1054 [(set (ResTy QPR:$dst),
1055 (ResTy (IntOp (OpTy DPR:$src1),
1056 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1058 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1059 string OpcodeStr, ValueType ResTy, ValueType OpTy,
1061 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1062 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1063 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
1064 [(set (ResTy QPR:$dst),
1065 (ResTy (IntOp (OpTy DPR:$src1),
1066 (OpTy (NEONvduplane (OpTy DPR_8:$src2),
1069 // Wide 3-register intrinsics.
1070 class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1071 string OpcodeStr, ValueType TyQ, ValueType TyD,
1072 Intrinsic IntOp, bit Commutable>
1073 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1074 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), IIC_VSUBiD,
1075 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
1076 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
1077 let isCommutable = Commutable;
1080 // Pairwise long 2-register intrinsics, both double- and quad-register.
1081 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1082 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1083 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1084 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1085 (ins DPR:$src), IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "",
1086 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
1087 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1088 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1089 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1090 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1091 (ins QPR:$src), IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "",
1092 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
1094 // Pairwise long 2-register accumulate intrinsics,
1095 // both double- and quad-register.
1096 // The destination register is also used as the first source operand register.
1097 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1098 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1099 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1100 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
1101 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), IIC_VPALiD,
1102 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
1103 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
1104 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1105 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1106 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1107 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
1108 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VPALiQ,
1109 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
1110 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
1112 // Shift by immediate,
1113 // both double- and quad-register.
1114 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1115 InstrItinClass itin, string OpcodeStr, ValueType Ty, SDNode OpNode>
1116 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1117 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), itin,
1118 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
1119 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
1120 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1121 InstrItinClass itin, string OpcodeStr, ValueType Ty, SDNode OpNode>
1122 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1123 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin,
1124 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
1125 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
1127 // Long shift by immediate.
1128 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1129 string OpcodeStr, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1130 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1131 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VSHLiD,
1132 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
1133 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
1134 (i32 imm:$SIMM))))]>;
1136 // Narrow shift by immediate.
1137 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1138 InstrItinClass itin, string OpcodeStr,
1139 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1140 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1141 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin,
1142 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
1143 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
1144 (i32 imm:$SIMM))))]>;
1146 // Shift right by immediate and accumulate,
1147 // both double- and quad-register.
1148 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1149 string OpcodeStr, ValueType Ty, SDNode ShOp>
1150 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1151 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), IIC_VPALiD,
1152 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
1153 [(set DPR:$dst, (Ty (add DPR:$src1,
1154 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
1155 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1156 string OpcodeStr, ValueType Ty, SDNode ShOp>
1157 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1158 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), IIC_VPALiD,
1159 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
1160 [(set QPR:$dst, (Ty (add QPR:$src1,
1161 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
1163 // Shift by immediate and insert,
1164 // both double- and quad-register.
1165 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1166 string OpcodeStr, ValueType Ty, SDNode ShOp>
1167 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1168 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), IIC_VSHLiD,
1169 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
1170 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
1171 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1172 string OpcodeStr, ValueType Ty, SDNode ShOp>
1173 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1174 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), IIC_VSHLiQ,
1175 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
1176 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
1178 // Convert, with fractional bits immediate,
1179 // both double- and quad-register.
1180 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1181 string OpcodeStr, ValueType ResTy, ValueType OpTy,
1183 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1184 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VUNAD,
1185 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
1186 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
1187 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1188 string OpcodeStr, ValueType ResTy, ValueType OpTy,
1190 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1191 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), IIC_VUNAQ,
1192 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
1193 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
1195 //===----------------------------------------------------------------------===//
1197 //===----------------------------------------------------------------------===//
1199 // Abbreviations used in multiclass suffixes:
1200 // Q = quarter int (8 bit) elements
1201 // H = half int (16 bit) elements
1202 // S = single int (32 bit) elements
1203 // D = double int (64 bit) elements
1205 // Neon 3-register vector operations.
1207 // First with only element sizes of 8, 16 and 32 bits:
1208 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1209 InstrItinClass itinD16, InstrItinClass itinD32,
1210 InstrItinClass itinQ16, InstrItinClass itinQ32,
1211 string OpcodeStr, SDNode OpNode, bit Commutable = 0> {
1212 // 64-bit vector types.
1213 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
1214 !strconcat(OpcodeStr, "8"), v8i8, v8i8, OpNode, Commutable>;
1215 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
1216 !strconcat(OpcodeStr, "16"), v4i16, v4i16, OpNode, Commutable>;
1217 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
1218 !strconcat(OpcodeStr, "32"), v2i32, v2i32, OpNode, Commutable>;
1220 // 128-bit vector types.
1221 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
1222 !strconcat(OpcodeStr, "8"), v16i8, v16i8, OpNode, Commutable>;
1223 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
1224 !strconcat(OpcodeStr, "16"), v8i16, v8i16, OpNode, Commutable>;
1225 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
1226 !strconcat(OpcodeStr, "32"), v4i32, v4i32, OpNode, Commutable>;
1229 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, SDNode ShOp> {
1230 def v4i16 : N3VDSL16<0b01, op11_8, !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
1231 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
1232 def v8i16 : N3VQSL16<0b01, op11_8, !strconcat(OpcodeStr, "16"), v8i16, v4i16, ShOp>;
1233 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, !strconcat(OpcodeStr, "32"), v4i32, v2i32, ShOp>;
1236 // ....then also with element size 64 bits:
1237 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1238 InstrItinClass itinD, InstrItinClass itinQ,
1239 string OpcodeStr, SDNode OpNode, bit Commutable = 0>
1240 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
1241 OpcodeStr, OpNode, Commutable> {
1242 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
1243 !strconcat(OpcodeStr, "64"), v1i64, v1i64, OpNode, Commutable>;
1244 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
1245 !strconcat(OpcodeStr, "64"), v2i64, v2i64, OpNode, Commutable>;
1249 // Neon Narrowing 2-register vector intrinsics,
1250 // source operand element sizes of 16, 32 and 64 bits:
1251 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1252 bits<5> op11_7, bit op6, bit op4,
1253 InstrItinClass itin, string OpcodeStr,
1255 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
1256 itin, !strconcat(OpcodeStr, "16"), v8i8, v8i16, IntOp>;
1257 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
1258 itin, !strconcat(OpcodeStr, "32"), v4i16, v4i32, IntOp>;
1259 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
1260 itin, !strconcat(OpcodeStr, "64"), v2i32, v2i64, IntOp>;
1264 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
1265 // source operand element sizes of 16, 32 and 64 bits:
1266 multiclass N2VLInt_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
1267 string OpcodeStr, Intrinsic IntOp> {
1268 def v8i16 : N2VLInt<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1269 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
1270 def v4i32 : N2VLInt<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1271 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
1272 def v2i64 : N2VLInt<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1273 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
1277 // Neon 3-register vector intrinsics.
1279 // First with only element sizes of 16 and 32 bits:
1280 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1281 InstrItinClass itinD16, InstrItinClass itinD32,
1282 InstrItinClass itinQ16, InstrItinClass itinQ32,
1283 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
1284 // 64-bit vector types.
1285 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, itinD16, !strconcat(OpcodeStr,"16"),
1286 v4i16, v4i16, IntOp, Commutable>;
1287 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, itinD32, !strconcat(OpcodeStr,"32"),
1288 v2i32, v2i32, IntOp, Commutable>;
1290 // 128-bit vector types.
1291 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, itinQ16, !strconcat(OpcodeStr,"16"),
1292 v8i16, v8i16, IntOp, Commutable>;
1293 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, itinQ32, !strconcat(OpcodeStr,"32"),
1294 v4i32, v4i32, IntOp, Commutable>;
1297 multiclass N3VIntSL_HS<bits<4> op11_8,
1298 InstrItinClass itinD16, InstrItinClass itinD32,
1299 InstrItinClass itinQ16, InstrItinClass itinQ32,
1300 string OpcodeStr, Intrinsic IntOp> {
1301 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16, !strconcat(OpcodeStr, "16"), v4i16, IntOp>;
1302 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32, !strconcat(OpcodeStr, "32"), v2i32, IntOp>;
1303 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16, !strconcat(OpcodeStr, "16"), v8i16, v4i16, IntOp>;
1304 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32, !strconcat(OpcodeStr, "32"), v4i32, v2i32, IntOp>;
1307 // ....then also with element size of 8 bits:
1308 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1309 InstrItinClass itinD16, InstrItinClass itinD32,
1310 InstrItinClass itinQ16, InstrItinClass itinQ32,
1311 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
1312 : N3VInt_HS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
1313 OpcodeStr, IntOp, Commutable> {
1314 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, itinD16,
1315 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp, Commutable>;
1316 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, itinQ16,
1317 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp, Commutable>;
1320 // ....then also with element size of 64 bits:
1321 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1322 InstrItinClass itinD16, InstrItinClass itinD32,
1323 InstrItinClass itinQ16, InstrItinClass itinQ32,
1324 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
1325 : N3VInt_QHS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
1326 OpcodeStr, IntOp, Commutable> {
1327 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, itinD32,
1328 !strconcat(OpcodeStr,"64"), v1i64, v1i64, IntOp, Commutable>;
1329 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, itinQ32,
1330 !strconcat(OpcodeStr,"64"), v2i64, v2i64, IntOp, Commutable>;
1334 // Neon Narrowing 3-register vector intrinsics,
1335 // source operand element sizes of 16, 32 and 64 bits:
1336 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1337 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
1338 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr,"16"),
1339 v8i8, v8i16, IntOp, Commutable>;
1340 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"32"),
1341 v4i16, v4i32, IntOp, Commutable>;
1342 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"64"),
1343 v2i32, v2i64, IntOp, Commutable>;
1347 // Neon Long 3-register vector intrinsics.
1349 // First with only element sizes of 16 and 32 bits:
1350 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1351 InstrItinClass itin, string OpcodeStr,
1352 Intrinsic IntOp, bit Commutable = 0> {
1353 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin,
1354 !strconcat(OpcodeStr,"16"), v4i32, v4i16, IntOp, Commutable>;
1355 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin,
1356 !strconcat(OpcodeStr,"32"), v2i64, v2i32, IntOp, Commutable>;
1359 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
1360 InstrItinClass itin, string OpcodeStr, Intrinsic IntOp> {
1361 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
1362 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
1363 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
1364 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
1367 // ....then also with element size of 8 bits:
1368 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1369 InstrItinClass itin, string OpcodeStr,
1370 Intrinsic IntOp, bit Commutable = 0>
1371 : N3VLInt_HS<op24, op23, op11_8, op4, itin, OpcodeStr, IntOp, Commutable> {
1372 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin,
1373 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp, Commutable>;
1377 // Neon Wide 3-register vector intrinsics,
1378 // source operand element sizes of 8, 16 and 32 bits:
1379 multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1380 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
1381 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
1382 v8i16, v8i8, IntOp, Commutable>;
1383 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
1384 v4i32, v4i16, IntOp, Commutable>;
1385 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
1386 v2i64, v2i32, IntOp, Commutable>;
1390 // Neon Multiply-Op vector operations,
1391 // element sizes of 8, 16 and 32 bits:
1392 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1393 InstrItinClass itinD16, InstrItinClass itinD32,
1394 InstrItinClass itinQ16, InstrItinClass itinQ32,
1395 string OpcodeStr, SDNode OpNode> {
1396 // 64-bit vector types.
1397 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
1398 !strconcat(OpcodeStr, "8"), v8i8, mul, OpNode>;
1399 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
1400 !strconcat(OpcodeStr, "16"), v4i16, mul, OpNode>;
1401 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
1402 !strconcat(OpcodeStr, "32"), v2i32, mul, OpNode>;
1404 // 128-bit vector types.
1405 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
1406 !strconcat(OpcodeStr, "8"), v16i8, mul, OpNode>;
1407 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
1408 !strconcat(OpcodeStr, "16"), v8i16, mul, OpNode>;
1409 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
1410 !strconcat(OpcodeStr, "32"), v4i32, mul, OpNode>;
1413 multiclass N3VMulOpSL_HS<bits<4> op11_8,
1414 InstrItinClass itinD16, InstrItinClass itinD32,
1415 InstrItinClass itinQ16, InstrItinClass itinQ32,
1416 string OpcodeStr, SDNode ShOp> {
1417 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
1418 !strconcat(OpcodeStr, "16"), v4i16, mul, ShOp>;
1419 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
1420 !strconcat(OpcodeStr, "32"), v2i32, mul, ShOp>;
1421 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
1422 !strconcat(OpcodeStr, "16"), v8i16, v4i16, mul, ShOp>;
1423 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
1424 !strconcat(OpcodeStr, "32"), v4i32, v2i32, mul, ShOp>;
1427 // Neon 3-argument intrinsics,
1428 // element sizes of 8, 16 and 32 bits:
1429 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1430 string OpcodeStr, Intrinsic IntOp> {
1431 // 64-bit vector types.
1432 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16D,
1433 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
1434 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
1435 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
1436 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32D,
1437 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
1439 // 128-bit vector types.
1440 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16Q,
1441 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
1442 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16Q,
1443 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
1444 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32Q,
1445 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
1449 // Neon Long 3-argument intrinsics.
1451 // First with only element sizes of 16 and 32 bits:
1452 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1453 string OpcodeStr, Intrinsic IntOp> {
1454 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
1455 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
1456 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi16D,
1457 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
1460 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
1461 string OpcodeStr, Intrinsic IntOp> {
1462 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
1463 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
1464 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
1465 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
1468 // ....then also with element size of 8 bits:
1469 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1470 string OpcodeStr, Intrinsic IntOp>
1471 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp> {
1472 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16D,
1473 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
1477 // Neon 2-register vector intrinsics,
1478 // element sizes of 8, 16 and 32 bits:
1479 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1480 bits<5> op11_7, bit op4,
1481 InstrItinClass itinD, InstrItinClass itinQ,
1482 string OpcodeStr, Intrinsic IntOp> {
1483 // 64-bit vector types.
1484 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1485 itinD, !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
1486 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1487 itinD, !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
1488 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1489 itinD, !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
1491 // 128-bit vector types.
1492 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1493 itinQ, !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
1494 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1495 itinQ, !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
1496 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1497 itinQ, !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
1501 // Neon Pairwise long 2-register intrinsics,
1502 // element sizes of 8, 16 and 32 bits:
1503 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1504 bits<5> op11_7, bit op4,
1505 string OpcodeStr, Intrinsic IntOp> {
1506 // 64-bit vector types.
1507 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1508 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
1509 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1510 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
1511 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1512 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
1514 // 128-bit vector types.
1515 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1516 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
1517 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1518 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
1519 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1520 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
1524 // Neon Pairwise long 2-register accumulate intrinsics,
1525 // element sizes of 8, 16 and 32 bits:
1526 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1527 bits<5> op11_7, bit op4,
1528 string OpcodeStr, Intrinsic IntOp> {
1529 // 64-bit vector types.
1530 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1531 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
1532 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1533 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
1534 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1535 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
1537 // 128-bit vector types.
1538 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1539 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
1540 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1541 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
1542 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1543 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
1547 // Neon 2-register vector shift by immediate,
1548 // element sizes of 8, 16, 32 and 64 bits:
1549 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1550 InstrItinClass itin, string OpcodeStr, SDNode OpNode> {
1551 // 64-bit vector types.
1552 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
1553 !strconcat(OpcodeStr, "8"), v8i8, OpNode> {
1554 let Inst{21-19} = 0b001; // imm6 = 001xxx
1556 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
1557 !strconcat(OpcodeStr, "16"), v4i16, OpNode> {
1558 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1560 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
1561 !strconcat(OpcodeStr, "32"), v2i32, OpNode> {
1562 let Inst{21} = 0b1; // imm6 = 1xxxxx
1564 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, itin,
1565 !strconcat(OpcodeStr, "64"), v1i64, OpNode>;
1568 // 128-bit vector types.
1569 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
1570 !strconcat(OpcodeStr, "8"), v16i8, OpNode> {
1571 let Inst{21-19} = 0b001; // imm6 = 001xxx
1573 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
1574 !strconcat(OpcodeStr, "16"), v8i16, OpNode> {
1575 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1577 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
1578 !strconcat(OpcodeStr, "32"), v4i32, OpNode> {
1579 let Inst{21} = 0b1; // imm6 = 1xxxxx
1581 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, itin,
1582 !strconcat(OpcodeStr, "64"), v2i64, OpNode>;
1587 // Neon Shift-Accumulate vector operations,
1588 // element sizes of 8, 16, 32 and 64 bits:
1589 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1590 string OpcodeStr, SDNode ShOp> {
1591 // 64-bit vector types.
1592 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1593 !strconcat(OpcodeStr, "8"), v8i8, ShOp> {
1594 let Inst{21-19} = 0b001; // imm6 = 001xxx
1596 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1597 !strconcat(OpcodeStr, "16"), v4i16, ShOp> {
1598 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1600 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1601 !strconcat(OpcodeStr, "32"), v2i32, ShOp> {
1602 let Inst{21} = 0b1; // imm6 = 1xxxxx
1604 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4,
1605 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
1608 // 128-bit vector types.
1609 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1610 !strconcat(OpcodeStr, "8"), v16i8, ShOp> {
1611 let Inst{21-19} = 0b001; // imm6 = 001xxx
1613 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1614 !strconcat(OpcodeStr, "16"), v8i16, ShOp> {
1615 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1617 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1618 !strconcat(OpcodeStr, "32"), v4i32, ShOp> {
1619 let Inst{21} = 0b1; // imm6 = 1xxxxx
1621 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4,
1622 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
1627 // Neon Shift-Insert vector operations,
1628 // element sizes of 8, 16, 32 and 64 bits:
1629 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1630 string OpcodeStr, SDNode ShOp> {
1631 // 64-bit vector types.
1632 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4,
1633 !strconcat(OpcodeStr, "8"), v8i8, ShOp> {
1634 let Inst{21-19} = 0b001; // imm6 = 001xxx
1636 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4,
1637 !strconcat(OpcodeStr, "16"), v4i16, ShOp> {
1638 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1640 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4,
1641 !strconcat(OpcodeStr, "32"), v2i32, ShOp> {
1642 let Inst{21} = 0b1; // imm6 = 1xxxxx
1644 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4,
1645 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
1648 // 128-bit vector types.
1649 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4,
1650 !strconcat(OpcodeStr, "8"), v16i8, ShOp> {
1651 let Inst{21-19} = 0b001; // imm6 = 001xxx
1653 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4,
1654 !strconcat(OpcodeStr, "16"), v8i16, ShOp> {
1655 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1657 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4,
1658 !strconcat(OpcodeStr, "32"), v4i32, ShOp> {
1659 let Inst{21} = 0b1; // imm6 = 1xxxxx
1661 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4,
1662 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
1666 // Neon Shift Long operations,
1667 // element sizes of 8, 16, 32 bits:
1668 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
1669 bit op4, string OpcodeStr, SDNode OpNode> {
1670 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1671 !strconcat(OpcodeStr, "8"), v8i16, v8i8, OpNode> {
1672 let Inst{21-19} = 0b001; // imm6 = 001xxx
1674 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1675 !strconcat(OpcodeStr, "16"), v4i32, v4i16, OpNode> {
1676 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1678 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1679 !strconcat(OpcodeStr, "32"), v2i64, v2i32, OpNode> {
1680 let Inst{21} = 0b1; // imm6 = 1xxxxx
1684 // Neon Shift Narrow operations,
1685 // element sizes of 16, 32, 64 bits:
1686 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
1687 bit op4, InstrItinClass itin, string OpcodeStr,
1689 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1690 !strconcat(OpcodeStr, "16"), v8i8, v8i16, OpNode> {
1691 let Inst{21-19} = 0b001; // imm6 = 001xxx
1693 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1694 !strconcat(OpcodeStr, "32"), v4i16, v4i32, OpNode> {
1695 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1697 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1698 !strconcat(OpcodeStr, "64"), v2i32, v2i64, OpNode> {
1699 let Inst{21} = 0b1; // imm6 = 1xxxxx
1703 //===----------------------------------------------------------------------===//
1704 // Instruction Definitions.
1705 //===----------------------------------------------------------------------===//
1707 // Vector Add Operations.
1709 // VADD : Vector Add (integer and floating-point)
1710 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd.i", add, 1>;
1711 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd.f32", v2f32, v2f32, fadd, 1>;
1712 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd.f32", v4f32, v4f32, fadd, 1>;
1713 // VADDL : Vector Add Long (Q = D + D)
1714 defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, IIC_VSHLiD, "vaddl.s", int_arm_neon_vaddls, 1>;
1715 defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, IIC_VSHLiD, "vaddl.u", int_arm_neon_vaddlu, 1>;
1716 // VADDW : Vector Add Wide (Q = Q + D)
1717 defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw.s", int_arm_neon_vaddws, 0>;
1718 defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw.u", int_arm_neon_vaddwu, 0>;
1719 // VHADD : Vector Halving Add
1720 defm VHADDs : N3VInt_QHS<0,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1721 IIC_VBINi4Q, "vhadd.s", int_arm_neon_vhadds, 1>;
1722 defm VHADDu : N3VInt_QHS<1,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1723 IIC_VBINi4Q, "vhadd.u", int_arm_neon_vhaddu, 1>;
1724 // VRHADD : Vector Rounding Halving Add
1725 defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1726 IIC_VBINi4Q, "vrhadd.s", int_arm_neon_vrhadds, 1>;
1727 defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1728 IIC_VBINi4Q, "vrhadd.u", int_arm_neon_vrhaddu, 1>;
1729 // VQADD : Vector Saturating Add
1730 defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1731 IIC_VBINi4Q, "vqadd.s", int_arm_neon_vqadds, 1>;
1732 defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1733 IIC_VBINi4Q, "vqadd.u", int_arm_neon_vqaddu, 1>;
1734 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
1735 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn.i", int_arm_neon_vaddhn, 1>;
1736 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
1737 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn.i", int_arm_neon_vraddhn, 1>;
1739 // Vector Multiply Operations.
1741 // VMUL : Vector Multiply (integer, polynomial and floating-point)
1742 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D, IIC_VMULi16Q,
1743 IIC_VMULi32Q, "vmul.i", mul, 1>;
1744 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16D, "vmul.p8", v8i8, v8i8,
1745 int_arm_neon_vmulp, 1>;
1746 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16Q, "vmul.p8", v16i8, v16i8,
1747 int_arm_neon_vmulp, 1>;
1748 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VBIND, "vmul.f32", v2f32, v2f32, fmul, 1>;
1749 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VBINQ, "vmul.f32", v4f32, v4f32, fmul, 1>;
1750 defm VMULsl : N3VSL_HS<0b1000, "vmul.i", mul>;
1751 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul.f32", v2f32, fmul>;
1752 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul.f32", v4f32, v2f32, fmul>;
1753 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
1754 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
1755 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
1756 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1757 (DSubReg_i16_reg imm:$lane))),
1758 (SubReg_i16_lane imm:$lane)))>;
1759 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
1760 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
1761 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
1762 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1763 (DSubReg_i32_reg imm:$lane))),
1764 (SubReg_i32_lane imm:$lane)))>;
1765 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
1766 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
1767 (v4f32 (VMULslfq (v4f32 QPR:$src1),
1768 (v2f32 (EXTRACT_SUBREG QPR:$src2,
1769 (DSubReg_i32_reg imm:$lane))),
1770 (SubReg_i32_lane imm:$lane)))>;
1772 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
1773 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
1774 IIC_VMULi16Q, IIC_VMULi32Q,
1775 "vqdmulh.s", int_arm_neon_vqdmulh, 1>;
1776 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
1777 IIC_VMULi16Q, IIC_VMULi32Q,
1778 "vqdmulh.s", int_arm_neon_vqdmulh>;
1779 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
1780 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
1781 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
1782 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1783 (DSubReg_i16_reg imm:$lane))),
1784 (SubReg_i16_lane imm:$lane)))>;
1785 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
1786 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
1787 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
1788 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1789 (DSubReg_i32_reg imm:$lane))),
1790 (SubReg_i32_lane imm:$lane)))>;
1792 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
1793 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
1794 IIC_VMULi16Q, IIC_VMULi32Q,
1795 "vqrdmulh.s", int_arm_neon_vqrdmulh, 1>;
1796 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
1797 IIC_VMULi16Q, IIC_VMULi32Q,
1798 "vqrdmulh.s", int_arm_neon_vqrdmulh>;
1799 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
1800 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
1801 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
1802 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1803 (DSubReg_i16_reg imm:$lane))),
1804 (SubReg_i16_lane imm:$lane)))>;
1805 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
1806 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
1807 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
1808 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1809 (DSubReg_i32_reg imm:$lane))),
1810 (SubReg_i32_lane imm:$lane)))>;
1812 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
1813 defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, IIC_VMULi16D, "vmull.s", int_arm_neon_vmulls, 1>;
1814 defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, IIC_VMULi16D, "vmull.u", int_arm_neon_vmullu, 1>;
1815 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull.p8", v8i16, v8i8,
1816 int_arm_neon_vmullp, 1>;
1817 defm VMULLsls : N3VLIntSL_HS<0, 0b1010, IIC_VMULi16D, "vmull.s", int_arm_neon_vmulls>;
1818 defm VMULLslu : N3VLIntSL_HS<1, 0b1010, IIC_VMULi16D, "vmull.u", int_arm_neon_vmullu>;
1820 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
1821 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, "vqdmull.s", int_arm_neon_vqdmull, 1>;
1822 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D, "vqdmull.s", int_arm_neon_vqdmull>;
1824 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
1826 // VMLA : Vector Multiply Accumulate (integer and floating-point)
1827 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
1828 IIC_VMACi16Q, IIC_VMACi32Q, "vmla.i", add>;
1829 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla.f32", v2f32, fmul, fadd>;
1830 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla.f32", v4f32, fmul, fadd>;
1831 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
1832 IIC_VMACi16Q, IIC_VMACi32Q, "vmla.i", add>;
1833 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla.f32", v2f32, fmul, fadd>;
1834 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla.f32", v4f32, v2f32, fmul, fadd>;
1836 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
1837 (mul (v8i16 QPR:$src2),
1838 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
1839 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1),
1841 (v4i16 (EXTRACT_SUBREG QPR:$src3,
1842 (DSubReg_i16_reg imm:$lane))),
1843 (SubReg_i16_lane imm:$lane)))>;
1845 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
1846 (mul (v4i32 QPR:$src2),
1847 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
1848 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1),
1850 (v2i32 (EXTRACT_SUBREG QPR:$src3,
1851 (DSubReg_i32_reg imm:$lane))),
1852 (SubReg_i32_lane imm:$lane)))>;
1854 def : Pat<(v4f32 (fadd (v4f32 QPR:$src1),
1855 (fmul (v4f32 QPR:$src2),
1856 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
1857 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
1859 (v2f32 (EXTRACT_SUBREG QPR:$src3,
1860 (DSubReg_i32_reg imm:$lane))),
1861 (SubReg_i32_lane imm:$lane)))>;
1863 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
1864 defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal.s", int_arm_neon_vmlals>;
1865 defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal.u", int_arm_neon_vmlalu>;
1867 defm VMLALsls : N3VLInt3SL_HS<0, 0b0010, "vmlal.s", int_arm_neon_vmlals>;
1868 defm VMLALslu : N3VLInt3SL_HS<1, 0b0010, "vmlal.u", int_arm_neon_vmlalu>;
1870 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
1871 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal.s", int_arm_neon_vqdmlal>;
1872 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal.s", int_arm_neon_vqdmlal>;
1874 // VMLS : Vector Multiply Subtract (integer and floating-point)
1875 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
1876 IIC_VMACi16Q, IIC_VMACi32Q, "vmls.i", sub>;
1877 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls.f32", v2f32, fmul, fsub>;
1878 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls.f32", v4f32, fmul, fsub>;
1879 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
1880 IIC_VMACi16Q, IIC_VMACi32Q, "vmls.i", sub>;
1881 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls.f32", v2f32, fmul, fsub>;
1882 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls.f32", v4f32, v2f32, fmul, fsub>;
1884 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
1885 (mul (v8i16 QPR:$src2),
1886 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
1887 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1),
1889 (v4i16 (EXTRACT_SUBREG QPR:$src3,
1890 (DSubReg_i16_reg imm:$lane))),
1891 (SubReg_i16_lane imm:$lane)))>;
1893 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
1894 (mul (v4i32 QPR:$src2),
1895 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
1896 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1),
1898 (v2i32 (EXTRACT_SUBREG QPR:$src3,
1899 (DSubReg_i32_reg imm:$lane))),
1900 (SubReg_i32_lane imm:$lane)))>;
1902 def : Pat<(v4f32 (fsub (v4f32 QPR:$src1),
1903 (fmul (v4f32 QPR:$src2),
1904 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
1905 (v4f32 (VMLSslfq (v4f32 QPR:$src1),
1907 (v2f32 (EXTRACT_SUBREG QPR:$src3,
1908 (DSubReg_i32_reg imm:$lane))),
1909 (SubReg_i32_lane imm:$lane)))>;
1911 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
1912 defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl.s", int_arm_neon_vmlsls>;
1913 defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl.u", int_arm_neon_vmlslu>;
1915 defm VMLSLsls : N3VLInt3SL_HS<0, 0b0110, "vmlsl.s", int_arm_neon_vmlsls>;
1916 defm VMLSLslu : N3VLInt3SL_HS<1, 0b0110, "vmlsl.u", int_arm_neon_vmlslu>;
1918 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
1919 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl.s", int_arm_neon_vqdmlsl>;
1920 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl.s", int_arm_neon_vqdmlsl>;
1922 // Vector Subtract Operations.
1924 // VSUB : Vector Subtract (integer and floating-point)
1925 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ, "vsub.i", sub, 0>;
1926 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub.f32", v2f32, v2f32, fsub, 0>;
1927 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub.f32", v4f32, v4f32, fsub, 0>;
1928 // VSUBL : Vector Subtract Long (Q = D - D)
1929 defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, IIC_VSHLiD, "vsubl.s", int_arm_neon_vsubls, 1>;
1930 defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, IIC_VSHLiD, "vsubl.u", int_arm_neon_vsublu, 1>;
1931 // VSUBW : Vector Subtract Wide (Q = Q - D)
1932 defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw.s", int_arm_neon_vsubws, 0>;
1933 defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw.u", int_arm_neon_vsubwu, 0>;
1934 // VHSUB : Vector Halving Subtract
1935 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1936 IIC_VBINi4Q, "vhsub.s", int_arm_neon_vhsubs, 0>;
1937 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1938 IIC_VBINi4Q, "vhsub.u", int_arm_neon_vhsubu, 0>;
1939 // VQSUB : Vector Saturing Subtract
1940 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1941 IIC_VBINi4Q, "vqsub.s", int_arm_neon_vqsubs, 0>;
1942 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1943 IIC_VBINi4Q, "vqsub.u", int_arm_neon_vqsubu, 0>;
1944 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
1945 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn.i", int_arm_neon_vsubhn, 0>;
1946 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
1947 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn.i", int_arm_neon_vrsubhn, 0>;
1949 // Vector Comparisons.
1951 // VCEQ : Vector Compare Equal
1952 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1953 IIC_VBINi4Q, "vceq.i", NEONvceq, 1>;
1954 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq.f32", v2i32, v2f32, NEONvceq, 1>;
1955 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq.f32", v4i32, v4f32, NEONvceq, 1>;
1956 // VCGE : Vector Compare Greater Than or Equal
1957 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1958 IIC_VBINi4Q, "vcge.s", NEONvcge, 0>;
1959 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1960 IIC_VBINi4Q, "vcge.u", NEONvcgeu, 0>;
1961 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge.f32", v2i32, v2f32, NEONvcge, 0>;
1962 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge.f32", v4i32, v4f32, NEONvcge, 0>;
1963 // VCGT : Vector Compare Greater Than
1964 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1965 IIC_VBINi4Q, "vcgt.s", NEONvcgt, 0>;
1966 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1967 IIC_VBINi4Q, "vcgt.u", NEONvcgtu, 0>;
1968 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt.f32", v2i32, v2f32, NEONvcgt, 0>;
1969 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt.f32", v4i32, v4f32, NEONvcgt, 0>;
1970 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
1971 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, IIC_VBIND, "vacge.f32", v2i32, v2f32,
1972 int_arm_neon_vacged, 0>;
1973 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, IIC_VBINQ, "vacge.f32", v4i32, v4f32,
1974 int_arm_neon_vacgeq, 0>;
1975 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
1976 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, IIC_VBIND, "vacgt.f32", v2i32, v2f32,
1977 int_arm_neon_vacgtd, 0>;
1978 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, IIC_VBINQ, "vacgt.f32", v4i32, v4f32,
1979 int_arm_neon_vacgtq, 0>;
1980 // VTST : Vector Test Bits
1981 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1982 IIC_VBINi4Q, "vtst.i", NEONvtst, 1>;
1984 // Vector Bitwise Operations.
1986 // VAND : Vector Bitwise AND
1987 def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand", v2i32, v2i32, and, 1>;
1988 def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand", v4i32, v4i32, and, 1>;
1990 // VEOR : Vector Bitwise Exclusive OR
1991 def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor", v2i32, v2i32, xor, 1>;
1992 def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor", v4i32, v4i32, xor, 1>;
1994 // VORR : Vector Bitwise OR
1995 def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr", v2i32, v2i32, or, 1>;
1996 def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr", v4i32, v4i32, or, 1>;
1998 // VBIC : Vector Bitwise Bit Clear (AND NOT)
1999 def VBICd : N3V<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2000 (ins DPR:$src1, DPR:$src2), IIC_VBINiD,
2001 "vbic\t$dst, $src1, $src2", "",
2002 [(set DPR:$dst, (v2i32 (and DPR:$src1,
2003 (vnot_conv DPR:$src2))))]>;
2004 def VBICq : N3V<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2005 (ins QPR:$src1, QPR:$src2), IIC_VBINiQ,
2006 "vbic\t$dst, $src1, $src2", "",
2007 [(set QPR:$dst, (v4i32 (and QPR:$src1,
2008 (vnot_conv QPR:$src2))))]>;
2010 // VORN : Vector Bitwise OR NOT
2011 def VORNd : N3V<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
2012 (ins DPR:$src1, DPR:$src2), IIC_VBINiD,
2013 "vorn\t$dst, $src1, $src2", "",
2014 [(set DPR:$dst, (v2i32 (or DPR:$src1,
2015 (vnot_conv DPR:$src2))))]>;
2016 def VORNq : N3V<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
2017 (ins QPR:$src1, QPR:$src2), IIC_VBINiQ,
2018 "vorn\t$dst, $src1, $src2", "",
2019 [(set QPR:$dst, (v4i32 (or QPR:$src1,
2020 (vnot_conv QPR:$src2))))]>;
2022 // VMVN : Vector Bitwise NOT
2023 def VMVNd : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
2024 (outs DPR:$dst), (ins DPR:$src), IIC_VSHLiD,
2025 "vmvn\t$dst, $src", "",
2026 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>;
2027 def VMVNq : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
2028 (outs QPR:$dst), (ins QPR:$src), IIC_VSHLiD,
2029 "vmvn\t$dst, $src", "",
2030 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>;
2031 def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>;
2032 def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>;
2034 // VBSL : Vector Bitwise Select
2035 def VBSLd : N3V<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2036 (ins DPR:$src1, DPR:$src2, DPR:$src3), IIC_VCNTiD,
2037 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
2039 (v2i32 (or (and DPR:$src2, DPR:$src1),
2040 (and DPR:$src3, (vnot_conv DPR:$src1)))))]>;
2041 def VBSLq : N3V<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2042 (ins QPR:$src1, QPR:$src2, QPR:$src3), IIC_VCNTiQ,
2043 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
2045 (v4i32 (or (and QPR:$src2, QPR:$src1),
2046 (and QPR:$src3, (vnot_conv QPR:$src1)))))]>;
2048 // VBIF : Vector Bitwise Insert if False
2049 // like VBSL but with: "vbif\t$dst, $src3, $src1", "$src2 = $dst",
2050 // VBIT : Vector Bitwise Insert if True
2051 // like VBSL but with: "vbit\t$dst, $src2, $src1", "$src3 = $dst",
2052 // These are not yet implemented. The TwoAddress pass will not go looking
2053 // for equivalent operations with different register constraints; it just
2056 // Vector Absolute Differences.
2058 // VABD : Vector Absolute Difference
2059 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2060 IIC_VBINi4Q, "vabd.s", int_arm_neon_vabds, 0>;
2061 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2062 IIC_VBINi4Q, "vabd.u", int_arm_neon_vabdu, 0>;
2063 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, IIC_VBIND, "vabd.f32", v2f32, v2f32,
2064 int_arm_neon_vabds, 0>;
2065 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vabd.f32", v4f32, v4f32,
2066 int_arm_neon_vabds, 0>;
2068 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
2069 defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, IIC_VBINi4Q, "vabdl.s", int_arm_neon_vabdls, 0>;
2070 defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, IIC_VBINi4Q, "vabdl.u", int_arm_neon_vabdlu, 0>;
2072 // VABA : Vector Absolute Difference and Accumulate
2073 defm VABAs : N3VInt3_QHS<0,0,0b0111,1, "vaba.s", int_arm_neon_vabas>;
2074 defm VABAu : N3VInt3_QHS<1,0,0b0111,1, "vaba.u", int_arm_neon_vabau>;
2076 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
2077 defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal.s", int_arm_neon_vabals>;
2078 defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal.u", int_arm_neon_vabalu>;
2080 // Vector Maximum and Minimum.
2082 // VMAX : Vector Maximum
2083 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2084 IIC_VBINi4Q, "vmax.s", int_arm_neon_vmaxs, 1>;
2085 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2086 IIC_VBINi4Q, "vmax.u", int_arm_neon_vmaxu, 1>;
2087 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, IIC_VBIND, "vmax.f32", v2f32, v2f32,
2088 int_arm_neon_vmaxs, 1>;
2089 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, IIC_VBINQ, "vmax.f32", v4f32, v4f32,
2090 int_arm_neon_vmaxs, 1>;
2092 // VMIN : Vector Minimum
2093 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2094 IIC_VBINi4Q, "vmin.s", int_arm_neon_vmins, 1>;
2095 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2096 IIC_VBINi4Q, "vmin.u", int_arm_neon_vminu, 1>;
2097 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, IIC_VBIND, "vmin.f32", v2f32, v2f32,
2098 int_arm_neon_vmins, 1>;
2099 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, IIC_VBINQ, "vmin.f32", v4f32, v4f32,
2100 int_arm_neon_vmins, 1>;
2102 // Vector Pairwise Operations.
2104 // VPADD : Vector Pairwise Add
2105 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, IIC_VBINiD, "vpadd.i8", v8i8, v8i8,
2106 int_arm_neon_vpadd, 0>;
2107 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, IIC_VBINiD, "vpadd.i16", v4i16, v4i16,
2108 int_arm_neon_vpadd, 0>;
2109 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, IIC_VBINiD, "vpadd.i32", v2i32, v2i32,
2110 int_arm_neon_vpadd, 0>;
2111 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, IIC_VBIND, "vpadd.f32", v2f32, v2f32,
2112 int_arm_neon_vpadd, 0>;
2114 // VPADDL : Vector Pairwise Add Long
2115 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl.s",
2116 int_arm_neon_vpaddls>;
2117 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl.u",
2118 int_arm_neon_vpaddlu>;
2120 // VPADAL : Vector Pairwise Add and Accumulate Long
2121 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal.s",
2122 int_arm_neon_vpadals>;
2123 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal.u",
2124 int_arm_neon_vpadalu>;
2126 // VPMAX : Vector Pairwise Maximum
2127 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax.s8", v8i8, v8i8,
2128 int_arm_neon_vpmaxs, 0>;
2129 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax.s16", v4i16, v4i16,
2130 int_arm_neon_vpmaxs, 0>;
2131 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax.s32", v2i32, v2i32,
2132 int_arm_neon_vpmaxs, 0>;
2133 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax.u8", v8i8, v8i8,
2134 int_arm_neon_vpmaxu, 0>;
2135 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax.u16", v4i16, v4i16,
2136 int_arm_neon_vpmaxu, 0>;
2137 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax.u32", v2i32, v2i32,
2138 int_arm_neon_vpmaxu, 0>;
2139 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, IIC_VBINi4D, "vpmax.f32", v2f32, v2f32,
2140 int_arm_neon_vpmaxs, 0>;
2142 // VPMIN : Vector Pairwise Minimum
2143 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin.s8", v8i8, v8i8,
2144 int_arm_neon_vpmins, 0>;
2145 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin.s16", v4i16, v4i16,
2146 int_arm_neon_vpmins, 0>;
2147 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin.s32", v2i32, v2i32,
2148 int_arm_neon_vpmins, 0>;
2149 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin.u8", v8i8, v8i8,
2150 int_arm_neon_vpminu, 0>;
2151 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin.u16", v4i16, v4i16,
2152 int_arm_neon_vpminu, 0>;
2153 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin.u32", v2i32, v2i32,
2154 int_arm_neon_vpminu, 0>;
2155 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, IIC_VBINi4D, "vpmin.f32", v2f32, v2f32,
2156 int_arm_neon_vpmins, 0>;
2158 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
2160 // VRECPE : Vector Reciprocal Estimate
2161 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
2162 IIC_VUNAD, "vrecpe.u32",
2163 v2i32, v2i32, int_arm_neon_vrecpe>;
2164 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
2165 IIC_VUNAQ, "vrecpe.u32",
2166 v4i32, v4i32, int_arm_neon_vrecpe>;
2167 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
2168 IIC_VUNAD, "vrecpe.f32",
2169 v2f32, v2f32, int_arm_neon_vrecpe>;
2170 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
2171 IIC_VUNAQ, "vrecpe.f32",
2172 v4f32, v4f32, int_arm_neon_vrecpe>;
2174 // VRECPS : Vector Reciprocal Step
2175 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, IIC_VRECSD, "vrecps.f32", v2f32, v2f32,
2176 int_arm_neon_vrecps, 1>;
2177 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, IIC_VRECSQ, "vrecps.f32", v4f32, v4f32,
2178 int_arm_neon_vrecps, 1>;
2180 // VRSQRTE : Vector Reciprocal Square Root Estimate
2181 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
2182 IIC_VUNAD, "vrsqrte.u32",
2183 v2i32, v2i32, int_arm_neon_vrsqrte>;
2184 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
2185 IIC_VUNAQ, "vrsqrte.u32",
2186 v4i32, v4i32, int_arm_neon_vrsqrte>;
2187 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
2188 IIC_VUNAD, "vrsqrte.f32",
2189 v2f32, v2f32, int_arm_neon_vrsqrte>;
2190 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
2191 IIC_VUNAQ, "vrsqrte.f32",
2192 v4f32, v4f32, int_arm_neon_vrsqrte>;
2194 // VRSQRTS : Vector Reciprocal Square Root Step
2195 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, IIC_VRECSD, "vrsqrts.f32", v2f32, v2f32,
2196 int_arm_neon_vrsqrts, 1>;
2197 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, IIC_VRECSQ, "vrsqrts.f32", v4f32, v4f32,
2198 int_arm_neon_vrsqrts, 1>;
2202 // VSHL : Vector Shift
2203 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
2204 IIC_VSHLiQ, "vshl.s", int_arm_neon_vshifts, 0>;
2205 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
2206 IIC_VSHLiQ, "vshl.u", int_arm_neon_vshiftu, 0>;
2207 // VSHL : Vector Shift Left (Immediate)
2208 defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl.i", NEONvshl>;
2209 // VSHR : Vector Shift Right (Immediate)
2210 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr.s", NEONvshrs>;
2211 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr.u", NEONvshru>;
2213 // VSHLL : Vector Shift Left Long
2214 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll.s", NEONvshlls>;
2215 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll.u", NEONvshllu>;
2217 // VSHLL : Vector Shift Left Long (with maximum shift count)
2218 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
2219 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
2220 ValueType OpTy, SDNode OpNode>
2221 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, ResTy, OpTy, OpNode> {
2222 let Inst{21-16} = op21_16;
2224 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll.i8",
2225 v8i16, v8i8, NEONvshlli>;
2226 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll.i16",
2227 v4i32, v4i16, NEONvshlli>;
2228 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll.i32",
2229 v2i64, v2i32, NEONvshlli>;
2231 // VSHRN : Vector Shift Right and Narrow
2232 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn.i", NEONvshrn>;
2234 // VRSHL : Vector Rounding Shift
2235 defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2236 IIC_VSHLi4Q, "vrshl.s", int_arm_neon_vrshifts, 0>;
2237 defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2238 IIC_VSHLi4Q, "vrshl.u", int_arm_neon_vrshiftu, 0>;
2239 // VRSHR : Vector Rounding Shift Right
2240 defm VRSHRs : N2VSh_QHSD<0, 1, 0b0010, 1, IIC_VSHLi4D, "vrshr.s", NEONvrshrs>;
2241 defm VRSHRu : N2VSh_QHSD<1, 1, 0b0010, 1, IIC_VSHLi4D, "vrshr.u", NEONvrshru>;
2243 // VRSHRN : Vector Rounding Shift Right and Narrow
2244 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn.i",
2247 // VQSHL : Vector Saturating Shift
2248 defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2249 IIC_VSHLi4Q, "vqshl.s", int_arm_neon_vqshifts, 0>;
2250 defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2251 IIC_VSHLi4Q, "vqshl.u", int_arm_neon_vqshiftu, 0>;
2252 // VQSHL : Vector Saturating Shift Left (Immediate)
2253 defm VQSHLsi : N2VSh_QHSD<0, 1, 0b0111, 1, IIC_VSHLi4D, "vqshl.s", NEONvqshls>;
2254 defm VQSHLui : N2VSh_QHSD<1, 1, 0b0111, 1, IIC_VSHLi4D, "vqshl.u", NEONvqshlu>;
2255 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
2256 defm VQSHLsu : N2VSh_QHSD<1, 1, 0b0110, 1, IIC_VSHLi4D, "vqshlu.s", NEONvqshlsu>;
2258 // VQSHRN : Vector Saturating Shift Right and Narrow
2259 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn.s",
2261 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn.u",
2264 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
2265 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun.s",
2268 // VQRSHL : Vector Saturating Rounding Shift
2269 defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2270 IIC_VSHLi4Q, "vqrshl.s", int_arm_neon_vqrshifts, 0>;
2271 defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2272 IIC_VSHLi4Q, "vqrshl.u", int_arm_neon_vqrshiftu, 0>;
2274 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
2275 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn.s",
2277 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn.u",
2280 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
2281 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun.s",
2284 // VSRA : Vector Shift Right and Accumulate
2285 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra.s", NEONvshrs>;
2286 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra.u", NEONvshru>;
2287 // VRSRA : Vector Rounding Shift Right and Accumulate
2288 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra.s", NEONvrshrs>;
2289 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra.u", NEONvrshru>;
2291 // VSLI : Vector Shift Left and Insert
2292 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli.", NEONvsli>;
2293 // VSRI : Vector Shift Right and Insert
2294 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri.", NEONvsri>;
2296 // Vector Absolute and Saturating Absolute.
2298 // VABS : Vector Absolute Value
2299 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
2300 IIC_VUNAiD, IIC_VUNAiQ, "vabs.s",
2302 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2303 IIC_VUNAD, "vabs.f32",
2304 v2f32, v2f32, int_arm_neon_vabs>;
2305 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2306 IIC_VUNAQ, "vabs.f32",
2307 v4f32, v4f32, int_arm_neon_vabs>;
2309 // VQABS : Vector Saturating Absolute Value
2310 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
2311 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs.s",
2312 int_arm_neon_vqabs>;
2316 def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
2317 def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>;
2319 class VNEGD<bits<2> size, string OpcodeStr, ValueType Ty>
2320 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
2321 IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "",
2322 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>;
2323 class VNEGQ<bits<2> size, string OpcodeStr, ValueType Ty>
2324 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
2325 IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "",
2326 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>;
2328 // VNEG : Vector Negate
2329 def VNEGs8d : VNEGD<0b00, "vneg.s8", v8i8>;
2330 def VNEGs16d : VNEGD<0b01, "vneg.s16", v4i16>;
2331 def VNEGs32d : VNEGD<0b10, "vneg.s32", v2i32>;
2332 def VNEGs8q : VNEGQ<0b00, "vneg.s8", v16i8>;
2333 def VNEGs16q : VNEGQ<0b01, "vneg.s16", v8i16>;
2334 def VNEGs32q : VNEGQ<0b10, "vneg.s32", v4i32>;
2336 // VNEG : Vector Negate (floating-point)
2337 def VNEGf32d : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
2338 (outs DPR:$dst), (ins DPR:$src), IIC_VUNAD,
2339 "vneg.f32\t$dst, $src", "",
2340 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
2341 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
2342 (outs QPR:$dst), (ins QPR:$src), IIC_VUNAQ,
2343 "vneg.f32\t$dst, $src", "",
2344 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
2346 def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
2347 def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
2348 def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>;
2349 def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>;
2350 def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>;
2351 def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>;
2353 // VQNEG : Vector Saturating Negate
2354 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
2355 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg.s",
2356 int_arm_neon_vqneg>;
2358 // Vector Bit Counting Operations.
2360 // VCLS : Vector Count Leading Sign Bits
2361 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
2362 IIC_VCNTiD, IIC_VCNTiQ, "vcls.s",
2364 // VCLZ : Vector Count Leading Zeros
2365 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
2366 IIC_VCNTiD, IIC_VCNTiQ, "vclz.i",
2368 // VCNT : Vector Count One Bits
2369 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2370 IIC_VCNTiD, "vcnt.8",
2371 v8i8, v8i8, int_arm_neon_vcnt>;
2372 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2373 IIC_VCNTiQ, "vcnt.8",
2374 v16i8, v16i8, int_arm_neon_vcnt>;
2376 // Vector Move Operations.
2378 // VMOV : Vector Move (Register)
2380 def VMOVDneon: N3V<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
2381 IIC_VMOVD, "vmov\t$dst, $src", "", []>;
2382 def VMOVQ : N3V<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
2383 IIC_VMOVD, "vmov\t$dst, $src", "", []>;
2385 // VMOV : Vector Move (Immediate)
2387 // VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
2388 def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
2389 return ARM::getVMOVImm(N, 1, *CurDAG);
2391 def vmovImm8 : PatLeaf<(build_vector), [{
2392 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
2395 // VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
2396 def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
2397 return ARM::getVMOVImm(N, 2, *CurDAG);
2399 def vmovImm16 : PatLeaf<(build_vector), [{
2400 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
2401 }], VMOV_get_imm16>;
2403 // VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
2404 def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
2405 return ARM::getVMOVImm(N, 4, *CurDAG);
2407 def vmovImm32 : PatLeaf<(build_vector), [{
2408 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
2409 }], VMOV_get_imm32>;
2411 // VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
2412 def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
2413 return ARM::getVMOVImm(N, 8, *CurDAG);
2415 def vmovImm64 : PatLeaf<(build_vector), [{
2416 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
2417 }], VMOV_get_imm64>;
2419 // Note: Some of the cmode bits in the following VMOV instructions need to
2420 // be encoded based on the immed values.
2422 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
2423 (ins h8imm:$SIMM), IIC_VMOVImm,
2424 "vmov.i8\t$dst, $SIMM", "",
2425 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
2426 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
2427 (ins h8imm:$SIMM), IIC_VMOVImm,
2428 "vmov.i8\t$dst, $SIMM", "",
2429 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
2431 def VMOVv4i16 : N1ModImm<1, 0b000, 0b1000, 0, 0, 0, 1, (outs DPR:$dst),
2432 (ins h16imm:$SIMM), IIC_VMOVImm,
2433 "vmov.i16\t$dst, $SIMM", "",
2434 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
2435 def VMOVv8i16 : N1ModImm<1, 0b000, 0b1000, 0, 1, 0, 1, (outs QPR:$dst),
2436 (ins h16imm:$SIMM), IIC_VMOVImm,
2437 "vmov.i16\t$dst, $SIMM", "",
2438 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
2440 def VMOVv2i32 : N1ModImm<1, 0b000, 0b0000, 0, 0, 0, 1, (outs DPR:$dst),
2441 (ins h32imm:$SIMM), IIC_VMOVImm,
2442 "vmov.i32\t$dst, $SIMM", "",
2443 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
2444 def VMOVv4i32 : N1ModImm<1, 0b000, 0b0000, 0, 1, 0, 1, (outs QPR:$dst),
2445 (ins h32imm:$SIMM), IIC_VMOVImm,
2446 "vmov.i32\t$dst, $SIMM", "",
2447 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
2449 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
2450 (ins h64imm:$SIMM), IIC_VMOVImm,
2451 "vmov.i64\t$dst, $SIMM", "",
2452 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
2453 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
2454 (ins h64imm:$SIMM), IIC_VMOVImm,
2455 "vmov.i64\t$dst, $SIMM", "",
2456 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
2458 // VMOV : Vector Get Lane (move scalar to ARM core register)
2460 def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00,
2461 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2462 IIC_VMOVSI, "vmov", ".s8\t$dst, $src[$lane]",
2463 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
2465 def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01,
2466 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2467 IIC_VMOVSI, "vmov", ".s16\t$dst, $src[$lane]",
2468 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
2470 def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00,
2471 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2472 IIC_VMOVSI, "vmov", ".u8\t$dst, $src[$lane]",
2473 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
2475 def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01,
2476 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2477 IIC_VMOVSI, "vmov", ".u16\t$dst, $src[$lane]",
2478 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
2480 def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00,
2481 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2482 IIC_VMOVSI, "vmov", ".32\t$dst, $src[$lane]",
2483 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
2485 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
2486 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
2487 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2488 (DSubReg_i8_reg imm:$lane))),
2489 (SubReg_i8_lane imm:$lane))>;
2490 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
2491 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2492 (DSubReg_i16_reg imm:$lane))),
2493 (SubReg_i16_lane imm:$lane))>;
2494 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
2495 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2496 (DSubReg_i8_reg imm:$lane))),
2497 (SubReg_i8_lane imm:$lane))>;
2498 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
2499 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2500 (DSubReg_i16_reg imm:$lane))),
2501 (SubReg_i16_lane imm:$lane))>;
2502 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
2503 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
2504 (DSubReg_i32_reg imm:$lane))),
2505 (SubReg_i32_lane imm:$lane))>;
2506 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
2507 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1), DPR_VFP2)),
2508 (SSubReg_f32_reg imm:$src2))>;
2509 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
2510 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1), QPR_VFP2)),
2511 (SSubReg_f32_reg imm:$src2))>;
2512 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
2513 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2514 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
2515 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2518 // VMOV : Vector Set Lane (move ARM core register to scalar)
2520 let Constraints = "$src1 = $dst" in {
2521 def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst),
2522 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2523 IIC_VMOVISL, "vmov", ".8\t$dst[$lane], $src2",
2524 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
2525 GPR:$src2, imm:$lane))]>;
2526 def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst),
2527 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2528 IIC_VMOVISL, "vmov", ".16\t$dst[$lane], $src2",
2529 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
2530 GPR:$src2, imm:$lane))]>;
2531 def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst),
2532 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2533 IIC_VMOVISL, "vmov", ".32\t$dst[$lane], $src2",
2534 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
2535 GPR:$src2, imm:$lane))]>;
2537 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
2538 (v16i8 (INSERT_SUBREG QPR:$src1,
2539 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
2540 (DSubReg_i8_reg imm:$lane))),
2541 GPR:$src2, (SubReg_i8_lane imm:$lane)),
2542 (DSubReg_i8_reg imm:$lane)))>;
2543 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
2544 (v8i16 (INSERT_SUBREG QPR:$src1,
2545 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
2546 (DSubReg_i16_reg imm:$lane))),
2547 GPR:$src2, (SubReg_i16_lane imm:$lane)),
2548 (DSubReg_i16_reg imm:$lane)))>;
2549 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
2550 (v4i32 (INSERT_SUBREG QPR:$src1,
2551 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
2552 (DSubReg_i32_reg imm:$lane))),
2553 GPR:$src2, (SubReg_i32_lane imm:$lane)),
2554 (DSubReg_i32_reg imm:$lane)))>;
2556 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
2557 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
2558 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
2559 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
2560 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
2561 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
2563 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
2564 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
2565 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
2566 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
2568 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
2569 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
2570 def : Pat<(v2f64 (scalar_to_vector DPR:$src)),
2571 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, arm_dsubreg_0)>;
2572 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
2573 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
2575 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
2576 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2577 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
2578 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2579 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
2580 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2582 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
2583 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
2584 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2586 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
2587 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
2588 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2590 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
2591 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
2592 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2595 // VDUP : Vector Duplicate (from ARM core register to all elements)
2597 class VDUPD<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
2598 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
2599 IIC_VMOVIS, "vdup", !strconcat(asmSize, "\t$dst, $src"),
2600 [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
2601 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
2602 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
2603 IIC_VMOVIS, "vdup", !strconcat(asmSize, "\t$dst, $src"),
2604 [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
2606 def VDUP8d : VDUPD<0b11101100, 0b00, ".8", v8i8>;
2607 def VDUP16d : VDUPD<0b11101000, 0b01, ".16", v4i16>;
2608 def VDUP32d : VDUPD<0b11101000, 0b00, ".32", v2i32>;
2609 def VDUP8q : VDUPQ<0b11101110, 0b00, ".8", v16i8>;
2610 def VDUP16q : VDUPQ<0b11101010, 0b01, ".16", v8i16>;
2611 def VDUP32q : VDUPQ<0b11101010, 0b00, ".32", v4i32>;
2613 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
2614 IIC_VMOVIS, "vdup", ".32\t$dst, $src",
2615 [(set DPR:$dst, (v2f32 (NEONvdup
2616 (f32 (bitconvert GPR:$src)))))]>;
2617 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
2618 IIC_VMOVIS, "vdup", ".32\t$dst, $src",
2619 [(set QPR:$dst, (v4f32 (NEONvdup
2620 (f32 (bitconvert GPR:$src)))))]>;
2622 // VDUP : Vector Duplicate Lane (from scalar to all elements)
2624 class VDUPLND<string OpcodeStr, ValueType Ty>
2625 : N2VDup<0b11, 0b11, 0b11000, 0, 0,
2626 (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
2627 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
2628 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
2630 class VDUPLNQ<string OpcodeStr, ValueType ResTy, ValueType OpTy>
2631 : N2VDup<0b11, 0b11, 0b11000, 1, 0,
2632 (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
2633 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
2634 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src), imm:$lane)))]>;
2636 // Inst{19-16} is partially specified depending on the element size.
2638 def VDUPLN8d : VDUPLND<"vdup.8", v8i8> { let Inst{16} = 1; }
2639 def VDUPLN16d : VDUPLND<"vdup.16", v4i16> { let Inst{17-16} = 0b10; }
2640 def VDUPLN32d : VDUPLND<"vdup.32", v2i32> { let Inst{18-16} = 0b100; }
2641 def VDUPLNfd : VDUPLND<"vdup.32", v2f32> { let Inst{18-16} = 0b100; }
2642 def VDUPLN8q : VDUPLNQ<"vdup.8", v16i8, v8i8> { let Inst{16} = 1; }
2643 def VDUPLN16q : VDUPLNQ<"vdup.16", v8i16, v4i16> { let Inst{17-16} = 0b10; }
2644 def VDUPLN32q : VDUPLNQ<"vdup.32", v4i32, v2i32> { let Inst{18-16} = 0b100; }
2645 def VDUPLNfq : VDUPLNQ<"vdup.32", v4f32, v2f32> { let Inst{18-16} = 0b100; }
2647 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
2648 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
2649 (DSubReg_i8_reg imm:$lane))),
2650 (SubReg_i8_lane imm:$lane)))>;
2651 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
2652 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
2653 (DSubReg_i16_reg imm:$lane))),
2654 (SubReg_i16_lane imm:$lane)))>;
2655 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
2656 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
2657 (DSubReg_i32_reg imm:$lane))),
2658 (SubReg_i32_lane imm:$lane)))>;
2659 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
2660 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
2661 (DSubReg_i32_reg imm:$lane))),
2662 (SubReg_i32_lane imm:$lane)))>;
2664 def VDUPfdf : N2VDup<0b11, 0b11, 0b11000, 0, 0,
2665 (outs DPR:$dst), (ins SPR:$src),
2666 IIC_VMOVD, "vdup.32\t$dst, ${src:lane}", "",
2667 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]> {
2668 let Inst{18-16} = 0b100;
2671 def VDUPfqf : N2VDup<0b11, 0b11, 0b11000, 1, 0,
2672 (outs QPR:$dst), (ins SPR:$src),
2673 IIC_VMOVD, "vdup.32\t$dst, ${src:lane}", "",
2674 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]> {
2675 let Inst{18-16} = 0b100;
2678 def : Pat<(v2i64 (NEONvduplane (v2i64 QPR:$src), imm:$lane)),
2679 (INSERT_SUBREG QPR:$src,
2680 (i64 (EXTRACT_SUBREG QPR:$src, (DSubReg_f64_reg imm:$lane))),
2681 (DSubReg_f64_other_reg imm:$lane))>;
2682 def : Pat<(v2f64 (NEONvduplane (v2f64 QPR:$src), imm:$lane)),
2683 (INSERT_SUBREG QPR:$src,
2684 (f64 (EXTRACT_SUBREG QPR:$src, (DSubReg_f64_reg imm:$lane))),
2685 (DSubReg_f64_other_reg imm:$lane))>;
2687 // VMOVN : Vector Narrowing Move
2688 defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVD, "vmovn.i",
2689 int_arm_neon_vmovn>;
2690 // VQMOVN : Vector Saturating Narrowing Move
2691 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD, "vqmovn.s",
2692 int_arm_neon_vqmovns>;
2693 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD, "vqmovn.u",
2694 int_arm_neon_vqmovnu>;
2695 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD, "vqmovun.s",
2696 int_arm_neon_vqmovnsu>;
2697 // VMOVL : Vector Lengthening Move
2698 defm VMOVLs : N2VLInt_QHS<0b01,0b10100,0,1, "vmovl.s", int_arm_neon_vmovls>;
2699 defm VMOVLu : N2VLInt_QHS<0b11,0b10100,0,1, "vmovl.u", int_arm_neon_vmovlu>;
2701 // Vector Conversions.
2703 // VCVT : Vector Convert Between Floating-Point and Integers
2704 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
2705 v2i32, v2f32, fp_to_sint>;
2706 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
2707 v2i32, v2f32, fp_to_uint>;
2708 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
2709 v2f32, v2i32, sint_to_fp>;
2710 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
2711 v2f32, v2i32, uint_to_fp>;
2713 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
2714 v4i32, v4f32, fp_to_sint>;
2715 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
2716 v4i32, v4f32, fp_to_uint>;
2717 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
2718 v4f32, v4i32, sint_to_fp>;
2719 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
2720 v4f32, v4i32, uint_to_fp>;
2722 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
2723 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt.s32.f32",
2724 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
2725 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt.u32.f32",
2726 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
2727 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt.f32.s32",
2728 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
2729 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt.f32.u32",
2730 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
2732 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt.s32.f32",
2733 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
2734 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt.u32.f32",
2735 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
2736 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt.f32.s32",
2737 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
2738 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt.f32.u32",
2739 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
2743 // VREV64 : Vector Reverse elements within 64-bit doublewords
2745 class VREV64D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2746 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
2747 (ins DPR:$src), IIC_VMOVD,
2748 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2749 [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
2750 class VREV64Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2751 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
2752 (ins QPR:$src), IIC_VMOVD,
2753 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2754 [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
2756 def VREV64d8 : VREV64D<0b00, "vrev64.8", v8i8>;
2757 def VREV64d16 : VREV64D<0b01, "vrev64.16", v4i16>;
2758 def VREV64d32 : VREV64D<0b10, "vrev64.32", v2i32>;
2759 def VREV64df : VREV64D<0b10, "vrev64.32", v2f32>;
2761 def VREV64q8 : VREV64Q<0b00, "vrev64.8", v16i8>;
2762 def VREV64q16 : VREV64Q<0b01, "vrev64.16", v8i16>;
2763 def VREV64q32 : VREV64Q<0b10, "vrev64.32", v4i32>;
2764 def VREV64qf : VREV64Q<0b10, "vrev64.32", v4f32>;
2766 // VREV32 : Vector Reverse elements within 32-bit words
2768 class VREV32D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2769 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
2770 (ins DPR:$src), IIC_VMOVD,
2771 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2772 [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
2773 class VREV32Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2774 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
2775 (ins QPR:$src), IIC_VMOVD,
2776 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2777 [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
2779 def VREV32d8 : VREV32D<0b00, "vrev32.8", v8i8>;
2780 def VREV32d16 : VREV32D<0b01, "vrev32.16", v4i16>;
2782 def VREV32q8 : VREV32Q<0b00, "vrev32.8", v16i8>;
2783 def VREV32q16 : VREV32Q<0b01, "vrev32.16", v8i16>;
2785 // VREV16 : Vector Reverse elements within 16-bit halfwords
2787 class VREV16D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2788 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
2789 (ins DPR:$src), IIC_VMOVD,
2790 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2791 [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
2792 class VREV16Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2793 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
2794 (ins QPR:$src), IIC_VMOVD,
2795 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2796 [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
2798 def VREV16d8 : VREV16D<0b00, "vrev16.8", v8i8>;
2799 def VREV16q8 : VREV16Q<0b00, "vrev16.8", v16i8>;
2801 // Other Vector Shuffles.
2803 // VEXT : Vector Extract
2805 class VEXTd<string OpcodeStr, ValueType Ty>
2806 : N3VImm<0,1,0b11,0,0, (outs DPR:$dst),
2807 (ins DPR:$lhs, DPR:$rhs, i32imm:$index), IIC_VEXTD,
2808 !strconcat(OpcodeStr, "\t$dst, $lhs, $rhs, $index"), "",
2809 [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
2810 (Ty DPR:$rhs), imm:$index)))]>;
2812 class VEXTq<string OpcodeStr, ValueType Ty>
2813 : N3VImm<0,1,0b11,1,0, (outs QPR:$dst),
2814 (ins QPR:$lhs, QPR:$rhs, i32imm:$index), IIC_VEXTQ,
2815 !strconcat(OpcodeStr, "\t$dst, $lhs, $rhs, $index"), "",
2816 [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
2817 (Ty QPR:$rhs), imm:$index)))]>;
2819 def VEXTd8 : VEXTd<"vext.8", v8i8>;
2820 def VEXTd16 : VEXTd<"vext.16", v4i16>;
2821 def VEXTd32 : VEXTd<"vext.32", v2i32>;
2822 def VEXTdf : VEXTd<"vext.32", v2f32>;
2824 def VEXTq8 : VEXTq<"vext.8", v16i8>;
2825 def VEXTq16 : VEXTq<"vext.16", v8i16>;
2826 def VEXTq32 : VEXTq<"vext.32", v4i32>;
2827 def VEXTqf : VEXTq<"vext.32", v4f32>;
2829 // VTRN : Vector Transpose
2831 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn.8">;
2832 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn.16">;
2833 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn.32">;
2835 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn.8">;
2836 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn.16">;
2837 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn.32">;
2839 // VUZP : Vector Unzip (Deinterleave)
2841 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp.8">;
2842 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp.16">;
2843 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp.32">;
2845 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp.8">;
2846 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp.16">;
2847 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp.32">;
2849 // VZIP : Vector Zip (Interleave)
2851 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip.8">;
2852 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip.16">;
2853 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip.32">;
2855 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip.8">;
2856 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip.16">;
2857 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip.32">;
2859 // Vector Table Lookup and Table Extension.
2861 // VTBL : Vector Table Lookup
2863 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
2864 (ins DPR:$tbl1, DPR:$src), IIC_VTB1,
2865 "vtbl.8\t$dst, \\{$tbl1\\}, $src", "",
2866 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
2867 let hasExtraSrcRegAllocReq = 1 in {
2869 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
2870 (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTB2,
2871 "vtbl.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "",
2872 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl2
2873 DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
2875 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
2876 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTB3,
2877 "vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "",
2878 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl3
2879 DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
2881 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
2882 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTB4,
2883 "vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "",
2884 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl4 DPR:$tbl1, DPR:$tbl2,
2885 DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
2886 } // hasExtraSrcRegAllocReq = 1
2888 // VTBX : Vector Table Extension
2890 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
2891 (ins DPR:$orig, DPR:$tbl1, DPR:$src), IIC_VTBX1,
2892 "vtbx.8\t$dst, \\{$tbl1\\}, $src", "$orig = $dst",
2893 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
2894 DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
2895 let hasExtraSrcRegAllocReq = 1 in {
2897 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
2898 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTBX2,
2899 "vtbx.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "$orig = $dst",
2900 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx2
2901 DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
2903 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
2904 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTBX3,
2905 "vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "$orig = $dst",
2906 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx3 DPR:$orig, DPR:$tbl1,
2907 DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
2909 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
2910 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTBX4,
2911 "vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "$orig = $dst",
2912 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx4 DPR:$orig, DPR:$tbl1,
2913 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
2914 } // hasExtraSrcRegAllocReq = 1
2916 //===----------------------------------------------------------------------===//
2917 // NEON instructions for single-precision FP math
2918 //===----------------------------------------------------------------------===//
2920 // These need separate instructions because they must use DPR_VFP2 register
2921 // class which have SPR sub-registers.
2923 // Vector Add Operations used for single-precision FP
2924 let neverHasSideEffects = 1 in
2925 def VADDfd_sfp : N3VDs<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd,1>;
2926 def : N3VDsPat<fadd, VADDfd_sfp>;
2928 // Vector Sub Operations used for single-precision FP
2929 let neverHasSideEffects = 1 in
2930 def VSUBfd_sfp : N3VDs<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub,0>;
2931 def : N3VDsPat<fsub, VSUBfd_sfp>;
2933 // Vector Multiply Operations used for single-precision FP
2934 let neverHasSideEffects = 1 in
2935 def VMULfd_sfp : N3VDs<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul,1>;
2936 def : N3VDsPat<fmul, VMULfd_sfp>;
2938 // Vector Multiply-Accumulate/Subtract used for single-precision FP
2939 // vml[as].f32 can cause 4-8 cycle stalls in following ASIMD instructions, so
2940 // we want to avoid them for now. e.g., alternating vmla/vadd instructions.
2942 //let neverHasSideEffects = 1 in
2943 //def VMLAfd_sfp : N3VDMulOps<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla.f32", v2f32,fmul,fadd>;
2944 //def : N3VDMulOpsPat<fmul, fadd, VMLAfd_sfp>;
2946 //let neverHasSideEffects = 1 in
2947 //def VMLSfd_sfp : N3VDMulOps<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls.f32", v2f32,fmul,fsub>;
2948 //def : N3VDMulOpsPat<fmul, fsub, VMLSfd_sfp>;
2950 // Vector Absolute used for single-precision FP
2951 let neverHasSideEffects = 1 in
2952 def VABSfd_sfp : N2VDInts<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2953 IIC_VUNAD, "vabs.f32",
2954 v2f32, v2f32, int_arm_neon_vabs>;
2955 def : N2VDIntsPat<fabs, VABSfd_sfp>;
2957 // Vector Negate used for single-precision FP
2958 let neverHasSideEffects = 1 in
2959 def VNEGf32d_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
2960 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
2961 "vneg.f32\t$dst, $src", "", []>;
2962 def : N2VDIntsPat<fneg, VNEGf32d_sfp>;
2964 // Vector Convert between single-precision FP and integer
2965 let neverHasSideEffects = 1 in
2966 def VCVTf2sd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
2967 v2i32, v2f32, fp_to_sint>;
2968 def : N2VDsPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
2970 let neverHasSideEffects = 1 in
2971 def VCVTf2ud_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
2972 v2i32, v2f32, fp_to_uint>;
2973 def : N2VDsPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
2975 let neverHasSideEffects = 1 in
2976 def VCVTs2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
2977 v2f32, v2i32, sint_to_fp>;
2978 def : N2VDsPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
2980 let neverHasSideEffects = 1 in
2981 def VCVTu2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
2982 v2f32, v2i32, uint_to_fp>;
2983 def : N2VDsPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
2985 //===----------------------------------------------------------------------===//
2986 // Non-Instruction Patterns
2987 //===----------------------------------------------------------------------===//
2990 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
2991 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
2992 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
2993 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
2994 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
2995 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
2996 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
2997 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
2998 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
2999 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
3000 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
3001 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
3002 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
3003 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
3004 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
3005 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
3006 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
3007 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
3008 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
3009 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
3010 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
3011 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
3012 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
3013 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
3014 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
3015 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
3016 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
3017 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
3018 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
3019 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
3021 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
3022 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
3023 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
3024 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
3025 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
3026 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
3027 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
3028 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
3029 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
3030 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
3031 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
3032 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
3033 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
3034 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
3035 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
3036 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
3037 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
3038 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
3039 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
3040 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
3041 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
3042 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
3043 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
3044 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
3045 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
3046 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
3047 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
3048 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
3049 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
3050 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;