1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
70 // VDUPLANE can produce a quad-register result from a double-register source,
71 // so the result is not constrained to match the source.
72 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
73 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
76 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
77 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
78 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
80 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
81 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
82 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
83 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
85 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
86 SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>]>;
87 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
88 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
89 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
91 //===----------------------------------------------------------------------===//
92 // NEON operand definitions
93 //===----------------------------------------------------------------------===//
95 // addrmode_neonldstm := reg
97 /* TODO: Take advantage of vldm.
98 def addrmode_neonldstm : Operand<i32>,
99 ComplexPattern<i32, 2, "SelectAddrModeNeonLdStM", []> {
100 let PrintMethod = "printAddrNeonLdStMOperand";
101 let MIOperandInfo = (ops GPR, i32imm);
105 def h8imm : Operand<i8> {
106 let PrintMethod = "printHex8ImmOperand";
108 def h16imm : Operand<i16> {
109 let PrintMethod = "printHex16ImmOperand";
111 def h32imm : Operand<i32> {
112 let PrintMethod = "printHex32ImmOperand";
114 def h64imm : Operand<i64> {
115 let PrintMethod = "printHex64ImmOperand";
118 //===----------------------------------------------------------------------===//
119 // NEON load / store instructions
120 //===----------------------------------------------------------------------===//
122 /* TODO: Take advantage of vldm.
123 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
124 def VLDMD : NI<(outs),
125 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
127 "vldm", "${addr:submode} ${addr:base}, $dst1",
129 let Inst{27-25} = 0b110;
131 let Inst{11-9} = 0b101;
134 def VLDMS : NI<(outs),
135 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
137 "vldm", "${addr:submode} ${addr:base}, $dst1",
139 let Inst{27-25} = 0b110;
141 let Inst{11-9} = 0b101;
146 // Use vldmia to load a Q register as a D register pair.
147 def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr),
149 "vldmia", "$addr, ${dst:dregpair}",
150 [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]> {
151 let Inst{27-25} = 0b110;
152 let Inst{24} = 0; // P bit
153 let Inst{23} = 1; // U bit
155 let Inst{11-8} = 0b1011;
158 // Use vstmia to store a Q register as a D register pair.
159 def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr),
161 "vstmia", "$addr, ${src:dregpair}",
162 [(store (v2f64 QPR:$src), addrmode4:$addr)]> {
163 let Inst{27-25} = 0b110;
164 let Inst{24} = 0; // P bit
165 let Inst{23} = 1; // U bit
167 let Inst{11-8} = 0b1011;
170 // VLD1 : Vector Load (multiple single elements)
171 class VLD1D<bits<4> op7_4, string OpcodeStr, string Dt,
172 ValueType Ty, Intrinsic IntOp>
173 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst), (ins addrmode6:$addr), IIC_VLD1,
174 OpcodeStr, Dt, "\\{$dst\\}, $addr", "",
175 [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
176 class VLD1Q<bits<4> op7_4, string OpcodeStr, string Dt,
177 ValueType Ty, Intrinsic IntOp>
178 : NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst), (ins addrmode6:$addr), IIC_VLD1,
179 OpcodeStr, Dt, "${dst:dregpair}, $addr", "",
180 [(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
182 def VLD1d8 : VLD1D<0b0000, "vld1", "8", v8i8, int_arm_neon_vld1>;
183 def VLD1d16 : VLD1D<0b0100, "vld1", "16", v4i16, int_arm_neon_vld1>;
184 def VLD1d32 : VLD1D<0b1000, "vld1", "32", v2i32, int_arm_neon_vld1>;
185 def VLD1df : VLD1D<0b1000, "vld1", "32", v2f32, int_arm_neon_vld1>;
186 def VLD1d64 : VLD1D<0b1100, "vld1", "64", v1i64, int_arm_neon_vld1>;
188 def VLD1q8 : VLD1Q<0b0000, "vld1", "8", v16i8, int_arm_neon_vld1>;
189 def VLD1q16 : VLD1Q<0b0100, "vld1", "16", v8i16, int_arm_neon_vld1>;
190 def VLD1q32 : VLD1Q<0b1000, "vld1", "32", v4i32, int_arm_neon_vld1>;
191 def VLD1qf : VLD1Q<0b1000, "vld1", "32", v4f32, int_arm_neon_vld1>;
192 def VLD1q64 : VLD1Q<0b1100, "vld1", "64", v2i64, int_arm_neon_vld1>;
194 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
196 // VLD2 : Vector Load (multiple 2-element structures)
197 class VLD2D<bits<4> op7_4, string OpcodeStr, string Dt>
198 : NLdSt<0,0b10,0b1000,op7_4, (outs DPR:$dst1, DPR:$dst2),
199 (ins addrmode6:$addr), IIC_VLD2,
200 OpcodeStr, Dt, "\\{$dst1,$dst2\\}, $addr", "", []>;
201 class VLD2Q<bits<4> op7_4, string OpcodeStr, string Dt>
202 : NLdSt<0,0b10,0b0011,op7_4,
203 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
204 (ins addrmode6:$addr), IIC_VLD2,
205 OpcodeStr, Dt, "\\{$dst1,$dst2,$dst3,$dst4\\}, $addr",
208 def VLD2d8 : VLD2D<0b0000, "vld2", "8">;
209 def VLD2d16 : VLD2D<0b0100, "vld2", "16">;
210 def VLD2d32 : VLD2D<0b1000, "vld2", "32">;
211 def VLD2d64 : NLdSt<0,0b10,0b1010,0b1100, (outs DPR:$dst1, DPR:$dst2),
212 (ins addrmode6:$addr), IIC_VLD1,
213 "vld1", "64", "\\{$dst1,$dst2\\}, $addr", "", []>;
215 def VLD2q8 : VLD2Q<0b0000, "vld2", "8">;
216 def VLD2q16 : VLD2Q<0b0100, "vld2", "16">;
217 def VLD2q32 : VLD2Q<0b1000, "vld2", "32">;
219 // VLD3 : Vector Load (multiple 3-element structures)
220 class VLD3D<bits<4> op7_4, string OpcodeStr, string Dt>
221 : NLdSt<0,0b10,0b0100,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
222 (ins addrmode6:$addr), IIC_VLD3,
223 OpcodeStr, Dt, "\\{$dst1,$dst2,$dst3\\}, $addr", "", []>;
224 class VLD3WB<bits<4> op7_4, string OpcodeStr, string Dt>
225 : NLdSt<0,0b10,0b0101,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
226 (ins addrmode6:$addr), IIC_VLD3,
227 OpcodeStr, Dt, "\\{$dst1,$dst2,$dst3\\}, $addr",
228 "$addr.addr = $wb", []>;
230 def VLD3d8 : VLD3D<0b0000, "vld3", "8">;
231 def VLD3d16 : VLD3D<0b0100, "vld3", "16">;
232 def VLD3d32 : VLD3D<0b1000, "vld3", "32">;
233 def VLD3d64 : NLdSt<0,0b10,0b0110,0b1100,
234 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
235 (ins addrmode6:$addr), IIC_VLD1,
236 "vld1", "64", "\\{$dst1,$dst2,$dst3\\}, $addr", "", []>;
238 // vld3 to double-spaced even registers.
239 def VLD3q8a : VLD3WB<0b0000, "vld3", "8">;
240 def VLD3q16a : VLD3WB<0b0100, "vld3", "16">;
241 def VLD3q32a : VLD3WB<0b1000, "vld3", "32">;
243 // vld3 to double-spaced odd registers.
244 def VLD3q8b : VLD3WB<0b0000, "vld3", "8">;
245 def VLD3q16b : VLD3WB<0b0100, "vld3", "16">;
246 def VLD3q32b : VLD3WB<0b1000, "vld3", "32">;
248 // VLD4 : Vector Load (multiple 4-element structures)
249 class VLD4D<bits<4> op7_4, string OpcodeStr, string Dt>
250 : NLdSt<0,0b10,0b0000,op7_4,
251 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
252 (ins addrmode6:$addr), IIC_VLD4,
253 OpcodeStr, Dt, "\\{$dst1,$dst2,$dst3,$dst4\\}, $addr",
255 class VLD4WB<bits<4> op7_4, string OpcodeStr, string Dt>
256 : NLdSt<0,0b10,0b0001,op7_4,
257 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
258 (ins addrmode6:$addr), IIC_VLD4,
259 OpcodeStr, Dt, "\\{$dst1,$dst2,$dst3,$dst4\\}, $addr",
260 "$addr.addr = $wb", []>;
262 def VLD4d8 : VLD4D<0b0000, "vld4", "8">;
263 def VLD4d16 : VLD4D<0b0100, "vld4", "16">;
264 def VLD4d32 : VLD4D<0b1000, "vld4", "32">;
265 def VLD4d64 : NLdSt<0,0b10,0b0010,0b1100,
266 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
267 (ins addrmode6:$addr), IIC_VLD1,
268 "vld1", "64", "\\{$dst1,$dst2,$dst3,$dst4\\}, $addr", "", []>;
270 // vld4 to double-spaced even registers.
271 def VLD4q8a : VLD4WB<0b0000, "vld4", "8">;
272 def VLD4q16a : VLD4WB<0b0100, "vld4", "16">;
273 def VLD4q32a : VLD4WB<0b1000, "vld4", "32">;
275 // vld4 to double-spaced odd registers.
276 def VLD4q8b : VLD4WB<0b0000, "vld4", "8">;
277 def VLD4q16b : VLD4WB<0b0100, "vld4", "16">;
278 def VLD4q32b : VLD4WB<0b1000, "vld4", "32">;
280 // VLD1LN : Vector Load (single element to one lane)
281 // FIXME: Not yet implemented.
283 // VLD2LN : Vector Load (single 2-element structure to one lane)
284 class VLD2LN<bits<4> op11_8, string OpcodeStr, string Dt>
285 : NLdSt<1,0b10,op11_8,{?,?,?,?}, (outs DPR:$dst1, DPR:$dst2),
286 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
288 OpcodeStr, Dt, "\\{$dst1[$lane],$dst2[$lane]\\}, $addr",
289 "$src1 = $dst1, $src2 = $dst2", []>;
291 // vld2 to single-spaced registers.
292 def VLD2LNd8 : VLD2LN<0b0001, "vld2", "8">;
293 def VLD2LNd16 : VLD2LN<0b0101, "vld2", "16"> {
296 def VLD2LNd32 : VLD2LN<0b1001, "vld2", "32"> {
300 // vld2 to double-spaced even registers.
301 def VLD2LNq16a: VLD2LN<0b0101, "vld2", "16"> {
304 def VLD2LNq32a: VLD2LN<0b1001, "vld2", "32"> {
308 // vld2 to double-spaced odd registers.
309 def VLD2LNq16b: VLD2LN<0b0101, "vld2", "16"> {
312 def VLD2LNq32b: VLD2LN<0b1001, "vld2", "32"> {
316 // VLD3LN : Vector Load (single 3-element structure to one lane)
317 class VLD3LN<bits<4> op11_8, string OpcodeStr, string Dt>
318 : NLdSt<1,0b10,op11_8,{?,?,?,?}, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
319 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
320 nohash_imm:$lane), IIC_VLD3,
322 "\\{$dst1[$lane],$dst2[$lane],$dst3[$lane]\\}, $addr",
323 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
325 // vld3 to single-spaced registers.
326 def VLD3LNd8 : VLD3LN<0b0010, "vld3", "8"> {
329 def VLD3LNd16 : VLD3LN<0b0110, "vld3", "16"> {
330 let Inst{5-4} = 0b00;
332 def VLD3LNd32 : VLD3LN<0b1010, "vld3", "32"> {
333 let Inst{6-4} = 0b000;
336 // vld3 to double-spaced even registers.
337 def VLD3LNq16a: VLD3LN<0b0110, "vld3", "16"> {
338 let Inst{5-4} = 0b10;
340 def VLD3LNq32a: VLD3LN<0b1010, "vld3", "32"> {
341 let Inst{6-4} = 0b100;
344 // vld3 to double-spaced odd registers.
345 def VLD3LNq16b: VLD3LN<0b0110, "vld3", "16"> {
346 let Inst{5-4} = 0b10;
348 def VLD3LNq32b: VLD3LN<0b1010, "vld3", "32"> {
349 let Inst{6-4} = 0b100;
352 // VLD4LN : Vector Load (single 4-element structure to one lane)
353 class VLD4LN<bits<4> op11_8, string OpcodeStr, string Dt>
354 : NLdSt<1,0b10,op11_8,{?,?,?,?},
355 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
356 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
357 nohash_imm:$lane), IIC_VLD4,
359 "\\{$dst1[$lane],$dst2[$lane],$dst3[$lane],$dst4[$lane]\\}, $addr",
360 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
362 // vld4 to single-spaced registers.
363 def VLD4LNd8 : VLD4LN<0b0011, "vld4", "8">;
364 def VLD4LNd16 : VLD4LN<0b0111, "vld4", "16"> {
367 def VLD4LNd32 : VLD4LN<0b1011, "vld4", "32"> {
371 // vld4 to double-spaced even registers.
372 def VLD4LNq16a: VLD4LN<0b0111, "vld4", "16"> {
375 def VLD4LNq32a: VLD4LN<0b1011, "vld4", "32"> {
379 // vld4 to double-spaced odd registers.
380 def VLD4LNq16b: VLD4LN<0b0111, "vld4", "16"> {
383 def VLD4LNq32b: VLD4LN<0b1011, "vld4", "32"> {
387 // VLD1DUP : Vector Load (single element to all lanes)
388 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
389 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
390 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
391 // FIXME: Not yet implemented.
392 } // mayLoad = 1, hasExtraDefRegAllocReq = 1
394 // VST1 : Vector Store (multiple single elements)
395 class VST1D<bits<4> op7_4, string OpcodeStr, string Dt,
396 ValueType Ty, Intrinsic IntOp>
397 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src), IIC_VST,
398 OpcodeStr, Dt, "\\{$src\\}, $addr", "",
399 [(IntOp addrmode6:$addr, (Ty DPR:$src))]>;
400 class VST1Q<bits<4> op7_4, string OpcodeStr, string Dt,
401 ValueType Ty, Intrinsic IntOp>
402 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$addr, QPR:$src), IIC_VST,
403 OpcodeStr, Dt, "${src:dregpair}, $addr", "",
404 [(IntOp addrmode6:$addr, (Ty QPR:$src))]>;
406 let hasExtraSrcRegAllocReq = 1 in {
407 def VST1d8 : VST1D<0b0000, "vst1", "8", v8i8, int_arm_neon_vst1>;
408 def VST1d16 : VST1D<0b0100, "vst1", "16", v4i16, int_arm_neon_vst1>;
409 def VST1d32 : VST1D<0b1000, "vst1", "32", v2i32, int_arm_neon_vst1>;
410 def VST1df : VST1D<0b1000, "vst1", "32", v2f32, int_arm_neon_vst1>;
411 def VST1d64 : VST1D<0b1100, "vst1", "64", v1i64, int_arm_neon_vst1>;
413 def VST1q8 : VST1Q<0b0000, "vst1", "8", v16i8, int_arm_neon_vst1>;
414 def VST1q16 : VST1Q<0b0100, "vst1", "16", v8i16, int_arm_neon_vst1>;
415 def VST1q32 : VST1Q<0b1000, "vst1", "32", v4i32, int_arm_neon_vst1>;
416 def VST1qf : VST1Q<0b1000, "vst1", "32", v4f32, int_arm_neon_vst1>;
417 def VST1q64 : VST1Q<0b1100, "vst1", "64", v2i64, int_arm_neon_vst1>;
418 } // hasExtraSrcRegAllocReq
420 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
422 // VST2 : Vector Store (multiple 2-element structures)
423 class VST2D<bits<4> op7_4, string OpcodeStr, string Dt>
424 : NLdSt<0,0b00,0b1000,op7_4, (outs),
425 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
426 OpcodeStr, Dt, "\\{$src1,$src2\\}, $addr", "", []>;
427 class VST2Q<bits<4> op7_4, string OpcodeStr, string Dt>
428 : NLdSt<0,0b00,0b0011,op7_4, (outs),
429 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
431 OpcodeStr, Dt, "\\{$src1,$src2,$src3,$src4\\}, $addr",
434 def VST2d8 : VST2D<0b0000, "vst2", "8">;
435 def VST2d16 : VST2D<0b0100, "vst2", "16">;
436 def VST2d32 : VST2D<0b1000, "vst2", "32">;
437 def VST2d64 : NLdSt<0,0b00,0b1010,0b1100, (outs),
438 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
439 "vst1", "64", "\\{$src1,$src2\\}, $addr", "", []>;
441 def VST2q8 : VST2Q<0b0000, "vst2", "8">;
442 def VST2q16 : VST2Q<0b0100, "vst2", "16">;
443 def VST2q32 : VST2Q<0b1000, "vst2", "32">;
445 // VST3 : Vector Store (multiple 3-element structures)
446 class VST3D<bits<4> op7_4, string OpcodeStr, string Dt>
447 : NLdSt<0,0b00,0b0100,op7_4, (outs),
448 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
449 OpcodeStr, Dt, "\\{$src1,$src2,$src3\\}, $addr", "", []>;
450 class VST3WB<bits<4> op7_4, string OpcodeStr, string Dt>
451 : NLdSt<0,0b00,0b0101,op7_4, (outs GPR:$wb),
452 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
453 OpcodeStr, Dt, "\\{$src1,$src2,$src3\\}, $addr",
454 "$addr.addr = $wb", []>;
456 def VST3d8 : VST3D<0b0000, "vst3", "8">;
457 def VST3d16 : VST3D<0b0100, "vst3", "16">;
458 def VST3d32 : VST3D<0b1000, "vst3", "32">;
459 def VST3d64 : NLdSt<0,0b00,0b0110,0b1100, (outs),
460 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
462 "vst1", "64", "\\{$src1,$src2,$src3\\}, $addr", "", []>;
464 // vst3 to double-spaced even registers.
465 def VST3q8a : VST3WB<0b0000, "vst3", "8">;
466 def VST3q16a : VST3WB<0b0100, "vst3", "16">;
467 def VST3q32a : VST3WB<0b1000, "vst3", "32">;
469 // vst3 to double-spaced odd registers.
470 def VST3q8b : VST3WB<0b0000, "vst3", "8">;
471 def VST3q16b : VST3WB<0b0100, "vst3", "16">;
472 def VST3q32b : VST3WB<0b1000, "vst3", "32">;
474 // VST4 : Vector Store (multiple 4-element structures)
475 class VST4D<bits<4> op7_4, string OpcodeStr, string Dt>
476 : NLdSt<0,0b00,0b0000,op7_4, (outs),
477 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
479 OpcodeStr, Dt, "\\{$src1,$src2,$src3,$src4\\}, $addr",
481 class VST4WB<bits<4> op7_4, string OpcodeStr, string Dt>
482 : NLdSt<0,0b00,0b0001,op7_4, (outs GPR:$wb),
483 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
485 OpcodeStr, Dt, "\\{$src1,$src2,$src3,$src4\\}, $addr",
486 "$addr.addr = $wb", []>;
488 def VST4d8 : VST4D<0b0000, "vst4", "8">;
489 def VST4d16 : VST4D<0b0100, "vst4", "16">;
490 def VST4d32 : VST4D<0b1000, "vst4", "32">;
491 def VST4d64 : NLdSt<0,0b00,0b0010,0b1100, (outs),
492 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
494 "vst1", "64", "\\{$src1,$src2,$src3,$src4\\}, $addr", "", []>;
496 // vst4 to double-spaced even registers.
497 def VST4q8a : VST4WB<0b0000, "vst4", "8">;
498 def VST4q16a : VST4WB<0b0100, "vst4", "16">;
499 def VST4q32a : VST4WB<0b1000, "vst4", "32">;
501 // vst4 to double-spaced odd registers.
502 def VST4q8b : VST4WB<0b0000, "vst4", "8">;
503 def VST4q16b : VST4WB<0b0100, "vst4", "16">;
504 def VST4q32b : VST4WB<0b1000, "vst4", "32">;
506 // VST1LN : Vector Store (single element from one lane)
507 // FIXME: Not yet implemented.
509 // VST2LN : Vector Store (single 2-element structure from one lane)
510 class VST2LN<bits<4> op11_8, string OpcodeStr, string Dt>
511 : NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs),
512 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
514 OpcodeStr, Dt, "\\{$src1[$lane],$src2[$lane]\\}, $addr",
517 // vst2 to single-spaced registers.
518 def VST2LNd8 : VST2LN<0b0001, "vst2", "8">;
519 def VST2LNd16 : VST2LN<0b0101, "vst2", "16"> {
522 def VST2LNd32 : VST2LN<0b1001, "vst2", "32"> {
526 // vst2 to double-spaced even registers.
527 def VST2LNq16a: VST2LN<0b0101, "vst2", "16"> {
530 def VST2LNq32a: VST2LN<0b1001, "vst2", "32"> {
534 // vst2 to double-spaced odd registers.
535 def VST2LNq16b: VST2LN<0b0101, "vst2", "16"> {
538 def VST2LNq32b: VST2LN<0b1001, "vst2", "32"> {
542 // VST3LN : Vector Store (single 3-element structure from one lane)
543 class VST3LN<bits<4> op11_8, string OpcodeStr, string Dt>
544 : NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs),
545 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
546 nohash_imm:$lane), IIC_VST,
548 "\\{$src1[$lane],$src2[$lane],$src3[$lane]\\}, $addr", "", []>;
550 // vst3 to single-spaced registers.
551 def VST3LNd8 : VST3LN<0b0010, "vst3", "8"> {
554 def VST3LNd16 : VST3LN<0b0110, "vst3", "16"> {
555 let Inst{5-4} = 0b00;
557 def VST3LNd32 : VST3LN<0b1010, "vst3", "32"> {
558 let Inst{6-4} = 0b000;
561 // vst3 to double-spaced even registers.
562 def VST3LNq16a: VST3LN<0b0110, "vst3", "16"> {
563 let Inst{5-4} = 0b10;
565 def VST3LNq32a: VST3LN<0b1010, "vst3", "32"> {
566 let Inst{6-4} = 0b100;
569 // vst3 to double-spaced odd registers.
570 def VST3LNq16b: VST3LN<0b0110, "vst3", "16"> {
571 let Inst{5-4} = 0b10;
573 def VST3LNq32b: VST3LN<0b1010, "vst3", "32"> {
574 let Inst{6-4} = 0b100;
577 // VST4LN : Vector Store (single 4-element structure from one lane)
578 class VST4LN<bits<4> op11_8, string OpcodeStr, string Dt>
579 : NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs),
580 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
581 nohash_imm:$lane), IIC_VST,
583 "\\{$src1[$lane],$src2[$lane],$src3[$lane],$src4[$lane]\\}, $addr",
586 // vst4 to single-spaced registers.
587 def VST4LNd8 : VST4LN<0b0011, "vst4", "8">;
588 def VST4LNd16 : VST4LN<0b0111, "vst4", "16"> {
591 def VST4LNd32 : VST4LN<0b1011, "vst4", "32"> {
595 // vst4 to double-spaced even registers.
596 def VST4LNq16a: VST4LN<0b0111, "vst4", "16"> {
599 def VST4LNq32a: VST4LN<0b1011, "vst4", "32"> {
603 // vst4 to double-spaced odd registers.
604 def VST4LNq16b: VST4LN<0b0111, "vst4", "16"> {
607 def VST4LNq32b: VST4LN<0b1011, "vst4", "32"> {
611 } // mayStore = 1, hasExtraSrcRegAllocReq = 1
614 //===----------------------------------------------------------------------===//
615 // NEON pattern fragments
616 //===----------------------------------------------------------------------===//
618 // Extract D sub-registers of Q registers.
619 // (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
620 def DSubReg_i8_reg : SDNodeXForm<imm, [{
621 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
623 def DSubReg_i16_reg : SDNodeXForm<imm, [{
624 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
626 def DSubReg_i32_reg : SDNodeXForm<imm, [{
627 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
629 def DSubReg_f64_reg : SDNodeXForm<imm, [{
630 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
632 def DSubReg_f64_other_reg : SDNodeXForm<imm, [{
633 return CurDAG->getTargetConstant(5 + (1 - N->getZExtValue()), MVT::i32);
636 // Extract S sub-registers of Q/D registers.
637 // (arm_ssubreg_0 is 1; arm_ssubreg_1 is 2; etc.)
638 def SSubReg_f32_reg : SDNodeXForm<imm, [{
639 return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32);
642 // Translate lane numbers from Q registers to D subregs.
643 def SubReg_i8_lane : SDNodeXForm<imm, [{
644 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
646 def SubReg_i16_lane : SDNodeXForm<imm, [{
647 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
649 def SubReg_i32_lane : SDNodeXForm<imm, [{
650 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
653 //===----------------------------------------------------------------------===//
654 // Instruction Classes
655 //===----------------------------------------------------------------------===//
657 // Basic 2-register operations, both double- and quad-register.
658 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
659 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,string Dt,
660 ValueType ResTy, ValueType OpTy, SDNode OpNode>
661 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
662 (ins DPR:$src), IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "",
663 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
664 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
665 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,string Dt,
666 ValueType ResTy, ValueType OpTy, SDNode OpNode>
667 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
668 (ins QPR:$src), IIC_VUNAQ, OpcodeStr, Dt, "$dst, $src", "",
669 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
671 // Basic 2-register operations, scalar single-precision.
672 class N2VDs<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
673 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,string Dt,
674 ValueType ResTy, ValueType OpTy, SDNode OpNode>
675 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
676 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
677 IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
679 class N2VDsPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
680 : NEONFPPat<(ResTy (OpNode SPR:$a)),
682 (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
685 // Basic 2-register intrinsics, both double- and quad-register.
686 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
687 bits<2> op17_16, bits<5> op11_7, bit op4,
688 InstrItinClass itin, string OpcodeStr, string Dt,
689 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
690 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
691 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
692 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
693 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
694 bits<2> op17_16, bits<5> op11_7, bit op4,
695 InstrItinClass itin, string OpcodeStr, string Dt,
696 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
697 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
698 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
699 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
701 // Basic 2-register intrinsics, scalar single-precision
702 class N2VDInts<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
703 bits<2> op17_16, bits<5> op11_7, bit op4,
704 InstrItinClass itin, string OpcodeStr, string Dt,
705 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
706 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
707 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), itin,
708 OpcodeStr, Dt, "$dst, $src", "", []>;
710 class N2VDIntsPat<SDNode OpNode, NeonI Inst>
711 : NEONFPPat<(f32 (OpNode SPR:$a)),
713 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
716 // Narrow 2-register intrinsics.
717 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
718 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
719 InstrItinClass itin, string OpcodeStr, string Dt,
720 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
721 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
722 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
723 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
725 // Long 2-register intrinsics (currently only used for VMOVL).
726 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
727 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
728 InstrItinClass itin, string OpcodeStr, string Dt,
729 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
730 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$dst),
731 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
732 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
734 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
735 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
736 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
737 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
738 OpcodeStr, Dt, "$dst1, $dst2",
739 "$src1 = $dst1, $src2 = $dst2", []>;
740 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
741 InstrItinClass itin, string OpcodeStr, string Dt>
742 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
743 (ins QPR:$src1, QPR:$src2), itin,
744 OpcodeStr, Dt, "$dst1, $dst2",
745 "$src1 = $dst1, $src2 = $dst2", []>;
747 // Basic 3-register operations, both double- and quad-register.
748 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
749 InstrItinClass itin, string OpcodeStr, string Dt,
750 ValueType ResTy, ValueType OpTy,
751 SDNode OpNode, bit Commutable>
752 : N3V<op24, op23, op21_20, op11_8, 0, op4,
753 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
754 OpcodeStr, Dt, "$dst, $src1, $src2", "",
755 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
756 let isCommutable = Commutable;
758 // Same as N3VD but no data type.
759 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
760 InstrItinClass itin, string OpcodeStr,
761 ValueType ResTy, ValueType OpTy,
762 SDNode OpNode, bit Commutable>
763 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
764 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
765 OpcodeStr, "$dst, $src1, $src2", "",
766 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
767 let isCommutable = Commutable;
769 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
770 InstrItinClass itin, string OpcodeStr, string Dt,
771 ValueType Ty, SDNode ShOp>
772 : N3V<0, 1, op21_20, op11_8, 1, 0,
773 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
774 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
776 (Ty (ShOp (Ty DPR:$src1),
777 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
779 let isCommutable = 0;
781 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
782 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
783 : N3V<0, 1, op21_20, op11_8, 1, 0,
784 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
786 OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
788 (Ty (ShOp (Ty DPR:$src1),
789 (Ty (NEONvduplane (Ty DPR_8:$src2),
791 let isCommutable = 0;
794 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
795 InstrItinClass itin, string OpcodeStr, string Dt,
796 ValueType ResTy, ValueType OpTy,
797 SDNode OpNode, bit Commutable>
798 : N3V<op24, op23, op21_20, op11_8, 1, op4,
799 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
800 OpcodeStr, Dt, "$dst, $src1, $src2", "",
801 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
802 let isCommutable = Commutable;
804 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
805 InstrItinClass itin, string OpcodeStr,
806 ValueType ResTy, ValueType OpTy,
807 SDNode OpNode, bit Commutable>
808 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
809 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
810 OpcodeStr, "$dst, $src1, $src2", "",
811 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
812 let isCommutable = Commutable;
814 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
815 InstrItinClass itin, string OpcodeStr, string Dt,
816 ValueType ResTy, ValueType OpTy, SDNode ShOp>
817 : N3V<1, 1, op21_20, op11_8, 1, 0,
818 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
819 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
820 [(set (ResTy QPR:$dst),
821 (ResTy (ShOp (ResTy QPR:$src1),
822 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
824 let isCommutable = 0;
826 class N3VQSL16<bits<2> op21_20, bits<4> op11_8,
827 string OpcodeStr, string Dt,
828 ValueType ResTy, ValueType OpTy, SDNode ShOp>
829 : N3V<1, 1, op21_20, op11_8, 1, 0,
830 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
832 OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
833 [(set (ResTy QPR:$dst),
834 (ResTy (ShOp (ResTy QPR:$src1),
835 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
837 let isCommutable = 0;
840 // Basic 3-register operations, scalar single-precision
841 class N3VDs<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
842 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
843 SDNode OpNode, bit Commutable>
844 : N3V<op24, op23, op21_20, op11_8, 0, op4,
845 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), IIC_VBIND,
846 OpcodeStr, Dt, "$dst, $src1, $src2", "", []> {
847 let isCommutable = Commutable;
849 class N3VDsPat<SDNode OpNode, NeonI Inst>
850 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
852 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
853 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
856 // Basic 3-register intrinsics, both double- and quad-register.
857 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
858 InstrItinClass itin, string OpcodeStr, string Dt,
859 ValueType ResTy, ValueType OpTy,
860 Intrinsic IntOp, bit Commutable>
861 : N3V<op24, op23, op21_20, op11_8, 0, op4,
862 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
863 OpcodeStr, Dt, "$dst, $src1, $src2", "",
864 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
865 let isCommutable = Commutable;
867 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
868 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
869 : N3V<0, 1, op21_20, op11_8, 1, 0,
870 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
871 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
873 (Ty (IntOp (Ty DPR:$src1),
874 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
876 let isCommutable = 0;
878 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
879 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
880 : N3V<0, 1, op21_20, op11_8, 1, 0,
881 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
882 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
884 (Ty (IntOp (Ty DPR:$src1),
885 (Ty (NEONvduplane (Ty DPR_8:$src2),
887 let isCommutable = 0;
890 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
891 InstrItinClass itin, string OpcodeStr, string Dt,
892 ValueType ResTy, ValueType OpTy,
893 Intrinsic IntOp, bit Commutable>
894 : N3V<op24, op23, op21_20, op11_8, 1, op4,
895 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
896 OpcodeStr, Dt, "$dst, $src1, $src2", "",
897 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
898 let isCommutable = Commutable;
900 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
901 string OpcodeStr, string Dt,
902 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
903 : N3V<1, 1, op21_20, op11_8, 1, 0,
904 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
905 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
906 [(set (ResTy QPR:$dst),
907 (ResTy (IntOp (ResTy QPR:$src1),
908 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
910 let isCommutable = 0;
912 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
913 string OpcodeStr, string Dt,
914 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
915 : N3V<1, 1, op21_20, op11_8, 1, 0,
916 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
917 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
918 [(set (ResTy QPR:$dst),
919 (ResTy (IntOp (ResTy QPR:$src1),
920 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
922 let isCommutable = 0;
925 // Multiply-Add/Sub operations, both double- and quad-register.
926 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
927 InstrItinClass itin, string OpcodeStr, string Dt,
928 ValueType Ty, SDNode MulOp, SDNode OpNode>
929 : N3V<op24, op23, op21_20, op11_8, 0, op4,
930 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin,
931 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
932 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
933 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
934 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
935 string OpcodeStr, string Dt,
936 ValueType Ty, SDNode MulOp, SDNode ShOp>
937 : N3V<0, 1, op21_20, op11_8, 1, 0,
939 (ins DPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
940 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
942 (Ty (ShOp (Ty DPR:$src1),
943 (Ty (MulOp DPR:$src2,
944 (Ty (NEONvduplane (Ty DPR_VFP2:$src3),
946 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
947 string OpcodeStr, string Dt,
948 ValueType Ty, SDNode MulOp, SDNode ShOp>
949 : N3V<0, 1, op21_20, op11_8, 1, 0,
951 (ins DPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
952 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
954 (Ty (ShOp (Ty DPR:$src1),
955 (Ty (MulOp DPR:$src2,
956 (Ty (NEONvduplane (Ty DPR_8:$src3),
959 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
960 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
961 SDNode MulOp, SDNode OpNode>
962 : N3V<op24, op23, op21_20, op11_8, 1, op4,
963 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin,
964 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
965 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
966 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
967 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
968 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
969 SDNode MulOp, SDNode ShOp>
970 : N3V<1, 1, op21_20, op11_8, 1, 0,
972 (ins QPR:$src1, QPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
973 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
974 [(set (ResTy QPR:$dst),
975 (ResTy (ShOp (ResTy QPR:$src1),
976 (ResTy (MulOp QPR:$src2,
977 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src3),
979 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
980 string OpcodeStr, string Dt,
981 ValueType ResTy, ValueType OpTy,
982 SDNode MulOp, SDNode ShOp>
983 : N3V<1, 1, op21_20, op11_8, 1, 0,
985 (ins QPR:$src1, QPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
986 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
987 [(set (ResTy QPR:$dst),
988 (ResTy (ShOp (ResTy QPR:$src1),
989 (ResTy (MulOp QPR:$src2,
990 (ResTy (NEONvduplane (OpTy DPR_8:$src3),
993 // Multiply-Add/Sub operations, scalar single-precision
994 class N3VDMulOps<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
995 InstrItinClass itin, string OpcodeStr, string Dt,
996 ValueType Ty, SDNode MulOp, SDNode OpNode>
997 : N3V<op24, op23, op21_20, op11_8, 0, op4,
998 (outs DPR_VFP2:$dst),
999 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), itin,
1000 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst", []>;
1002 class N3VDMulOpsPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
1003 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
1005 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$acc, arm_ssubreg_0),
1006 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
1007 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
1010 // Neon 3-argument intrinsics, both double- and quad-register.
1011 // The destination register is also used as the first source operand register.
1012 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1013 InstrItinClass itin, string OpcodeStr, string Dt,
1014 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1015 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1016 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin,
1017 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1018 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
1019 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
1020 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1021 InstrItinClass itin, string OpcodeStr, string Dt,
1022 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1023 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1024 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin,
1025 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1026 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
1027 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
1029 // Neon Long 3-argument intrinsic. The destination register is
1030 // a quad-register and is also used as the first source operand register.
1031 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1032 InstrItinClass itin, string OpcodeStr, string Dt,
1033 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
1034 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1035 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), itin,
1036 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1038 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
1039 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1040 string OpcodeStr, string Dt,
1041 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1042 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1044 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
1045 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1046 [(set (ResTy QPR:$dst),
1047 (ResTy (IntOp (ResTy QPR:$src1),
1049 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src3),
1051 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1052 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1054 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1056 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
1057 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1058 [(set (ResTy QPR:$dst),
1059 (ResTy (IntOp (ResTy QPR:$src1),
1061 (OpTy (NEONvduplane (OpTy DPR_8:$src3),
1065 // Narrowing 3-register intrinsics.
1066 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1067 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
1068 Intrinsic IntOp, bit Commutable>
1069 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1070 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VBINi4D,
1071 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1072 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
1073 let isCommutable = Commutable;
1076 // Long 3-register intrinsics.
1077 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1078 InstrItinClass itin, string OpcodeStr, string Dt,
1079 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
1080 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1081 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
1082 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1083 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
1084 let isCommutable = Commutable;
1086 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1087 string OpcodeStr, string Dt,
1088 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1089 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1090 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1091 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1092 [(set (ResTy QPR:$dst),
1093 (ResTy (IntOp (OpTy DPR:$src1),
1094 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1096 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1097 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1099 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1100 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1101 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1102 [(set (ResTy QPR:$dst),
1103 (ResTy (IntOp (OpTy DPR:$src1),
1104 (OpTy (NEONvduplane (OpTy DPR_8:$src2),
1107 // Wide 3-register intrinsics.
1108 class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1109 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
1110 Intrinsic IntOp, bit Commutable>
1111 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1112 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), IIC_VSUBiD,
1113 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1114 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
1115 let isCommutable = Commutable;
1118 // Pairwise long 2-register intrinsics, both double- and quad-register.
1119 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1120 bits<2> op17_16, bits<5> op11_7, bit op4,
1121 string OpcodeStr, string Dt,
1122 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1123 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1124 (ins DPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
1125 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
1126 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1127 bits<2> op17_16, bits<5> op11_7, bit op4,
1128 string OpcodeStr, string Dt,
1129 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1130 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1131 (ins QPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
1132 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
1134 // Pairwise long 2-register accumulate intrinsics,
1135 // both double- and quad-register.
1136 // The destination register is also used as the first source operand register.
1137 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1138 bits<2> op17_16, bits<5> op11_7, bit op4,
1139 string OpcodeStr, string Dt,
1140 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1141 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
1142 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), IIC_VPALiD,
1143 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
1144 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
1145 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1146 bits<2> op17_16, bits<5> op11_7, bit op4,
1147 string OpcodeStr, string Dt,
1148 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1149 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
1150 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VPALiQ,
1151 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
1152 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
1154 // Shift by immediate,
1155 // both double- and quad-register.
1156 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1157 InstrItinClass itin, string OpcodeStr, string Dt,
1158 ValueType Ty, SDNode OpNode>
1159 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1160 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), itin,
1161 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1162 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
1163 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1164 InstrItinClass itin, string OpcodeStr, string Dt,
1165 ValueType Ty, SDNode OpNode>
1166 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1167 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin,
1168 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1169 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
1171 // Long shift by immediate.
1172 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1173 string OpcodeStr, string Dt,
1174 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1175 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1176 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VSHLiD,
1177 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1178 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
1179 (i32 imm:$SIMM))))]>;
1181 // Narrow shift by immediate.
1182 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1183 InstrItinClass itin, string OpcodeStr, string Dt,
1184 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1185 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1186 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin,
1187 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1188 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
1189 (i32 imm:$SIMM))))]>;
1191 // Shift right by immediate and accumulate,
1192 // both double- and quad-register.
1193 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1194 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1195 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1196 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), IIC_VPALiD,
1197 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1198 [(set DPR:$dst, (Ty (add DPR:$src1,
1199 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
1200 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1201 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1202 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1203 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), IIC_VPALiD,
1204 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1205 [(set QPR:$dst, (Ty (add QPR:$src1,
1206 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
1208 // Shift by immediate and insert,
1209 // both double- and quad-register.
1210 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1211 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1212 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1213 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), IIC_VSHLiD,
1214 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1215 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
1216 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1217 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1218 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1219 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), IIC_VSHLiQ,
1220 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1221 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
1223 // Convert, with fractional bits immediate,
1224 // both double- and quad-register.
1225 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1226 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1228 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1229 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VUNAD,
1230 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1231 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
1232 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1233 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1235 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1236 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), IIC_VUNAQ,
1237 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1238 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
1240 //===----------------------------------------------------------------------===//
1242 //===----------------------------------------------------------------------===//
1244 // Abbreviations used in multiclass suffixes:
1245 // Q = quarter int (8 bit) elements
1246 // H = half int (16 bit) elements
1247 // S = single int (32 bit) elements
1248 // D = double int (64 bit) elements
1250 // Neon 3-register vector operations.
1252 // First with only element sizes of 8, 16 and 32 bits:
1253 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1254 InstrItinClass itinD16, InstrItinClass itinD32,
1255 InstrItinClass itinQ16, InstrItinClass itinQ32,
1256 string OpcodeStr, string Dt,
1257 SDNode OpNode, bit Commutable = 0> {
1258 // 64-bit vector types.
1259 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
1260 OpcodeStr, !strconcat(Dt, "8"),
1261 v8i8, v8i8, OpNode, Commutable>;
1262 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
1263 OpcodeStr, !strconcat(Dt, "16"),
1264 v4i16, v4i16, OpNode, Commutable>;
1265 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
1266 OpcodeStr, !strconcat(Dt, "32"),
1267 v2i32, v2i32, OpNode, Commutable>;
1269 // 128-bit vector types.
1270 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
1271 OpcodeStr, !strconcat(Dt, "8"),
1272 v16i8, v16i8, OpNode, Commutable>;
1273 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
1274 OpcodeStr, !strconcat(Dt, "16"),
1275 v8i16, v8i16, OpNode, Commutable>;
1276 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
1277 OpcodeStr, !strconcat(Dt, "32"),
1278 v4i32, v4i32, OpNode, Commutable>;
1281 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
1282 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1284 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
1286 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1287 v8i16, v4i16, ShOp>;
1288 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
1289 v4i32, v2i32, ShOp>;
1292 // ....then also with element size 64 bits:
1293 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1294 InstrItinClass itinD, InstrItinClass itinQ,
1295 string OpcodeStr, string Dt,
1296 SDNode OpNode, bit Commutable = 0>
1297 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
1298 OpcodeStr, Dt, OpNode, Commutable> {
1299 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
1300 OpcodeStr, !strconcat(Dt, "64"),
1301 v1i64, v1i64, OpNode, Commutable>;
1302 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
1303 OpcodeStr, !strconcat(Dt, "64"),
1304 v2i64, v2i64, OpNode, Commutable>;
1308 // Neon Narrowing 2-register vector intrinsics,
1309 // source operand element sizes of 16, 32 and 64 bits:
1310 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1311 bits<5> op11_7, bit op6, bit op4,
1312 InstrItinClass itin, string OpcodeStr, string Dt,
1314 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
1315 itin, OpcodeStr, !strconcat(Dt, "16"),
1316 v8i8, v8i16, IntOp>;
1317 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
1318 itin, OpcodeStr, !strconcat(Dt, "32"),
1319 v4i16, v4i32, IntOp>;
1320 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
1321 itin, OpcodeStr, !strconcat(Dt, "64"),
1322 v2i32, v2i64, IntOp>;
1326 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
1327 // source operand element sizes of 16, 32 and 64 bits:
1328 multiclass N2VLInt_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
1329 string OpcodeStr, string Dt, Intrinsic IntOp> {
1330 def v8i16 : N2VLInt<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1331 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
1332 def v4i32 : N2VLInt<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1333 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1334 def v2i64 : N2VLInt<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1335 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1339 // Neon 3-register vector intrinsics.
1341 // First with only element sizes of 16 and 32 bits:
1342 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1343 InstrItinClass itinD16, InstrItinClass itinD32,
1344 InstrItinClass itinQ16, InstrItinClass itinQ32,
1345 string OpcodeStr, string Dt,
1346 Intrinsic IntOp, bit Commutable = 0> {
1347 // 64-bit vector types.
1348 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, itinD16,
1349 OpcodeStr, !strconcat(Dt, "16"),
1350 v4i16, v4i16, IntOp, Commutable>;
1351 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, itinD32,
1352 OpcodeStr, !strconcat(Dt, "32"),
1353 v2i32, v2i32, IntOp, Commutable>;
1355 // 128-bit vector types.
1356 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, itinQ16,
1357 OpcodeStr, !strconcat(Dt, "16"),
1358 v8i16, v8i16, IntOp, Commutable>;
1359 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, itinQ32,
1360 OpcodeStr, !strconcat(Dt, "32"),
1361 v4i32, v4i32, IntOp, Commutable>;
1364 multiclass N3VIntSL_HS<bits<4> op11_8,
1365 InstrItinClass itinD16, InstrItinClass itinD32,
1366 InstrItinClass itinQ16, InstrItinClass itinQ32,
1367 string OpcodeStr, string Dt, Intrinsic IntOp> {
1368 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
1369 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
1370 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
1371 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
1372 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
1373 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
1374 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
1375 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
1378 // ....then also with element size of 8 bits:
1379 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1380 InstrItinClass itinD16, InstrItinClass itinD32,
1381 InstrItinClass itinQ16, InstrItinClass itinQ32,
1382 string OpcodeStr, string Dt,
1383 Intrinsic IntOp, bit Commutable = 0>
1384 : N3VInt_HS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
1385 OpcodeStr, Dt, IntOp, Commutable> {
1386 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, itinD16,
1387 OpcodeStr, !strconcat(Dt, "8"),
1388 v8i8, v8i8, IntOp, Commutable>;
1389 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, itinQ16,
1390 OpcodeStr, !strconcat(Dt, "8"),
1391 v16i8, v16i8, IntOp, Commutable>;
1394 // ....then also with element size of 64 bits:
1395 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1396 InstrItinClass itinD16, InstrItinClass itinD32,
1397 InstrItinClass itinQ16, InstrItinClass itinQ32,
1398 string OpcodeStr, string Dt,
1399 Intrinsic IntOp, bit Commutable = 0>
1400 : N3VInt_QHS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
1401 OpcodeStr, Dt, IntOp, Commutable> {
1402 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, itinD32,
1403 OpcodeStr, !strconcat(Dt, "64"),
1404 v1i64, v1i64, IntOp, Commutable>;
1405 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, itinQ32,
1406 OpcodeStr, !strconcat(Dt, "64"),
1407 v2i64, v2i64, IntOp, Commutable>;
1411 // Neon Narrowing 3-register vector intrinsics,
1412 // source operand element sizes of 16, 32 and 64 bits:
1413 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1414 string OpcodeStr, string Dt,
1415 Intrinsic IntOp, bit Commutable = 0> {
1416 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
1417 OpcodeStr, !strconcat(Dt, "16"),
1418 v8i8, v8i16, IntOp, Commutable>;
1419 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
1420 OpcodeStr, !strconcat(Dt, "32"),
1421 v4i16, v4i32, IntOp, Commutable>;
1422 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
1423 OpcodeStr, !strconcat(Dt, "64"),
1424 v2i32, v2i64, IntOp, Commutable>;
1428 // Neon Long 3-register vector intrinsics.
1430 // First with only element sizes of 16 and 32 bits:
1431 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1432 InstrItinClass itin, string OpcodeStr, string Dt,
1433 Intrinsic IntOp, bit Commutable = 0> {
1434 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin,
1435 OpcodeStr, !strconcat(Dt, "16"),
1436 v4i32, v4i16, IntOp, Commutable>;
1437 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin,
1438 OpcodeStr, !strconcat(Dt, "32"),
1439 v2i64, v2i32, IntOp, Commutable>;
1442 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
1443 InstrItinClass itin, string OpcodeStr, string Dt,
1445 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
1446 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1447 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
1448 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1451 // ....then also with element size of 8 bits:
1452 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1453 InstrItinClass itin, string OpcodeStr, string Dt,
1454 Intrinsic IntOp, bit Commutable = 0>
1455 : N3VLInt_HS<op24, op23, op11_8, op4, itin, OpcodeStr, Dt,
1456 IntOp, Commutable> {
1457 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin,
1458 OpcodeStr, !strconcat(Dt, "8"),
1459 v8i16, v8i8, IntOp, Commutable>;
1463 // Neon Wide 3-register vector intrinsics,
1464 // source operand element sizes of 8, 16 and 32 bits:
1465 multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1466 string OpcodeStr, string Dt,
1467 Intrinsic IntOp, bit Commutable = 0> {
1468 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4,
1469 OpcodeStr, !strconcat(Dt, "8"),
1470 v8i16, v8i8, IntOp, Commutable>;
1471 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4,
1472 OpcodeStr, !strconcat(Dt, "16"),
1473 v4i32, v4i16, IntOp, Commutable>;
1474 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4,
1475 OpcodeStr, !strconcat(Dt, "32"),
1476 v2i64, v2i32, IntOp, Commutable>;
1480 // Neon Multiply-Op vector operations,
1481 // element sizes of 8, 16 and 32 bits:
1482 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1483 InstrItinClass itinD16, InstrItinClass itinD32,
1484 InstrItinClass itinQ16, InstrItinClass itinQ32,
1485 string OpcodeStr, string Dt, SDNode OpNode> {
1486 // 64-bit vector types.
1487 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
1488 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
1489 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
1490 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
1491 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
1492 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
1494 // 128-bit vector types.
1495 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
1496 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
1497 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
1498 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
1499 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
1500 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
1503 multiclass N3VMulOpSL_HS<bits<4> op11_8,
1504 InstrItinClass itinD16, InstrItinClass itinD32,
1505 InstrItinClass itinQ16, InstrItinClass itinQ32,
1506 string OpcodeStr, string Dt, SDNode ShOp> {
1507 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
1508 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
1509 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
1510 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
1511 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
1512 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, mul, ShOp>;
1513 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
1514 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, mul, ShOp>;
1517 // Neon 3-argument intrinsics,
1518 // element sizes of 8, 16 and 32 bits:
1519 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1520 string OpcodeStr, string Dt, Intrinsic IntOp> {
1521 // 64-bit vector types.
1522 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16D,
1523 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
1524 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
1525 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
1526 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32D,
1527 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
1529 // 128-bit vector types.
1530 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16Q,
1531 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
1532 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16Q,
1533 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
1534 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32Q,
1535 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
1539 // Neon Long 3-argument intrinsics.
1541 // First with only element sizes of 16 and 32 bits:
1542 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1543 string OpcodeStr, string Dt, Intrinsic IntOp> {
1544 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
1545 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1546 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi16D,
1547 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1550 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
1551 string OpcodeStr, string Dt, Intrinsic IntOp> {
1552 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
1553 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
1554 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
1555 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1558 // ....then also with element size of 8 bits:
1559 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1560 string OpcodeStr, string Dt, Intrinsic IntOp>
1561 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, Dt, IntOp> {
1562 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16D,
1563 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
1567 // Neon 2-register vector intrinsics,
1568 // element sizes of 8, 16 and 32 bits:
1569 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1570 bits<5> op11_7, bit op4,
1571 InstrItinClass itinD, InstrItinClass itinQ,
1572 string OpcodeStr, string Dt, Intrinsic IntOp> {
1573 // 64-bit vector types.
1574 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1575 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
1576 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1577 itinD, OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
1578 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1579 itinD, OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
1581 // 128-bit vector types.
1582 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1583 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
1584 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1585 itinQ, OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
1586 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1587 itinQ, OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
1591 // Neon Pairwise long 2-register intrinsics,
1592 // element sizes of 8, 16 and 32 bits:
1593 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1594 bits<5> op11_7, bit op4,
1595 string OpcodeStr, string Dt, Intrinsic IntOp> {
1596 // 64-bit vector types.
1597 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1598 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
1599 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1600 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
1601 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1602 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
1604 // 128-bit vector types.
1605 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1606 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
1607 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1608 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
1609 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1610 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
1614 // Neon Pairwise long 2-register accumulate intrinsics,
1615 // element sizes of 8, 16 and 32 bits:
1616 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1617 bits<5> op11_7, bit op4,
1618 string OpcodeStr, string Dt, Intrinsic IntOp> {
1619 // 64-bit vector types.
1620 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1621 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
1622 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1623 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
1624 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1625 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
1627 // 128-bit vector types.
1628 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1629 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
1630 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1631 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
1632 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1633 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
1637 // Neon 2-register vector shift by immediate,
1638 // element sizes of 8, 16, 32 and 64 bits:
1639 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1640 InstrItinClass itin, string OpcodeStr, string Dt,
1642 // 64-bit vector types.
1643 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
1644 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
1645 let Inst{21-19} = 0b001; // imm6 = 001xxx
1647 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
1648 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
1649 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1651 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
1652 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
1653 let Inst{21} = 0b1; // imm6 = 1xxxxx
1655 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, itin,
1656 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
1659 // 128-bit vector types.
1660 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
1661 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
1662 let Inst{21-19} = 0b001; // imm6 = 001xxx
1664 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
1665 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
1666 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1668 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
1669 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
1670 let Inst{21} = 0b1; // imm6 = 1xxxxx
1672 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, itin,
1673 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
1678 // Neon Shift-Accumulate vector operations,
1679 // element sizes of 8, 16, 32 and 64 bits:
1680 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1681 string OpcodeStr, string Dt, SDNode ShOp> {
1682 // 64-bit vector types.
1683 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1684 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
1685 let Inst{21-19} = 0b001; // imm6 = 001xxx
1687 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1688 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
1689 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1691 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1692 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
1693 let Inst{21} = 0b1; // imm6 = 1xxxxx
1695 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4,
1696 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
1699 // 128-bit vector types.
1700 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1701 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
1702 let Inst{21-19} = 0b001; // imm6 = 001xxx
1704 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1705 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
1706 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1708 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1709 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
1710 let Inst{21} = 0b1; // imm6 = 1xxxxx
1712 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4,
1713 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
1718 // Neon Shift-Insert vector operations,
1719 // element sizes of 8, 16, 32 and 64 bits:
1720 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1721 string OpcodeStr, SDNode ShOp> {
1722 // 64-bit vector types.
1723 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4,
1724 OpcodeStr, "8", v8i8, ShOp> {
1725 let Inst{21-19} = 0b001; // imm6 = 001xxx
1727 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4,
1728 OpcodeStr, "16", v4i16, ShOp> {
1729 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1731 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4,
1732 OpcodeStr, "32", v2i32, ShOp> {
1733 let Inst{21} = 0b1; // imm6 = 1xxxxx
1735 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4,
1736 OpcodeStr, "64", v1i64, ShOp>;
1739 // 128-bit vector types.
1740 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4,
1741 OpcodeStr, "8", v16i8, ShOp> {
1742 let Inst{21-19} = 0b001; // imm6 = 001xxx
1744 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4,
1745 OpcodeStr, "16", v8i16, ShOp> {
1746 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1748 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4,
1749 OpcodeStr, "32", v4i32, ShOp> {
1750 let Inst{21} = 0b1; // imm6 = 1xxxxx
1752 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4,
1753 OpcodeStr, "64", v2i64, ShOp>;
1757 // Neon Shift Long operations,
1758 // element sizes of 8, 16, 32 bits:
1759 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
1760 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
1761 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1762 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
1763 let Inst{21-19} = 0b001; // imm6 = 001xxx
1765 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1766 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
1767 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1769 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1770 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
1771 let Inst{21} = 0b1; // imm6 = 1xxxxx
1775 // Neon Shift Narrow operations,
1776 // element sizes of 16, 32, 64 bits:
1777 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
1778 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
1780 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1781 OpcodeStr, !strconcat(Dt, "16"), v8i8, v8i16, OpNode> {
1782 let Inst{21-19} = 0b001; // imm6 = 001xxx
1784 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1785 OpcodeStr, !strconcat(Dt, "32"), v4i16, v4i32, OpNode> {
1786 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1788 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1789 OpcodeStr, !strconcat(Dt, "64"), v2i32, v2i64, OpNode> {
1790 let Inst{21} = 0b1; // imm6 = 1xxxxx
1794 //===----------------------------------------------------------------------===//
1795 // Instruction Definitions.
1796 //===----------------------------------------------------------------------===//
1798 // Vector Add Operations.
1800 // VADD : Vector Add (integer and floating-point)
1801 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
1803 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
1804 v2f32, v2f32, fadd, 1>;
1805 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
1806 v4f32, v4f32, fadd, 1>;
1807 // VADDL : Vector Add Long (Q = D + D)
1808 defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, IIC_VSHLiD, "vaddl", "s",
1809 int_arm_neon_vaddls, 1>;
1810 defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, IIC_VSHLiD, "vaddl", "u",
1811 int_arm_neon_vaddlu, 1>;
1812 // VADDW : Vector Add Wide (Q = Q + D)
1813 defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw", "s", int_arm_neon_vaddws, 0>;
1814 defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw", "u", int_arm_neon_vaddwu, 0>;
1815 // VHADD : Vector Halving Add
1816 defm VHADDs : N3VInt_QHS<0,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1817 IIC_VBINi4Q, "vhadd", "s", int_arm_neon_vhadds, 1>;
1818 defm VHADDu : N3VInt_QHS<1,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1819 IIC_VBINi4Q, "vhadd", "u", int_arm_neon_vhaddu, 1>;
1820 // VRHADD : Vector Rounding Halving Add
1821 defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1822 IIC_VBINi4Q, "vrhadd", "s", int_arm_neon_vrhadds, 1>;
1823 defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1824 IIC_VBINi4Q, "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
1825 // VQADD : Vector Saturating Add
1826 defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1827 IIC_VBINi4Q, "vqadd", "s", int_arm_neon_vqadds, 1>;
1828 defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1829 IIC_VBINi4Q, "vqadd", "u", int_arm_neon_vqaddu, 1>;
1830 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
1831 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
1832 int_arm_neon_vaddhn, 1>;
1833 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
1834 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
1835 int_arm_neon_vraddhn, 1>;
1837 // Vector Multiply Operations.
1839 // VMUL : Vector Multiply (integer, polynomial and floating-point)
1840 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
1841 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
1842 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16D, "vmul", "p8",
1843 v8i8, v8i8, int_arm_neon_vmulp, 1>;
1844 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16Q, "vmul", "p8",
1845 v16i8, v16i8, int_arm_neon_vmulp, 1>;
1846 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VBIND, "vmul", "f32",
1847 v2f32, v2f32, fmul, 1>;
1848 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VBINQ, "vmul", "f32",
1849 v4f32, v4f32, fmul, 1>;
1850 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
1851 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
1852 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32, v2f32, fmul>;
1853 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
1854 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
1855 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
1856 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1857 (DSubReg_i16_reg imm:$lane))),
1858 (SubReg_i16_lane imm:$lane)))>;
1859 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
1860 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
1861 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
1862 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1863 (DSubReg_i32_reg imm:$lane))),
1864 (SubReg_i32_lane imm:$lane)))>;
1865 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
1866 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
1867 (v4f32 (VMULslfq (v4f32 QPR:$src1),
1868 (v2f32 (EXTRACT_SUBREG QPR:$src2,
1869 (DSubReg_i32_reg imm:$lane))),
1870 (SubReg_i32_lane imm:$lane)))>;
1872 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
1873 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
1874 IIC_VMULi16Q, IIC_VMULi32Q,
1875 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
1876 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
1877 IIC_VMULi16Q, IIC_VMULi32Q,
1878 "vqdmulh", "s", int_arm_neon_vqdmulh>;
1879 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
1880 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
1882 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
1883 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1884 (DSubReg_i16_reg imm:$lane))),
1885 (SubReg_i16_lane imm:$lane)))>;
1886 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
1887 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
1889 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
1890 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1891 (DSubReg_i32_reg imm:$lane))),
1892 (SubReg_i32_lane imm:$lane)))>;
1894 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
1895 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
1896 IIC_VMULi16Q, IIC_VMULi32Q,
1897 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
1898 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
1899 IIC_VMULi16Q, IIC_VMULi32Q,
1900 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
1901 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
1902 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
1904 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
1905 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1906 (DSubReg_i16_reg imm:$lane))),
1907 (SubReg_i16_lane imm:$lane)))>;
1908 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
1909 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
1911 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
1912 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1913 (DSubReg_i32_reg imm:$lane))),
1914 (SubReg_i32_lane imm:$lane)))>;
1916 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
1917 defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, IIC_VMULi16D, "vmull", "s",
1918 int_arm_neon_vmulls, 1>;
1919 defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, IIC_VMULi16D, "vmull", "u",
1920 int_arm_neon_vmullu, 1>;
1921 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
1922 v8i16, v8i8, int_arm_neon_vmullp, 1>;
1923 defm VMULLsls : N3VLIntSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s",
1924 int_arm_neon_vmulls>;
1925 defm VMULLslu : N3VLIntSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u",
1926 int_arm_neon_vmullu>;
1928 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
1929 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, "vqdmull", "s",
1930 int_arm_neon_vqdmull, 1>;
1931 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D, "vqdmull", "s",
1932 int_arm_neon_vqdmull>;
1934 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
1936 // VMLA : Vector Multiply Accumulate (integer and floating-point)
1937 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
1938 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
1939 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
1941 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
1943 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
1944 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
1945 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
1947 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
1948 v4f32, v2f32, fmul, fadd>;
1950 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
1951 (mul (v8i16 QPR:$src2),
1952 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
1953 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1),
1955 (v4i16 (EXTRACT_SUBREG QPR:$src3,
1956 (DSubReg_i16_reg imm:$lane))),
1957 (SubReg_i16_lane imm:$lane)))>;
1959 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
1960 (mul (v4i32 QPR:$src2),
1961 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
1962 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1),
1964 (v2i32 (EXTRACT_SUBREG QPR:$src3,
1965 (DSubReg_i32_reg imm:$lane))),
1966 (SubReg_i32_lane imm:$lane)))>;
1968 def : Pat<(v4f32 (fadd (v4f32 QPR:$src1),
1969 (fmul (v4f32 QPR:$src2),
1970 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
1971 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
1973 (v2f32 (EXTRACT_SUBREG QPR:$src3,
1974 (DSubReg_i32_reg imm:$lane))),
1975 (SubReg_i32_lane imm:$lane)))>;
1977 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
1978 defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal", "s", int_arm_neon_vmlals>;
1979 defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal", "u", int_arm_neon_vmlalu>;
1981 defm VMLALsls : N3VLInt3SL_HS<0, 0b0010, "vmlal", "s", int_arm_neon_vmlals>;
1982 defm VMLALslu : N3VLInt3SL_HS<1, 0b0010, "vmlal", "u", int_arm_neon_vmlalu>;
1984 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
1985 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal", "s",
1986 int_arm_neon_vqdmlal>;
1987 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
1989 // VMLS : Vector Multiply Subtract (integer and floating-point)
1990 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
1991 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
1992 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
1994 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
1996 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
1997 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
1998 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
2000 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
2001 v4f32, v2f32, fmul, fsub>;
2003 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
2004 (mul (v8i16 QPR:$src2),
2005 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
2006 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1),
2008 (v4i16 (EXTRACT_SUBREG QPR:$src3,
2009 (DSubReg_i16_reg imm:$lane))),
2010 (SubReg_i16_lane imm:$lane)))>;
2012 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
2013 (mul (v4i32 QPR:$src2),
2014 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
2015 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1),
2017 (v2i32 (EXTRACT_SUBREG QPR:$src3,
2018 (DSubReg_i32_reg imm:$lane))),
2019 (SubReg_i32_lane imm:$lane)))>;
2021 def : Pat<(v4f32 (fsub (v4f32 QPR:$src1),
2022 (fmul (v4f32 QPR:$src2),
2023 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
2024 (v4f32 (VMLSslfq (v4f32 QPR:$src1),
2026 (v2f32 (EXTRACT_SUBREG QPR:$src3,
2027 (DSubReg_i32_reg imm:$lane))),
2028 (SubReg_i32_lane imm:$lane)))>;
2030 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
2031 defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl", "s", int_arm_neon_vmlsls>;
2032 defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl", "u", int_arm_neon_vmlslu>;
2034 defm VMLSLsls : N3VLInt3SL_HS<0, 0b0110, "vmlsl", "s", int_arm_neon_vmlsls>;
2035 defm VMLSLslu : N3VLInt3SL_HS<1, 0b0110, "vmlsl", "u", int_arm_neon_vmlslu>;
2037 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
2038 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl", "s",
2039 int_arm_neon_vqdmlsl>;
2040 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
2042 // Vector Subtract Operations.
2044 // VSUB : Vector Subtract (integer and floating-point)
2045 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
2046 "vsub", "i", sub, 0>;
2047 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
2048 v2f32, v2f32, fsub, 0>;
2049 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
2050 v4f32, v4f32, fsub, 0>;
2051 // VSUBL : Vector Subtract Long (Q = D - D)
2052 defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, IIC_VSHLiD, "vsubl", "s",
2053 int_arm_neon_vsubls, 1>;
2054 defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, IIC_VSHLiD, "vsubl", "u",
2055 int_arm_neon_vsublu, 1>;
2056 // VSUBW : Vector Subtract Wide (Q = Q - D)
2057 defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw", "s", int_arm_neon_vsubws, 0>;
2058 defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw", "u", int_arm_neon_vsubwu, 0>;
2059 // VHSUB : Vector Halving Subtract
2060 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D,
2061 IIC_VBINi4Q, IIC_VBINi4Q,
2062 "vhsub", "s", int_arm_neon_vhsubs, 0>;
2063 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D,
2064 IIC_VBINi4Q, IIC_VBINi4Q,
2065 "vhsub", "u", int_arm_neon_vhsubu, 0>;
2066 // VQSUB : Vector Saturing Subtract
2067 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D,
2068 IIC_VBINi4Q, IIC_VBINi4Q,
2069 "vqsub", "s", int_arm_neon_vqsubs, 0>;
2070 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D,
2071 IIC_VBINi4Q, IIC_VBINi4Q,
2072 "vqsub", "u", int_arm_neon_vqsubu, 0>;
2073 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
2074 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
2075 int_arm_neon_vsubhn, 0>;
2076 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
2077 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
2078 int_arm_neon_vrsubhn, 0>;
2080 // Vector Comparisons.
2082 // VCEQ : Vector Compare Equal
2083 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2084 IIC_VBINi4Q, "vceq", "i", NEONvceq, 1>;
2085 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
2087 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
2089 // VCGE : Vector Compare Greater Than or Equal
2090 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2091 IIC_VBINi4Q, "vcge", "s", NEONvcge, 0>;
2092 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2093 IIC_VBINi4Q, "vcge", "u", NEONvcgeu, 0>;
2094 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32",
2095 v2i32, v2f32, NEONvcge, 0>;
2096 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
2098 // VCGT : Vector Compare Greater Than
2099 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2100 IIC_VBINi4Q, "vcgt", "s", NEONvcgt, 0>;
2101 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2102 IIC_VBINi4Q, "vcgt", "u", NEONvcgtu, 0>;
2103 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
2105 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
2107 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
2108 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, IIC_VBIND, "vacge", "f32",
2109 v2i32, v2f32, int_arm_neon_vacged, 0>;
2110 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, IIC_VBINQ, "vacge", "f32",
2111 v4i32, v4f32, int_arm_neon_vacgeq, 0>;
2112 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
2113 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, IIC_VBIND, "vacgt", "f32",
2114 v2i32, v2f32, int_arm_neon_vacgtd, 0>;
2115 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, IIC_VBINQ, "vacgt", "f32",
2116 v4i32, v4f32, int_arm_neon_vacgtq, 0>;
2117 // VTST : Vector Test Bits
2118 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2119 IIC_VBINi4Q, "vtst", "i", NEONvtst, 1>;
2121 // Vector Bitwise Operations.
2123 // VAND : Vector Bitwise AND
2124 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
2125 v2i32, v2i32, and, 1>;
2126 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
2127 v4i32, v4i32, and, 1>;
2129 // VEOR : Vector Bitwise Exclusive OR
2130 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
2131 v2i32, v2i32, xor, 1>;
2132 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
2133 v4i32, v4i32, xor, 1>;
2135 // VORR : Vector Bitwise OR
2136 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
2137 v2i32, v2i32, or, 1>;
2138 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
2139 v4i32, v4i32, or, 1>;
2141 // VBIC : Vector Bitwise Bit Clear (AND NOT)
2142 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2143 (ins DPR:$src1, DPR:$src2), IIC_VBINiD,
2144 "vbic", "$dst, $src1, $src2", "",
2145 [(set DPR:$dst, (v2i32 (and DPR:$src1,
2146 (vnot_conv DPR:$src2))))]>;
2147 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2148 (ins QPR:$src1, QPR:$src2), IIC_VBINiQ,
2149 "vbic", "$dst, $src1, $src2", "",
2150 [(set QPR:$dst, (v4i32 (and QPR:$src1,
2151 (vnot_conv QPR:$src2))))]>;
2153 // VORN : Vector Bitwise OR NOT
2154 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
2155 (ins DPR:$src1, DPR:$src2), IIC_VBINiD,
2156 "vorn", "$dst, $src1, $src2", "",
2157 [(set DPR:$dst, (v2i32 (or DPR:$src1,
2158 (vnot_conv DPR:$src2))))]>;
2159 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
2160 (ins QPR:$src1, QPR:$src2), IIC_VBINiQ,
2161 "vorn", "$dst, $src1, $src2", "",
2162 [(set QPR:$dst, (v4i32 (or QPR:$src1,
2163 (vnot_conv QPR:$src2))))]>;
2165 // VMVN : Vector Bitwise NOT
2166 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
2167 (outs DPR:$dst), (ins DPR:$src), IIC_VSHLiD,
2168 "vmvn", "$dst, $src", "",
2169 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>;
2170 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
2171 (outs QPR:$dst), (ins QPR:$src), IIC_VSHLiD,
2172 "vmvn", "$dst, $src", "",
2173 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>;
2174 def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>;
2175 def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>;
2177 // VBSL : Vector Bitwise Select
2178 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2179 (ins DPR:$src1, DPR:$src2, DPR:$src3), IIC_VCNTiD,
2180 "vbsl", "$dst, $src2, $src3", "$src1 = $dst",
2182 (v2i32 (or (and DPR:$src2, DPR:$src1),
2183 (and DPR:$src3, (vnot_conv DPR:$src1)))))]>;
2184 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2185 (ins QPR:$src1, QPR:$src2, QPR:$src3), IIC_VCNTiQ,
2186 "vbsl", "$dst, $src2, $src3", "$src1 = $dst",
2188 (v4i32 (or (and QPR:$src2, QPR:$src1),
2189 (and QPR:$src3, (vnot_conv QPR:$src1)))))]>;
2191 // VBIF : Vector Bitwise Insert if False
2192 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
2193 // VBIT : Vector Bitwise Insert if True
2194 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
2195 // These are not yet implemented. The TwoAddress pass will not go looking
2196 // for equivalent operations with different register constraints; it just
2199 // Vector Absolute Differences.
2201 // VABD : Vector Absolute Difference
2202 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D,
2203 IIC_VBINi4Q, IIC_VBINi4Q,
2204 "vabd", "s", int_arm_neon_vabds, 0>;
2205 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D,
2206 IIC_VBINi4Q, IIC_VBINi4Q,
2207 "vabd", "u", int_arm_neon_vabdu, 0>;
2208 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, IIC_VBIND,
2209 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 0>;
2210 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, IIC_VBINQ,
2211 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 0>;
2213 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
2214 defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, IIC_VBINi4Q,
2215 "vabdl", "s", int_arm_neon_vabdls, 0>;
2216 defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, IIC_VBINi4Q,
2217 "vabdl", "u", int_arm_neon_vabdlu, 0>;
2219 // VABA : Vector Absolute Difference and Accumulate
2220 defm VABAs : N3VInt3_QHS<0,0,0b0111,1, "vaba", "s", int_arm_neon_vabas>;
2221 defm VABAu : N3VInt3_QHS<1,0,0b0111,1, "vaba", "u", int_arm_neon_vabau>;
2223 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
2224 defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal", "s", int_arm_neon_vabals>;
2225 defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal", "u", int_arm_neon_vabalu>;
2227 // Vector Maximum and Minimum.
2229 // VMAX : Vector Maximum
2230 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2231 IIC_VBINi4Q, "vmax", "s", int_arm_neon_vmaxs, 1>;
2232 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2233 IIC_VBINi4Q, "vmax", "u", int_arm_neon_vmaxu, 1>;
2234 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, IIC_VBIND, "vmax", "f32",
2235 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
2236 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, IIC_VBINQ, "vmax", "f32",
2237 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
2239 // VMIN : Vector Minimum
2240 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2241 IIC_VBINi4Q, "vmin", "s", int_arm_neon_vmins, 1>;
2242 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2243 IIC_VBINi4Q, "vmin", "u", int_arm_neon_vminu, 1>;
2244 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, IIC_VBIND, "vmin", "f32",
2245 v2f32, v2f32, int_arm_neon_vmins, 1>;
2246 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, IIC_VBINQ, "vmin", "f32",
2247 v4f32, v4f32, int_arm_neon_vmins, 1>;
2249 // Vector Pairwise Operations.
2251 // VPADD : Vector Pairwise Add
2252 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, IIC_VBINiD, "vpadd", "i8",
2253 v8i8, v8i8, int_arm_neon_vpadd, 0>;
2254 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, IIC_VBINiD, "vpadd", "i16",
2255 v4i16, v4i16, int_arm_neon_vpadd, 0>;
2256 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, IIC_VBINiD, "vpadd", "i32",
2257 v2i32, v2i32, int_arm_neon_vpadd, 0>;
2258 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, IIC_VBIND, "vpadd", "f32",
2259 v2f32, v2f32, int_arm_neon_vpadd, 0>;
2261 // VPADDL : Vector Pairwise Add Long
2262 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
2263 int_arm_neon_vpaddls>;
2264 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
2265 int_arm_neon_vpaddlu>;
2267 // VPADAL : Vector Pairwise Add and Accumulate Long
2268 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
2269 int_arm_neon_vpadals>;
2270 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
2271 int_arm_neon_vpadalu>;
2273 // VPMAX : Vector Pairwise Maximum
2274 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax", "s8",
2275 v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
2276 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax", "s16",
2277 v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
2278 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax", "s32",
2279 v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
2280 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax", "u8",
2281 v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
2282 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax", "u16",
2283 v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
2284 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax", "u32",
2285 v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
2286 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, IIC_VBINi4D, "vpmax", "f32",
2287 v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
2289 // VPMIN : Vector Pairwise Minimum
2290 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin", "s8",
2291 v8i8, v8i8, int_arm_neon_vpmins, 0>;
2292 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin", "s16",
2293 v4i16, v4i16, int_arm_neon_vpmins, 0>;
2294 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin", "s32",
2295 v2i32, v2i32, int_arm_neon_vpmins, 0>;
2296 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin", "u8",
2297 v8i8, v8i8, int_arm_neon_vpminu, 0>;
2298 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin", "u16",
2299 v4i16, v4i16, int_arm_neon_vpminu, 0>;
2300 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin", "u32",
2301 v2i32, v2i32, int_arm_neon_vpminu, 0>;
2302 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, IIC_VBINi4D, "vpmin", "f32",
2303 v2f32, v2f32, int_arm_neon_vpmins, 0>;
2305 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
2307 // VRECPE : Vector Reciprocal Estimate
2308 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
2309 IIC_VUNAD, "vrecpe", "u32",
2310 v2i32, v2i32, int_arm_neon_vrecpe>;
2311 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
2312 IIC_VUNAQ, "vrecpe", "u32",
2313 v4i32, v4i32, int_arm_neon_vrecpe>;
2314 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
2315 IIC_VUNAD, "vrecpe", "f32",
2316 v2f32, v2f32, int_arm_neon_vrecpe>;
2317 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
2318 IIC_VUNAQ, "vrecpe", "f32",
2319 v4f32, v4f32, int_arm_neon_vrecpe>;
2321 // VRECPS : Vector Reciprocal Step
2322 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1,
2323 IIC_VRECSD, "vrecps", "f32",
2324 v2f32, v2f32, int_arm_neon_vrecps, 1>;
2325 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1,
2326 IIC_VRECSQ, "vrecps", "f32",
2327 v4f32, v4f32, int_arm_neon_vrecps, 1>;
2329 // VRSQRTE : Vector Reciprocal Square Root Estimate
2330 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
2331 IIC_VUNAD, "vrsqrte", "u32",
2332 v2i32, v2i32, int_arm_neon_vrsqrte>;
2333 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
2334 IIC_VUNAQ, "vrsqrte", "u32",
2335 v4i32, v4i32, int_arm_neon_vrsqrte>;
2336 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
2337 IIC_VUNAD, "vrsqrte", "f32",
2338 v2f32, v2f32, int_arm_neon_vrsqrte>;
2339 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
2340 IIC_VUNAQ, "vrsqrte", "f32",
2341 v4f32, v4f32, int_arm_neon_vrsqrte>;
2343 // VRSQRTS : Vector Reciprocal Square Root Step
2344 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1,
2345 IIC_VRECSD, "vrsqrts", "f32",
2346 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
2347 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1,
2348 IIC_VRECSQ, "vrsqrts", "f32",
2349 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
2353 // VSHL : Vector Shift
2354 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
2355 IIC_VSHLiQ, "vshl", "s", int_arm_neon_vshifts, 0>;
2356 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
2357 IIC_VSHLiQ, "vshl", "u", int_arm_neon_vshiftu, 0>;
2358 // VSHL : Vector Shift Left (Immediate)
2359 defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
2360 // VSHR : Vector Shift Right (Immediate)
2361 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", NEONvshrs>;
2362 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", NEONvshru>;
2364 // VSHLL : Vector Shift Left Long
2365 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
2366 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
2368 // VSHLL : Vector Shift Left Long (with maximum shift count)
2369 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
2370 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
2371 ValueType OpTy, SDNode OpNode>
2372 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
2373 ResTy, OpTy, OpNode> {
2374 let Inst{21-16} = op21_16;
2376 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
2377 v8i16, v8i8, NEONvshlli>;
2378 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
2379 v4i32, v4i16, NEONvshlli>;
2380 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
2381 v2i64, v2i32, NEONvshlli>;
2383 // VSHRN : Vector Shift Right and Narrow
2384 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i", NEONvshrn>;
2386 // VRSHL : Vector Rounding Shift
2387 defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2388 IIC_VSHLi4Q, "vrshl", "s", int_arm_neon_vrshifts, 0>;
2389 defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2390 IIC_VSHLi4Q, "vrshl", "u", int_arm_neon_vrshiftu, 0>;
2391 // VRSHR : Vector Rounding Shift Right
2392 defm VRSHRs : N2VSh_QHSD<0, 1, 0b0010, 1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs>;
2393 defm VRSHRu : N2VSh_QHSD<1, 1, 0b0010, 1, IIC_VSHLi4D, "vrshr", "u", NEONvrshru>;
2395 // VRSHRN : Vector Rounding Shift Right and Narrow
2396 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
2399 // VQSHL : Vector Saturating Shift
2400 defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2401 IIC_VSHLi4Q, "vqshl", "s", int_arm_neon_vqshifts, 0>;
2402 defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2403 IIC_VSHLi4Q, "vqshl", "u", int_arm_neon_vqshiftu, 0>;
2404 // VQSHL : Vector Saturating Shift Left (Immediate)
2405 defm VQSHLsi : N2VSh_QHSD<0, 1, 0b0111, 1, IIC_VSHLi4D, "vqshl", "s", NEONvqshls>;
2406 defm VQSHLui : N2VSh_QHSD<1, 1, 0b0111, 1, IIC_VSHLi4D, "vqshl", "u", NEONvqshlu>;
2407 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
2408 defm VQSHLsu : N2VSh_QHSD<1, 1, 0b0110, 1, IIC_VSHLi4D, "vqshlu", "s", NEONvqshlsu>;
2410 // VQSHRN : Vector Saturating Shift Right and Narrow
2411 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
2413 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
2416 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
2417 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
2420 // VQRSHL : Vector Saturating Rounding Shift
2421 defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2422 IIC_VSHLi4Q, "vqrshl", "s",
2423 int_arm_neon_vqrshifts, 0>;
2424 defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2425 IIC_VSHLi4Q, "vqrshl", "u",
2426 int_arm_neon_vqrshiftu, 0>;
2428 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
2429 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
2431 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
2434 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
2435 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
2438 // VSRA : Vector Shift Right and Accumulate
2439 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
2440 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
2441 // VRSRA : Vector Rounding Shift Right and Accumulate
2442 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
2443 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
2445 // VSLI : Vector Shift Left and Insert
2446 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli", NEONvsli>;
2447 // VSRI : Vector Shift Right and Insert
2448 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri", NEONvsri>;
2450 // Vector Absolute and Saturating Absolute.
2452 // VABS : Vector Absolute Value
2453 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
2454 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
2456 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2457 IIC_VUNAD, "vabs", "f32",
2458 v2f32, v2f32, int_arm_neon_vabs>;
2459 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2460 IIC_VUNAQ, "vabs", "f32",
2461 v4f32, v4f32, int_arm_neon_vabs>;
2463 // VQABS : Vector Saturating Absolute Value
2464 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
2465 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
2466 int_arm_neon_vqabs>;
2470 def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
2471 def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>;
2473 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
2474 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
2475 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
2476 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>;
2477 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
2478 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
2479 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
2480 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>;
2482 // VNEG : Vector Negate
2483 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
2484 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
2485 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
2486 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
2487 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
2488 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
2490 // VNEG : Vector Negate (floating-point)
2491 def VNEGf32d : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
2492 (outs DPR:$dst), (ins DPR:$src), IIC_VUNAD,
2493 "vneg", "f32", "$dst, $src", "",
2494 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
2495 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
2496 (outs QPR:$dst), (ins QPR:$src), IIC_VUNAQ,
2497 "vneg", "f32", "$dst, $src", "",
2498 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
2500 def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
2501 def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
2502 def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>;
2503 def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>;
2504 def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>;
2505 def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>;
2507 // VQNEG : Vector Saturating Negate
2508 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
2509 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
2510 int_arm_neon_vqneg>;
2512 // Vector Bit Counting Operations.
2514 // VCLS : Vector Count Leading Sign Bits
2515 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
2516 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
2518 // VCLZ : Vector Count Leading Zeros
2519 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
2520 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
2522 // VCNT : Vector Count One Bits
2523 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2524 IIC_VCNTiD, "vcnt", "8",
2525 v8i8, v8i8, int_arm_neon_vcnt>;
2526 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2527 IIC_VCNTiQ, "vcnt", "8",
2528 v16i8, v16i8, int_arm_neon_vcnt>;
2530 // Vector Move Operations.
2532 // VMOV : Vector Move (Register)
2534 def VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
2535 IIC_VMOVD, "vmov", "$dst, $src", "", []>;
2536 def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
2537 IIC_VMOVD, "vmov", "$dst, $src", "", []>;
2539 // VMOV : Vector Move (Immediate)
2541 // VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
2542 def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
2543 return ARM::getVMOVImm(N, 1, *CurDAG);
2545 def vmovImm8 : PatLeaf<(build_vector), [{
2546 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
2549 // VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
2550 def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
2551 return ARM::getVMOVImm(N, 2, *CurDAG);
2553 def vmovImm16 : PatLeaf<(build_vector), [{
2554 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
2555 }], VMOV_get_imm16>;
2557 // VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
2558 def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
2559 return ARM::getVMOVImm(N, 4, *CurDAG);
2561 def vmovImm32 : PatLeaf<(build_vector), [{
2562 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
2563 }], VMOV_get_imm32>;
2565 // VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
2566 def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
2567 return ARM::getVMOVImm(N, 8, *CurDAG);
2569 def vmovImm64 : PatLeaf<(build_vector), [{
2570 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
2571 }], VMOV_get_imm64>;
2573 // Note: Some of the cmode bits in the following VMOV instructions need to
2574 // be encoded based on the immed values.
2576 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
2577 (ins h8imm:$SIMM), IIC_VMOVImm,
2578 "vmov", "i8", "$dst, $SIMM", "",
2579 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
2580 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
2581 (ins h8imm:$SIMM), IIC_VMOVImm,
2582 "vmov", "i8", "$dst, $SIMM", "",
2583 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
2585 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,?}, 0, 0, {?}, 1, (outs DPR:$dst),
2586 (ins h16imm:$SIMM), IIC_VMOVImm,
2587 "vmov", "i16", "$dst, $SIMM", "",
2588 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
2589 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,?}, 0, 1, {?}, 1, (outs QPR:$dst),
2590 (ins h16imm:$SIMM), IIC_VMOVImm,
2591 "vmov", "i16", "$dst, $SIMM", "",
2592 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
2594 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, {?}, 1, (outs DPR:$dst),
2595 (ins h32imm:$SIMM), IIC_VMOVImm,
2596 "vmov", "i32", "$dst, $SIMM", "",
2597 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
2598 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, {?}, 1, (outs QPR:$dst),
2599 (ins h32imm:$SIMM), IIC_VMOVImm,
2600 "vmov", "i32", "$dst, $SIMM", "",
2601 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
2603 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
2604 (ins h64imm:$SIMM), IIC_VMOVImm,
2605 "vmov", "i64", "$dst, $SIMM", "",
2606 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
2607 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
2608 (ins h64imm:$SIMM), IIC_VMOVImm,
2609 "vmov", "i64", "$dst, $SIMM", "",
2610 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
2612 // VMOV : Vector Get Lane (move scalar to ARM core register)
2614 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
2615 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2616 IIC_VMOVSI, "vmov", "s8", "$dst, $src[$lane]",
2617 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
2619 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
2620 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2621 IIC_VMOVSI, "vmov", "s16", "$dst, $src[$lane]",
2622 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
2624 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
2625 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2626 IIC_VMOVSI, "vmov", "u8", "$dst, $src[$lane]",
2627 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
2629 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
2630 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2631 IIC_VMOVSI, "vmov", "u16", "$dst, $src[$lane]",
2632 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
2634 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
2635 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2636 IIC_VMOVSI, "vmov", "32", "$dst, $src[$lane]",
2637 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
2639 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
2640 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
2641 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2642 (DSubReg_i8_reg imm:$lane))),
2643 (SubReg_i8_lane imm:$lane))>;
2644 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
2645 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2646 (DSubReg_i16_reg imm:$lane))),
2647 (SubReg_i16_lane imm:$lane))>;
2648 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
2649 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2650 (DSubReg_i8_reg imm:$lane))),
2651 (SubReg_i8_lane imm:$lane))>;
2652 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
2653 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2654 (DSubReg_i16_reg imm:$lane))),
2655 (SubReg_i16_lane imm:$lane))>;
2656 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
2657 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
2658 (DSubReg_i32_reg imm:$lane))),
2659 (SubReg_i32_lane imm:$lane))>;
2660 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
2661 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1), DPR_VFP2)),
2662 (SSubReg_f32_reg imm:$src2))>;
2663 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
2664 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1), QPR_VFP2)),
2665 (SSubReg_f32_reg imm:$src2))>;
2666 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
2667 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2668 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
2669 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2672 // VMOV : Vector Set Lane (move ARM core register to scalar)
2674 let Constraints = "$src1 = $dst" in {
2675 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$dst),
2676 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2677 IIC_VMOVISL, "vmov", "8", "$dst[$lane], $src2",
2678 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
2679 GPR:$src2, imm:$lane))]>;
2680 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$dst),
2681 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2682 IIC_VMOVISL, "vmov", "16", "$dst[$lane], $src2",
2683 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
2684 GPR:$src2, imm:$lane))]>;
2685 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$dst),
2686 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2687 IIC_VMOVISL, "vmov", "32", "$dst[$lane], $src2",
2688 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
2689 GPR:$src2, imm:$lane))]>;
2691 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
2692 (v16i8 (INSERT_SUBREG QPR:$src1,
2693 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
2694 (DSubReg_i8_reg imm:$lane))),
2695 GPR:$src2, (SubReg_i8_lane imm:$lane)),
2696 (DSubReg_i8_reg imm:$lane)))>;
2697 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
2698 (v8i16 (INSERT_SUBREG QPR:$src1,
2699 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
2700 (DSubReg_i16_reg imm:$lane))),
2701 GPR:$src2, (SubReg_i16_lane imm:$lane)),
2702 (DSubReg_i16_reg imm:$lane)))>;
2703 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
2704 (v4i32 (INSERT_SUBREG QPR:$src1,
2705 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
2706 (DSubReg_i32_reg imm:$lane))),
2707 GPR:$src2, (SubReg_i32_lane imm:$lane)),
2708 (DSubReg_i32_reg imm:$lane)))>;
2710 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
2711 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
2712 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
2713 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
2714 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
2715 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
2717 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
2718 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
2719 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
2720 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
2722 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
2723 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
2724 def : Pat<(v2f64 (scalar_to_vector DPR:$src)),
2725 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, arm_dsubreg_0)>;
2726 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
2727 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
2729 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
2730 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2731 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
2732 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2733 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
2734 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2736 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
2737 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
2738 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2740 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
2741 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
2742 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2744 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
2745 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
2746 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2749 // VDUP : Vector Duplicate (from ARM core register to all elements)
2751 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
2752 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
2753 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
2754 [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
2755 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
2756 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
2757 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
2758 [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
2760 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
2761 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
2762 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
2763 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
2764 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
2765 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
2767 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
2768 IIC_VMOVIS, "vdup", "32", "$dst, $src",
2769 [(set DPR:$dst, (v2f32 (NEONvdup
2770 (f32 (bitconvert GPR:$src)))))]>;
2771 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
2772 IIC_VMOVIS, "vdup", "32", "$dst, $src",
2773 [(set QPR:$dst, (v4f32 (NEONvdup
2774 (f32 (bitconvert GPR:$src)))))]>;
2776 // VDUP : Vector Duplicate Lane (from scalar to all elements)
2778 class VDUPLND<bits<2> op19_18, bits<2> op17_16,
2779 string OpcodeStr, string Dt, ValueType Ty>
2780 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
2781 (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
2782 OpcodeStr, Dt, "$dst, $src[$lane]", "",
2783 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
2785 class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, string Dt,
2786 ValueType ResTy, ValueType OpTy>
2787 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
2788 (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
2789 OpcodeStr, Dt, "$dst, $src[$lane]", "",
2790 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src), imm:$lane)))]>;
2792 // Inst{19-16} is partially specified depending on the element size.
2794 def VDUPLN8d : VDUPLND<{?,?}, {?,1}, "vdup", "8", v8i8>;
2795 def VDUPLN16d : VDUPLND<{?,?}, {1,0}, "vdup", "16", v4i16>;
2796 def VDUPLN32d : VDUPLND<{?,1}, {0,0}, "vdup", "32", v2i32>;
2797 def VDUPLNfd : VDUPLND<{?,1}, {0,0}, "vdup", "32", v2f32>;
2798 def VDUPLN8q : VDUPLNQ<{?,?}, {?,1}, "vdup", "8", v16i8, v8i8>;
2799 def VDUPLN16q : VDUPLNQ<{?,?}, {1,0}, "vdup", "16", v8i16, v4i16>;
2800 def VDUPLN32q : VDUPLNQ<{?,1}, {0,0}, "vdup", "32", v4i32, v2i32>;
2801 def VDUPLNfq : VDUPLNQ<{?,1}, {0,0}, "vdup", "32", v4f32, v2f32>;
2803 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
2804 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
2805 (DSubReg_i8_reg imm:$lane))),
2806 (SubReg_i8_lane imm:$lane)))>;
2807 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
2808 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
2809 (DSubReg_i16_reg imm:$lane))),
2810 (SubReg_i16_lane imm:$lane)))>;
2811 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
2812 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
2813 (DSubReg_i32_reg imm:$lane))),
2814 (SubReg_i32_lane imm:$lane)))>;
2815 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
2816 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
2817 (DSubReg_i32_reg imm:$lane))),
2818 (SubReg_i32_lane imm:$lane)))>;
2820 def VDUPfdf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 0, 0,
2821 (outs DPR:$dst), (ins SPR:$src),
2822 IIC_VMOVD, "vdup", "32", "$dst, ${src:lane}", "",
2823 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
2825 def VDUPfqf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 1, 0,
2826 (outs QPR:$dst), (ins SPR:$src),
2827 IIC_VMOVD, "vdup", "32", "$dst, ${src:lane}", "",
2828 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
2830 def : Pat<(v2i64 (NEONvduplane (v2i64 QPR:$src), imm:$lane)),
2831 (INSERT_SUBREG QPR:$src,
2832 (i64 (EXTRACT_SUBREG QPR:$src, (DSubReg_f64_reg imm:$lane))),
2833 (DSubReg_f64_other_reg imm:$lane))>;
2834 def : Pat<(v2f64 (NEONvduplane (v2f64 QPR:$src), imm:$lane)),
2835 (INSERT_SUBREG QPR:$src,
2836 (f64 (EXTRACT_SUBREG QPR:$src, (DSubReg_f64_reg imm:$lane))),
2837 (DSubReg_f64_other_reg imm:$lane))>;
2839 // VMOVN : Vector Narrowing Move
2840 defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVD,
2841 "vmovn", "i", int_arm_neon_vmovn>;
2842 // VQMOVN : Vector Saturating Narrowing Move
2843 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
2844 "vqmovn", "s", int_arm_neon_vqmovns>;
2845 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
2846 "vqmovn", "u", int_arm_neon_vqmovnu>;
2847 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
2848 "vqmovun", "s", int_arm_neon_vqmovnsu>;
2849 // VMOVL : Vector Lengthening Move
2850 defm VMOVLs : N2VLInt_QHS<0b01,0b10100,0,1, "vmovl", "s",
2851 int_arm_neon_vmovls>;
2852 defm VMOVLu : N2VLInt_QHS<0b11,0b10100,0,1, "vmovl", "u",
2853 int_arm_neon_vmovlu>;
2855 // Vector Conversions.
2857 // VCVT : Vector Convert Between Floating-Point and Integers
2858 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
2859 v2i32, v2f32, fp_to_sint>;
2860 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
2861 v2i32, v2f32, fp_to_uint>;
2862 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
2863 v2f32, v2i32, sint_to_fp>;
2864 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
2865 v2f32, v2i32, uint_to_fp>;
2867 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
2868 v4i32, v4f32, fp_to_sint>;
2869 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
2870 v4i32, v4f32, fp_to_uint>;
2871 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
2872 v4f32, v4i32, sint_to_fp>;
2873 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
2874 v4f32, v4i32, uint_to_fp>;
2876 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
2877 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
2878 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
2879 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
2880 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
2881 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
2882 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
2883 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
2884 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
2886 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
2887 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
2888 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
2889 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
2890 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
2891 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
2892 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
2893 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
2897 // VREV64 : Vector Reverse elements within 64-bit doublewords
2899 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
2900 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
2901 (ins DPR:$src), IIC_VMOVD,
2902 OpcodeStr, Dt, "$dst, $src", "",
2903 [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
2904 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
2905 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
2906 (ins QPR:$src), IIC_VMOVD,
2907 OpcodeStr, Dt, "$dst, $src", "",
2908 [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
2910 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
2911 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
2912 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
2913 def VREV64df : VREV64D<0b10, "vrev64", "32", v2f32>;
2915 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
2916 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
2917 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
2918 def VREV64qf : VREV64Q<0b10, "vrev64", "32", v4f32>;
2920 // VREV32 : Vector Reverse elements within 32-bit words
2922 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
2923 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
2924 (ins DPR:$src), IIC_VMOVD,
2925 OpcodeStr, Dt, "$dst, $src", "",
2926 [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
2927 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
2928 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
2929 (ins QPR:$src), IIC_VMOVD,
2930 OpcodeStr, Dt, "$dst, $src", "",
2931 [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
2933 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
2934 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
2936 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
2937 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
2939 // VREV16 : Vector Reverse elements within 16-bit halfwords
2941 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
2942 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
2943 (ins DPR:$src), IIC_VMOVD,
2944 OpcodeStr, Dt, "$dst, $src", "",
2945 [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
2946 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
2947 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
2948 (ins QPR:$src), IIC_VMOVD,
2949 OpcodeStr, Dt, "$dst, $src", "",
2950 [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
2952 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
2953 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
2955 // Other Vector Shuffles.
2957 // VEXT : Vector Extract
2959 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
2960 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$dst),
2961 (ins DPR:$lhs, DPR:$rhs, i32imm:$index), IIC_VEXTD,
2962 OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
2963 [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
2964 (Ty DPR:$rhs), imm:$index)))]>;
2966 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
2967 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$dst),
2968 (ins QPR:$lhs, QPR:$rhs, i32imm:$index), IIC_VEXTQ,
2969 OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
2970 [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
2971 (Ty QPR:$rhs), imm:$index)))]>;
2973 def VEXTd8 : VEXTd<"vext", "8", v8i8>;
2974 def VEXTd16 : VEXTd<"vext", "16", v4i16>;
2975 def VEXTd32 : VEXTd<"vext", "32", v2i32>;
2976 def VEXTdf : VEXTd<"vext", "32", v2f32>;
2978 def VEXTq8 : VEXTq<"vext", "8", v16i8>;
2979 def VEXTq16 : VEXTq<"vext", "16", v8i16>;
2980 def VEXTq32 : VEXTq<"vext", "32", v4i32>;
2981 def VEXTqf : VEXTq<"vext", "32", v4f32>;
2983 // VTRN : Vector Transpose
2985 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
2986 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
2987 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
2989 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
2990 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
2991 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
2993 // VUZP : Vector Unzip (Deinterleave)
2995 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
2996 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
2997 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
2999 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
3000 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
3001 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
3003 // VZIP : Vector Zip (Interleave)
3005 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
3006 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
3007 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
3009 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
3010 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
3011 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
3013 // Vector Table Lookup and Table Extension.
3015 // VTBL : Vector Table Lookup
3017 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
3018 (ins DPR:$tbl1, DPR:$src), IIC_VTB1,
3019 "vtbl", "8", "$dst, \\{$tbl1\\}, $src", "",
3020 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
3021 let hasExtraSrcRegAllocReq = 1 in {
3023 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
3024 (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTB2,
3025 "vtbl", "8", "$dst, \\{$tbl1,$tbl2\\}, $src", "",
3026 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl2
3027 DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
3029 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
3030 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTB3,
3031 "vtbl", "8", "$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "",
3032 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl3
3033 DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
3035 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
3036 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTB4,
3037 "vtbl", "8", "$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "",
3038 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl4 DPR:$tbl1, DPR:$tbl2,
3039 DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
3040 } // hasExtraSrcRegAllocReq = 1
3042 // VTBX : Vector Table Extension
3044 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
3045 (ins DPR:$orig, DPR:$tbl1, DPR:$src), IIC_VTBX1,
3046 "vtbx", "8", "$dst, \\{$tbl1\\}, $src", "$orig = $dst",
3047 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
3048 DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
3049 let hasExtraSrcRegAllocReq = 1 in {
3051 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
3052 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTBX2,
3053 "vtbx", "8", "$dst, \\{$tbl1,$tbl2\\}, $src", "$orig = $dst",
3054 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx2
3055 DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
3057 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
3058 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTBX3,
3059 "vtbx", "8", "$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "$orig = $dst",
3060 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx3 DPR:$orig, DPR:$tbl1,
3061 DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
3063 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
3064 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTBX4,
3065 "vtbx", "8", "$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "$orig = $dst",
3066 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx4 DPR:$orig, DPR:$tbl1,
3067 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
3068 } // hasExtraSrcRegAllocReq = 1
3070 //===----------------------------------------------------------------------===//
3071 // NEON instructions for single-precision FP math
3072 //===----------------------------------------------------------------------===//
3074 // These need separate instructions because they must use DPR_VFP2 register
3075 // class which have SPR sub-registers.
3077 // Vector Add Operations used for single-precision FP
3078 let neverHasSideEffects = 1 in
3079 def VADDfd_sfp : N3VDs<0, 0, 0b00, 0b1101, 0, "vadd", "f32", v2f32, v2f32, fadd,1>;
3080 def : N3VDsPat<fadd, VADDfd_sfp>;
3082 // Vector Sub Operations used for single-precision FP
3083 let neverHasSideEffects = 1 in
3084 def VSUBfd_sfp : N3VDs<0, 0, 0b10, 0b1101, 0, "vsub", "f32", v2f32, v2f32, fsub,0>;
3085 def : N3VDsPat<fsub, VSUBfd_sfp>;
3087 // Vector Multiply Operations used for single-precision FP
3088 let neverHasSideEffects = 1 in
3089 def VMULfd_sfp : N3VDs<1, 0, 0b00, 0b1101, 1, "vmul", "f32", v2f32, v2f32, fmul,1>;
3090 def : N3VDsPat<fmul, VMULfd_sfp>;
3092 // Vector Multiply-Accumulate/Subtract used for single-precision FP
3093 // vml[as].f32 can cause 4-8 cycle stalls in following ASIMD instructions, so
3094 // we want to avoid them for now. e.g., alternating vmla/vadd instructions.
3096 //let neverHasSideEffects = 1 in
3097 //def VMLAfd_sfp : N3VDMulOps<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32", v2f32,fmul,fadd>;
3098 //def : N3VDMulOpsPat<fmul, fadd, VMLAfd_sfp>;
3100 //let neverHasSideEffects = 1 in
3101 //def VMLSfd_sfp : N3VDMulOps<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32", v2f32,fmul,fsub>;
3102 //def : N3VDMulOpsPat<fmul, fsub, VMLSfd_sfp>;
3104 // Vector Absolute used for single-precision FP
3105 let neverHasSideEffects = 1 in
3106 def VABSfd_sfp : N2VDInts<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
3107 IIC_VUNAD, "vabs", "f32",
3108 v2f32, v2f32, int_arm_neon_vabs>;
3109 def : N2VDIntsPat<fabs, VABSfd_sfp>;
3111 // Vector Negate used for single-precision FP
3112 let neverHasSideEffects = 1 in
3113 def VNEGf32d_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
3114 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
3115 "vneg", "f32", "$dst, $src", "", []>;
3116 def : N2VDIntsPat<fneg, VNEGf32d_sfp>;
3118 // Vector Convert between single-precision FP and integer
3119 let neverHasSideEffects = 1 in
3120 def VCVTf2sd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3121 v2i32, v2f32, fp_to_sint>;
3122 def : N2VDsPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
3124 let neverHasSideEffects = 1 in
3125 def VCVTf2ud_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3126 v2i32, v2f32, fp_to_uint>;
3127 def : N2VDsPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
3129 let neverHasSideEffects = 1 in
3130 def VCVTs2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3131 v2f32, v2i32, sint_to_fp>;
3132 def : N2VDsPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
3134 let neverHasSideEffects = 1 in
3135 def VCVTu2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3136 v2f32, v2i32, uint_to_fp>;
3137 def : N2VDsPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
3139 //===----------------------------------------------------------------------===//
3140 // Non-Instruction Patterns
3141 //===----------------------------------------------------------------------===//
3144 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
3145 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
3146 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
3147 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
3148 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
3149 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
3150 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
3151 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
3152 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
3153 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
3154 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
3155 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
3156 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
3157 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
3158 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
3159 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
3160 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
3161 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
3162 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
3163 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
3164 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
3165 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
3166 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
3167 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
3168 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
3169 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
3170 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
3171 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
3172 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
3173 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
3175 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
3176 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
3177 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
3178 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
3179 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
3180 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
3181 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
3182 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
3183 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
3184 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
3185 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
3186 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
3187 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
3188 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
3189 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
3190 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
3191 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
3192 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
3193 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
3194 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
3195 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
3196 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
3197 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
3198 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
3199 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
3200 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
3201 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
3202 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
3203 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
3204 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;