1 //===-- ARMInstrNEON.td - NEON support for ARM -------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // NEON-specific Operands.
17 //===----------------------------------------------------------------------===//
18 def nModImm : Operand<i32> {
19 let PrintMethod = "printNEONModImmOperand";
22 def nImmSplatI8AsmOperand : AsmOperandClass { let Name = "NEONi8splat"; }
23 def nImmSplatI8 : Operand<i32> {
24 let PrintMethod = "printNEONModImmOperand";
25 let ParserMatchClass = nImmSplatI8AsmOperand;
27 def nImmSplatI16AsmOperand : AsmOperandClass { let Name = "NEONi16splat"; }
28 def nImmSplatI16 : Operand<i32> {
29 let PrintMethod = "printNEONModImmOperand";
30 let ParserMatchClass = nImmSplatI16AsmOperand;
32 def nImmSplatI32AsmOperand : AsmOperandClass { let Name = "NEONi32splat"; }
33 def nImmSplatI32 : Operand<i32> {
34 let PrintMethod = "printNEONModImmOperand";
35 let ParserMatchClass = nImmSplatI32AsmOperand;
37 def nImmVMOVI32AsmOperand : AsmOperandClass { let Name = "NEONi32vmov"; }
38 def nImmVMOVI32 : Operand<i32> {
39 let PrintMethod = "printNEONModImmOperand";
40 let ParserMatchClass = nImmVMOVI32AsmOperand;
42 def nImmVMOVI32NegAsmOperand : AsmOperandClass { let Name = "NEONi32vmovNeg"; }
43 def nImmVMOVI32Neg : Operand<i32> {
44 let PrintMethod = "printNEONModImmOperand";
45 let ParserMatchClass = nImmVMOVI32NegAsmOperand;
47 def nImmVMOVF32 : Operand<i32> {
48 let PrintMethod = "printFPImmOperand";
49 let ParserMatchClass = FPImmOperand;
51 def nImmSplatI64AsmOperand : AsmOperandClass { let Name = "NEONi64splat"; }
52 def nImmSplatI64 : Operand<i32> {
53 let PrintMethod = "printNEONModImmOperand";
54 let ParserMatchClass = nImmSplatI64AsmOperand;
57 def VectorIndex8Operand : AsmOperandClass { let Name = "VectorIndex8"; }
58 def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; }
59 def VectorIndex32Operand : AsmOperandClass { let Name = "VectorIndex32"; }
60 def VectorIndex8 : Operand<i32>, ImmLeaf<i32, [{
61 return ((uint64_t)Imm) < 8;
63 let ParserMatchClass = VectorIndex8Operand;
64 let PrintMethod = "printVectorIndex";
65 let MIOperandInfo = (ops i32imm);
67 def VectorIndex16 : Operand<i32>, ImmLeaf<i32, [{
68 return ((uint64_t)Imm) < 4;
70 let ParserMatchClass = VectorIndex16Operand;
71 let PrintMethod = "printVectorIndex";
72 let MIOperandInfo = (ops i32imm);
74 def VectorIndex32 : Operand<i32>, ImmLeaf<i32, [{
75 return ((uint64_t)Imm) < 2;
77 let ParserMatchClass = VectorIndex32Operand;
78 let PrintMethod = "printVectorIndex";
79 let MIOperandInfo = (ops i32imm);
82 // Register list of one D register.
83 def VecListOneDAsmOperand : AsmOperandClass {
84 let Name = "VecListOneD";
85 let ParserMethod = "parseVectorList";
86 let RenderMethod = "addVecListOperands";
88 def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> {
89 let ParserMatchClass = VecListOneDAsmOperand;
91 // Register list of two sequential D registers.
92 def VecListDPairAsmOperand : AsmOperandClass {
93 let Name = "VecListDPair";
94 let ParserMethod = "parseVectorList";
95 let RenderMethod = "addVecListOperands";
97 def VecListDPair : RegisterOperand<DPair, "printVectorListTwo"> {
98 let ParserMatchClass = VecListDPairAsmOperand;
100 // Register list of three sequential D registers.
101 def VecListThreeDAsmOperand : AsmOperandClass {
102 let Name = "VecListThreeD";
103 let ParserMethod = "parseVectorList";
104 let RenderMethod = "addVecListOperands";
106 def VecListThreeD : RegisterOperand<DPR, "printVectorListThree"> {
107 let ParserMatchClass = VecListThreeDAsmOperand;
109 // Register list of four sequential D registers.
110 def VecListFourDAsmOperand : AsmOperandClass {
111 let Name = "VecListFourD";
112 let ParserMethod = "parseVectorList";
113 let RenderMethod = "addVecListOperands";
115 def VecListFourD : RegisterOperand<DPR, "printVectorListFour"> {
116 let ParserMatchClass = VecListFourDAsmOperand;
118 // Register list of two D registers spaced by 2 (two sequential Q registers).
119 def VecListDPairSpacedAsmOperand : AsmOperandClass {
120 let Name = "VecListDPairSpaced";
121 let ParserMethod = "parseVectorList";
122 let RenderMethod = "addVecListOperands";
124 def VecListDPairSpaced : RegisterOperand<DPair, "printVectorListTwoSpaced"> {
125 let ParserMatchClass = VecListDPairSpacedAsmOperand;
127 // Register list of three D registers spaced by 2 (three Q registers).
128 def VecListThreeQAsmOperand : AsmOperandClass {
129 let Name = "VecListThreeQ";
130 let ParserMethod = "parseVectorList";
131 let RenderMethod = "addVecListOperands";
133 def VecListThreeQ : RegisterOperand<DPR, "printVectorListThreeSpaced"> {
134 let ParserMatchClass = VecListThreeQAsmOperand;
136 // Register list of three D registers spaced by 2 (three Q registers).
137 def VecListFourQAsmOperand : AsmOperandClass {
138 let Name = "VecListFourQ";
139 let ParserMethod = "parseVectorList";
140 let RenderMethod = "addVecListOperands";
142 def VecListFourQ : RegisterOperand<DPR, "printVectorListFourSpaced"> {
143 let ParserMatchClass = VecListFourQAsmOperand;
146 // Register list of one D register, with "all lanes" subscripting.
147 def VecListOneDAllLanesAsmOperand : AsmOperandClass {
148 let Name = "VecListOneDAllLanes";
149 let ParserMethod = "parseVectorList";
150 let RenderMethod = "addVecListOperands";
152 def VecListOneDAllLanes : RegisterOperand<DPR, "printVectorListOneAllLanes"> {
153 let ParserMatchClass = VecListOneDAllLanesAsmOperand;
155 // Register list of two D registers, with "all lanes" subscripting.
156 def VecListDPairAllLanesAsmOperand : AsmOperandClass {
157 let Name = "VecListDPairAllLanes";
158 let ParserMethod = "parseVectorList";
159 let RenderMethod = "addVecListOperands";
161 def VecListDPairAllLanes : RegisterOperand<DPair,
162 "printVectorListTwoAllLanes"> {
163 let ParserMatchClass = VecListDPairAllLanesAsmOperand;
165 // Register list of two D registers spaced by 2 (two sequential Q registers).
166 def VecListDPairSpacedAllLanesAsmOperand : AsmOperandClass {
167 let Name = "VecListDPairSpacedAllLanes";
168 let ParserMethod = "parseVectorList";
169 let RenderMethod = "addVecListOperands";
171 def VecListDPairSpacedAllLanes : RegisterOperand<DPair,
172 "printVectorListTwoSpacedAllLanes"> {
173 let ParserMatchClass = VecListDPairSpacedAllLanesAsmOperand;
175 // Register list of three D registers, with "all lanes" subscripting.
176 def VecListThreeDAllLanesAsmOperand : AsmOperandClass {
177 let Name = "VecListThreeDAllLanes";
178 let ParserMethod = "parseVectorList";
179 let RenderMethod = "addVecListOperands";
181 def VecListThreeDAllLanes : RegisterOperand<DPR,
182 "printVectorListThreeAllLanes"> {
183 let ParserMatchClass = VecListThreeDAllLanesAsmOperand;
185 // Register list of three D registers spaced by 2 (three sequential Q regs).
186 def VecListThreeQAllLanesAsmOperand : AsmOperandClass {
187 let Name = "VecListThreeQAllLanes";
188 let ParserMethod = "parseVectorList";
189 let RenderMethod = "addVecListOperands";
191 def VecListThreeQAllLanes : RegisterOperand<DPR,
192 "printVectorListThreeSpacedAllLanes"> {
193 let ParserMatchClass = VecListThreeQAllLanesAsmOperand;
195 // Register list of four D registers, with "all lanes" subscripting.
196 def VecListFourDAllLanesAsmOperand : AsmOperandClass {
197 let Name = "VecListFourDAllLanes";
198 let ParserMethod = "parseVectorList";
199 let RenderMethod = "addVecListOperands";
201 def VecListFourDAllLanes : RegisterOperand<DPR, "printVectorListFourAllLanes"> {
202 let ParserMatchClass = VecListFourDAllLanesAsmOperand;
204 // Register list of four D registers spaced by 2 (four sequential Q regs).
205 def VecListFourQAllLanesAsmOperand : AsmOperandClass {
206 let Name = "VecListFourQAllLanes";
207 let ParserMethod = "parseVectorList";
208 let RenderMethod = "addVecListOperands";
210 def VecListFourQAllLanes : RegisterOperand<DPR,
211 "printVectorListFourSpacedAllLanes"> {
212 let ParserMatchClass = VecListFourQAllLanesAsmOperand;
216 // Register list of one D register, with byte lane subscripting.
217 def VecListOneDByteIndexAsmOperand : AsmOperandClass {
218 let Name = "VecListOneDByteIndexed";
219 let ParserMethod = "parseVectorList";
220 let RenderMethod = "addVecListIndexedOperands";
222 def VecListOneDByteIndexed : Operand<i32> {
223 let ParserMatchClass = VecListOneDByteIndexAsmOperand;
224 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
226 // ...with half-word lane subscripting.
227 def VecListOneDHWordIndexAsmOperand : AsmOperandClass {
228 let Name = "VecListOneDHWordIndexed";
229 let ParserMethod = "parseVectorList";
230 let RenderMethod = "addVecListIndexedOperands";
232 def VecListOneDHWordIndexed : Operand<i32> {
233 let ParserMatchClass = VecListOneDHWordIndexAsmOperand;
234 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
236 // ...with word lane subscripting.
237 def VecListOneDWordIndexAsmOperand : AsmOperandClass {
238 let Name = "VecListOneDWordIndexed";
239 let ParserMethod = "parseVectorList";
240 let RenderMethod = "addVecListIndexedOperands";
242 def VecListOneDWordIndexed : Operand<i32> {
243 let ParserMatchClass = VecListOneDWordIndexAsmOperand;
244 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
247 // Register list of two D registers with byte lane subscripting.
248 def VecListTwoDByteIndexAsmOperand : AsmOperandClass {
249 let Name = "VecListTwoDByteIndexed";
250 let ParserMethod = "parseVectorList";
251 let RenderMethod = "addVecListIndexedOperands";
253 def VecListTwoDByteIndexed : Operand<i32> {
254 let ParserMatchClass = VecListTwoDByteIndexAsmOperand;
255 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
257 // ...with half-word lane subscripting.
258 def VecListTwoDHWordIndexAsmOperand : AsmOperandClass {
259 let Name = "VecListTwoDHWordIndexed";
260 let ParserMethod = "parseVectorList";
261 let RenderMethod = "addVecListIndexedOperands";
263 def VecListTwoDHWordIndexed : Operand<i32> {
264 let ParserMatchClass = VecListTwoDHWordIndexAsmOperand;
265 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
267 // ...with word lane subscripting.
268 def VecListTwoDWordIndexAsmOperand : AsmOperandClass {
269 let Name = "VecListTwoDWordIndexed";
270 let ParserMethod = "parseVectorList";
271 let RenderMethod = "addVecListIndexedOperands";
273 def VecListTwoDWordIndexed : Operand<i32> {
274 let ParserMatchClass = VecListTwoDWordIndexAsmOperand;
275 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
277 // Register list of two Q registers with half-word lane subscripting.
278 def VecListTwoQHWordIndexAsmOperand : AsmOperandClass {
279 let Name = "VecListTwoQHWordIndexed";
280 let ParserMethod = "parseVectorList";
281 let RenderMethod = "addVecListIndexedOperands";
283 def VecListTwoQHWordIndexed : Operand<i32> {
284 let ParserMatchClass = VecListTwoQHWordIndexAsmOperand;
285 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
287 // ...with word lane subscripting.
288 def VecListTwoQWordIndexAsmOperand : AsmOperandClass {
289 let Name = "VecListTwoQWordIndexed";
290 let ParserMethod = "parseVectorList";
291 let RenderMethod = "addVecListIndexedOperands";
293 def VecListTwoQWordIndexed : Operand<i32> {
294 let ParserMatchClass = VecListTwoQWordIndexAsmOperand;
295 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
299 // Register list of three D registers with byte lane subscripting.
300 def VecListThreeDByteIndexAsmOperand : AsmOperandClass {
301 let Name = "VecListThreeDByteIndexed";
302 let ParserMethod = "parseVectorList";
303 let RenderMethod = "addVecListIndexedOperands";
305 def VecListThreeDByteIndexed : Operand<i32> {
306 let ParserMatchClass = VecListThreeDByteIndexAsmOperand;
307 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
309 // ...with half-word lane subscripting.
310 def VecListThreeDHWordIndexAsmOperand : AsmOperandClass {
311 let Name = "VecListThreeDHWordIndexed";
312 let ParserMethod = "parseVectorList";
313 let RenderMethod = "addVecListIndexedOperands";
315 def VecListThreeDHWordIndexed : Operand<i32> {
316 let ParserMatchClass = VecListThreeDHWordIndexAsmOperand;
317 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
319 // ...with word lane subscripting.
320 def VecListThreeDWordIndexAsmOperand : AsmOperandClass {
321 let Name = "VecListThreeDWordIndexed";
322 let ParserMethod = "parseVectorList";
323 let RenderMethod = "addVecListIndexedOperands";
325 def VecListThreeDWordIndexed : Operand<i32> {
326 let ParserMatchClass = VecListThreeDWordIndexAsmOperand;
327 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
329 // Register list of three Q registers with half-word lane subscripting.
330 def VecListThreeQHWordIndexAsmOperand : AsmOperandClass {
331 let Name = "VecListThreeQHWordIndexed";
332 let ParserMethod = "parseVectorList";
333 let RenderMethod = "addVecListIndexedOperands";
335 def VecListThreeQHWordIndexed : Operand<i32> {
336 let ParserMatchClass = VecListThreeQHWordIndexAsmOperand;
337 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
339 // ...with word lane subscripting.
340 def VecListThreeQWordIndexAsmOperand : AsmOperandClass {
341 let Name = "VecListThreeQWordIndexed";
342 let ParserMethod = "parseVectorList";
343 let RenderMethod = "addVecListIndexedOperands";
345 def VecListThreeQWordIndexed : Operand<i32> {
346 let ParserMatchClass = VecListThreeQWordIndexAsmOperand;
347 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
350 // Register list of four D registers with byte lane subscripting.
351 def VecListFourDByteIndexAsmOperand : AsmOperandClass {
352 let Name = "VecListFourDByteIndexed";
353 let ParserMethod = "parseVectorList";
354 let RenderMethod = "addVecListIndexedOperands";
356 def VecListFourDByteIndexed : Operand<i32> {
357 let ParserMatchClass = VecListFourDByteIndexAsmOperand;
358 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
360 // ...with half-word lane subscripting.
361 def VecListFourDHWordIndexAsmOperand : AsmOperandClass {
362 let Name = "VecListFourDHWordIndexed";
363 let ParserMethod = "parseVectorList";
364 let RenderMethod = "addVecListIndexedOperands";
366 def VecListFourDHWordIndexed : Operand<i32> {
367 let ParserMatchClass = VecListFourDHWordIndexAsmOperand;
368 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
370 // ...with word lane subscripting.
371 def VecListFourDWordIndexAsmOperand : AsmOperandClass {
372 let Name = "VecListFourDWordIndexed";
373 let ParserMethod = "parseVectorList";
374 let RenderMethod = "addVecListIndexedOperands";
376 def VecListFourDWordIndexed : Operand<i32> {
377 let ParserMatchClass = VecListFourDWordIndexAsmOperand;
378 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
380 // Register list of four Q registers with half-word lane subscripting.
381 def VecListFourQHWordIndexAsmOperand : AsmOperandClass {
382 let Name = "VecListFourQHWordIndexed";
383 let ParserMethod = "parseVectorList";
384 let RenderMethod = "addVecListIndexedOperands";
386 def VecListFourQHWordIndexed : Operand<i32> {
387 let ParserMatchClass = VecListFourQHWordIndexAsmOperand;
388 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
390 // ...with word lane subscripting.
391 def VecListFourQWordIndexAsmOperand : AsmOperandClass {
392 let Name = "VecListFourQWordIndexed";
393 let ParserMethod = "parseVectorList";
394 let RenderMethod = "addVecListIndexedOperands";
396 def VecListFourQWordIndexed : Operand<i32> {
397 let ParserMatchClass = VecListFourQWordIndexAsmOperand;
398 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
402 //===----------------------------------------------------------------------===//
403 // NEON-specific DAG Nodes.
404 //===----------------------------------------------------------------------===//
406 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
407 def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
409 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
410 def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
411 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
412 def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
413 def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
414 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
415 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
416 def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
417 def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
418 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
419 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
421 // Types for vector shift by immediates. The "SHX" version is for long and
422 // narrow operations where the source and destination vectors have different
423 // types. The "SHINS" version is for shift and insert operations.
424 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
426 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
428 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
429 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
431 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
432 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
433 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
434 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
435 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
436 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
437 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
439 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
440 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
441 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
443 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
444 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
445 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
446 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
447 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
448 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
450 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
451 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
452 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
454 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
455 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
457 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
459 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
460 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
462 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
463 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
464 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
465 def NEONvmovFPImm : SDNode<"ARMISD::VMOVFPIMM", SDTARMVMOVIMM>;
467 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
469 def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
470 def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
472 def NEONvbsl : SDNode<"ARMISD::VBSL",
473 SDTypeProfile<1, 3, [SDTCisVec<0>,
476 SDTCisSameAs<0, 3>]>>;
478 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
480 // VDUPLANE can produce a quad-register result from a double-register source,
481 // so the result is not constrained to match the source.
482 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
483 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
486 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
487 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
488 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
490 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
491 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
492 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
493 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
495 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
497 SDTCisSameAs<0, 3>]>;
498 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
499 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
500 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
502 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
503 SDTCisSameAs<1, 2>]>;
504 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
505 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
507 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
508 SDTCisSameAs<0, 2>]>;
509 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
510 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
512 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
513 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
514 unsigned EltBits = 0;
515 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
516 return (EltBits == 32 && EltVal == 0);
519 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
520 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
521 unsigned EltBits = 0;
522 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
523 return (EltBits == 8 && EltVal == 0xff);
526 //===----------------------------------------------------------------------===//
527 // NEON load / store instructions
528 //===----------------------------------------------------------------------===//
530 // Use VLDM to load a Q register as a D register pair.
531 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
533 : PseudoVFPLdStM<(outs DPair:$dst), (ins GPR:$Rn),
535 [(set DPair:$dst, (v2f64 (load GPR:$Rn)))]>;
537 // Use VSTM to store a Q register as a D register pair.
538 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
540 : PseudoVFPLdStM<(outs), (ins DPair:$src, GPR:$Rn),
542 [(store (v2f64 DPair:$src), GPR:$Rn)]>;
544 // Classes for VLD* pseudo-instructions with multi-register operands.
545 // These are expanded to real instructions after register allocation.
546 class VLDQPseudo<InstrItinClass itin>
547 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
548 class VLDQWBPseudo<InstrItinClass itin>
549 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
550 (ins addrmode6:$addr, am6offset:$offset), itin,
552 class VLDQWBfixedPseudo<InstrItinClass itin>
553 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
554 (ins addrmode6:$addr), itin,
556 class VLDQWBregisterPseudo<InstrItinClass itin>
557 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
558 (ins addrmode6:$addr, rGPR:$offset), itin,
561 class VLDQQPseudo<InstrItinClass itin>
562 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
563 class VLDQQWBPseudo<InstrItinClass itin>
564 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
565 (ins addrmode6:$addr, am6offset:$offset), itin,
567 class VLDQQWBfixedPseudo<InstrItinClass itin>
568 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
569 (ins addrmode6:$addr), itin,
571 class VLDQQWBregisterPseudo<InstrItinClass itin>
572 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
573 (ins addrmode6:$addr, rGPR:$offset), itin,
577 class VLDQQQQPseudo<InstrItinClass itin>
578 : PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src),itin,
580 class VLDQQQQWBPseudo<InstrItinClass itin>
581 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
582 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
583 "$addr.addr = $wb, $src = $dst">;
585 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
587 // VLD1 : Vector Load (multiple single elements)
588 class VLD1D<bits<4> op7_4, string Dt>
589 : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd),
590 (ins addrmode6:$Rn), IIC_VLD1,
591 "vld1", Dt, "$Vd, $Rn", "", []> {
594 let DecoderMethod = "DecodeVLDInstruction";
596 class VLD1Q<bits<4> op7_4, string Dt>
597 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd),
598 (ins addrmode6:$Rn), IIC_VLD1x2,
599 "vld1", Dt, "$Vd, $Rn", "", []> {
601 let Inst{5-4} = Rn{5-4};
602 let DecoderMethod = "DecodeVLDInstruction";
605 def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
606 def VLD1d16 : VLD1D<{0,1,0,?}, "16">;
607 def VLD1d32 : VLD1D<{1,0,0,?}, "32">;
608 def VLD1d64 : VLD1D<{1,1,0,?}, "64">;
610 def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;
611 def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
612 def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
613 def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
615 // ...with address register writeback:
616 multiclass VLD1DWB<bits<4> op7_4, string Dt> {
617 def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
618 (ins addrmode6:$Rn), IIC_VLD1u,
619 "vld1", Dt, "$Vd, $Rn!",
620 "$Rn.addr = $wb", []> {
621 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
623 let DecoderMethod = "DecodeVLDInstruction";
624 let AsmMatchConverter = "cvtVLDwbFixed";
626 def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
627 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1u,
628 "vld1", Dt, "$Vd, $Rn, $Rm",
629 "$Rn.addr = $wb", []> {
631 let DecoderMethod = "DecodeVLDInstruction";
632 let AsmMatchConverter = "cvtVLDwbRegister";
635 multiclass VLD1QWB<bits<4> op7_4, string Dt> {
636 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
637 (ins addrmode6:$Rn), IIC_VLD1x2u,
638 "vld1", Dt, "$Vd, $Rn!",
639 "$Rn.addr = $wb", []> {
640 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
641 let Inst{5-4} = Rn{5-4};
642 let DecoderMethod = "DecodeVLDInstruction";
643 let AsmMatchConverter = "cvtVLDwbFixed";
645 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
646 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
647 "vld1", Dt, "$Vd, $Rn, $Rm",
648 "$Rn.addr = $wb", []> {
649 let Inst{5-4} = Rn{5-4};
650 let DecoderMethod = "DecodeVLDInstruction";
651 let AsmMatchConverter = "cvtVLDwbRegister";
655 defm VLD1d8wb : VLD1DWB<{0,0,0,?}, "8">;
656 defm VLD1d16wb : VLD1DWB<{0,1,0,?}, "16">;
657 defm VLD1d32wb : VLD1DWB<{1,0,0,?}, "32">;
658 defm VLD1d64wb : VLD1DWB<{1,1,0,?}, "64">;
659 defm VLD1q8wb : VLD1QWB<{0,0,?,?}, "8">;
660 defm VLD1q16wb : VLD1QWB<{0,1,?,?}, "16">;
661 defm VLD1q32wb : VLD1QWB<{1,0,?,?}, "32">;
662 defm VLD1q64wb : VLD1QWB<{1,1,?,?}, "64">;
664 // ...with 3 registers
665 class VLD1D3<bits<4> op7_4, string Dt>
666 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd),
667 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
668 "$Vd, $Rn", "", []> {
671 let DecoderMethod = "DecodeVLDInstruction";
673 multiclass VLD1D3WB<bits<4> op7_4, string Dt> {
674 def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
675 (ins addrmode6:$Rn), IIC_VLD1x2u,
676 "vld1", Dt, "$Vd, $Rn!",
677 "$Rn.addr = $wb", []> {
678 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
680 let DecoderMethod = "DecodeVLDInstruction";
681 let AsmMatchConverter = "cvtVLDwbFixed";
683 def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
684 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
685 "vld1", Dt, "$Vd, $Rn, $Rm",
686 "$Rn.addr = $wb", []> {
688 let DecoderMethod = "DecodeVLDInstruction";
689 let AsmMatchConverter = "cvtVLDwbRegister";
693 def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
694 def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;
695 def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;
696 def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;
698 defm VLD1d8Twb : VLD1D3WB<{0,0,0,?}, "8">;
699 defm VLD1d16Twb : VLD1D3WB<{0,1,0,?}, "16">;
700 defm VLD1d32Twb : VLD1D3WB<{1,0,0,?}, "32">;
701 defm VLD1d64Twb : VLD1D3WB<{1,1,0,?}, "64">;
703 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
705 // ...with 4 registers
706 class VLD1D4<bits<4> op7_4, string Dt>
707 : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd),
708 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
709 "$Vd, $Rn", "", []> {
711 let Inst{5-4} = Rn{5-4};
712 let DecoderMethod = "DecodeVLDInstruction";
714 multiclass VLD1D4WB<bits<4> op7_4, string Dt> {
715 def _fixed : NLdSt<0,0b10,0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb),
716 (ins addrmode6:$Rn), IIC_VLD1x2u,
717 "vld1", Dt, "$Vd, $Rn!",
718 "$Rn.addr = $wb", []> {
719 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
720 let Inst{5-4} = Rn{5-4};
721 let DecoderMethod = "DecodeVLDInstruction";
722 let AsmMatchConverter = "cvtVLDwbFixed";
724 def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb),
725 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
726 "vld1", Dt, "$Vd, $Rn, $Rm",
727 "$Rn.addr = $wb", []> {
728 let Inst{5-4} = Rn{5-4};
729 let DecoderMethod = "DecodeVLDInstruction";
730 let AsmMatchConverter = "cvtVLDwbRegister";
734 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
735 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;
736 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;
737 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;
739 defm VLD1d8Qwb : VLD1D4WB<{0,0,?,?}, "8">;
740 defm VLD1d16Qwb : VLD1D4WB<{0,1,?,?}, "16">;
741 defm VLD1d32Qwb : VLD1D4WB<{1,0,?,?}, "32">;
742 defm VLD1d64Qwb : VLD1D4WB<{1,1,?,?}, "64">;
744 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
746 // VLD2 : Vector Load (multiple 2-element structures)
747 class VLD2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
749 : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd),
750 (ins addrmode6:$Rn), itin,
751 "vld2", Dt, "$Vd, $Rn", "", []> {
753 let Inst{5-4} = Rn{5-4};
754 let DecoderMethod = "DecodeVLDInstruction";
757 def VLD2d8 : VLD2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2>;
758 def VLD2d16 : VLD2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2>;
759 def VLD2d32 : VLD2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2>;
761 def VLD2q8 : VLD2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2>;
762 def VLD2q16 : VLD2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2>;
763 def VLD2q32 : VLD2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2>;
765 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
766 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
767 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
769 // ...with address register writeback:
770 multiclass VLD2WB<bits<4> op11_8, bits<4> op7_4, string Dt,
771 RegisterOperand VdTy, InstrItinClass itin> {
772 def _fixed : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
773 (ins addrmode6:$Rn), itin,
774 "vld2", Dt, "$Vd, $Rn!",
775 "$Rn.addr = $wb", []> {
776 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
777 let Inst{5-4} = Rn{5-4};
778 let DecoderMethod = "DecodeVLDInstruction";
779 let AsmMatchConverter = "cvtVLDwbFixed";
781 def _register : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
782 (ins addrmode6:$Rn, rGPR:$Rm), itin,
783 "vld2", Dt, "$Vd, $Rn, $Rm",
784 "$Rn.addr = $wb", []> {
785 let Inst{5-4} = Rn{5-4};
786 let DecoderMethod = "DecodeVLDInstruction";
787 let AsmMatchConverter = "cvtVLDwbRegister";
791 defm VLD2d8wb : VLD2WB<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2u>;
792 defm VLD2d16wb : VLD2WB<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2u>;
793 defm VLD2d32wb : VLD2WB<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2u>;
795 defm VLD2q8wb : VLD2WB<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2u>;
796 defm VLD2q16wb : VLD2WB<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2u>;
797 defm VLD2q32wb : VLD2WB<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2u>;
799 def VLD2q8PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
800 def VLD2q16PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
801 def VLD2q32PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
802 def VLD2q8PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
803 def VLD2q16PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
804 def VLD2q32PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
806 // ...with double-spaced registers
807 def VLD2b8 : VLD2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2>;
808 def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2>;
809 def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2>;
810 defm VLD2b8wb : VLD2WB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2u>;
811 defm VLD2b16wb : VLD2WB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2u>;
812 defm VLD2b32wb : VLD2WB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2u>;
814 // VLD3 : Vector Load (multiple 3-element structures)
815 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
816 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
817 (ins addrmode6:$Rn), IIC_VLD3,
818 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
821 let DecoderMethod = "DecodeVLDInstruction";
824 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
825 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
826 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
828 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
829 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
830 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
832 // ...with address register writeback:
833 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
834 : NLdSt<0, 0b10, op11_8, op7_4,
835 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
836 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
837 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
838 "$Rn.addr = $wb", []> {
840 let DecoderMethod = "DecodeVLDInstruction";
843 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
844 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
845 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
847 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
848 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
849 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
851 // ...with double-spaced registers:
852 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
853 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
854 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
855 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
856 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
857 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
859 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
860 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
861 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
863 // ...alternate versions to be allocated odd register numbers:
864 def VLD3q8oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
865 def VLD3q16oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
866 def VLD3q32oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
868 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
869 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
870 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
872 // VLD4 : Vector Load (multiple 4-element structures)
873 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
874 : NLdSt<0, 0b10, op11_8, op7_4,
875 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
876 (ins addrmode6:$Rn), IIC_VLD4,
877 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
879 let Inst{5-4} = Rn{5-4};
880 let DecoderMethod = "DecodeVLDInstruction";
883 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
884 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
885 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
887 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
888 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
889 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
891 // ...with address register writeback:
892 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
893 : NLdSt<0, 0b10, op11_8, op7_4,
894 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
895 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u,
896 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
897 "$Rn.addr = $wb", []> {
898 let Inst{5-4} = Rn{5-4};
899 let DecoderMethod = "DecodeVLDInstruction";
902 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
903 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
904 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
906 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
907 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
908 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
910 // ...with double-spaced registers:
911 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
912 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
913 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
914 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
915 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
916 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
918 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
919 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
920 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
922 // ...alternate versions to be allocated odd register numbers:
923 def VLD4q8oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
924 def VLD4q16oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
925 def VLD4q32oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
927 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
928 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
929 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
931 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
933 // Classes for VLD*LN pseudo-instructions with multi-register operands.
934 // These are expanded to real instructions after register allocation.
935 class VLDQLNPseudo<InstrItinClass itin>
936 : PseudoNLdSt<(outs QPR:$dst),
937 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
938 itin, "$src = $dst">;
939 class VLDQLNWBPseudo<InstrItinClass itin>
940 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
941 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
942 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
943 class VLDQQLNPseudo<InstrItinClass itin>
944 : PseudoNLdSt<(outs QQPR:$dst),
945 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
946 itin, "$src = $dst">;
947 class VLDQQLNWBPseudo<InstrItinClass itin>
948 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
949 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
950 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
951 class VLDQQQQLNPseudo<InstrItinClass itin>
952 : PseudoNLdSt<(outs QQQQPR:$dst),
953 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
954 itin, "$src = $dst">;
955 class VLDQQQQLNWBPseudo<InstrItinClass itin>
956 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
957 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
958 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
960 // VLD1LN : Vector Load (single element to one lane)
961 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
963 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
964 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
965 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
967 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
968 (i32 (LoadOp addrmode6:$Rn)),
971 let DecoderMethod = "DecodeVLD1LN";
973 class VLD1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
975 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
976 (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane),
977 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
979 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
980 (i32 (LoadOp addrmode6oneL32:$Rn)),
983 let DecoderMethod = "DecodeVLD1LN";
985 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
986 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
987 (i32 (LoadOp addrmode6:$addr)),
991 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
992 let Inst{7-5} = lane{2-0};
994 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
995 let Inst{7-6} = lane{1-0};
996 let Inst{5-4} = Rn{5-4};
998 def VLD1LNd32 : VLD1LN32<0b1000, {?,0,?,?}, "32", v2i32, load> {
999 let Inst{7} = lane{0};
1000 let Inst{5-4} = Rn{5-4};
1003 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
1004 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
1005 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
1007 def : Pat<(vector_insert (v2f32 DPR:$src),
1008 (f32 (load addrmode6:$addr)), imm:$lane),
1009 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1010 def : Pat<(vector_insert (v4f32 QPR:$src),
1011 (f32 (load addrmode6:$addr)), imm:$lane),
1012 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1014 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1016 // ...with address register writeback:
1017 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1018 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
1019 (ins addrmode6:$Rn, am6offset:$Rm,
1020 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
1021 "\\{$Vd[$lane]\\}, $Rn$Rm",
1022 "$src = $Vd, $Rn.addr = $wb", []> {
1023 let DecoderMethod = "DecodeVLD1LN";
1026 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
1027 let Inst{7-5} = lane{2-0};
1029 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
1030 let Inst{7-6} = lane{1-0};
1031 let Inst{4} = Rn{4};
1033 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
1034 let Inst{7} = lane{0};
1035 let Inst{5} = Rn{4};
1036 let Inst{4} = Rn{4};
1039 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
1040 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
1041 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
1043 // VLD2LN : Vector Load (single 2-element structure to one lane)
1044 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1045 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
1046 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
1047 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
1048 "$src1 = $Vd, $src2 = $dst2", []> {
1050 let Inst{4} = Rn{4};
1051 let DecoderMethod = "DecodeVLD2LN";
1054 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
1055 let Inst{7-5} = lane{2-0};
1057 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
1058 let Inst{7-6} = lane{1-0};
1060 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
1061 let Inst{7} = lane{0};
1064 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
1065 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
1066 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
1068 // ...with double-spaced registers:
1069 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
1070 let Inst{7-6} = lane{1-0};
1072 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
1073 let Inst{7} = lane{0};
1076 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
1077 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
1079 // ...with address register writeback:
1080 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1081 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
1082 (ins addrmode6:$Rn, am6offset:$Rm,
1083 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
1084 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
1085 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
1086 let Inst{4} = Rn{4};
1087 let DecoderMethod = "DecodeVLD2LN";
1090 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
1091 let Inst{7-5} = lane{2-0};
1093 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
1094 let Inst{7-6} = lane{1-0};
1096 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
1097 let Inst{7} = lane{0};
1100 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
1101 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
1102 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
1104 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
1105 let Inst{7-6} = lane{1-0};
1107 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
1108 let Inst{7} = lane{0};
1111 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
1112 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
1114 // VLD3LN : Vector Load (single 3-element structure to one lane)
1115 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1116 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1117 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
1118 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
1119 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
1120 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
1122 let DecoderMethod = "DecodeVLD3LN";
1125 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
1126 let Inst{7-5} = lane{2-0};
1128 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
1129 let Inst{7-6} = lane{1-0};
1131 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
1132 let Inst{7} = lane{0};
1135 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1136 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1137 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1139 // ...with double-spaced registers:
1140 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
1141 let Inst{7-6} = lane{1-0};
1143 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
1144 let Inst{7} = lane{0};
1147 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
1148 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
1150 // ...with address register writeback:
1151 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1152 : NLdStLn<1, 0b10, op11_8, op7_4,
1153 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1154 (ins addrmode6:$Rn, am6offset:$Rm,
1155 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1156 IIC_VLD3lnu, "vld3", Dt,
1157 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
1158 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
1160 let DecoderMethod = "DecodeVLD3LN";
1163 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
1164 let Inst{7-5} = lane{2-0};
1166 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
1167 let Inst{7-6} = lane{1-0};
1169 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
1170 let Inst{7} = lane{0};
1173 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1174 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1175 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1177 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
1178 let Inst{7-6} = lane{1-0};
1180 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
1181 let Inst{7} = lane{0};
1184 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
1185 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
1187 // VLD4LN : Vector Load (single 4-element structure to one lane)
1188 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1189 : NLdStLn<1, 0b10, op11_8, op7_4,
1190 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1191 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
1192 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
1193 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
1194 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
1196 let Inst{4} = Rn{4};
1197 let DecoderMethod = "DecodeVLD4LN";
1200 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
1201 let Inst{7-5} = lane{2-0};
1203 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
1204 let Inst{7-6} = lane{1-0};
1206 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
1207 let Inst{7} = lane{0};
1208 let Inst{5} = Rn{5};
1211 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1212 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1213 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1215 // ...with double-spaced registers:
1216 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
1217 let Inst{7-6} = lane{1-0};
1219 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
1220 let Inst{7} = lane{0};
1221 let Inst{5} = Rn{5};
1224 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
1225 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
1227 // ...with address register writeback:
1228 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1229 : NLdStLn<1, 0b10, op11_8, op7_4,
1230 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1231 (ins addrmode6:$Rn, am6offset:$Rm,
1232 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1233 IIC_VLD4lnu, "vld4", Dt,
1234 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
1235 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
1237 let Inst{4} = Rn{4};
1238 let DecoderMethod = "DecodeVLD4LN" ;
1241 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
1242 let Inst{7-5} = lane{2-0};
1244 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
1245 let Inst{7-6} = lane{1-0};
1247 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
1248 let Inst{7} = lane{0};
1249 let Inst{5} = Rn{5};
1252 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1253 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1254 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1256 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
1257 let Inst{7-6} = lane{1-0};
1259 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
1260 let Inst{7} = lane{0};
1261 let Inst{5} = Rn{5};
1264 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
1265 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
1267 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1269 // VLD1DUP : Vector Load (single element to all lanes)
1270 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
1271 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd),
1272 (ins addrmode6dup:$Rn),
1273 IIC_VLD1dup, "vld1", Dt, "$Vd, $Rn", "",
1274 [(set VecListOneDAllLanes:$Vd,
1275 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
1277 let Inst{4} = Rn{4};
1278 let DecoderMethod = "DecodeVLD1DupInstruction";
1280 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
1281 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;
1282 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;
1284 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1285 (VLD1DUPd32 addrmode6:$addr)>;
1287 class VLD1QDUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
1288 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListDPairAllLanes:$Vd),
1289 (ins addrmode6dup:$Rn), IIC_VLD1dup,
1290 "vld1", Dt, "$Vd, $Rn", "",
1291 [(set VecListDPairAllLanes:$Vd,
1292 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
1294 let Inst{4} = Rn{4};
1295 let DecoderMethod = "DecodeVLD1DupInstruction";
1298 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8", v16i8, extloadi8>;
1299 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16", v8i16, extloadi16>;
1300 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32", v4i32, load>;
1302 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1303 (VLD1DUPq32 addrmode6:$addr)>;
1305 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1306 // ...with address register writeback:
1307 multiclass VLD1DUPWB<bits<4> op7_4, string Dt> {
1308 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1309 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1310 (ins addrmode6dup:$Rn), IIC_VLD1dupu,
1311 "vld1", Dt, "$Vd, $Rn!",
1312 "$Rn.addr = $wb", []> {
1313 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1314 let Inst{4} = Rn{4};
1315 let DecoderMethod = "DecodeVLD1DupInstruction";
1316 let AsmMatchConverter = "cvtVLDwbFixed";
1318 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1319 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1320 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1321 "vld1", Dt, "$Vd, $Rn, $Rm",
1322 "$Rn.addr = $wb", []> {
1323 let Inst{4} = Rn{4};
1324 let DecoderMethod = "DecodeVLD1DupInstruction";
1325 let AsmMatchConverter = "cvtVLDwbRegister";
1328 multiclass VLD1QDUPWB<bits<4> op7_4, string Dt> {
1329 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1330 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
1331 (ins addrmode6dup:$Rn), IIC_VLD1dupu,
1332 "vld1", Dt, "$Vd, $Rn!",
1333 "$Rn.addr = $wb", []> {
1334 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1335 let Inst{4} = Rn{4};
1336 let DecoderMethod = "DecodeVLD1DupInstruction";
1337 let AsmMatchConverter = "cvtVLDwbFixed";
1339 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1340 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
1341 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1342 "vld1", Dt, "$Vd, $Rn, $Rm",
1343 "$Rn.addr = $wb", []> {
1344 let Inst{4} = Rn{4};
1345 let DecoderMethod = "DecodeVLD1DupInstruction";
1346 let AsmMatchConverter = "cvtVLDwbRegister";
1350 defm VLD1DUPd8wb : VLD1DUPWB<{0,0,0,0}, "8">;
1351 defm VLD1DUPd16wb : VLD1DUPWB<{0,1,0,?}, "16">;
1352 defm VLD1DUPd32wb : VLD1DUPWB<{1,0,0,?}, "32">;
1354 defm VLD1DUPq8wb : VLD1QDUPWB<{0,0,1,0}, "8">;
1355 defm VLD1DUPq16wb : VLD1QDUPWB<{0,1,1,?}, "16">;
1356 defm VLD1DUPq32wb : VLD1QDUPWB<{1,0,1,?}, "32">;
1358 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
1359 class VLD2DUP<bits<4> op7_4, string Dt, RegisterOperand VdTy>
1360 : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd),
1361 (ins addrmode6dup:$Rn), IIC_VLD2dup,
1362 "vld2", Dt, "$Vd, $Rn", "", []> {
1364 let Inst{4} = Rn{4};
1365 let DecoderMethod = "DecodeVLD2DupInstruction";
1368 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListDPairAllLanes>;
1369 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes>;
1370 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes>;
1372 // ...with double-spaced registers
1373 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListDPairSpacedAllLanes>;
1374 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListDPairSpacedAllLanes>;
1375 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListDPairSpacedAllLanes>;
1377 // ...with address register writeback:
1378 multiclass VLD2DUPWB<bits<4> op7_4, string Dt, RegisterOperand VdTy> {
1379 def _fixed : NLdSt<1, 0b10, 0b1101, op7_4,
1380 (outs VdTy:$Vd, GPR:$wb),
1381 (ins addrmode6dup:$Rn), IIC_VLD2dupu,
1382 "vld2", Dt, "$Vd, $Rn!",
1383 "$Rn.addr = $wb", []> {
1384 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1385 let Inst{4} = Rn{4};
1386 let DecoderMethod = "DecodeVLD2DupInstruction";
1387 let AsmMatchConverter = "cvtVLDwbFixed";
1389 def _register : NLdSt<1, 0b10, 0b1101, op7_4,
1390 (outs VdTy:$Vd, GPR:$wb),
1391 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD2dupu,
1392 "vld2", Dt, "$Vd, $Rn, $Rm",
1393 "$Rn.addr = $wb", []> {
1394 let Inst{4} = Rn{4};
1395 let DecoderMethod = "DecodeVLD2DupInstruction";
1396 let AsmMatchConverter = "cvtVLDwbRegister";
1400 defm VLD2DUPd8wb : VLD2DUPWB<{0,0,0,0}, "8", VecListDPairAllLanes>;
1401 defm VLD2DUPd16wb : VLD2DUPWB<{0,1,0,?}, "16", VecListDPairAllLanes>;
1402 defm VLD2DUPd32wb : VLD2DUPWB<{1,0,0,?}, "32", VecListDPairAllLanes>;
1404 defm VLD2DUPd8x2wb : VLD2DUPWB<{0,0,1,0}, "8", VecListDPairSpacedAllLanes>;
1405 defm VLD2DUPd16x2wb : VLD2DUPWB<{0,1,1,?}, "16", VecListDPairSpacedAllLanes>;
1406 defm VLD2DUPd32x2wb : VLD2DUPWB<{1,0,1,?}, "32", VecListDPairSpacedAllLanes>;
1408 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
1409 class VLD3DUP<bits<4> op7_4, string Dt>
1410 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1411 (ins addrmode6dup:$Rn), IIC_VLD3dup,
1412 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
1415 let DecoderMethod = "DecodeVLD3DupInstruction";
1418 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
1419 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
1420 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
1422 def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1423 def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1424 def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1426 // ...with double-spaced registers (not used for codegen):
1427 def VLD3DUPq8 : VLD3DUP<{0,0,1,?}, "8">;
1428 def VLD3DUPq16 : VLD3DUP<{0,1,1,?}, "16">;
1429 def VLD3DUPq32 : VLD3DUP<{1,0,1,?}, "32">;
1431 // ...with address register writeback:
1432 class VLD3DUPWB<bits<4> op7_4, string Dt>
1433 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1434 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu,
1435 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
1436 "$Rn.addr = $wb", []> {
1438 let DecoderMethod = "DecodeVLD3DupInstruction";
1441 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;
1442 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">;
1443 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">;
1445 def VLD3DUPq8_UPD : VLD3DUPWB<{0,0,1,0}, "8">;
1446 def VLD3DUPq16_UPD : VLD3DUPWB<{0,1,1,?}, "16">;
1447 def VLD3DUPq32_UPD : VLD3DUPWB<{1,0,1,?}, "32">;
1449 def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1450 def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1451 def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1453 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1454 class VLD4DUP<bits<4> op7_4, string Dt>
1455 : NLdSt<1, 0b10, 0b1111, op7_4,
1456 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1457 (ins addrmode6dup:$Rn), IIC_VLD4dup,
1458 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
1460 let Inst{4} = Rn{4};
1461 let DecoderMethod = "DecodeVLD4DupInstruction";
1464 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1465 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1466 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1468 def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1469 def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1470 def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1472 // ...with double-spaced registers (not used for codegen):
1473 def VLD4DUPq8 : VLD4DUP<{0,0,1,?}, "8">;
1474 def VLD4DUPq16 : VLD4DUP<{0,1,1,?}, "16">;
1475 def VLD4DUPq32 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1477 // ...with address register writeback:
1478 class VLD4DUPWB<bits<4> op7_4, string Dt>
1479 : NLdSt<1, 0b10, 0b1111, op7_4,
1480 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1481 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
1482 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
1483 "$Rn.addr = $wb", []> {
1484 let Inst{4} = Rn{4};
1485 let DecoderMethod = "DecodeVLD4DupInstruction";
1488 def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">;
1489 def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">;
1490 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1492 def VLD4DUPq8_UPD : VLD4DUPWB<{0,0,1,0}, "8">;
1493 def VLD4DUPq16_UPD : VLD4DUPWB<{0,1,1,?}, "16">;
1494 def VLD4DUPq32_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1496 def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1497 def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1498 def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1500 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1502 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1504 // Classes for VST* pseudo-instructions with multi-register operands.
1505 // These are expanded to real instructions after register allocation.
1506 class VSTQPseudo<InstrItinClass itin>
1507 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1508 class VSTQWBPseudo<InstrItinClass itin>
1509 : PseudoNLdSt<(outs GPR:$wb),
1510 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1511 "$addr.addr = $wb">;
1512 class VSTQWBfixedPseudo<InstrItinClass itin>
1513 : PseudoNLdSt<(outs GPR:$wb),
1514 (ins addrmode6:$addr, QPR:$src), itin,
1515 "$addr.addr = $wb">;
1516 class VSTQWBregisterPseudo<InstrItinClass itin>
1517 : PseudoNLdSt<(outs GPR:$wb),
1518 (ins addrmode6:$addr, rGPR:$offset, QPR:$src), itin,
1519 "$addr.addr = $wb">;
1520 class VSTQQPseudo<InstrItinClass itin>
1521 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
1522 class VSTQQWBPseudo<InstrItinClass itin>
1523 : PseudoNLdSt<(outs GPR:$wb),
1524 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
1525 "$addr.addr = $wb">;
1526 class VSTQQWBfixedPseudo<InstrItinClass itin>
1527 : PseudoNLdSt<(outs GPR:$wb),
1528 (ins addrmode6:$addr, QQPR:$src), itin,
1529 "$addr.addr = $wb">;
1530 class VSTQQWBregisterPseudo<InstrItinClass itin>
1531 : PseudoNLdSt<(outs GPR:$wb),
1532 (ins addrmode6:$addr, rGPR:$offset, QQPR:$src), itin,
1533 "$addr.addr = $wb">;
1535 class VSTQQQQPseudo<InstrItinClass itin>
1536 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src), itin, "">;
1537 class VSTQQQQWBPseudo<InstrItinClass itin>
1538 : PseudoNLdSt<(outs GPR:$wb),
1539 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
1540 "$addr.addr = $wb">;
1542 // VST1 : Vector Store (multiple single elements)
1543 class VST1D<bits<4> op7_4, string Dt>
1544 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, VecListOneD:$Vd),
1545 IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []> {
1547 let Inst{4} = Rn{4};
1548 let DecoderMethod = "DecodeVSTInstruction";
1550 class VST1Q<bits<4> op7_4, string Dt>
1551 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$Rn, VecListDPair:$Vd),
1552 IIC_VST1x2, "vst1", Dt, "$Vd, $Rn", "", []> {
1554 let Inst{5-4} = Rn{5-4};
1555 let DecoderMethod = "DecodeVSTInstruction";
1558 def VST1d8 : VST1D<{0,0,0,?}, "8">;
1559 def VST1d16 : VST1D<{0,1,0,?}, "16">;
1560 def VST1d32 : VST1D<{1,0,0,?}, "32">;
1561 def VST1d64 : VST1D<{1,1,0,?}, "64">;
1563 def VST1q8 : VST1Q<{0,0,?,?}, "8">;
1564 def VST1q16 : VST1Q<{0,1,?,?}, "16">;
1565 def VST1q32 : VST1Q<{1,0,?,?}, "32">;
1566 def VST1q64 : VST1Q<{1,1,?,?}, "64">;
1568 // ...with address register writeback:
1569 multiclass VST1DWB<bits<4> op7_4, string Dt> {
1570 def _fixed : NLdSt<0,0b00, 0b0111,op7_4, (outs GPR:$wb),
1571 (ins addrmode6:$Rn, VecListOneD:$Vd), IIC_VLD1u,
1572 "vst1", Dt, "$Vd, $Rn!",
1573 "$Rn.addr = $wb", []> {
1574 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1575 let Inst{4} = Rn{4};
1576 let DecoderMethod = "DecodeVSTInstruction";
1577 let AsmMatchConverter = "cvtVSTwbFixed";
1579 def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb),
1580 (ins addrmode6:$Rn, rGPR:$Rm, VecListOneD:$Vd),
1582 "vst1", Dt, "$Vd, $Rn, $Rm",
1583 "$Rn.addr = $wb", []> {
1584 let Inst{4} = Rn{4};
1585 let DecoderMethod = "DecodeVSTInstruction";
1586 let AsmMatchConverter = "cvtVSTwbRegister";
1589 multiclass VST1QWB<bits<4> op7_4, string Dt> {
1590 def _fixed : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1591 (ins addrmode6:$Rn, VecListDPair:$Vd), IIC_VLD1x2u,
1592 "vst1", Dt, "$Vd, $Rn!",
1593 "$Rn.addr = $wb", []> {
1594 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1595 let Inst{5-4} = Rn{5-4};
1596 let DecoderMethod = "DecodeVSTInstruction";
1597 let AsmMatchConverter = "cvtVSTwbFixed";
1599 def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1600 (ins addrmode6:$Rn, rGPR:$Rm, VecListDPair:$Vd),
1602 "vst1", Dt, "$Vd, $Rn, $Rm",
1603 "$Rn.addr = $wb", []> {
1604 let Inst{5-4} = Rn{5-4};
1605 let DecoderMethod = "DecodeVSTInstruction";
1606 let AsmMatchConverter = "cvtVSTwbRegister";
1610 defm VST1d8wb : VST1DWB<{0,0,0,?}, "8">;
1611 defm VST1d16wb : VST1DWB<{0,1,0,?}, "16">;
1612 defm VST1d32wb : VST1DWB<{1,0,0,?}, "32">;
1613 defm VST1d64wb : VST1DWB<{1,1,0,?}, "64">;
1615 defm VST1q8wb : VST1QWB<{0,0,?,?}, "8">;
1616 defm VST1q16wb : VST1QWB<{0,1,?,?}, "16">;
1617 defm VST1q32wb : VST1QWB<{1,0,?,?}, "32">;
1618 defm VST1q64wb : VST1QWB<{1,1,?,?}, "64">;
1620 // ...with 3 registers
1621 class VST1D3<bits<4> op7_4, string Dt>
1622 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1623 (ins addrmode6:$Rn, VecListThreeD:$Vd),
1624 IIC_VST1x3, "vst1", Dt, "$Vd, $Rn", "", []> {
1626 let Inst{4} = Rn{4};
1627 let DecoderMethod = "DecodeVSTInstruction";
1629 multiclass VST1D3WB<bits<4> op7_4, string Dt> {
1630 def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1631 (ins addrmode6:$Rn, VecListThreeD:$Vd), IIC_VLD1x3u,
1632 "vst1", Dt, "$Vd, $Rn!",
1633 "$Rn.addr = $wb", []> {
1634 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1635 let Inst{5-4} = Rn{5-4};
1636 let DecoderMethod = "DecodeVSTInstruction";
1637 let AsmMatchConverter = "cvtVSTwbFixed";
1639 def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1640 (ins addrmode6:$Rn, rGPR:$Rm, VecListThreeD:$Vd),
1642 "vst1", Dt, "$Vd, $Rn, $Rm",
1643 "$Rn.addr = $wb", []> {
1644 let Inst{5-4} = Rn{5-4};
1645 let DecoderMethod = "DecodeVSTInstruction";
1646 let AsmMatchConverter = "cvtVSTwbRegister";
1650 def VST1d8T : VST1D3<{0,0,0,?}, "8">;
1651 def VST1d16T : VST1D3<{0,1,0,?}, "16">;
1652 def VST1d32T : VST1D3<{1,0,0,?}, "32">;
1653 def VST1d64T : VST1D3<{1,1,0,?}, "64">;
1655 defm VST1d8Twb : VST1D3WB<{0,0,0,?}, "8">;
1656 defm VST1d16Twb : VST1D3WB<{0,1,0,?}, "16">;
1657 defm VST1d32Twb : VST1D3WB<{1,0,0,?}, "32">;
1658 defm VST1d64Twb : VST1D3WB<{1,1,0,?}, "64">;
1660 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
1661 def VST1d64TPseudoWB_fixed : VSTQQWBPseudo<IIC_VST1x3u>;
1662 def VST1d64TPseudoWB_register : VSTQQWBPseudo<IIC_VST1x3u>;
1664 // ...with 4 registers
1665 class VST1D4<bits<4> op7_4, string Dt>
1666 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1667 (ins addrmode6:$Rn, VecListFourD:$Vd),
1668 IIC_VST1x4, "vst1", Dt, "$Vd, $Rn", "",
1671 let Inst{5-4} = Rn{5-4};
1672 let DecoderMethod = "DecodeVSTInstruction";
1674 multiclass VST1D4WB<bits<4> op7_4, string Dt> {
1675 def _fixed : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1676 (ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1x4u,
1677 "vst1", Dt, "$Vd, $Rn!",
1678 "$Rn.addr = $wb", []> {
1679 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1680 let Inst{5-4} = Rn{5-4};
1681 let DecoderMethod = "DecodeVSTInstruction";
1682 let AsmMatchConverter = "cvtVSTwbFixed";
1684 def _register : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1685 (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1687 "vst1", Dt, "$Vd, $Rn, $Rm",
1688 "$Rn.addr = $wb", []> {
1689 let Inst{5-4} = Rn{5-4};
1690 let DecoderMethod = "DecodeVSTInstruction";
1691 let AsmMatchConverter = "cvtVSTwbRegister";
1695 def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
1696 def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
1697 def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
1698 def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
1700 defm VST1d8Qwb : VST1D4WB<{0,0,?,?}, "8">;
1701 defm VST1d16Qwb : VST1D4WB<{0,1,?,?}, "16">;
1702 defm VST1d32Qwb : VST1D4WB<{1,0,?,?}, "32">;
1703 defm VST1d64Qwb : VST1D4WB<{1,1,?,?}, "64">;
1705 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
1706 def VST1d64QPseudoWB_fixed : VSTQQWBPseudo<IIC_VST1x4u>;
1707 def VST1d64QPseudoWB_register : VSTQQWBPseudo<IIC_VST1x4u>;
1709 // VST2 : Vector Store (multiple 2-element structures)
1710 class VST2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
1711 InstrItinClass itin>
1712 : NLdSt<0, 0b00, op11_8, op7_4, (outs), (ins addrmode6:$Rn, VdTy:$Vd),
1713 itin, "vst2", Dt, "$Vd, $Rn", "", []> {
1715 let Inst{5-4} = Rn{5-4};
1716 let DecoderMethod = "DecodeVSTInstruction";
1719 def VST2d8 : VST2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VST2>;
1720 def VST2d16 : VST2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VST2>;
1721 def VST2d32 : VST2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VST2>;
1723 def VST2q8 : VST2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VST2x2>;
1724 def VST2q16 : VST2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VST2x2>;
1725 def VST2q32 : VST2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VST2x2>;
1727 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
1728 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
1729 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
1731 // ...with address register writeback:
1732 multiclass VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt,
1733 RegisterOperand VdTy> {
1734 def _fixed : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1735 (ins addrmode6:$Rn, VdTy:$Vd), IIC_VLD1u,
1736 "vst2", Dt, "$Vd, $Rn!",
1737 "$Rn.addr = $wb", []> {
1738 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1739 let Inst{5-4} = Rn{5-4};
1740 let DecoderMethod = "DecodeVSTInstruction";
1741 let AsmMatchConverter = "cvtVSTwbFixed";
1743 def _register : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1744 (ins addrmode6:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u,
1745 "vst2", Dt, "$Vd, $Rn, $Rm",
1746 "$Rn.addr = $wb", []> {
1747 let Inst{5-4} = Rn{5-4};
1748 let DecoderMethod = "DecodeVSTInstruction";
1749 let AsmMatchConverter = "cvtVSTwbRegister";
1752 multiclass VST2QWB<bits<4> op7_4, string Dt> {
1753 def _fixed : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1754 (ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1u,
1755 "vst2", Dt, "$Vd, $Rn!",
1756 "$Rn.addr = $wb", []> {
1757 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1758 let Inst{5-4} = Rn{5-4};
1759 let DecoderMethod = "DecodeVSTInstruction";
1760 let AsmMatchConverter = "cvtVSTwbFixed";
1762 def _register : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1763 (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1765 "vst2", Dt, "$Vd, $Rn, $Rm",
1766 "$Rn.addr = $wb", []> {
1767 let Inst{5-4} = Rn{5-4};
1768 let DecoderMethod = "DecodeVSTInstruction";
1769 let AsmMatchConverter = "cvtVSTwbRegister";
1773 defm VST2d8wb : VST2DWB<0b1000, {0,0,?,?}, "8", VecListDPair>;
1774 defm VST2d16wb : VST2DWB<0b1000, {0,1,?,?}, "16", VecListDPair>;
1775 defm VST2d32wb : VST2DWB<0b1000, {1,0,?,?}, "32", VecListDPair>;
1777 defm VST2q8wb : VST2QWB<{0,0,?,?}, "8">;
1778 defm VST2q16wb : VST2QWB<{0,1,?,?}, "16">;
1779 defm VST2q32wb : VST2QWB<{1,0,?,?}, "32">;
1781 def VST2q8PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1782 def VST2q16PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1783 def VST2q32PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1784 def VST2q8PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1785 def VST2q16PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1786 def VST2q32PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1788 // ...with double-spaced registers
1789 def VST2b8 : VST2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VST2>;
1790 def VST2b16 : VST2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VST2>;
1791 def VST2b32 : VST2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VST2>;
1792 defm VST2b8wb : VST2DWB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced>;
1793 defm VST2b16wb : VST2DWB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced>;
1794 defm VST2b32wb : VST2DWB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced>;
1796 // VST3 : Vector Store (multiple 3-element structures)
1797 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1798 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1799 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1800 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1802 let Inst{4} = Rn{4};
1803 let DecoderMethod = "DecodeVSTInstruction";
1806 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1807 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1808 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
1810 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1811 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1812 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
1814 // ...with address register writeback:
1815 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1816 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1817 (ins addrmode6:$Rn, am6offset:$Rm,
1818 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1819 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1820 "$Rn.addr = $wb", []> {
1821 let Inst{4} = Rn{4};
1822 let DecoderMethod = "DecodeVSTInstruction";
1825 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1826 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1827 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
1829 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1830 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1831 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1833 // ...with double-spaced registers:
1834 def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1835 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1836 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1837 def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1838 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1839 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
1841 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1842 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1843 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1845 // ...alternate versions to be allocated odd register numbers:
1846 def VST3q8oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1847 def VST3q16oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1848 def VST3q32oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1850 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1851 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1852 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1854 // VST4 : Vector Store (multiple 4-element structures)
1855 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1856 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1857 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1858 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1861 let Inst{5-4} = Rn{5-4};
1862 let DecoderMethod = "DecodeVSTInstruction";
1865 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1866 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1867 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
1869 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1870 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1871 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
1873 // ...with address register writeback:
1874 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1875 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1876 (ins addrmode6:$Rn, am6offset:$Rm,
1877 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1878 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1879 "$Rn.addr = $wb", []> {
1880 let Inst{5-4} = Rn{5-4};
1881 let DecoderMethod = "DecodeVSTInstruction";
1884 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
1885 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
1886 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
1888 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1889 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1890 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1892 // ...with double-spaced registers:
1893 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
1894 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
1895 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
1896 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
1897 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
1898 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
1900 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1901 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1902 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1904 // ...alternate versions to be allocated odd register numbers:
1905 def VST4q8oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1906 def VST4q16oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1907 def VST4q32oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1909 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1910 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1911 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1913 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1915 // Classes for VST*LN pseudo-instructions with multi-register operands.
1916 // These are expanded to real instructions after register allocation.
1917 class VSTQLNPseudo<InstrItinClass itin>
1918 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1920 class VSTQLNWBPseudo<InstrItinClass itin>
1921 : PseudoNLdSt<(outs GPR:$wb),
1922 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1923 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1924 class VSTQQLNPseudo<InstrItinClass itin>
1925 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1927 class VSTQQLNWBPseudo<InstrItinClass itin>
1928 : PseudoNLdSt<(outs GPR:$wb),
1929 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1930 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1931 class VSTQQQQLNPseudo<InstrItinClass itin>
1932 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1934 class VSTQQQQLNWBPseudo<InstrItinClass itin>
1935 : PseudoNLdSt<(outs GPR:$wb),
1936 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1937 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1939 // VST1LN : Vector Store (single element from one lane)
1940 class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1941 PatFrag StoreOp, SDNode ExtractOp, Operand AddrMode>
1942 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1943 (ins AddrMode:$Rn, DPR:$Vd, nohash_imm:$lane),
1944 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1945 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), AddrMode:$Rn)]> {
1947 let DecoderMethod = "DecodeVST1LN";
1949 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1950 : VSTQLNPseudo<IIC_VST1ln> {
1951 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1955 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
1956 NEONvgetlaneu, addrmode6> {
1957 let Inst{7-5} = lane{2-0};
1959 def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
1960 NEONvgetlaneu, addrmode6> {
1961 let Inst{7-6} = lane{1-0};
1962 let Inst{4} = Rn{5};
1965 def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt,
1967 let Inst{7} = lane{0};
1968 let Inst{5-4} = Rn{5-4};
1971 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
1972 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
1973 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
1975 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
1976 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1977 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
1978 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1980 // ...with address register writeback:
1981 class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1982 PatFrag StoreOp, SDNode ExtractOp, Operand AdrMode>
1983 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1984 (ins AdrMode:$Rn, am6offset:$Rm,
1985 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
1986 "\\{$Vd[$lane]\\}, $Rn$Rm",
1988 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
1989 AdrMode:$Rn, am6offset:$Rm))]> {
1990 let DecoderMethod = "DecodeVST1LN";
1992 class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1993 : VSTQLNWBPseudo<IIC_VST1lnu> {
1994 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1995 addrmode6:$addr, am6offset:$offset))];
1998 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8,
1999 NEONvgetlaneu, addrmode6> {
2000 let Inst{7-5} = lane{2-0};
2002 def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16", v4i16, post_truncsti16,
2003 NEONvgetlaneu, addrmode6> {
2004 let Inst{7-6} = lane{1-0};
2005 let Inst{4} = Rn{5};
2007 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32", v2i32, post_store,
2008 extractelt, addrmode6oneL32> {
2009 let Inst{7} = lane{0};
2010 let Inst{5-4} = Rn{5-4};
2013 def VST1LNq8Pseudo_UPD : VST1QLNWBPseudo<v16i8, post_truncsti8, NEONvgetlaneu>;
2014 def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,NEONvgetlaneu>;
2015 def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
2017 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2019 // VST2LN : Vector Store (single 2-element structure from one lane)
2020 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2021 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2022 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
2023 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
2026 let Inst{4} = Rn{4};
2027 let DecoderMethod = "DecodeVST2LN";
2030 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
2031 let Inst{7-5} = lane{2-0};
2033 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
2034 let Inst{7-6} = lane{1-0};
2036 def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
2037 let Inst{7} = lane{0};
2040 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
2041 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
2042 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
2044 // ...with double-spaced registers:
2045 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
2046 let Inst{7-6} = lane{1-0};
2047 let Inst{4} = Rn{4};
2049 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
2050 let Inst{7} = lane{0};
2051 let Inst{4} = Rn{4};
2054 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
2055 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
2057 // ...with address register writeback:
2058 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2059 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2060 (ins addrmode6:$Rn, am6offset:$Rm,
2061 DPR:$Vd, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
2062 "\\{$Vd[$lane], $src2[$lane]\\}, $Rn$Rm",
2063 "$Rn.addr = $wb", []> {
2064 let Inst{4} = Rn{4};
2065 let DecoderMethod = "DecodeVST2LN";
2068 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
2069 let Inst{7-5} = lane{2-0};
2071 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
2072 let Inst{7-6} = lane{1-0};
2074 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
2075 let Inst{7} = lane{0};
2078 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2079 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2080 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2082 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
2083 let Inst{7-6} = lane{1-0};
2085 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
2086 let Inst{7} = lane{0};
2089 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
2090 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
2092 // VST3LN : Vector Store (single 3-element structure from one lane)
2093 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2094 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2095 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
2096 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
2097 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
2099 let DecoderMethod = "DecodeVST3LN";
2102 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
2103 let Inst{7-5} = lane{2-0};
2105 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
2106 let Inst{7-6} = lane{1-0};
2108 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
2109 let Inst{7} = lane{0};
2112 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2113 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2114 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2116 // ...with double-spaced registers:
2117 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
2118 let Inst{7-6} = lane{1-0};
2120 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
2121 let Inst{7} = lane{0};
2124 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
2125 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
2127 // ...with address register writeback:
2128 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2129 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2130 (ins addrmode6:$Rn, am6offset:$Rm,
2131 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
2132 IIC_VST3lnu, "vst3", Dt,
2133 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
2134 "$Rn.addr = $wb", []> {
2135 let DecoderMethod = "DecodeVST3LN";
2138 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
2139 let Inst{7-5} = lane{2-0};
2141 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
2142 let Inst{7-6} = lane{1-0};
2144 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
2145 let Inst{7} = lane{0};
2148 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2149 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2150 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2152 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
2153 let Inst{7-6} = lane{1-0};
2155 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
2156 let Inst{7} = lane{0};
2159 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
2160 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
2162 // VST4LN : Vector Store (single 4-element structure from one lane)
2163 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2164 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2165 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
2166 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
2167 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
2170 let Inst{4} = Rn{4};
2171 let DecoderMethod = "DecodeVST4LN";
2174 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
2175 let Inst{7-5} = lane{2-0};
2177 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
2178 let Inst{7-6} = lane{1-0};
2180 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
2181 let Inst{7} = lane{0};
2182 let Inst{5} = Rn{5};
2185 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2186 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2187 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2189 // ...with double-spaced registers:
2190 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
2191 let Inst{7-6} = lane{1-0};
2193 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
2194 let Inst{7} = lane{0};
2195 let Inst{5} = Rn{5};
2198 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
2199 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
2201 // ...with address register writeback:
2202 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2203 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2204 (ins addrmode6:$Rn, am6offset:$Rm,
2205 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
2206 IIC_VST4lnu, "vst4", Dt,
2207 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
2208 "$Rn.addr = $wb", []> {
2209 let Inst{4} = Rn{4};
2210 let DecoderMethod = "DecodeVST4LN";
2213 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
2214 let Inst{7-5} = lane{2-0};
2216 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
2217 let Inst{7-6} = lane{1-0};
2219 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
2220 let Inst{7} = lane{0};
2221 let Inst{5} = Rn{5};
2224 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2225 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2226 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2228 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
2229 let Inst{7-6} = lane{1-0};
2231 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
2232 let Inst{7} = lane{0};
2233 let Inst{5} = Rn{5};
2236 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
2237 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
2239 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2242 //===----------------------------------------------------------------------===//
2243 // NEON pattern fragments
2244 //===----------------------------------------------------------------------===//
2246 // Extract D sub-registers of Q registers.
2247 def DSubReg_i8_reg : SDNodeXForm<imm, [{
2248 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2249 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
2251 def DSubReg_i16_reg : SDNodeXForm<imm, [{
2252 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2253 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
2255 def DSubReg_i32_reg : SDNodeXForm<imm, [{
2256 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2257 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
2259 def DSubReg_f64_reg : SDNodeXForm<imm, [{
2260 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2261 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
2264 // Extract S sub-registers of Q/D registers.
2265 def SSubReg_f32_reg : SDNodeXForm<imm, [{
2266 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
2267 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
2270 // Translate lane numbers from Q registers to D subregs.
2271 def SubReg_i8_lane : SDNodeXForm<imm, [{
2272 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
2274 def SubReg_i16_lane : SDNodeXForm<imm, [{
2275 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
2277 def SubReg_i32_lane : SDNodeXForm<imm, [{
2278 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
2281 //===----------------------------------------------------------------------===//
2282 // Instruction Classes
2283 //===----------------------------------------------------------------------===//
2285 // Basic 2-register operations: double- and quad-register.
2286 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2287 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
2288 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2289 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2290 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
2291 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
2292 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2293 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
2294 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2295 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2296 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
2297 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
2299 // Basic 2-register intrinsics, both double- and quad-register.
2300 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2301 bits<2> op17_16, bits<5> op11_7, bit op4,
2302 InstrItinClass itin, string OpcodeStr, string Dt,
2303 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2304 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2305 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2306 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2307 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2308 bits<2> op17_16, bits<5> op11_7, bit op4,
2309 InstrItinClass itin, string OpcodeStr, string Dt,
2310 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2311 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2312 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2313 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2315 // Narrow 2-register operations.
2316 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2317 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2318 InstrItinClass itin, string OpcodeStr, string Dt,
2319 ValueType TyD, ValueType TyQ, SDNode OpNode>
2320 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2321 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2322 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
2324 // Narrow 2-register intrinsics.
2325 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2326 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2327 InstrItinClass itin, string OpcodeStr, string Dt,
2328 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
2329 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2330 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2331 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
2333 // Long 2-register operations (currently only used for VMOVL).
2334 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2335 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2336 InstrItinClass itin, string OpcodeStr, string Dt,
2337 ValueType TyQ, ValueType TyD, SDNode OpNode>
2338 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2339 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2340 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
2342 // Long 2-register intrinsics.
2343 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2344 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2345 InstrItinClass itin, string OpcodeStr, string Dt,
2346 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
2347 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2348 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2349 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
2351 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
2352 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
2353 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
2354 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
2355 OpcodeStr, Dt, "$Vd, $Vm",
2356 "$src1 = $Vd, $src2 = $Vm", []>;
2357 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
2358 InstrItinClass itin, string OpcodeStr, string Dt>
2359 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
2360 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
2361 "$src1 = $Vd, $src2 = $Vm", []>;
2363 // Basic 3-register operations: double- and quad-register.
2364 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2365 InstrItinClass itin, string OpcodeStr, string Dt,
2366 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2367 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2368 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2369 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2370 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2371 // All of these have a two-operand InstAlias.
2372 let TwoOperandAliasConstraint = "$Vn = $Vd";
2373 let isCommutable = Commutable;
2375 // Same as N3VD but no data type.
2376 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2377 InstrItinClass itin, string OpcodeStr,
2378 ValueType ResTy, ValueType OpTy,
2379 SDNode OpNode, bit Commutable>
2380 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
2381 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2382 OpcodeStr, "$Vd, $Vn, $Vm", "",
2383 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
2384 // All of these have a two-operand InstAlias.
2385 let TwoOperandAliasConstraint = "$Vn = $Vd";
2386 let isCommutable = Commutable;
2389 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
2390 InstrItinClass itin, string OpcodeStr, string Dt,
2391 ValueType Ty, SDNode ShOp>
2392 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2393 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2394 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2396 (Ty (ShOp (Ty DPR:$Vn),
2397 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
2398 let isCommutable = 0;
2400 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
2401 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2402 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2403 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2404 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane","",
2406 (Ty (ShOp (Ty DPR:$Vn),
2407 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2408 let isCommutable = 0;
2411 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2412 InstrItinClass itin, string OpcodeStr, string Dt,
2413 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2414 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2415 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2416 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2417 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2418 // All of these have a two-operand InstAlias.
2419 let TwoOperandAliasConstraint = "$Vn = $Vd";
2420 let isCommutable = Commutable;
2422 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2423 InstrItinClass itin, string OpcodeStr,
2424 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2425 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
2426 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2427 OpcodeStr, "$Vd, $Vn, $Vm", "",
2428 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
2429 // All of these have a two-operand InstAlias.
2430 let TwoOperandAliasConstraint = "$Vn = $Vd";
2431 let isCommutable = Commutable;
2433 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
2434 InstrItinClass itin, string OpcodeStr, string Dt,
2435 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2436 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2437 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2438 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2439 [(set (ResTy QPR:$Vd),
2440 (ResTy (ShOp (ResTy QPR:$Vn),
2441 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2443 let isCommutable = 0;
2445 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
2446 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2447 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2448 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2449 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane", "",
2450 [(set (ResTy QPR:$Vd),
2451 (ResTy (ShOp (ResTy QPR:$Vn),
2452 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2454 let isCommutable = 0;
2457 // Basic 3-register intrinsics, both double- and quad-register.
2458 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2459 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2460 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
2461 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2462 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
2463 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2464 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2465 // All of these have a two-operand InstAlias.
2466 let TwoOperandAliasConstraint = "$Vn = $Vd";
2467 let isCommutable = Commutable;
2469 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2470 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
2471 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2472 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2473 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2475 (Ty (IntOp (Ty DPR:$Vn),
2476 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2478 let isCommutable = 0;
2480 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2481 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
2482 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2483 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2484 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2486 (Ty (IntOp (Ty DPR:$Vn),
2487 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2488 let isCommutable = 0;
2490 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2491 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2492 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2493 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2494 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
2495 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2496 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
2497 let TwoOperandAliasConstraint = "$Vm = $Vd";
2498 let isCommutable = 0;
2501 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2502 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2503 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
2504 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2505 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
2506 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2507 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2508 // All of these have a two-operand InstAlias.
2509 let TwoOperandAliasConstraint = "$Vn = $Vd";
2510 let isCommutable = Commutable;
2512 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2513 string OpcodeStr, string Dt,
2514 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2515 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2516 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2517 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2518 [(set (ResTy QPR:$Vd),
2519 (ResTy (IntOp (ResTy QPR:$Vn),
2520 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2522 let isCommutable = 0;
2524 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2525 string OpcodeStr, string Dt,
2526 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2527 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2528 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2529 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2530 [(set (ResTy QPR:$Vd),
2531 (ResTy (IntOp (ResTy QPR:$Vn),
2532 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2534 let isCommutable = 0;
2536 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2537 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2538 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2539 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2540 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
2541 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2542 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
2543 let TwoOperandAliasConstraint = "$Vm = $Vd";
2544 let isCommutable = 0;
2547 // Multiply-Add/Sub operations: double- and quad-register.
2548 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2549 InstrItinClass itin, string OpcodeStr, string Dt,
2550 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode>
2551 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2552 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2553 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2554 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2555 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
2557 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2558 string OpcodeStr, string Dt,
2559 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
2560 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2562 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2564 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2566 (Ty (ShOp (Ty DPR:$src1),
2568 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2570 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2571 string OpcodeStr, string Dt,
2572 ValueType Ty, SDNode MulOp, SDNode ShOp>
2573 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2575 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2577 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2579 (Ty (ShOp (Ty DPR:$src1),
2581 (Ty (NEONvduplane (Ty DPR_8:$Vm),
2584 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2585 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
2586 SDPatternOperator MulOp, SDPatternOperator OpNode>
2587 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2588 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2589 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2590 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2591 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
2592 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2593 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2594 SDPatternOperator MulOp, SDPatternOperator ShOp>
2595 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2597 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2599 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2600 [(set (ResTy QPR:$Vd),
2601 (ResTy (ShOp (ResTy QPR:$src1),
2602 (ResTy (MulOp QPR:$Vn,
2603 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2605 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2606 string OpcodeStr, string Dt,
2607 ValueType ResTy, ValueType OpTy,
2608 SDNode MulOp, SDNode ShOp>
2609 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2611 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2613 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2614 [(set (ResTy QPR:$Vd),
2615 (ResTy (ShOp (ResTy QPR:$src1),
2616 (ResTy (MulOp QPR:$Vn,
2617 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2620 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
2621 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2622 InstrItinClass itin, string OpcodeStr, string Dt,
2623 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2624 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2625 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2626 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2627 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2628 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
2629 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2630 InstrItinClass itin, string OpcodeStr, string Dt,
2631 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2632 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2633 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2634 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2635 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2636 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2638 // Neon 3-argument intrinsics, both double- and quad-register.
2639 // The destination register is also used as the first source operand register.
2640 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2641 InstrItinClass itin, string OpcodeStr, string Dt,
2642 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2643 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2644 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2645 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2646 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2647 (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2648 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2649 InstrItinClass itin, string OpcodeStr, string Dt,
2650 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2651 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2652 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2653 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2654 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2655 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2657 // Long Multiply-Add/Sub operations.
2658 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2659 InstrItinClass itin, string OpcodeStr, string Dt,
2660 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2661 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2662 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2663 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2664 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2665 (TyQ (MulOp (TyD DPR:$Vn),
2666 (TyD DPR:$Vm)))))]>;
2667 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2668 InstrItinClass itin, string OpcodeStr, string Dt,
2669 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2670 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2671 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2673 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2675 (OpNode (TyQ QPR:$src1),
2676 (TyQ (MulOp (TyD DPR:$Vn),
2677 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),
2679 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2680 InstrItinClass itin, string OpcodeStr, string Dt,
2681 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2682 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2683 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2685 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2687 (OpNode (TyQ QPR:$src1),
2688 (TyQ (MulOp (TyD DPR:$Vn),
2689 (TyD (NEONvduplane (TyD DPR_8:$Vm),
2692 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
2693 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2694 InstrItinClass itin, string OpcodeStr, string Dt,
2695 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2697 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2698 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2699 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2700 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2701 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2702 (TyD DPR:$Vm)))))))]>;
2704 // Neon Long 3-argument intrinsic. The destination register is
2705 // a quad-register and is also used as the first source operand register.
2706 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2707 InstrItinClass itin, string OpcodeStr, string Dt,
2708 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
2709 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2710 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2711 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2713 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2714 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2715 string OpcodeStr, string Dt,
2716 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2717 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2719 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2721 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2722 [(set (ResTy QPR:$Vd),
2723 (ResTy (IntOp (ResTy QPR:$src1),
2725 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2727 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2728 InstrItinClass itin, string OpcodeStr, string Dt,
2729 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2730 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2732 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2734 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2735 [(set (ResTy QPR:$Vd),
2736 (ResTy (IntOp (ResTy QPR:$src1),
2738 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2741 // Narrowing 3-register intrinsics.
2742 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2743 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
2744 Intrinsic IntOp, bit Commutable>
2745 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2746 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2747 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2748 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2749 let isCommutable = Commutable;
2752 // Long 3-register operations.
2753 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2754 InstrItinClass itin, string OpcodeStr, string Dt,
2755 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
2756 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2757 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2758 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2759 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2760 let isCommutable = Commutable;
2762 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2763 InstrItinClass itin, string OpcodeStr, string Dt,
2764 ValueType TyQ, ValueType TyD, SDNode OpNode>
2765 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2766 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2767 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2769 (TyQ (OpNode (TyD DPR:$Vn),
2770 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
2771 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2772 InstrItinClass itin, string OpcodeStr, string Dt,
2773 ValueType TyQ, ValueType TyD, SDNode OpNode>
2774 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2775 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2776 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2778 (TyQ (OpNode (TyD DPR:$Vn),
2779 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
2781 // Long 3-register operations with explicitly extended operands.
2782 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2783 InstrItinClass itin, string OpcodeStr, string Dt,
2784 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
2786 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2787 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2788 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2789 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
2790 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2791 let isCommutable = Commutable;
2794 // Long 3-register intrinsics with explicit extend (VABDL).
2795 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2796 InstrItinClass itin, string OpcodeStr, string Dt,
2797 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2799 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2800 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2801 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2802 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2803 (TyD DPR:$Vm))))))]> {
2804 let isCommutable = Commutable;
2807 // Long 3-register intrinsics.
2808 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2809 InstrItinClass itin, string OpcodeStr, string Dt,
2810 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
2811 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2812 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2813 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2814 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2815 let isCommutable = Commutable;
2817 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2818 string OpcodeStr, string Dt,
2819 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2820 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2821 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2822 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2823 [(set (ResTy QPR:$Vd),
2824 (ResTy (IntOp (OpTy DPR:$Vn),
2825 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2827 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2828 InstrItinClass itin, string OpcodeStr, string Dt,
2829 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2830 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2831 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2832 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2833 [(set (ResTy QPR:$Vd),
2834 (ResTy (IntOp (OpTy DPR:$Vn),
2835 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2838 // Wide 3-register operations.
2839 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2840 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
2841 SDNode OpNode, SDNode ExtOp, bit Commutable>
2842 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2843 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
2844 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2845 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
2846 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2847 // All of these have a two-operand InstAlias.
2848 let TwoOperandAliasConstraint = "$Vn = $Vd";
2849 let isCommutable = Commutable;
2852 // Pairwise long 2-register intrinsics, both double- and quad-register.
2853 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2854 bits<2> op17_16, bits<5> op11_7, bit op4,
2855 string OpcodeStr, string Dt,
2856 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2857 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2858 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2859 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2860 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2861 bits<2> op17_16, bits<5> op11_7, bit op4,
2862 string OpcodeStr, string Dt,
2863 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2864 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2865 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2866 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2868 // Pairwise long 2-register accumulate intrinsics,
2869 // both double- and quad-register.
2870 // The destination register is also used as the first source operand register.
2871 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2872 bits<2> op17_16, bits<5> op11_7, bit op4,
2873 string OpcodeStr, string Dt,
2874 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2875 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
2876 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
2877 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2878 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
2879 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2880 bits<2> op17_16, bits<5> op11_7, bit op4,
2881 string OpcodeStr, string Dt,
2882 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2883 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
2884 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
2885 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2886 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
2888 // Shift by immediate,
2889 // both double- and quad-register.
2890 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
2891 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2892 Format f, InstrItinClass itin, Operand ImmTy,
2893 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2894 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2895 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
2896 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2897 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
2898 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2899 Format f, InstrItinClass itin, Operand ImmTy,
2900 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2901 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2902 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
2903 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2904 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
2907 // Long shift by immediate.
2908 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2909 string OpcodeStr, string Dt,
2910 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode>
2911 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2912 (outs QPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), N2RegVShLFrm,
2913 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2914 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm),
2915 (i32 imm:$SIMM))))]>;
2917 // Narrow shift by immediate.
2918 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2919 InstrItinClass itin, string OpcodeStr, string Dt,
2920 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode>
2921 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2922 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
2923 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2924 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
2925 (i32 imm:$SIMM))))]>;
2927 // Shift right by immediate and accumulate,
2928 // both double- and quad-register.
2929 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2930 Operand ImmTy, string OpcodeStr, string Dt,
2931 ValueType Ty, SDNode ShOp>
2932 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2933 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2934 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2935 [(set DPR:$Vd, (Ty (add DPR:$src1,
2936 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
2937 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2938 Operand ImmTy, string OpcodeStr, string Dt,
2939 ValueType Ty, SDNode ShOp>
2940 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2941 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2942 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2943 [(set QPR:$Vd, (Ty (add QPR:$src1,
2944 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
2946 // Shift by immediate and insert,
2947 // both double- and quad-register.
2948 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2949 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2950 ValueType Ty,SDNode ShOp>
2951 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2952 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiD,
2953 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2954 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
2955 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2956 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2957 ValueType Ty,SDNode ShOp>
2958 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2959 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiQ,
2960 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2961 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
2963 // Convert, with fractional bits immediate,
2964 // both double- and quad-register.
2965 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2966 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2968 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2969 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2970 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2971 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
2972 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2973 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2975 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2976 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2977 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2978 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
2980 //===----------------------------------------------------------------------===//
2982 //===----------------------------------------------------------------------===//
2984 // Abbreviations used in multiclass suffixes:
2985 // Q = quarter int (8 bit) elements
2986 // H = half int (16 bit) elements
2987 // S = single int (32 bit) elements
2988 // D = double int (64 bit) elements
2990 // Neon 2-register vector operations and intrinsics.
2992 // Neon 2-register comparisons.
2993 // source operand element sizes of 8, 16 and 32 bits:
2994 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2995 bits<5> op11_7, bit op4, string opc, string Dt,
2996 string asm, SDNode OpNode> {
2997 // 64-bit vector types.
2998 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
2999 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3000 opc, !strconcat(Dt, "8"), asm, "",
3001 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
3002 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
3003 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3004 opc, !strconcat(Dt, "16"), asm, "",
3005 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>;
3006 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
3007 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3008 opc, !strconcat(Dt, "32"), asm, "",
3009 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>;
3010 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
3011 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3012 opc, "f32", asm, "",
3013 [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> {
3014 let Inst{10} = 1; // overwrite F = 1
3017 // 128-bit vector types.
3018 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
3019 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3020 opc, !strconcat(Dt, "8"), asm, "",
3021 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
3022 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
3023 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3024 opc, !strconcat(Dt, "16"), asm, "",
3025 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
3026 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
3027 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3028 opc, !strconcat(Dt, "32"), asm, "",
3029 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
3030 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
3031 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3032 opc, "f32", asm, "",
3033 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
3034 let Inst{10} = 1; // overwrite F = 1
3039 // Neon 2-register vector intrinsics,
3040 // element sizes of 8, 16 and 32 bits:
3041 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3042 bits<5> op11_7, bit op4,
3043 InstrItinClass itinD, InstrItinClass itinQ,
3044 string OpcodeStr, string Dt, Intrinsic IntOp> {
3045 // 64-bit vector types.
3046 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3047 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
3048 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3049 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
3050 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3051 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
3053 // 128-bit vector types.
3054 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3055 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
3056 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3057 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
3058 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3059 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
3063 // Neon Narrowing 2-register vector operations,
3064 // source operand element sizes of 16, 32 and 64 bits:
3065 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3066 bits<5> op11_7, bit op6, bit op4,
3067 InstrItinClass itin, string OpcodeStr, string Dt,
3069 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
3070 itin, OpcodeStr, !strconcat(Dt, "16"),
3071 v8i8, v8i16, OpNode>;
3072 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3073 itin, OpcodeStr, !strconcat(Dt, "32"),
3074 v4i16, v4i32, OpNode>;
3075 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
3076 itin, OpcodeStr, !strconcat(Dt, "64"),
3077 v2i32, v2i64, OpNode>;
3080 // Neon Narrowing 2-register vector intrinsics,
3081 // source operand element sizes of 16, 32 and 64 bits:
3082 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3083 bits<5> op11_7, bit op6, bit op4,
3084 InstrItinClass itin, string OpcodeStr, string Dt,
3086 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
3087 itin, OpcodeStr, !strconcat(Dt, "16"),
3088 v8i8, v8i16, IntOp>;
3089 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3090 itin, OpcodeStr, !strconcat(Dt, "32"),
3091 v4i16, v4i32, IntOp>;
3092 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
3093 itin, OpcodeStr, !strconcat(Dt, "64"),
3094 v2i32, v2i64, IntOp>;
3098 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
3099 // source operand element sizes of 16, 32 and 64 bits:
3100 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
3101 string OpcodeStr, string Dt, SDNode OpNode> {
3102 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3103 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
3104 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3105 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
3106 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3107 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
3111 // Neon 3-register vector operations.
3113 // First with only element sizes of 8, 16 and 32 bits:
3114 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3115 InstrItinClass itinD16, InstrItinClass itinD32,
3116 InstrItinClass itinQ16, InstrItinClass itinQ32,
3117 string OpcodeStr, string Dt,
3118 SDNode OpNode, bit Commutable = 0> {
3119 // 64-bit vector types.
3120 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
3121 OpcodeStr, !strconcat(Dt, "8"),
3122 v8i8, v8i8, OpNode, Commutable>;
3123 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
3124 OpcodeStr, !strconcat(Dt, "16"),
3125 v4i16, v4i16, OpNode, Commutable>;
3126 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
3127 OpcodeStr, !strconcat(Dt, "32"),
3128 v2i32, v2i32, OpNode, Commutable>;
3130 // 128-bit vector types.
3131 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
3132 OpcodeStr, !strconcat(Dt, "8"),
3133 v16i8, v16i8, OpNode, Commutable>;
3134 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
3135 OpcodeStr, !strconcat(Dt, "16"),
3136 v8i16, v8i16, OpNode, Commutable>;
3137 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
3138 OpcodeStr, !strconcat(Dt, "32"),
3139 v4i32, v4i32, OpNode, Commutable>;
3142 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, SDNode ShOp> {
3143 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, "i16", v4i16, ShOp>;
3144 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, "i32", v2i32, ShOp>;
3145 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, "i16", v8i16, v4i16, ShOp>;
3146 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, "i32",
3147 v4i32, v2i32, ShOp>;
3150 // ....then also with element size 64 bits:
3151 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3152 InstrItinClass itinD, InstrItinClass itinQ,
3153 string OpcodeStr, string Dt,
3154 SDNode OpNode, bit Commutable = 0>
3155 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
3156 OpcodeStr, Dt, OpNode, Commutable> {
3157 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
3158 OpcodeStr, !strconcat(Dt, "64"),
3159 v1i64, v1i64, OpNode, Commutable>;
3160 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
3161 OpcodeStr, !strconcat(Dt, "64"),
3162 v2i64, v2i64, OpNode, Commutable>;
3166 // Neon 3-register vector intrinsics.
3168 // First with only element sizes of 16 and 32 bits:
3169 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3170 InstrItinClass itinD16, InstrItinClass itinD32,
3171 InstrItinClass itinQ16, InstrItinClass itinQ32,
3172 string OpcodeStr, string Dt,
3173 Intrinsic IntOp, bit Commutable = 0> {
3174 // 64-bit vector types.
3175 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
3176 OpcodeStr, !strconcat(Dt, "16"),
3177 v4i16, v4i16, IntOp, Commutable>;
3178 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
3179 OpcodeStr, !strconcat(Dt, "32"),
3180 v2i32, v2i32, IntOp, Commutable>;
3182 // 128-bit vector types.
3183 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3184 OpcodeStr, !strconcat(Dt, "16"),
3185 v8i16, v8i16, IntOp, Commutable>;
3186 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3187 OpcodeStr, !strconcat(Dt, "32"),
3188 v4i32, v4i32, IntOp, Commutable>;
3190 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3191 InstrItinClass itinD16, InstrItinClass itinD32,
3192 InstrItinClass itinQ16, InstrItinClass itinQ32,
3193 string OpcodeStr, string Dt,
3195 // 64-bit vector types.
3196 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
3197 OpcodeStr, !strconcat(Dt, "16"),
3198 v4i16, v4i16, IntOp>;
3199 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
3200 OpcodeStr, !strconcat(Dt, "32"),
3201 v2i32, v2i32, IntOp>;
3203 // 128-bit vector types.
3204 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3205 OpcodeStr, !strconcat(Dt, "16"),
3206 v8i16, v8i16, IntOp>;
3207 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3208 OpcodeStr, !strconcat(Dt, "32"),
3209 v4i32, v4i32, IntOp>;
3212 multiclass N3VIntSL_HS<bits<4> op11_8,
3213 InstrItinClass itinD16, InstrItinClass itinD32,
3214 InstrItinClass itinQ16, InstrItinClass itinQ32,
3215 string OpcodeStr, string Dt, Intrinsic IntOp> {
3216 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
3217 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
3218 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
3219 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
3220 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
3221 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
3222 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
3223 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
3226 // ....then also with element size of 8 bits:
3227 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3228 InstrItinClass itinD16, InstrItinClass itinD32,
3229 InstrItinClass itinQ16, InstrItinClass itinQ32,
3230 string OpcodeStr, string Dt,
3231 Intrinsic IntOp, bit Commutable = 0>
3232 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3233 OpcodeStr, Dt, IntOp, Commutable> {
3234 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
3235 OpcodeStr, !strconcat(Dt, "8"),
3236 v8i8, v8i8, IntOp, Commutable>;
3237 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
3238 OpcodeStr, !strconcat(Dt, "8"),
3239 v16i8, v16i8, IntOp, Commutable>;
3241 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3242 InstrItinClass itinD16, InstrItinClass itinD32,
3243 InstrItinClass itinQ16, InstrItinClass itinQ32,
3244 string OpcodeStr, string Dt,
3246 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3247 OpcodeStr, Dt, IntOp> {
3248 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
3249 OpcodeStr, !strconcat(Dt, "8"),
3251 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
3252 OpcodeStr, !strconcat(Dt, "8"),
3253 v16i8, v16i8, IntOp>;
3257 // ....then also with element size of 64 bits:
3258 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3259 InstrItinClass itinD16, InstrItinClass itinD32,
3260 InstrItinClass itinQ16, InstrItinClass itinQ32,
3261 string OpcodeStr, string Dt,
3262 Intrinsic IntOp, bit Commutable = 0>
3263 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3264 OpcodeStr, Dt, IntOp, Commutable> {
3265 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
3266 OpcodeStr, !strconcat(Dt, "64"),
3267 v1i64, v1i64, IntOp, Commutable>;
3268 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3269 OpcodeStr, !strconcat(Dt, "64"),
3270 v2i64, v2i64, IntOp, Commutable>;
3272 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3273 InstrItinClass itinD16, InstrItinClass itinD32,
3274 InstrItinClass itinQ16, InstrItinClass itinQ32,
3275 string OpcodeStr, string Dt,
3277 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3278 OpcodeStr, Dt, IntOp> {
3279 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
3280 OpcodeStr, !strconcat(Dt, "64"),
3281 v1i64, v1i64, IntOp>;
3282 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3283 OpcodeStr, !strconcat(Dt, "64"),
3284 v2i64, v2i64, IntOp>;
3287 // Neon Narrowing 3-register vector intrinsics,
3288 // source operand element sizes of 16, 32 and 64 bits:
3289 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3290 string OpcodeStr, string Dt,
3291 Intrinsic IntOp, bit Commutable = 0> {
3292 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
3293 OpcodeStr, !strconcat(Dt, "16"),
3294 v8i8, v8i16, IntOp, Commutable>;
3295 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
3296 OpcodeStr, !strconcat(Dt, "32"),
3297 v4i16, v4i32, IntOp, Commutable>;
3298 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
3299 OpcodeStr, !strconcat(Dt, "64"),
3300 v2i32, v2i64, IntOp, Commutable>;
3304 // Neon Long 3-register vector operations.
3306 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3307 InstrItinClass itin16, InstrItinClass itin32,
3308 string OpcodeStr, string Dt,
3309 SDNode OpNode, bit Commutable = 0> {
3310 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
3311 OpcodeStr, !strconcat(Dt, "8"),
3312 v8i16, v8i8, OpNode, Commutable>;
3313 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
3314 OpcodeStr, !strconcat(Dt, "16"),
3315 v4i32, v4i16, OpNode, Commutable>;
3316 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
3317 OpcodeStr, !strconcat(Dt, "32"),
3318 v2i64, v2i32, OpNode, Commutable>;
3321 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
3322 InstrItinClass itin, string OpcodeStr, string Dt,
3324 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
3325 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
3326 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
3327 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
3330 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3331 InstrItinClass itin16, InstrItinClass itin32,
3332 string OpcodeStr, string Dt,
3333 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3334 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
3335 OpcodeStr, !strconcat(Dt, "8"),
3336 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3337 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
3338 OpcodeStr, !strconcat(Dt, "16"),
3339 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3340 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
3341 OpcodeStr, !strconcat(Dt, "32"),
3342 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3345 // Neon Long 3-register vector intrinsics.
3347 // First with only element sizes of 16 and 32 bits:
3348 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3349 InstrItinClass itin16, InstrItinClass itin32,
3350 string OpcodeStr, string Dt,
3351 Intrinsic IntOp, bit Commutable = 0> {
3352 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
3353 OpcodeStr, !strconcat(Dt, "16"),
3354 v4i32, v4i16, IntOp, Commutable>;
3355 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
3356 OpcodeStr, !strconcat(Dt, "32"),
3357 v2i64, v2i32, IntOp, Commutable>;
3360 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
3361 InstrItinClass itin, string OpcodeStr, string Dt,
3363 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
3364 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3365 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
3366 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3369 // ....then also with element size of 8 bits:
3370 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3371 InstrItinClass itin16, InstrItinClass itin32,
3372 string OpcodeStr, string Dt,
3373 Intrinsic IntOp, bit Commutable = 0>
3374 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
3375 IntOp, Commutable> {
3376 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
3377 OpcodeStr, !strconcat(Dt, "8"),
3378 v8i16, v8i8, IntOp, Commutable>;
3381 // ....with explicit extend (VABDL).
3382 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3383 InstrItinClass itin, string OpcodeStr, string Dt,
3384 Intrinsic IntOp, SDNode ExtOp, bit Commutable = 0> {
3385 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
3386 OpcodeStr, !strconcat(Dt, "8"),
3387 v8i16, v8i8, IntOp, ExtOp, Commutable>;
3388 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
3389 OpcodeStr, !strconcat(Dt, "16"),
3390 v4i32, v4i16, IntOp, ExtOp, Commutable>;
3391 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
3392 OpcodeStr, !strconcat(Dt, "32"),
3393 v2i64, v2i32, IntOp, ExtOp, Commutable>;
3397 // Neon Wide 3-register vector intrinsics,
3398 // source operand element sizes of 8, 16 and 32 bits:
3399 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3400 string OpcodeStr, string Dt,
3401 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3402 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
3403 OpcodeStr, !strconcat(Dt, "8"),
3404 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3405 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
3406 OpcodeStr, !strconcat(Dt, "16"),
3407 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3408 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
3409 OpcodeStr, !strconcat(Dt, "32"),
3410 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3414 // Neon Multiply-Op vector operations,
3415 // element sizes of 8, 16 and 32 bits:
3416 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3417 InstrItinClass itinD16, InstrItinClass itinD32,
3418 InstrItinClass itinQ16, InstrItinClass itinQ32,
3419 string OpcodeStr, string Dt, SDNode OpNode> {
3420 // 64-bit vector types.
3421 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
3422 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
3423 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
3424 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
3425 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
3426 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
3428 // 128-bit vector types.
3429 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
3430 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
3431 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
3432 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
3433 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
3434 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
3437 multiclass N3VMulOpSL_HS<bits<4> op11_8,
3438 InstrItinClass itinD16, InstrItinClass itinD32,
3439 InstrItinClass itinQ16, InstrItinClass itinQ32,
3440 string OpcodeStr, string Dt, SDNode ShOp> {
3441 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
3442 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
3443 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
3444 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
3445 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
3446 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
3448 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
3449 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
3453 // Neon Intrinsic-Op vector operations,
3454 // element sizes of 8, 16 and 32 bits:
3455 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3456 InstrItinClass itinD, InstrItinClass itinQ,
3457 string OpcodeStr, string Dt, Intrinsic IntOp,
3459 // 64-bit vector types.
3460 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
3461 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
3462 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
3463 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
3464 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
3465 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
3467 // 128-bit vector types.
3468 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
3469 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
3470 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
3471 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
3472 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
3473 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
3476 // Neon 3-argument intrinsics,
3477 // element sizes of 8, 16 and 32 bits:
3478 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3479 InstrItinClass itinD, InstrItinClass itinQ,
3480 string OpcodeStr, string Dt, Intrinsic IntOp> {
3481 // 64-bit vector types.
3482 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
3483 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
3484 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
3485 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
3486 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
3487 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
3489 // 128-bit vector types.
3490 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
3491 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
3492 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
3493 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
3494 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
3495 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
3499 // Neon Long Multiply-Op vector operations,
3500 // element sizes of 8, 16 and 32 bits:
3501 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3502 InstrItinClass itin16, InstrItinClass itin32,
3503 string OpcodeStr, string Dt, SDNode MulOp,
3505 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
3506 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
3507 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
3508 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
3509 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
3510 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3513 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
3514 string Dt, SDNode MulOp, SDNode OpNode> {
3515 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
3516 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
3517 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
3518 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3522 // Neon Long 3-argument intrinsics.
3524 // First with only element sizes of 16 and 32 bits:
3525 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3526 InstrItinClass itin16, InstrItinClass itin32,
3527 string OpcodeStr, string Dt, Intrinsic IntOp> {
3528 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
3529 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3530 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
3531 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3534 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
3535 string OpcodeStr, string Dt, Intrinsic IntOp> {
3536 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
3537 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
3538 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
3539 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3542 // ....then also with element size of 8 bits:
3543 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3544 InstrItinClass itin16, InstrItinClass itin32,
3545 string OpcodeStr, string Dt, Intrinsic IntOp>
3546 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
3547 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
3548 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
3551 // ....with explicit extend (VABAL).
3552 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3553 InstrItinClass itin, string OpcodeStr, string Dt,
3554 Intrinsic IntOp, SDNode ExtOp, SDNode OpNode> {
3555 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
3556 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
3557 IntOp, ExtOp, OpNode>;
3558 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
3559 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
3560 IntOp, ExtOp, OpNode>;
3561 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
3562 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
3563 IntOp, ExtOp, OpNode>;
3567 // Neon Pairwise long 2-register intrinsics,
3568 // element sizes of 8, 16 and 32 bits:
3569 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3570 bits<5> op11_7, bit op4,
3571 string OpcodeStr, string Dt, Intrinsic IntOp> {
3572 // 64-bit vector types.
3573 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3574 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3575 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3576 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3577 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3578 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3580 // 128-bit vector types.
3581 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3582 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3583 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3584 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3585 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3586 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3590 // Neon Pairwise long 2-register accumulate intrinsics,
3591 // element sizes of 8, 16 and 32 bits:
3592 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3593 bits<5> op11_7, bit op4,
3594 string OpcodeStr, string Dt, Intrinsic IntOp> {
3595 // 64-bit vector types.
3596 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3597 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3598 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3599 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3600 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3601 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3603 // 128-bit vector types.
3604 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3605 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3606 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3607 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3608 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3609 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3613 // Neon 2-register vector shift by immediate,
3614 // with f of either N2RegVShLFrm or N2RegVShRFrm
3615 // element sizes of 8, 16, 32 and 64 bits:
3616 multiclass N2VShL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3617 InstrItinClass itin, string OpcodeStr, string Dt,
3619 // 64-bit vector types.
3620 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3621 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3622 let Inst{21-19} = 0b001; // imm6 = 001xxx
3624 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3625 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3626 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3628 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3629 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3630 let Inst{21} = 0b1; // imm6 = 1xxxxx
3632 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3633 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3636 // 128-bit vector types.
3637 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3638 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3639 let Inst{21-19} = 0b001; // imm6 = 001xxx
3641 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3642 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3643 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3645 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3646 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3647 let Inst{21} = 0b1; // imm6 = 1xxxxx
3649 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3650 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3653 multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3654 InstrItinClass itin, string OpcodeStr, string Dt,
3655 string baseOpc, SDNode OpNode> {
3656 // 64-bit vector types.
3657 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3658 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3659 let Inst{21-19} = 0b001; // imm6 = 001xxx
3661 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3662 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3663 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3665 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3666 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3667 let Inst{21} = 0b1; // imm6 = 1xxxxx
3669 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3670 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3673 // 128-bit vector types.
3674 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3675 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3676 let Inst{21-19} = 0b001; // imm6 = 001xxx
3678 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3679 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3680 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3682 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3683 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3684 let Inst{21} = 0b1; // imm6 = 1xxxxx
3686 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3687 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3691 // Neon Shift-Accumulate vector operations,
3692 // element sizes of 8, 16, 32 and 64 bits:
3693 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3694 string OpcodeStr, string Dt, SDNode ShOp> {
3695 // 64-bit vector types.
3696 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3697 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
3698 let Inst{21-19} = 0b001; // imm6 = 001xxx
3700 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3701 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
3702 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3704 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3705 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
3706 let Inst{21} = 0b1; // imm6 = 1xxxxx
3708 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3709 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
3712 // 128-bit vector types.
3713 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3714 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
3715 let Inst{21-19} = 0b001; // imm6 = 001xxx
3717 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3718 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
3719 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3721 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3722 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
3723 let Inst{21} = 0b1; // imm6 = 1xxxxx
3725 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3726 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
3730 // Neon Shift-Insert vector operations,
3731 // with f of either N2RegVShLFrm or N2RegVShRFrm
3732 // element sizes of 8, 16, 32 and 64 bits:
3733 multiclass N2VShInsL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3735 // 64-bit vector types.
3736 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3737 N2RegVShLFrm, OpcodeStr, "8", v8i8, NEONvsli> {
3738 let Inst{21-19} = 0b001; // imm6 = 001xxx
3740 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3741 N2RegVShLFrm, OpcodeStr, "16", v4i16, NEONvsli> {
3742 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3744 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3745 N2RegVShLFrm, OpcodeStr, "32", v2i32, NEONvsli> {
3746 let Inst{21} = 0b1; // imm6 = 1xxxxx
3748 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, i32imm,
3749 N2RegVShLFrm, OpcodeStr, "64", v1i64, NEONvsli>;
3752 // 128-bit vector types.
3753 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3754 N2RegVShLFrm, OpcodeStr, "8", v16i8, NEONvsli> {
3755 let Inst{21-19} = 0b001; // imm6 = 001xxx
3757 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3758 N2RegVShLFrm, OpcodeStr, "16", v8i16, NEONvsli> {
3759 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3761 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3762 N2RegVShLFrm, OpcodeStr, "32", v4i32, NEONvsli> {
3763 let Inst{21} = 0b1; // imm6 = 1xxxxx
3765 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, i32imm,
3766 N2RegVShLFrm, OpcodeStr, "64", v2i64, NEONvsli>;
3769 multiclass N2VShInsR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3771 // 64-bit vector types.
3772 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3773 N2RegVShRFrm, OpcodeStr, "8", v8i8, NEONvsri> {
3774 let Inst{21-19} = 0b001; // imm6 = 001xxx
3776 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3777 N2RegVShRFrm, OpcodeStr, "16", v4i16, NEONvsri> {
3778 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3780 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3781 N2RegVShRFrm, OpcodeStr, "32", v2i32, NEONvsri> {
3782 let Inst{21} = 0b1; // imm6 = 1xxxxx
3784 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3785 N2RegVShRFrm, OpcodeStr, "64", v1i64, NEONvsri>;
3788 // 128-bit vector types.
3789 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3790 N2RegVShRFrm, OpcodeStr, "8", v16i8, NEONvsri> {
3791 let Inst{21-19} = 0b001; // imm6 = 001xxx
3793 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3794 N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsri> {
3795 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3797 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3798 N2RegVShRFrm, OpcodeStr, "32", v4i32, NEONvsri> {
3799 let Inst{21} = 0b1; // imm6 = 1xxxxx
3801 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3802 N2RegVShRFrm, OpcodeStr, "64", v2i64, NEONvsri>;
3806 // Neon Shift Long operations,
3807 // element sizes of 8, 16, 32 bits:
3808 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3809 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
3810 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3811 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, imm1_7, OpNode> {
3812 let Inst{21-19} = 0b001; // imm6 = 001xxx
3814 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3815 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, imm1_15, OpNode> {
3816 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3818 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3819 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, imm1_31, OpNode> {
3820 let Inst{21} = 0b1; // imm6 = 1xxxxx
3824 // Neon Shift Narrow operations,
3825 // element sizes of 16, 32, 64 bits:
3826 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3827 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
3829 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3830 OpcodeStr, !strconcat(Dt, "16"),
3831 v8i8, v8i16, shr_imm8, OpNode> {
3832 let Inst{21-19} = 0b001; // imm6 = 001xxx
3834 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3835 OpcodeStr, !strconcat(Dt, "32"),
3836 v4i16, v4i32, shr_imm16, OpNode> {
3837 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3839 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3840 OpcodeStr, !strconcat(Dt, "64"),
3841 v2i32, v2i64, shr_imm32, OpNode> {
3842 let Inst{21} = 0b1; // imm6 = 1xxxxx
3846 //===----------------------------------------------------------------------===//
3847 // Instruction Definitions.
3848 //===----------------------------------------------------------------------===//
3850 // Vector Add Operations.
3852 // VADD : Vector Add (integer and floating-point)
3853 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
3855 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
3856 v2f32, v2f32, fadd, 1>;
3857 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
3858 v4f32, v4f32, fadd, 1>;
3859 // VADDL : Vector Add Long (Q = D + D)
3860 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3861 "vaddl", "s", add, sext, 1>;
3862 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3863 "vaddl", "u", add, zext, 1>;
3864 // VADDW : Vector Add Wide (Q = Q + D)
3865 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
3866 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
3867 // VHADD : Vector Halving Add
3868 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
3869 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3870 "vhadd", "s", int_arm_neon_vhadds, 1>;
3871 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
3872 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3873 "vhadd", "u", int_arm_neon_vhaddu, 1>;
3874 // VRHADD : Vector Rounding Halving Add
3875 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
3876 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3877 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
3878 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
3879 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3880 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
3881 // VQADD : Vector Saturating Add
3882 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
3883 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3884 "vqadd", "s", int_arm_neon_vqadds, 1>;
3885 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
3886 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3887 "vqadd", "u", int_arm_neon_vqaddu, 1>;
3888 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
3889 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
3890 int_arm_neon_vaddhn, 1>;
3891 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
3892 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
3893 int_arm_neon_vraddhn, 1>;
3895 // Vector Multiply Operations.
3897 // VMUL : Vector Multiply (integer, polynomial and floating-point)
3898 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
3899 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
3900 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
3901 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
3902 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
3903 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
3904 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
3905 v2f32, v2f32, fmul, 1>;
3906 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
3907 v4f32, v4f32, fmul, 1>;
3908 defm VMULsl : N3VSL_HS<0b1000, "vmul", mul>;
3909 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
3910 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
3913 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
3914 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
3915 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
3916 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3917 (DSubReg_i16_reg imm:$lane))),
3918 (SubReg_i16_lane imm:$lane)))>;
3919 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
3920 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
3921 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
3922 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3923 (DSubReg_i32_reg imm:$lane))),
3924 (SubReg_i32_lane imm:$lane)))>;
3925 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
3926 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
3927 (v4f32 (VMULslfq (v4f32 QPR:$src1),
3928 (v2f32 (EXTRACT_SUBREG QPR:$src2,
3929 (DSubReg_i32_reg imm:$lane))),
3930 (SubReg_i32_lane imm:$lane)))>;
3932 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
3933 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
3934 IIC_VMULi16Q, IIC_VMULi32Q,
3935 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
3936 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
3937 IIC_VMULi16Q, IIC_VMULi32Q,
3938 "vqdmulh", "s", int_arm_neon_vqdmulh>;
3939 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
3940 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3942 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
3943 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3944 (DSubReg_i16_reg imm:$lane))),
3945 (SubReg_i16_lane imm:$lane)))>;
3946 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
3947 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3949 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
3950 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3951 (DSubReg_i32_reg imm:$lane))),
3952 (SubReg_i32_lane imm:$lane)))>;
3954 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
3955 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
3956 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
3957 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
3958 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
3959 IIC_VMULi16Q, IIC_VMULi32Q,
3960 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
3961 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
3962 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3964 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
3965 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3966 (DSubReg_i16_reg imm:$lane))),
3967 (SubReg_i16_lane imm:$lane)))>;
3968 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
3969 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3971 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
3972 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3973 (DSubReg_i32_reg imm:$lane))),
3974 (SubReg_i32_lane imm:$lane)))>;
3976 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
3977 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3978 "vmull", "s", NEONvmulls, 1>;
3979 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3980 "vmull", "u", NEONvmullu, 1>;
3981 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
3982 v8i16, v8i8, int_arm_neon_vmullp, 1>;
3983 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
3984 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
3986 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
3987 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
3988 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
3989 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
3990 "vqdmull", "s", int_arm_neon_vqdmull>;
3992 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
3994 // VMLA : Vector Multiply Accumulate (integer and floating-point)
3995 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3996 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3997 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
3998 v2f32, fmul_su, fadd_mlx>,
3999 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4000 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
4001 v4f32, fmul_su, fadd_mlx>,
4002 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4003 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
4004 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
4005 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
4006 v2f32, fmul_su, fadd_mlx>,
4007 Requires<[HasNEON, UseFPVMLx]>;
4008 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
4009 v4f32, v2f32, fmul_su, fadd_mlx>,
4010 Requires<[HasNEON, UseFPVMLx]>;
4012 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
4013 (mul (v8i16 QPR:$src2),
4014 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4015 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
4016 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4017 (DSubReg_i16_reg imm:$lane))),
4018 (SubReg_i16_lane imm:$lane)))>;
4020 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
4021 (mul (v4i32 QPR:$src2),
4022 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4023 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
4024 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4025 (DSubReg_i32_reg imm:$lane))),
4026 (SubReg_i32_lane imm:$lane)))>;
4028 def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1),
4029 (fmul_su (v4f32 QPR:$src2),
4030 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
4031 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
4033 (v2f32 (EXTRACT_SUBREG QPR:$src3,
4034 (DSubReg_i32_reg imm:$lane))),
4035 (SubReg_i32_lane imm:$lane)))>,
4036 Requires<[HasNEON, UseFPVMLx]>;
4038 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
4039 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
4040 "vmlal", "s", NEONvmulls, add>;
4041 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
4042 "vmlal", "u", NEONvmullu, add>;
4044 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
4045 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
4047 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
4048 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
4049 "vqdmlal", "s", int_arm_neon_vqdmlal>;
4050 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
4052 // VMLS : Vector Multiply Subtract (integer and floating-point)
4053 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
4054 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
4055 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
4056 v2f32, fmul_su, fsub_mlx>,
4057 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4058 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
4059 v4f32, fmul_su, fsub_mlx>,
4060 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4061 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
4062 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
4063 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
4064 v2f32, fmul_su, fsub_mlx>,
4065 Requires<[HasNEON, UseFPVMLx]>;
4066 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
4067 v4f32, v2f32, fmul_su, fsub_mlx>,
4068 Requires<[HasNEON, UseFPVMLx]>;
4070 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
4071 (mul (v8i16 QPR:$src2),
4072 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4073 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
4074 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4075 (DSubReg_i16_reg imm:$lane))),
4076 (SubReg_i16_lane imm:$lane)))>;
4078 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
4079 (mul (v4i32 QPR:$src2),
4080 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4081 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
4082 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4083 (DSubReg_i32_reg imm:$lane))),
4084 (SubReg_i32_lane imm:$lane)))>;
4086 def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1),
4087 (fmul_su (v4f32 QPR:$src2),
4088 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
4089 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
4090 (v2f32 (EXTRACT_SUBREG QPR:$src3,
4091 (DSubReg_i32_reg imm:$lane))),
4092 (SubReg_i32_lane imm:$lane)))>,
4093 Requires<[HasNEON, UseFPVMLx]>;
4095 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
4096 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
4097 "vmlsl", "s", NEONvmulls, sub>;
4098 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
4099 "vmlsl", "u", NEONvmullu, sub>;
4101 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
4102 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
4104 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
4105 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
4106 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
4107 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
4109 // Fused Vector Multiply-Accumulate and Fused Multiply-Subtract Operations.
4110 def VFMAfd : N3VDMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACD, "vfma", "f32",
4111 v2f32, fmul_su, fadd_mlx>,
4112 Requires<[HasVFP4,UseFusedMAC]>;
4114 def VFMAfq : N3VQMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACQ, "vfma", "f32",
4115 v4f32, fmul_su, fadd_mlx>,
4116 Requires<[HasVFP4,UseFusedMAC]>;
4118 // Fused Vector Multiply Subtract (floating-point)
4119 def VFMSfd : N3VDMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACD, "vfms", "f32",
4120 v2f32, fmul_su, fsub_mlx>,
4121 Requires<[HasVFP4,UseFusedMAC]>;
4122 def VFMSfq : N3VQMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACQ, "vfms", "f32",
4123 v4f32, fmul_su, fsub_mlx>,
4124 Requires<[HasVFP4,UseFusedMAC]>;
4126 // Match @llvm.fma.* intrinsics
4127 def : Pat<(v2f32 (fma DPR:$src1, DPR:$Vn, DPR:$Vm)),
4128 (VFMAfd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4129 Requires<[HasVFP4]>;
4130 def : Pat<(v4f32 (fma QPR:$src1, QPR:$Vn, QPR:$Vm)),
4131 (VFMAfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4132 Requires<[HasVFP4]>;
4133 def : Pat<(v2f32 (fma (fneg DPR:$src1), DPR:$Vn, DPR:$Vm)),
4134 (VFMSfd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4135 Requires<[HasVFP4]>;
4136 def : Pat<(v4f32 (fma (fneg QPR:$src1), QPR:$Vn, QPR:$Vm)),
4137 (VFMSfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4138 Requires<[HasVFP4]>;
4140 // Vector Subtract Operations.
4142 // VSUB : Vector Subtract (integer and floating-point)
4143 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
4144 "vsub", "i", sub, 0>;
4145 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
4146 v2f32, v2f32, fsub, 0>;
4147 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
4148 v4f32, v4f32, fsub, 0>;
4149 // VSUBL : Vector Subtract Long (Q = D - D)
4150 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
4151 "vsubl", "s", sub, sext, 0>;
4152 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
4153 "vsubl", "u", sub, zext, 0>;
4154 // VSUBW : Vector Subtract Wide (Q = Q - D)
4155 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
4156 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
4157 // VHSUB : Vector Halving Subtract
4158 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
4159 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4160 "vhsub", "s", int_arm_neon_vhsubs, 0>;
4161 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
4162 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4163 "vhsub", "u", int_arm_neon_vhsubu, 0>;
4164 // VQSUB : Vector Saturing Subtract
4165 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
4166 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4167 "vqsub", "s", int_arm_neon_vqsubs, 0>;
4168 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
4169 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4170 "vqsub", "u", int_arm_neon_vqsubu, 0>;
4171 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
4172 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
4173 int_arm_neon_vsubhn, 0>;
4174 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
4175 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
4176 int_arm_neon_vrsubhn, 0>;
4178 // Vector Comparisons.
4180 // VCEQ : Vector Compare Equal
4181 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4182 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
4183 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
4185 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
4188 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
4189 "$Vd, $Vm, #0", NEONvceqz>;
4191 // VCGE : Vector Compare Greater Than or Equal
4192 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4193 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
4194 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4195 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
4196 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
4198 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
4201 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
4202 "$Vd, $Vm, #0", NEONvcgez>;
4203 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
4204 "$Vd, $Vm, #0", NEONvclez>;
4206 // VCGT : Vector Compare Greater Than
4207 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4208 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
4209 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4210 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
4211 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
4213 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
4216 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
4217 "$Vd, $Vm, #0", NEONvcgtz>;
4218 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
4219 "$Vd, $Vm, #0", NEONvcltz>;
4221 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
4222 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
4223 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
4224 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
4225 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
4226 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
4227 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
4228 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
4229 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
4230 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
4231 // VTST : Vector Test Bits
4232 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
4233 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
4235 // Vector Bitwise Operations.
4237 def vnotd : PatFrag<(ops node:$in),
4238 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
4239 def vnotq : PatFrag<(ops node:$in),
4240 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
4243 // VAND : Vector Bitwise AND
4244 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
4245 v2i32, v2i32, and, 1>;
4246 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
4247 v4i32, v4i32, and, 1>;
4249 // VEOR : Vector Bitwise Exclusive OR
4250 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
4251 v2i32, v2i32, xor, 1>;
4252 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
4253 v4i32, v4i32, xor, 1>;
4255 // VORR : Vector Bitwise OR
4256 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
4257 v2i32, v2i32, or, 1>;
4258 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
4259 v4i32, v4i32, or, 1>;
4261 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
4262 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4264 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4266 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4267 let Inst{9} = SIMM{9};
4270 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
4271 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4273 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4275 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4276 let Inst{10-9} = SIMM{10-9};
4279 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
4280 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4282 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4284 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4285 let Inst{9} = SIMM{9};
4288 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
4289 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4291 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4293 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4294 let Inst{10-9} = SIMM{10-9};
4298 // VBIC : Vector Bitwise Bit Clear (AND NOT)
4299 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4300 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
4301 "vbic", "$Vd, $Vn, $Vm", "",
4302 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
4303 (vnotd DPR:$Vm))))]>;
4304 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4305 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4306 "vbic", "$Vd, $Vn, $Vm", "",
4307 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
4308 (vnotq QPR:$Vm))))]>;
4310 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
4311 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4313 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4315 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4316 let Inst{9} = SIMM{9};
4319 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
4320 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4322 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4324 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4325 let Inst{10-9} = SIMM{10-9};
4328 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
4329 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4331 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4333 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4334 let Inst{9} = SIMM{9};
4337 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
4338 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4340 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4342 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4343 let Inst{10-9} = SIMM{10-9};
4346 // VORN : Vector Bitwise OR NOT
4347 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
4348 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
4349 "vorn", "$Vd, $Vn, $Vm", "",
4350 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
4351 (vnotd DPR:$Vm))))]>;
4352 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
4353 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4354 "vorn", "$Vd, $Vn, $Vm", "",
4355 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
4356 (vnotq QPR:$Vm))))]>;
4358 // VMVN : Vector Bitwise NOT (Immediate)
4360 let isReMaterializable = 1 in {
4362 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
4363 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4364 "vmvn", "i16", "$Vd, $SIMM", "",
4365 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
4366 let Inst{9} = SIMM{9};
4369 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
4370 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4371 "vmvn", "i16", "$Vd, $SIMM", "",
4372 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
4373 let Inst{9} = SIMM{9};
4376 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
4377 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4378 "vmvn", "i32", "$Vd, $SIMM", "",
4379 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
4380 let Inst{11-8} = SIMM{11-8};
4383 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
4384 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4385 "vmvn", "i32", "$Vd, $SIMM", "",
4386 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
4387 let Inst{11-8} = SIMM{11-8};
4391 // VMVN : Vector Bitwise NOT
4392 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
4393 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
4394 "vmvn", "$Vd, $Vm", "",
4395 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
4396 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
4397 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
4398 "vmvn", "$Vd, $Vm", "",
4399 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
4400 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
4401 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
4403 // VBSL : Vector Bitwise Select
4404 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4405 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4406 N3RegFrm, IIC_VCNTiD,
4407 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4409 (v2i32 (NEONvbsl DPR:$src1, DPR:$Vn, DPR:$Vm)))]>;
4411 def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
4412 (and DPR:$Vm, (vnotd DPR:$Vd)))),
4413 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>;
4415 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4416 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4417 N3RegFrm, IIC_VCNTiQ,
4418 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4420 (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>;
4422 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
4423 (and QPR:$Vm, (vnotq QPR:$Vd)))),
4424 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
4426 // VBIF : Vector Bitwise Insert if False
4427 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
4428 // FIXME: This instruction's encoding MAY NOT BE correct.
4429 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
4430 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4431 N3RegFrm, IIC_VBINiD,
4432 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4434 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
4435 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4436 N3RegFrm, IIC_VBINiQ,
4437 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4440 // VBIT : Vector Bitwise Insert if True
4441 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
4442 // FIXME: This instruction's encoding MAY NOT BE correct.
4443 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
4444 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4445 N3RegFrm, IIC_VBINiD,
4446 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4448 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
4449 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4450 N3RegFrm, IIC_VBINiQ,
4451 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4454 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
4455 // for equivalent operations with different register constraints; it just
4458 // Vector Absolute Differences.
4460 // VABD : Vector Absolute Difference
4461 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
4462 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4463 "vabd", "s", int_arm_neon_vabds, 1>;
4464 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
4465 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4466 "vabd", "u", int_arm_neon_vabdu, 1>;
4467 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
4468 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
4469 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
4470 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
4472 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
4473 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
4474 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
4475 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
4476 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
4478 // VABA : Vector Absolute Difference and Accumulate
4479 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4480 "vaba", "s", int_arm_neon_vabds, add>;
4481 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4482 "vaba", "u", int_arm_neon_vabdu, add>;
4484 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
4485 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
4486 "vabal", "s", int_arm_neon_vabds, zext, add>;
4487 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
4488 "vabal", "u", int_arm_neon_vabdu, zext, add>;
4490 // Vector Maximum and Minimum.
4492 // VMAX : Vector Maximum
4493 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
4494 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4495 "vmax", "s", int_arm_neon_vmaxs, 1>;
4496 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
4497 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4498 "vmax", "u", int_arm_neon_vmaxu, 1>;
4499 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
4501 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
4502 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4504 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
4506 // VMIN : Vector Minimum
4507 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
4508 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4509 "vmin", "s", int_arm_neon_vmins, 1>;
4510 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
4511 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4512 "vmin", "u", int_arm_neon_vminu, 1>;
4513 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
4515 v2f32, v2f32, int_arm_neon_vmins, 1>;
4516 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4518 v4f32, v4f32, int_arm_neon_vmins, 1>;
4520 // Vector Pairwise Operations.
4522 // VPADD : Vector Pairwise Add
4523 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4525 v8i8, v8i8, int_arm_neon_vpadd, 0>;
4526 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4528 v4i16, v4i16, int_arm_neon_vpadd, 0>;
4529 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4531 v2i32, v2i32, int_arm_neon_vpadd, 0>;
4532 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
4533 IIC_VPBIND, "vpadd", "f32",
4534 v2f32, v2f32, int_arm_neon_vpadd, 0>;
4536 // VPADDL : Vector Pairwise Add Long
4537 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
4538 int_arm_neon_vpaddls>;
4539 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
4540 int_arm_neon_vpaddlu>;
4542 // VPADAL : Vector Pairwise Add and Accumulate Long
4543 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
4544 int_arm_neon_vpadals>;
4545 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
4546 int_arm_neon_vpadalu>;
4548 // VPMAX : Vector Pairwise Maximum
4549 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4550 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
4551 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4552 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
4553 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4554 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
4555 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4556 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
4557 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4558 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
4559 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4560 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
4561 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
4562 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
4564 // VPMIN : Vector Pairwise Minimum
4565 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4566 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
4567 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4568 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
4569 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4570 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
4571 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4572 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
4573 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4574 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
4575 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4576 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
4577 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
4578 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
4580 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
4582 // VRECPE : Vector Reciprocal Estimate
4583 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4584 IIC_VUNAD, "vrecpe", "u32",
4585 v2i32, v2i32, int_arm_neon_vrecpe>;
4586 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4587 IIC_VUNAQ, "vrecpe", "u32",
4588 v4i32, v4i32, int_arm_neon_vrecpe>;
4589 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4590 IIC_VUNAD, "vrecpe", "f32",
4591 v2f32, v2f32, int_arm_neon_vrecpe>;
4592 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4593 IIC_VUNAQ, "vrecpe", "f32",
4594 v4f32, v4f32, int_arm_neon_vrecpe>;
4596 // VRECPS : Vector Reciprocal Step
4597 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4598 IIC_VRECSD, "vrecps", "f32",
4599 v2f32, v2f32, int_arm_neon_vrecps, 1>;
4600 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4601 IIC_VRECSQ, "vrecps", "f32",
4602 v4f32, v4f32, int_arm_neon_vrecps, 1>;
4604 // VRSQRTE : Vector Reciprocal Square Root Estimate
4605 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4606 IIC_VUNAD, "vrsqrte", "u32",
4607 v2i32, v2i32, int_arm_neon_vrsqrte>;
4608 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4609 IIC_VUNAQ, "vrsqrte", "u32",
4610 v4i32, v4i32, int_arm_neon_vrsqrte>;
4611 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4612 IIC_VUNAD, "vrsqrte", "f32",
4613 v2f32, v2f32, int_arm_neon_vrsqrte>;
4614 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4615 IIC_VUNAQ, "vrsqrte", "f32",
4616 v4f32, v4f32, int_arm_neon_vrsqrte>;
4618 // VRSQRTS : Vector Reciprocal Square Root Step
4619 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4620 IIC_VRECSD, "vrsqrts", "f32",
4621 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
4622 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4623 IIC_VRECSQ, "vrsqrts", "f32",
4624 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
4628 // VSHL : Vector Shift
4629 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
4630 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4631 "vshl", "s", int_arm_neon_vshifts>;
4632 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
4633 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4634 "vshl", "u", int_arm_neon_vshiftu>;
4636 // VSHL : Vector Shift Left (Immediate)
4637 defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
4639 // VSHR : Vector Shift Right (Immediate)
4640 defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", "VSHRs",
4642 defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", "VSHRu",
4645 // VSHLL : Vector Shift Left Long
4646 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
4647 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
4649 // VSHLL : Vector Shift Left Long (with maximum shift count)
4650 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
4651 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
4652 ValueType OpTy, Operand ImmTy, SDNode OpNode>
4653 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
4654 ResTy, OpTy, ImmTy, OpNode> {
4655 let Inst{21-16} = op21_16;
4656 let DecoderMethod = "DecodeVSHLMaxInstruction";
4658 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
4659 v8i16, v8i8, imm8, NEONvshlli>;
4660 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
4661 v4i32, v4i16, imm16, NEONvshlli>;
4662 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
4663 v2i64, v2i32, imm32, NEONvshlli>;
4665 // VSHRN : Vector Shift Right and Narrow
4666 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
4669 // VRSHL : Vector Rounding Shift
4670 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
4671 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4672 "vrshl", "s", int_arm_neon_vrshifts>;
4673 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
4674 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4675 "vrshl", "u", int_arm_neon_vrshiftu>;
4676 // VRSHR : Vector Rounding Shift Right
4677 defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", "VRSHRs",
4679 defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", "VRSHRu",
4682 // VRSHRN : Vector Rounding Shift Right and Narrow
4683 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
4686 // VQSHL : Vector Saturating Shift
4687 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
4688 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4689 "vqshl", "s", int_arm_neon_vqshifts>;
4690 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
4691 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4692 "vqshl", "u", int_arm_neon_vqshiftu>;
4693 // VQSHL : Vector Saturating Shift Left (Immediate)
4694 defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls>;
4695 defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu>;
4697 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
4698 defm VQSHLsu : N2VShL_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu>;
4700 // VQSHRN : Vector Saturating Shift Right and Narrow
4701 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
4703 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
4706 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
4707 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
4710 // VQRSHL : Vector Saturating Rounding Shift
4711 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
4712 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4713 "vqrshl", "s", int_arm_neon_vqrshifts>;
4714 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
4715 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4716 "vqrshl", "u", int_arm_neon_vqrshiftu>;
4718 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
4719 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
4721 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
4724 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
4725 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
4728 // VSRA : Vector Shift Right and Accumulate
4729 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
4730 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
4731 // VRSRA : Vector Rounding Shift Right and Accumulate
4732 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
4733 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
4735 // VSLI : Vector Shift Left and Insert
4736 defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">;
4738 // VSRI : Vector Shift Right and Insert
4739 defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;
4741 // Vector Absolute and Saturating Absolute.
4743 // VABS : Vector Absolute Value
4744 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
4745 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
4747 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4748 IIC_VUNAD, "vabs", "f32",
4749 v2f32, v2f32, int_arm_neon_vabs>;
4750 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4751 IIC_VUNAQ, "vabs", "f32",
4752 v4f32, v4f32, int_arm_neon_vabs>;
4754 // VQABS : Vector Saturating Absolute Value
4755 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
4756 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
4757 int_arm_neon_vqabs>;
4761 def vnegd : PatFrag<(ops node:$in),
4762 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
4763 def vnegq : PatFrag<(ops node:$in),
4764 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
4766 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4767 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
4768 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
4769 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
4770 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4771 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
4772 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
4773 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
4775 // VNEG : Vector Negate (integer)
4776 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
4777 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
4778 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
4779 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
4780 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
4781 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
4783 // VNEG : Vector Negate (floating-point)
4784 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
4785 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
4786 "vneg", "f32", "$Vd, $Vm", "",
4787 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
4788 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
4789 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
4790 "vneg", "f32", "$Vd, $Vm", "",
4791 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
4793 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
4794 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
4795 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
4796 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
4797 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
4798 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
4800 // VQNEG : Vector Saturating Negate
4801 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
4802 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
4803 int_arm_neon_vqneg>;
4805 // Vector Bit Counting Operations.
4807 // VCLS : Vector Count Leading Sign Bits
4808 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
4809 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
4811 // VCLZ : Vector Count Leading Zeros
4812 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
4813 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
4815 // VCNT : Vector Count One Bits
4816 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4817 IIC_VCNTiD, "vcnt", "8",
4818 v8i8, v8i8, int_arm_neon_vcnt>;
4819 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4820 IIC_VCNTiQ, "vcnt", "8",
4821 v16i8, v16i8, int_arm_neon_vcnt>;
4824 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
4825 (outs DPR:$Vd, DPR:$Vm), (ins DPR:$in1, DPR:$in2),
4826 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
4828 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
4829 (outs QPR:$Vd, QPR:$Vm), (ins QPR:$in1, QPR:$in2),
4830 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
4833 // Vector Move Operations.
4835 // VMOV : Vector Move (Register)
4836 def : InstAlias<"vmov${p} $Vd, $Vm",
4837 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
4838 def : InstAlias<"vmov${p} $Vd, $Vm",
4839 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
4841 // VMOV : Vector Move (Immediate)
4843 let isReMaterializable = 1 in {
4844 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
4845 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
4846 "vmov", "i8", "$Vd, $SIMM", "",
4847 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
4848 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
4849 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
4850 "vmov", "i8", "$Vd, $SIMM", "",
4851 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
4853 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
4854 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4855 "vmov", "i16", "$Vd, $SIMM", "",
4856 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
4857 let Inst{9} = SIMM{9};
4860 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
4861 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4862 "vmov", "i16", "$Vd, $SIMM", "",
4863 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
4864 let Inst{9} = SIMM{9};
4867 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
4868 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4869 "vmov", "i32", "$Vd, $SIMM", "",
4870 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
4871 let Inst{11-8} = SIMM{11-8};
4874 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
4875 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4876 "vmov", "i32", "$Vd, $SIMM", "",
4877 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
4878 let Inst{11-8} = SIMM{11-8};
4881 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
4882 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
4883 "vmov", "i64", "$Vd, $SIMM", "",
4884 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
4885 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
4886 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
4887 "vmov", "i64", "$Vd, $SIMM", "",
4888 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
4890 def VMOVv2f32 : N1ModImm<1, 0b000, 0b1111, 0, 0, 0, 1, (outs DPR:$Vd),
4891 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
4892 "vmov", "f32", "$Vd, $SIMM", "",
4893 [(set DPR:$Vd, (v2f32 (NEONvmovFPImm timm:$SIMM)))]>;
4894 def VMOVv4f32 : N1ModImm<1, 0b000, 0b1111, 0, 1, 0, 1, (outs QPR:$Vd),
4895 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
4896 "vmov", "f32", "$Vd, $SIMM", "",
4897 [(set QPR:$Vd, (v4f32 (NEONvmovFPImm timm:$SIMM)))]>;
4898 } // isReMaterializable
4900 // VMOV : Vector Get Lane (move scalar to ARM core register)
4902 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
4903 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
4904 IIC_VMOVSI, "vmov", "s8", "$R, $V$lane",
4905 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
4907 let Inst{21} = lane{2};
4908 let Inst{6-5} = lane{1-0};
4910 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
4911 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
4912 IIC_VMOVSI, "vmov", "s16", "$R, $V$lane",
4913 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
4915 let Inst{21} = lane{1};
4916 let Inst{6} = lane{0};
4918 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
4919 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
4920 IIC_VMOVSI, "vmov", "u8", "$R, $V$lane",
4921 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
4923 let Inst{21} = lane{2};
4924 let Inst{6-5} = lane{1-0};
4926 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
4927 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
4928 IIC_VMOVSI, "vmov", "u16", "$R, $V$lane",
4929 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
4931 let Inst{21} = lane{1};
4932 let Inst{6} = lane{0};
4934 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
4935 (outs GPR:$R), (ins DPR:$V, VectorIndex32:$lane),
4936 IIC_VMOVSI, "vmov", "32", "$R, $V$lane",
4937 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
4939 let Inst{21} = lane{0};
4941 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
4942 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
4943 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4944 (DSubReg_i8_reg imm:$lane))),
4945 (SubReg_i8_lane imm:$lane))>;
4946 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
4947 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4948 (DSubReg_i16_reg imm:$lane))),
4949 (SubReg_i16_lane imm:$lane))>;
4950 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
4951 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4952 (DSubReg_i8_reg imm:$lane))),
4953 (SubReg_i8_lane imm:$lane))>;
4954 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
4955 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4956 (DSubReg_i16_reg imm:$lane))),
4957 (SubReg_i16_lane imm:$lane))>;
4958 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
4959 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
4960 (DSubReg_i32_reg imm:$lane))),
4961 (SubReg_i32_lane imm:$lane))>;
4962 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
4963 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
4964 (SSubReg_f32_reg imm:$src2))>;
4965 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
4966 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
4967 (SSubReg_f32_reg imm:$src2))>;
4968 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
4969 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4970 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
4971 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4974 // VMOV : Vector Set Lane (move ARM core register to scalar)
4976 let Constraints = "$src1 = $V" in {
4977 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
4978 (ins DPR:$src1, GPR:$R, VectorIndex8:$lane),
4979 IIC_VMOVISL, "vmov", "8", "$V$lane, $R",
4980 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
4981 GPR:$R, imm:$lane))]> {
4982 let Inst{21} = lane{2};
4983 let Inst{6-5} = lane{1-0};
4985 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
4986 (ins DPR:$src1, GPR:$R, VectorIndex16:$lane),
4987 IIC_VMOVISL, "vmov", "16", "$V$lane, $R",
4988 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
4989 GPR:$R, imm:$lane))]> {
4990 let Inst{21} = lane{1};
4991 let Inst{6} = lane{0};
4993 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
4994 (ins DPR:$src1, GPR:$R, VectorIndex32:$lane),
4995 IIC_VMOVISL, "vmov", "32", "$V$lane, $R",
4996 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
4997 GPR:$R, imm:$lane))]> {
4998 let Inst{21} = lane{0};
5001 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
5002 (v16i8 (INSERT_SUBREG QPR:$src1,
5003 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
5004 (DSubReg_i8_reg imm:$lane))),
5005 GPR:$src2, (SubReg_i8_lane imm:$lane))),
5006 (DSubReg_i8_reg imm:$lane)))>;
5007 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
5008 (v8i16 (INSERT_SUBREG QPR:$src1,
5009 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
5010 (DSubReg_i16_reg imm:$lane))),
5011 GPR:$src2, (SubReg_i16_lane imm:$lane))),
5012 (DSubReg_i16_reg imm:$lane)))>;
5013 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
5014 (v4i32 (INSERT_SUBREG QPR:$src1,
5015 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
5016 (DSubReg_i32_reg imm:$lane))),
5017 GPR:$src2, (SubReg_i32_lane imm:$lane))),
5018 (DSubReg_i32_reg imm:$lane)))>;
5020 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
5021 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
5022 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
5023 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
5024 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
5025 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
5027 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
5028 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
5029 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
5030 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
5032 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
5033 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
5034 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
5035 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
5036 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
5037 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
5039 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
5040 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5041 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
5042 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5043 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
5044 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5046 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
5047 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
5048 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
5050 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
5051 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
5052 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
5054 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
5055 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
5056 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
5059 // VDUP : Vector Duplicate (from ARM core register to all elements)
5061 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
5062 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
5063 IIC_VMOVIS, "vdup", Dt, "$V, $R",
5064 [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
5065 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
5066 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
5067 IIC_VMOVIS, "vdup", Dt, "$V, $R",
5068 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
5070 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
5071 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
5072 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
5073 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
5074 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
5075 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
5077 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32d GPR:$R)>;
5078 def : Pat<(v4f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32q GPR:$R)>;
5080 // VDUP : Vector Duplicate Lane (from scalar to all elements)
5082 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
5083 ValueType Ty, Operand IdxTy>
5084 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
5085 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm$lane",
5086 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
5088 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
5089 ValueType ResTy, ValueType OpTy, Operand IdxTy>
5090 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
5091 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm$lane",
5092 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
5093 VectorIndex32:$lane)))]>;
5095 // Inst{19-16} is partially specified depending on the element size.
5097 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8, VectorIndex8> {
5099 let Inst{19-17} = lane{2-0};
5101 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16, VectorIndex16> {
5103 let Inst{19-18} = lane{1-0};
5105 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32, VectorIndex32> {
5107 let Inst{19} = lane{0};
5109 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8, VectorIndex8> {
5111 let Inst{19-17} = lane{2-0};
5113 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16, VectorIndex16> {
5115 let Inst{19-18} = lane{1-0};
5117 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32, VectorIndex32> {
5119 let Inst{19} = lane{0};
5122 def : Pat<(v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
5123 (VDUPLN32d DPR:$Vm, imm:$lane)>;
5125 def : Pat<(v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
5126 (VDUPLN32q DPR:$Vm, imm:$lane)>;
5128 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
5129 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
5130 (DSubReg_i8_reg imm:$lane))),
5131 (SubReg_i8_lane imm:$lane)))>;
5132 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
5133 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
5134 (DSubReg_i16_reg imm:$lane))),
5135 (SubReg_i16_lane imm:$lane)))>;
5136 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
5137 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
5138 (DSubReg_i32_reg imm:$lane))),
5139 (SubReg_i32_lane imm:$lane)))>;
5140 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
5141 (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src,
5142 (DSubReg_i32_reg imm:$lane))),
5143 (SubReg_i32_lane imm:$lane)))>;
5145 def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
5146 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
5147 def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
5148 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
5150 // VMOVN : Vector Narrowing Move
5151 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
5152 "vmovn", "i", trunc>;
5153 // VQMOVN : Vector Saturating Narrowing Move
5154 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
5155 "vqmovn", "s", int_arm_neon_vqmovns>;
5156 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
5157 "vqmovn", "u", int_arm_neon_vqmovnu>;
5158 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
5159 "vqmovun", "s", int_arm_neon_vqmovnsu>;
5160 // VMOVL : Vector Lengthening Move
5161 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
5162 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
5163 def : Pat<(v8i16 (anyext (v8i8 DPR:$Vm))), (VMOVLuv8i16 DPR:$Vm)>;
5164 def : Pat<(v4i32 (anyext (v4i16 DPR:$Vm))), (VMOVLuv4i32 DPR:$Vm)>;
5165 def : Pat<(v2i64 (anyext (v2i32 DPR:$Vm))), (VMOVLuv2i64 DPR:$Vm)>;
5167 // Vector Conversions.
5169 // VCVT : Vector Convert Between Floating-Point and Integers
5170 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
5171 v2i32, v2f32, fp_to_sint>;
5172 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
5173 v2i32, v2f32, fp_to_uint>;
5174 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
5175 v2f32, v2i32, sint_to_fp>;
5176 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
5177 v2f32, v2i32, uint_to_fp>;
5179 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
5180 v4i32, v4f32, fp_to_sint>;
5181 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
5182 v4i32, v4f32, fp_to_uint>;
5183 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
5184 v4f32, v4i32, sint_to_fp>;
5185 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
5186 v4f32, v4i32, uint_to_fp>;
5188 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
5189 let DecoderMethod = "DecodeVCVTD" in {
5190 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
5191 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
5192 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
5193 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
5194 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
5195 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
5196 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
5197 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
5200 let DecoderMethod = "DecodeVCVTQ" in {
5201 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
5202 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
5203 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
5204 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
5205 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
5206 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
5207 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
5208 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
5211 // VCVT : Vector Convert Between Half-Precision and Single-Precision.
5212 def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
5213 IIC_VUNAQ, "vcvt", "f16.f32",
5214 v4i16, v4f32, int_arm_neon_vcvtfp2hf>,
5215 Requires<[HasNEON, HasFP16]>;
5216 def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
5217 IIC_VUNAQ, "vcvt", "f32.f16",
5218 v4f32, v4i16, int_arm_neon_vcvthf2fp>,
5219 Requires<[HasNEON, HasFP16]>;
5223 // VREV64 : Vector Reverse elements within 64-bit doublewords
5225 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5226 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
5227 (ins DPR:$Vm), IIC_VMOVD,
5228 OpcodeStr, Dt, "$Vd, $Vm", "",
5229 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
5230 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5231 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
5232 (ins QPR:$Vm), IIC_VMOVQ,
5233 OpcodeStr, Dt, "$Vd, $Vm", "",
5234 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
5236 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
5237 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
5238 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
5239 def : Pat<(v2f32 (NEONvrev64 (v2f32 DPR:$Vm))), (VREV64d32 DPR:$Vm)>;
5241 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
5242 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
5243 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
5244 def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>;
5246 // VREV32 : Vector Reverse elements within 32-bit words
5248 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5249 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
5250 (ins DPR:$Vm), IIC_VMOVD,
5251 OpcodeStr, Dt, "$Vd, $Vm", "",
5252 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
5253 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5254 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
5255 (ins QPR:$Vm), IIC_VMOVQ,
5256 OpcodeStr, Dt, "$Vd, $Vm", "",
5257 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
5259 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
5260 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
5262 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
5263 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
5265 // VREV16 : Vector Reverse elements within 16-bit halfwords
5267 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5268 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
5269 (ins DPR:$Vm), IIC_VMOVD,
5270 OpcodeStr, Dt, "$Vd, $Vm", "",
5271 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
5272 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5273 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
5274 (ins QPR:$Vm), IIC_VMOVQ,
5275 OpcodeStr, Dt, "$Vd, $Vm", "",
5276 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
5278 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
5279 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
5281 // Other Vector Shuffles.
5283 // Aligned extractions: really just dropping registers
5285 class AlignedVEXTq<ValueType DestTy, ValueType SrcTy, SDNodeXForm LaneCVT>
5286 : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))),
5287 (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>;
5289 def : AlignedVEXTq<v8i8, v16i8, DSubReg_i8_reg>;
5291 def : AlignedVEXTq<v4i16, v8i16, DSubReg_i16_reg>;
5293 def : AlignedVEXTq<v2i32, v4i32, DSubReg_i32_reg>;
5295 def : AlignedVEXTq<v1i64, v2i64, DSubReg_f64_reg>;
5297 def : AlignedVEXTq<v2f32, v4f32, DSubReg_i32_reg>;
5300 // VEXT : Vector Extract
5302 class VEXTd<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
5303 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
5304 (ins DPR:$Vn, DPR:$Vm, immTy:$index), NVExtFrm,
5305 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
5306 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
5307 (Ty DPR:$Vm), imm:$index)))]> {
5309 let Inst{11-8} = index{3-0};
5312 class VEXTq<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
5313 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
5314 (ins QPR:$Vn, QPR:$Vm, imm0_15:$index), NVExtFrm,
5315 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
5316 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
5317 (Ty QPR:$Vm), imm:$index)))]> {
5319 let Inst{11-8} = index{3-0};
5322 def VEXTd8 : VEXTd<"vext", "8", v8i8, imm0_7> {
5323 let Inst{11-8} = index{3-0};
5325 def VEXTd16 : VEXTd<"vext", "16", v4i16, imm0_3> {
5326 let Inst{11-9} = index{2-0};
5329 def VEXTd32 : VEXTd<"vext", "32", v2i32, imm0_1> {
5330 let Inst{11-10} = index{1-0};
5331 let Inst{9-8} = 0b00;
5333 def : Pat<(v2f32 (NEONvext (v2f32 DPR:$Vn),
5336 (VEXTd32 DPR:$Vn, DPR:$Vm, imm:$index)>;
5338 def VEXTq8 : VEXTq<"vext", "8", v16i8, imm0_15> {
5339 let Inst{11-8} = index{3-0};
5341 def VEXTq16 : VEXTq<"vext", "16", v8i16, imm0_7> {
5342 let Inst{11-9} = index{2-0};
5345 def VEXTq32 : VEXTq<"vext", "32", v4i32, imm0_3> {
5346 let Inst{11-10} = index{1-0};
5347 let Inst{9-8} = 0b00;
5349 def VEXTq64 : VEXTq<"vext", "64", v2i64, imm0_1> {
5350 let Inst{11} = index{0};
5351 let Inst{10-8} = 0b000;
5353 def : Pat<(v4f32 (NEONvext (v4f32 QPR:$Vn),
5356 (VEXTq32 QPR:$Vn, QPR:$Vm, imm:$index)>;
5358 // VTRN : Vector Transpose
5360 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
5361 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
5362 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
5364 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
5365 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
5366 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
5368 // VUZP : Vector Unzip (Deinterleave)
5370 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
5371 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
5372 // vuzp.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
5373 def : NEONInstAlias<"vuzp${p}.32 $Dd, $Dm",
5374 (VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p)>;
5376 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
5377 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
5378 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
5380 // VZIP : Vector Zip (Interleave)
5382 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
5383 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
5384 // vzip.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
5385 def : NEONInstAlias<"vzip${p}.32 $Dd, $Dm",
5386 (VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p)>;
5388 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
5389 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
5390 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
5392 // Vector Table Lookup and Table Extension.
5394 // VTBL : Vector Table Lookup
5395 let DecoderMethod = "DecodeTBLInstruction" in {
5397 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
5398 (ins VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
5399 "vtbl", "8", "$Vd, $Vn, $Vm", "",
5400 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 VecListOneD:$Vn, DPR:$Vm)))]>;
5401 let hasExtraSrcRegAllocReq = 1 in {
5403 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
5404 (ins VecListDPair:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB2,
5405 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5407 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
5408 (ins VecListThreeD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB3,
5409 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5411 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
5412 (ins VecListFourD:$Vn, DPR:$Vm),
5414 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5415 } // hasExtraSrcRegAllocReq = 1
5418 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
5420 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
5422 // VTBX : Vector Table Extension
5424 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
5425 (ins DPR:$orig, VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
5426 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd",
5427 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
5428 DPR:$orig, VecListOneD:$Vn, DPR:$Vm)))]>;
5429 let hasExtraSrcRegAllocReq = 1 in {
5431 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
5432 (ins DPR:$orig, VecListDPair:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
5433 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd", []>;
5435 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
5436 (ins DPR:$orig, VecListThreeD:$Vn, DPR:$Vm),
5437 NVTBLFrm, IIC_VTBX3,
5438 "vtbx", "8", "$Vd, $Vn, $Vm",
5441 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd),
5442 (ins DPR:$orig, VecListFourD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
5443 "vtbx", "8", "$Vd, $Vn, $Vm",
5445 } // hasExtraSrcRegAllocReq = 1
5448 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
5449 IIC_VTBX3, "$orig = $dst", []>;
5451 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
5452 IIC_VTBX4, "$orig = $dst", []>;
5453 } // DecoderMethod = "DecodeTBLInstruction"
5455 //===----------------------------------------------------------------------===//
5456 // NEON instructions for single-precision FP math
5457 //===----------------------------------------------------------------------===//
5459 class N2VSPat<SDNode OpNode, NeonI Inst>
5460 : NEONFPPat<(f32 (OpNode SPR:$a)),
5462 (v2f32 (COPY_TO_REGCLASS (Inst
5464 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5465 SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>;
5467 class N3VSPat<SDNode OpNode, NeonI Inst>
5468 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
5470 (v2f32 (COPY_TO_REGCLASS (Inst
5472 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5475 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5476 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
5478 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
5479 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
5481 (v2f32 (COPY_TO_REGCLASS (Inst
5483 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5486 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5489 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5490 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
5492 def : N3VSPat<fadd, VADDfd>;
5493 def : N3VSPat<fsub, VSUBfd>;
5494 def : N3VSPat<fmul, VMULfd>;
5495 def : N3VSMulOpPat<fmul, fadd, VMLAfd>,
5496 Requires<[HasNEON, UseNEONForFP, UseFPVMLx, DontUseFusedMAC]>;
5497 def : N3VSMulOpPat<fmul, fsub, VMLSfd>,
5498 Requires<[HasNEON, UseNEONForFP, UseFPVMLx, DontUseFusedMAC]>;
5499 def : N3VSMulOpPat<fmul, fadd, VFMAfd>,
5500 Requires<[HasVFP4, UseNEONForFP, UseFusedMAC]>;
5501 def : N3VSMulOpPat<fmul, fsub, VFMSfd>,
5502 Requires<[HasVFP4, UseNEONForFP, UseFusedMAC]>;
5503 def : N2VSPat<fabs, VABSfd>;
5504 def : N2VSPat<fneg, VNEGfd>;
5505 def : N3VSPat<NEONfmax, VMAXfd>;
5506 def : N3VSPat<NEONfmin, VMINfd>;
5507 def : N2VSPat<arm_ftosi, VCVTf2sd>;
5508 def : N2VSPat<arm_ftoui, VCVTf2ud>;
5509 def : N2VSPat<arm_sitof, VCVTs2fd>;
5510 def : N2VSPat<arm_uitof, VCVTu2fd>;
5512 //===----------------------------------------------------------------------===//
5513 // Non-Instruction Patterns
5514 //===----------------------------------------------------------------------===//
5517 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
5518 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
5519 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
5520 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
5521 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
5522 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
5523 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
5524 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
5525 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
5526 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
5527 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
5528 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
5529 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
5530 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
5531 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
5532 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
5533 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
5534 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
5535 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
5536 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
5537 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
5538 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
5539 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
5540 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
5541 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
5542 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
5543 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
5544 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
5545 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
5546 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
5548 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
5549 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
5550 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
5551 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
5552 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
5553 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
5554 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
5555 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
5556 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
5557 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
5558 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
5559 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
5560 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
5561 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
5562 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
5563 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
5564 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
5565 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
5566 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
5567 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
5568 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
5569 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
5570 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
5571 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
5572 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
5573 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
5574 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
5575 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
5576 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
5577 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
5579 // Vector lengthening move with load, matching extending loads.
5581 // extload, zextload and sextload for a standard lengthening load. Example:
5582 // Lengthen_Single<"8", "i16", "i8"> = Pat<(v8i16 (extloadvi8 addrmode5:$addr))
5583 // (VMOVLuv8i16 (VLDRD addrmode5:$addr))>;
5584 multiclass Lengthen_Single<string DestLanes, string DestTy, string SrcTy> {
5585 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5586 (!cast<PatFrag>("extloadv" # SrcTy) addrmode5:$addr)),
5587 (!cast<Instruction>("VMOVLuv" # DestLanes # DestTy)
5588 (VLDRD addrmode5:$addr))>;
5589 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5590 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode5:$addr)),
5591 (!cast<Instruction>("VMOVLuv" # DestLanes # DestTy)
5592 (VLDRD addrmode5:$addr))>;
5593 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5594 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode5:$addr)),
5595 (!cast<Instruction>("VMOVLsv" # DestLanes # DestTy)
5596 (VLDRD addrmode5:$addr))>;
5599 // extload, zextload and sextload for a lengthening load which only uses
5600 // half the lanes available. Example:
5601 // Lengthen_HalfSingle<"4", "i16", "8", "i16", "i8"> =
5602 // Pat<(v4i16 (extloadvi8 addrmode5:$addr))
5603 // (EXTRACT_SUBREG (VMOVLuv8i16 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
5604 // (VLDRS addrmode5:$addr),
5607 multiclass Lengthen_HalfSingle<string DestLanes, string DestTy, string SrcTy,
5608 string InsnLanes, string InsnTy> {
5609 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5610 (!cast<PatFrag>("extloadv" # SrcTy) addrmode5:$addr)),
5611 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
5612 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), ssub_0)),
5614 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5615 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode5:$addr)),
5616 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
5617 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), ssub_0)),
5619 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5620 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode5:$addr)),
5621 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # InsnLanes # InsnTy)
5622 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), ssub_0)),
5626 // extload, zextload and sextload for a lengthening load followed by another
5627 // lengthening load, to quadruple the initial length.
5629 // Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32", qsub_0> =
5630 // Pat<(v4i32 (extloadvi8 addrmode5:$addr))
5631 // (EXTRACT_SUBREG (VMOVLuv4i32
5632 // (EXTRACT_SUBREG (VMOVLuv8i16 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
5633 // (VLDRS addrmode5:$addr),
5637 multiclass Lengthen_Double<string DestLanes, string DestTy, string SrcTy,
5638 string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
5640 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5641 (!cast<PatFrag>("extloadv" # SrcTy) addrmode5:$addr)),
5642 (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
5643 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
5644 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
5645 ssub_0)), dsub_0))>;
5646 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5647 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode5:$addr)),
5648 (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
5649 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
5650 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
5651 ssub_0)), dsub_0))>;
5652 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5653 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode5:$addr)),
5654 (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
5655 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
5656 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
5657 ssub_0)), dsub_0))>;
5660 // extload, zextload and sextload for a lengthening load followed by another
5661 // lengthening load, to quadruple the initial length, but which ends up only
5662 // requiring half the available lanes (a 64-bit outcome instead of a 128-bit).
5664 // Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32"> =
5665 // Pat<(v4i32 (extloadvi8 addrmode5:$addr))
5666 // (EXTRACT_SUBREG (VMOVLuv4i32
5667 // (EXTRACT_SUBREG (VMOVLuv8i16 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
5668 // (VLDRS addrmode5:$addr),
5672 multiclass Lengthen_HalfDouble<string DestLanes, string DestTy, string SrcTy,
5673 string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
5675 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5676 (!cast<PatFrag>("extloadv" # SrcTy) addrmode5:$addr)),
5677 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
5678 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
5679 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
5682 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5683 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode5:$addr)),
5684 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
5685 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
5686 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
5689 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5690 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode5:$addr)),
5691 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
5692 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
5693 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
5698 defm : Lengthen_Single<"8", "i16", "i8">; // v8i8 -> v8i16
5699 defm : Lengthen_Single<"4", "i32", "i16">; // v4i16 -> v4i32
5700 defm : Lengthen_Single<"2", "i64", "i32">; // v2i32 -> v2i64
5702 defm : Lengthen_HalfSingle<"4", "i16", "i8", "8", "i16">; // v4i8 -> v4i16
5703 defm : Lengthen_HalfSingle<"2", "i16", "i8", "8", "i16">; // v2i8 -> v2i16
5704 defm : Lengthen_HalfSingle<"2", "i32", "i16", "4", "i32">; // v2i16 -> v2i32
5706 // Double lengthening - v4i8 -> v4i16 -> v4i32
5707 defm : Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32">;
5708 // v2i8 -> v2i16 -> v2i32
5709 defm : Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32">;
5710 // v2i16 -> v2i32 -> v2i64
5711 defm : Lengthen_Double<"2", "i64", "i16", "4", "i32", "2", "i64">;
5713 // Triple lengthening - v2i8 -> v2i16 -> v2i32 -> v2i64
5714 def : Pat<(v2i64 (extloadvi8 addrmode5:$addr)),
5715 (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
5716 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), ssub_0)),
5717 dsub_0)), dsub_0))>;
5718 def : Pat<(v2i64 (zextloadvi8 addrmode5:$addr)),
5719 (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
5720 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), ssub_0)),
5721 dsub_0)), dsub_0))>;
5722 def : Pat<(v2i64 (sextloadvi8 addrmode5:$addr)),
5723 (VMOVLsv2i64 (EXTRACT_SUBREG (VMOVLsv4i32 (EXTRACT_SUBREG (VMOVLsv8i16
5724 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), ssub_0)),
5725 dsub_0)), dsub_0))>;
5727 //===----------------------------------------------------------------------===//
5728 // Assembler aliases
5731 def : VFP2InstAlias<"fmdhr${p} $Dd, $Rn",
5732 (VSETLNi32 DPR:$Dd, GPR:$Rn, 1, pred:$p)>;
5733 def : VFP2InstAlias<"fmdlr${p} $Dd, $Rn",
5734 (VSETLNi32 DPR:$Dd, GPR:$Rn, 0, pred:$p)>;
5736 // VAND/VBIC/VEOR/VORR accept but do not require a type suffix.
5737 defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
5738 (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
5739 defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
5740 (VANDq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
5741 defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
5742 (VBICd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
5743 defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
5744 (VBICq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
5745 defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
5746 (VEORd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
5747 defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
5748 (VEORq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
5749 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
5750 (VORRd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
5751 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
5752 (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
5753 // ... two-operand aliases
5754 defm : NEONDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",
5755 (VANDd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5756 defm : NEONDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",
5757 (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5758 defm : NEONDTAnyInstAlias<"veor${p}", "$Vdn, $Vm",
5759 (VEORd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5760 defm : NEONDTAnyInstAlias<"veor${p}", "$Vdn, $Vm",
5761 (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5762 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
5763 (VORRd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5764 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
5765 (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5767 // VMUL two-operand aliases.
5768 def : NEONInstAlias<"vmul${p}.i16 $Ddn, $Dm$lane",
5769 (VMULslv4i16 DPR:$Ddn, DPR:$Ddn, DPR_8:$Dm,
5770 VectorIndex16:$lane, pred:$p)>;
5771 def : NEONInstAlias<"vmul${p}.i16 $Qdn, $Dm$lane",
5772 (VMULslv8i16 QPR:$Qdn, QPR:$Qdn, DPR_8:$Dm,
5773 VectorIndex16:$lane, pred:$p)>;
5775 def : NEONInstAlias<"vmul${p}.i32 $Ddn, $Dm$lane",
5776 (VMULslv2i32 DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm,
5777 VectorIndex32:$lane, pred:$p)>;
5778 def : NEONInstAlias<"vmul${p}.i32 $Qdn, $Dm$lane",
5779 (VMULslv4i32 QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm,
5780 VectorIndex32:$lane, pred:$p)>;
5782 def : NEONInstAlias<"vmul${p}.f32 $Ddn, $Dm$lane",
5783 (VMULslfd DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm,
5784 VectorIndex32:$lane, pred:$p)>;
5785 def : NEONInstAlias<"vmul${p}.f32 $Qdn, $Dm$lane",
5786 (VMULslfq QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm,
5787 VectorIndex32:$lane, pred:$p)>;
5789 // VLD1 single-lane pseudo-instructions. These need special handling for
5790 // the lane index that an InstAlias can't handle, so we use these instead.
5791 def VLD1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr",
5792 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5793 def VLD1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr",
5794 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5795 def VLD1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr",
5796 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5798 def VLD1LNdWB_fixed_Asm_8 :
5799 NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr!",
5800 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5801 def VLD1LNdWB_fixed_Asm_16 :
5802 NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr!",
5803 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5804 def VLD1LNdWB_fixed_Asm_32 :
5805 NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr!",
5806 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5807 def VLD1LNdWB_register_Asm_8 :
5808 NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr, $Rm",
5809 (ins VecListOneDByteIndexed:$list, addrmode6:$addr,
5810 rGPR:$Rm, pred:$p)>;
5811 def VLD1LNdWB_register_Asm_16 :
5812 NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr, $Rm",
5813 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr,
5814 rGPR:$Rm, pred:$p)>;
5815 def VLD1LNdWB_register_Asm_32 :
5816 NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr, $Rm",
5817 (ins VecListOneDWordIndexed:$list, addrmode6:$addr,
5818 rGPR:$Rm, pred:$p)>;
5821 // VST1 single-lane pseudo-instructions. These need special handling for
5822 // the lane index that an InstAlias can't handle, so we use these instead.
5823 def VST1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr",
5824 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5825 def VST1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr",
5826 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5827 def VST1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr",
5828 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5830 def VST1LNdWB_fixed_Asm_8 :
5831 NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr!",
5832 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5833 def VST1LNdWB_fixed_Asm_16 :
5834 NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr!",
5835 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5836 def VST1LNdWB_fixed_Asm_32 :
5837 NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr!",
5838 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5839 def VST1LNdWB_register_Asm_8 :
5840 NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr, $Rm",
5841 (ins VecListOneDByteIndexed:$list, addrmode6:$addr,
5842 rGPR:$Rm, pred:$p)>;
5843 def VST1LNdWB_register_Asm_16 :
5844 NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr, $Rm",
5845 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr,
5846 rGPR:$Rm, pred:$p)>;
5847 def VST1LNdWB_register_Asm_32 :
5848 NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr, $Rm",
5849 (ins VecListOneDWordIndexed:$list, addrmode6:$addr,
5850 rGPR:$Rm, pred:$p)>;
5852 // VLD2 single-lane pseudo-instructions. These need special handling for
5853 // the lane index that an InstAlias can't handle, so we use these instead.
5854 def VLD2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr",
5855 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5856 def VLD2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr",
5857 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5858 def VLD2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr",
5859 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5860 def VLD2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr",
5861 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5862 def VLD2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr",
5863 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5865 def VLD2LNdWB_fixed_Asm_8 :
5866 NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr!",
5867 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5868 def VLD2LNdWB_fixed_Asm_16 :
5869 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!",
5870 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5871 def VLD2LNdWB_fixed_Asm_32 :
5872 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!",
5873 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5874 def VLD2LNqWB_fixed_Asm_16 :
5875 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!",
5876 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5877 def VLD2LNqWB_fixed_Asm_32 :
5878 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!",
5879 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5880 def VLD2LNdWB_register_Asm_8 :
5881 NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr, $Rm",
5882 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr,
5883 rGPR:$Rm, pred:$p)>;
5884 def VLD2LNdWB_register_Asm_16 :
5885 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm",
5886 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr,
5887 rGPR:$Rm, pred:$p)>;
5888 def VLD2LNdWB_register_Asm_32 :
5889 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm",
5890 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr,
5891 rGPR:$Rm, pred:$p)>;
5892 def VLD2LNqWB_register_Asm_16 :
5893 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm",
5894 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr,
5895 rGPR:$Rm, pred:$p)>;
5896 def VLD2LNqWB_register_Asm_32 :
5897 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm",
5898 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr,
5899 rGPR:$Rm, pred:$p)>;
5902 // VST2 single-lane pseudo-instructions. These need special handling for
5903 // the lane index that an InstAlias can't handle, so we use these instead.
5904 def VST2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr",
5905 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5906 def VST2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr",
5907 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5908 def VST2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr",
5909 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5910 def VST2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr",
5911 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5912 def VST2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr",
5913 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5915 def VST2LNdWB_fixed_Asm_8 :
5916 NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr!",
5917 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5918 def VST2LNdWB_fixed_Asm_16 :
5919 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!",
5920 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5921 def VST2LNdWB_fixed_Asm_32 :
5922 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!",
5923 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5924 def VST2LNqWB_fixed_Asm_16 :
5925 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!",
5926 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5927 def VST2LNqWB_fixed_Asm_32 :
5928 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!",
5929 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5930 def VST2LNdWB_register_Asm_8 :
5931 NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr, $Rm",
5932 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr,
5933 rGPR:$Rm, pred:$p)>;
5934 def VST2LNdWB_register_Asm_16 :
5935 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm",
5936 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr,
5937 rGPR:$Rm, pred:$p)>;
5938 def VST2LNdWB_register_Asm_32 :
5939 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm",
5940 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr,
5941 rGPR:$Rm, pred:$p)>;
5942 def VST2LNqWB_register_Asm_16 :
5943 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm",
5944 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr,
5945 rGPR:$Rm, pred:$p)>;
5946 def VST2LNqWB_register_Asm_32 :
5947 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm",
5948 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr,
5949 rGPR:$Rm, pred:$p)>;
5951 // VLD3 all-lanes pseudo-instructions. These need special handling for
5952 // the lane index that an InstAlias can't handle, so we use these instead.
5953 def VLD3DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
5954 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
5955 def VLD3DUPdAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
5956 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
5957 def VLD3DUPdAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
5958 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
5959 def VLD3DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
5960 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
5961 def VLD3DUPqAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
5962 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
5963 def VLD3DUPqAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
5964 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
5966 def VLD3DUPdWB_fixed_Asm_8 :
5967 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
5968 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
5969 def VLD3DUPdWB_fixed_Asm_16 :
5970 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
5971 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
5972 def VLD3DUPdWB_fixed_Asm_32 :
5973 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
5974 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
5975 def VLD3DUPqWB_fixed_Asm_8 :
5976 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
5977 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
5978 def VLD3DUPqWB_fixed_Asm_16 :
5979 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
5980 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
5981 def VLD3DUPqWB_fixed_Asm_32 :
5982 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
5983 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
5984 def VLD3DUPdWB_register_Asm_8 :
5985 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
5986 (ins VecListThreeDAllLanes:$list, addrmode6:$addr,
5987 rGPR:$Rm, pred:$p)>;
5988 def VLD3DUPdWB_register_Asm_16 :
5989 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
5990 (ins VecListThreeDAllLanes:$list, addrmode6:$addr,
5991 rGPR:$Rm, pred:$p)>;
5992 def VLD3DUPdWB_register_Asm_32 :
5993 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
5994 (ins VecListThreeDAllLanes:$list, addrmode6:$addr,
5995 rGPR:$Rm, pred:$p)>;
5996 def VLD3DUPqWB_register_Asm_8 :
5997 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
5998 (ins VecListThreeQAllLanes:$list, addrmode6:$addr,
5999 rGPR:$Rm, pred:$p)>;
6000 def VLD3DUPqWB_register_Asm_16 :
6001 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6002 (ins VecListThreeQAllLanes:$list, addrmode6:$addr,
6003 rGPR:$Rm, pred:$p)>;
6004 def VLD3DUPqWB_register_Asm_32 :
6005 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6006 (ins VecListThreeQAllLanes:$list, addrmode6:$addr,
6007 rGPR:$Rm, pred:$p)>;
6010 // VLD3 single-lane pseudo-instructions. These need special handling for
6011 // the lane index that an InstAlias can't handle, so we use these instead.
6012 def VLD3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6013 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6014 def VLD3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6015 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6016 def VLD3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6017 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6018 def VLD3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6019 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6020 def VLD3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6021 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6023 def VLD3LNdWB_fixed_Asm_8 :
6024 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6025 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6026 def VLD3LNdWB_fixed_Asm_16 :
6027 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6028 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6029 def VLD3LNdWB_fixed_Asm_32 :
6030 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6031 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6032 def VLD3LNqWB_fixed_Asm_16 :
6033 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6034 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6035 def VLD3LNqWB_fixed_Asm_32 :
6036 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6037 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6038 def VLD3LNdWB_register_Asm_8 :
6039 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6040 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr,
6041 rGPR:$Rm, pred:$p)>;
6042 def VLD3LNdWB_register_Asm_16 :
6043 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6044 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr,
6045 rGPR:$Rm, pred:$p)>;
6046 def VLD3LNdWB_register_Asm_32 :
6047 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6048 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr,
6049 rGPR:$Rm, pred:$p)>;
6050 def VLD3LNqWB_register_Asm_16 :
6051 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6052 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr,
6053 rGPR:$Rm, pred:$p)>;
6054 def VLD3LNqWB_register_Asm_32 :
6055 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6056 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr,
6057 rGPR:$Rm, pred:$p)>;
6059 // VLD3 multiple structure pseudo-instructions. These need special handling for
6060 // the vector operands that the normal instructions don't yet model.
6061 // FIXME: Remove these when the register classes and instructions are updated.
6062 def VLD3dAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6063 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6064 def VLD3dAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6065 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6066 def VLD3dAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6067 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6068 def VLD3qAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6069 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6070 def VLD3qAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6071 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6072 def VLD3qAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6073 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6075 def VLD3dWB_fixed_Asm_8 :
6076 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6077 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6078 def VLD3dWB_fixed_Asm_16 :
6079 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6080 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6081 def VLD3dWB_fixed_Asm_32 :
6082 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6083 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6084 def VLD3qWB_fixed_Asm_8 :
6085 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6086 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6087 def VLD3qWB_fixed_Asm_16 :
6088 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6089 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6090 def VLD3qWB_fixed_Asm_32 :
6091 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6092 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6093 def VLD3dWB_register_Asm_8 :
6094 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6095 (ins VecListThreeD:$list, addrmode6:$addr,
6096 rGPR:$Rm, pred:$p)>;
6097 def VLD3dWB_register_Asm_16 :
6098 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6099 (ins VecListThreeD:$list, addrmode6:$addr,
6100 rGPR:$Rm, pred:$p)>;
6101 def VLD3dWB_register_Asm_32 :
6102 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6103 (ins VecListThreeD:$list, addrmode6:$addr,
6104 rGPR:$Rm, pred:$p)>;
6105 def VLD3qWB_register_Asm_8 :
6106 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6107 (ins VecListThreeQ:$list, addrmode6:$addr,
6108 rGPR:$Rm, pred:$p)>;
6109 def VLD3qWB_register_Asm_16 :
6110 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6111 (ins VecListThreeQ:$list, addrmode6:$addr,
6112 rGPR:$Rm, pred:$p)>;
6113 def VLD3qWB_register_Asm_32 :
6114 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6115 (ins VecListThreeQ:$list, addrmode6:$addr,
6116 rGPR:$Rm, pred:$p)>;
6118 // VST3 single-lane pseudo-instructions. These need special handling for
6119 // the lane index that an InstAlias can't handle, so we use these instead.
6120 def VST3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6121 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6122 def VST3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6123 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6124 def VST3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6125 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6126 def VST3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6127 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6128 def VST3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6129 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6131 def VST3LNdWB_fixed_Asm_8 :
6132 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6133 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6134 def VST3LNdWB_fixed_Asm_16 :
6135 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6136 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6137 def VST3LNdWB_fixed_Asm_32 :
6138 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6139 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6140 def VST3LNqWB_fixed_Asm_16 :
6141 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6142 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6143 def VST3LNqWB_fixed_Asm_32 :
6144 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6145 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6146 def VST3LNdWB_register_Asm_8 :
6147 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6148 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr,
6149 rGPR:$Rm, pred:$p)>;
6150 def VST3LNdWB_register_Asm_16 :
6151 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6152 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr,
6153 rGPR:$Rm, pred:$p)>;
6154 def VST3LNdWB_register_Asm_32 :
6155 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6156 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr,
6157 rGPR:$Rm, pred:$p)>;
6158 def VST3LNqWB_register_Asm_16 :
6159 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6160 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr,
6161 rGPR:$Rm, pred:$p)>;
6162 def VST3LNqWB_register_Asm_32 :
6163 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6164 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr,
6165 rGPR:$Rm, pred:$p)>;
6168 // VST3 multiple structure pseudo-instructions. These need special handling for
6169 // the vector operands that the normal instructions don't yet model.
6170 // FIXME: Remove these when the register classes and instructions are updated.
6171 def VST3dAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6172 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6173 def VST3dAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6174 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6175 def VST3dAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6176 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6177 def VST3qAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6178 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6179 def VST3qAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6180 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6181 def VST3qAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6182 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6184 def VST3dWB_fixed_Asm_8 :
6185 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6186 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6187 def VST3dWB_fixed_Asm_16 :
6188 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6189 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6190 def VST3dWB_fixed_Asm_32 :
6191 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6192 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6193 def VST3qWB_fixed_Asm_8 :
6194 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6195 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6196 def VST3qWB_fixed_Asm_16 :
6197 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6198 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6199 def VST3qWB_fixed_Asm_32 :
6200 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6201 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6202 def VST3dWB_register_Asm_8 :
6203 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6204 (ins VecListThreeD:$list, addrmode6:$addr,
6205 rGPR:$Rm, pred:$p)>;
6206 def VST3dWB_register_Asm_16 :
6207 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6208 (ins VecListThreeD:$list, addrmode6:$addr,
6209 rGPR:$Rm, pred:$p)>;
6210 def VST3dWB_register_Asm_32 :
6211 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6212 (ins VecListThreeD:$list, addrmode6:$addr,
6213 rGPR:$Rm, pred:$p)>;
6214 def VST3qWB_register_Asm_8 :
6215 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6216 (ins VecListThreeQ:$list, addrmode6:$addr,
6217 rGPR:$Rm, pred:$p)>;
6218 def VST3qWB_register_Asm_16 :
6219 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6220 (ins VecListThreeQ:$list, addrmode6:$addr,
6221 rGPR:$Rm, pred:$p)>;
6222 def VST3qWB_register_Asm_32 :
6223 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6224 (ins VecListThreeQ:$list, addrmode6:$addr,
6225 rGPR:$Rm, pred:$p)>;
6227 // VLD4 all-lanes pseudo-instructions. These need special handling for
6228 // the lane index that an InstAlias can't handle, so we use these instead.
6229 def VLD4DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6230 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6231 def VLD4DUPdAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6232 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6233 def VLD4DUPdAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6234 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6235 def VLD4DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6236 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6237 def VLD4DUPqAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6238 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6239 def VLD4DUPqAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6240 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6242 def VLD4DUPdWB_fixed_Asm_8 :
6243 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6244 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6245 def VLD4DUPdWB_fixed_Asm_16 :
6246 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6247 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6248 def VLD4DUPdWB_fixed_Asm_32 :
6249 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6250 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6251 def VLD4DUPqWB_fixed_Asm_8 :
6252 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6253 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6254 def VLD4DUPqWB_fixed_Asm_16 :
6255 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6256 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6257 def VLD4DUPqWB_fixed_Asm_32 :
6258 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6259 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6260 def VLD4DUPdWB_register_Asm_8 :
6261 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6262 (ins VecListFourDAllLanes:$list, addrmode6:$addr,
6263 rGPR:$Rm, pred:$p)>;
6264 def VLD4DUPdWB_register_Asm_16 :
6265 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6266 (ins VecListFourDAllLanes:$list, addrmode6:$addr,
6267 rGPR:$Rm, pred:$p)>;
6268 def VLD4DUPdWB_register_Asm_32 :
6269 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6270 (ins VecListFourDAllLanes:$list, addrmode6:$addr,
6271 rGPR:$Rm, pred:$p)>;
6272 def VLD4DUPqWB_register_Asm_8 :
6273 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6274 (ins VecListFourQAllLanes:$list, addrmode6:$addr,
6275 rGPR:$Rm, pred:$p)>;
6276 def VLD4DUPqWB_register_Asm_16 :
6277 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6278 (ins VecListFourQAllLanes:$list, addrmode6:$addr,
6279 rGPR:$Rm, pred:$p)>;
6280 def VLD4DUPqWB_register_Asm_32 :
6281 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6282 (ins VecListFourQAllLanes:$list, addrmode6:$addr,
6283 rGPR:$Rm, pred:$p)>;
6286 // VLD4 single-lane pseudo-instructions. These need special handling for
6287 // the lane index that an InstAlias can't handle, so we use these instead.
6288 def VLD4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6289 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6290 def VLD4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6291 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6292 def VLD4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6293 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6294 def VLD4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6295 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6296 def VLD4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6297 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6299 def VLD4LNdWB_fixed_Asm_8 :
6300 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6301 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6302 def VLD4LNdWB_fixed_Asm_16 :
6303 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6304 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6305 def VLD4LNdWB_fixed_Asm_32 :
6306 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6307 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6308 def VLD4LNqWB_fixed_Asm_16 :
6309 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6310 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6311 def VLD4LNqWB_fixed_Asm_32 :
6312 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6313 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6314 def VLD4LNdWB_register_Asm_8 :
6315 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6316 (ins VecListFourDByteIndexed:$list, addrmode6:$addr,
6317 rGPR:$Rm, pred:$p)>;
6318 def VLD4LNdWB_register_Asm_16 :
6319 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6320 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr,
6321 rGPR:$Rm, pred:$p)>;
6322 def VLD4LNdWB_register_Asm_32 :
6323 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6324 (ins VecListFourDWordIndexed:$list, addrmode6:$addr,
6325 rGPR:$Rm, pred:$p)>;
6326 def VLD4LNqWB_register_Asm_16 :
6327 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6328 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr,
6329 rGPR:$Rm, pred:$p)>;
6330 def VLD4LNqWB_register_Asm_32 :
6331 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6332 (ins VecListFourQWordIndexed:$list, addrmode6:$addr,
6333 rGPR:$Rm, pred:$p)>;
6337 // VLD4 multiple structure pseudo-instructions. These need special handling for
6338 // the vector operands that the normal instructions don't yet model.
6339 // FIXME: Remove these when the register classes and instructions are updated.
6340 def VLD4dAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6341 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6342 def VLD4dAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6343 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6344 def VLD4dAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6345 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6346 def VLD4qAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6347 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6348 def VLD4qAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6349 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6350 def VLD4qAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6351 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6353 def VLD4dWB_fixed_Asm_8 :
6354 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6355 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6356 def VLD4dWB_fixed_Asm_16 :
6357 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6358 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6359 def VLD4dWB_fixed_Asm_32 :
6360 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6361 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6362 def VLD4qWB_fixed_Asm_8 :
6363 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6364 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6365 def VLD4qWB_fixed_Asm_16 :
6366 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6367 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6368 def VLD4qWB_fixed_Asm_32 :
6369 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6370 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6371 def VLD4dWB_register_Asm_8 :
6372 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6373 (ins VecListFourD:$list, addrmode6:$addr,
6374 rGPR:$Rm, pred:$p)>;
6375 def VLD4dWB_register_Asm_16 :
6376 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6377 (ins VecListFourD:$list, addrmode6:$addr,
6378 rGPR:$Rm, pred:$p)>;
6379 def VLD4dWB_register_Asm_32 :
6380 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6381 (ins VecListFourD:$list, addrmode6:$addr,
6382 rGPR:$Rm, pred:$p)>;
6383 def VLD4qWB_register_Asm_8 :
6384 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6385 (ins VecListFourQ:$list, addrmode6:$addr,
6386 rGPR:$Rm, pred:$p)>;
6387 def VLD4qWB_register_Asm_16 :
6388 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6389 (ins VecListFourQ:$list, addrmode6:$addr,
6390 rGPR:$Rm, pred:$p)>;
6391 def VLD4qWB_register_Asm_32 :
6392 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6393 (ins VecListFourQ:$list, addrmode6:$addr,
6394 rGPR:$Rm, pred:$p)>;
6396 // VST4 single-lane pseudo-instructions. These need special handling for
6397 // the lane index that an InstAlias can't handle, so we use these instead.
6398 def VST4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
6399 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6400 def VST4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
6401 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6402 def VST4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
6403 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6404 def VST4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
6405 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6406 def VST4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
6407 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6409 def VST4LNdWB_fixed_Asm_8 :
6410 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
6411 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6412 def VST4LNdWB_fixed_Asm_16 :
6413 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
6414 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6415 def VST4LNdWB_fixed_Asm_32 :
6416 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
6417 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6418 def VST4LNqWB_fixed_Asm_16 :
6419 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
6420 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6421 def VST4LNqWB_fixed_Asm_32 :
6422 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
6423 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6424 def VST4LNdWB_register_Asm_8 :
6425 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
6426 (ins VecListFourDByteIndexed:$list, addrmode6:$addr,
6427 rGPR:$Rm, pred:$p)>;
6428 def VST4LNdWB_register_Asm_16 :
6429 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
6430 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr,
6431 rGPR:$Rm, pred:$p)>;
6432 def VST4LNdWB_register_Asm_32 :
6433 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
6434 (ins VecListFourDWordIndexed:$list, addrmode6:$addr,
6435 rGPR:$Rm, pred:$p)>;
6436 def VST4LNqWB_register_Asm_16 :
6437 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
6438 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr,
6439 rGPR:$Rm, pred:$p)>;
6440 def VST4LNqWB_register_Asm_32 :
6441 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
6442 (ins VecListFourQWordIndexed:$list, addrmode6:$addr,
6443 rGPR:$Rm, pred:$p)>;
6446 // VST4 multiple structure pseudo-instructions. These need special handling for
6447 // the vector operands that the normal instructions don't yet model.
6448 // FIXME: Remove these when the register classes and instructions are updated.
6449 def VST4dAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
6450 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6451 def VST4dAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
6452 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6453 def VST4dAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
6454 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6455 def VST4qAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
6456 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6457 def VST4qAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
6458 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6459 def VST4qAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
6460 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6462 def VST4dWB_fixed_Asm_8 :
6463 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
6464 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6465 def VST4dWB_fixed_Asm_16 :
6466 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
6467 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6468 def VST4dWB_fixed_Asm_32 :
6469 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
6470 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6471 def VST4qWB_fixed_Asm_8 :
6472 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
6473 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6474 def VST4qWB_fixed_Asm_16 :
6475 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
6476 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6477 def VST4qWB_fixed_Asm_32 :
6478 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
6479 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6480 def VST4dWB_register_Asm_8 :
6481 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
6482 (ins VecListFourD:$list, addrmode6:$addr,
6483 rGPR:$Rm, pred:$p)>;
6484 def VST4dWB_register_Asm_16 :
6485 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
6486 (ins VecListFourD:$list, addrmode6:$addr,
6487 rGPR:$Rm, pred:$p)>;
6488 def VST4dWB_register_Asm_32 :
6489 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
6490 (ins VecListFourD:$list, addrmode6:$addr,
6491 rGPR:$Rm, pred:$p)>;
6492 def VST4qWB_register_Asm_8 :
6493 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
6494 (ins VecListFourQ:$list, addrmode6:$addr,
6495 rGPR:$Rm, pred:$p)>;
6496 def VST4qWB_register_Asm_16 :
6497 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
6498 (ins VecListFourQ:$list, addrmode6:$addr,
6499 rGPR:$Rm, pred:$p)>;
6500 def VST4qWB_register_Asm_32 :
6501 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
6502 (ins VecListFourQ:$list, addrmode6:$addr,
6503 rGPR:$Rm, pred:$p)>;
6505 // VMOV takes an optional datatype suffix
6506 defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
6507 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
6508 defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
6509 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
6511 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
6512 // D-register versions.
6513 def : NEONInstAlias<"vcle${p}.s8 $Dd, $Dn, $Dm",
6514 (VCGEsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6515 def : NEONInstAlias<"vcle${p}.s16 $Dd, $Dn, $Dm",
6516 (VCGEsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6517 def : NEONInstAlias<"vcle${p}.s32 $Dd, $Dn, $Dm",
6518 (VCGEsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6519 def : NEONInstAlias<"vcle${p}.u8 $Dd, $Dn, $Dm",
6520 (VCGEuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6521 def : NEONInstAlias<"vcle${p}.u16 $Dd, $Dn, $Dm",
6522 (VCGEuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6523 def : NEONInstAlias<"vcle${p}.u32 $Dd, $Dn, $Dm",
6524 (VCGEuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6525 def : NEONInstAlias<"vcle${p}.f32 $Dd, $Dn, $Dm",
6526 (VCGEfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6527 // Q-register versions.
6528 def : NEONInstAlias<"vcle${p}.s8 $Qd, $Qn, $Qm",
6529 (VCGEsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6530 def : NEONInstAlias<"vcle${p}.s16 $Qd, $Qn, $Qm",
6531 (VCGEsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6532 def : NEONInstAlias<"vcle${p}.s32 $Qd, $Qn, $Qm",
6533 (VCGEsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6534 def : NEONInstAlias<"vcle${p}.u8 $Qd, $Qn, $Qm",
6535 (VCGEuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6536 def : NEONInstAlias<"vcle${p}.u16 $Qd, $Qn, $Qm",
6537 (VCGEuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6538 def : NEONInstAlias<"vcle${p}.u32 $Qd, $Qn, $Qm",
6539 (VCGEuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6540 def : NEONInstAlias<"vcle${p}.f32 $Qd, $Qn, $Qm",
6541 (VCGEfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6543 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
6544 // D-register versions.
6545 def : NEONInstAlias<"vclt${p}.s8 $Dd, $Dn, $Dm",
6546 (VCGTsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6547 def : NEONInstAlias<"vclt${p}.s16 $Dd, $Dn, $Dm",
6548 (VCGTsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6549 def : NEONInstAlias<"vclt${p}.s32 $Dd, $Dn, $Dm",
6550 (VCGTsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6551 def : NEONInstAlias<"vclt${p}.u8 $Dd, $Dn, $Dm",
6552 (VCGTuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6553 def : NEONInstAlias<"vclt${p}.u16 $Dd, $Dn, $Dm",
6554 (VCGTuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6555 def : NEONInstAlias<"vclt${p}.u32 $Dd, $Dn, $Dm",
6556 (VCGTuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6557 def : NEONInstAlias<"vclt${p}.f32 $Dd, $Dn, $Dm",
6558 (VCGTfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6559 // Q-register versions.
6560 def : NEONInstAlias<"vclt${p}.s8 $Qd, $Qn, $Qm",
6561 (VCGTsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6562 def : NEONInstAlias<"vclt${p}.s16 $Qd, $Qn, $Qm",
6563 (VCGTsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6564 def : NEONInstAlias<"vclt${p}.s32 $Qd, $Qn, $Qm",
6565 (VCGTsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6566 def : NEONInstAlias<"vclt${p}.u8 $Qd, $Qn, $Qm",
6567 (VCGTuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6568 def : NEONInstAlias<"vclt${p}.u16 $Qd, $Qn, $Qm",
6569 (VCGTuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6570 def : NEONInstAlias<"vclt${p}.u32 $Qd, $Qn, $Qm",
6571 (VCGTuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6572 def : NEONInstAlias<"vclt${p}.f32 $Qd, $Qn, $Qm",
6573 (VCGTfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6575 // Two-operand variants for VEXT
6576 def : NEONInstAlias<"vext${p}.8 $Vdn, $Vm, $imm",
6577 (VEXTd8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_7:$imm, pred:$p)>;
6578 def : NEONInstAlias<"vext${p}.16 $Vdn, $Vm, $imm",
6579 (VEXTd16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_3:$imm, pred:$p)>;
6580 def : NEONInstAlias<"vext${p}.32 $Vdn, $Vm, $imm",
6581 (VEXTd32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_1:$imm, pred:$p)>;
6583 def : NEONInstAlias<"vext${p}.8 $Vdn, $Vm, $imm",
6584 (VEXTq8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_15:$imm, pred:$p)>;
6585 def : NEONInstAlias<"vext${p}.16 $Vdn, $Vm, $imm",
6586 (VEXTq16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_7:$imm, pred:$p)>;
6587 def : NEONInstAlias<"vext${p}.32 $Vdn, $Vm, $imm",
6588 (VEXTq32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_3:$imm, pred:$p)>;
6589 def : NEONInstAlias<"vext${p}.64 $Vdn, $Vm, $imm",
6590 (VEXTq64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_1:$imm, pred:$p)>;
6592 // Two-operand variants for VQDMULH
6593 def : NEONInstAlias<"vqdmulh${p}.s16 $Vdn, $Vm",
6594 (VQDMULHv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6595 def : NEONInstAlias<"vqdmulh${p}.s32 $Vdn, $Vm",
6596 (VQDMULHv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6598 def : NEONInstAlias<"vqdmulh${p}.s16 $Vdn, $Vm",
6599 (VQDMULHv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6600 def : NEONInstAlias<"vqdmulh${p}.s32 $Vdn, $Vm",
6601 (VQDMULHv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6603 // Two-operand variants for VSRA.
6605 def : NEONInstAlias<"vsra${p}.s8 $Vdm, $imm",
6606 (VSRAsv8i8 DPR:$Vdm, DPR:$Vdm, shr_imm8:$imm, pred:$p)>;
6607 def : NEONInstAlias<"vsra${p}.s16 $Vdm, $imm",
6608 (VSRAsv4i16 DPR:$Vdm, DPR:$Vdm, shr_imm16:$imm, pred:$p)>;
6609 def : NEONInstAlias<"vsra${p}.s32 $Vdm, $imm",
6610 (VSRAsv2i32 DPR:$Vdm, DPR:$Vdm, shr_imm32:$imm, pred:$p)>;
6611 def : NEONInstAlias<"vsra${p}.s64 $Vdm, $imm",
6612 (VSRAsv1i64 DPR:$Vdm, DPR:$Vdm, shr_imm64:$imm, pred:$p)>;
6614 def : NEONInstAlias<"vsra${p}.s8 $Vdm, $imm",
6615 (VSRAsv16i8 QPR:$Vdm, QPR:$Vdm, shr_imm8:$imm, pred:$p)>;
6616 def : NEONInstAlias<"vsra${p}.s16 $Vdm, $imm",
6617 (VSRAsv8i16 QPR:$Vdm, QPR:$Vdm, shr_imm16:$imm, pred:$p)>;
6618 def : NEONInstAlias<"vsra${p}.s32 $Vdm, $imm",
6619 (VSRAsv4i32 QPR:$Vdm, QPR:$Vdm, shr_imm32:$imm, pred:$p)>;
6620 def : NEONInstAlias<"vsra${p}.s64 $Vdm, $imm",
6621 (VSRAsv2i64 QPR:$Vdm, QPR:$Vdm, shr_imm64:$imm, pred:$p)>;
6624 def : NEONInstAlias<"vsra${p}.u8 $Vdm, $imm",
6625 (VSRAuv8i8 DPR:$Vdm, DPR:$Vdm, shr_imm8:$imm, pred:$p)>;
6626 def : NEONInstAlias<"vsra${p}.u16 $Vdm, $imm",
6627 (VSRAuv4i16 DPR:$Vdm, DPR:$Vdm, shr_imm16:$imm, pred:$p)>;
6628 def : NEONInstAlias<"vsra${p}.u32 $Vdm, $imm",
6629 (VSRAuv2i32 DPR:$Vdm, DPR:$Vdm, shr_imm32:$imm, pred:$p)>;
6630 def : NEONInstAlias<"vsra${p}.u64 $Vdm, $imm",
6631 (VSRAuv1i64 DPR:$Vdm, DPR:$Vdm, shr_imm64:$imm, pred:$p)>;
6633 def : NEONInstAlias<"vsra${p}.u8 $Vdm, $imm",
6634 (VSRAuv16i8 QPR:$Vdm, QPR:$Vdm, shr_imm8:$imm, pred:$p)>;
6635 def : NEONInstAlias<"vsra${p}.u16 $Vdm, $imm",
6636 (VSRAuv8i16 QPR:$Vdm, QPR:$Vdm, shr_imm16:$imm, pred:$p)>;
6637 def : NEONInstAlias<"vsra${p}.u32 $Vdm, $imm",
6638 (VSRAuv4i32 QPR:$Vdm, QPR:$Vdm, shr_imm32:$imm, pred:$p)>;
6639 def : NEONInstAlias<"vsra${p}.u64 $Vdm, $imm",
6640 (VSRAuv2i64 QPR:$Vdm, QPR:$Vdm, shr_imm64:$imm, pred:$p)>;
6642 // Two-operand variants for VSRI.
6643 def : NEONInstAlias<"vsri${p}.8 $Vdm, $imm",
6644 (VSRIv8i8 DPR:$Vdm, DPR:$Vdm, shr_imm8:$imm, pred:$p)>;
6645 def : NEONInstAlias<"vsri${p}.16 $Vdm, $imm",
6646 (VSRIv4i16 DPR:$Vdm, DPR:$Vdm, shr_imm16:$imm, pred:$p)>;
6647 def : NEONInstAlias<"vsri${p}.32 $Vdm, $imm",
6648 (VSRIv2i32 DPR:$Vdm, DPR:$Vdm, shr_imm32:$imm, pred:$p)>;
6649 def : NEONInstAlias<"vsri${p}.64 $Vdm, $imm",
6650 (VSRIv1i64 DPR:$Vdm, DPR:$Vdm, shr_imm64:$imm, pred:$p)>;
6652 def : NEONInstAlias<"vsri${p}.8 $Vdm, $imm",
6653 (VSRIv16i8 QPR:$Vdm, QPR:$Vdm, shr_imm8:$imm, pred:$p)>;
6654 def : NEONInstAlias<"vsri${p}.16 $Vdm, $imm",
6655 (VSRIv8i16 QPR:$Vdm, QPR:$Vdm, shr_imm16:$imm, pred:$p)>;
6656 def : NEONInstAlias<"vsri${p}.32 $Vdm, $imm",
6657 (VSRIv4i32 QPR:$Vdm, QPR:$Vdm, shr_imm32:$imm, pred:$p)>;
6658 def : NEONInstAlias<"vsri${p}.64 $Vdm, $imm",
6659 (VSRIv2i64 QPR:$Vdm, QPR:$Vdm, shr_imm64:$imm, pred:$p)>;
6661 // Two-operand variants for VSLI.
6662 def : NEONInstAlias<"vsli${p}.8 $Vdm, $imm",
6663 (VSLIv8i8 DPR:$Vdm, DPR:$Vdm, shr_imm8:$imm, pred:$p)>;
6664 def : NEONInstAlias<"vsli${p}.16 $Vdm, $imm",
6665 (VSLIv4i16 DPR:$Vdm, DPR:$Vdm, shr_imm16:$imm, pred:$p)>;
6666 def : NEONInstAlias<"vsli${p}.32 $Vdm, $imm",
6667 (VSLIv2i32 DPR:$Vdm, DPR:$Vdm, shr_imm32:$imm, pred:$p)>;
6668 def : NEONInstAlias<"vsli${p}.64 $Vdm, $imm",
6669 (VSLIv1i64 DPR:$Vdm, DPR:$Vdm, shr_imm64:$imm, pred:$p)>;
6671 def : NEONInstAlias<"vsli${p}.8 $Vdm, $imm",
6672 (VSLIv16i8 QPR:$Vdm, QPR:$Vdm, shr_imm8:$imm, pred:$p)>;
6673 def : NEONInstAlias<"vsli${p}.16 $Vdm, $imm",
6674 (VSLIv8i16 QPR:$Vdm, QPR:$Vdm, shr_imm16:$imm, pred:$p)>;
6675 def : NEONInstAlias<"vsli${p}.32 $Vdm, $imm",
6676 (VSLIv4i32 QPR:$Vdm, QPR:$Vdm, shr_imm32:$imm, pred:$p)>;
6677 def : NEONInstAlias<"vsli${p}.64 $Vdm, $imm",
6678 (VSLIv2i64 QPR:$Vdm, QPR:$Vdm, shr_imm64:$imm, pred:$p)>;
6680 // VSWP allows, but does not require, a type suffix.
6681 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
6682 (VSWPd DPR:$Vd, DPR:$Vm, pred:$p)>;
6683 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
6684 (VSWPq QPR:$Vd, QPR:$Vm, pred:$p)>;
6686 // VBIF, VBIT, and VBSL allow, but do not require, a type suffix.
6687 defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm",
6688 (VBIFd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6689 defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm",
6690 (VBITd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6691 defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm",
6692 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6693 defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm",
6694 (VBIFq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6695 defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm",
6696 (VBITq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6697 defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm",
6698 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6700 // "vmov Rd, #-imm" can be handled via "vmvn".
6701 def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
6702 (VMVNv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
6703 def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
6704 (VMVNv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
6705 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
6706 (VMOVv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
6707 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
6708 (VMOVv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
6710 // 'gas' compatibility aliases for quad-word instructions. Strictly speaking,
6711 // these should restrict to just the Q register variants, but the register
6712 // classes are enough to match correctly regardless, so we keep it simple
6713 // and just use MnemonicAlias.
6714 def : NEONMnemonicAlias<"vbicq", "vbic">;
6715 def : NEONMnemonicAlias<"vandq", "vand">;
6716 def : NEONMnemonicAlias<"veorq", "veor">;
6717 def : NEONMnemonicAlias<"vorrq", "vorr">;
6719 def : NEONMnemonicAlias<"vmovq", "vmov">;
6720 def : NEONMnemonicAlias<"vmvnq", "vmvn">;
6721 // Explicit versions for floating point so that the FPImm variants get
6722 // handled early. The parser gets confused otherwise.
6723 def : NEONMnemonicAlias<"vmovq.f32", "vmov.f32">;
6724 def : NEONMnemonicAlias<"vmovq.f64", "vmov.f64">;
6726 def : NEONMnemonicAlias<"vaddq", "vadd">;
6727 def : NEONMnemonicAlias<"vsubq", "vsub">;
6729 def : NEONMnemonicAlias<"vminq", "vmin">;
6730 def : NEONMnemonicAlias<"vmaxq", "vmax">;
6732 def : NEONMnemonicAlias<"vmulq", "vmul">;
6734 def : NEONMnemonicAlias<"vabsq", "vabs">;
6736 def : NEONMnemonicAlias<"vshlq", "vshl">;
6737 def : NEONMnemonicAlias<"vshrq", "vshr">;
6739 def : NEONMnemonicAlias<"vcvtq", "vcvt">;
6741 def : NEONMnemonicAlias<"vcleq", "vcle">;
6742 def : NEONMnemonicAlias<"vceqq", "vceq">;
6744 def : NEONMnemonicAlias<"vzipq", "vzip">;
6745 def : NEONMnemonicAlias<"vswpq", "vswp">;
6747 def : NEONMnemonicAlias<"vrecpeq.f32", "vrecpe.f32">;
6748 def : NEONMnemonicAlias<"vrecpeq.u32", "vrecpe.u32">;
6751 // Alias for loading floating point immediates that aren't representable
6752 // using the vmov.f32 encoding but the bitpattern is representable using
6753 // the .i32 encoding.
6754 def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
6755 (VMOVv4i32 QPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;
6756 def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
6757 (VMOVv2i32 DPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;