1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
70 // VDUPLANE can produce a quad-register result from a double-register source,
71 // so the result is not constrained to match the source.
72 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
73 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
76 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
77 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
78 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
80 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
81 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
82 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
83 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
85 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
86 SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>]>;
87 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
88 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
89 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
91 //===----------------------------------------------------------------------===//
92 // NEON operand definitions
93 //===----------------------------------------------------------------------===//
95 // addrmode_neonldstm := reg
97 /* TODO: Take advantage of vldm.
98 def addrmode_neonldstm : Operand<i32>,
99 ComplexPattern<i32, 2, "SelectAddrModeNeonLdStM", []> {
100 let PrintMethod = "printAddrNeonLdStMOperand";
101 let MIOperandInfo = (ops GPR, i32imm);
105 //===----------------------------------------------------------------------===//
106 // NEON load / store instructions
107 //===----------------------------------------------------------------------===//
109 /* TODO: Take advantage of vldm.
111 def VLDMD : NI<(outs),
112 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
114 "vldm${addr:submode} ${addr:base}, $dst1",
116 let Inst{27-25} = 0b110;
118 let Inst{11-9} = 0b101;
121 def VLDMS : NI<(outs),
122 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
124 "vldm${addr:submode} ${addr:base}, $dst1",
126 let Inst{27-25} = 0b110;
128 let Inst{11-9} = 0b101;
133 // Use vldmia to load a Q register as a D register pair.
134 def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr),
136 "vldmia $addr, ${dst:dregpair}",
137 [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]> {
138 let Inst{27-25} = 0b110;
139 let Inst{24} = 0; // P bit
140 let Inst{23} = 1; // U bit
142 let Inst{11-9} = 0b101;
145 // Use vstmia to store a Q register as a D register pair.
146 def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr),
148 "vstmia $addr, ${src:dregpair}",
149 [(store (v2f64 QPR:$src), addrmode4:$addr)]> {
150 let Inst{27-25} = 0b110;
151 let Inst{24} = 0; // P bit
152 let Inst{23} = 1; // U bit
154 let Inst{11-9} = 0b101;
157 // VLD1 : Vector Load (multiple single elements)
158 class VLD1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
159 : NLdSt<(outs DPR:$dst), (ins addrmode6:$addr), NoItinerary,
160 !strconcat(OpcodeStr, "\t\\{$dst\\}, $addr"), "",
161 [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
162 class VLD1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
163 : NLdSt<(outs QPR:$dst), (ins addrmode6:$addr), NoItinerary,
164 !strconcat(OpcodeStr, "\t${dst:dregpair}, $addr"), "",
165 [(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
167 def VLD1d8 : VLD1D<"vld1.8", v8i8, int_arm_neon_vld1>;
168 def VLD1d16 : VLD1D<"vld1.16", v4i16, int_arm_neon_vld1>;
169 def VLD1d32 : VLD1D<"vld1.32", v2i32, int_arm_neon_vld1>;
170 def VLD1df : VLD1D<"vld1.32", v2f32, int_arm_neon_vld1>;
171 def VLD1d64 : VLD1D<"vld1.64", v1i64, int_arm_neon_vld1>;
173 def VLD1q8 : VLD1Q<"vld1.8", v16i8, int_arm_neon_vld1>;
174 def VLD1q16 : VLD1Q<"vld1.16", v8i16, int_arm_neon_vld1>;
175 def VLD1q32 : VLD1Q<"vld1.32", v4i32, int_arm_neon_vld1>;
176 def VLD1qf : VLD1Q<"vld1.32", v4f32, int_arm_neon_vld1>;
177 def VLD1q64 : VLD1Q<"vld1.64", v2i64, int_arm_neon_vld1>;
181 // VLD2 : Vector Load (multiple 2-element structures)
182 class VLD2D<string OpcodeStr>
183 : NLdSt<(outs DPR:$dst1, DPR:$dst2), (ins addrmode6:$addr), NoItinerary,
184 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2\\}, $addr"), "", []>;
186 def VLD2d8 : VLD2D<"vld2.8">;
187 def VLD2d16 : VLD2D<"vld2.16">;
188 def VLD2d32 : VLD2D<"vld2.32">;
190 // VLD3 : Vector Load (multiple 3-element structures)
191 class VLD3D<string OpcodeStr>
192 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3), (ins addrmode6:$addr),
194 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"), "", []>;
196 def VLD3d8 : VLD3D<"vld3.8">;
197 def VLD3d16 : VLD3D<"vld3.16">;
198 def VLD3d32 : VLD3D<"vld3.32">;
200 // VLD4 : Vector Load (multiple 4-element structures)
201 class VLD4D<string OpcodeStr>
202 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
203 (ins addrmode6:$addr), NoItinerary,
204 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"),
207 def VLD4d8 : VLD4D<"vld4.8">;
208 def VLD4d16 : VLD4D<"vld4.16">;
209 def VLD4d32 : VLD4D<"vld4.32">;
211 // VLD2LN : Vector Load (single 2-element structure to one lane)
212 class VLD2LND<string OpcodeStr>
213 : NLdSt<(outs DPR:$dst1, DPR:$dst2),
214 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
216 !strconcat(OpcodeStr, "\t\\{$dst1[$lane],$dst2[$lane]\\}, $addr"),
217 "$src1 = $dst1, $src2 = $dst2", []>;
219 def VLD2LNd8 : VLD2LND<"vld2.8">;
220 def VLD2LNd16 : VLD2LND<"vld2.16">;
221 def VLD2LNd32 : VLD2LND<"vld2.32">;
223 // VLD3LN : Vector Load (single 3-element structure to one lane)
224 class VLD3LND<string OpcodeStr>
225 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
226 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
227 nohash_imm:$lane), NoItinerary,
228 !strconcat(OpcodeStr,
229 "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane]\\}, $addr"),
230 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
232 def VLD3LNd8 : VLD3LND<"vld3.8">;
233 def VLD3LNd16 : VLD3LND<"vld3.16">;
234 def VLD3LNd32 : VLD3LND<"vld3.32">;
236 // VLD4LN : Vector Load (single 4-element structure to one lane)
237 class VLD4LND<string OpcodeStr>
238 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
239 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
240 nohash_imm:$lane), NoItinerary,
241 !strconcat(OpcodeStr,
242 "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane],$dst4[$lane]\\}, $addr"),
243 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
245 def VLD4LNd8 : VLD4LND<"vld4.8">;
246 def VLD4LNd16 : VLD4LND<"vld4.16">;
247 def VLD4LNd32 : VLD4LND<"vld4.32">;
250 // VST1 : Vector Store (multiple single elements)
251 class VST1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
252 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src), NoItinerary,
253 !strconcat(OpcodeStr, "\t\\{$src\\}, $addr"), "",
254 [(IntOp addrmode6:$addr, (Ty DPR:$src))]>;
255 class VST1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
256 : NLdSt<(outs), (ins addrmode6:$addr, QPR:$src), NoItinerary,
257 !strconcat(OpcodeStr, "\t${src:dregpair}, $addr"), "",
258 [(IntOp addrmode6:$addr, (Ty QPR:$src))]>;
260 def VST1d8 : VST1D<"vst1.8", v8i8, int_arm_neon_vst1>;
261 def VST1d16 : VST1D<"vst1.16", v4i16, int_arm_neon_vst1>;
262 def VST1d32 : VST1D<"vst1.32", v2i32, int_arm_neon_vst1>;
263 def VST1df : VST1D<"vst1.32", v2f32, int_arm_neon_vst1>;
264 def VST1d64 : VST1D<"vst1.64", v1i64, int_arm_neon_vst1>;
266 def VST1q8 : VST1Q<"vst1.8", v16i8, int_arm_neon_vst1>;
267 def VST1q16 : VST1Q<"vst1.16", v8i16, int_arm_neon_vst1>;
268 def VST1q32 : VST1Q<"vst1.32", v4i32, int_arm_neon_vst1>;
269 def VST1qf : VST1Q<"vst1.32", v4f32, int_arm_neon_vst1>;
270 def VST1q64 : VST1Q<"vst1.64", v2i64, int_arm_neon_vst1>;
272 let mayStore = 1 in {
274 // VST2 : Vector Store (multiple 2-element structures)
275 class VST2D<string OpcodeStr>
276 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2), NoItinerary,
277 !strconcat(OpcodeStr, "\t\\{$src1,$src2\\}, $addr"), "", []>;
279 def VST2d8 : VST2D<"vst2.8">;
280 def VST2d16 : VST2D<"vst2.16">;
281 def VST2d32 : VST2D<"vst2.32">;
283 // VST3 : Vector Store (multiple 3-element structures)
284 class VST3D<string OpcodeStr>
285 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
287 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"), "", []>;
289 def VST3d8 : VST3D<"vst3.8">;
290 def VST3d16 : VST3D<"vst3.16">;
291 def VST3d32 : VST3D<"vst3.32">;
293 // VST4 : Vector Store (multiple 4-element structures)
294 class VST4D<string OpcodeStr>
295 : NLdSt<(outs), (ins addrmode6:$addr,
296 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), NoItinerary,
297 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"),
300 def VST4d8 : VST4D<"vst4.8">;
301 def VST4d16 : VST4D<"vst4.16">;
302 def VST4d32 : VST4D<"vst4.32">;
306 //===----------------------------------------------------------------------===//
307 // NEON pattern fragments
308 //===----------------------------------------------------------------------===//
310 // Extract D sub-registers of Q registers.
311 // (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
312 def DSubReg_i8_reg : SDNodeXForm<imm, [{
313 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
315 def DSubReg_i16_reg : SDNodeXForm<imm, [{
316 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
318 def DSubReg_i32_reg : SDNodeXForm<imm, [{
319 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
321 def DSubReg_f64_reg : SDNodeXForm<imm, [{
322 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
325 // Extract S sub-registers of Q/D registers.
326 // (arm_ssubreg_0 is 1; arm_ssubreg_1 is 2; etc.)
327 def SSubReg_f32_reg : SDNodeXForm<imm, [{
328 return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32);
331 // Translate lane numbers from Q registers to D subregs.
332 def SubReg_i8_lane : SDNodeXForm<imm, [{
333 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
335 def SubReg_i16_lane : SDNodeXForm<imm, [{
336 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
338 def SubReg_i32_lane : SDNodeXForm<imm, [{
339 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
342 //===----------------------------------------------------------------------===//
343 // Instruction Classes
344 //===----------------------------------------------------------------------===//
346 // Basic 2-register operations, both double- and quad-register.
347 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
348 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
349 ValueType ResTy, ValueType OpTy, SDNode OpNode>
350 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
351 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
352 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
353 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
354 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
355 ValueType ResTy, ValueType OpTy, SDNode OpNode>
356 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
357 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
358 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
360 // Basic 2-register operations, scalar single-precision.
361 class N2VDs<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
362 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
363 ValueType ResTy, ValueType OpTy, SDNode OpNode>
364 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
365 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
366 NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
368 class N2VDsPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
369 : NEONFPPat<(ResTy (OpNode SPR:$a)),
371 (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
374 // Basic 2-register intrinsics, both double- and quad-register.
375 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
376 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
377 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
378 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
379 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
380 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
381 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
382 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
383 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
384 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
385 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
386 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
388 // Basic 2-register intrinsics, scalar single-precision
389 class N2VDInts<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
390 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
391 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
392 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
393 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NoItinerary,
394 !strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
396 class N2VDIntsPat<SDNode OpNode, NeonI Inst>
397 : NEONFPPat<(f32 (OpNode SPR:$a)),
399 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
402 // Narrow 2-register intrinsics.
403 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
404 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
405 string OpcodeStr, ValueType TyD, ValueType TyQ, Intrinsic IntOp>
406 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
407 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
408 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
410 // Long 2-register intrinsics. (This is currently only used for VMOVL and is
411 // derived from N2VImm instead of N2V because of the way the size is encoded.)
412 class N2VLInt<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
413 bit op6, bit op4, string OpcodeStr, ValueType TyQ, ValueType TyD,
415 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4, (outs QPR:$dst),
416 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
417 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
419 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
420 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr>
421 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
422 (ins DPR:$src1, DPR:$src2), NoItinerary,
423 !strconcat(OpcodeStr, "\t$dst1, $dst2"),
424 "$src1 = $dst1, $src2 = $dst2", []>;
425 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr>
426 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
427 (ins QPR:$src1, QPR:$src2), NoItinerary,
428 !strconcat(OpcodeStr, "\t$dst1, $dst2"),
429 "$src1 = $dst1, $src2 = $dst2", []>;
431 // Basic 3-register operations, both double- and quad-register.
432 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
433 string OpcodeStr, ValueType ResTy, ValueType OpTy,
434 SDNode OpNode, bit Commutable>
435 : N3V<op24, op23, op21_20, op11_8, 0, op4,
436 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
437 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
438 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
439 let isCommutable = Commutable;
441 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
442 string OpcodeStr, ValueType ResTy, ValueType OpTy,
443 SDNode OpNode, bit Commutable>
444 : N3V<op24, op23, op21_20, op11_8, 1, op4,
445 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
446 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
447 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
448 let isCommutable = Commutable;
451 // Basic 3-register operations, scalar single-precision
452 class N3VDs<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
453 string OpcodeStr, ValueType ResTy, ValueType OpTy,
454 SDNode OpNode, bit Commutable>
455 : N3V<op24, op23, op21_20, op11_8, 0, op4,
456 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), NoItinerary,
457 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", []> {
458 let isCommutable = Commutable;
460 class N3VDsPat<SDNode OpNode, NeonI Inst>
461 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
463 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
464 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
467 // Basic 3-register intrinsics, both double- and quad-register.
468 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
469 string OpcodeStr, ValueType ResTy, ValueType OpTy,
470 Intrinsic IntOp, bit Commutable>
471 : N3V<op24, op23, op21_20, op11_8, 0, op4,
472 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
473 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
474 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
475 let isCommutable = Commutable;
477 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
478 string OpcodeStr, ValueType ResTy, ValueType OpTy,
479 Intrinsic IntOp, bit Commutable>
480 : N3V<op24, op23, op21_20, op11_8, 1, op4,
481 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
482 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
483 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
484 let isCommutable = Commutable;
487 // Multiply-Add/Sub operations, both double- and quad-register.
488 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
489 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
490 : N3V<op24, op23, op21_20, op11_8, 0, op4,
491 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
492 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
493 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
494 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
495 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
496 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
497 : N3V<op24, op23, op21_20, op11_8, 1, op4,
498 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
499 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
500 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
501 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
503 // Multiply-Add/Sub operations, scalar single-precision
504 class N3VDMulOps<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
505 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
506 : N3V<op24, op23, op21_20, op11_8, 0, op4,
507 (outs DPR_VFP2:$dst),
508 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), NoItinerary,
509 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", []>;
511 class N3VDMulOpsPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
512 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
514 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$acc, arm_ssubreg_0),
515 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
516 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
519 // Neon 3-argument intrinsics, both double- and quad-register.
520 // The destination register is also used as the first source operand register.
521 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
522 string OpcodeStr, ValueType ResTy, ValueType OpTy,
524 : N3V<op24, op23, op21_20, op11_8, 0, op4,
525 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
526 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
527 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
528 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
529 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
530 string OpcodeStr, ValueType ResTy, ValueType OpTy,
532 : N3V<op24, op23, op21_20, op11_8, 1, op4,
533 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
534 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
535 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
536 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
538 // Neon Long 3-argument intrinsic. The destination register is
539 // a quad-register and is also used as the first source operand register.
540 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
541 string OpcodeStr, ValueType TyQ, ValueType TyD, Intrinsic IntOp>
542 : N3V<op24, op23, op21_20, op11_8, 0, op4,
543 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
544 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
546 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
548 // Narrowing 3-register intrinsics.
549 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
550 string OpcodeStr, ValueType TyD, ValueType TyQ,
551 Intrinsic IntOp, bit Commutable>
552 : N3V<op24, op23, op21_20, op11_8, 0, op4,
553 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
554 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
555 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
556 let isCommutable = Commutable;
559 // Long 3-register intrinsics.
560 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
561 string OpcodeStr, ValueType TyQ, ValueType TyD,
562 Intrinsic IntOp, bit Commutable>
563 : N3V<op24, op23, op21_20, op11_8, 0, op4,
564 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
565 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
566 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
567 let isCommutable = Commutable;
570 // Wide 3-register intrinsics.
571 class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
572 string OpcodeStr, ValueType TyQ, ValueType TyD,
573 Intrinsic IntOp, bit Commutable>
574 : N3V<op24, op23, op21_20, op11_8, 0, op4,
575 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), NoItinerary,
576 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
577 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
578 let isCommutable = Commutable;
581 // Pairwise long 2-register intrinsics, both double- and quad-register.
582 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
583 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
584 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
585 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
586 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
587 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
588 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
589 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
590 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
591 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
592 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
593 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
595 // Pairwise long 2-register accumulate intrinsics,
596 // both double- and quad-register.
597 // The destination register is also used as the first source operand register.
598 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
599 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
600 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
601 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
602 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
603 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
604 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
605 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
606 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
607 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
608 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
609 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
610 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
611 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
613 // Shift by immediate,
614 // both double- and quad-register.
615 class N2VDSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
616 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
617 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
618 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
619 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
620 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
621 class N2VQSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
622 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
623 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
624 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
625 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
626 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
628 // Long shift by immediate.
629 class N2VLSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
630 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
631 ValueType OpTy, SDNode OpNode>
632 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
633 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
634 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
635 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
636 (i32 imm:$SIMM))))]>;
638 // Narrow shift by immediate.
639 class N2VNSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
640 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
641 ValueType OpTy, SDNode OpNode>
642 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
643 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
644 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
645 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
646 (i32 imm:$SIMM))))]>;
648 // Shift right by immediate and accumulate,
649 // both double- and quad-register.
650 class N2VDShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
651 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
652 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
653 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
655 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
656 [(set DPR:$dst, (Ty (add DPR:$src1,
657 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
658 class N2VQShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
659 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
660 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
661 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
663 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
664 [(set QPR:$dst, (Ty (add QPR:$src1,
665 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
667 // Shift by immediate and insert,
668 // both double- and quad-register.
669 class N2VDShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
670 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
671 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
672 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
674 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
675 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
676 class N2VQShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
677 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
678 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
679 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
681 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
682 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
684 // Convert, with fractional bits immediate,
685 // both double- and quad-register.
686 class N2VCvtD<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
687 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
689 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
690 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
691 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
692 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
693 class N2VCvtQ<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
694 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
696 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
697 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
698 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
699 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
701 //===----------------------------------------------------------------------===//
703 //===----------------------------------------------------------------------===//
705 // Neon 3-register vector operations.
707 // First with only element sizes of 8, 16 and 32 bits:
708 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
709 string OpcodeStr, SDNode OpNode, bit Commutable = 0> {
710 // 64-bit vector types.
711 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
712 v8i8, v8i8, OpNode, Commutable>;
713 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
714 v4i16, v4i16, OpNode, Commutable>;
715 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
716 v2i32, v2i32, OpNode, Commutable>;
718 // 128-bit vector types.
719 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
720 v16i8, v16i8, OpNode, Commutable>;
721 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
722 v8i16, v8i16, OpNode, Commutable>;
723 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
724 v4i32, v4i32, OpNode, Commutable>;
727 // ....then also with element size 64 bits:
728 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
729 string OpcodeStr, SDNode OpNode, bit Commutable = 0>
730 : N3V_QHS<op24, op23, op11_8, op4, OpcodeStr, OpNode, Commutable> {
731 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
732 v1i64, v1i64, OpNode, Commutable>;
733 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
734 v2i64, v2i64, OpNode, Commutable>;
738 // Neon Narrowing 2-register vector intrinsics,
739 // source operand element sizes of 16, 32 and 64 bits:
740 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
741 bits<5> op11_7, bit op6, bit op4, string OpcodeStr,
743 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
744 !strconcat(OpcodeStr, "16"), v8i8, v8i16, IntOp>;
745 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
746 !strconcat(OpcodeStr, "32"), v4i16, v4i32, IntOp>;
747 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
748 !strconcat(OpcodeStr, "64"), v2i32, v2i64, IntOp>;
752 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
753 // source operand element sizes of 16, 32 and 64 bits:
754 multiclass N2VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
755 bit op4, string OpcodeStr, Intrinsic IntOp> {
756 def v8i16 : N2VLInt<op24, op23, 0b001000, op11_8, op7, op6, op4,
757 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
758 def v4i32 : N2VLInt<op24, op23, 0b010000, op11_8, op7, op6, op4,
759 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
760 def v2i64 : N2VLInt<op24, op23, 0b100000, op11_8, op7, op6, op4,
761 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
765 // Neon 3-register vector intrinsics.
767 // First with only element sizes of 16 and 32 bits:
768 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
769 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
770 // 64-bit vector types.
771 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
772 v4i16, v4i16, IntOp, Commutable>;
773 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
774 v2i32, v2i32, IntOp, Commutable>;
776 // 128-bit vector types.
777 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
778 v8i16, v8i16, IntOp, Commutable>;
779 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
780 v4i32, v4i32, IntOp, Commutable>;
783 // ....then also with element size of 8 bits:
784 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
785 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
786 : N3VInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
787 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
788 v8i8, v8i8, IntOp, Commutable>;
789 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
790 v16i8, v16i8, IntOp, Commutable>;
793 // ....then also with element size of 64 bits:
794 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
795 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
796 : N3VInt_QHS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
797 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
798 v1i64, v1i64, IntOp, Commutable>;
799 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
800 v2i64, v2i64, IntOp, Commutable>;
804 // Neon Narrowing 3-register vector intrinsics,
805 // source operand element sizes of 16, 32 and 64 bits:
806 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
807 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
808 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr,"16"),
809 v8i8, v8i16, IntOp, Commutable>;
810 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"32"),
811 v4i16, v4i32, IntOp, Commutable>;
812 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"64"),
813 v2i32, v2i64, IntOp, Commutable>;
817 // Neon Long 3-register vector intrinsics.
819 // First with only element sizes of 16 and 32 bits:
820 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
821 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
822 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
823 v4i32, v4i16, IntOp, Commutable>;
824 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
825 v2i64, v2i32, IntOp, Commutable>;
828 // ....then also with element size of 8 bits:
829 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
830 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
831 : N3VLInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
832 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
833 v8i16, v8i8, IntOp, Commutable>;
837 // Neon Wide 3-register vector intrinsics,
838 // source operand element sizes of 8, 16 and 32 bits:
839 multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
840 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
841 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
842 v8i16, v8i8, IntOp, Commutable>;
843 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
844 v4i32, v4i16, IntOp, Commutable>;
845 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
846 v2i64, v2i32, IntOp, Commutable>;
850 // Neon Multiply-Op vector operations,
851 // element sizes of 8, 16 and 32 bits:
852 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
853 string OpcodeStr, SDNode OpNode> {
854 // 64-bit vector types.
855 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4,
856 !strconcat(OpcodeStr, "8"), v8i8, mul, OpNode>;
857 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4,
858 !strconcat(OpcodeStr, "16"), v4i16, mul, OpNode>;
859 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4,
860 !strconcat(OpcodeStr, "32"), v2i32, mul, OpNode>;
862 // 128-bit vector types.
863 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4,
864 !strconcat(OpcodeStr, "8"), v16i8, mul, OpNode>;
865 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4,
866 !strconcat(OpcodeStr, "16"), v8i16, mul, OpNode>;
867 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4,
868 !strconcat(OpcodeStr, "32"), v4i32, mul, OpNode>;
872 // Neon 3-argument intrinsics,
873 // element sizes of 8, 16 and 32 bits:
874 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
875 string OpcodeStr, Intrinsic IntOp> {
876 // 64-bit vector types.
877 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4,
878 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
879 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4,
880 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
881 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4,
882 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
884 // 128-bit vector types.
885 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4,
886 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
887 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4,
888 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
889 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4,
890 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
894 // Neon Long 3-argument intrinsics.
896 // First with only element sizes of 16 and 32 bits:
897 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
898 string OpcodeStr, Intrinsic IntOp> {
899 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
900 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
901 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4,
902 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
905 // ....then also with element size of 8 bits:
906 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
907 string OpcodeStr, Intrinsic IntOp>
908 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp> {
909 def v8i16 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
910 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
914 // Neon 2-register vector intrinsics,
915 // element sizes of 8, 16 and 32 bits:
916 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
917 bits<5> op11_7, bit op4, string OpcodeStr,
919 // 64-bit vector types.
920 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
921 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
922 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
923 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
924 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
925 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
927 // 128-bit vector types.
928 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
929 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
930 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
931 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
932 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
933 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
937 // Neon Pairwise long 2-register intrinsics,
938 // element sizes of 8, 16 and 32 bits:
939 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
940 bits<5> op11_7, bit op4,
941 string OpcodeStr, Intrinsic IntOp> {
942 // 64-bit vector types.
943 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
944 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
945 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
946 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
947 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
948 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
950 // 128-bit vector types.
951 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
952 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
953 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
954 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
955 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
956 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
960 // Neon Pairwise long 2-register accumulate intrinsics,
961 // element sizes of 8, 16 and 32 bits:
962 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
963 bits<5> op11_7, bit op4,
964 string OpcodeStr, Intrinsic IntOp> {
965 // 64-bit vector types.
966 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
967 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
968 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
969 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
970 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
971 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
973 // 128-bit vector types.
974 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
975 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
976 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
977 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
978 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
979 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
983 // Neon 2-register vector shift by immediate,
984 // element sizes of 8, 16, 32 and 64 bits:
985 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
986 string OpcodeStr, SDNode OpNode> {
987 // 64-bit vector types.
988 def v8i8 : N2VDSh<op24, op23, 0b001000, op11_8, 0, op4,
989 !strconcat(OpcodeStr, "8"), v8i8, OpNode>;
990 def v4i16 : N2VDSh<op24, op23, 0b010000, op11_8, 0, op4,
991 !strconcat(OpcodeStr, "16"), v4i16, OpNode>;
992 def v2i32 : N2VDSh<op24, op23, 0b100000, op11_8, 0, op4,
993 !strconcat(OpcodeStr, "32"), v2i32, OpNode>;
994 def v1i64 : N2VDSh<op24, op23, 0b000000, op11_8, 1, op4,
995 !strconcat(OpcodeStr, "64"), v1i64, OpNode>;
997 // 128-bit vector types.
998 def v16i8 : N2VQSh<op24, op23, 0b001000, op11_8, 0, op4,
999 !strconcat(OpcodeStr, "8"), v16i8, OpNode>;
1000 def v8i16 : N2VQSh<op24, op23, 0b010000, op11_8, 0, op4,
1001 !strconcat(OpcodeStr, "16"), v8i16, OpNode>;
1002 def v4i32 : N2VQSh<op24, op23, 0b100000, op11_8, 0, op4,
1003 !strconcat(OpcodeStr, "32"), v4i32, OpNode>;
1004 def v2i64 : N2VQSh<op24, op23, 0b000000, op11_8, 1, op4,
1005 !strconcat(OpcodeStr, "64"), v2i64, OpNode>;
1009 // Neon Shift-Accumulate vector operations,
1010 // element sizes of 8, 16, 32 and 64 bits:
1011 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1012 string OpcodeStr, SDNode ShOp> {
1013 // 64-bit vector types.
1014 def v8i8 : N2VDShAdd<op24, op23, 0b001000, op11_8, 0, op4,
1015 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
1016 def v4i16 : N2VDShAdd<op24, op23, 0b010000, op11_8, 0, op4,
1017 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
1018 def v2i32 : N2VDShAdd<op24, op23, 0b100000, op11_8, 0, op4,
1019 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
1020 def v1i64 : N2VDShAdd<op24, op23, 0b000000, op11_8, 1, op4,
1021 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
1023 // 128-bit vector types.
1024 def v16i8 : N2VQShAdd<op24, op23, 0b001000, op11_8, 0, op4,
1025 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
1026 def v8i16 : N2VQShAdd<op24, op23, 0b010000, op11_8, 0, op4,
1027 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
1028 def v4i32 : N2VQShAdd<op24, op23, 0b100000, op11_8, 0, op4,
1029 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
1030 def v2i64 : N2VQShAdd<op24, op23, 0b000000, op11_8, 1, op4,
1031 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
1035 // Neon Shift-Insert vector operations,
1036 // element sizes of 8, 16, 32 and 64 bits:
1037 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1038 string OpcodeStr, SDNode ShOp> {
1039 // 64-bit vector types.
1040 def v8i8 : N2VDShIns<op24, op23, 0b001000, op11_8, 0, op4,
1041 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
1042 def v4i16 : N2VDShIns<op24, op23, 0b010000, op11_8, 0, op4,
1043 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
1044 def v2i32 : N2VDShIns<op24, op23, 0b100000, op11_8, 0, op4,
1045 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
1046 def v1i64 : N2VDShIns<op24, op23, 0b000000, op11_8, 1, op4,
1047 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
1049 // 128-bit vector types.
1050 def v16i8 : N2VQShIns<op24, op23, 0b001000, op11_8, 0, op4,
1051 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
1052 def v8i16 : N2VQShIns<op24, op23, 0b010000, op11_8, 0, op4,
1053 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
1054 def v4i32 : N2VQShIns<op24, op23, 0b100000, op11_8, 0, op4,
1055 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
1056 def v2i64 : N2VQShIns<op24, op23, 0b000000, op11_8, 1, op4,
1057 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
1060 //===----------------------------------------------------------------------===//
1061 // Instruction Definitions.
1062 //===----------------------------------------------------------------------===//
1064 // Vector Add Operations.
1066 // VADD : Vector Add (integer and floating-point)
1067 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, "vadd.i", add, 1>;
1068 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd, 1>;
1069 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, "vadd.f32", v4f32, v4f32, fadd, 1>;
1070 // VADDL : Vector Add Long (Q = D + D)
1071 defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, "vaddl.s", int_arm_neon_vaddls, 1>;
1072 defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, "vaddl.u", int_arm_neon_vaddlu, 1>;
1073 // VADDW : Vector Add Wide (Q = Q + D)
1074 defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw.s", int_arm_neon_vaddws, 0>;
1075 defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw.u", int_arm_neon_vaddwu, 0>;
1076 // VHADD : Vector Halving Add
1077 defm VHADDs : N3VInt_QHS<0,0,0b0000,0, "vhadd.s", int_arm_neon_vhadds, 1>;
1078 defm VHADDu : N3VInt_QHS<1,0,0b0000,0, "vhadd.u", int_arm_neon_vhaddu, 1>;
1079 // VRHADD : Vector Rounding Halving Add
1080 defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, "vrhadd.s", int_arm_neon_vrhadds, 1>;
1081 defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, "vrhadd.u", int_arm_neon_vrhaddu, 1>;
1082 // VQADD : Vector Saturating Add
1083 defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, "vqadd.s", int_arm_neon_vqadds, 1>;
1084 defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, "vqadd.u", int_arm_neon_vqaddu, 1>;
1085 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
1086 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn.i", int_arm_neon_vaddhn, 1>;
1087 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
1088 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn.i", int_arm_neon_vraddhn, 1>;
1090 // Vector Multiply Operations.
1092 // VMUL : Vector Multiply (integer, polynomial and floating-point)
1093 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, "vmul.i", mul, 1>;
1094 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v8i8, v8i8,
1095 int_arm_neon_vmulp, 1>;
1096 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v16i8, v16i8,
1097 int_arm_neon_vmulp, 1>;
1098 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul, 1>;
1099 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, "vmul.f32", v4f32, v4f32, fmul, 1>;
1100 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
1101 defm VQDMULH : N3VInt_HS<0,0,0b1011,0, "vqdmulh.s", int_arm_neon_vqdmulh, 1>;
1102 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
1103 defm VQRDMULH : N3VInt_HS<1,0,0b1011,0, "vqrdmulh.s", int_arm_neon_vqrdmulh, 1>;
1104 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
1105 defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, "vmull.s", int_arm_neon_vmulls, 1>;
1106 defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, "vmull.u", int_arm_neon_vmullu, 1>;
1107 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, "vmull.p8", v8i16, v8i8,
1108 int_arm_neon_vmullp, 1>;
1109 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
1110 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, "vqdmull.s", int_arm_neon_vqdmull, 1>;
1112 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
1114 // VMLA : Vector Multiply Accumulate (integer and floating-point)
1115 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmla.i", add>;
1116 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32, fmul, fadd>;
1117 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v4f32, fmul, fadd>;
1118 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
1119 defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal.s", int_arm_neon_vmlals>;
1120 defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal.u", int_arm_neon_vmlalu>;
1121 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
1122 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal.s", int_arm_neon_vqdmlal>;
1123 // VMLS : Vector Multiply Subtract (integer and floating-point)
1124 defm VMLS : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmls.i", sub>;
1125 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32, fmul, fsub>;
1126 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v4f32, fmul, fsub>;
1127 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
1128 defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl.s", int_arm_neon_vmlsls>;
1129 defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl.u", int_arm_neon_vmlslu>;
1130 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
1131 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl.s", int_arm_neon_vqdmlsl>;
1133 // Vector Subtract Operations.
1135 // VSUB : Vector Subtract (integer and floating-point)
1136 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, "vsub.i", sub, 0>;
1137 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub, 0>;
1138 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, "vsub.f32", v4f32, v4f32, fsub, 0>;
1139 // VSUBL : Vector Subtract Long (Q = D - D)
1140 defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, "vsubl.s", int_arm_neon_vsubls, 1>;
1141 defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, "vsubl.u", int_arm_neon_vsublu, 1>;
1142 // VSUBW : Vector Subtract Wide (Q = Q - D)
1143 defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw.s", int_arm_neon_vsubws, 0>;
1144 defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw.u", int_arm_neon_vsubwu, 0>;
1145 // VHSUB : Vector Halving Subtract
1146 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, "vhsub.s", int_arm_neon_vhsubs, 0>;
1147 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, "vhsub.u", int_arm_neon_vhsubu, 0>;
1148 // VQSUB : Vector Saturing Subtract
1149 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, "vqsub.s", int_arm_neon_vqsubs, 0>;
1150 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, "vqsub.u", int_arm_neon_vqsubu, 0>;
1151 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
1152 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn.i", int_arm_neon_vsubhn, 0>;
1153 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
1154 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn.i", int_arm_neon_vrsubhn, 0>;
1156 // Vector Comparisons.
1158 // VCEQ : Vector Compare Equal
1159 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, "vceq.i", NEONvceq, 1>;
1160 def VCEQfd : N3VD<0,0,0b00,0b1110,0, "vceq.f32", v2i32, v2f32, NEONvceq, 1>;
1161 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, "vceq.f32", v4i32, v4f32, NEONvceq, 1>;
1162 // VCGE : Vector Compare Greater Than or Equal
1163 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, "vcge.s", NEONvcge, 0>;
1164 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, "vcge.u", NEONvcgeu, 0>;
1165 def VCGEfd : N3VD<1,0,0b00,0b1110,0, "vcge.f32", v2i32, v2f32, NEONvcge, 0>;
1166 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, "vcge.f32", v4i32, v4f32, NEONvcge, 0>;
1167 // VCGT : Vector Compare Greater Than
1168 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, "vcgt.s", NEONvcgt, 0>;
1169 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, "vcgt.u", NEONvcgtu, 0>;
1170 def VCGTfd : N3VD<1,0,0b10,0b1110,0, "vcgt.f32", v2i32, v2f32, NEONvcgt, 0>;
1171 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, "vcgt.f32", v4i32, v4f32, NEONvcgt, 0>;
1172 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
1173 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v2i32, v2f32,
1174 int_arm_neon_vacged, 0>;
1175 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v4i32, v4f32,
1176 int_arm_neon_vacgeq, 0>;
1177 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
1178 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v2i32, v2f32,
1179 int_arm_neon_vacgtd, 0>;
1180 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v4i32, v4f32,
1181 int_arm_neon_vacgtq, 0>;
1182 // VTST : Vector Test Bits
1183 defm VTST : N3V_QHS<0, 0, 0b1000, 1, "vtst.i", NEONvtst, 1>;
1185 // Vector Bitwise Operations.
1187 // VAND : Vector Bitwise AND
1188 def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, "vand", v2i32, v2i32, and, 1>;
1189 def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, "vand", v4i32, v4i32, and, 1>;
1191 // VEOR : Vector Bitwise Exclusive OR
1192 def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, "veor", v2i32, v2i32, xor, 1>;
1193 def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, "veor", v4i32, v4i32, xor, 1>;
1195 // VORR : Vector Bitwise OR
1196 def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, "vorr", v2i32, v2i32, or, 1>;
1197 def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, "vorr", v4i32, v4i32, or, 1>;
1199 // VBIC : Vector Bitwise Bit Clear (AND NOT)
1200 def VBICd : N3V<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1201 (ins DPR:$src1, DPR:$src2), NoItinerary,
1202 "vbic\t$dst, $src1, $src2", "",
1203 [(set DPR:$dst, (v2i32 (and DPR:$src1,(vnot DPR:$src2))))]>;
1204 def VBICq : N3V<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1205 (ins QPR:$src1, QPR:$src2), NoItinerary,
1206 "vbic\t$dst, $src1, $src2", "",
1207 [(set QPR:$dst, (v4i32 (and QPR:$src1,(vnot QPR:$src2))))]>;
1209 // VORN : Vector Bitwise OR NOT
1210 def VORNd : N3V<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
1211 (ins DPR:$src1, DPR:$src2), NoItinerary,
1212 "vorn\t$dst, $src1, $src2", "",
1213 [(set DPR:$dst, (v2i32 (or DPR:$src1, (vnot DPR:$src2))))]>;
1214 def VORNq : N3V<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
1215 (ins QPR:$src1, QPR:$src2), NoItinerary,
1216 "vorn\t$dst, $src1, $src2", "",
1217 [(set QPR:$dst, (v4i32 (or QPR:$src1, (vnot QPR:$src2))))]>;
1219 // VMVN : Vector Bitwise NOT
1220 def VMVNd : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
1221 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1222 "vmvn\t$dst, $src", "",
1223 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>;
1224 def VMVNq : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
1225 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1226 "vmvn\t$dst, $src", "",
1227 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>;
1228 def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>;
1229 def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>;
1231 // VBSL : Vector Bitwise Select
1232 def VBSLd : N3V<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1233 (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
1234 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1236 (v2i32 (or (and DPR:$src2, DPR:$src1),
1237 (and DPR:$src3, (vnot DPR:$src1)))))]>;
1238 def VBSLq : N3V<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1239 (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
1240 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1242 (v4i32 (or (and QPR:$src2, QPR:$src1),
1243 (and QPR:$src3, (vnot QPR:$src1)))))]>;
1245 // VBIF : Vector Bitwise Insert if False
1246 // like VBSL but with: "vbif\t$dst, $src3, $src1", "$src2 = $dst",
1247 // VBIT : Vector Bitwise Insert if True
1248 // like VBSL but with: "vbit\t$dst, $src2, $src1", "$src3 = $dst",
1249 // These are not yet implemented. The TwoAddress pass will not go looking
1250 // for equivalent operations with different register constraints; it just
1253 // Vector Absolute Differences.
1255 // VABD : Vector Absolute Difference
1256 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, "vabd.s", int_arm_neon_vabds, 0>;
1257 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, "vabd.u", int_arm_neon_vabdu, 0>;
1258 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v2f32, v2f32,
1259 int_arm_neon_vabds, 0>;
1260 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v4f32, v4f32,
1261 int_arm_neon_vabds, 0>;
1263 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
1264 defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, "vabdl.s", int_arm_neon_vabdls, 0>;
1265 defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, "vabdl.u", int_arm_neon_vabdlu, 0>;
1267 // VABA : Vector Absolute Difference and Accumulate
1268 defm VABAs : N3VInt3_QHS<0,1,0b0101,0, "vaba.s", int_arm_neon_vabas>;
1269 defm VABAu : N3VInt3_QHS<1,1,0b0101,0, "vaba.u", int_arm_neon_vabau>;
1271 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
1272 defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal.s", int_arm_neon_vabals>;
1273 defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal.u", int_arm_neon_vabalu>;
1275 // Vector Maximum and Minimum.
1277 // VMAX : Vector Maximum
1278 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, "vmax.s", int_arm_neon_vmaxs, 1>;
1279 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, "vmax.u", int_arm_neon_vmaxu, 1>;
1280 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v2f32, v2f32,
1281 int_arm_neon_vmaxs, 1>;
1282 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v4f32, v4f32,
1283 int_arm_neon_vmaxs, 1>;
1285 // VMIN : Vector Minimum
1286 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, "vmin.s", int_arm_neon_vmins, 1>;
1287 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, "vmin.u", int_arm_neon_vminu, 1>;
1288 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v2f32, v2f32,
1289 int_arm_neon_vmins, 1>;
1290 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v4f32, v4f32,
1291 int_arm_neon_vmins, 1>;
1293 // Vector Pairwise Operations.
1295 // VPADD : Vector Pairwise Add
1296 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, "vpadd.i8", v8i8, v8i8,
1297 int_arm_neon_vpadd, 0>;
1298 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, "vpadd.i16", v4i16, v4i16,
1299 int_arm_neon_vpadd, 0>;
1300 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, "vpadd.i32", v2i32, v2i32,
1301 int_arm_neon_vpadd, 0>;
1302 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, "vpadd.f32", v2f32, v2f32,
1303 int_arm_neon_vpadd, 0>;
1305 // VPADDL : Vector Pairwise Add Long
1306 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl.s",
1307 int_arm_neon_vpaddls>;
1308 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl.u",
1309 int_arm_neon_vpaddlu>;
1311 // VPADAL : Vector Pairwise Add and Accumulate Long
1312 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpadal.s",
1313 int_arm_neon_vpadals>;
1314 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpadal.u",
1315 int_arm_neon_vpadalu>;
1317 // VPMAX : Vector Pairwise Maximum
1318 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, "vpmax.s8", v8i8, v8i8,
1319 int_arm_neon_vpmaxs, 0>;
1320 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, "vpmax.s16", v4i16, v4i16,
1321 int_arm_neon_vpmaxs, 0>;
1322 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, "vpmax.s32", v2i32, v2i32,
1323 int_arm_neon_vpmaxs, 0>;
1324 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, "vpmax.u8", v8i8, v8i8,
1325 int_arm_neon_vpmaxu, 0>;
1326 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, "vpmax.u16", v4i16, v4i16,
1327 int_arm_neon_vpmaxu, 0>;
1328 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, "vpmax.u32", v2i32, v2i32,
1329 int_arm_neon_vpmaxu, 0>;
1330 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, "vpmax.f32", v2f32, v2f32,
1331 int_arm_neon_vpmaxs, 0>;
1333 // VPMIN : Vector Pairwise Minimum
1334 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, "vpmin.s8", v8i8, v8i8,
1335 int_arm_neon_vpmins, 0>;
1336 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, "vpmin.s16", v4i16, v4i16,
1337 int_arm_neon_vpmins, 0>;
1338 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, "vpmin.s32", v2i32, v2i32,
1339 int_arm_neon_vpmins, 0>;
1340 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, "vpmin.u8", v8i8, v8i8,
1341 int_arm_neon_vpminu, 0>;
1342 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, "vpmin.u16", v4i16, v4i16,
1343 int_arm_neon_vpminu, 0>;
1344 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, "vpmin.u32", v2i32, v2i32,
1345 int_arm_neon_vpminu, 0>;
1346 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, "vpmin.f32", v2f32, v2f32,
1347 int_arm_neon_vpmins, 0>;
1349 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
1351 // VRECPE : Vector Reciprocal Estimate
1352 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1353 v2i32, v2i32, int_arm_neon_vrecpe>;
1354 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1355 v4i32, v4i32, int_arm_neon_vrecpe>;
1356 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1357 v2f32, v2f32, int_arm_neon_vrecpe>;
1358 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1359 v4f32, v4f32, int_arm_neon_vrecpe>;
1361 // VRECPS : Vector Reciprocal Step
1362 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v2f32, v2f32,
1363 int_arm_neon_vrecps, 1>;
1364 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v4f32, v4f32,
1365 int_arm_neon_vrecps, 1>;
1367 // VRSQRTE : Vector Reciprocal Square Root Estimate
1368 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1369 v2i32, v2i32, int_arm_neon_vrsqrte>;
1370 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1371 v4i32, v4i32, int_arm_neon_vrsqrte>;
1372 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1373 v2f32, v2f32, int_arm_neon_vrsqrte>;
1374 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1375 v4f32, v4f32, int_arm_neon_vrsqrte>;
1377 // VRSQRTS : Vector Reciprocal Square Root Step
1378 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v2f32, v2f32,
1379 int_arm_neon_vrsqrts, 1>;
1380 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v4f32, v4f32,
1381 int_arm_neon_vrsqrts, 1>;
1385 // VSHL : Vector Shift
1386 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, "vshl.s", int_arm_neon_vshifts, 0>;
1387 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, "vshl.u", int_arm_neon_vshiftu, 0>;
1388 // VSHL : Vector Shift Left (Immediate)
1389 defm VSHLi : N2VSh_QHSD<0, 1, 0b0111, 1, "vshl.i", NEONvshl>;
1390 // VSHR : Vector Shift Right (Immediate)
1391 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, "vshr.s", NEONvshrs>;
1392 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, "vshr.u", NEONvshru>;
1394 // VSHLL : Vector Shift Left Long
1395 def VSHLLs8 : N2VLSh<0, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.s8",
1396 v8i16, v8i8, NEONvshlls>;
1397 def VSHLLs16 : N2VLSh<0, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.s16",
1398 v4i32, v4i16, NEONvshlls>;
1399 def VSHLLs32 : N2VLSh<0, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.s32",
1400 v2i64, v2i32, NEONvshlls>;
1401 def VSHLLu8 : N2VLSh<1, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.u8",
1402 v8i16, v8i8, NEONvshllu>;
1403 def VSHLLu16 : N2VLSh<1, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.u16",
1404 v4i32, v4i16, NEONvshllu>;
1405 def VSHLLu32 : N2VLSh<1, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.u32",
1406 v2i64, v2i32, NEONvshllu>;
1408 // VSHLL : Vector Shift Left Long (with maximum shift count)
1409 def VSHLLi8 : N2VLSh<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll.i8",
1410 v8i16, v8i8, NEONvshlli>;
1411 def VSHLLi16 : N2VLSh<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll.i16",
1412 v4i32, v4i16, NEONvshlli>;
1413 def VSHLLi32 : N2VLSh<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll.i32",
1414 v2i64, v2i32, NEONvshlli>;
1416 // VSHRN : Vector Shift Right and Narrow
1417 def VSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 0, 1, "vshrn.i16",
1418 v8i8, v8i16, NEONvshrn>;
1419 def VSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 0, 1, "vshrn.i32",
1420 v4i16, v4i32, NEONvshrn>;
1421 def VSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 0, 1, "vshrn.i64",
1422 v2i32, v2i64, NEONvshrn>;
1424 // VRSHL : Vector Rounding Shift
1425 defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, "vrshl.s", int_arm_neon_vrshifts, 0>;
1426 defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, "vrshl.u", int_arm_neon_vrshiftu, 0>;
1427 // VRSHR : Vector Rounding Shift Right
1428 defm VRSHRs : N2VSh_QHSD<0, 1, 0b0010, 1, "vrshr.s", NEONvrshrs>;
1429 defm VRSHRu : N2VSh_QHSD<1, 1, 0b0010, 1, "vrshr.u", NEONvrshru>;
1431 // VRSHRN : Vector Rounding Shift Right and Narrow
1432 def VRSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 1, 1, "vrshrn.i16",
1433 v8i8, v8i16, NEONvrshrn>;
1434 def VRSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 1, 1, "vrshrn.i32",
1435 v4i16, v4i32, NEONvrshrn>;
1436 def VRSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 1, 1, "vrshrn.i64",
1437 v2i32, v2i64, NEONvrshrn>;
1439 // VQSHL : Vector Saturating Shift
1440 defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, "vqshl.s", int_arm_neon_vqshifts, 0>;
1441 defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, "vqshl.u", int_arm_neon_vqshiftu, 0>;
1442 // VQSHL : Vector Saturating Shift Left (Immediate)
1443 defm VQSHLsi : N2VSh_QHSD<0, 1, 0b0111, 1, "vqshl.s", NEONvqshls>;
1444 defm VQSHLui : N2VSh_QHSD<1, 1, 0b0111, 1, "vqshl.u", NEONvqshlu>;
1445 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
1446 defm VQSHLsu : N2VSh_QHSD<1, 1, 0b0110, 1, "vqshlu.s", NEONvqshlsu>;
1448 // VQSHRN : Vector Saturating Shift Right and Narrow
1449 def VQSHRNs16 : N2VNSh<0, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.s16",
1450 v8i8, v8i16, NEONvqshrns>;
1451 def VQSHRNs32 : N2VNSh<0, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.s32",
1452 v4i16, v4i32, NEONvqshrns>;
1453 def VQSHRNs64 : N2VNSh<0, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.s64",
1454 v2i32, v2i64, NEONvqshrns>;
1455 def VQSHRNu16 : N2VNSh<1, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.u16",
1456 v8i8, v8i16, NEONvqshrnu>;
1457 def VQSHRNu32 : N2VNSh<1, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.u32",
1458 v4i16, v4i32, NEONvqshrnu>;
1459 def VQSHRNu64 : N2VNSh<1, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.u64",
1460 v2i32, v2i64, NEONvqshrnu>;
1462 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
1463 def VQSHRUN16 : N2VNSh<1, 1, 0b001000, 0b1000, 0, 0, 1, "vqshrun.s16",
1464 v8i8, v8i16, NEONvqshrnsu>;
1465 def VQSHRUN32 : N2VNSh<1, 1, 0b010000, 0b1000, 0, 0, 1, "vqshrun.s32",
1466 v4i16, v4i32, NEONvqshrnsu>;
1467 def VQSHRUN64 : N2VNSh<1, 1, 0b100000, 0b1000, 0, 0, 1, "vqshrun.s64",
1468 v2i32, v2i64, NEONvqshrnsu>;
1470 // VQRSHL : Vector Saturating Rounding Shift
1471 defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, "vqrshl.s",
1472 int_arm_neon_vqrshifts, 0>;
1473 defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, "vqrshl.u",
1474 int_arm_neon_vqrshiftu, 0>;
1476 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
1477 def VQRSHRNs16: N2VNSh<0, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.s16",
1478 v8i8, v8i16, NEONvqrshrns>;
1479 def VQRSHRNs32: N2VNSh<0, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.s32",
1480 v4i16, v4i32, NEONvqrshrns>;
1481 def VQRSHRNs64: N2VNSh<0, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.s64",
1482 v2i32, v2i64, NEONvqrshrns>;
1483 def VQRSHRNu16: N2VNSh<1, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.u16",
1484 v8i8, v8i16, NEONvqrshrnu>;
1485 def VQRSHRNu32: N2VNSh<1, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.u32",
1486 v4i16, v4i32, NEONvqrshrnu>;
1487 def VQRSHRNu64: N2VNSh<1, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.u64",
1488 v2i32, v2i64, NEONvqrshrnu>;
1490 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
1491 def VQRSHRUN16: N2VNSh<1, 1, 0b001000, 0b1000, 0, 1, 1, "vqrshrun.s16",
1492 v8i8, v8i16, NEONvqrshrnsu>;
1493 def VQRSHRUN32: N2VNSh<1, 1, 0b010000, 0b1000, 0, 1, 1, "vqrshrun.s32",
1494 v4i16, v4i32, NEONvqrshrnsu>;
1495 def VQRSHRUN64: N2VNSh<1, 1, 0b100000, 0b1000, 0, 1, 1, "vqrshrun.s64",
1496 v2i32, v2i64, NEONvqrshrnsu>;
1498 // VSRA : Vector Shift Right and Accumulate
1499 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra.s", NEONvshrs>;
1500 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra.u", NEONvshru>;
1501 // VRSRA : Vector Rounding Shift Right and Accumulate
1502 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra.s", NEONvrshrs>;
1503 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra.u", NEONvrshru>;
1505 // VSLI : Vector Shift Left and Insert
1506 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli.", NEONvsli>;
1507 // VSRI : Vector Shift Right and Insert
1508 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri.", NEONvsri>;
1510 // Vector Absolute and Saturating Absolute.
1512 // VABS : Vector Absolute Value
1513 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0, "vabs.s",
1515 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1516 v2f32, v2f32, int_arm_neon_vabs>;
1517 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1518 v4f32, v4f32, int_arm_neon_vabs>;
1520 // VQABS : Vector Saturating Absolute Value
1521 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0, "vqabs.s",
1522 int_arm_neon_vqabs>;
1526 def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
1527 def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>;
1529 class VNEGD<bits<2> size, string OpcodeStr, ValueType Ty>
1530 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
1532 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1533 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>;
1534 class VNEGQ<bits<2> size, string OpcodeStr, ValueType Ty>
1535 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
1537 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1538 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>;
1540 // VNEG : Vector Negate
1541 def VNEGs8d : VNEGD<0b00, "vneg.s8", v8i8>;
1542 def VNEGs16d : VNEGD<0b01, "vneg.s16", v4i16>;
1543 def VNEGs32d : VNEGD<0b10, "vneg.s32", v2i32>;
1544 def VNEGs8q : VNEGQ<0b00, "vneg.s8", v16i8>;
1545 def VNEGs16q : VNEGQ<0b01, "vneg.s16", v8i16>;
1546 def VNEGs32q : VNEGQ<0b10, "vneg.s32", v4i32>;
1548 // VNEG : Vector Negate (floating-point)
1549 def VNEGf32d : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
1550 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1551 "vneg.f32\t$dst, $src", "",
1552 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
1553 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
1554 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1555 "vneg.f32\t$dst, $src", "",
1556 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
1558 def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
1559 def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
1560 def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>;
1561 def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>;
1562 def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>;
1563 def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>;
1565 // VQNEG : Vector Saturating Negate
1566 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0, "vqneg.s",
1567 int_arm_neon_vqneg>;
1569 // Vector Bit Counting Operations.
1571 // VCLS : Vector Count Leading Sign Bits
1572 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0, "vcls.s",
1574 // VCLZ : Vector Count Leading Zeros
1575 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0, "vclz.i",
1577 // VCNT : Vector Count One Bits
1578 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1579 v8i8, v8i8, int_arm_neon_vcnt>;
1580 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1581 v16i8, v16i8, int_arm_neon_vcnt>;
1583 // Vector Move Operations.
1585 // VMOV : Vector Move (Register)
1587 def VMOVD : N3V<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
1588 NoItinerary, "vmov\t$dst, $src", "", []>;
1589 def VMOVQ : N3V<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
1590 NoItinerary, "vmov\t$dst, $src", "", []>;
1592 // VMOV : Vector Move (Immediate)
1594 // VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
1595 def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
1596 return ARM::getVMOVImm(N, 1, *CurDAG);
1598 def vmovImm8 : PatLeaf<(build_vector), [{
1599 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
1602 // VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
1603 def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
1604 return ARM::getVMOVImm(N, 2, *CurDAG);
1606 def vmovImm16 : PatLeaf<(build_vector), [{
1607 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
1608 }], VMOV_get_imm16>;
1610 // VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
1611 def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
1612 return ARM::getVMOVImm(N, 4, *CurDAG);
1614 def vmovImm32 : PatLeaf<(build_vector), [{
1615 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
1616 }], VMOV_get_imm32>;
1618 // VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
1619 def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
1620 return ARM::getVMOVImm(N, 8, *CurDAG);
1622 def vmovImm64 : PatLeaf<(build_vector), [{
1623 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
1624 }], VMOV_get_imm64>;
1626 // Note: Some of the cmode bits in the following VMOV instructions need to
1627 // be encoded based on the immed values.
1629 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
1630 (ins i8imm:$SIMM), NoItinerary,
1631 "vmov.i8\t$dst, $SIMM", "",
1632 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
1633 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
1634 (ins i8imm:$SIMM), NoItinerary,
1635 "vmov.i8\t$dst, $SIMM", "",
1636 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
1638 def VMOVv4i16 : N1ModImm<1, 0b000, 0b1000, 0, 0, 0, 1, (outs DPR:$dst),
1639 (ins i16imm:$SIMM), NoItinerary,
1640 "vmov.i16\t$dst, $SIMM", "",
1641 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
1642 def VMOVv8i16 : N1ModImm<1, 0b000, 0b1000, 0, 1, 0, 1, (outs QPR:$dst),
1643 (ins i16imm:$SIMM), NoItinerary,
1644 "vmov.i16\t$dst, $SIMM", "",
1645 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
1647 def VMOVv2i32 : N1ModImm<1, 0b000, 0b0000, 0, 0, 0, 1, (outs DPR:$dst),
1648 (ins i32imm:$SIMM), NoItinerary,
1649 "vmov.i32\t$dst, $SIMM", "",
1650 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
1651 def VMOVv4i32 : N1ModImm<1, 0b000, 0b0000, 0, 1, 0, 1, (outs QPR:$dst),
1652 (ins i32imm:$SIMM), NoItinerary,
1653 "vmov.i32\t$dst, $SIMM", "",
1654 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
1656 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
1657 (ins i64imm:$SIMM), NoItinerary,
1658 "vmov.i64\t$dst, $SIMM", "",
1659 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
1660 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
1661 (ins i64imm:$SIMM), NoItinerary,
1662 "vmov.i64\t$dst, $SIMM", "",
1663 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
1665 // VMOV : Vector Get Lane (move scalar to ARM core register)
1667 def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00,
1668 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
1669 NoItinerary, "vmov", ".s8\t$dst, $src[$lane]",
1670 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
1672 def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01,
1673 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
1674 NoItinerary, "vmov", ".s16\t$dst, $src[$lane]",
1675 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
1677 def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00,
1678 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
1679 NoItinerary, "vmov", ".u8\t$dst, $src[$lane]",
1680 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
1682 def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01,
1683 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
1684 NoItinerary, "vmov", ".u16\t$dst, $src[$lane]",
1685 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
1687 def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00,
1688 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
1689 NoItinerary, "vmov", ".32\t$dst, $src[$lane]",
1690 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
1692 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
1693 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
1694 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1695 (DSubReg_i8_reg imm:$lane))),
1696 (SubReg_i8_lane imm:$lane))>;
1697 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
1698 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1699 (DSubReg_i16_reg imm:$lane))),
1700 (SubReg_i16_lane imm:$lane))>;
1701 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
1702 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1703 (DSubReg_i8_reg imm:$lane))),
1704 (SubReg_i8_lane imm:$lane))>;
1705 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
1706 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1707 (DSubReg_i16_reg imm:$lane))),
1708 (SubReg_i16_lane imm:$lane))>;
1709 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
1710 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
1711 (DSubReg_i32_reg imm:$lane))),
1712 (SubReg_i32_lane imm:$lane))>;
1713 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
1714 (EXTRACT_SUBREG DPR:$src1, (SSubReg_f32_reg imm:$src2))>;
1715 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
1716 (EXTRACT_SUBREG QPR:$src1, (SSubReg_f32_reg imm:$src2))>;
1717 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
1718 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
1719 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
1720 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
1723 // VMOV : Vector Set Lane (move ARM core register to scalar)
1725 let Constraints = "$src1 = $dst" in {
1726 def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst),
1727 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
1728 NoItinerary, "vmov", ".8\t$dst[$lane], $src2",
1729 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
1730 GPR:$src2, imm:$lane))]>;
1731 def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst),
1732 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
1733 NoItinerary, "vmov", ".16\t$dst[$lane], $src2",
1734 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
1735 GPR:$src2, imm:$lane))]>;
1736 def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst),
1737 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
1738 NoItinerary, "vmov", ".32\t$dst[$lane], $src2",
1739 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
1740 GPR:$src2, imm:$lane))]>;
1742 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
1743 (v16i8 (INSERT_SUBREG QPR:$src1,
1744 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
1745 (DSubReg_i8_reg imm:$lane))),
1746 GPR:$src2, (SubReg_i8_lane imm:$lane)),
1747 (DSubReg_i8_reg imm:$lane)))>;
1748 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
1749 (v8i16 (INSERT_SUBREG QPR:$src1,
1750 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
1751 (DSubReg_i16_reg imm:$lane))),
1752 GPR:$src2, (SubReg_i16_lane imm:$lane)),
1753 (DSubReg_i16_reg imm:$lane)))>;
1754 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
1755 (v4i32 (INSERT_SUBREG QPR:$src1,
1756 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
1757 (DSubReg_i32_reg imm:$lane))),
1758 GPR:$src2, (SubReg_i32_lane imm:$lane)),
1759 (DSubReg_i32_reg imm:$lane)))>;
1761 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
1762 (INSERT_SUBREG DPR:$src1, SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
1763 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
1764 (INSERT_SUBREG QPR:$src1, SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
1766 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1767 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
1768 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1769 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
1771 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
1772 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
1773 def : Pat<(v2f64 (scalar_to_vector DPR:$src)),
1774 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, arm_dsubreg_0)>;
1775 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
1776 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
1778 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
1779 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
1780 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
1781 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
1782 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
1783 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
1785 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
1786 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1787 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
1789 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
1790 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1791 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
1793 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
1794 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1795 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
1798 // VDUP : Vector Duplicate (from ARM core register to all elements)
1800 class VDUPD<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1801 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
1802 NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"),
1803 [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
1804 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1805 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
1806 NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"),
1807 [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
1809 def VDUP8d : VDUPD<0b11101100, 0b00, ".8", v8i8>;
1810 def VDUP16d : VDUPD<0b11101000, 0b01, ".16", v4i16>;
1811 def VDUP32d : VDUPD<0b11101000, 0b00, ".32", v2i32>;
1812 def VDUP8q : VDUPQ<0b11101110, 0b00, ".8", v16i8>;
1813 def VDUP16q : VDUPQ<0b11101010, 0b01, ".16", v8i16>;
1814 def VDUP32q : VDUPQ<0b11101010, 0b00, ".32", v4i32>;
1816 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
1817 NoItinerary, "vdup", ".32\t$dst, $src",
1818 [(set DPR:$dst, (v2f32 (NEONvdup
1819 (f32 (bitconvert GPR:$src)))))]>;
1820 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
1821 NoItinerary, "vdup", ".32\t$dst, $src",
1822 [(set QPR:$dst, (v4f32 (NEONvdup
1823 (f32 (bitconvert GPR:$src)))))]>;
1825 // VDUP : Vector Duplicate Lane (from scalar to all elements)
1827 class VDUPLND<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty>
1828 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
1829 (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane), NoItinerary,
1830 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
1831 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
1833 class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr,
1834 ValueType ResTy, ValueType OpTy>
1835 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
1836 (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane), NoItinerary,
1837 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
1838 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src), imm:$lane)))]>;
1840 def VDUPLN8d : VDUPLND<0b00, 0b01, "vdup.8", v8i8>;
1841 def VDUPLN16d : VDUPLND<0b00, 0b10, "vdup.16", v4i16>;
1842 def VDUPLN32d : VDUPLND<0b01, 0b00, "vdup.32", v2i32>;
1843 def VDUPLNfd : VDUPLND<0b01, 0b00, "vdup.32", v2f32>;
1844 def VDUPLN8q : VDUPLNQ<0b00, 0b01, "vdup.8", v16i8, v8i8>;
1845 def VDUPLN16q : VDUPLNQ<0b00, 0b10, "vdup.16", v8i16, v4i16>;
1846 def VDUPLN32q : VDUPLNQ<0b01, 0b00, "vdup.32", v4i32, v2i32>;
1847 def VDUPLNfq : VDUPLNQ<0b01, 0b00, "vdup.32", v4f32, v2f32>;
1849 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
1850 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
1851 (DSubReg_i8_reg imm:$lane))),
1852 (SubReg_i8_lane imm:$lane)))>;
1853 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
1854 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
1855 (DSubReg_i16_reg imm:$lane))),
1856 (SubReg_i16_lane imm:$lane)))>;
1857 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
1858 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
1859 (DSubReg_i32_reg imm:$lane))),
1860 (SubReg_i32_lane imm:$lane)))>;
1861 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
1862 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
1863 (DSubReg_i32_reg imm:$lane))),
1864 (SubReg_i32_lane imm:$lane)))>;
1866 def VDUPfdf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 0, 0,
1867 (outs DPR:$dst), (ins SPR:$src),
1868 NoItinerary, "vdup.32\t$dst, ${src:lane}", "",
1869 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
1871 def VDUPfqf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 1, 0,
1872 (outs QPR:$dst), (ins SPR:$src),
1873 NoItinerary, "vdup.32\t$dst, ${src:lane}", "",
1874 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
1876 // VMOVN : Vector Narrowing Move
1877 defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, "vmovn.i",
1878 int_arm_neon_vmovn>;
1879 // VQMOVN : Vector Saturating Narrowing Move
1880 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, "vqmovn.s",
1881 int_arm_neon_vqmovns>;
1882 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, "vqmovn.u",
1883 int_arm_neon_vqmovnu>;
1884 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, "vqmovun.s",
1885 int_arm_neon_vqmovnsu>;
1886 // VMOVL : Vector Lengthening Move
1887 defm VMOVLs : N2VLInt_QHS<0,1,0b1010,0,0,1, "vmovl.s", int_arm_neon_vmovls>;
1888 defm VMOVLu : N2VLInt_QHS<1,1,0b1010,0,0,1, "vmovl.u", int_arm_neon_vmovlu>;
1890 // Vector Conversions.
1892 // VCVT : Vector Convert Between Floating-Point and Integers
1893 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1894 v2i32, v2f32, fp_to_sint>;
1895 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1896 v2i32, v2f32, fp_to_uint>;
1897 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1898 v2f32, v2i32, sint_to_fp>;
1899 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1900 v2f32, v2i32, uint_to_fp>;
1902 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1903 v4i32, v4f32, fp_to_sint>;
1904 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1905 v4i32, v4f32, fp_to_uint>;
1906 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1907 v4f32, v4i32, sint_to_fp>;
1908 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1909 v4f32, v4i32, uint_to_fp>;
1911 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
1912 // Note: Some of the opcode bits in the following VCVT instructions need to
1913 // be encoded based on the immed values.
1914 def VCVTf2xsd : N2VCvtD<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1915 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
1916 def VCVTf2xud : N2VCvtD<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1917 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
1918 def VCVTxs2fd : N2VCvtD<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1919 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
1920 def VCVTxu2fd : N2VCvtD<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1921 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
1923 def VCVTf2xsq : N2VCvtQ<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1924 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
1925 def VCVTf2xuq : N2VCvtQ<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1926 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
1927 def VCVTxs2fq : N2VCvtQ<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1928 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
1929 def VCVTxu2fq : N2VCvtQ<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1930 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
1934 // VREV64 : Vector Reverse elements within 64-bit doublewords
1936 class VREV64D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1937 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
1938 (ins DPR:$src), NoItinerary,
1939 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1940 [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
1941 class VREV64Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1942 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
1943 (ins QPR:$src), NoItinerary,
1944 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1945 [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
1947 def VREV64d8 : VREV64D<0b00, "vrev64.8", v8i8>;
1948 def VREV64d16 : VREV64D<0b01, "vrev64.16", v4i16>;
1949 def VREV64d32 : VREV64D<0b10, "vrev64.32", v2i32>;
1950 def VREV64df : VREV64D<0b10, "vrev64.32", v2f32>;
1952 def VREV64q8 : VREV64Q<0b00, "vrev64.8", v16i8>;
1953 def VREV64q16 : VREV64Q<0b01, "vrev64.16", v8i16>;
1954 def VREV64q32 : VREV64Q<0b10, "vrev64.32", v4i32>;
1955 def VREV64qf : VREV64Q<0b10, "vrev64.32", v4f32>;
1957 // VREV32 : Vector Reverse elements within 32-bit words
1959 class VREV32D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1960 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
1961 (ins DPR:$src), NoItinerary,
1962 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1963 [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
1964 class VREV32Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1965 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
1966 (ins QPR:$src), NoItinerary,
1967 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1968 [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
1970 def VREV32d8 : VREV32D<0b00, "vrev32.8", v8i8>;
1971 def VREV32d16 : VREV32D<0b01, "vrev32.16", v4i16>;
1973 def VREV32q8 : VREV32Q<0b00, "vrev32.8", v16i8>;
1974 def VREV32q16 : VREV32Q<0b01, "vrev32.16", v8i16>;
1976 // VREV16 : Vector Reverse elements within 16-bit halfwords
1978 class VREV16D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1979 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
1980 (ins DPR:$src), NoItinerary,
1981 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1982 [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
1983 class VREV16Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1984 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
1985 (ins QPR:$src), NoItinerary,
1986 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1987 [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
1989 def VREV16d8 : VREV16D<0b00, "vrev16.8", v8i8>;
1990 def VREV16q8 : VREV16Q<0b00, "vrev16.8", v16i8>;
1992 // Other Vector Shuffles.
1994 // VEXT : Vector Extract
1996 class VEXTd<string OpcodeStr, ValueType Ty>
1997 : N3V<0,1,0b11,0b0000,0,0, (outs DPR:$dst),
1998 (ins DPR:$lhs, DPR:$rhs, i32imm:$index), NoItinerary,
1999 !strconcat(OpcodeStr, "\t$dst, $lhs, $rhs, $index"), "",
2000 [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
2001 (Ty DPR:$rhs), imm:$index)))]>;
2003 class VEXTq<string OpcodeStr, ValueType Ty>
2004 : N3V<0,1,0b11,0b0000,1,0, (outs QPR:$dst),
2005 (ins QPR:$lhs, QPR:$rhs, i32imm:$index), NoItinerary,
2006 !strconcat(OpcodeStr, "\t$dst, $lhs, $rhs, $index"), "",
2007 [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
2008 (Ty QPR:$rhs), imm:$index)))]>;
2010 def VEXTd8 : VEXTd<"vext.8", v8i8>;
2011 def VEXTd16 : VEXTd<"vext.16", v4i16>;
2012 def VEXTd32 : VEXTd<"vext.32", v2i32>;
2013 def VEXTdf : VEXTd<"vext.32", v2f32>;
2015 def VEXTq8 : VEXTq<"vext.8", v16i8>;
2016 def VEXTq16 : VEXTq<"vext.16", v8i16>;
2017 def VEXTq32 : VEXTq<"vext.32", v4i32>;
2018 def VEXTqf : VEXTq<"vext.32", v4f32>;
2020 // VTRN : Vector Transpose
2022 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn.8">;
2023 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn.16">;
2024 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn.32">;
2026 def VTRNq8 : N2VQShuffle<0b00, 0b00001, "vtrn.8">;
2027 def VTRNq16 : N2VQShuffle<0b01, 0b00001, "vtrn.16">;
2028 def VTRNq32 : N2VQShuffle<0b10, 0b00001, "vtrn.32">;
2030 // VUZP : Vector Unzip (Deinterleave)
2032 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp.8">;
2033 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp.16">;
2034 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp.32">;
2036 def VUZPq8 : N2VQShuffle<0b00, 0b00010, "vuzp.8">;
2037 def VUZPq16 : N2VQShuffle<0b01, 0b00010, "vuzp.16">;
2038 def VUZPq32 : N2VQShuffle<0b10, 0b00010, "vuzp.32">;
2040 // VZIP : Vector Zip (Interleave)
2042 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip.8">;
2043 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip.16">;
2044 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip.32">;
2046 def VZIPq8 : N2VQShuffle<0b00, 0b00011, "vzip.8">;
2047 def VZIPq16 : N2VQShuffle<0b01, 0b00011, "vzip.16">;
2048 def VZIPq32 : N2VQShuffle<0b10, 0b00011, "vzip.32">;
2050 // Vector Table Lookup and Table Extension.
2052 // VTBL : Vector Table Lookup
2054 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
2055 (ins DPR:$tbl1, DPR:$src), NoItinerary,
2056 "vtbl.8\t$dst, \\{$tbl1\\}, $src", "",
2057 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
2059 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
2060 (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), NoItinerary,
2061 "vtbl.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "",
2062 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl2
2063 DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
2065 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
2066 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), NoItinerary,
2067 "vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "",
2068 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl3
2069 DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
2071 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
2072 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), NoItinerary,
2073 "vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "",
2074 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl4 DPR:$tbl1, DPR:$tbl2,
2075 DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
2077 // VTBX : Vector Table Extension
2079 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
2080 (ins DPR:$orig, DPR:$tbl1, DPR:$src), NoItinerary,
2081 "vtbx.8\t$dst, \\{$tbl1\\}, $src", "$orig = $dst",
2082 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
2083 DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
2085 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
2086 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), NoItinerary,
2087 "vtbx.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "$orig = $dst",
2088 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx2
2089 DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
2091 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
2092 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), NoItinerary,
2093 "vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "$orig = $dst",
2094 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx3 DPR:$orig, DPR:$tbl1,
2095 DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
2097 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
2098 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), NoItinerary,
2099 "vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "$orig = $dst",
2100 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx4 DPR:$orig, DPR:$tbl1,
2101 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
2103 //===----------------------------------------------------------------------===//
2104 // NEON instructions for single-precision FP math
2105 //===----------------------------------------------------------------------===//
2107 // These need separate instructions because they must use DPR_VFP2 register
2108 // class which have SPR sub-registers.
2110 // Vector Add Operations used for single-precision FP
2111 let neverHasSideEffects = 1 in
2112 def VADDfd_sfp : N3VDs<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd,1>;
2113 def : N3VDsPat<fadd, VADDfd_sfp>;
2115 // Vector Sub Operations used for single-precision FP
2116 let neverHasSideEffects = 1 in
2117 def VSUBfd_sfp : N3VDs<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub,0>;
2118 def : N3VDsPat<fsub, VSUBfd_sfp>;
2120 // Vector Multiply Operations used for single-precision FP
2121 let neverHasSideEffects = 1 in
2122 def VMULfd_sfp : N3VDs<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul,1>;
2123 def : N3VDsPat<fmul, VMULfd_sfp>;
2125 // Vector Multiply-Accumulate/Subtract used for single-precision FP
2126 let neverHasSideEffects = 1 in
2127 def VMLAfd_sfp : N3VDMulOps<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32,fmul,fadd>;
2128 def : N3VDMulOpsPat<fmul, fadd, VMLAfd_sfp>;
2130 let neverHasSideEffects = 1 in
2131 def VMLSfd_sfp : N3VDMulOps<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32,fmul,fsub>;
2132 def : N3VDMulOpsPat<fmul, fsub, VMLSfd_sfp>;
2134 // Vector Absolute used for single-precision FP
2135 let neverHasSideEffects = 1 in
2136 def VABSfd_sfp : N2VDInts<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
2137 v2f32, v2f32, int_arm_neon_vabs>;
2138 def : N2VDIntsPat<fabs, VABSfd_sfp>;
2140 // Vector Negate used for single-precision FP
2141 let neverHasSideEffects = 1 in
2142 def VNEGf32d_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
2143 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NoItinerary,
2144 "vneg.f32\t$dst, $src", "", []>;
2145 def : N2VDIntsPat<fneg, VNEGf32d_sfp>;
2147 // Vector Convert between single-precision FP and integer
2148 let neverHasSideEffects = 1 in
2149 def VCVTf2sd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
2150 v2i32, v2f32, fp_to_sint>;
2151 def : N2VDsPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
2153 let neverHasSideEffects = 1 in
2154 def VCVTf2ud_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
2155 v2i32, v2f32, fp_to_uint>;
2156 def : N2VDsPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
2158 let neverHasSideEffects = 1 in
2159 def VCVTs2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
2160 v2f32, v2i32, sint_to_fp>;
2161 def : N2VDsPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
2163 let neverHasSideEffects = 1 in
2164 def VCVTu2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
2165 v2f32, v2i32, uint_to_fp>;
2166 def : N2VDsPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
2168 //===----------------------------------------------------------------------===//
2169 // Non-Instruction Patterns
2170 //===----------------------------------------------------------------------===//
2173 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
2174 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
2175 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
2176 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
2177 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
2178 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
2179 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
2180 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
2181 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
2182 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
2183 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
2184 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
2185 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
2186 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
2187 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
2188 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
2189 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
2190 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
2191 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
2192 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
2193 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
2194 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
2195 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
2196 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
2197 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
2198 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
2199 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
2200 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
2201 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
2202 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
2204 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
2205 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
2206 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
2207 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
2208 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
2209 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
2210 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
2211 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
2212 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
2213 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
2214 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
2215 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
2216 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
2217 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
2218 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
2219 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
2220 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
2221 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
2222 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
2223 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
2224 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
2225 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
2226 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
2227 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
2228 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
2229 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
2230 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
2231 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
2232 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
2233 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
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