1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
70 // VDUPLANE can produce a quad-register result from a double-register source,
71 // so the result is not constrained to match the source.
72 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
73 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
76 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
77 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
78 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
80 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
81 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
82 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
83 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
85 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
88 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
89 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
90 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
92 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
94 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
95 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
97 //===----------------------------------------------------------------------===//
98 // NEON operand definitions
99 //===----------------------------------------------------------------------===//
101 def h8imm : Operand<i8> {
102 let PrintMethod = "printHex8ImmOperand";
104 def h16imm : Operand<i16> {
105 let PrintMethod = "printHex16ImmOperand";
107 def h32imm : Operand<i32> {
108 let PrintMethod = "printHex32ImmOperand";
110 def h64imm : Operand<i64> {
111 let PrintMethod = "printHex64ImmOperand";
114 //===----------------------------------------------------------------------===//
115 // NEON load / store instructions
116 //===----------------------------------------------------------------------===//
119 // Use vldmia to load a Q register as a D register pair.
120 // This is equivalent to VLDMD except that it has a Q register operand
121 // instead of a pair of D registers.
123 : AXDI5<(outs QPR:$dst), (ins addrmode5:$addr, pred:$p),
124 IndexModeNone, IIC_fpLoadm,
125 "vldm${addr:submode}${p}\t${addr:base}, ${dst:dregpair}", "", []>;
127 : AXDI5<(outs QPR:$dst, GPR:$wb), (ins addrmode5:$addr, pred:$p),
128 IndexModeUpd, IIC_fpLoadm,
129 "vldm${addr:submode}${p}\t${addr:base}!, ${dst:dregpair}",
130 "$addr.base = $wb", []>;
132 // Use vld1 to load a Q register as a D register pair.
133 // This alternative to VLDMQ allows an alignment to be specified.
134 // This is equivalent to VLD1q64 except that it has a Q register operand.
136 : NLdSt<0,0b10,0b1010,0b1100, (outs QPR:$dst), (ins addrmode6:$addr),
137 IIC_VLD1, "vld1", "64", "${dst:dregpair}, $addr", "", []>;
139 : NLdSt<0,0b10,0b1010,0b1100, (outs QPR:$dst, GPR:$wb),
140 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1, "vld1", "64",
141 "${dst:dregpair}, $addr$offset", "$addr.addr = $wb", []>;
144 let mayStore = 1 in {
145 // Use vstmia to store a Q register as a D register pair.
146 // This is equivalent to VSTMD except that it has a Q register operand
147 // instead of a pair of D registers.
149 : AXDI5<(outs), (ins QPR:$src, addrmode5:$addr, pred:$p),
150 IndexModeNone, IIC_fpStorem,
151 "vstm${addr:submode}${p}\t${addr:base}, ${src:dregpair}", "", []>;
153 : AXDI5<(outs GPR:$wb), (ins QPR:$src, addrmode5:$addr, pred:$p),
154 IndexModeUpd, IIC_fpStorem,
155 "vstm${addr:submode}${p}\t${addr:base}!, ${src:dregpair}",
156 "$addr.base = $wb", []>;
158 // Use vst1 to store a Q register as a D register pair.
159 // This alternative to VSTMQ allows an alignment to be specified.
160 // This is equivalent to VST1q64 except that it has a Q register operand.
162 : NLdSt<0,0b00,0b1010,0b1100, (outs), (ins addrmode6:$addr, QPR:$src),
163 IIC_VST, "vst1", "64", "${src:dregpair}, $addr", "", []>;
165 : NLdSt<0,0b00,0b1010,0b1100, (outs GPR:$wb),
166 (ins addrmode6:$addr, am6offset:$offset, QPR:$src),
167 IIC_VST, "vst1", "64", "{$src:dregpair}, $addr$offset",
168 "$addr.addr = $wb", []>;
171 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
173 // VLD1 : Vector Load (multiple single elements)
174 class VLD1D<bits<4> op7_4, string Dt>
175 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst),
176 (ins addrmode6:$addr), IIC_VLD1,
177 "vld1", Dt, "\\{$dst\\}, $addr", "", []>;
178 class VLD1Q<bits<4> op7_4, string Dt>
179 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$dst1, DPR:$dst2),
180 (ins addrmode6:$addr), IIC_VLD1,
181 "vld1", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>;
183 def VLD1d8 : VLD1D<0b0000, "8">;
184 def VLD1d16 : VLD1D<0b0100, "16">;
185 def VLD1d32 : VLD1D<0b1000, "32">;
186 def VLD1d64 : VLD1D<0b1100, "64">;
188 def VLD1q8 : VLD1Q<0b0000, "8">;
189 def VLD1q16 : VLD1Q<0b0100, "16">;
190 def VLD1q32 : VLD1Q<0b1000, "32">;
191 def VLD1q64 : VLD1Q<0b1100, "64">;
193 // ...with address register writeback:
194 class VLD1DWB<bits<4> op7_4, string Dt>
195 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst, GPR:$wb),
196 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1,
197 "vld1", Dt, "\\{$dst\\}, $addr$offset",
198 "$addr.addr = $wb", []>;
199 class VLD1QWB<bits<4> op7_4, string Dt>
200 : NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst, GPR:$wb),
201 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1,
202 "vld1", Dt, "${dst:dregpair}, $addr$offset",
203 "$addr.addr = $wb", []>;
205 def VLD1d8_UPD : VLD1DWB<0b0000, "8">;
206 def VLD1d16_UPD : VLD1DWB<0b0100, "16">;
207 def VLD1d32_UPD : VLD1DWB<0b1000, "32">;
208 def VLD1d64_UPD : VLD1DWB<0b1100, "64">;
210 def VLD1q8_UPD : VLD1QWB<0b0000, "8">;
211 def VLD1q16_UPD : VLD1QWB<0b0100, "16">;
212 def VLD1q32_UPD : VLD1QWB<0b1000, "32">;
213 def VLD1q64_UPD : VLD1QWB<0b1100, "64">;
215 // ...with 3 registers (some of these are only for the disassembler):
216 class VLD1D3<bits<4> op7_4, string Dt>
217 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
218 (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
219 "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
220 class VLD1D3WB<bits<4> op7_4, string Dt>
221 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
222 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1, "vld1", Dt,
223 "\\{$dst1, $dst2, $dst3\\}, $addr$offset", "$addr.addr = $wb", []>;
225 def VLD1d8T : VLD1D3<0b0000, "8">;
226 def VLD1d16T : VLD1D3<0b0100, "16">;
227 def VLD1d32T : VLD1D3<0b1000, "32">;
228 def VLD1d64T : VLD1D3<0b1100, "64">;
230 def VLD1d8T_UPD : VLD1D3WB<0b0000, "8">;
231 def VLD1d16T_UPD : VLD1D3WB<0b0100, "16">;
232 def VLD1d32T_UPD : VLD1D3WB<0b1000, "32">;
233 def VLD1d64T_UPD : VLD1D3WB<0b1100, "64">;
235 // ...with 4 registers (some of these are only for the disassembler):
236 class VLD1D4<bits<4> op7_4, string Dt>
237 : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
238 (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
239 "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
240 class VLD1D4WB<bits<4> op7_4, string Dt>
241 : NLdSt<0,0b10,0b0010,op7_4,
242 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
243 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1, "vld1", Dt,
244 "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset", "$addr.addr = $wb",
247 def VLD1d8Q : VLD1D4<0b0000, "8">;
248 def VLD1d16Q : VLD1D4<0b0100, "16">;
249 def VLD1d32Q : VLD1D4<0b1000, "32">;
250 def VLD1d64Q : VLD1D4<0b1100, "64">;
252 def VLD1d8Q_UPD : VLD1D4WB<0b0000, "8">;
253 def VLD1d16Q_UPD : VLD1D4WB<0b0100, "16">;
254 def VLD1d32Q_UPD : VLD1D4WB<0b1000, "32">;
255 def VLD1d64Q_UPD : VLD1D4WB<0b1100, "64">;
257 // VLD2 : Vector Load (multiple 2-element structures)
258 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
259 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2),
260 (ins addrmode6:$addr), IIC_VLD2,
261 "vld2", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>;
262 class VLD2Q<bits<4> op7_4, string Dt>
263 : NLdSt<0, 0b10, 0b0011, op7_4,
264 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
265 (ins addrmode6:$addr), IIC_VLD2,
266 "vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
268 def VLD2d8 : VLD2D<0b1000, 0b0000, "8">;
269 def VLD2d16 : VLD2D<0b1000, 0b0100, "16">;
270 def VLD2d32 : VLD2D<0b1000, 0b1000, "32">;
272 def VLD2q8 : VLD2Q<0b0000, "8">;
273 def VLD2q16 : VLD2Q<0b0100, "16">;
274 def VLD2q32 : VLD2Q<0b1000, "32">;
276 // ...with address register writeback:
277 class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
278 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
279 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2,
280 "vld2", Dt, "\\{$dst1, $dst2\\}, $addr$offset",
281 "$addr.addr = $wb", []>;
282 class VLD2QWB<bits<4> op7_4, string Dt>
283 : NLdSt<0, 0b10, 0b0011, op7_4,
284 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
285 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2,
286 "vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset",
287 "$addr.addr = $wb", []>;
289 def VLD2d8_UPD : VLD2DWB<0b1000, 0b0000, "8">;
290 def VLD2d16_UPD : VLD2DWB<0b1000, 0b0100, "16">;
291 def VLD2d32_UPD : VLD2DWB<0b1000, 0b1000, "32">;
293 def VLD2q8_UPD : VLD2QWB<0b0000, "8">;
294 def VLD2q16_UPD : VLD2QWB<0b0100, "16">;
295 def VLD2q32_UPD : VLD2QWB<0b1000, "32">;
297 // ...with double-spaced registers (for disassembly only):
298 def VLD2b8 : VLD2D<0b1001, 0b0000, "8">;
299 def VLD2b16 : VLD2D<0b1001, 0b0100, "16">;
300 def VLD2b32 : VLD2D<0b1001, 0b1000, "32">;
301 def VLD2b8_UPD : VLD2DWB<0b1001, 0b0000, "8">;
302 def VLD2b16_UPD : VLD2DWB<0b1001, 0b0100, "16">;
303 def VLD2b32_UPD : VLD2DWB<0b1001, 0b1000, "32">;
305 // VLD3 : Vector Load (multiple 3-element structures)
306 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
307 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
308 (ins addrmode6:$addr), IIC_VLD3,
309 "vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
311 def VLD3d8 : VLD3D<0b0100, 0b0000, "8">;
312 def VLD3d16 : VLD3D<0b0100, 0b0100, "16">;
313 def VLD3d32 : VLD3D<0b0100, 0b1000, "32">;
315 // ...with address register writeback:
316 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
317 : NLdSt<0, 0b10, op11_8, op7_4,
318 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
319 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD3,
320 "vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr$offset",
321 "$addr.addr = $wb", []>;
323 def VLD3d8_UPD : VLD3DWB<0b0100, 0b0000, "8">;
324 def VLD3d16_UPD : VLD3DWB<0b0100, 0b0100, "16">;
325 def VLD3d32_UPD : VLD3DWB<0b0100, 0b1000, "32">;
327 // ...with double-spaced registers (non-updating versions for disassembly only):
328 def VLD3q8 : VLD3D<0b0101, 0b0000, "8">;
329 def VLD3q16 : VLD3D<0b0101, 0b0100, "16">;
330 def VLD3q32 : VLD3D<0b0101, 0b1000, "32">;
331 def VLD3q8_UPD : VLD3DWB<0b0101, 0b0000, "8">;
332 def VLD3q16_UPD : VLD3DWB<0b0101, 0b0100, "16">;
333 def VLD3q32_UPD : VLD3DWB<0b0101, 0b1000, "32">;
335 // ...alternate versions to be allocated odd register numbers:
336 def VLD3q8odd_UPD : VLD3DWB<0b0101, 0b0000, "8">;
337 def VLD3q16odd_UPD : VLD3DWB<0b0101, 0b0100, "16">;
338 def VLD3q32odd_UPD : VLD3DWB<0b0101, 0b1000, "32">;
340 // VLD4 : Vector Load (multiple 4-element structures)
341 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
342 : NLdSt<0, 0b10, op11_8, op7_4,
343 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
344 (ins addrmode6:$addr), IIC_VLD4,
345 "vld4", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
347 def VLD4d8 : VLD4D<0b0000, 0b0000, "8">;
348 def VLD4d16 : VLD4D<0b0000, 0b0100, "16">;
349 def VLD4d32 : VLD4D<0b0000, 0b1000, "32">;
351 // ...with address register writeback:
352 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
353 : NLdSt<0, 0b10, op11_8, op7_4,
354 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
355 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD4,
356 "vld4", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset",
357 "$addr.addr = $wb", []>;
359 def VLD4d8_UPD : VLD4DWB<0b0000, 0b0000, "8">;
360 def VLD4d16_UPD : VLD4DWB<0b0000, 0b0100, "16">;
361 def VLD4d32_UPD : VLD4DWB<0b0000, 0b1000, "32">;
363 // ...with double-spaced registers (non-updating versions for disassembly only):
364 def VLD4q8 : VLD4D<0b0001, 0b0000, "8">;
365 def VLD4q16 : VLD4D<0b0001, 0b0100, "16">;
366 def VLD4q32 : VLD4D<0b0001, 0b1000, "32">;
367 def VLD4q8_UPD : VLD4DWB<0b0001, 0b0000, "8">;
368 def VLD4q16_UPD : VLD4DWB<0b0001, 0b0100, "16">;
369 def VLD4q32_UPD : VLD4DWB<0b0001, 0b1000, "32">;
371 // ...alternate versions to be allocated odd register numbers:
372 def VLD4q8odd_UPD : VLD4DWB<0b0001, 0b0000, "8">;
373 def VLD4q16odd_UPD : VLD4DWB<0b0001, 0b0100, "16">;
374 def VLD4q32odd_UPD : VLD4DWB<0b0001, 0b1000, "32">;
376 // VLD1LN : Vector Load (single element to one lane)
377 // FIXME: Not yet implemented.
379 // VLD2LN : Vector Load (single 2-element structure to one lane)
380 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
381 : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2),
382 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
383 IIC_VLD2, "vld2", Dt, "\\{$dst1[$lane], $dst2[$lane]\\}, $addr",
384 "$src1 = $dst1, $src2 = $dst2", []>;
386 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8">;
387 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16">;
388 def VLD2LNd32 : VLD2LN<0b1001, {?,0,?,?}, "32">;
390 // ...with double-spaced registers:
391 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16">;
392 def VLD2LNq32 : VLD2LN<0b1001, {?,1,?,?}, "32">;
394 // ...alternate versions to be allocated odd register numbers:
395 def VLD2LNq16odd : VLD2LN<0b0101, {?,?,1,?}, "16">;
396 def VLD2LNq32odd : VLD2LN<0b1001, {?,1,?,?}, "32">;
398 // ...with address register writeback:
399 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
400 : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
401 (ins addrmode6:$addr, am6offset:$offset,
402 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2, "vld2", Dt,
403 "\\{$dst1[$lane], $dst2[$lane]\\}, $addr$offset",
404 "$src1 = $dst1, $src2 = $dst2, $addr.addr = $wb", []>;
406 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8">;
407 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16">;
408 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,?,?}, "32">;
410 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16">;
411 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,?,?}, "32">;
413 // VLD3LN : Vector Load (single 3-element structure to one lane)
414 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
415 : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
416 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
417 nohash_imm:$lane), IIC_VLD3, "vld3", Dt,
418 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr",
419 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
421 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8">;
422 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16">;
423 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32">;
425 // ...with double-spaced registers:
426 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16">;
427 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32">;
429 // ...alternate versions to be allocated odd register numbers:
430 def VLD3LNq16odd : VLD3LN<0b0110, {?,?,1,0}, "16">;
431 def VLD3LNq32odd : VLD3LN<0b1010, {?,1,0,0}, "32">;
433 // ...with address register writeback:
434 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
435 : NLdSt<1, 0b10, op11_8, op7_4,
436 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
437 (ins addrmode6:$addr, am6offset:$offset,
438 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
439 IIC_VLD3, "vld3", Dt,
440 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr$offset",
441 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $addr.addr = $wb",
444 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8">;
445 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16">;
446 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32">;
448 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16">;
449 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32">;
451 // VLD4LN : Vector Load (single 4-element structure to one lane)
452 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
453 : NLdSt<1, 0b10, op11_8, op7_4,
454 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
455 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
456 nohash_imm:$lane), IIC_VLD4, "vld4", Dt,
457 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr",
458 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
460 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8">;
461 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16">;
462 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32">;
464 // ...with double-spaced registers:
465 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16">;
466 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32">;
468 // ...alternate versions to be allocated odd register numbers:
469 def VLD4LNq16odd : VLD4LN<0b0111, {?,?,1,?}, "16">;
470 def VLD4LNq32odd : VLD4LN<0b1011, {?,1,?,?}, "32">;
472 // ...with address register writeback:
473 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
474 : NLdSt<1, 0b10, op11_8, op7_4,
475 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
476 (ins addrmode6:$addr, am6offset:$offset,
477 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
478 IIC_VLD4, "vld4", Dt,
479 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr$offset",
480 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $addr.addr = $wb",
483 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8">;
484 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16">;
485 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32">;
487 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16">;
488 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32">;
490 // VLD1DUP : Vector Load (single element to all lanes)
491 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
492 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
493 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
494 // FIXME: Not yet implemented.
495 } // mayLoad = 1, hasExtraDefRegAllocReq = 1
497 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
499 // VST1 : Vector Store (multiple single elements)
500 class VST1D<bits<4> op7_4, string Dt>
501 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src), IIC_VST,
502 "vst1", Dt, "\\{$src\\}, $addr", "", []>;
503 class VST1Q<bits<4> op7_4, string Dt>
504 : NLdSt<0,0b00,0b1010,op7_4, (outs),
505 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
506 "vst1", Dt, "\\{$src1, $src2\\}, $addr", "", []>;
508 def VST1d8 : VST1D<0b0000, "8">;
509 def VST1d16 : VST1D<0b0100, "16">;
510 def VST1d32 : VST1D<0b1000, "32">;
511 def VST1d64 : VST1D<0b1100, "64">;
513 def VST1q8 : VST1Q<0b0000, "8">;
514 def VST1q16 : VST1Q<0b0100, "16">;
515 def VST1q32 : VST1Q<0b1000, "32">;
516 def VST1q64 : VST1Q<0b1100, "64">;
518 // ...with address register writeback:
519 class VST1DWB<bits<4> op7_4, string Dt>
520 : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
521 (ins addrmode6:$addr, am6offset:$offset, DPR:$src), IIC_VST,
522 "vst1", Dt, "\\{$src\\}, $addr$offset", "$addr.addr = $wb", []>;
523 class VST1QWB<bits<4> op7_4, string Dt>
524 : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),
525 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), IIC_VST,
526 "vst1", Dt, "${src:dregpair}, $addr$offset", "$addr.addr = $wb", []>;
528 def VST1d8_UPD : VST1DWB<0b0000, "8">;
529 def VST1d16_UPD : VST1DWB<0b0100, "16">;
530 def VST1d32_UPD : VST1DWB<0b1000, "32">;
531 def VST1d64_UPD : VST1DWB<0b1100, "64">;
533 def VST1q8_UPD : VST1QWB<0b0000, "8">;
534 def VST1q16_UPD : VST1QWB<0b0100, "16">;
535 def VST1q32_UPD : VST1QWB<0b1000, "32">;
536 def VST1q64_UPD : VST1QWB<0b1100, "64">;
538 // ...with 3 registers (some of these are only for the disassembler):
539 class VST1D3<bits<4> op7_4, string Dt>
540 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
541 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
542 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>;
543 class VST1D3WB<bits<4> op7_4, string Dt>
544 : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
545 (ins addrmode6:$addr, am6offset:$offset,
546 DPR:$src1, DPR:$src2, DPR:$src3),
547 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr$offset",
548 "$addr.addr = $wb", []>;
550 def VST1d8T : VST1D3<0b0000, "8">;
551 def VST1d16T : VST1D3<0b0100, "16">;
552 def VST1d32T : VST1D3<0b1000, "32">;
553 def VST1d64T : VST1D3<0b1100, "64">;
555 def VST1d8T_UPD : VST1D3WB<0b0000, "8">;
556 def VST1d16T_UPD : VST1D3WB<0b0100, "16">;
557 def VST1d32T_UPD : VST1D3WB<0b1000, "32">;
558 def VST1d64T_UPD : VST1D3WB<0b1100, "64">;
560 // ...with 4 registers (some of these are only for the disassembler):
561 class VST1D4<bits<4> op7_4, string Dt>
562 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
563 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
564 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr", "",
566 class VST1D4WB<bits<4> op7_4, string Dt>
567 : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
568 (ins addrmode6:$addr, am6offset:$offset,
569 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
570 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
571 "$addr.addr = $wb", []>;
573 def VST1d8Q : VST1D4<0b0000, "8">;
574 def VST1d16Q : VST1D4<0b0100, "16">;
575 def VST1d32Q : VST1D4<0b1000, "32">;
576 def VST1d64Q : VST1D4<0b1100, "64">;
578 def VST1d8Q_UPD : VST1D4WB<0b0000, "8">;
579 def VST1d16Q_UPD : VST1D4WB<0b0100, "16">;
580 def VST1d32Q_UPD : VST1D4WB<0b1000, "32">;
581 def VST1d64Q_UPD : VST1D4WB<0b1100, "64">;
583 // VST2 : Vector Store (multiple 2-element structures)
584 class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
585 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
586 (ins addrmode6:$addr, DPR:$src1, DPR:$src2),
587 IIC_VST, "vst2", Dt, "\\{$src1, $src2\\}, $addr", "", []>;
588 class VST2Q<bits<4> op7_4, string Dt>
589 : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
590 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
591 IIC_VST, "vst2", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
594 def VST2d8 : VST2D<0b1000, 0b0000, "8">;
595 def VST2d16 : VST2D<0b1000, 0b0100, "16">;
596 def VST2d32 : VST2D<0b1000, 0b1000, "32">;
598 def VST2q8 : VST2Q<0b0000, "8">;
599 def VST2q16 : VST2Q<0b0100, "16">;
600 def VST2q32 : VST2Q<0b1000, "32">;
602 // ...with address register writeback:
603 class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
604 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
605 (ins addrmode6:$addr, am6offset:$offset, DPR:$src1, DPR:$src2),
606 IIC_VST, "vst2", Dt, "\\{$src1, $src2\\}, $addr$offset",
607 "$addr.addr = $wb", []>;
608 class VST2QWB<bits<4> op7_4, string Dt>
609 : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
610 (ins addrmode6:$addr, am6offset:$offset,
611 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
612 IIC_VST, "vst2", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
613 "$addr.addr = $wb", []>;
615 def VST2d8_UPD : VST2DWB<0b1000, 0b0000, "8">;
616 def VST2d16_UPD : VST2DWB<0b1000, 0b0100, "16">;
617 def VST2d32_UPD : VST2DWB<0b1000, 0b1000, "32">;
619 def VST2q8_UPD : VST2QWB<0b0000, "8">;
620 def VST2q16_UPD : VST2QWB<0b0100, "16">;
621 def VST2q32_UPD : VST2QWB<0b1000, "32">;
623 // ...with double-spaced registers (for disassembly only):
624 def VST2b8 : VST2D<0b1001, 0b0000, "8">;
625 def VST2b16 : VST2D<0b1001, 0b0100, "16">;
626 def VST2b32 : VST2D<0b1001, 0b1000, "32">;
627 def VST2b8_UPD : VST2DWB<0b1001, 0b0000, "8">;
628 def VST2b16_UPD : VST2DWB<0b1001, 0b0100, "16">;
629 def VST2b32_UPD : VST2DWB<0b1001, 0b1000, "32">;
631 // VST3 : Vector Store (multiple 3-element structures)
632 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
633 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
634 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
635 "vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>;
637 def VST3d8 : VST3D<0b0100, 0b0000, "8">;
638 def VST3d16 : VST3D<0b0100, 0b0100, "16">;
639 def VST3d32 : VST3D<0b0100, 0b1000, "32">;
641 // ...with address register writeback:
642 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
643 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
644 (ins addrmode6:$addr, am6offset:$offset,
645 DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
646 "vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr$offset",
647 "$addr.addr = $wb", []>;
649 def VST3d8_UPD : VST3DWB<0b0100, 0b0000, "8">;
650 def VST3d16_UPD : VST3DWB<0b0100, 0b0100, "16">;
651 def VST3d32_UPD : VST3DWB<0b0100, 0b1000, "32">;
653 // ...with double-spaced registers (non-updating versions for disassembly only):
654 def VST3q8 : VST3D<0b0101, 0b0000, "8">;
655 def VST3q16 : VST3D<0b0101, 0b0100, "16">;
656 def VST3q32 : VST3D<0b0101, 0b1000, "32">;
657 def VST3q8_UPD : VST3DWB<0b0101, 0b0000, "8">;
658 def VST3q16_UPD : VST3DWB<0b0101, 0b0100, "16">;
659 def VST3q32_UPD : VST3DWB<0b0101, 0b1000, "32">;
661 // ...alternate versions to be allocated odd register numbers:
662 def VST3q8odd_UPD : VST3DWB<0b0101, 0b0000, "8">;
663 def VST3q16odd_UPD : VST3DWB<0b0101, 0b0100, "16">;
664 def VST3q32odd_UPD : VST3DWB<0b0101, 0b1000, "32">;
666 // VST4 : Vector Store (multiple 4-element structures)
667 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
668 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
669 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
670 IIC_VST, "vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
673 def VST4d8 : VST4D<0b0000, 0b0000, "8">;
674 def VST4d16 : VST4D<0b0000, 0b0100, "16">;
675 def VST4d32 : VST4D<0b0000, 0b1000, "32">;
677 // ...with address register writeback:
678 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
679 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
680 (ins addrmode6:$addr, am6offset:$offset,
681 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST,
682 "vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
683 "$addr.addr = $wb", []>;
685 def VST4d8_UPD : VST4DWB<0b0000, 0b0000, "8">;
686 def VST4d16_UPD : VST4DWB<0b0000, 0b0100, "16">;
687 def VST4d32_UPD : VST4DWB<0b0000, 0b1000, "32">;
689 // ...with double-spaced registers (non-updating versions for disassembly only):
690 def VST4q8 : VST4D<0b0001, 0b0000, "8">;
691 def VST4q16 : VST4D<0b0001, 0b0100, "16">;
692 def VST4q32 : VST4D<0b0001, 0b1000, "32">;
693 def VST4q8_UPD : VST4DWB<0b0001, 0b0000, "8">;
694 def VST4q16_UPD : VST4DWB<0b0001, 0b0100, "16">;
695 def VST4q32_UPD : VST4DWB<0b0001, 0b1000, "32">;
697 // ...alternate versions to be allocated odd register numbers:
698 def VST4q8odd_UPD : VST4DWB<0b0001, 0b0000, "8">;
699 def VST4q16odd_UPD : VST4DWB<0b0001, 0b0100, "16">;
700 def VST4q32odd_UPD : VST4DWB<0b0001, 0b1000, "32">;
702 // VST1LN : Vector Store (single element from one lane)
703 // FIXME: Not yet implemented.
705 // VST2LN : Vector Store (single 2-element structure from one lane)
706 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
707 : NLdSt<1, 0b00, op11_8, op7_4, (outs),
708 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
709 IIC_VST, "vst2", Dt, "\\{$src1[$lane], $src2[$lane]\\}, $addr",
712 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8">;
713 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16">;
714 def VST2LNd32 : VST2LN<0b1001, {?,0,?,?}, "32">;
716 // ...with double-spaced registers:
717 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16">;
718 def VST2LNq32 : VST2LN<0b1001, {?,1,?,?}, "32">;
720 // ...alternate versions to be allocated odd register numbers:
721 def VST2LNq16odd : VST2LN<0b0101, {?,?,1,?}, "16">;
722 def VST2LNq32odd : VST2LN<0b1001, {?,1,?,?}, "32">;
724 // ...with address register writeback:
725 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
726 : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
727 (ins addrmode6:$addr, am6offset:$offset,
728 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST, "vst2", Dt,
729 "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset",
730 "$addr.addr = $wb", []>;
732 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8">;
733 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16">;
734 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,?,?}, "32">;
736 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16">;
737 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,?,?}, "32">;
739 // VST3LN : Vector Store (single 3-element structure from one lane)
740 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
741 : NLdSt<1, 0b00, op11_8, op7_4, (outs),
742 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
743 nohash_imm:$lane), IIC_VST, "vst3", Dt,
744 "\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr", "", []>;
746 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8">;
747 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16">;
748 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32">;
750 // ...with double-spaced registers:
751 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16">;
752 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32">;
754 // ...alternate versions to be allocated odd register numbers:
755 def VST3LNq16odd : VST3LN<0b0110, {?,?,1,0}, "16">;
756 def VST3LNq32odd : VST3LN<0b1010, {?,1,0,0}, "32">;
758 // ...with address register writeback:
759 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
760 : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
761 (ins addrmode6:$addr, am6offset:$offset,
762 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
764 "\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr$offset",
765 "$addr.addr = $wb", []>;
767 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8">;
768 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16">;
769 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32">;
771 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16">;
772 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32">;
774 // VST4LN : Vector Store (single 4-element structure from one lane)
775 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
776 : NLdSt<1, 0b00, op11_8, op7_4, (outs),
777 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
778 nohash_imm:$lane), IIC_VST, "vst4", Dt,
779 "\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr",
782 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8">;
783 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16">;
784 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32">;
786 // ...with double-spaced registers:
787 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16">;
788 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32">;
790 // ...alternate versions to be allocated odd register numbers:
791 def VST4LNq16odd : VST4LN<0b0111, {?,?,1,?}, "16">;
792 def VST4LNq32odd : VST4LN<0b1011, {?,1,?,?}, "32">;
794 // ...with address register writeback:
795 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
796 : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
797 (ins addrmode6:$addr, am6offset:$offset,
798 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
800 "\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr$offset",
801 "$addr.addr = $wb", []>;
803 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8">;
804 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16">;
805 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32">;
807 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16">;
808 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32">;
810 } // mayStore = 1, hasExtraSrcRegAllocReq = 1
813 //===----------------------------------------------------------------------===//
814 // NEON pattern fragments
815 //===----------------------------------------------------------------------===//
817 // Extract D sub-registers of Q registers.
818 // (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
819 def DSubReg_i8_reg : SDNodeXForm<imm, [{
820 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
822 def DSubReg_i16_reg : SDNodeXForm<imm, [{
823 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
825 def DSubReg_i32_reg : SDNodeXForm<imm, [{
826 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
828 def DSubReg_f64_reg : SDNodeXForm<imm, [{
829 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
831 def DSubReg_f64_other_reg : SDNodeXForm<imm, [{
832 return CurDAG->getTargetConstant(5 + (1 - N->getZExtValue()), MVT::i32);
835 // Extract S sub-registers of Q/D registers.
836 // (arm_ssubreg_0 is 1; arm_ssubreg_1 is 2; etc.)
837 def SSubReg_f32_reg : SDNodeXForm<imm, [{
838 return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32);
841 // Translate lane numbers from Q registers to D subregs.
842 def SubReg_i8_lane : SDNodeXForm<imm, [{
843 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
845 def SubReg_i16_lane : SDNodeXForm<imm, [{
846 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
848 def SubReg_i32_lane : SDNodeXForm<imm, [{
849 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
852 //===----------------------------------------------------------------------===//
853 // Instruction Classes
854 //===----------------------------------------------------------------------===//
856 // Same as N2V except that it doesn't pass a default NVdVmImmFrm to NDataI.
857 class N2V2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
858 bits<5> op11_7, bit op6, bit op4,
859 dag oops, dag iops, Format f, InstrItinClass itin,
860 string opc, string dt, string asm, string cstr, list<dag> pattern>
861 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
862 let Inst{24-23} = op24_23;
863 let Inst{21-20} = op21_20;
864 let Inst{19-18} = op19_18;
865 let Inst{17-16} = op17_16;
866 let Inst{11-7} = op11_7;
871 // Basic 2-register operations: single-, double- and quad-register.
872 // This is used for NVdVmVCVTFrm form.
873 class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
874 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
875 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
876 : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
877 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NVdVmVCVTFrm,
878 IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
879 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
880 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
881 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
882 : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
883 (ins DPR:$src), NVdVmVCVTFrm, IIC_VUNAD, OpcodeStr, Dt,"$dst, $src","",
884 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
885 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
886 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
887 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
888 : N2V2<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
889 (ins QPR:$src), NVdVmVCVTFrm, IIC_VUNAQ, OpcodeStr, Dt,"$dst, $src","",
890 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
892 // Basic 2-register intrinsics, both double- and quad-register.
893 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
894 bits<2> op17_16, bits<5> op11_7, bit op4,
895 InstrItinClass itin, string OpcodeStr, string Dt,
896 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
897 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
898 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
899 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
900 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
901 bits<2> op17_16, bits<5> op11_7, bit op4,
902 InstrItinClass itin, string OpcodeStr, string Dt,
903 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
904 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
905 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
906 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
908 // Narrow 2-register intrinsics.
909 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
910 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
911 InstrItinClass itin, string OpcodeStr, string Dt,
912 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
913 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
914 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
915 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
917 // Long 2-register intrinsics (currently only used for VMOVL).
918 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
919 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
920 InstrItinClass itin, string OpcodeStr, string Dt,
921 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
922 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$dst),
923 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
924 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
926 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
927 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
928 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
929 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
930 OpcodeStr, Dt, "$dst1, $dst2",
931 "$src1 = $dst1, $src2 = $dst2", []>;
932 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
933 InstrItinClass itin, string OpcodeStr, string Dt>
934 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
935 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$dst1, $dst2",
936 "$src1 = $dst1, $src2 = $dst2", []>;
938 // Basic 3-register operations: single-, double- and quad-register.
939 class N3VS<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
940 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
941 SDNode OpNode, bit Commutable>
942 : N3V<op24, op23, op21_20, op11_8, 0, op4,
943 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), IIC_VBIND,
944 OpcodeStr, Dt, "$dst, $src1, $src2", "", []> {
945 let isCommutable = Commutable;
948 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
949 InstrItinClass itin, string OpcodeStr, string Dt,
950 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
951 : N3V<op24, op23, op21_20, op11_8, 0, op4,
952 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
953 OpcodeStr, Dt, "$dst, $src1, $src2", "",
954 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
955 let isCommutable = Commutable;
957 // Same as N3VD but no data type.
958 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
959 InstrItinClass itin, string OpcodeStr,
960 ValueType ResTy, ValueType OpTy,
961 SDNode OpNode, bit Commutable>
962 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
963 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
964 OpcodeStr, "$dst, $src1, $src2", "",
965 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]>{
966 let isCommutable = Commutable;
968 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
969 InstrItinClass itin, string OpcodeStr, string Dt,
970 ValueType Ty, SDNode ShOp>
971 : N3V<0, 1, op21_20, op11_8, 1, 0,
972 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
973 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
975 (Ty (ShOp (Ty DPR:$src1),
976 (Ty (NEONvduplane (Ty DPR_VFP2:$src2), imm:$lane)))))]>{
977 let isCommutable = 0;
979 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
980 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
981 : N3V<0, 1, op21_20, op11_8, 1, 0,
982 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
983 IIC_VMULi16D, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
985 (Ty (ShOp (Ty DPR:$src1),
986 (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
987 let isCommutable = 0;
990 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
991 InstrItinClass itin, string OpcodeStr, string Dt,
992 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
993 : N3V<op24, op23, op21_20, op11_8, 1, op4,
994 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
995 OpcodeStr, Dt, "$dst, $src1, $src2", "",
996 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
997 let isCommutable = Commutable;
999 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1000 InstrItinClass itin, string OpcodeStr,
1001 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1002 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
1003 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
1004 OpcodeStr, "$dst, $src1, $src2", "",
1005 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]>{
1006 let isCommutable = Commutable;
1008 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
1009 InstrItinClass itin, string OpcodeStr, string Dt,
1010 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1011 : N3V<1, 1, op21_20, op11_8, 1, 0,
1012 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1013 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1014 [(set (ResTy QPR:$dst),
1015 (ResTy (ShOp (ResTy QPR:$src1),
1016 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1018 let isCommutable = 0;
1020 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
1021 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1022 : N3V<1, 1, op21_20, op11_8, 1, 0,
1023 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1024 IIC_VMULi16Q, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1025 [(set (ResTy QPR:$dst),
1026 (ResTy (ShOp (ResTy QPR:$src1),
1027 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
1029 let isCommutable = 0;
1032 // Basic 3-register intrinsics, both double- and quad-register.
1033 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1034 InstrItinClass itin, string OpcodeStr, string Dt,
1035 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1036 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1037 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
1038 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1039 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
1040 let isCommutable = Commutable;
1042 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1043 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1044 : N3V<0, 1, op21_20, op11_8, 1, 0,
1045 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1046 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1047 [(set (Ty DPR:$dst),
1048 (Ty (IntOp (Ty DPR:$src1),
1049 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
1051 let isCommutable = 0;
1053 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1054 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1055 : N3V<0, 1, op21_20, op11_8, 1, 0,
1056 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1057 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1058 [(set (Ty DPR:$dst),
1059 (Ty (IntOp (Ty DPR:$src1),
1060 (Ty (NEONvduplane (Ty DPR_8:$src2),
1062 let isCommutable = 0;
1065 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1066 InstrItinClass itin, string OpcodeStr, string Dt,
1067 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1068 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1069 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
1070 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1071 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
1072 let isCommutable = Commutable;
1074 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1075 string OpcodeStr, string Dt,
1076 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1077 : N3V<1, 1, op21_20, op11_8, 1, 0,
1078 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1079 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1080 [(set (ResTy QPR:$dst),
1081 (ResTy (IntOp (ResTy QPR:$src1),
1082 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1084 let isCommutable = 0;
1086 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1087 string OpcodeStr, string Dt,
1088 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1089 : N3V<1, 1, op21_20, op11_8, 1, 0,
1090 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1091 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1092 [(set (ResTy QPR:$dst),
1093 (ResTy (IntOp (ResTy QPR:$src1),
1094 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
1096 let isCommutable = 0;
1099 // Multiply-Add/Sub operations: single-, double- and quad-register.
1100 class N3VSMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1101 InstrItinClass itin, string OpcodeStr, string Dt,
1102 ValueType Ty, SDNode MulOp, SDNode OpNode>
1103 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1104 (outs DPR_VFP2:$dst),
1105 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), itin,
1106 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst", []>;
1108 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1109 InstrItinClass itin, string OpcodeStr, string Dt,
1110 ValueType Ty, SDNode MulOp, SDNode OpNode>
1111 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1112 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin,
1113 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1114 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
1115 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
1116 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1117 string OpcodeStr, string Dt,
1118 ValueType Ty, SDNode MulOp, SDNode ShOp>
1119 : N3V<0, 1, op21_20, op11_8, 1, 0,
1121 (ins DPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
1122 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1123 [(set (Ty DPR:$dst),
1124 (Ty (ShOp (Ty DPR:$src1),
1125 (Ty (MulOp DPR:$src2,
1126 (Ty (NEONvduplane (Ty DPR_VFP2:$src3),
1128 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1129 string OpcodeStr, string Dt,
1130 ValueType Ty, SDNode MulOp, SDNode ShOp>
1131 : N3V<0, 1, op21_20, op11_8, 1, 0,
1133 (ins DPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
1134 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1135 [(set (Ty DPR:$dst),
1136 (Ty (ShOp (Ty DPR:$src1),
1137 (Ty (MulOp DPR:$src2,
1138 (Ty (NEONvduplane (Ty DPR_8:$src3),
1141 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1142 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
1143 SDNode MulOp, SDNode OpNode>
1144 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1145 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin,
1146 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1147 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
1148 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
1149 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1150 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1151 SDNode MulOp, SDNode ShOp>
1152 : N3V<1, 1, op21_20, op11_8, 1, 0,
1154 (ins QPR:$src1, QPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
1155 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1156 [(set (ResTy QPR:$dst),
1157 (ResTy (ShOp (ResTy QPR:$src1),
1158 (ResTy (MulOp QPR:$src2,
1159 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src3),
1161 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1162 string OpcodeStr, string Dt,
1163 ValueType ResTy, ValueType OpTy,
1164 SDNode MulOp, SDNode ShOp>
1165 : N3V<1, 1, op21_20, op11_8, 1, 0,
1167 (ins QPR:$src1, QPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
1168 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1169 [(set (ResTy QPR:$dst),
1170 (ResTy (ShOp (ResTy QPR:$src1),
1171 (ResTy (MulOp QPR:$src2,
1172 (ResTy (NEONvduplane (OpTy DPR_8:$src3),
1175 // Neon 3-argument intrinsics, both double- and quad-register.
1176 // The destination register is also used as the first source operand register.
1177 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1178 InstrItinClass itin, string OpcodeStr, string Dt,
1179 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1180 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1181 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin,
1182 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1183 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
1184 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
1185 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1186 InstrItinClass itin, string OpcodeStr, string Dt,
1187 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1188 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1189 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin,
1190 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1191 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
1192 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
1194 // Neon Long 3-argument intrinsic. The destination register is
1195 // a quad-register and is also used as the first source operand register.
1196 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1197 InstrItinClass itin, string OpcodeStr, string Dt,
1198 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
1199 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1200 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), itin,
1201 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1203 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
1204 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1205 string OpcodeStr, string Dt,
1206 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1207 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1209 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
1210 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1211 [(set (ResTy QPR:$dst),
1212 (ResTy (IntOp (ResTy QPR:$src1),
1214 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src3),
1216 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1217 InstrItinClass itin, string OpcodeStr, string Dt,
1218 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1219 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1221 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
1222 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1223 [(set (ResTy QPR:$dst),
1224 (ResTy (IntOp (ResTy QPR:$src1),
1226 (OpTy (NEONvduplane (OpTy DPR_8:$src3),
1229 // Narrowing 3-register intrinsics.
1230 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1231 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
1232 Intrinsic IntOp, bit Commutable>
1233 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1234 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VBINi4D,
1235 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1236 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
1237 let isCommutable = Commutable;
1240 // Long 3-register intrinsics.
1241 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1242 InstrItinClass itin, string OpcodeStr, string Dt,
1243 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
1244 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1245 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
1246 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1247 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
1248 let isCommutable = Commutable;
1250 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1251 string OpcodeStr, string Dt,
1252 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1253 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1254 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1255 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1256 [(set (ResTy QPR:$dst),
1257 (ResTy (IntOp (OpTy DPR:$src1),
1258 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1260 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1261 InstrItinClass itin, string OpcodeStr, string Dt,
1262 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1263 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1264 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1265 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1266 [(set (ResTy QPR:$dst),
1267 (ResTy (IntOp (OpTy DPR:$src1),
1268 (OpTy (NEONvduplane (OpTy DPR_8:$src2),
1271 // Wide 3-register intrinsics.
1272 class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1273 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
1274 Intrinsic IntOp, bit Commutable>
1275 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1276 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), IIC_VSUBiD,
1277 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1278 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
1279 let isCommutable = Commutable;
1282 // Pairwise long 2-register intrinsics, both double- and quad-register.
1283 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1284 bits<2> op17_16, bits<5> op11_7, bit op4,
1285 string OpcodeStr, string Dt,
1286 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1287 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1288 (ins DPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
1289 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
1290 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1291 bits<2> op17_16, bits<5> op11_7, bit op4,
1292 string OpcodeStr, string Dt,
1293 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1294 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1295 (ins QPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
1296 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
1298 // Pairwise long 2-register accumulate intrinsics,
1299 // both double- and quad-register.
1300 // The destination register is also used as the first source operand register.
1301 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1302 bits<2> op17_16, bits<5> op11_7, bit op4,
1303 string OpcodeStr, string Dt,
1304 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1305 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
1306 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), IIC_VPALiD,
1307 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
1308 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
1309 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1310 bits<2> op17_16, bits<5> op11_7, bit op4,
1311 string OpcodeStr, string Dt,
1312 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1313 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
1314 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VPALiQ,
1315 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
1316 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
1318 // Shift by immediate,
1319 // both double- and quad-register.
1320 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1321 InstrItinClass itin, string OpcodeStr, string Dt,
1322 ValueType Ty, SDNode OpNode>
1323 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1324 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), itin,
1325 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1326 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
1327 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1328 InstrItinClass itin, string OpcodeStr, string Dt,
1329 ValueType Ty, SDNode OpNode>
1330 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1331 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin,
1332 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1333 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
1335 // Long shift by immediate.
1336 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1337 string OpcodeStr, string Dt,
1338 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1339 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1340 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VSHLiD,
1341 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1342 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
1343 (i32 imm:$SIMM))))]>;
1345 // Narrow shift by immediate.
1346 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1347 InstrItinClass itin, string OpcodeStr, string Dt,
1348 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1349 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1350 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin,
1351 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1352 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
1353 (i32 imm:$SIMM))))]>;
1355 // Shift right by immediate and accumulate,
1356 // both double- and quad-register.
1357 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1358 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1359 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1360 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), IIC_VPALiD,
1361 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1362 [(set DPR:$dst, (Ty (add DPR:$src1,
1363 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
1364 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1365 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1366 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1367 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), IIC_VPALiD,
1368 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1369 [(set QPR:$dst, (Ty (add QPR:$src1,
1370 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
1372 // Shift by immediate and insert,
1373 // both double- and quad-register.
1374 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1375 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1376 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1377 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), IIC_VSHLiD,
1378 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1379 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
1380 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1381 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1382 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1383 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), IIC_VSHLiQ,
1384 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1385 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
1387 // Convert, with fractional bits immediate,
1388 // both double- and quad-register.
1389 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1390 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1392 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1393 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VUNAD,
1394 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1395 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
1396 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1397 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1399 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1400 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), IIC_VUNAQ,
1401 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1402 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
1404 //===----------------------------------------------------------------------===//
1406 //===----------------------------------------------------------------------===//
1408 // Abbreviations used in multiclass suffixes:
1409 // Q = quarter int (8 bit) elements
1410 // H = half int (16 bit) elements
1411 // S = single int (32 bit) elements
1412 // D = double int (64 bit) elements
1414 // Neon 2-register vector operations -- for disassembly only.
1416 // First with only element sizes of 8, 16 and 32 bits:
1417 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1418 bits<5> op11_7, bit op4, string opc, string Dt,
1420 // 64-bit vector types.
1421 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
1422 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1423 opc, !strconcat(Dt, "8"), asm, "", []>;
1424 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
1425 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1426 opc, !strconcat(Dt, "16"), asm, "", []>;
1427 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
1428 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1429 opc, !strconcat(Dt, "32"), asm, "", []>;
1430 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
1431 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1432 opc, "f32", asm, "", []> {
1433 let Inst{10} = 1; // overwrite F = 1
1436 // 128-bit vector types.
1437 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
1438 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1439 opc, !strconcat(Dt, "8"), asm, "", []>;
1440 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
1441 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1442 opc, !strconcat(Dt, "16"), asm, "", []>;
1443 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
1444 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1445 opc, !strconcat(Dt, "32"), asm, "", []>;
1446 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
1447 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1448 opc, "f32", asm, "", []> {
1449 let Inst{10} = 1; // overwrite F = 1
1453 // Neon 3-register vector operations.
1455 // First with only element sizes of 8, 16 and 32 bits:
1456 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1457 InstrItinClass itinD16, InstrItinClass itinD32,
1458 InstrItinClass itinQ16, InstrItinClass itinQ32,
1459 string OpcodeStr, string Dt,
1460 SDNode OpNode, bit Commutable = 0> {
1461 // 64-bit vector types.
1462 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
1463 OpcodeStr, !strconcat(Dt, "8"),
1464 v8i8, v8i8, OpNode, Commutable>;
1465 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
1466 OpcodeStr, !strconcat(Dt, "16"),
1467 v4i16, v4i16, OpNode, Commutable>;
1468 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
1469 OpcodeStr, !strconcat(Dt, "32"),
1470 v2i32, v2i32, OpNode, Commutable>;
1472 // 128-bit vector types.
1473 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
1474 OpcodeStr, !strconcat(Dt, "8"),
1475 v16i8, v16i8, OpNode, Commutable>;
1476 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
1477 OpcodeStr, !strconcat(Dt, "16"),
1478 v8i16, v8i16, OpNode, Commutable>;
1479 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
1480 OpcodeStr, !strconcat(Dt, "32"),
1481 v4i32, v4i32, OpNode, Commutable>;
1484 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
1485 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1487 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
1489 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1490 v8i16, v4i16, ShOp>;
1491 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
1492 v4i32, v2i32, ShOp>;
1495 // ....then also with element size 64 bits:
1496 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1497 InstrItinClass itinD, InstrItinClass itinQ,
1498 string OpcodeStr, string Dt,
1499 SDNode OpNode, bit Commutable = 0>
1500 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
1501 OpcodeStr, Dt, OpNode, Commutable> {
1502 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
1503 OpcodeStr, !strconcat(Dt, "64"),
1504 v1i64, v1i64, OpNode, Commutable>;
1505 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
1506 OpcodeStr, !strconcat(Dt, "64"),
1507 v2i64, v2i64, OpNode, Commutable>;
1511 // Neon Narrowing 2-register vector intrinsics,
1512 // source operand element sizes of 16, 32 and 64 bits:
1513 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1514 bits<5> op11_7, bit op6, bit op4,
1515 InstrItinClass itin, string OpcodeStr, string Dt,
1517 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
1518 itin, OpcodeStr, !strconcat(Dt, "16"),
1519 v8i8, v8i16, IntOp>;
1520 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
1521 itin, OpcodeStr, !strconcat(Dt, "32"),
1522 v4i16, v4i32, IntOp>;
1523 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
1524 itin, OpcodeStr, !strconcat(Dt, "64"),
1525 v2i32, v2i64, IntOp>;
1529 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
1530 // source operand element sizes of 16, 32 and 64 bits:
1531 multiclass N2VLInt_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
1532 string OpcodeStr, string Dt, Intrinsic IntOp> {
1533 def v8i16 : N2VLInt<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1534 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
1535 def v4i32 : N2VLInt<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1536 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1537 def v2i64 : N2VLInt<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1538 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1542 // Neon 3-register vector intrinsics.
1544 // First with only element sizes of 16 and 32 bits:
1545 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1546 InstrItinClass itinD16, InstrItinClass itinD32,
1547 InstrItinClass itinQ16, InstrItinClass itinQ32,
1548 string OpcodeStr, string Dt,
1549 Intrinsic IntOp, bit Commutable = 0> {
1550 // 64-bit vector types.
1551 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, itinD16,
1552 OpcodeStr, !strconcat(Dt, "16"),
1553 v4i16, v4i16, IntOp, Commutable>;
1554 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, itinD32,
1555 OpcodeStr, !strconcat(Dt, "32"),
1556 v2i32, v2i32, IntOp, Commutable>;
1558 // 128-bit vector types.
1559 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, itinQ16,
1560 OpcodeStr, !strconcat(Dt, "16"),
1561 v8i16, v8i16, IntOp, Commutable>;
1562 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, itinQ32,
1563 OpcodeStr, !strconcat(Dt, "32"),
1564 v4i32, v4i32, IntOp, Commutable>;
1567 multiclass N3VIntSL_HS<bits<4> op11_8,
1568 InstrItinClass itinD16, InstrItinClass itinD32,
1569 InstrItinClass itinQ16, InstrItinClass itinQ32,
1570 string OpcodeStr, string Dt, Intrinsic IntOp> {
1571 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
1572 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
1573 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
1574 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
1575 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
1576 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
1577 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
1578 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
1581 // ....then also with element size of 8 bits:
1582 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1583 InstrItinClass itinD16, InstrItinClass itinD32,
1584 InstrItinClass itinQ16, InstrItinClass itinQ32,
1585 string OpcodeStr, string Dt,
1586 Intrinsic IntOp, bit Commutable = 0>
1587 : N3VInt_HS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
1588 OpcodeStr, Dt, IntOp, Commutable> {
1589 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, itinD16,
1590 OpcodeStr, !strconcat(Dt, "8"),
1591 v8i8, v8i8, IntOp, Commutable>;
1592 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, itinQ16,
1593 OpcodeStr, !strconcat(Dt, "8"),
1594 v16i8, v16i8, IntOp, Commutable>;
1597 // ....then also with element size of 64 bits:
1598 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1599 InstrItinClass itinD16, InstrItinClass itinD32,
1600 InstrItinClass itinQ16, InstrItinClass itinQ32,
1601 string OpcodeStr, string Dt,
1602 Intrinsic IntOp, bit Commutable = 0>
1603 : N3VInt_QHS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
1604 OpcodeStr, Dt, IntOp, Commutable> {
1605 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, itinD32,
1606 OpcodeStr, !strconcat(Dt, "64"),
1607 v1i64, v1i64, IntOp, Commutable>;
1608 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, itinQ32,
1609 OpcodeStr, !strconcat(Dt, "64"),
1610 v2i64, v2i64, IntOp, Commutable>;
1614 // Neon Narrowing 3-register vector intrinsics,
1615 // source operand element sizes of 16, 32 and 64 bits:
1616 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1617 string OpcodeStr, string Dt,
1618 Intrinsic IntOp, bit Commutable = 0> {
1619 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
1620 OpcodeStr, !strconcat(Dt, "16"),
1621 v8i8, v8i16, IntOp, Commutable>;
1622 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
1623 OpcodeStr, !strconcat(Dt, "32"),
1624 v4i16, v4i32, IntOp, Commutable>;
1625 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
1626 OpcodeStr, !strconcat(Dt, "64"),
1627 v2i32, v2i64, IntOp, Commutable>;
1631 // Neon Long 3-register vector intrinsics.
1633 // First with only element sizes of 16 and 32 bits:
1634 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1635 InstrItinClass itin, string OpcodeStr, string Dt,
1636 Intrinsic IntOp, bit Commutable = 0> {
1637 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin,
1638 OpcodeStr, !strconcat(Dt, "16"),
1639 v4i32, v4i16, IntOp, Commutable>;
1640 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin,
1641 OpcodeStr, !strconcat(Dt, "32"),
1642 v2i64, v2i32, IntOp, Commutable>;
1645 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
1646 InstrItinClass itin, string OpcodeStr, string Dt,
1648 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
1649 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1650 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
1651 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1654 // ....then also with element size of 8 bits:
1655 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1656 InstrItinClass itin, string OpcodeStr, string Dt,
1657 Intrinsic IntOp, bit Commutable = 0>
1658 : N3VLInt_HS<op24, op23, op11_8, op4, itin, OpcodeStr, Dt,
1659 IntOp, Commutable> {
1660 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin,
1661 OpcodeStr, !strconcat(Dt, "8"),
1662 v8i16, v8i8, IntOp, Commutable>;
1666 // Neon Wide 3-register vector intrinsics,
1667 // source operand element sizes of 8, 16 and 32 bits:
1668 multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1669 string OpcodeStr, string Dt,
1670 Intrinsic IntOp, bit Commutable = 0> {
1671 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4,
1672 OpcodeStr, !strconcat(Dt, "8"),
1673 v8i16, v8i8, IntOp, Commutable>;
1674 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4,
1675 OpcodeStr, !strconcat(Dt, "16"),
1676 v4i32, v4i16, IntOp, Commutable>;
1677 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4,
1678 OpcodeStr, !strconcat(Dt, "32"),
1679 v2i64, v2i32, IntOp, Commutable>;
1683 // Neon Multiply-Op vector operations,
1684 // element sizes of 8, 16 and 32 bits:
1685 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1686 InstrItinClass itinD16, InstrItinClass itinD32,
1687 InstrItinClass itinQ16, InstrItinClass itinQ32,
1688 string OpcodeStr, string Dt, SDNode OpNode> {
1689 // 64-bit vector types.
1690 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
1691 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
1692 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
1693 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
1694 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
1695 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
1697 // 128-bit vector types.
1698 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
1699 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
1700 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
1701 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
1702 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
1703 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
1706 multiclass N3VMulOpSL_HS<bits<4> op11_8,
1707 InstrItinClass itinD16, InstrItinClass itinD32,
1708 InstrItinClass itinQ16, InstrItinClass itinQ32,
1709 string OpcodeStr, string Dt, SDNode ShOp> {
1710 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
1711 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
1712 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
1713 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
1714 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
1715 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
1717 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
1718 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
1722 // Neon 3-argument intrinsics,
1723 // element sizes of 8, 16 and 32 bits:
1724 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1725 string OpcodeStr, string Dt, Intrinsic IntOp> {
1726 // 64-bit vector types.
1727 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16D,
1728 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
1729 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
1730 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
1731 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32D,
1732 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
1734 // 128-bit vector types.
1735 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16Q,
1736 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
1737 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16Q,
1738 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
1739 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32Q,
1740 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
1744 // Neon Long 3-argument intrinsics.
1746 // First with only element sizes of 16 and 32 bits:
1747 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1748 string OpcodeStr, string Dt, Intrinsic IntOp> {
1749 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
1750 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1751 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi16D,
1752 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1755 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
1756 string OpcodeStr, string Dt, Intrinsic IntOp> {
1757 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
1758 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
1759 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
1760 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1763 // ....then also with element size of 8 bits:
1764 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1765 string OpcodeStr, string Dt, Intrinsic IntOp>
1766 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, Dt, IntOp> {
1767 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16D,
1768 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
1772 // Neon 2-register vector intrinsics,
1773 // element sizes of 8, 16 and 32 bits:
1774 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1775 bits<5> op11_7, bit op4,
1776 InstrItinClass itinD, InstrItinClass itinQ,
1777 string OpcodeStr, string Dt, Intrinsic IntOp> {
1778 // 64-bit vector types.
1779 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1780 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
1781 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1782 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
1783 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1784 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
1786 // 128-bit vector types.
1787 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1788 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
1789 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1790 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
1791 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1792 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
1796 // Neon Pairwise long 2-register intrinsics,
1797 // element sizes of 8, 16 and 32 bits:
1798 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1799 bits<5> op11_7, bit op4,
1800 string OpcodeStr, string Dt, Intrinsic IntOp> {
1801 // 64-bit vector types.
1802 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1803 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
1804 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1805 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
1806 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1807 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
1809 // 128-bit vector types.
1810 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1811 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
1812 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1813 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
1814 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1815 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
1819 // Neon Pairwise long 2-register accumulate intrinsics,
1820 // element sizes of 8, 16 and 32 bits:
1821 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1822 bits<5> op11_7, bit op4,
1823 string OpcodeStr, string Dt, Intrinsic IntOp> {
1824 // 64-bit vector types.
1825 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1826 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
1827 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1828 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
1829 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1830 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
1832 // 128-bit vector types.
1833 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1834 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
1835 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1836 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
1837 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1838 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
1842 // Neon 2-register vector shift by immediate,
1843 // element sizes of 8, 16, 32 and 64 bits:
1844 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1845 InstrItinClass itin, string OpcodeStr, string Dt,
1847 // 64-bit vector types.
1848 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
1849 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
1850 let Inst{21-19} = 0b001; // imm6 = 001xxx
1852 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
1853 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
1854 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1856 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
1857 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
1858 let Inst{21} = 0b1; // imm6 = 1xxxxx
1860 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, itin,
1861 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
1864 // 128-bit vector types.
1865 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
1866 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
1867 let Inst{21-19} = 0b001; // imm6 = 001xxx
1869 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
1870 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
1871 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1873 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
1874 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
1875 let Inst{21} = 0b1; // imm6 = 1xxxxx
1877 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, itin,
1878 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
1883 // Neon Shift-Accumulate vector operations,
1884 // element sizes of 8, 16, 32 and 64 bits:
1885 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1886 string OpcodeStr, string Dt, SDNode ShOp> {
1887 // 64-bit vector types.
1888 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1889 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
1890 let Inst{21-19} = 0b001; // imm6 = 001xxx
1892 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1893 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
1894 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1896 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1897 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
1898 let Inst{21} = 0b1; // imm6 = 1xxxxx
1900 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4,
1901 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
1904 // 128-bit vector types.
1905 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1906 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
1907 let Inst{21-19} = 0b001; // imm6 = 001xxx
1909 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1910 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
1911 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1913 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1914 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
1915 let Inst{21} = 0b1; // imm6 = 1xxxxx
1917 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4,
1918 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
1923 // Neon Shift-Insert vector operations,
1924 // element sizes of 8, 16, 32 and 64 bits:
1925 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1926 string OpcodeStr, SDNode ShOp> {
1927 // 64-bit vector types.
1928 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4,
1929 OpcodeStr, "8", v8i8, ShOp> {
1930 let Inst{21-19} = 0b001; // imm6 = 001xxx
1932 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4,
1933 OpcodeStr, "16", v4i16, ShOp> {
1934 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1936 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4,
1937 OpcodeStr, "32", v2i32, ShOp> {
1938 let Inst{21} = 0b1; // imm6 = 1xxxxx
1940 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4,
1941 OpcodeStr, "64", v1i64, ShOp>;
1944 // 128-bit vector types.
1945 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4,
1946 OpcodeStr, "8", v16i8, ShOp> {
1947 let Inst{21-19} = 0b001; // imm6 = 001xxx
1949 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4,
1950 OpcodeStr, "16", v8i16, ShOp> {
1951 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1953 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4,
1954 OpcodeStr, "32", v4i32, ShOp> {
1955 let Inst{21} = 0b1; // imm6 = 1xxxxx
1957 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4,
1958 OpcodeStr, "64", v2i64, ShOp>;
1962 // Neon Shift Long operations,
1963 // element sizes of 8, 16, 32 bits:
1964 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
1965 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
1966 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1967 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
1968 let Inst{21-19} = 0b001; // imm6 = 001xxx
1970 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1971 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
1972 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1974 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1975 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
1976 let Inst{21} = 0b1; // imm6 = 1xxxxx
1980 // Neon Shift Narrow operations,
1981 // element sizes of 16, 32, 64 bits:
1982 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
1983 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
1985 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1986 OpcodeStr, !strconcat(Dt, "16"), v8i8, v8i16, OpNode> {
1987 let Inst{21-19} = 0b001; // imm6 = 001xxx
1989 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1990 OpcodeStr, !strconcat(Dt, "32"), v4i16, v4i32, OpNode> {
1991 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1993 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1994 OpcodeStr, !strconcat(Dt, "64"), v2i32, v2i64, OpNode> {
1995 let Inst{21} = 0b1; // imm6 = 1xxxxx
1999 //===----------------------------------------------------------------------===//
2000 // Instruction Definitions.
2001 //===----------------------------------------------------------------------===//
2003 // Vector Add Operations.
2005 // VADD : Vector Add (integer and floating-point)
2006 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
2008 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
2009 v2f32, v2f32, fadd, 1>;
2010 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
2011 v4f32, v4f32, fadd, 1>;
2012 // VADDL : Vector Add Long (Q = D + D)
2013 defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, IIC_VSHLiD, "vaddl", "s",
2014 int_arm_neon_vaddls, 1>;
2015 defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, IIC_VSHLiD, "vaddl", "u",
2016 int_arm_neon_vaddlu, 1>;
2017 // VADDW : Vector Add Wide (Q = Q + D)
2018 defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw", "s", int_arm_neon_vaddws, 0>;
2019 defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw", "u", int_arm_neon_vaddwu, 0>;
2020 // VHADD : Vector Halving Add
2021 defm VHADDs : N3VInt_QHS<0,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2022 IIC_VBINi4Q, "vhadd", "s", int_arm_neon_vhadds, 1>;
2023 defm VHADDu : N3VInt_QHS<1,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2024 IIC_VBINi4Q, "vhadd", "u", int_arm_neon_vhaddu, 1>;
2025 // VRHADD : Vector Rounding Halving Add
2026 defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2027 IIC_VBINi4Q, "vrhadd", "s", int_arm_neon_vrhadds, 1>;
2028 defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2029 IIC_VBINi4Q, "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
2030 // VQADD : Vector Saturating Add
2031 defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2032 IIC_VBINi4Q, "vqadd", "s", int_arm_neon_vqadds, 1>;
2033 defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2034 IIC_VBINi4Q, "vqadd", "u", int_arm_neon_vqaddu, 1>;
2035 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
2036 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
2037 int_arm_neon_vaddhn, 1>;
2038 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
2039 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
2040 int_arm_neon_vraddhn, 1>;
2042 // Vector Multiply Operations.
2044 // VMUL : Vector Multiply (integer, polynomial and floating-point)
2045 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
2046 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
2047 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16D, "vmul", "p8",
2048 v8i8, v8i8, int_arm_neon_vmulp, 1>;
2049 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16Q, "vmul", "p8",
2050 v16i8, v16i8, int_arm_neon_vmulp, 1>;
2051 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VBIND, "vmul", "f32",
2052 v2f32, v2f32, fmul, 1>;
2053 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VBINQ, "vmul", "f32",
2054 v4f32, v4f32, fmul, 1>;
2055 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
2056 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
2057 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
2060 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
2061 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
2062 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
2063 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2064 (DSubReg_i16_reg imm:$lane))),
2065 (SubReg_i16_lane imm:$lane)))>;
2066 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
2067 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
2068 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
2069 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2070 (DSubReg_i32_reg imm:$lane))),
2071 (SubReg_i32_lane imm:$lane)))>;
2072 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
2073 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
2074 (v4f32 (VMULslfq (v4f32 QPR:$src1),
2075 (v2f32 (EXTRACT_SUBREG QPR:$src2,
2076 (DSubReg_i32_reg imm:$lane))),
2077 (SubReg_i32_lane imm:$lane)))>;
2079 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
2080 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
2081 IIC_VMULi16Q, IIC_VMULi32Q,
2082 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
2083 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
2084 IIC_VMULi16Q, IIC_VMULi32Q,
2085 "vqdmulh", "s", int_arm_neon_vqdmulh>;
2086 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
2087 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
2089 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
2090 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2091 (DSubReg_i16_reg imm:$lane))),
2092 (SubReg_i16_lane imm:$lane)))>;
2093 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
2094 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
2096 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
2097 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2098 (DSubReg_i32_reg imm:$lane))),
2099 (SubReg_i32_lane imm:$lane)))>;
2101 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
2102 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
2103 IIC_VMULi16Q, IIC_VMULi32Q,
2104 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
2105 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
2106 IIC_VMULi16Q, IIC_VMULi32Q,
2107 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
2108 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
2109 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
2111 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
2112 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2113 (DSubReg_i16_reg imm:$lane))),
2114 (SubReg_i16_lane imm:$lane)))>;
2115 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
2116 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
2118 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
2119 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2120 (DSubReg_i32_reg imm:$lane))),
2121 (SubReg_i32_lane imm:$lane)))>;
2123 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
2124 defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, IIC_VMULi16D, "vmull", "s",
2125 int_arm_neon_vmulls, 1>;
2126 defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, IIC_VMULi16D, "vmull", "u",
2127 int_arm_neon_vmullu, 1>;
2128 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
2129 v8i16, v8i8, int_arm_neon_vmullp, 1>;
2130 defm VMULLsls : N3VLIntSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s",
2131 int_arm_neon_vmulls>;
2132 defm VMULLslu : N3VLIntSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u",
2133 int_arm_neon_vmullu>;
2135 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
2136 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, "vqdmull", "s",
2137 int_arm_neon_vqdmull, 1>;
2138 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D, "vqdmull", "s",
2139 int_arm_neon_vqdmull>;
2141 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
2143 // VMLA : Vector Multiply Accumulate (integer and floating-point)
2144 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
2145 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
2146 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
2148 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
2150 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
2151 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
2152 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
2154 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
2155 v4f32, v2f32, fmul, fadd>;
2157 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
2158 (mul (v8i16 QPR:$src2),
2159 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
2160 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
2161 (v4i16 (EXTRACT_SUBREG QPR:$src3,
2162 (DSubReg_i16_reg imm:$lane))),
2163 (SubReg_i16_lane imm:$lane)))>;
2165 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
2166 (mul (v4i32 QPR:$src2),
2167 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
2168 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
2169 (v2i32 (EXTRACT_SUBREG QPR:$src3,
2170 (DSubReg_i32_reg imm:$lane))),
2171 (SubReg_i32_lane imm:$lane)))>;
2173 def : Pat<(v4f32 (fadd (v4f32 QPR:$src1),
2174 (fmul (v4f32 QPR:$src2),
2175 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
2176 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
2178 (v2f32 (EXTRACT_SUBREG QPR:$src3,
2179 (DSubReg_i32_reg imm:$lane))),
2180 (SubReg_i32_lane imm:$lane)))>;
2182 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
2183 defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal", "s", int_arm_neon_vmlals>;
2184 defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal", "u", int_arm_neon_vmlalu>;
2186 defm VMLALsls : N3VLInt3SL_HS<0, 0b0010, "vmlal", "s", int_arm_neon_vmlals>;
2187 defm VMLALslu : N3VLInt3SL_HS<1, 0b0010, "vmlal", "u", int_arm_neon_vmlalu>;
2189 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
2190 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal", "s",
2191 int_arm_neon_vqdmlal>;
2192 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
2194 // VMLS : Vector Multiply Subtract (integer and floating-point)
2195 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
2196 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
2197 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
2199 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
2201 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
2202 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
2203 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
2205 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
2206 v4f32, v2f32, fmul, fsub>;
2208 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
2209 (mul (v8i16 QPR:$src2),
2210 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
2211 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
2212 (v4i16 (EXTRACT_SUBREG QPR:$src3,
2213 (DSubReg_i16_reg imm:$lane))),
2214 (SubReg_i16_lane imm:$lane)))>;
2216 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
2217 (mul (v4i32 QPR:$src2),
2218 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
2219 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
2220 (v2i32 (EXTRACT_SUBREG QPR:$src3,
2221 (DSubReg_i32_reg imm:$lane))),
2222 (SubReg_i32_lane imm:$lane)))>;
2224 def : Pat<(v4f32 (fsub (v4f32 QPR:$src1),
2225 (fmul (v4f32 QPR:$src2),
2226 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
2227 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
2228 (v2f32 (EXTRACT_SUBREG QPR:$src3,
2229 (DSubReg_i32_reg imm:$lane))),
2230 (SubReg_i32_lane imm:$lane)))>;
2232 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
2233 defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl", "s", int_arm_neon_vmlsls>;
2234 defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl", "u", int_arm_neon_vmlslu>;
2236 defm VMLSLsls : N3VLInt3SL_HS<0, 0b0110, "vmlsl", "s", int_arm_neon_vmlsls>;
2237 defm VMLSLslu : N3VLInt3SL_HS<1, 0b0110, "vmlsl", "u", int_arm_neon_vmlslu>;
2239 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
2240 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl", "s",
2241 int_arm_neon_vqdmlsl>;
2242 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
2244 // Vector Subtract Operations.
2246 // VSUB : Vector Subtract (integer and floating-point)
2247 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
2248 "vsub", "i", sub, 0>;
2249 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
2250 v2f32, v2f32, fsub, 0>;
2251 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
2252 v4f32, v4f32, fsub, 0>;
2253 // VSUBL : Vector Subtract Long (Q = D - D)
2254 defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, IIC_VSHLiD, "vsubl", "s",
2255 int_arm_neon_vsubls, 1>;
2256 defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, IIC_VSHLiD, "vsubl", "u",
2257 int_arm_neon_vsublu, 1>;
2258 // VSUBW : Vector Subtract Wide (Q = Q - D)
2259 defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw", "s", int_arm_neon_vsubws, 0>;
2260 defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw", "u", int_arm_neon_vsubwu, 0>;
2261 // VHSUB : Vector Halving Subtract
2262 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D,
2263 IIC_VBINi4Q, IIC_VBINi4Q,
2264 "vhsub", "s", int_arm_neon_vhsubs, 0>;
2265 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D,
2266 IIC_VBINi4Q, IIC_VBINi4Q,
2267 "vhsub", "u", int_arm_neon_vhsubu, 0>;
2268 // VQSUB : Vector Saturing Subtract
2269 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D,
2270 IIC_VBINi4Q, IIC_VBINi4Q,
2271 "vqsub", "s", int_arm_neon_vqsubs, 0>;
2272 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D,
2273 IIC_VBINi4Q, IIC_VBINi4Q,
2274 "vqsub", "u", int_arm_neon_vqsubu, 0>;
2275 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
2276 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
2277 int_arm_neon_vsubhn, 0>;
2278 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
2279 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
2280 int_arm_neon_vrsubhn, 0>;
2282 // Vector Comparisons.
2284 // VCEQ : Vector Compare Equal
2285 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2286 IIC_VBINi4Q, "vceq", "i", NEONvceq, 1>;
2287 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
2289 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
2291 // For disassembly only.
2292 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
2295 // VCGE : Vector Compare Greater Than or Equal
2296 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2297 IIC_VBINi4Q, "vcge", "s", NEONvcge, 0>;
2298 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2299 IIC_VBINi4Q, "vcge", "u", NEONvcgeu, 0>;
2300 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32",
2301 v2i32, v2f32, NEONvcge, 0>;
2302 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
2304 // For disassembly only.
2305 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
2307 // For disassembly only.
2308 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
2311 // VCGT : Vector Compare Greater Than
2312 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2313 IIC_VBINi4Q, "vcgt", "s", NEONvcgt, 0>;
2314 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2315 IIC_VBINi4Q, "vcgt", "u", NEONvcgtu, 0>;
2316 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
2318 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
2320 // For disassembly only.
2321 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
2323 // For disassembly only.
2324 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
2327 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
2328 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, IIC_VBIND, "vacge", "f32",
2329 v2i32, v2f32, int_arm_neon_vacged, 0>;
2330 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, IIC_VBINQ, "vacge", "f32",
2331 v4i32, v4f32, int_arm_neon_vacgeq, 0>;
2332 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
2333 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, IIC_VBIND, "vacgt", "f32",
2334 v2i32, v2f32, int_arm_neon_vacgtd, 0>;
2335 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, IIC_VBINQ, "vacgt", "f32",
2336 v4i32, v4f32, int_arm_neon_vacgtq, 0>;
2337 // VTST : Vector Test Bits
2338 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2339 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
2341 // Vector Bitwise Operations.
2343 // VAND : Vector Bitwise AND
2344 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
2345 v2i32, v2i32, and, 1>;
2346 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
2347 v4i32, v4i32, and, 1>;
2349 // VEOR : Vector Bitwise Exclusive OR
2350 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
2351 v2i32, v2i32, xor, 1>;
2352 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
2353 v4i32, v4i32, xor, 1>;
2355 // VORR : Vector Bitwise OR
2356 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
2357 v2i32, v2i32, or, 1>;
2358 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
2359 v4i32, v4i32, or, 1>;
2361 // VBIC : Vector Bitwise Bit Clear (AND NOT)
2362 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2363 (ins DPR:$src1, DPR:$src2), IIC_VBINiD,
2364 "vbic", "$dst, $src1, $src2", "",
2365 [(set DPR:$dst, (v2i32 (and DPR:$src1,
2366 (vnot_conv DPR:$src2))))]>;
2367 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2368 (ins QPR:$src1, QPR:$src2), IIC_VBINiQ,
2369 "vbic", "$dst, $src1, $src2", "",
2370 [(set QPR:$dst, (v4i32 (and QPR:$src1,
2371 (vnot_conv QPR:$src2))))]>;
2373 // VORN : Vector Bitwise OR NOT
2374 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
2375 (ins DPR:$src1, DPR:$src2), IIC_VBINiD,
2376 "vorn", "$dst, $src1, $src2", "",
2377 [(set DPR:$dst, (v2i32 (or DPR:$src1,
2378 (vnot_conv DPR:$src2))))]>;
2379 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
2380 (ins QPR:$src1, QPR:$src2), IIC_VBINiQ,
2381 "vorn", "$dst, $src1, $src2", "",
2382 [(set QPR:$dst, (v4i32 (or QPR:$src1,
2383 (vnot_conv QPR:$src2))))]>;
2385 // VMVN : Vector Bitwise NOT
2386 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
2387 (outs DPR:$dst), (ins DPR:$src), IIC_VSHLiD,
2388 "vmvn", "$dst, $src", "",
2389 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>;
2390 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
2391 (outs QPR:$dst), (ins QPR:$src), IIC_VSHLiD,
2392 "vmvn", "$dst, $src", "",
2393 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>;
2394 def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>;
2395 def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>;
2397 // VBSL : Vector Bitwise Select
2398 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2399 (ins DPR:$src1, DPR:$src2, DPR:$src3), IIC_VCNTiD,
2400 "vbsl", "$dst, $src2, $src3", "$src1 = $dst",
2402 (v2i32 (or (and DPR:$src2, DPR:$src1),
2403 (and DPR:$src3, (vnot_conv DPR:$src1)))))]>;
2404 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2405 (ins QPR:$src1, QPR:$src2, QPR:$src3), IIC_VCNTiQ,
2406 "vbsl", "$dst, $src2, $src3", "$src1 = $dst",
2408 (v4i32 (or (and QPR:$src2, QPR:$src1),
2409 (and QPR:$src3, (vnot_conv QPR:$src1)))))]>;
2411 // VBIF : Vector Bitwise Insert if False
2412 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
2413 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
2414 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
2415 IIC_VBINiD, "vbif", "$dst, $src2, $src3", "$src1 = $dst",
2416 [/* For disassembly only; pattern left blank */]>;
2417 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
2418 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
2419 IIC_VBINiQ, "vbif", "$dst, $src2, $src3", "$src1 = $dst",
2420 [/* For disassembly only; pattern left blank */]>;
2422 // VBIT : Vector Bitwise Insert if True
2423 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
2424 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
2425 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
2426 IIC_VBINiD, "vbit", "$dst, $src2, $src3", "$src1 = $dst",
2427 [/* For disassembly only; pattern left blank */]>;
2428 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
2429 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
2430 IIC_VBINiQ, "vbit", "$dst, $src2, $src3", "$src1 = $dst",
2431 [/* For disassembly only; pattern left blank */]>;
2433 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
2434 // for equivalent operations with different register constraints; it just
2437 // Vector Absolute Differences.
2439 // VABD : Vector Absolute Difference
2440 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D,
2441 IIC_VBINi4Q, IIC_VBINi4Q,
2442 "vabd", "s", int_arm_neon_vabds, 0>;
2443 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D,
2444 IIC_VBINi4Q, IIC_VBINi4Q,
2445 "vabd", "u", int_arm_neon_vabdu, 0>;
2446 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, IIC_VBIND,
2447 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 0>;
2448 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, IIC_VBINQ,
2449 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 0>;
2451 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
2452 defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, IIC_VBINi4Q,
2453 "vabdl", "s", int_arm_neon_vabdls, 0>;
2454 defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, IIC_VBINi4Q,
2455 "vabdl", "u", int_arm_neon_vabdlu, 0>;
2457 // VABA : Vector Absolute Difference and Accumulate
2458 defm VABAs : N3VInt3_QHS<0,0,0b0111,1, "vaba", "s", int_arm_neon_vabas>;
2459 defm VABAu : N3VInt3_QHS<1,0,0b0111,1, "vaba", "u", int_arm_neon_vabau>;
2461 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
2462 defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal", "s", int_arm_neon_vabals>;
2463 defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal", "u", int_arm_neon_vabalu>;
2465 // Vector Maximum and Minimum.
2467 // VMAX : Vector Maximum
2468 defm VMAXs : N3VInt_QHS<0,0,0b0110,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2469 IIC_VBINi4Q, "vmax", "s", int_arm_neon_vmaxs, 1>;
2470 defm VMAXu : N3VInt_QHS<1,0,0b0110,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2471 IIC_VBINi4Q, "vmax", "u", int_arm_neon_vmaxu, 1>;
2472 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, IIC_VBIND, "vmax", "f32",
2473 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
2474 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, IIC_VBINQ, "vmax", "f32",
2475 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
2477 // VMIN : Vector Minimum
2478 defm VMINs : N3VInt_QHS<0,0,0b0110,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2479 IIC_VBINi4Q, "vmin", "s", int_arm_neon_vmins, 1>;
2480 defm VMINu : N3VInt_QHS<1,0,0b0110,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2481 IIC_VBINi4Q, "vmin", "u", int_arm_neon_vminu, 1>;
2482 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, IIC_VBIND, "vmin", "f32",
2483 v2f32, v2f32, int_arm_neon_vmins, 1>;
2484 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, IIC_VBINQ, "vmin", "f32",
2485 v4f32, v4f32, int_arm_neon_vmins, 1>;
2487 // Vector Pairwise Operations.
2489 // VPADD : Vector Pairwise Add
2490 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, IIC_VBINiD, "vpadd", "i8",
2491 v8i8, v8i8, int_arm_neon_vpadd, 0>;
2492 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, IIC_VBINiD, "vpadd", "i16",
2493 v4i16, v4i16, int_arm_neon_vpadd, 0>;
2494 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, IIC_VBINiD, "vpadd", "i32",
2495 v2i32, v2i32, int_arm_neon_vpadd, 0>;
2496 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, IIC_VBIND, "vpadd", "f32",
2497 v2f32, v2f32, int_arm_neon_vpadd, 0>;
2499 // VPADDL : Vector Pairwise Add Long
2500 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
2501 int_arm_neon_vpaddls>;
2502 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
2503 int_arm_neon_vpaddlu>;
2505 // VPADAL : Vector Pairwise Add and Accumulate Long
2506 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
2507 int_arm_neon_vpadals>;
2508 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
2509 int_arm_neon_vpadalu>;
2511 // VPMAX : Vector Pairwise Maximum
2512 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax", "s8",
2513 v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
2514 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax", "s16",
2515 v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
2516 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax", "s32",
2517 v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
2518 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax", "u8",
2519 v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
2520 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax", "u16",
2521 v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
2522 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax", "u32",
2523 v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
2524 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, IIC_VBINi4D, "vpmax", "f32",
2525 v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
2527 // VPMIN : Vector Pairwise Minimum
2528 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin", "s8",
2529 v8i8, v8i8, int_arm_neon_vpmins, 0>;
2530 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin", "s16",
2531 v4i16, v4i16, int_arm_neon_vpmins, 0>;
2532 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin", "s32",
2533 v2i32, v2i32, int_arm_neon_vpmins, 0>;
2534 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin", "u8",
2535 v8i8, v8i8, int_arm_neon_vpminu, 0>;
2536 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin", "u16",
2537 v4i16, v4i16, int_arm_neon_vpminu, 0>;
2538 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin", "u32",
2539 v2i32, v2i32, int_arm_neon_vpminu, 0>;
2540 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, IIC_VBINi4D, "vpmin", "f32",
2541 v2f32, v2f32, int_arm_neon_vpmins, 0>;
2543 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
2545 // VRECPE : Vector Reciprocal Estimate
2546 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
2547 IIC_VUNAD, "vrecpe", "u32",
2548 v2i32, v2i32, int_arm_neon_vrecpe>;
2549 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
2550 IIC_VUNAQ, "vrecpe", "u32",
2551 v4i32, v4i32, int_arm_neon_vrecpe>;
2552 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
2553 IIC_VUNAD, "vrecpe", "f32",
2554 v2f32, v2f32, int_arm_neon_vrecpe>;
2555 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
2556 IIC_VUNAQ, "vrecpe", "f32",
2557 v4f32, v4f32, int_arm_neon_vrecpe>;
2559 // VRECPS : Vector Reciprocal Step
2560 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1,
2561 IIC_VRECSD, "vrecps", "f32",
2562 v2f32, v2f32, int_arm_neon_vrecps, 1>;
2563 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1,
2564 IIC_VRECSQ, "vrecps", "f32",
2565 v4f32, v4f32, int_arm_neon_vrecps, 1>;
2567 // VRSQRTE : Vector Reciprocal Square Root Estimate
2568 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
2569 IIC_VUNAD, "vrsqrte", "u32",
2570 v2i32, v2i32, int_arm_neon_vrsqrte>;
2571 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
2572 IIC_VUNAQ, "vrsqrte", "u32",
2573 v4i32, v4i32, int_arm_neon_vrsqrte>;
2574 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
2575 IIC_VUNAD, "vrsqrte", "f32",
2576 v2f32, v2f32, int_arm_neon_vrsqrte>;
2577 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
2578 IIC_VUNAQ, "vrsqrte", "f32",
2579 v4f32, v4f32, int_arm_neon_vrsqrte>;
2581 // VRSQRTS : Vector Reciprocal Square Root Step
2582 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1,
2583 IIC_VRECSD, "vrsqrts", "f32",
2584 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
2585 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1,
2586 IIC_VRECSQ, "vrsqrts", "f32",
2587 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
2591 // VSHL : Vector Shift
2592 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
2593 IIC_VSHLiQ, "vshl", "s", int_arm_neon_vshifts, 0>;
2594 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
2595 IIC_VSHLiQ, "vshl", "u", int_arm_neon_vshiftu, 0>;
2596 // VSHL : Vector Shift Left (Immediate)
2597 defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
2598 // VSHR : Vector Shift Right (Immediate)
2599 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", NEONvshrs>;
2600 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", NEONvshru>;
2602 // VSHLL : Vector Shift Left Long
2603 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
2604 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
2606 // VSHLL : Vector Shift Left Long (with maximum shift count)
2607 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
2608 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
2609 ValueType OpTy, SDNode OpNode>
2610 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
2611 ResTy, OpTy, OpNode> {
2612 let Inst{21-16} = op21_16;
2614 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
2615 v8i16, v8i8, NEONvshlli>;
2616 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
2617 v4i32, v4i16, NEONvshlli>;
2618 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
2619 v2i64, v2i32, NEONvshlli>;
2621 // VSHRN : Vector Shift Right and Narrow
2622 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
2625 // VRSHL : Vector Rounding Shift
2626 defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2627 IIC_VSHLi4Q, "vrshl", "s", int_arm_neon_vrshifts,0>;
2628 defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2629 IIC_VSHLi4Q, "vrshl", "u", int_arm_neon_vrshiftu,0>;
2630 // VRSHR : Vector Rounding Shift Right
2631 defm VRSHRs : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs>;
2632 defm VRSHRu : N2VSh_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", NEONvrshru>;
2634 // VRSHRN : Vector Rounding Shift Right and Narrow
2635 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
2638 // VQSHL : Vector Saturating Shift
2639 defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2640 IIC_VSHLi4Q, "vqshl", "s", int_arm_neon_vqshifts,0>;
2641 defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2642 IIC_VSHLi4Q, "vqshl", "u", int_arm_neon_vqshiftu,0>;
2643 // VQSHL : Vector Saturating Shift Left (Immediate)
2644 defm VQSHLsi : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s", NEONvqshls>;
2645 defm VQSHLui : N2VSh_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u", NEONvqshlu>;
2646 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
2647 defm VQSHLsu : N2VSh_QHSD<1,1,0b0110,1, IIC_VSHLi4D, "vqshlu","s",NEONvqshlsu>;
2649 // VQSHRN : Vector Saturating Shift Right and Narrow
2650 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
2652 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
2655 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
2656 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
2659 // VQRSHL : Vector Saturating Rounding Shift
2660 defm VQRSHLs : N3VInt_QHSD<0,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2661 IIC_VSHLi4Q, "vqrshl", "s",
2662 int_arm_neon_vqrshifts, 0>;
2663 defm VQRSHLu : N3VInt_QHSD<1,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2664 IIC_VSHLi4Q, "vqrshl", "u",
2665 int_arm_neon_vqrshiftu, 0>;
2667 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
2668 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
2670 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
2673 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
2674 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
2677 // VSRA : Vector Shift Right and Accumulate
2678 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
2679 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
2680 // VRSRA : Vector Rounding Shift Right and Accumulate
2681 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
2682 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
2684 // VSLI : Vector Shift Left and Insert
2685 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli", NEONvsli>;
2686 // VSRI : Vector Shift Right and Insert
2687 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri", NEONvsri>;
2689 // Vector Absolute and Saturating Absolute.
2691 // VABS : Vector Absolute Value
2692 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
2693 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
2695 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2696 IIC_VUNAD, "vabs", "f32",
2697 v2f32, v2f32, int_arm_neon_vabs>;
2698 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2699 IIC_VUNAQ, "vabs", "f32",
2700 v4f32, v4f32, int_arm_neon_vabs>;
2702 // VQABS : Vector Saturating Absolute Value
2703 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
2704 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
2705 int_arm_neon_vqabs>;
2709 def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
2710 def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>;
2712 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
2713 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
2714 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
2715 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>;
2716 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
2717 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
2718 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
2719 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>;
2721 // VNEG : Vector Negate
2722 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
2723 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
2724 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
2725 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
2726 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
2727 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
2729 // VNEG : Vector Negate (floating-point)
2730 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
2731 (outs DPR:$dst), (ins DPR:$src), IIC_VUNAD,
2732 "vneg", "f32", "$dst, $src", "",
2733 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
2734 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
2735 (outs QPR:$dst), (ins QPR:$src), IIC_VUNAQ,
2736 "vneg", "f32", "$dst, $src", "",
2737 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
2739 def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
2740 def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
2741 def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>;
2742 def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>;
2743 def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>;
2744 def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>;
2746 // VQNEG : Vector Saturating Negate
2747 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
2748 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
2749 int_arm_neon_vqneg>;
2751 // Vector Bit Counting Operations.
2753 // VCLS : Vector Count Leading Sign Bits
2754 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
2755 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
2757 // VCLZ : Vector Count Leading Zeros
2758 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
2759 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
2761 // VCNT : Vector Count One Bits
2762 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2763 IIC_VCNTiD, "vcnt", "8",
2764 v8i8, v8i8, int_arm_neon_vcnt>;
2765 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2766 IIC_VCNTiQ, "vcnt", "8",
2767 v16i8, v16i8, int_arm_neon_vcnt>;
2769 // Vector Swap -- for disassembly only.
2770 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
2771 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
2772 "vswp", "$dst, $src", "", []>;
2773 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
2774 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
2775 "vswp", "$dst, $src", "", []>;
2777 // Vector Move Operations.
2779 // VMOV : Vector Move (Register)
2781 def VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
2782 IIC_VMOVD, "vmov", "$dst, $src", "", []>;
2783 def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
2784 IIC_VMOVD, "vmov", "$dst, $src", "", []>;
2786 // VMOV : Vector Move (Immediate)
2788 // VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
2789 def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
2790 return ARM::getVMOVImm(N, 1, *CurDAG);
2792 def vmovImm8 : PatLeaf<(build_vector), [{
2793 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
2796 // VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
2797 def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
2798 return ARM::getVMOVImm(N, 2, *CurDAG);
2800 def vmovImm16 : PatLeaf<(build_vector), [{
2801 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
2802 }], VMOV_get_imm16>;
2804 // VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
2805 def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
2806 return ARM::getVMOVImm(N, 4, *CurDAG);
2808 def vmovImm32 : PatLeaf<(build_vector), [{
2809 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
2810 }], VMOV_get_imm32>;
2812 // VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
2813 def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
2814 return ARM::getVMOVImm(N, 8, *CurDAG);
2816 def vmovImm64 : PatLeaf<(build_vector), [{
2817 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
2818 }], VMOV_get_imm64>;
2820 // Note: Some of the cmode bits in the following VMOV instructions need to
2821 // be encoded based on the immed values.
2823 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
2824 (ins h8imm:$SIMM), IIC_VMOVImm,
2825 "vmov", "i8", "$dst, $SIMM", "",
2826 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
2827 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
2828 (ins h8imm:$SIMM), IIC_VMOVImm,
2829 "vmov", "i8", "$dst, $SIMM", "",
2830 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
2832 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,?}, 0, 0, {?}, 1, (outs DPR:$dst),
2833 (ins h16imm:$SIMM), IIC_VMOVImm,
2834 "vmov", "i16", "$dst, $SIMM", "",
2835 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
2836 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,?}, 0, 1, {?}, 1, (outs QPR:$dst),
2837 (ins h16imm:$SIMM), IIC_VMOVImm,
2838 "vmov", "i16", "$dst, $SIMM", "",
2839 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
2841 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, {?}, 1, (outs DPR:$dst),
2842 (ins h32imm:$SIMM), IIC_VMOVImm,
2843 "vmov", "i32", "$dst, $SIMM", "",
2844 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
2845 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, {?}, 1, (outs QPR:$dst),
2846 (ins h32imm:$SIMM), IIC_VMOVImm,
2847 "vmov", "i32", "$dst, $SIMM", "",
2848 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
2850 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
2851 (ins h64imm:$SIMM), IIC_VMOVImm,
2852 "vmov", "i64", "$dst, $SIMM", "",
2853 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
2854 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
2855 (ins h64imm:$SIMM), IIC_VMOVImm,
2856 "vmov", "i64", "$dst, $SIMM", "",
2857 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
2859 // VMOV : Vector Get Lane (move scalar to ARM core register)
2861 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
2862 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2863 IIC_VMOVSI, "vmov", "s8", "$dst, $src[$lane]",
2864 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
2866 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
2867 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2868 IIC_VMOVSI, "vmov", "s16", "$dst, $src[$lane]",
2869 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
2871 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
2872 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2873 IIC_VMOVSI, "vmov", "u8", "$dst, $src[$lane]",
2874 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
2876 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
2877 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2878 IIC_VMOVSI, "vmov", "u16", "$dst, $src[$lane]",
2879 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
2881 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
2882 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2883 IIC_VMOVSI, "vmov", "32", "$dst, $src[$lane]",
2884 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
2886 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
2887 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
2888 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2889 (DSubReg_i8_reg imm:$lane))),
2890 (SubReg_i8_lane imm:$lane))>;
2891 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
2892 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2893 (DSubReg_i16_reg imm:$lane))),
2894 (SubReg_i16_lane imm:$lane))>;
2895 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
2896 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2897 (DSubReg_i8_reg imm:$lane))),
2898 (SubReg_i8_lane imm:$lane))>;
2899 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
2900 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2901 (DSubReg_i16_reg imm:$lane))),
2902 (SubReg_i16_lane imm:$lane))>;
2903 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
2904 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
2905 (DSubReg_i32_reg imm:$lane))),
2906 (SubReg_i32_lane imm:$lane))>;
2907 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
2908 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
2909 (SSubReg_f32_reg imm:$src2))>;
2910 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
2911 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
2912 (SSubReg_f32_reg imm:$src2))>;
2913 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
2914 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2915 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
2916 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2919 // VMOV : Vector Set Lane (move ARM core register to scalar)
2921 let Constraints = "$src1 = $dst" in {
2922 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$dst),
2923 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2924 IIC_VMOVISL, "vmov", "8", "$dst[$lane], $src2",
2925 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
2926 GPR:$src2, imm:$lane))]>;
2927 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$dst),
2928 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2929 IIC_VMOVISL, "vmov", "16", "$dst[$lane], $src2",
2930 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
2931 GPR:$src2, imm:$lane))]>;
2932 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$dst),
2933 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2934 IIC_VMOVISL, "vmov", "32", "$dst[$lane], $src2",
2935 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
2936 GPR:$src2, imm:$lane))]>;
2938 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
2939 (v16i8 (INSERT_SUBREG QPR:$src1,
2940 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
2941 (DSubReg_i8_reg imm:$lane))),
2942 GPR:$src2, (SubReg_i8_lane imm:$lane))),
2943 (DSubReg_i8_reg imm:$lane)))>;
2944 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
2945 (v8i16 (INSERT_SUBREG QPR:$src1,
2946 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
2947 (DSubReg_i16_reg imm:$lane))),
2948 GPR:$src2, (SubReg_i16_lane imm:$lane))),
2949 (DSubReg_i16_reg imm:$lane)))>;
2950 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
2951 (v4i32 (INSERT_SUBREG QPR:$src1,
2952 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
2953 (DSubReg_i32_reg imm:$lane))),
2954 GPR:$src2, (SubReg_i32_lane imm:$lane))),
2955 (DSubReg_i32_reg imm:$lane)))>;
2957 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
2958 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
2959 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
2960 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
2961 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
2962 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
2964 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
2965 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
2966 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
2967 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
2969 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
2970 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
2971 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
2972 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, arm_dsubreg_0)>;
2973 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
2974 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
2976 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
2977 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2978 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
2979 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2980 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
2981 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2983 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
2984 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
2985 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2987 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
2988 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
2989 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2991 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
2992 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
2993 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2996 // VDUP : Vector Duplicate (from ARM core register to all elements)
2998 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
2999 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
3000 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
3001 [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
3002 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
3003 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
3004 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
3005 [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
3007 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
3008 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
3009 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
3010 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
3011 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
3012 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
3014 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
3015 IIC_VMOVIS, "vdup", "32", "$dst, $src",
3016 [(set DPR:$dst, (v2f32 (NEONvdup
3017 (f32 (bitconvert GPR:$src)))))]>;
3018 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
3019 IIC_VMOVIS, "vdup", "32", "$dst, $src",
3020 [(set QPR:$dst, (v4f32 (NEONvdup
3021 (f32 (bitconvert GPR:$src)))))]>;
3023 // VDUP : Vector Duplicate Lane (from scalar to all elements)
3025 class VDUPLND<bits<2> op19_18, bits<2> op17_16,
3026 string OpcodeStr, string Dt, ValueType Ty>
3027 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
3028 (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
3029 OpcodeStr, Dt, "$dst, $src[$lane]", "",
3030 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
3032 class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, string Dt,
3033 ValueType ResTy, ValueType OpTy>
3034 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
3035 (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
3036 OpcodeStr, Dt, "$dst, $src[$lane]", "",
3037 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src), imm:$lane)))]>;
3039 // Inst{19-16} is partially specified depending on the element size.
3041 def VDUPLN8d : VDUPLND<{?,?}, {?,1}, "vdup", "8", v8i8>;
3042 def VDUPLN16d : VDUPLND<{?,?}, {1,0}, "vdup", "16", v4i16>;
3043 def VDUPLN32d : VDUPLND<{?,1}, {0,0}, "vdup", "32", v2i32>;
3044 def VDUPLNfd : VDUPLND<{?,1}, {0,0}, "vdup", "32", v2f32>;
3045 def VDUPLN8q : VDUPLNQ<{?,?}, {?,1}, "vdup", "8", v16i8, v8i8>;
3046 def VDUPLN16q : VDUPLNQ<{?,?}, {1,0}, "vdup", "16", v8i16, v4i16>;
3047 def VDUPLN32q : VDUPLNQ<{?,1}, {0,0}, "vdup", "32", v4i32, v2i32>;
3048 def VDUPLNfq : VDUPLNQ<{?,1}, {0,0}, "vdup", "32", v4f32, v2f32>;
3050 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
3051 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
3052 (DSubReg_i8_reg imm:$lane))),
3053 (SubReg_i8_lane imm:$lane)))>;
3054 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
3055 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
3056 (DSubReg_i16_reg imm:$lane))),
3057 (SubReg_i16_lane imm:$lane)))>;
3058 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
3059 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
3060 (DSubReg_i32_reg imm:$lane))),
3061 (SubReg_i32_lane imm:$lane)))>;
3062 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
3063 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
3064 (DSubReg_i32_reg imm:$lane))),
3065 (SubReg_i32_lane imm:$lane)))>;
3067 def VDUPfdf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 0, 0,
3068 (outs DPR:$dst), (ins SPR:$src),
3069 IIC_VMOVD, "vdup", "32", "$dst, ${src:lane}", "",
3070 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
3072 def VDUPfqf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 1, 0,
3073 (outs QPR:$dst), (ins SPR:$src),
3074 IIC_VMOVD, "vdup", "32", "$dst, ${src:lane}", "",
3075 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
3077 def : Pat<(v2i64 (NEONvduplane (v2i64 QPR:$src), imm:$lane)),
3078 (INSERT_SUBREG QPR:$src,
3079 (i64 (EXTRACT_SUBREG QPR:$src,
3080 (DSubReg_f64_reg imm:$lane))),
3081 (DSubReg_f64_other_reg imm:$lane))>;
3082 def : Pat<(v2f64 (NEONvduplane (v2f64 QPR:$src), imm:$lane)),
3083 (INSERT_SUBREG QPR:$src,
3084 (f64 (EXTRACT_SUBREG QPR:$src,
3085 (DSubReg_f64_reg imm:$lane))),
3086 (DSubReg_f64_other_reg imm:$lane))>;
3088 // VMOVN : Vector Narrowing Move
3089 defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVD,
3090 "vmovn", "i", int_arm_neon_vmovn>;
3091 // VQMOVN : Vector Saturating Narrowing Move
3092 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
3093 "vqmovn", "s", int_arm_neon_vqmovns>;
3094 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
3095 "vqmovn", "u", int_arm_neon_vqmovnu>;
3096 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
3097 "vqmovun", "s", int_arm_neon_vqmovnsu>;
3098 // VMOVL : Vector Lengthening Move
3099 defm VMOVLs : N2VLInt_QHS<0b01,0b10100,0,1, "vmovl", "s",
3100 int_arm_neon_vmovls>;
3101 defm VMOVLu : N2VLInt_QHS<0b11,0b10100,0,1, "vmovl", "u",
3102 int_arm_neon_vmovlu>;
3104 // Vector Conversions.
3106 // VCVT : Vector Convert Between Floating-Point and Integers
3107 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3108 v2i32, v2f32, fp_to_sint>;
3109 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3110 v2i32, v2f32, fp_to_uint>;
3111 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3112 v2f32, v2i32, sint_to_fp>;
3113 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3114 v2f32, v2i32, uint_to_fp>;
3116 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3117 v4i32, v4f32, fp_to_sint>;
3118 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3119 v4i32, v4f32, fp_to_uint>;
3120 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3121 v4f32, v4i32, sint_to_fp>;
3122 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3123 v4f32, v4i32, uint_to_fp>;
3125 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
3126 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
3127 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
3128 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
3129 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
3130 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
3131 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
3132 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
3133 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
3135 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
3136 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
3137 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
3138 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
3139 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
3140 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
3141 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
3142 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
3146 // VREV64 : Vector Reverse elements within 64-bit doublewords
3148 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3149 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
3150 (ins DPR:$src), IIC_VMOVD,
3151 OpcodeStr, Dt, "$dst, $src", "",
3152 [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
3153 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3154 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
3155 (ins QPR:$src), IIC_VMOVD,
3156 OpcodeStr, Dt, "$dst, $src", "",
3157 [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
3159 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
3160 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
3161 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
3162 def VREV64df : VREV64D<0b10, "vrev64", "32", v2f32>;
3164 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
3165 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
3166 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
3167 def VREV64qf : VREV64Q<0b10, "vrev64", "32", v4f32>;
3169 // VREV32 : Vector Reverse elements within 32-bit words
3171 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3172 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
3173 (ins DPR:$src), IIC_VMOVD,
3174 OpcodeStr, Dt, "$dst, $src", "",
3175 [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
3176 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3177 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
3178 (ins QPR:$src), IIC_VMOVD,
3179 OpcodeStr, Dt, "$dst, $src", "",
3180 [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
3182 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
3183 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
3185 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
3186 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
3188 // VREV16 : Vector Reverse elements within 16-bit halfwords
3190 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3191 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
3192 (ins DPR:$src), IIC_VMOVD,
3193 OpcodeStr, Dt, "$dst, $src", "",
3194 [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
3195 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3196 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
3197 (ins QPR:$src), IIC_VMOVD,
3198 OpcodeStr, Dt, "$dst, $src", "",
3199 [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
3201 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
3202 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
3204 // Other Vector Shuffles.
3206 // VEXT : Vector Extract
3208 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
3209 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$dst),
3210 (ins DPR:$lhs, DPR:$rhs, i32imm:$index), IIC_VEXTD,
3211 OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
3212 [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
3213 (Ty DPR:$rhs), imm:$index)))]>;
3215 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
3216 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$dst),
3217 (ins QPR:$lhs, QPR:$rhs, i32imm:$index), IIC_VEXTQ,
3218 OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
3219 [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
3220 (Ty QPR:$rhs), imm:$index)))]>;
3222 def VEXTd8 : VEXTd<"vext", "8", v8i8>;
3223 def VEXTd16 : VEXTd<"vext", "16", v4i16>;
3224 def VEXTd32 : VEXTd<"vext", "32", v2i32>;
3225 def VEXTdf : VEXTd<"vext", "32", v2f32>;
3227 def VEXTq8 : VEXTq<"vext", "8", v16i8>;
3228 def VEXTq16 : VEXTq<"vext", "16", v8i16>;
3229 def VEXTq32 : VEXTq<"vext", "32", v4i32>;
3230 def VEXTqf : VEXTq<"vext", "32", v4f32>;
3232 // VTRN : Vector Transpose
3234 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
3235 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
3236 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
3238 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
3239 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
3240 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
3242 // VUZP : Vector Unzip (Deinterleave)
3244 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
3245 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
3246 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
3248 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
3249 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
3250 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
3252 // VZIP : Vector Zip (Interleave)
3254 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
3255 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
3256 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
3258 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
3259 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
3260 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
3262 // Vector Table Lookup and Table Extension.
3264 // VTBL : Vector Table Lookup
3266 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
3267 (ins DPR:$tbl1, DPR:$src), IIC_VTB1,
3268 "vtbl", "8", "$dst, \\{$tbl1\\}, $src", "",
3269 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
3270 let hasExtraSrcRegAllocReq = 1 in {
3272 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
3273 (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTB2,
3274 "vtbl", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "",
3275 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl2
3276 DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
3278 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
3279 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTB3,
3280 "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src", "",
3281 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl3
3282 DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
3284 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
3285 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTB4,
3286 "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src", "",
3287 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl4 DPR:$tbl1, DPR:$tbl2,
3288 DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
3289 } // hasExtraSrcRegAllocReq = 1
3291 // VTBX : Vector Table Extension
3293 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
3294 (ins DPR:$orig, DPR:$tbl1, DPR:$src), IIC_VTBX1,
3295 "vtbx", "8", "$dst, \\{$tbl1\\}, $src", "$orig = $dst",
3296 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
3297 DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
3298 let hasExtraSrcRegAllocReq = 1 in {
3300 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
3301 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTBX2,
3302 "vtbx", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "$orig = $dst",
3303 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx2
3304 DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
3306 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
3307 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTBX3,
3308 "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src", "$orig = $dst",
3309 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx3 DPR:$orig, DPR:$tbl1,
3310 DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
3312 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
3313 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTBX4,
3314 "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src",
3316 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx4 DPR:$orig, DPR:$tbl1,
3317 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
3318 } // hasExtraSrcRegAllocReq = 1
3320 //===----------------------------------------------------------------------===//
3321 // NEON instructions for single-precision FP math
3322 //===----------------------------------------------------------------------===//
3324 class N2VSPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
3325 : NEONFPPat<(ResTy (OpNode SPR:$a)),
3326 (EXTRACT_SUBREG (OpTy (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)),
3327 SPR:$a, arm_ssubreg_0))),
3330 class N3VSPat<SDNode OpNode, NeonI Inst>
3331 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
3332 (EXTRACT_SUBREG (v2f32
3333 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3334 SPR:$a, arm_ssubreg_0),
3335 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3336 SPR:$b, arm_ssubreg_0))),
3339 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
3340 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
3341 (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3342 SPR:$acc, arm_ssubreg_0),
3343 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3344 SPR:$a, arm_ssubreg_0),
3345 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3346 SPR:$b, arm_ssubreg_0)),
3349 // These need separate instructions because they must use DPR_VFP2 register
3350 // class which have SPR sub-registers.
3352 // Vector Add Operations used for single-precision FP
3353 let neverHasSideEffects = 1 in
3354 def VADDfd_sfp : N3VS<0,0,0b00,0b1101,0, "vadd", "f32", v2f32, v2f32, fadd, 1>;
3355 def : N3VSPat<fadd, VADDfd_sfp>;
3357 // Vector Sub Operations used for single-precision FP
3358 let neverHasSideEffects = 1 in
3359 def VSUBfd_sfp : N3VS<0,0,0b10,0b1101,0, "vsub", "f32", v2f32, v2f32, fsub, 0>;
3360 def : N3VSPat<fsub, VSUBfd_sfp>;
3362 // Vector Multiply Operations used for single-precision FP
3363 let neverHasSideEffects = 1 in
3364 def VMULfd_sfp : N3VS<1,0,0b00,0b1101,1, "vmul", "f32", v2f32, v2f32, fmul, 1>;
3365 def : N3VSPat<fmul, VMULfd_sfp>;
3367 // Vector Multiply-Accumulate/Subtract used for single-precision FP
3368 // vml[as].f32 can cause 4-8 cycle stalls in following ASIMD instructions, so
3369 // we want to avoid them for now. e.g., alternating vmla/vadd instructions.
3371 //let neverHasSideEffects = 1 in
3372 //def VMLAfd_sfp : N3VSMulOp<0,0,0b00,0b1101,1, IIC_VMACD, "vmla", "f32",
3373 // v2f32, fmul, fadd>;
3374 //def : N3VSMulOpPat<fmul, fadd, VMLAfd_sfp>;
3376 //let neverHasSideEffects = 1 in
3377 //def VMLSfd_sfp : N3VSMulOp<0,0,0b10,0b1101,1, IIC_VMACD, "vmls", "f32",
3378 // v2f32, fmul, fsub>;
3379 //def : N3VSMulOpPat<fmul, fsub, VMLSfd_sfp>;
3381 // Vector Absolute used for single-precision FP
3382 let neverHasSideEffects = 1 in
3383 def VABSfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01110, 0, 0,
3384 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
3385 "vabs", "f32", "$dst, $src", "", []>;
3386 def : N2VSPat<fabs, f32, v2f32, VABSfd_sfp>;
3388 // Vector Negate used for single-precision FP
3389 let neverHasSideEffects = 1 in
3390 def VNEGfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
3391 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
3392 "vneg", "f32", "$dst, $src", "", []>;
3393 def : N2VSPat<fneg, f32, v2f32, VNEGfd_sfp>;
3395 // Vector Maximum used for single-precision FP
3396 let neverHasSideEffects = 1 in
3397 def VMAXfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
3398 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), IIC_VBIND,
3399 "vmax", "f32", "$dst, $src1, $src2", "", []>;
3400 def : N3VSPat<NEONfmax, VMAXfd_sfp>;
3402 // Vector Minimum used for single-precision FP
3403 let neverHasSideEffects = 1 in
3404 def VMINfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
3405 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), IIC_VBIND,
3406 "vmin", "f32", "$dst, $src1, $src2", "", []>;
3407 def : N3VSPat<NEONfmin, VMINfd_sfp>;
3409 // Vector Convert between single-precision FP and integer
3410 let neverHasSideEffects = 1 in
3411 def VCVTf2sd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3412 v2i32, v2f32, fp_to_sint>;
3413 def : N2VSPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
3415 let neverHasSideEffects = 1 in
3416 def VCVTf2ud_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3417 v2i32, v2f32, fp_to_uint>;
3418 def : N2VSPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
3420 let neverHasSideEffects = 1 in
3421 def VCVTs2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3422 v2f32, v2i32, sint_to_fp>;
3423 def : N2VSPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
3425 let neverHasSideEffects = 1 in
3426 def VCVTu2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3427 v2f32, v2i32, uint_to_fp>;
3428 def : N2VSPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
3430 //===----------------------------------------------------------------------===//
3431 // Non-Instruction Patterns
3432 //===----------------------------------------------------------------------===//
3435 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
3436 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
3437 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
3438 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
3439 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
3440 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
3441 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
3442 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
3443 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
3444 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
3445 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
3446 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
3447 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
3448 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
3449 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
3450 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
3451 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
3452 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
3453 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
3454 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
3455 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
3456 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
3457 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
3458 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
3459 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
3460 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
3461 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
3462 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
3463 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
3464 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
3466 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
3467 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
3468 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
3469 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
3470 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
3471 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
3472 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
3473 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
3474 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
3475 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
3476 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
3477 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
3478 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
3479 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
3480 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
3481 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
3482 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
3483 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
3484 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
3485 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
3486 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
3487 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
3488 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
3489 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
3490 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
3491 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
3492 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
3493 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
3494 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
3495 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;