1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
19 def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
21 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
22 def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
23 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
24 def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
25 def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
26 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
27 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
28 def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
29 def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
30 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
31 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
33 // Types for vector shift by immediates. The "SHX" version is for long and
34 // narrow operations where the source and destination vectors have different
35 // types. The "SHINS" version is for shift and insert operations.
36 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
38 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
40 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
43 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
44 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
45 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
46 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
47 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
48 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
49 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
51 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
52 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
53 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
55 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
56 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
57 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
58 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
59 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
60 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
62 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
63 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
64 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
66 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
67 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
69 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
71 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
72 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
74 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
75 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
76 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
78 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
80 def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
81 def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
83 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
85 // VDUPLANE can produce a quad-register result from a double-register source,
86 // so the result is not constrained to match the source.
87 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
88 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
91 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
92 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
93 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
95 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
96 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
97 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
98 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
100 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
102 SDTCisSameAs<0, 3>]>;
103 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
104 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
105 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
107 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
108 SDTCisSameAs<1, 2>]>;
109 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
110 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
112 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
113 SDTCisSameAs<0, 2>]>;
114 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
115 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
117 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
118 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
119 unsigned EltBits = 0;
120 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
121 return (EltBits == 32 && EltVal == 0);
124 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
125 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
126 unsigned EltBits = 0;
127 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
128 return (EltBits == 8 && EltVal == 0xff);
131 //===----------------------------------------------------------------------===//
132 // NEON operand definitions
133 //===----------------------------------------------------------------------===//
135 def nModImm : Operand<i32> {
136 let PrintMethod = "printNEONModImmOperand";
139 //===----------------------------------------------------------------------===//
140 // NEON load / store instructions
141 //===----------------------------------------------------------------------===//
143 // Use VLDM to load a Q register as a D register pair.
144 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
146 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
148 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
150 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
152 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
154 // Use VSTM to store a Q register as a D register pair.
155 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
157 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
159 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
161 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
163 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
165 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
167 // Classes for VLD* pseudo-instructions with multi-register operands.
168 // These are expanded to real instructions after register allocation.
169 class VLDQPseudo<InstrItinClass itin>
170 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
171 class VLDQWBPseudo<InstrItinClass itin>
172 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
173 (ins addrmode6:$addr, am6offset:$offset), itin,
175 class VLDQQPseudo<InstrItinClass itin>
176 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
177 class VLDQQWBPseudo<InstrItinClass itin>
178 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
179 (ins addrmode6:$addr, am6offset:$offset), itin,
181 class VLDQQQQWBPseudo<InstrItinClass itin>
182 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
183 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
184 "$addr.addr = $wb, $src = $dst">;
186 // VLD1 : Vector Load (multiple single elements)
187 class VLD1D<bits<4> op7_4, string Dt>
188 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd),
189 (ins addrmode6:$Rn), IIC_VLD1,
190 "vld1", Dt, "\\{$Vd\\}, $Rn", "", []> {
194 class VLD1Q<bits<4> op7_4, string Dt>
195 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2),
196 (ins addrmode6:$Rn), IIC_VLD1x2,
197 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
199 let Inst{5-4} = Rn{5-4};
202 def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
203 def VLD1d16 : VLD1D<{0,1,0,?}, "16">;
204 def VLD1d32 : VLD1D<{1,0,0,?}, "32">;
205 def VLD1d64 : VLD1D<{1,1,0,?}, "64">;
207 def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;
208 def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
209 def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
210 def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
212 def VLD1q8Pseudo : VLDQPseudo<IIC_VLD1x2>;
213 def VLD1q16Pseudo : VLDQPseudo<IIC_VLD1x2>;
214 def VLD1q32Pseudo : VLDQPseudo<IIC_VLD1x2>;
215 def VLD1q64Pseudo : VLDQPseudo<IIC_VLD1x2>;
217 // ...with address register writeback:
218 class VLD1DWB<bits<4> op7_4, string Dt>
219 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd, GPR:$wb),
220 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1u,
221 "vld1", Dt, "\\{$Vd\\}, $Rn$Rm",
222 "$Rn.addr = $wb", []> {
225 class VLD1QWB<bits<4> op7_4, string Dt>
226 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
227 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x2u,
228 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
229 "$Rn.addr = $wb", []> {
230 let Inst{5-4} = Rn{5-4};
233 def VLD1d8_UPD : VLD1DWB<{0,0,0,?}, "8">;
234 def VLD1d16_UPD : VLD1DWB<{0,1,0,?}, "16">;
235 def VLD1d32_UPD : VLD1DWB<{1,0,0,?}, "32">;
236 def VLD1d64_UPD : VLD1DWB<{1,1,0,?}, "64">;
238 def VLD1q8_UPD : VLD1QWB<{0,0,?,?}, "8">;
239 def VLD1q16_UPD : VLD1QWB<{0,1,?,?}, "16">;
240 def VLD1q32_UPD : VLD1QWB<{1,0,?,?}, "32">;
241 def VLD1q64_UPD : VLD1QWB<{1,1,?,?}, "64">;
243 def VLD1q8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
244 def VLD1q16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
245 def VLD1q32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
246 def VLD1q64Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
248 // ...with 3 registers (some of these are only for the disassembler):
249 class VLD1D3<bits<4> op7_4, string Dt>
250 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
251 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
252 "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
256 class VLD1D3WB<bits<4> op7_4, string Dt>
257 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
258 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x3u, "vld1", Dt,
259 "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
263 def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
264 def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;
265 def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;
266 def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;
268 def VLD1d8T_UPD : VLD1D3WB<{0,0,0,?}, "8">;
269 def VLD1d16T_UPD : VLD1D3WB<{0,1,0,?}, "16">;
270 def VLD1d32T_UPD : VLD1D3WB<{1,0,0,?}, "32">;
271 def VLD1d64T_UPD : VLD1D3WB<{1,1,0,?}, "64">;
273 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
274 def VLD1d64TPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x3u>;
276 // ...with 4 registers (some of these are only for the disassembler):
277 class VLD1D4<bits<4> op7_4, string Dt>
278 : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
279 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
280 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
282 let Inst{5-4} = Rn{5-4};
284 class VLD1D4WB<bits<4> op7_4, string Dt>
285 : NLdSt<0,0b10,0b0010,op7_4,
286 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
287 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4, "vld1", Dt,
288 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", "$Rn.addr = $wb",
290 let Inst{5-4} = Rn{5-4};
293 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
294 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;
295 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;
296 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;
298 def VLD1d8Q_UPD : VLD1D4WB<{0,0,?,?}, "8">;
299 def VLD1d16Q_UPD : VLD1D4WB<{0,1,?,?}, "16">;
300 def VLD1d32Q_UPD : VLD1D4WB<{1,0,?,?}, "32">;
301 def VLD1d64Q_UPD : VLD1D4WB<{1,1,?,?}, "64">;
303 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
304 def VLD1d64QPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x4u>;
306 // VLD2 : Vector Load (multiple 2-element structures)
307 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
308 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
309 (ins addrmode6:$Rn), IIC_VLD2,
310 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
312 let Inst{5-4} = Rn{5-4};
314 class VLD2Q<bits<4> op7_4, string Dt>
315 : NLdSt<0, 0b10, 0b0011, op7_4,
316 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
317 (ins addrmode6:$Rn), IIC_VLD2x2,
318 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
320 let Inst{5-4} = Rn{5-4};
323 def VLD2d8 : VLD2D<0b1000, {0,0,?,?}, "8">;
324 def VLD2d16 : VLD2D<0b1000, {0,1,?,?}, "16">;
325 def VLD2d32 : VLD2D<0b1000, {1,0,?,?}, "32">;
327 def VLD2q8 : VLD2Q<{0,0,?,?}, "8">;
328 def VLD2q16 : VLD2Q<{0,1,?,?}, "16">;
329 def VLD2q32 : VLD2Q<{1,0,?,?}, "32">;
331 def VLD2d8Pseudo : VLDQPseudo<IIC_VLD2>;
332 def VLD2d16Pseudo : VLDQPseudo<IIC_VLD2>;
333 def VLD2d32Pseudo : VLDQPseudo<IIC_VLD2>;
335 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
336 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
337 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
339 // ...with address register writeback:
340 class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
341 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
342 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2u,
343 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
344 "$Rn.addr = $wb", []> {
345 let Inst{5-4} = Rn{5-4};
347 class VLD2QWB<bits<4> op7_4, string Dt>
348 : NLdSt<0, 0b10, 0b0011, op7_4,
349 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
350 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2x2u,
351 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
352 "$Rn.addr = $wb", []> {
353 let Inst{5-4} = Rn{5-4};
356 def VLD2d8_UPD : VLD2DWB<0b1000, {0,0,?,?}, "8">;
357 def VLD2d16_UPD : VLD2DWB<0b1000, {0,1,?,?}, "16">;
358 def VLD2d32_UPD : VLD2DWB<0b1000, {1,0,?,?}, "32">;
360 def VLD2q8_UPD : VLD2QWB<{0,0,?,?}, "8">;
361 def VLD2q16_UPD : VLD2QWB<{0,1,?,?}, "16">;
362 def VLD2q32_UPD : VLD2QWB<{1,0,?,?}, "32">;
364 def VLD2d8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
365 def VLD2d16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
366 def VLD2d32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
368 def VLD2q8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
369 def VLD2q16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
370 def VLD2q32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
372 // ...with double-spaced registers (for disassembly only):
373 def VLD2b8 : VLD2D<0b1001, {0,0,?,?}, "8">;
374 def VLD2b16 : VLD2D<0b1001, {0,1,?,?}, "16">;
375 def VLD2b32 : VLD2D<0b1001, {1,0,?,?}, "32">;
376 def VLD2b8_UPD : VLD2DWB<0b1001, {0,0,?,?}, "8">;
377 def VLD2b16_UPD : VLD2DWB<0b1001, {0,1,?,?}, "16">;
378 def VLD2b32_UPD : VLD2DWB<0b1001, {1,0,?,?}, "32">;
380 // VLD3 : Vector Load (multiple 3-element structures)
381 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
382 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
383 (ins addrmode6:$Rn), IIC_VLD3,
384 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
389 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
390 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
391 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
393 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
394 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
395 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
397 // ...with address register writeback:
398 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
399 : NLdSt<0, 0b10, op11_8, op7_4,
400 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
401 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
402 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
403 "$Rn.addr = $wb", []> {
407 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
408 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
409 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
411 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
412 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
413 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
415 // ...with double-spaced registers (non-updating versions for disassembly only):
416 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
417 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
418 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
419 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
420 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
421 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
423 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
424 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
425 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
427 // ...alternate versions to be allocated odd register numbers:
428 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
429 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
430 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
432 // VLD4 : Vector Load (multiple 4-element structures)
433 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
434 : NLdSt<0, 0b10, op11_8, op7_4,
435 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
436 (ins addrmode6:$Rn), IIC_VLD4,
437 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
439 let Inst{5-4} = Rn{5-4};
442 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
443 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
444 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
446 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
447 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
448 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
450 // ...with address register writeback:
451 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
452 : NLdSt<0, 0b10, op11_8, op7_4,
453 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
454 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4,
455 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
456 "$Rn.addr = $wb", []> {
457 let Inst{5-4} = Rn{5-4};
460 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
461 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
462 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
464 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
465 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
466 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
468 // ...with double-spaced registers (non-updating versions for disassembly only):
469 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
470 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
471 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
472 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
473 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
474 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
476 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
477 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
478 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
480 // ...alternate versions to be allocated odd register numbers:
481 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
482 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
483 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
485 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
487 // Classes for VLD*LN pseudo-instructions with multi-register operands.
488 // These are expanded to real instructions after register allocation.
489 class VLDQLNPseudo<InstrItinClass itin>
490 : PseudoNLdSt<(outs QPR:$dst),
491 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
492 itin, "$src = $dst">;
493 class VLDQLNWBPseudo<InstrItinClass itin>
494 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
495 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
496 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
497 class VLDQQLNPseudo<InstrItinClass itin>
498 : PseudoNLdSt<(outs QQPR:$dst),
499 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
500 itin, "$src = $dst">;
501 class VLDQQLNWBPseudo<InstrItinClass itin>
502 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
503 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
504 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
505 class VLDQQQQLNPseudo<InstrItinClass itin>
506 : PseudoNLdSt<(outs QQQQPR:$dst),
507 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
508 itin, "$src = $dst">;
509 class VLDQQQQLNWBPseudo<InstrItinClass itin>
510 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
511 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
512 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
514 // VLD1LN : Vector Load (single element to one lane)
515 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
517 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
518 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
519 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
521 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
522 (i32 (LoadOp addrmode6:$Rn)),
526 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
527 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
528 (i32 (LoadOp addrmode6:$addr)),
532 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
533 let Inst{7-5} = lane{2-0};
535 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
536 let Inst{7-6} = lane{1-0};
539 def VLD1LNd32 : VLD1LN<0b1000, {?,0,?,?}, "32", v2i32, load> {
540 let Inst{7} = lane{0};
545 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
546 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
547 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
549 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
551 // ...with address register writeback:
552 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
553 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
554 (ins addrmode6:$Rn, am6offset:$Rm,
555 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
556 "\\{$Vd[$lane]\\}, $Rn$Rm",
557 "$src = $Vd, $Rn.addr = $wb", []>;
559 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
560 let Inst{7-5} = lane{2-0};
562 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
563 let Inst{7-6} = lane{1-0};
566 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
567 let Inst{7} = lane{0};
572 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
573 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
574 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
576 // VLD2LN : Vector Load (single 2-element structure to one lane)
577 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
578 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
579 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
580 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
581 "$src1 = $Vd, $src2 = $dst2", []> {
586 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
587 let Inst{7-5} = lane{2-0};
589 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
590 let Inst{7-6} = lane{1-0};
592 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
593 let Inst{7} = lane{0};
596 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
597 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
598 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
600 // ...with double-spaced registers:
601 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
602 let Inst{7-6} = lane{1-0};
604 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
605 let Inst{7} = lane{0};
608 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
609 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
611 // ...with address register writeback:
612 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
613 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
614 (ins addrmode6:$Rn, am6offset:$Rm,
615 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
616 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
617 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
621 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
622 let Inst{7-5} = lane{2-0};
624 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
625 let Inst{7-6} = lane{1-0};
627 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
628 let Inst{7} = lane{0};
631 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
632 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
633 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
635 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
636 let Inst{7-6} = lane{1-0};
638 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
639 let Inst{7} = lane{0};
642 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
643 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
645 // VLD3LN : Vector Load (single 3-element structure to one lane)
646 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
647 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
648 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
649 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
650 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
651 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
655 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
656 let Inst{7-5} = lane{2-0};
658 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
659 let Inst{7-6} = lane{1-0};
661 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
662 let Inst{7} = lane{0};
665 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
666 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
667 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
669 // ...with double-spaced registers:
670 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
671 let Inst{7-6} = lane{1-0};
673 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
674 let Inst{7} = lane{0};
677 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
678 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
680 // ...with address register writeback:
681 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
682 : NLdStLn<1, 0b10, op11_8, op7_4,
683 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
684 (ins addrmode6:$Rn, am6offset:$Rm,
685 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
686 IIC_VLD3lnu, "vld3", Dt,
687 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
688 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
691 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
692 let Inst{7-5} = lane{2-0};
694 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
695 let Inst{7-6} = lane{1-0};
697 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
698 let Inst{7} = lane{0};
701 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
702 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
703 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
705 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
706 let Inst{7-6} = lane{1-0};
708 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
709 let Inst{7} = lane{0};
712 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
713 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
715 // VLD4LN : Vector Load (single 4-element structure to one lane)
716 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
717 : NLdStLn<1, 0b10, op11_8, op7_4,
718 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
719 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
720 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
721 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
722 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
727 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
728 let Inst{7-5} = lane{2-0};
730 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
731 let Inst{7-6} = lane{1-0};
733 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
734 let Inst{7} = lane{0};
738 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
739 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
740 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
742 // ...with double-spaced registers:
743 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
744 let Inst{7-6} = lane{1-0};
746 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
747 let Inst{7} = lane{0};
751 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
752 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
754 // ...with address register writeback:
755 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
756 : NLdStLn<1, 0b10, op11_8, op7_4,
757 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
758 (ins addrmode6:$Rn, am6offset:$Rm,
759 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
760 IIC_VLD4ln, "vld4", Dt,
761 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
762 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
767 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
768 let Inst{7-5} = lane{2-0};
770 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
771 let Inst{7-6} = lane{1-0};
773 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
774 let Inst{7} = lane{0};
778 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
779 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
780 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
782 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
783 let Inst{7-6} = lane{1-0};
785 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
786 let Inst{7} = lane{0};
790 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
791 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
793 // VLD1DUP : Vector Load (single element to all lanes)
794 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
795 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
796 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
797 // FIXME: Not yet implemented.
798 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
800 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
802 // Classes for VST* pseudo-instructions with multi-register operands.
803 // These are expanded to real instructions after register allocation.
804 class VSTQPseudo<InstrItinClass itin>
805 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
806 class VSTQWBPseudo<InstrItinClass itin>
807 : PseudoNLdSt<(outs GPR:$wb),
808 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
810 class VSTQQPseudo<InstrItinClass itin>
811 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
812 class VSTQQWBPseudo<InstrItinClass itin>
813 : PseudoNLdSt<(outs GPR:$wb),
814 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
816 class VSTQQQQWBPseudo<InstrItinClass itin>
817 : PseudoNLdSt<(outs GPR:$wb),
818 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
821 // VST1 : Vector Store (multiple single elements)
822 class VST1D<bits<4> op7_4, string Dt>
823 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, DPR:$Vd),
824 IIC_VST1, "vst1", Dt, "\\{$Vd\\}, $Rn", "", []> {
828 class VST1Q<bits<4> op7_4, string Dt>
829 : NLdSt<0,0b00,0b1010,op7_4, (outs),
830 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2), IIC_VST1x2,
831 "vst1", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
833 let Inst{5-4} = Rn{5-4};
836 def VST1d8 : VST1D<{0,0,0,?}, "8">;
837 def VST1d16 : VST1D<{0,1,0,?}, "16">;
838 def VST1d32 : VST1D<{1,0,0,?}, "32">;
839 def VST1d64 : VST1D<{1,1,0,?}, "64">;
841 def VST1q8 : VST1Q<{0,0,?,?}, "8">;
842 def VST1q16 : VST1Q<{0,1,?,?}, "16">;
843 def VST1q32 : VST1Q<{1,0,?,?}, "32">;
844 def VST1q64 : VST1Q<{1,1,?,?}, "64">;
846 def VST1q8Pseudo : VSTQPseudo<IIC_VST1x2>;
847 def VST1q16Pseudo : VSTQPseudo<IIC_VST1x2>;
848 def VST1q32Pseudo : VSTQPseudo<IIC_VST1x2>;
849 def VST1q64Pseudo : VSTQPseudo<IIC_VST1x2>;
851 // ...with address register writeback:
852 class VST1DWB<bits<4> op7_4, string Dt>
853 : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
854 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd), IIC_VST1u,
855 "vst1", Dt, "\\{$Vd\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
858 class VST1QWB<bits<4> op7_4, string Dt>
859 : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),
860 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
861 IIC_VST1x2u, "vst1", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
862 "$Rn.addr = $wb", []> {
863 let Inst{5-4} = Rn{5-4};
866 def VST1d8_UPD : VST1DWB<{0,0,0,?}, "8">;
867 def VST1d16_UPD : VST1DWB<{0,1,0,?}, "16">;
868 def VST1d32_UPD : VST1DWB<{1,0,0,?}, "32">;
869 def VST1d64_UPD : VST1DWB<{1,1,0,?}, "64">;
871 def VST1q8_UPD : VST1QWB<{0,0,?,?}, "8">;
872 def VST1q16_UPD : VST1QWB<{0,1,?,?}, "16">;
873 def VST1q32_UPD : VST1QWB<{1,0,?,?}, "32">;
874 def VST1q64_UPD : VST1QWB<{1,1,?,?}, "64">;
876 def VST1q8Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
877 def VST1q16Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
878 def VST1q32Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
879 def VST1q64Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
881 // ...with 3 registers (some of these are only for the disassembler):
882 class VST1D3<bits<4> op7_4, string Dt>
883 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
884 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3),
885 IIC_VST1x3, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
889 class VST1D3WB<bits<4> op7_4, string Dt>
890 : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
891 (ins addrmode6:$Rn, am6offset:$Rm,
892 DPR:$Vd, DPR:$src2, DPR:$src3),
893 IIC_VST1x3u, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
894 "$Rn.addr = $wb", []> {
898 def VST1d8T : VST1D3<{0,0,0,?}, "8">;
899 def VST1d16T : VST1D3<{0,1,0,?}, "16">;
900 def VST1d32T : VST1D3<{1,0,0,?}, "32">;
901 def VST1d64T : VST1D3<{1,1,0,?}, "64">;
903 def VST1d8T_UPD : VST1D3WB<{0,0,0,?}, "8">;
904 def VST1d16T_UPD : VST1D3WB<{0,1,0,?}, "16">;
905 def VST1d32T_UPD : VST1D3WB<{1,0,0,?}, "32">;
906 def VST1d64T_UPD : VST1D3WB<{1,1,0,?}, "64">;
908 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
909 def VST1d64TPseudo_UPD : VSTQQWBPseudo<IIC_VST1x3u>;
911 // ...with 4 registers (some of these are only for the disassembler):
912 class VST1D4<bits<4> op7_4, string Dt>
913 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
914 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
915 IIC_VST1x4, "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", "",
918 let Inst{5-4} = Rn{5-4};
920 class VST1D4WB<bits<4> op7_4, string Dt>
921 : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
922 (ins addrmode6:$Rn, am6offset:$Rm,
923 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST1x4u,
924 "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
925 "$Rn.addr = $wb", []> {
926 let Inst{5-4} = Rn{5-4};
929 def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
930 def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
931 def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
932 def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
934 def VST1d8Q_UPD : VST1D4WB<{0,0,?,?}, "8">;
935 def VST1d16Q_UPD : VST1D4WB<{0,1,?,?}, "16">;
936 def VST1d32Q_UPD : VST1D4WB<{1,0,?,?}, "32">;
937 def VST1d64Q_UPD : VST1D4WB<{1,1,?,?}, "64">;
939 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
940 def VST1d64QPseudo_UPD : VSTQQWBPseudo<IIC_VST1x4u>;
942 // VST2 : Vector Store (multiple 2-element structures)
943 class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
944 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
945 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2),
946 IIC_VST2, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
948 let Inst{5-4} = Rn{5-4};
950 class VST2Q<bits<4> op7_4, string Dt>
951 : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
952 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
953 IIC_VST2x2, "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
956 let Inst{5-4} = Rn{5-4};
959 def VST2d8 : VST2D<0b1000, {0,0,?,?}, "8">;
960 def VST2d16 : VST2D<0b1000, {0,1,?,?}, "16">;
961 def VST2d32 : VST2D<0b1000, {1,0,?,?}, "32">;
963 def VST2q8 : VST2Q<{0,0,?,?}, "8">;
964 def VST2q16 : VST2Q<{0,1,?,?}, "16">;
965 def VST2q32 : VST2Q<{1,0,?,?}, "32">;
967 def VST2d8Pseudo : VSTQPseudo<IIC_VST2>;
968 def VST2d16Pseudo : VSTQPseudo<IIC_VST2>;
969 def VST2d32Pseudo : VSTQPseudo<IIC_VST2>;
971 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
972 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
973 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
975 // ...with address register writeback:
976 class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
977 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
978 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
979 IIC_VST2u, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
980 "$Rn.addr = $wb", []> {
981 let Inst{5-4} = Rn{5-4};
983 class VST2QWB<bits<4> op7_4, string Dt>
984 : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
985 (ins addrmode6:$Rn, am6offset:$Rm,
986 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST2x2u,
987 "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
988 "$Rn.addr = $wb", []> {
989 let Inst{5-4} = Rn{5-4};
992 def VST2d8_UPD : VST2DWB<0b1000, {0,0,?,?}, "8">;
993 def VST2d16_UPD : VST2DWB<0b1000, {0,1,?,?}, "16">;
994 def VST2d32_UPD : VST2DWB<0b1000, {1,0,?,?}, "32">;
996 def VST2q8_UPD : VST2QWB<{0,0,?,?}, "8">;
997 def VST2q16_UPD : VST2QWB<{0,1,?,?}, "16">;
998 def VST2q32_UPD : VST2QWB<{1,0,?,?}, "32">;
1000 def VST2d8Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1001 def VST2d16Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1002 def VST2d32Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1004 def VST2q8Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1005 def VST2q16Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1006 def VST2q32Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1008 // ...with double-spaced registers (for disassembly only):
1009 def VST2b8 : VST2D<0b1001, {0,0,?,?}, "8">;
1010 def VST2b16 : VST2D<0b1001, {0,1,?,?}, "16">;
1011 def VST2b32 : VST2D<0b1001, {1,0,?,?}, "32">;
1012 def VST2b8_UPD : VST2DWB<0b1001, {0,0,?,?}, "8">;
1013 def VST2b16_UPD : VST2DWB<0b1001, {0,1,?,?}, "16">;
1014 def VST2b32_UPD : VST2DWB<0b1001, {1,0,?,?}, "32">;
1016 // VST3 : Vector Store (multiple 3-element structures)
1017 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1018 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1019 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1020 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1022 let Inst{4} = Rn{4};
1025 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1026 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1027 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
1029 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1030 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1031 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
1033 // ...with address register writeback:
1034 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1035 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1036 (ins addrmode6:$Rn, am6offset:$Rm,
1037 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1038 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1039 "$Rn.addr = $wb", []> {
1040 let Inst{4} = Rn{4};
1043 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1044 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1045 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
1047 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1048 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1049 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1051 // ...with double-spaced registers (non-updating versions for disassembly only):
1052 def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1053 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1054 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1055 def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1056 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1057 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
1059 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1060 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1061 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1063 // ...alternate versions to be allocated odd register numbers:
1064 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1065 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1066 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1068 // VST4 : Vector Store (multiple 4-element structures)
1069 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1070 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1071 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1072 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1075 let Inst{5-4} = Rn{5-4};
1078 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1079 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1080 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
1082 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1083 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1084 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
1086 // ...with address register writeback:
1087 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1088 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1089 (ins addrmode6:$Rn, am6offset:$Rm,
1090 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1091 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1092 "$Rn.addr = $wb", []> {
1093 let Inst{5-4} = Rn{5-4};
1096 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
1097 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
1098 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
1100 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1101 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1102 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1104 // ...with double-spaced registers (non-updating versions for disassembly only):
1105 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
1106 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
1107 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
1108 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
1109 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
1110 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
1112 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1113 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1114 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1116 // ...alternate versions to be allocated odd register numbers:
1117 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1118 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1119 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1121 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1123 // Classes for VST*LN pseudo-instructions with multi-register operands.
1124 // These are expanded to real instructions after register allocation.
1125 class VSTQLNPseudo<InstrItinClass itin>
1126 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1128 class VSTQLNWBPseudo<InstrItinClass itin>
1129 : PseudoNLdSt<(outs GPR:$wb),
1130 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1131 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1132 class VSTQQLNPseudo<InstrItinClass itin>
1133 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1135 class VSTQQLNWBPseudo<InstrItinClass itin>
1136 : PseudoNLdSt<(outs GPR:$wb),
1137 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1138 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1139 class VSTQQQQLNPseudo<InstrItinClass itin>
1140 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1142 class VSTQQQQLNWBPseudo<InstrItinClass itin>
1143 : PseudoNLdSt<(outs GPR:$wb),
1144 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1145 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1147 // VST1LN : Vector Store (single element from one lane)
1148 class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1149 PatFrag StoreOp, SDNode ExtractOp>
1150 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1151 (ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane),
1152 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1153 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6:$Rn)]> {
1156 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1157 : VSTQLNPseudo<IIC_VST1ln> {
1158 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1162 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
1164 let Inst{7-5} = lane{2-0};
1166 def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
1168 let Inst{7-6} = lane{1-0};
1169 let Inst{4} = Rn{5};
1171 def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt> {
1172 let Inst{7} = lane{0};
1173 let Inst{5-4} = Rn{5-4};
1176 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
1177 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
1178 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
1180 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1182 // ...with address register writeback:
1183 class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1184 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1185 (ins addrmode6:$Rn, am6offset:$Rm,
1186 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
1187 "\\{$Vd[$lane]\\}, $Rn$Rm",
1188 "$Rn.addr = $wb", []>;
1190 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8"> {
1191 let Inst{7-5} = lane{2-0};
1193 def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16"> {
1194 let Inst{7-6} = lane{1-0};
1195 let Inst{4} = Rn{5};
1197 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32"> {
1198 let Inst{7} = lane{0};
1199 let Inst{5-4} = Rn{5-4};
1202 def VST1LNq8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST1lnu>;
1203 def VST1LNq16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST1lnu>;
1204 def VST1LNq32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST1lnu>;
1206 // VST2LN : Vector Store (single 2-element structure from one lane)
1207 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1208 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1209 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
1210 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
1213 let Inst{4} = Rn{4};
1216 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
1217 let Inst{7-5} = lane{2-0};
1219 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
1220 let Inst{7-6} = lane{1-0};
1222 def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
1223 let Inst{7} = lane{0};
1226 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1227 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1228 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1230 // ...with double-spaced registers:
1231 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
1232 let Inst{7-6} = lane{1-0};
1233 let Inst{4} = Rn{4};
1235 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
1236 let Inst{7} = lane{0};
1237 let Inst{4} = Rn{4};
1240 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1241 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1243 // ...with address register writeback:
1244 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1245 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1246 (ins addrmode6:$addr, am6offset:$offset,
1247 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
1248 "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset",
1249 "$addr.addr = $wb", []> {
1250 let Inst{4} = Rn{4};
1253 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
1254 let Inst{7-5} = lane{2-0};
1256 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
1257 let Inst{7-6} = lane{1-0};
1259 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
1260 let Inst{7} = lane{0};
1263 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1264 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1265 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1267 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
1268 let Inst{7-6} = lane{1-0};
1270 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
1271 let Inst{7} = lane{0};
1274 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1275 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1277 // VST3LN : Vector Store (single 3-element structure from one lane)
1278 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1279 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1280 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
1281 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
1282 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
1286 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
1287 let Inst{7-5} = lane{2-0};
1289 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
1290 let Inst{7-6} = lane{1-0};
1292 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
1293 let Inst{7} = lane{0};
1296 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1297 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1298 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1300 // ...with double-spaced registers:
1301 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
1302 let Inst{7-6} = lane{1-0};
1304 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
1305 let Inst{7} = lane{0};
1308 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1309 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1311 // ...with address register writeback:
1312 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1313 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1314 (ins addrmode6:$Rn, am6offset:$Rm,
1315 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1316 IIC_VST3lnu, "vst3", Dt,
1317 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
1318 "$Rn.addr = $wb", []>;
1320 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
1321 let Inst{7-5} = lane{2-0};
1323 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
1324 let Inst{7-6} = lane{1-0};
1326 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
1327 let Inst{7} = lane{0};
1330 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1331 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1332 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1334 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
1335 let Inst{7-6} = lane{1-0};
1337 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
1338 let Inst{7} = lane{0};
1341 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1342 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1344 // VST4LN : Vector Store (single 4-element structure from one lane)
1345 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1346 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1347 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
1348 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
1349 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
1352 let Inst{4} = Rn{4};
1355 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
1356 let Inst{7-5} = lane{2-0};
1358 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
1359 let Inst{7-6} = lane{1-0};
1361 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
1362 let Inst{7} = lane{0};
1363 let Inst{5} = Rn{5};
1366 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1367 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1368 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1370 // ...with double-spaced registers:
1371 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
1372 let Inst{7-6} = lane{1-0};
1374 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
1375 let Inst{7} = lane{0};
1376 let Inst{5} = Rn{5};
1379 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1380 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1382 // ...with address register writeback:
1383 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1384 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1385 (ins addrmode6:$Rn, am6offset:$Rm,
1386 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1387 IIC_VST4lnu, "vst4", Dt,
1388 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
1389 "$Rn.addr = $wb", []> {
1390 let Inst{4} = Rn{4};
1393 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
1394 let Inst{7-5} = lane{2-0};
1396 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
1397 let Inst{7-6} = lane{1-0};
1399 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
1400 let Inst{7} = lane{0};
1401 let Inst{5} = Rn{5};
1404 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1405 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1406 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1408 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
1409 let Inst{7-6} = lane{1-0};
1411 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
1412 let Inst{7} = lane{0};
1413 let Inst{5} = Rn{5};
1416 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1417 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1419 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1422 //===----------------------------------------------------------------------===//
1423 // NEON pattern fragments
1424 //===----------------------------------------------------------------------===//
1426 // Extract D sub-registers of Q registers.
1427 def DSubReg_i8_reg : SDNodeXForm<imm, [{
1428 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1429 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
1431 def DSubReg_i16_reg : SDNodeXForm<imm, [{
1432 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1433 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
1435 def DSubReg_i32_reg : SDNodeXForm<imm, [{
1436 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1437 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
1439 def DSubReg_f64_reg : SDNodeXForm<imm, [{
1440 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1441 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
1444 // Extract S sub-registers of Q/D registers.
1445 def SSubReg_f32_reg : SDNodeXForm<imm, [{
1446 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
1447 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
1450 // Translate lane numbers from Q registers to D subregs.
1451 def SubReg_i8_lane : SDNodeXForm<imm, [{
1452 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
1454 def SubReg_i16_lane : SDNodeXForm<imm, [{
1455 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
1457 def SubReg_i32_lane : SDNodeXForm<imm, [{
1458 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
1461 //===----------------------------------------------------------------------===//
1462 // Instruction Classes
1463 //===----------------------------------------------------------------------===//
1465 // Basic 2-register operations: single-, double- and quad-register.
1466 class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1467 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1468 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1469 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
1470 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
1471 IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
1472 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1473 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1474 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1475 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1476 (ins DPR:$src), IIC_VUNAD, OpcodeStr, Dt,"$dst, $src", "",
1477 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
1478 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1479 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1480 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1481 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1482 (ins QPR:$src), IIC_VUNAQ, OpcodeStr, Dt,"$dst, $src", "",
1483 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
1485 // Basic 2-register intrinsics, both double- and quad-register.
1486 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1487 bits<2> op17_16, bits<5> op11_7, bit op4,
1488 InstrItinClass itin, string OpcodeStr, string Dt,
1489 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1490 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1491 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1492 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
1493 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1494 bits<2> op17_16, bits<5> op11_7, bit op4,
1495 InstrItinClass itin, string OpcodeStr, string Dt,
1496 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1497 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1498 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1499 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
1501 // Narrow 2-register operations.
1502 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1503 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1504 InstrItinClass itin, string OpcodeStr, string Dt,
1505 ValueType TyD, ValueType TyQ, SDNode OpNode>
1506 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
1507 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1508 [(set DPR:$dst, (TyD (OpNode (TyQ QPR:$src))))]>;
1510 // Narrow 2-register intrinsics.
1511 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1512 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1513 InstrItinClass itin, string OpcodeStr, string Dt,
1514 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
1515 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
1516 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1517 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
1519 // Long 2-register operations (currently only used for VMOVL).
1520 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1521 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1522 InstrItinClass itin, string OpcodeStr, string Dt,
1523 ValueType TyQ, ValueType TyD, SDNode OpNode>
1524 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$dst),
1525 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1526 [(set QPR:$dst, (TyQ (OpNode (TyD DPR:$src))))]>;
1528 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
1529 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
1530 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
1531 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
1532 OpcodeStr, Dt, "$dst1, $dst2",
1533 "$src1 = $dst1, $src2 = $dst2", []>;
1534 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
1535 InstrItinClass itin, string OpcodeStr, string Dt>
1536 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
1537 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$dst1, $dst2",
1538 "$src1 = $dst1, $src2 = $dst2", []>;
1540 // Basic 3-register operations: single-, double- and quad-register.
1541 class N3VS<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1542 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1543 SDNode OpNode, bit Commutable>
1544 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1545 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm,
1546 IIC_VBIND, OpcodeStr, Dt, "$dst, $src1, $src2", "", []> {
1547 let isCommutable = Commutable;
1550 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1551 InstrItinClass itin, string OpcodeStr, string Dt,
1552 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1553 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1554 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1555 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1556 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
1557 let isCommutable = Commutable;
1559 // Same as N3VD but no data type.
1560 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1561 InstrItinClass itin, string OpcodeStr,
1562 ValueType ResTy, ValueType OpTy,
1563 SDNode OpNode, bit Commutable>
1564 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
1565 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1566 OpcodeStr, "$Vd, $Vn, $Vm", "",
1567 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
1568 let isCommutable = Commutable;
1571 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
1572 InstrItinClass itin, string OpcodeStr, string Dt,
1573 ValueType Ty, SDNode ShOp>
1574 : N3V<0, 1, op21_20, op11_8, 1, 0,
1575 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1576 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1577 [(set (Ty DPR:$dst),
1578 (Ty (ShOp (Ty DPR:$src1),
1579 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),imm:$lane)))))]> {
1580 let isCommutable = 0;
1582 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
1583 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1584 : N3V<0, 1, op21_20, op11_8, 1, 0,
1585 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1586 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$dst, $src1, $src2[$lane]","",
1587 [(set (Ty DPR:$dst),
1588 (Ty (ShOp (Ty DPR:$src1),
1589 (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
1590 let isCommutable = 0;
1593 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1594 InstrItinClass itin, string OpcodeStr, string Dt,
1595 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1596 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1597 (outs QPR:$Qd), (ins QPR:$Qn, QPR:$Qm), N3RegFrm, itin,
1598 OpcodeStr, Dt, "$Qd, $Qn, $Qm", "",
1599 [(set QPR:$Qd, (ResTy (OpNode (OpTy QPR:$Qn), (OpTy QPR:$Qm))))]> {
1600 let isCommutable = Commutable;
1602 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1603 InstrItinClass itin, string OpcodeStr,
1604 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1605 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
1606 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, itin,
1607 OpcodeStr, "$dst, $src1, $src2", "",
1608 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]>{
1609 let isCommutable = Commutable;
1611 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
1612 InstrItinClass itin, string OpcodeStr, string Dt,
1613 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1614 : N3V<1, 1, op21_20, op11_8, 1, 0,
1615 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1616 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1617 [(set (ResTy QPR:$dst),
1618 (ResTy (ShOp (ResTy QPR:$src1),
1619 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1621 let isCommutable = 0;
1623 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
1624 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1625 : N3V<1, 1, op21_20, op11_8, 1, 0,
1626 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1627 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$dst, $src1, $src2[$lane]","",
1628 [(set (ResTy QPR:$dst),
1629 (ResTy (ShOp (ResTy QPR:$src1),
1630 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
1632 let isCommutable = 0;
1635 // Basic 3-register intrinsics, both double- and quad-register.
1636 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1637 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1638 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1639 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1640 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
1641 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1642 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
1643 let isCommutable = Commutable;
1645 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1646 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1647 : N3V<0, 1, op21_20, op11_8, 1, 0,
1648 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1649 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1650 [(set (Ty DPR:$dst),
1651 (Ty (IntOp (Ty DPR:$src1),
1652 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
1654 let isCommutable = 0;
1656 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1657 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1658 : N3V<0, 1, op21_20, op11_8, 1, 0,
1659 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1660 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1661 [(set (Ty DPR:$dst),
1662 (Ty (IntOp (Ty DPR:$src1),
1663 (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
1664 let isCommutable = 0;
1666 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1667 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1668 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1669 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1670 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
1671 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
1672 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
1673 let isCommutable = 0;
1676 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1677 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1678 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1679 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1680 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
1681 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1682 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
1683 let isCommutable = Commutable;
1685 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1686 string OpcodeStr, string Dt,
1687 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1688 : N3V<1, 1, op21_20, op11_8, 1, 0,
1689 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1690 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1691 [(set (ResTy QPR:$dst),
1692 (ResTy (IntOp (ResTy QPR:$src1),
1693 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1695 let isCommutable = 0;
1697 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1698 string OpcodeStr, string Dt,
1699 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1700 : N3V<1, 1, op21_20, op11_8, 1, 0,
1701 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1702 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1703 [(set (ResTy QPR:$dst),
1704 (ResTy (IntOp (ResTy QPR:$src1),
1705 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
1707 let isCommutable = 0;
1709 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1710 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1711 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1712 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1713 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
1714 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
1715 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
1716 let isCommutable = 0;
1719 // Multiply-Add/Sub operations: single-, double- and quad-register.
1720 class N3VSMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1721 InstrItinClass itin, string OpcodeStr, string Dt,
1722 ValueType Ty, SDNode MulOp, SDNode OpNode>
1723 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1724 (outs DPR_VFP2:$dst),
1725 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), N3RegFrm, itin,
1726 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst", []>;
1728 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1729 InstrItinClass itin, string OpcodeStr, string Dt,
1730 ValueType Ty, SDNode MulOp, SDNode OpNode>
1731 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1732 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1733 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1734 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
1735 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
1737 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1738 string OpcodeStr, string Dt,
1739 ValueType Ty, SDNode MulOp, SDNode ShOp>
1740 : N3V<0, 1, op21_20, op11_8, 1, 0,
1742 (ins DPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1744 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1745 [(set (Ty DPR:$dst),
1746 (Ty (ShOp (Ty DPR:$src1),
1747 (Ty (MulOp DPR:$src2,
1748 (Ty (NEONvduplane (Ty DPR_VFP2:$src3),
1750 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1751 string OpcodeStr, string Dt,
1752 ValueType Ty, SDNode MulOp, SDNode ShOp>
1753 : N3V<0, 1, op21_20, op11_8, 1, 0,
1755 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1757 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
1759 (Ty (ShOp (Ty DPR:$src1),
1761 (Ty (NEONvduplane (Ty DPR_8:$Vm),
1764 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1765 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
1766 SDNode MulOp, SDNode OpNode>
1767 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1768 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1769 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1770 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
1771 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
1772 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1773 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1774 SDNode MulOp, SDNode ShOp>
1775 : N3V<1, 1, op21_20, op11_8, 1, 0,
1777 (ins QPR:$src1, QPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1779 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1780 [(set (ResTy QPR:$dst),
1781 (ResTy (ShOp (ResTy QPR:$src1),
1782 (ResTy (MulOp QPR:$src2,
1783 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src3),
1785 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1786 string OpcodeStr, string Dt,
1787 ValueType ResTy, ValueType OpTy,
1788 SDNode MulOp, SDNode ShOp>
1789 : N3V<1, 1, op21_20, op11_8, 1, 0,
1791 (ins QPR:$src1, QPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1793 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1794 [(set (ResTy QPR:$dst),
1795 (ResTy (ShOp (ResTy QPR:$src1),
1796 (ResTy (MulOp QPR:$src2,
1797 (ResTy (NEONvduplane (OpTy DPR_8:$src3),
1800 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
1801 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1802 InstrItinClass itin, string OpcodeStr, string Dt,
1803 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
1804 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1805 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1806 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1807 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
1808 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
1809 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1810 InstrItinClass itin, string OpcodeStr, string Dt,
1811 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
1812 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1813 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1814 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1815 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
1816 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
1818 // Neon 3-argument intrinsics, both double- and quad-register.
1819 // The destination register is also used as the first source operand register.
1820 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1821 InstrItinClass itin, string OpcodeStr, string Dt,
1822 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1823 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1824 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1825 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1826 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
1827 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
1828 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1829 InstrItinClass itin, string OpcodeStr, string Dt,
1830 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1831 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1832 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), N3RegFrm, itin,
1833 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1834 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
1835 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
1837 // Long Multiply-Add/Sub operations.
1838 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1839 InstrItinClass itin, string OpcodeStr, string Dt,
1840 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
1841 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1842 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1843 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1844 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
1845 (TyQ (MulOp (TyD DPR:$Vn),
1846 (TyD DPR:$Vm)))))]>;
1847 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
1848 InstrItinClass itin, string OpcodeStr, string Dt,
1849 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
1850 : N3V<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$dst),
1851 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1853 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1855 (OpNode (TyQ QPR:$src1),
1856 (TyQ (MulOp (TyD DPR:$src2),
1857 (TyD (NEONvduplane (TyD DPR_VFP2:$src3),
1859 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1860 InstrItinClass itin, string OpcodeStr, string Dt,
1861 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
1862 : N3V<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$dst),
1863 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1865 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1867 (OpNode (TyQ QPR:$src1),
1868 (TyQ (MulOp (TyD DPR:$src2),
1869 (TyD (NEONvduplane (TyD DPR_8:$src3),
1872 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
1873 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1874 InstrItinClass itin, string OpcodeStr, string Dt,
1875 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
1877 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1878 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1879 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1880 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
1881 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
1882 (TyD DPR:$Vm)))))))]>;
1884 // Neon Long 3-argument intrinsic. The destination register is
1885 // a quad-register and is also used as the first source operand register.
1886 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1887 InstrItinClass itin, string OpcodeStr, string Dt,
1888 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
1889 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1890 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1891 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1893 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
1894 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1895 string OpcodeStr, string Dt,
1896 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1897 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1899 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1901 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1902 [(set (ResTy QPR:$dst),
1903 (ResTy (IntOp (ResTy QPR:$src1),
1905 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src3),
1907 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1908 InstrItinClass itin, string OpcodeStr, string Dt,
1909 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1910 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1912 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1914 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1915 [(set (ResTy QPR:$dst),
1916 (ResTy (IntOp (ResTy QPR:$src1),
1918 (OpTy (NEONvduplane (OpTy DPR_8:$src3),
1921 // Narrowing 3-register intrinsics.
1922 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1923 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
1924 Intrinsic IntOp, bit Commutable>
1925 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1926 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINi4D,
1927 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1928 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
1929 let isCommutable = Commutable;
1932 // Long 3-register operations.
1933 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1934 InstrItinClass itin, string OpcodeStr, string Dt,
1935 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
1936 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1937 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1938 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1939 [(set QPR:$dst, (TyQ (OpNode (TyD DPR:$src1), (TyD DPR:$src2))))]> {
1940 let isCommutable = Commutable;
1942 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
1943 InstrItinClass itin, string OpcodeStr, string Dt,
1944 ValueType TyQ, ValueType TyD, SDNode OpNode>
1945 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1946 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1947 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1949 (TyQ (OpNode (TyD DPR:$src1),
1950 (TyD (NEONvduplane (TyD DPR_VFP2:$src2),imm:$lane)))))]>;
1951 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1952 InstrItinClass itin, string OpcodeStr, string Dt,
1953 ValueType TyQ, ValueType TyD, SDNode OpNode>
1954 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1955 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1956 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1958 (TyQ (OpNode (TyD DPR:$src1),
1959 (TyD (NEONvduplane (TyD DPR_8:$src2), imm:$lane)))))]>;
1961 // Long 3-register operations with explicitly extended operands.
1962 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1963 InstrItinClass itin, string OpcodeStr, string Dt,
1964 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
1966 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1967 (outs QPR:$Qd), (ins DPR:$Dn, DPR:$Dm), N3RegFrm, itin,
1968 OpcodeStr, Dt, "$Qd, $Dn, $Dm", "",
1969 [(set QPR:$Qd, (OpNode (TyQ (ExtOp (TyD DPR:$Dn))),
1970 (TyQ (ExtOp (TyD DPR:$Dm)))))]> {
1971 let isCommutable = Commutable;
1974 // Long 3-register intrinsics with explicit extend (VABDL).
1975 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1976 InstrItinClass itin, string OpcodeStr, string Dt,
1977 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
1979 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1980 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1981 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1982 [(set QPR:$dst, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$src1),
1983 (TyD DPR:$src2))))))]> {
1984 let isCommutable = Commutable;
1987 // Long 3-register intrinsics.
1988 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1989 InstrItinClass itin, string OpcodeStr, string Dt,
1990 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
1991 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1992 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1993 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1994 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
1995 let isCommutable = Commutable;
1997 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1998 string OpcodeStr, string Dt,
1999 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2000 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2001 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
2002 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
2003 [(set (ResTy QPR:$dst),
2004 (ResTy (IntOp (OpTy DPR:$src1),
2005 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src2),
2007 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2008 InstrItinClass itin, string OpcodeStr, string Dt,
2009 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2010 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2011 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
2012 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
2013 [(set (ResTy QPR:$dst),
2014 (ResTy (IntOp (OpTy DPR:$src1),
2015 (OpTy (NEONvduplane (OpTy DPR_8:$src2),
2018 // Wide 3-register operations.
2019 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2020 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
2021 SDNode OpNode, SDNode ExtOp, bit Commutable>
2022 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2023 (outs QPR:$Qd), (ins QPR:$Qn, DPR:$Dm), N3RegFrm, IIC_VSUBiD,
2024 OpcodeStr, Dt, "$Qd, $Qn, $Dm", "",
2025 [(set QPR:$Qd, (OpNode (TyQ QPR:$Qn),
2026 (TyQ (ExtOp (TyD DPR:$Dm)))))]> {
2027 let isCommutable = Commutable;
2030 // Pairwise long 2-register intrinsics, both double- and quad-register.
2031 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2032 bits<2> op17_16, bits<5> op11_7, bit op4,
2033 string OpcodeStr, string Dt,
2034 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2035 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
2036 (ins DPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
2037 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
2038 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2039 bits<2> op17_16, bits<5> op11_7, bit op4,
2040 string OpcodeStr, string Dt,
2041 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2042 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
2043 (ins QPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
2044 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
2046 // Pairwise long 2-register accumulate intrinsics,
2047 // both double- and quad-register.
2048 // The destination register is also used as the first source operand register.
2049 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2050 bits<2> op17_16, bits<5> op11_7, bit op4,
2051 string OpcodeStr, string Dt,
2052 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2053 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
2054 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
2055 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2056 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
2057 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2058 bits<2> op17_16, bits<5> op11_7, bit op4,
2059 string OpcodeStr, string Dt,
2060 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2061 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
2062 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
2063 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2064 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
2066 // Shift by immediate,
2067 // both double- and quad-register.
2068 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2069 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2070 ValueType Ty, SDNode OpNode>
2071 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2072 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), f, itin,
2073 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
2074 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
2075 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2076 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2077 ValueType Ty, SDNode OpNode>
2078 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2079 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), f, itin,
2080 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
2081 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
2083 // Long shift by immediate.
2084 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2085 string OpcodeStr, string Dt,
2086 ValueType ResTy, ValueType OpTy, SDNode OpNode>
2087 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2088 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), N2RegVShLFrm,
2089 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
2090 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
2091 (i32 imm:$SIMM))))]>;
2093 // Narrow shift by immediate.
2094 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2095 InstrItinClass itin, string OpcodeStr, string Dt,
2096 ValueType ResTy, ValueType OpTy, SDNode OpNode>
2097 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2098 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), N2RegVShRFrm, itin,
2099 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
2100 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
2101 (i32 imm:$SIMM))))]>;
2103 // Shift right by immediate and accumulate,
2104 // both double- and quad-register.
2105 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2106 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2107 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2108 (ins DPR:$src1, DPR:$Vm, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2109 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2110 [(set DPR:$Vd, (Ty (add DPR:$src1,
2111 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
2112 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2113 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2114 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2115 (ins QPR:$src1, QPR:$Vm, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2116 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2117 [(set QPR:$Vd, (Ty (add QPR:$src1,
2118 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
2120 // Shift by immediate and insert,
2121 // both double- and quad-register.
2122 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2123 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
2124 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2125 (ins DPR:$src1, DPR:$Vm, i32imm:$SIMM), f, IIC_VSHLiD,
2126 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2127 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
2128 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2129 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
2130 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2131 (ins QPR:$src1, QPR:$Vm, i32imm:$SIMM), f, IIC_VSHLiQ,
2132 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2133 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
2135 // Convert, with fractional bits immediate,
2136 // both double- and quad-register.
2137 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2138 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2140 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2141 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2142 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2143 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
2144 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2145 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2147 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2148 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2149 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2150 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
2152 //===----------------------------------------------------------------------===//
2154 //===----------------------------------------------------------------------===//
2156 // Abbreviations used in multiclass suffixes:
2157 // Q = quarter int (8 bit) elements
2158 // H = half int (16 bit) elements
2159 // S = single int (32 bit) elements
2160 // D = double int (64 bit) elements
2162 // Neon 2-register vector operations -- for disassembly only.
2164 // First with only element sizes of 8, 16 and 32 bits:
2165 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2166 bits<5> op11_7, bit op4, string opc, string Dt,
2167 string asm, SDNode OpNode> {
2168 // 64-bit vector types.
2169 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
2170 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
2171 opc, !strconcat(Dt, "8"), asm, "",
2172 [(set DPR:$dst, (v8i8 (OpNode (v8i8 DPR:$src))))]>;
2173 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
2174 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
2175 opc, !strconcat(Dt, "16"), asm, "",
2176 [(set DPR:$dst, (v4i16 (OpNode (v4i16 DPR:$src))))]>;
2177 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2178 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
2179 opc, !strconcat(Dt, "32"), asm, "",
2180 [(set DPR:$dst, (v2i32 (OpNode (v2i32 DPR:$src))))]>;
2181 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2182 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
2183 opc, "f32", asm, "",
2184 [(set DPR:$dst, (v2f32 (OpNode (v2f32 DPR:$src))))]> {
2185 let Inst{10} = 1; // overwrite F = 1
2188 // 128-bit vector types.
2189 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
2190 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
2191 opc, !strconcat(Dt, "8"), asm, "",
2192 [(set QPR:$dst, (v16i8 (OpNode (v16i8 QPR:$src))))]>;
2193 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
2194 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
2195 opc, !strconcat(Dt, "16"), asm, "",
2196 [(set QPR:$dst, (v8i16 (OpNode (v8i16 QPR:$src))))]>;
2197 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2198 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
2199 opc, !strconcat(Dt, "32"), asm, "",
2200 [(set QPR:$dst, (v4i32 (OpNode (v4i32 QPR:$src))))]>;
2201 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2202 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
2203 opc, "f32", asm, "",
2204 [(set QPR:$dst, (v4f32 (OpNode (v4f32 QPR:$src))))]> {
2205 let Inst{10} = 1; // overwrite F = 1
2209 // Neon 3-register vector operations.
2211 // First with only element sizes of 8, 16 and 32 bits:
2212 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2213 InstrItinClass itinD16, InstrItinClass itinD32,
2214 InstrItinClass itinQ16, InstrItinClass itinQ32,
2215 string OpcodeStr, string Dt,
2216 SDNode OpNode, bit Commutable = 0> {
2217 // 64-bit vector types.
2218 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
2219 OpcodeStr, !strconcat(Dt, "8"),
2220 v8i8, v8i8, OpNode, Commutable>;
2221 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
2222 OpcodeStr, !strconcat(Dt, "16"),
2223 v4i16, v4i16, OpNode, Commutable>;
2224 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
2225 OpcodeStr, !strconcat(Dt, "32"),
2226 v2i32, v2i32, OpNode, Commutable>;
2228 // 128-bit vector types.
2229 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
2230 OpcodeStr, !strconcat(Dt, "8"),
2231 v16i8, v16i8, OpNode, Commutable>;
2232 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
2233 OpcodeStr, !strconcat(Dt, "16"),
2234 v8i16, v8i16, OpNode, Commutable>;
2235 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
2236 OpcodeStr, !strconcat(Dt, "32"),
2237 v4i32, v4i32, OpNode, Commutable>;
2240 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
2241 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2243 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
2245 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2246 v8i16, v4i16, ShOp>;
2247 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
2248 v4i32, v2i32, ShOp>;
2251 // ....then also with element size 64 bits:
2252 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2253 InstrItinClass itinD, InstrItinClass itinQ,
2254 string OpcodeStr, string Dt,
2255 SDNode OpNode, bit Commutable = 0>
2256 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
2257 OpcodeStr, Dt, OpNode, Commutable> {
2258 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
2259 OpcodeStr, !strconcat(Dt, "64"),
2260 v1i64, v1i64, OpNode, Commutable>;
2261 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
2262 OpcodeStr, !strconcat(Dt, "64"),
2263 v2i64, v2i64, OpNode, Commutable>;
2267 // Neon Narrowing 2-register vector operations,
2268 // source operand element sizes of 16, 32 and 64 bits:
2269 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2270 bits<5> op11_7, bit op6, bit op4,
2271 InstrItinClass itin, string OpcodeStr, string Dt,
2273 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2274 itin, OpcodeStr, !strconcat(Dt, "16"),
2275 v8i8, v8i16, OpNode>;
2276 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2277 itin, OpcodeStr, !strconcat(Dt, "32"),
2278 v4i16, v4i32, OpNode>;
2279 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2280 itin, OpcodeStr, !strconcat(Dt, "64"),
2281 v2i32, v2i64, OpNode>;
2284 // Neon Narrowing 2-register vector intrinsics,
2285 // source operand element sizes of 16, 32 and 64 bits:
2286 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2287 bits<5> op11_7, bit op6, bit op4,
2288 InstrItinClass itin, string OpcodeStr, string Dt,
2290 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2291 itin, OpcodeStr, !strconcat(Dt, "16"),
2292 v8i8, v8i16, IntOp>;
2293 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2294 itin, OpcodeStr, !strconcat(Dt, "32"),
2295 v4i16, v4i32, IntOp>;
2296 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2297 itin, OpcodeStr, !strconcat(Dt, "64"),
2298 v2i32, v2i64, IntOp>;
2302 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
2303 // source operand element sizes of 16, 32 and 64 bits:
2304 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
2305 string OpcodeStr, string Dt, SDNode OpNode> {
2306 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2307 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
2308 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2309 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2310 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2311 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2315 // Neon 3-register vector intrinsics.
2317 // First with only element sizes of 16 and 32 bits:
2318 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2319 InstrItinClass itinD16, InstrItinClass itinD32,
2320 InstrItinClass itinQ16, InstrItinClass itinQ32,
2321 string OpcodeStr, string Dt,
2322 Intrinsic IntOp, bit Commutable = 0> {
2323 // 64-bit vector types.
2324 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
2325 OpcodeStr, !strconcat(Dt, "16"),
2326 v4i16, v4i16, IntOp, Commutable>;
2327 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
2328 OpcodeStr, !strconcat(Dt, "32"),
2329 v2i32, v2i32, IntOp, Commutable>;
2331 // 128-bit vector types.
2332 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2333 OpcodeStr, !strconcat(Dt, "16"),
2334 v8i16, v8i16, IntOp, Commutable>;
2335 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2336 OpcodeStr, !strconcat(Dt, "32"),
2337 v4i32, v4i32, IntOp, Commutable>;
2339 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2340 InstrItinClass itinD16, InstrItinClass itinD32,
2341 InstrItinClass itinQ16, InstrItinClass itinQ32,
2342 string OpcodeStr, string Dt,
2344 // 64-bit vector types.
2345 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
2346 OpcodeStr, !strconcat(Dt, "16"),
2347 v4i16, v4i16, IntOp>;
2348 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
2349 OpcodeStr, !strconcat(Dt, "32"),
2350 v2i32, v2i32, IntOp>;
2352 // 128-bit vector types.
2353 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2354 OpcodeStr, !strconcat(Dt, "16"),
2355 v8i16, v8i16, IntOp>;
2356 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2357 OpcodeStr, !strconcat(Dt, "32"),
2358 v4i32, v4i32, IntOp>;
2361 multiclass N3VIntSL_HS<bits<4> op11_8,
2362 InstrItinClass itinD16, InstrItinClass itinD32,
2363 InstrItinClass itinQ16, InstrItinClass itinQ32,
2364 string OpcodeStr, string Dt, Intrinsic IntOp> {
2365 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
2366 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
2367 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
2368 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
2369 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
2370 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
2371 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
2372 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
2375 // ....then also with element size of 8 bits:
2376 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2377 InstrItinClass itinD16, InstrItinClass itinD32,
2378 InstrItinClass itinQ16, InstrItinClass itinQ32,
2379 string OpcodeStr, string Dt,
2380 Intrinsic IntOp, bit Commutable = 0>
2381 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2382 OpcodeStr, Dt, IntOp, Commutable> {
2383 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
2384 OpcodeStr, !strconcat(Dt, "8"),
2385 v8i8, v8i8, IntOp, Commutable>;
2386 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2387 OpcodeStr, !strconcat(Dt, "8"),
2388 v16i8, v16i8, IntOp, Commutable>;
2390 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2391 InstrItinClass itinD16, InstrItinClass itinD32,
2392 InstrItinClass itinQ16, InstrItinClass itinQ32,
2393 string OpcodeStr, string Dt,
2395 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2396 OpcodeStr, Dt, IntOp> {
2397 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
2398 OpcodeStr, !strconcat(Dt, "8"),
2400 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2401 OpcodeStr, !strconcat(Dt, "8"),
2402 v16i8, v16i8, IntOp>;
2406 // ....then also with element size of 64 bits:
2407 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2408 InstrItinClass itinD16, InstrItinClass itinD32,
2409 InstrItinClass itinQ16, InstrItinClass itinQ32,
2410 string OpcodeStr, string Dt,
2411 Intrinsic IntOp, bit Commutable = 0>
2412 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2413 OpcodeStr, Dt, IntOp, Commutable> {
2414 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
2415 OpcodeStr, !strconcat(Dt, "64"),
2416 v1i64, v1i64, IntOp, Commutable>;
2417 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2418 OpcodeStr, !strconcat(Dt, "64"),
2419 v2i64, v2i64, IntOp, Commutable>;
2421 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2422 InstrItinClass itinD16, InstrItinClass itinD32,
2423 InstrItinClass itinQ16, InstrItinClass itinQ32,
2424 string OpcodeStr, string Dt,
2426 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2427 OpcodeStr, Dt, IntOp> {
2428 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
2429 OpcodeStr, !strconcat(Dt, "64"),
2430 v1i64, v1i64, IntOp>;
2431 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2432 OpcodeStr, !strconcat(Dt, "64"),
2433 v2i64, v2i64, IntOp>;
2436 // Neon Narrowing 3-register vector intrinsics,
2437 // source operand element sizes of 16, 32 and 64 bits:
2438 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2439 string OpcodeStr, string Dt,
2440 Intrinsic IntOp, bit Commutable = 0> {
2441 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
2442 OpcodeStr, !strconcat(Dt, "16"),
2443 v8i8, v8i16, IntOp, Commutable>;
2444 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
2445 OpcodeStr, !strconcat(Dt, "32"),
2446 v4i16, v4i32, IntOp, Commutable>;
2447 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
2448 OpcodeStr, !strconcat(Dt, "64"),
2449 v2i32, v2i64, IntOp, Commutable>;
2453 // Neon Long 3-register vector operations.
2455 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2456 InstrItinClass itin16, InstrItinClass itin32,
2457 string OpcodeStr, string Dt,
2458 SDNode OpNode, bit Commutable = 0> {
2459 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
2460 OpcodeStr, !strconcat(Dt, "8"),
2461 v8i16, v8i8, OpNode, Commutable>;
2462 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
2463 OpcodeStr, !strconcat(Dt, "16"),
2464 v4i32, v4i16, OpNode, Commutable>;
2465 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
2466 OpcodeStr, !strconcat(Dt, "32"),
2467 v2i64, v2i32, OpNode, Commutable>;
2470 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
2471 InstrItinClass itin, string OpcodeStr, string Dt,
2473 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
2474 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2475 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
2476 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2479 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2480 InstrItinClass itin16, InstrItinClass itin32,
2481 string OpcodeStr, string Dt,
2482 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2483 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
2484 OpcodeStr, !strconcat(Dt, "8"),
2485 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2486 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
2487 OpcodeStr, !strconcat(Dt, "16"),
2488 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2489 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
2490 OpcodeStr, !strconcat(Dt, "32"),
2491 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2494 // Neon Long 3-register vector intrinsics.
2496 // First with only element sizes of 16 and 32 bits:
2497 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2498 InstrItinClass itin16, InstrItinClass itin32,
2499 string OpcodeStr, string Dt,
2500 Intrinsic IntOp, bit Commutable = 0> {
2501 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
2502 OpcodeStr, !strconcat(Dt, "16"),
2503 v4i32, v4i16, IntOp, Commutable>;
2504 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
2505 OpcodeStr, !strconcat(Dt, "32"),
2506 v2i64, v2i32, IntOp, Commutable>;
2509 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
2510 InstrItinClass itin, string OpcodeStr, string Dt,
2512 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
2513 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2514 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
2515 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2518 // ....then also with element size of 8 bits:
2519 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2520 InstrItinClass itin16, InstrItinClass itin32,
2521 string OpcodeStr, string Dt,
2522 Intrinsic IntOp, bit Commutable = 0>
2523 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
2524 IntOp, Commutable> {
2525 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
2526 OpcodeStr, !strconcat(Dt, "8"),
2527 v8i16, v8i8, IntOp, Commutable>;
2530 // ....with explicit extend (VABDL).
2531 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2532 InstrItinClass itin, string OpcodeStr, string Dt,
2533 Intrinsic IntOp, SDNode ExtOp, bit Commutable = 0> {
2534 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
2535 OpcodeStr, !strconcat(Dt, "8"),
2536 v8i16, v8i8, IntOp, ExtOp, Commutable>;
2537 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
2538 OpcodeStr, !strconcat(Dt, "16"),
2539 v4i32, v4i16, IntOp, ExtOp, Commutable>;
2540 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
2541 OpcodeStr, !strconcat(Dt, "32"),
2542 v2i64, v2i32, IntOp, ExtOp, Commutable>;
2546 // Neon Wide 3-register vector intrinsics,
2547 // source operand element sizes of 8, 16 and 32 bits:
2548 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2549 string OpcodeStr, string Dt,
2550 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2551 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
2552 OpcodeStr, !strconcat(Dt, "8"),
2553 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2554 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
2555 OpcodeStr, !strconcat(Dt, "16"),
2556 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2557 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
2558 OpcodeStr, !strconcat(Dt, "32"),
2559 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2563 // Neon Multiply-Op vector operations,
2564 // element sizes of 8, 16 and 32 bits:
2565 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2566 InstrItinClass itinD16, InstrItinClass itinD32,
2567 InstrItinClass itinQ16, InstrItinClass itinQ32,
2568 string OpcodeStr, string Dt, SDNode OpNode> {
2569 // 64-bit vector types.
2570 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
2571 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
2572 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
2573 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
2574 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
2575 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
2577 // 128-bit vector types.
2578 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
2579 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
2580 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
2581 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
2582 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
2583 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
2586 multiclass N3VMulOpSL_HS<bits<4> op11_8,
2587 InstrItinClass itinD16, InstrItinClass itinD32,
2588 InstrItinClass itinQ16, InstrItinClass itinQ32,
2589 string OpcodeStr, string Dt, SDNode ShOp> {
2590 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
2591 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
2592 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
2593 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
2594 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
2595 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
2597 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
2598 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
2602 // Neon Intrinsic-Op vector operations,
2603 // element sizes of 8, 16 and 32 bits:
2604 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2605 InstrItinClass itinD, InstrItinClass itinQ,
2606 string OpcodeStr, string Dt, Intrinsic IntOp,
2608 // 64-bit vector types.
2609 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
2610 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
2611 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
2612 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
2613 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
2614 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
2616 // 128-bit vector types.
2617 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
2618 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
2619 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
2620 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
2621 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
2622 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
2625 // Neon 3-argument intrinsics,
2626 // element sizes of 8, 16 and 32 bits:
2627 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2628 InstrItinClass itinD, InstrItinClass itinQ,
2629 string OpcodeStr, string Dt, Intrinsic IntOp> {
2630 // 64-bit vector types.
2631 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
2632 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2633 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
2634 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
2635 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
2636 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
2638 // 128-bit vector types.
2639 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
2640 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
2641 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
2642 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
2643 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
2644 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
2648 // Neon Long Multiply-Op vector operations,
2649 // element sizes of 8, 16 and 32 bits:
2650 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2651 InstrItinClass itin16, InstrItinClass itin32,
2652 string OpcodeStr, string Dt, SDNode MulOp,
2654 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
2655 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
2656 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
2657 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
2658 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
2659 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
2662 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
2663 string Dt, SDNode MulOp, SDNode OpNode> {
2664 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
2665 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
2666 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
2667 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
2671 // Neon Long 3-argument intrinsics.
2673 // First with only element sizes of 16 and 32 bits:
2674 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2675 InstrItinClass itin16, InstrItinClass itin32,
2676 string OpcodeStr, string Dt, Intrinsic IntOp> {
2677 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
2678 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2679 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
2680 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2683 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
2684 string OpcodeStr, string Dt, Intrinsic IntOp> {
2685 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
2686 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
2687 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
2688 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2691 // ....then also with element size of 8 bits:
2692 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2693 InstrItinClass itin16, InstrItinClass itin32,
2694 string OpcodeStr, string Dt, Intrinsic IntOp>
2695 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
2696 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
2697 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
2700 // ....with explicit extend (VABAL).
2701 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2702 InstrItinClass itin, string OpcodeStr, string Dt,
2703 Intrinsic IntOp, SDNode ExtOp, SDNode OpNode> {
2704 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
2705 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
2706 IntOp, ExtOp, OpNode>;
2707 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
2708 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
2709 IntOp, ExtOp, OpNode>;
2710 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
2711 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
2712 IntOp, ExtOp, OpNode>;
2716 // Neon 2-register vector intrinsics,
2717 // element sizes of 8, 16 and 32 bits:
2718 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2719 bits<5> op11_7, bit op4,
2720 InstrItinClass itinD, InstrItinClass itinQ,
2721 string OpcodeStr, string Dt, Intrinsic IntOp> {
2722 // 64-bit vector types.
2723 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2724 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2725 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2726 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
2727 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2728 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
2730 // 128-bit vector types.
2731 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2732 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
2733 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2734 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
2735 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2736 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
2740 // Neon Pairwise long 2-register intrinsics,
2741 // element sizes of 8, 16 and 32 bits:
2742 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2743 bits<5> op11_7, bit op4,
2744 string OpcodeStr, string Dt, Intrinsic IntOp> {
2745 // 64-bit vector types.
2746 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2747 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
2748 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2749 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
2750 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2751 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
2753 // 128-bit vector types.
2754 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2755 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
2756 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2757 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
2758 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2759 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
2763 // Neon Pairwise long 2-register accumulate intrinsics,
2764 // element sizes of 8, 16 and 32 bits:
2765 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2766 bits<5> op11_7, bit op4,
2767 string OpcodeStr, string Dt, Intrinsic IntOp> {
2768 // 64-bit vector types.
2769 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2770 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
2771 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2772 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
2773 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2774 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
2776 // 128-bit vector types.
2777 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2778 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
2779 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2780 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
2781 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2782 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
2786 // Neon 2-register vector shift by immediate,
2787 // with f of either N2RegVShLFrm or N2RegVShRFrm
2788 // element sizes of 8, 16, 32 and 64 bits:
2789 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2790 InstrItinClass itin, string OpcodeStr, string Dt,
2791 SDNode OpNode, Format f> {
2792 // 64-bit vector types.
2793 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2794 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
2795 let Inst{21-19} = 0b001; // imm6 = 001xxx
2797 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2798 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
2799 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2801 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2802 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
2803 let Inst{21} = 0b1; // imm6 = 1xxxxx
2805 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, f, itin,
2806 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
2809 // 128-bit vector types.
2810 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
2811 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
2812 let Inst{21-19} = 0b001; // imm6 = 001xxx
2814 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
2815 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
2816 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2818 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
2819 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
2820 let Inst{21} = 0b1; // imm6 = 1xxxxx
2822 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, f, itin,
2823 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
2827 // Neon Shift-Accumulate vector operations,
2828 // element sizes of 8, 16, 32 and 64 bits:
2829 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2830 string OpcodeStr, string Dt, SDNode ShOp> {
2831 // 64-bit vector types.
2832 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4,
2833 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
2834 let Inst{21-19} = 0b001; // imm6 = 001xxx
2836 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4,
2837 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
2838 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2840 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4,
2841 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
2842 let Inst{21} = 0b1; // imm6 = 1xxxxx
2844 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4,
2845 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
2848 // 128-bit vector types.
2849 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4,
2850 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
2851 let Inst{21-19} = 0b001; // imm6 = 001xxx
2853 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4,
2854 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
2855 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2857 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4,
2858 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
2859 let Inst{21} = 0b1; // imm6 = 1xxxxx
2861 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4,
2862 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
2867 // Neon Shift-Insert vector operations,
2868 // with f of either N2RegVShLFrm or N2RegVShRFrm
2869 // element sizes of 8, 16, 32 and 64 bits:
2870 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2871 string OpcodeStr, SDNode ShOp,
2873 // 64-bit vector types.
2874 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4,
2875 f, OpcodeStr, "8", v8i8, ShOp> {
2876 let Inst{21-19} = 0b001; // imm6 = 001xxx
2878 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4,
2879 f, OpcodeStr, "16", v4i16, ShOp> {
2880 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2882 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4,
2883 f, OpcodeStr, "32", v2i32, ShOp> {
2884 let Inst{21} = 0b1; // imm6 = 1xxxxx
2886 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4,
2887 f, OpcodeStr, "64", v1i64, ShOp>;
2890 // 128-bit vector types.
2891 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4,
2892 f, OpcodeStr, "8", v16i8, ShOp> {
2893 let Inst{21-19} = 0b001; // imm6 = 001xxx
2895 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4,
2896 f, OpcodeStr, "16", v8i16, ShOp> {
2897 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2899 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4,
2900 f, OpcodeStr, "32", v4i32, ShOp> {
2901 let Inst{21} = 0b1; // imm6 = 1xxxxx
2903 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4,
2904 f, OpcodeStr, "64", v2i64, ShOp>;
2908 // Neon Shift Long operations,
2909 // element sizes of 8, 16, 32 bits:
2910 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
2911 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
2912 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
2913 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
2914 let Inst{21-19} = 0b001; // imm6 = 001xxx
2916 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
2917 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
2918 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2920 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
2921 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
2922 let Inst{21} = 0b1; // imm6 = 1xxxxx
2926 // Neon Shift Narrow operations,
2927 // element sizes of 16, 32, 64 bits:
2928 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
2929 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
2931 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
2932 OpcodeStr, !strconcat(Dt, "16"), v8i8, v8i16, OpNode> {
2933 let Inst{21-19} = 0b001; // imm6 = 001xxx
2935 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
2936 OpcodeStr, !strconcat(Dt, "32"), v4i16, v4i32, OpNode> {
2937 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2939 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
2940 OpcodeStr, !strconcat(Dt, "64"), v2i32, v2i64, OpNode> {
2941 let Inst{21} = 0b1; // imm6 = 1xxxxx
2945 //===----------------------------------------------------------------------===//
2946 // Instruction Definitions.
2947 //===----------------------------------------------------------------------===//
2949 // Vector Add Operations.
2951 // VADD : Vector Add (integer and floating-point)
2952 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
2954 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
2955 v2f32, v2f32, fadd, 1>;
2956 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
2957 v4f32, v4f32, fadd, 1>;
2958 // VADDL : Vector Add Long (Q = D + D)
2959 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
2960 "vaddl", "s", add, sext, 1>;
2961 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
2962 "vaddl", "u", add, zext, 1>;
2963 // VADDW : Vector Add Wide (Q = Q + D)
2964 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
2965 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
2966 // VHADD : Vector Halving Add
2967 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
2968 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2969 "vhadd", "s", int_arm_neon_vhadds, 1>;
2970 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
2971 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2972 "vhadd", "u", int_arm_neon_vhaddu, 1>;
2973 // VRHADD : Vector Rounding Halving Add
2974 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
2975 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2976 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
2977 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
2978 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2979 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
2980 // VQADD : Vector Saturating Add
2981 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
2982 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2983 "vqadd", "s", int_arm_neon_vqadds, 1>;
2984 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
2985 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2986 "vqadd", "u", int_arm_neon_vqaddu, 1>;
2987 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
2988 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
2989 int_arm_neon_vaddhn, 1>;
2990 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
2991 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
2992 int_arm_neon_vraddhn, 1>;
2994 // Vector Multiply Operations.
2996 // VMUL : Vector Multiply (integer, polynomial and floating-point)
2997 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
2998 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
2999 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
3000 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
3001 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
3002 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
3003 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
3004 v2f32, v2f32, fmul, 1>;
3005 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
3006 v4f32, v4f32, fmul, 1>;
3007 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
3008 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
3009 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
3012 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
3013 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
3014 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
3015 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3016 (DSubReg_i16_reg imm:$lane))),
3017 (SubReg_i16_lane imm:$lane)))>;
3018 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
3019 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
3020 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
3021 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3022 (DSubReg_i32_reg imm:$lane))),
3023 (SubReg_i32_lane imm:$lane)))>;
3024 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
3025 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
3026 (v4f32 (VMULslfq (v4f32 QPR:$src1),
3027 (v2f32 (EXTRACT_SUBREG QPR:$src2,
3028 (DSubReg_i32_reg imm:$lane))),
3029 (SubReg_i32_lane imm:$lane)))>;
3031 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
3032 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
3033 IIC_VMULi16Q, IIC_VMULi32Q,
3034 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
3035 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
3036 IIC_VMULi16Q, IIC_VMULi32Q,
3037 "vqdmulh", "s", int_arm_neon_vqdmulh>;
3038 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
3039 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3041 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
3042 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3043 (DSubReg_i16_reg imm:$lane))),
3044 (SubReg_i16_lane imm:$lane)))>;
3045 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
3046 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3048 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
3049 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3050 (DSubReg_i32_reg imm:$lane))),
3051 (SubReg_i32_lane imm:$lane)))>;
3053 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
3054 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
3055 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
3056 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
3057 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
3058 IIC_VMULi16Q, IIC_VMULi32Q,
3059 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
3060 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
3061 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3063 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
3064 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3065 (DSubReg_i16_reg imm:$lane))),
3066 (SubReg_i16_lane imm:$lane)))>;
3067 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
3068 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3070 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
3071 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3072 (DSubReg_i32_reg imm:$lane))),
3073 (SubReg_i32_lane imm:$lane)))>;
3075 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
3076 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3077 "vmull", "s", NEONvmulls, 1>;
3078 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3079 "vmull", "u", NEONvmullu, 1>;
3080 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
3081 v8i16, v8i8, int_arm_neon_vmullp, 1>;
3082 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
3083 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
3085 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
3086 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
3087 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
3088 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
3089 "vqdmull", "s", int_arm_neon_vqdmull>;
3091 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
3093 // VMLA : Vector Multiply Accumulate (integer and floating-point)
3094 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3095 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3096 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
3098 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
3100 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
3101 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3102 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
3104 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
3105 v4f32, v2f32, fmul, fadd>;
3107 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
3108 (mul (v8i16 QPR:$src2),
3109 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3110 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3111 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3112 (DSubReg_i16_reg imm:$lane))),
3113 (SubReg_i16_lane imm:$lane)))>;
3115 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
3116 (mul (v4i32 QPR:$src2),
3117 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3118 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3119 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3120 (DSubReg_i32_reg imm:$lane))),
3121 (SubReg_i32_lane imm:$lane)))>;
3123 def : Pat<(v4f32 (fadd (v4f32 QPR:$src1),
3124 (fmul (v4f32 QPR:$src2),
3125 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3126 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
3128 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3129 (DSubReg_i32_reg imm:$lane))),
3130 (SubReg_i32_lane imm:$lane)))>;
3132 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
3133 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3134 "vmlal", "s", NEONvmulls, add>;
3135 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3136 "vmlal", "u", NEONvmullu, add>;
3138 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
3139 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
3141 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
3142 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3143 "vqdmlal", "s", int_arm_neon_vqdmlal>;
3144 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
3146 // VMLS : Vector Multiply Subtract (integer and floating-point)
3147 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3148 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3149 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
3151 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
3153 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
3154 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3155 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
3157 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
3158 v4f32, v2f32, fmul, fsub>;
3160 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
3161 (mul (v8i16 QPR:$src2),
3162 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3163 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3164 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3165 (DSubReg_i16_reg imm:$lane))),
3166 (SubReg_i16_lane imm:$lane)))>;
3168 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
3169 (mul (v4i32 QPR:$src2),
3170 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3171 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3172 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3173 (DSubReg_i32_reg imm:$lane))),
3174 (SubReg_i32_lane imm:$lane)))>;
3176 def : Pat<(v4f32 (fsub (v4f32 QPR:$src1),
3177 (fmul (v4f32 QPR:$src2),
3178 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3179 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
3180 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3181 (DSubReg_i32_reg imm:$lane))),
3182 (SubReg_i32_lane imm:$lane)))>;
3184 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
3185 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3186 "vmlsl", "s", NEONvmulls, sub>;
3187 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3188 "vmlsl", "u", NEONvmullu, sub>;
3190 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
3191 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
3193 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
3194 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
3195 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3196 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3198 // Vector Subtract Operations.
3200 // VSUB : Vector Subtract (integer and floating-point)
3201 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
3202 "vsub", "i", sub, 0>;
3203 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
3204 v2f32, v2f32, fsub, 0>;
3205 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
3206 v4f32, v4f32, fsub, 0>;
3207 // VSUBL : Vector Subtract Long (Q = D - D)
3208 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3209 "vsubl", "s", sub, sext, 0>;
3210 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3211 "vsubl", "u", sub, zext, 0>;
3212 // VSUBW : Vector Subtract Wide (Q = Q - D)
3213 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
3214 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
3215 // VHSUB : Vector Halving Subtract
3216 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
3217 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3218 "vhsub", "s", int_arm_neon_vhsubs, 0>;
3219 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
3220 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3221 "vhsub", "u", int_arm_neon_vhsubu, 0>;
3222 // VQSUB : Vector Saturing Subtract
3223 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
3224 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3225 "vqsub", "s", int_arm_neon_vqsubs, 0>;
3226 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
3227 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3228 "vqsub", "u", int_arm_neon_vqsubu, 0>;
3229 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
3230 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
3231 int_arm_neon_vsubhn, 0>;
3232 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
3233 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
3234 int_arm_neon_vrsubhn, 0>;
3236 // Vector Comparisons.
3238 // VCEQ : Vector Compare Equal
3239 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3240 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
3241 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
3243 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
3246 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
3247 "$dst, $src, #0", NEONvceqz>;
3249 // VCGE : Vector Compare Greater Than or Equal
3250 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3251 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
3252 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3253 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
3254 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
3256 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
3259 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
3260 "$dst, $src, #0", NEONvcgez>;
3261 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
3262 "$dst, $src, #0", NEONvclez>;
3264 // VCGT : Vector Compare Greater Than
3265 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3266 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
3267 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3268 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
3269 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
3271 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
3274 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
3275 "$dst, $src, #0", NEONvcgtz>;
3276 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
3277 "$dst, $src, #0", NEONvcltz>;
3279 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
3280 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
3281 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
3282 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
3283 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
3284 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
3285 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
3286 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
3287 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
3288 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
3289 // VTST : Vector Test Bits
3290 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
3291 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
3293 // Vector Bitwise Operations.
3295 def vnotd : PatFrag<(ops node:$in),
3296 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
3297 def vnotq : PatFrag<(ops node:$in),
3298 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
3301 // VAND : Vector Bitwise AND
3302 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
3303 v2i32, v2i32, and, 1>;
3304 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
3305 v4i32, v4i32, and, 1>;
3307 // VEOR : Vector Bitwise Exclusive OR
3308 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
3309 v2i32, v2i32, xor, 1>;
3310 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
3311 v4i32, v4i32, xor, 1>;
3313 // VORR : Vector Bitwise OR
3314 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
3315 v2i32, v2i32, or, 1>;
3316 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
3317 v4i32, v4i32, or, 1>;
3319 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
3320 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3322 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3324 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3325 let Inst{9} = SIMM{9};
3328 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
3329 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3331 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3333 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3334 let Inst{10-9} = SIMM{10-9};
3337 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
3338 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3340 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3342 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3343 let Inst{9} = SIMM{9};
3346 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
3347 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3349 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3351 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3352 let Inst{10-9} = SIMM{10-9};
3356 // VBIC : Vector Bitwise Bit Clear (AND NOT)
3357 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
3358 (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD,
3359 "vbic", "$dst, $src1, $src2", "",
3360 [(set DPR:$dst, (v2i32 (and DPR:$src1,
3361 (vnotd DPR:$src2))))]>;
3362 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
3363 (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINiQ,
3364 "vbic", "$dst, $src1, $src2", "",
3365 [(set QPR:$dst, (v4i32 (and QPR:$src1,
3366 (vnotq QPR:$src2))))]>;
3368 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
3369 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3371 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3373 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3374 let Inst{9} = SIMM{9};
3377 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
3378 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3380 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3382 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3383 let Inst{10-9} = SIMM{10-9};
3386 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
3387 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3389 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3391 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3392 let Inst{9} = SIMM{9};
3395 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
3396 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3398 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3400 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3401 let Inst{10-9} = SIMM{10-9};
3404 // VORN : Vector Bitwise OR NOT
3405 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
3406 (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD,
3407 "vorn", "$dst, $src1, $src2", "",
3408 [(set DPR:$dst, (v2i32 (or DPR:$src1,
3409 (vnotd DPR:$src2))))]>;
3410 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
3411 (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINiQ,
3412 "vorn", "$dst, $src1, $src2", "",
3413 [(set QPR:$dst, (v4i32 (or QPR:$src1,
3414 (vnotq QPR:$src2))))]>;
3416 // VMVN : Vector Bitwise NOT (Immediate)
3418 let isReMaterializable = 1 in {
3420 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$dst),
3421 (ins nModImm:$SIMM), IIC_VMOVImm,
3422 "vmvn", "i16", "$dst, $SIMM", "",
3423 [(set DPR:$dst, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
3424 let Inst{9} = SIMM{9};
3427 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$dst),
3428 (ins nModImm:$SIMM), IIC_VMOVImm,
3429 "vmvn", "i16", "$dst, $SIMM", "",
3430 [(set QPR:$dst, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
3431 let Inst{9} = SIMM{9};
3434 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$dst),
3435 (ins nModImm:$SIMM), IIC_VMOVImm,
3436 "vmvn", "i32", "$dst, $SIMM", "",
3437 [(set DPR:$dst, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
3438 let Inst{11-8} = SIMM{11-8};
3441 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$dst),
3442 (ins nModImm:$SIMM), IIC_VMOVImm,
3443 "vmvn", "i32", "$dst, $SIMM", "",
3444 [(set QPR:$dst, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
3445 let Inst{11-8} = SIMM{11-8};
3449 // VMVN : Vector Bitwise NOT
3450 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
3451 (outs DPR:$dst), (ins DPR:$src), IIC_VSUBiD,
3452 "vmvn", "$dst, $src", "",
3453 [(set DPR:$dst, (v2i32 (vnotd DPR:$src)))]>;
3454 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
3455 (outs QPR:$dst), (ins QPR:$src), IIC_VSUBiD,
3456 "vmvn", "$dst, $src", "",
3457 [(set QPR:$dst, (v4i32 (vnotq QPR:$src)))]>;
3458 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
3459 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
3461 // VBSL : Vector Bitwise Select
3462 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
3463 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3464 N3RegFrm, IIC_VCNTiD,
3465 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3467 (v2i32 (or (and DPR:$Vn, DPR:$src1),
3468 (and DPR:$Vm, (vnotd DPR:$src1)))))]>;
3469 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
3470 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3471 N3RegFrm, IIC_VCNTiQ,
3472 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3474 (v4i32 (or (and QPR:$Vn, QPR:$src1),
3475 (and QPR:$Vm, (vnotq QPR:$src1)))))]>;
3477 // VBIF : Vector Bitwise Insert if False
3478 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
3479 // FIXME: This instruction's encoding MAY NOT BE correct.
3480 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
3481 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3482 N3RegFrm, IIC_VBINiD,
3483 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3484 [/* For disassembly only; pattern left blank */]>;
3485 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
3486 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3487 N3RegFrm, IIC_VBINiQ,
3488 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3489 [/* For disassembly only; pattern left blank */]>;
3491 // VBIT : Vector Bitwise Insert if True
3492 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
3493 // FIXME: This instruction's encoding MAY NOT BE correct.
3494 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
3495 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3496 N3RegFrm, IIC_VBINiD,
3497 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3498 [/* For disassembly only; pattern left blank */]>;
3499 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
3500 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3501 N3RegFrm, IIC_VBINiQ,
3502 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3503 [/* For disassembly only; pattern left blank */]>;
3505 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
3506 // for equivalent operations with different register constraints; it just
3509 // Vector Absolute Differences.
3511 // VABD : Vector Absolute Difference
3512 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
3513 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3514 "vabd", "s", int_arm_neon_vabds, 1>;
3515 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
3516 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3517 "vabd", "u", int_arm_neon_vabdu, 1>;
3518 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
3519 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
3520 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
3521 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
3523 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
3524 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
3525 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
3526 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
3527 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
3529 // VABA : Vector Absolute Difference and Accumulate
3530 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3531 "vaba", "s", int_arm_neon_vabds, add>;
3532 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3533 "vaba", "u", int_arm_neon_vabdu, add>;
3535 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
3536 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
3537 "vabal", "s", int_arm_neon_vabds, zext, add>;
3538 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
3539 "vabal", "u", int_arm_neon_vabdu, zext, add>;
3541 // Vector Maximum and Minimum.
3543 // VMAX : Vector Maximum
3544 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
3545 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3546 "vmax", "s", int_arm_neon_vmaxs, 1>;
3547 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
3548 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3549 "vmax", "u", int_arm_neon_vmaxu, 1>;
3550 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
3552 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
3553 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
3555 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
3557 // VMIN : Vector Minimum
3558 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
3559 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3560 "vmin", "s", int_arm_neon_vmins, 1>;
3561 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
3562 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3563 "vmin", "u", int_arm_neon_vminu, 1>;
3564 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
3566 v2f32, v2f32, int_arm_neon_vmins, 1>;
3567 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
3569 v4f32, v4f32, int_arm_neon_vmins, 1>;
3571 // Vector Pairwise Operations.
3573 // VPADD : Vector Pairwise Add
3574 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3576 v8i8, v8i8, int_arm_neon_vpadd, 0>;
3577 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3579 v4i16, v4i16, int_arm_neon_vpadd, 0>;
3580 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3582 v2i32, v2i32, int_arm_neon_vpadd, 0>;
3583 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
3584 IIC_VPBIND, "vpadd", "f32",
3585 v2f32, v2f32, int_arm_neon_vpadd, 0>;
3587 // VPADDL : Vector Pairwise Add Long
3588 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
3589 int_arm_neon_vpaddls>;
3590 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
3591 int_arm_neon_vpaddlu>;
3593 // VPADAL : Vector Pairwise Add and Accumulate Long
3594 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
3595 int_arm_neon_vpadals>;
3596 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
3597 int_arm_neon_vpadalu>;
3599 // VPMAX : Vector Pairwise Maximum
3600 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3601 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
3602 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3603 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
3604 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3605 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
3606 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3607 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
3608 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3609 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
3610 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3611 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
3612 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
3613 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
3615 // VPMIN : Vector Pairwise Minimum
3616 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3617 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
3618 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3619 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
3620 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3621 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
3622 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3623 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
3624 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3625 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
3626 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3627 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
3628 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
3629 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
3631 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
3633 // VRECPE : Vector Reciprocal Estimate
3634 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
3635 IIC_VUNAD, "vrecpe", "u32",
3636 v2i32, v2i32, int_arm_neon_vrecpe>;
3637 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
3638 IIC_VUNAQ, "vrecpe", "u32",
3639 v4i32, v4i32, int_arm_neon_vrecpe>;
3640 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
3641 IIC_VUNAD, "vrecpe", "f32",
3642 v2f32, v2f32, int_arm_neon_vrecpe>;
3643 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
3644 IIC_VUNAQ, "vrecpe", "f32",
3645 v4f32, v4f32, int_arm_neon_vrecpe>;
3647 // VRECPS : Vector Reciprocal Step
3648 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
3649 IIC_VRECSD, "vrecps", "f32",
3650 v2f32, v2f32, int_arm_neon_vrecps, 1>;
3651 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
3652 IIC_VRECSQ, "vrecps", "f32",
3653 v4f32, v4f32, int_arm_neon_vrecps, 1>;
3655 // VRSQRTE : Vector Reciprocal Square Root Estimate
3656 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
3657 IIC_VUNAD, "vrsqrte", "u32",
3658 v2i32, v2i32, int_arm_neon_vrsqrte>;
3659 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
3660 IIC_VUNAQ, "vrsqrte", "u32",
3661 v4i32, v4i32, int_arm_neon_vrsqrte>;
3662 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
3663 IIC_VUNAD, "vrsqrte", "f32",
3664 v2f32, v2f32, int_arm_neon_vrsqrte>;
3665 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
3666 IIC_VUNAQ, "vrsqrte", "f32",
3667 v4f32, v4f32, int_arm_neon_vrsqrte>;
3669 // VRSQRTS : Vector Reciprocal Square Root Step
3670 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
3671 IIC_VRECSD, "vrsqrts", "f32",
3672 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
3673 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
3674 IIC_VRECSQ, "vrsqrts", "f32",
3675 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
3679 // VSHL : Vector Shift
3680 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
3681 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
3682 "vshl", "s", int_arm_neon_vshifts>;
3683 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
3684 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
3685 "vshl", "u", int_arm_neon_vshiftu>;
3686 // VSHL : Vector Shift Left (Immediate)
3687 defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl,
3689 // VSHR : Vector Shift Right (Immediate)
3690 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", NEONvshrs,
3692 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", NEONvshru,
3695 // VSHLL : Vector Shift Left Long
3696 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
3697 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
3699 // VSHLL : Vector Shift Left Long (with maximum shift count)
3700 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
3701 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
3702 ValueType OpTy, SDNode OpNode>
3703 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
3704 ResTy, OpTy, OpNode> {
3705 let Inst{21-16} = op21_16;
3707 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
3708 v8i16, v8i8, NEONvshlli>;
3709 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
3710 v4i32, v4i16, NEONvshlli>;
3711 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
3712 v2i64, v2i32, NEONvshlli>;
3714 // VSHRN : Vector Shift Right and Narrow
3715 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
3718 // VRSHL : Vector Rounding Shift
3719 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
3720 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3721 "vrshl", "s", int_arm_neon_vrshifts>;
3722 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
3723 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3724 "vrshl", "u", int_arm_neon_vrshiftu>;
3725 // VRSHR : Vector Rounding Shift Right
3726 defm VRSHRs : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs,
3728 defm VRSHRu : N2VSh_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", NEONvrshru,
3731 // VRSHRN : Vector Rounding Shift Right and Narrow
3732 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
3735 // VQSHL : Vector Saturating Shift
3736 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
3737 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3738 "vqshl", "s", int_arm_neon_vqshifts>;
3739 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
3740 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3741 "vqshl", "u", int_arm_neon_vqshiftu>;
3742 // VQSHL : Vector Saturating Shift Left (Immediate)
3743 defm VQSHLsi : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls,
3745 defm VQSHLui : N2VSh_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu,
3747 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
3748 defm VQSHLsu : N2VSh_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu,
3751 // VQSHRN : Vector Saturating Shift Right and Narrow
3752 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
3754 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
3757 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
3758 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
3761 // VQRSHL : Vector Saturating Rounding Shift
3762 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
3763 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3764 "vqrshl", "s", int_arm_neon_vqrshifts>;
3765 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
3766 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3767 "vqrshl", "u", int_arm_neon_vqrshiftu>;
3769 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
3770 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
3772 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
3775 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
3776 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
3779 // VSRA : Vector Shift Right and Accumulate
3780 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
3781 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
3782 // VRSRA : Vector Rounding Shift Right and Accumulate
3783 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
3784 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
3786 // VSLI : Vector Shift Left and Insert
3787 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli", NEONvsli, N2RegVShLFrm>;
3788 // VSRI : Vector Shift Right and Insert
3789 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri", NEONvsri, N2RegVShRFrm>;
3791 // Vector Absolute and Saturating Absolute.
3793 // VABS : Vector Absolute Value
3794 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
3795 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
3797 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
3798 IIC_VUNAD, "vabs", "f32",
3799 v2f32, v2f32, int_arm_neon_vabs>;
3800 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
3801 IIC_VUNAQ, "vabs", "f32",
3802 v4f32, v4f32, int_arm_neon_vabs>;
3804 // VQABS : Vector Saturating Absolute Value
3805 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
3806 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
3807 int_arm_neon_vqabs>;
3811 def vnegd : PatFrag<(ops node:$in),
3812 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
3813 def vnegq : PatFrag<(ops node:$in),
3814 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
3816 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
3817 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
3818 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
3819 [(set DPR:$dst, (Ty (vnegd DPR:$src)))]>;
3820 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
3821 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
3822 IIC_VSHLiQ, OpcodeStr, Dt, "$dst, $src", "",
3823 [(set QPR:$dst, (Ty (vnegq QPR:$src)))]>;
3825 // VNEG : Vector Negate (integer)
3826 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
3827 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
3828 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
3829 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
3830 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
3831 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
3833 // VNEG : Vector Negate (floating-point)
3834 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
3835 (outs DPR:$dst), (ins DPR:$src), IIC_VUNAD,
3836 "vneg", "f32", "$dst, $src", "",
3837 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
3838 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
3839 (outs QPR:$dst), (ins QPR:$src), IIC_VUNAQ,
3840 "vneg", "f32", "$dst, $src", "",
3841 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
3843 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
3844 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
3845 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
3846 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
3847 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
3848 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
3850 // VQNEG : Vector Saturating Negate
3851 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
3852 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
3853 int_arm_neon_vqneg>;
3855 // Vector Bit Counting Operations.
3857 // VCLS : Vector Count Leading Sign Bits
3858 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
3859 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
3861 // VCLZ : Vector Count Leading Zeros
3862 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
3863 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
3865 // VCNT : Vector Count One Bits
3866 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
3867 IIC_VCNTiD, "vcnt", "8",
3868 v8i8, v8i8, int_arm_neon_vcnt>;
3869 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
3870 IIC_VCNTiQ, "vcnt", "8",
3871 v16i8, v16i8, int_arm_neon_vcnt>;
3873 // Vector Swap -- for disassembly only.
3874 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
3875 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
3876 "vswp", "$dst, $src", "", []>;
3877 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
3878 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
3879 "vswp", "$dst, $src", "", []>;
3881 // Vector Move Operations.
3883 // VMOV : Vector Move (Register)
3885 let neverHasSideEffects = 1 in {
3886 def VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$Vd), (ins DPR:$Vm),
3887 N3RegFrm, IIC_VMOV, "vmov", "$Vd, $Vm", "", []> {
3888 let Vn{4-0} = Vm{4-0};
3890 def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$Vd), (ins QPR:$Vm),
3891 N3RegFrm, IIC_VMOV, "vmov", "$Vd, $Vm", "", []> {
3892 let Vn{4-0} = Vm{4-0};
3895 // Pseudo vector move instructions for QQ and QQQQ registers. This should
3896 // be expanded after register allocation is completed.
3897 def VMOVQQ : PseudoInst<(outs QQPR:$dst), (ins QQPR:$src),
3900 def VMOVQQQQ : PseudoInst<(outs QQQQPR:$dst), (ins QQQQPR:$src),
3902 } // neverHasSideEffects
3904 // VMOV : Vector Move (Immediate)
3906 let isReMaterializable = 1 in {
3907 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
3908 (ins nModImm:$SIMM), IIC_VMOVImm,
3909 "vmov", "i8", "$dst, $SIMM", "",
3910 [(set DPR:$dst, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
3911 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
3912 (ins nModImm:$SIMM), IIC_VMOVImm,
3913 "vmov", "i8", "$dst, $SIMM", "",
3914 [(set QPR:$dst, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
3916 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$dst),
3917 (ins nModImm:$SIMM), IIC_VMOVImm,
3918 "vmov", "i16", "$dst, $SIMM", "",
3919 [(set DPR:$dst, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
3920 let Inst{9} = SIMM{9};
3923 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$dst),
3924 (ins nModImm:$SIMM), IIC_VMOVImm,
3925 "vmov", "i16", "$dst, $SIMM", "",
3926 [(set QPR:$dst, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
3927 let Inst{9} = SIMM{9};
3930 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$dst),
3931 (ins nModImm:$SIMM), IIC_VMOVImm,
3932 "vmov", "i32", "$dst, $SIMM", "",
3933 [(set DPR:$dst, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
3934 let Inst{11-8} = SIMM{11-8};
3937 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$dst),
3938 (ins nModImm:$SIMM), IIC_VMOVImm,
3939 "vmov", "i32", "$dst, $SIMM", "",
3940 [(set QPR:$dst, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
3941 let Inst{11-8} = SIMM{11-8};
3944 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
3945 (ins nModImm:$SIMM), IIC_VMOVImm,
3946 "vmov", "i64", "$dst, $SIMM", "",
3947 [(set DPR:$dst, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
3948 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
3949 (ins nModImm:$SIMM), IIC_VMOVImm,
3950 "vmov", "i64", "$dst, $SIMM", "",
3951 [(set QPR:$dst, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
3952 } // isReMaterializable
3954 // VMOV : Vector Get Lane (move scalar to ARM core register)
3956 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
3957 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
3958 IIC_VMOVSI, "vmov", "s8", "$R, $V[$lane]",
3959 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
3961 let Inst{21} = lane{2};
3962 let Inst{6-5} = lane{1-0};
3964 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
3965 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
3966 IIC_VMOVSI, "vmov", "s16", "$R, $V[$lane]",
3967 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
3969 let Inst{21} = lane{1};
3970 let Inst{6} = lane{0};
3972 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
3973 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
3974 IIC_VMOVSI, "vmov", "u8", "$R, $V[$lane]",
3975 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
3977 let Inst{21} = lane{2};
3978 let Inst{6-5} = lane{1-0};
3980 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
3981 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
3982 IIC_VMOVSI, "vmov", "u16", "$R, $V[$lane]",
3983 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
3985 let Inst{21} = lane{1};
3986 let Inst{6} = lane{0};
3988 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
3989 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
3990 IIC_VMOVSI, "vmov", "32", "$R, $V[$lane]",
3991 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
3993 let Inst{21} = lane{0};
3995 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
3996 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
3997 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
3998 (DSubReg_i8_reg imm:$lane))),
3999 (SubReg_i8_lane imm:$lane))>;
4000 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
4001 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4002 (DSubReg_i16_reg imm:$lane))),
4003 (SubReg_i16_lane imm:$lane))>;
4004 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
4005 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4006 (DSubReg_i8_reg imm:$lane))),
4007 (SubReg_i8_lane imm:$lane))>;
4008 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
4009 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4010 (DSubReg_i16_reg imm:$lane))),
4011 (SubReg_i16_lane imm:$lane))>;
4012 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
4013 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
4014 (DSubReg_i32_reg imm:$lane))),
4015 (SubReg_i32_lane imm:$lane))>;
4016 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
4017 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
4018 (SSubReg_f32_reg imm:$src2))>;
4019 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
4020 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
4021 (SSubReg_f32_reg imm:$src2))>;
4022 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
4023 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4024 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
4025 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4028 // VMOV : Vector Set Lane (move ARM core register to scalar)
4030 let Constraints = "$src1 = $V" in {
4031 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
4032 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4033 IIC_VMOVISL, "vmov", "8", "$V[$lane], $R",
4034 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
4035 GPR:$R, imm:$lane))]> {
4036 let Inst{21} = lane{2};
4037 let Inst{6-5} = lane{1-0};
4039 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
4040 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4041 IIC_VMOVISL, "vmov", "16", "$V[$lane], $R",
4042 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
4043 GPR:$R, imm:$lane))]> {
4044 let Inst{21} = lane{1};
4045 let Inst{6} = lane{0};
4047 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
4048 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4049 IIC_VMOVISL, "vmov", "32", "$V[$lane], $R",
4050 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
4051 GPR:$R, imm:$lane))]> {
4052 let Inst{21} = lane{0};
4055 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
4056 (v16i8 (INSERT_SUBREG QPR:$src1,
4057 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
4058 (DSubReg_i8_reg imm:$lane))),
4059 GPR:$src2, (SubReg_i8_lane imm:$lane))),
4060 (DSubReg_i8_reg imm:$lane)))>;
4061 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
4062 (v8i16 (INSERT_SUBREG QPR:$src1,
4063 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
4064 (DSubReg_i16_reg imm:$lane))),
4065 GPR:$src2, (SubReg_i16_lane imm:$lane))),
4066 (DSubReg_i16_reg imm:$lane)))>;
4067 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
4068 (v4i32 (INSERT_SUBREG QPR:$src1,
4069 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
4070 (DSubReg_i32_reg imm:$lane))),
4071 GPR:$src2, (SubReg_i32_lane imm:$lane))),
4072 (DSubReg_i32_reg imm:$lane)))>;
4074 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
4075 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
4076 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4077 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
4078 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
4079 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4081 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4082 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4083 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4084 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4086 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
4087 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4088 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
4089 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
4090 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
4091 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4093 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
4094 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4095 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
4096 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4097 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
4098 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4100 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
4101 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4102 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4104 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
4105 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
4106 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4108 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
4109 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4110 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4113 // VDUP : Vector Duplicate (from ARM core register to all elements)
4115 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4116 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
4117 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
4118 [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
4119 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4120 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
4121 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
4122 [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
4124 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
4125 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
4126 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
4127 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
4128 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
4129 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
4131 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
4132 IIC_VMOVIS, "vdup", "32", "$dst, $src",
4133 [(set DPR:$dst, (v2f32 (NEONvdup
4134 (f32 (bitconvert GPR:$src)))))]>;
4135 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
4136 IIC_VMOVIS, "vdup", "32", "$dst, $src",
4137 [(set QPR:$dst, (v4f32 (NEONvdup
4138 (f32 (bitconvert GPR:$src)))))]>;
4140 // VDUP : Vector Duplicate Lane (from scalar to all elements)
4142 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
4144 : NVDupLane<op19_16, 0, (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane),
4145 IIC_VMOVD, OpcodeStr, Dt, "$dst, $src[$lane]",
4146 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
4148 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
4149 ValueType ResTy, ValueType OpTy>
4150 : NVDupLane<op19_16, 1, (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane),
4151 IIC_VMOVQ, OpcodeStr, Dt, "$dst, $src[$lane]",
4152 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src),
4155 // Inst{19-16} is partially specified depending on the element size.
4157 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8> {
4158 let Inst{19-17} = lane{2-0};
4160 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16> {
4161 let Inst{19-18} = lane{1-0};
4163 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32> {
4164 let Inst{19} = lane{0};
4166 def VDUPLNfd : VDUPLND<{?,1,0,0}, "vdup", "32", v2f32> {
4167 let Inst{19} = lane{0};
4169 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8> {
4170 let Inst{19-17} = lane{2-0};
4172 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16> {
4173 let Inst{19-18} = lane{1-0};
4175 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32> {
4176 let Inst{19} = lane{0};
4178 def VDUPLNfq : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4f32, v2f32> {
4179 let Inst{19} = lane{0};
4182 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
4183 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
4184 (DSubReg_i8_reg imm:$lane))),
4185 (SubReg_i8_lane imm:$lane)))>;
4186 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
4187 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
4188 (DSubReg_i16_reg imm:$lane))),
4189 (SubReg_i16_lane imm:$lane)))>;
4190 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
4191 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
4192 (DSubReg_i32_reg imm:$lane))),
4193 (SubReg_i32_lane imm:$lane)))>;
4194 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
4195 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
4196 (DSubReg_i32_reg imm:$lane))),
4197 (SubReg_i32_lane imm:$lane)))>;
4199 def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4200 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
4201 def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4202 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
4204 // VMOVN : Vector Narrowing Move
4205 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
4206 "vmovn", "i", trunc>;
4207 // VQMOVN : Vector Saturating Narrowing Move
4208 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
4209 "vqmovn", "s", int_arm_neon_vqmovns>;
4210 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
4211 "vqmovn", "u", int_arm_neon_vqmovnu>;
4212 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
4213 "vqmovun", "s", int_arm_neon_vqmovnsu>;
4214 // VMOVL : Vector Lengthening Move
4215 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
4216 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
4218 // Vector Conversions.
4220 // VCVT : Vector Convert Between Floating-Point and Integers
4221 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4222 v2i32, v2f32, fp_to_sint>;
4223 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4224 v2i32, v2f32, fp_to_uint>;
4225 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4226 v2f32, v2i32, sint_to_fp>;
4227 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4228 v2f32, v2i32, uint_to_fp>;
4230 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4231 v4i32, v4f32, fp_to_sint>;
4232 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4233 v4i32, v4f32, fp_to_uint>;
4234 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4235 v4f32, v4i32, sint_to_fp>;
4236 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4237 v4f32, v4i32, uint_to_fp>;
4239 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
4240 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4241 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
4242 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4243 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
4244 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4245 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
4246 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4247 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
4249 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4250 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
4251 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4252 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
4253 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4254 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
4255 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4256 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
4260 // VREV64 : Vector Reverse elements within 64-bit doublewords
4262 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4263 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
4264 (ins DPR:$Vm), IIC_VMOVD,
4265 OpcodeStr, Dt, "$Vd, $Vm", "",
4266 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
4267 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4268 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
4269 (ins QPR:$Vm), IIC_VMOVQ,
4270 OpcodeStr, Dt, "$Vd, $Vm", "",
4271 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
4273 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
4274 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
4275 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
4276 def VREV64df : VREV64D<0b10, "vrev64", "32", v2f32>;
4278 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
4279 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
4280 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
4281 def VREV64qf : VREV64Q<0b10, "vrev64", "32", v4f32>;
4283 // VREV32 : Vector Reverse elements within 32-bit words
4285 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4286 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
4287 (ins DPR:$Vm), IIC_VMOVD,
4288 OpcodeStr, Dt, "$Vd, $Vm", "",
4289 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
4290 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4291 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
4292 (ins QPR:$Vm), IIC_VMOVQ,
4293 OpcodeStr, Dt, "$Vd, $Vm", "",
4294 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
4296 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
4297 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
4299 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
4300 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
4302 // VREV16 : Vector Reverse elements within 16-bit halfwords
4304 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4305 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
4306 (ins DPR:$Vm), IIC_VMOVD,
4307 OpcodeStr, Dt, "$Vd, $Vm", "",
4308 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
4309 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4310 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
4311 (ins QPR:$Vm), IIC_VMOVQ,
4312 OpcodeStr, Dt, "$Vd, $Vm", "",
4313 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
4315 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
4316 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
4318 // Other Vector Shuffles.
4320 // VEXT : Vector Extract
4322 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
4323 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
4324 (ins DPR:$Vn, DPR:$Vm, i32imm:$index), NVExtFrm,
4325 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4326 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
4327 (Ty DPR:$Vm), imm:$index)))]> {
4329 let Inst{11-8} = index{3-0};
4332 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
4333 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
4334 (ins QPR:$Vn, QPR:$Vm, i32imm:$index), NVExtFrm,
4335 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4336 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
4337 (Ty QPR:$Vm), imm:$index)))]> {
4339 let Inst{11-8} = index{3-0};
4342 def VEXTd8 : VEXTd<"vext", "8", v8i8> {
4343 let Inst{11-8} = index{3-0};
4345 def VEXTd16 : VEXTd<"vext", "16", v4i16> {
4346 let Inst{11-9} = index{2-0};
4349 def VEXTd32 : VEXTd<"vext", "32", v2i32> {
4350 let Inst{11-10} = index{1-0};
4351 let Inst{9-8} = 0b00;
4353 def VEXTdf : VEXTd<"vext", "32", v2f32> {
4354 let Inst{11} = index{0};
4355 let Inst{10-8} = 0b000;
4358 def VEXTq8 : VEXTq<"vext", "8", v16i8> {
4359 let Inst{11-8} = index{3-0};
4361 def VEXTq16 : VEXTq<"vext", "16", v8i16> {
4362 let Inst{11-9} = index{2-0};
4365 def VEXTq32 : VEXTq<"vext", "32", v4i32> {
4366 let Inst{11-10} = index{1-0};
4367 let Inst{9-8} = 0b00;
4369 def VEXTqf : VEXTq<"vext", "32", v4f32> {
4370 let Inst{11} = index{0};
4371 let Inst{10-8} = 0b000;
4374 // VTRN : Vector Transpose
4376 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
4377 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
4378 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
4380 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
4381 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
4382 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
4384 // VUZP : Vector Unzip (Deinterleave)
4386 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
4387 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
4388 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
4390 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
4391 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
4392 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
4394 // VZIP : Vector Zip (Interleave)
4396 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
4397 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
4398 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
4400 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
4401 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
4402 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
4404 // Vector Table Lookup and Table Extension.
4406 // VTBL : Vector Table Lookup
4408 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
4409 (ins DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
4410 "vtbl", "8", "$Vd, \\{$Vn\\}, $Vm", "",
4411 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 DPR:$Vn, DPR:$Vm)))]>;
4412 let hasExtraSrcRegAllocReq = 1 in {
4414 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
4415 (ins DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTB2,
4416 "vtbl", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "", []>;
4418 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
4419 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm), NVTBLFrm, IIC_VTB3,
4420 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm", "", []>;
4422 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
4423 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm),
4425 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm", "", []>;
4426 } // hasExtraSrcRegAllocReq = 1
4429 : PseudoNeonI<(outs DPR:$dst), (ins QPR:$tbl, DPR:$src), IIC_VTB2, "", []>;
4431 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
4433 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
4435 // VTBX : Vector Table Extension
4437 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
4438 (ins DPR:$orig, DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
4439 "vtbx", "8", "$Vd, \\{$Vn\\}, $Vm", "$orig = $Vd",
4440 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
4441 DPR:$orig, DPR:$Vn, DPR:$Vm)))]>;
4442 let hasExtraSrcRegAllocReq = 1 in {
4444 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
4445 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
4446 "vtbx", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "$orig = $Vd", []>;
4448 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
4449 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm),
4450 NVTBLFrm, IIC_VTBX3,
4451 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm",
4454 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd), (ins DPR:$orig, DPR:$Vn,
4455 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
4456 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm",
4458 } // hasExtraSrcRegAllocReq = 1
4461 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QPR:$tbl, DPR:$src),
4462 IIC_VTBX2, "$orig = $dst", []>;
4464 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4465 IIC_VTBX3, "$orig = $dst", []>;
4467 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4468 IIC_VTBX4, "$orig = $dst", []>;
4470 //===----------------------------------------------------------------------===//
4471 // NEON instructions for single-precision FP math
4472 //===----------------------------------------------------------------------===//
4474 class N2VSPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
4475 : NEONFPPat<(ResTy (OpNode SPR:$a)),
4476 (EXTRACT_SUBREG (OpTy (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)),
4480 class N3VSPat<SDNode OpNode, NeonI Inst>
4481 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
4482 (EXTRACT_SUBREG (v2f32
4483 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
4485 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
4489 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
4490 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
4491 (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
4493 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
4495 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
4499 // These need separate instructions because they must use DPR_VFP2 register
4500 // class which have SPR sub-registers.
4502 // Vector Add Operations used for single-precision FP
4503 let neverHasSideEffects = 1 in
4504 def VADDfd_sfp : N3VS<0,0,0b00,0b1101,0, "vadd", "f32", v2f32, v2f32, fadd, 1>;
4505 def : N3VSPat<fadd, VADDfd_sfp>;
4507 // Vector Sub Operations used for single-precision FP
4508 let neverHasSideEffects = 1 in
4509 def VSUBfd_sfp : N3VS<0,0,0b10,0b1101,0, "vsub", "f32", v2f32, v2f32, fsub, 0>;
4510 def : N3VSPat<fsub, VSUBfd_sfp>;
4512 // Vector Multiply Operations used for single-precision FP
4513 let neverHasSideEffects = 1 in
4514 def VMULfd_sfp : N3VS<1,0,0b00,0b1101,1, "vmul", "f32", v2f32, v2f32, fmul, 1>;
4515 def : N3VSPat<fmul, VMULfd_sfp>;
4517 // Vector Multiply-Accumulate/Subtract used for single-precision FP
4518 // vml[as].f32 can cause 4-8 cycle stalls in following ASIMD instructions, so
4519 // we want to avoid them for now. e.g., alternating vmla/vadd instructions.
4521 //let neverHasSideEffects = 1 in
4522 //def VMLAfd_sfp : N3VSMulOp<0,0,0b00,0b1101,1, IIC_VMACD, "vmla", "f32",
4523 // v2f32, fmul, fadd>;
4524 //def : N3VSMulOpPat<fmul, fadd, VMLAfd_sfp>;
4526 //let neverHasSideEffects = 1 in
4527 //def VMLSfd_sfp : N3VSMulOp<0,0,0b10,0b1101,1, IIC_VMACD, "vmls", "f32",
4528 // v2f32, fmul, fsub>;
4529 //def : N3VSMulOpPat<fmul, fsub, VMLSfd_sfp>;
4531 // Vector Absolute used for single-precision FP
4532 let neverHasSideEffects = 1 in
4533 def VABSfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01110, 0, 0,
4534 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
4535 "vabs", "f32", "$dst, $src", "", []>;
4536 def : N2VSPat<fabs, f32, v2f32, VABSfd_sfp>;
4538 // Vector Negate used for single-precision FP
4539 let neverHasSideEffects = 1 in
4540 def VNEGfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
4541 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
4542 "vneg", "f32", "$dst, $src", "", []>;
4543 def : N2VSPat<fneg, f32, v2f32, VNEGfd_sfp>;
4545 // Vector Maximum used for single-precision FP
4546 let neverHasSideEffects = 1 in
4547 def VMAXfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
4548 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm, IIC_VBIND,
4549 "vmax", "f32", "$dst, $src1, $src2", "", []>;
4550 def : N3VSPat<NEONfmax, VMAXfd_sfp>;
4552 // Vector Minimum used for single-precision FP
4553 let neverHasSideEffects = 1 in
4554 def VMINfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
4555 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm, IIC_VBIND,
4556 "vmin", "f32", "$dst, $src1, $src2", "", []>;
4557 def : N3VSPat<NEONfmin, VMINfd_sfp>;
4559 // Vector Convert between single-precision FP and integer
4560 let neverHasSideEffects = 1 in
4561 def VCVTf2sd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4562 v2i32, v2f32, fp_to_sint>;
4563 def : N2VSPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
4565 let neverHasSideEffects = 1 in
4566 def VCVTf2ud_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4567 v2i32, v2f32, fp_to_uint>;
4568 def : N2VSPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
4570 let neverHasSideEffects = 1 in
4571 def VCVTs2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4572 v2f32, v2i32, sint_to_fp>;
4573 def : N2VSPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
4575 let neverHasSideEffects = 1 in
4576 def VCVTu2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4577 v2f32, v2i32, uint_to_fp>;
4578 def : N2VSPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
4580 //===----------------------------------------------------------------------===//
4581 // Non-Instruction Patterns
4582 //===----------------------------------------------------------------------===//
4585 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
4586 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
4587 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
4588 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
4589 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
4590 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
4591 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
4592 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
4593 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
4594 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
4595 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
4596 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
4597 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
4598 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
4599 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
4600 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
4601 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
4602 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
4603 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
4604 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
4605 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
4606 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
4607 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
4608 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
4609 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
4610 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
4611 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
4612 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
4613 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
4614 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
4616 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
4617 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
4618 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
4619 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
4620 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
4621 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
4622 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
4623 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
4624 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
4625 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
4626 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
4627 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
4628 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
4629 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
4630 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
4631 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
4632 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
4633 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
4634 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
4635 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
4636 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
4637 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
4638 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
4639 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
4640 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
4641 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
4642 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
4643 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
4644 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
4645 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;