1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
19 def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
21 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
22 def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
23 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
24 def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
25 def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
26 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
27 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
28 def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
29 def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
30 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
31 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
33 // Types for vector shift by immediates. The "SHX" version is for long and
34 // narrow operations where the source and destination vectors have different
35 // types. The "SHINS" version is for shift and insert operations.
36 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
38 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
40 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
43 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
44 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
45 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
46 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
47 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
48 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
49 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
51 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
52 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
53 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
55 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
56 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
57 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
58 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
59 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
60 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
62 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
63 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
64 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
66 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
67 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
69 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
71 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
72 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
74 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
75 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
76 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
78 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
80 def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
81 def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
83 def NEONvbsl : SDNode<"ARMISD::VBSL",
84 SDTypeProfile<1, 3, [SDTCisVec<0>,
87 SDTCisSameAs<0, 3>]>>;
89 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
91 // VDUPLANE can produce a quad-register result from a double-register source,
92 // so the result is not constrained to match the source.
93 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
94 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
97 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
98 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
99 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
101 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
102 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
103 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
104 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
106 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
108 SDTCisSameAs<0, 3>]>;
109 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
110 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
111 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
113 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
114 SDTCisSameAs<1, 2>]>;
115 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
116 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
118 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
119 SDTCisSameAs<0, 2>]>;
120 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
121 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
123 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
124 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
125 unsigned EltBits = 0;
126 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
127 return (EltBits == 32 && EltVal == 0);
130 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
131 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
132 unsigned EltBits = 0;
133 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
134 return (EltBits == 8 && EltVal == 0xff);
137 //===----------------------------------------------------------------------===//
138 // NEON operand definitions
139 //===----------------------------------------------------------------------===//
141 def nModImm : Operand<i32> {
142 let PrintMethod = "printNEONModImmOperand";
145 //===----------------------------------------------------------------------===//
146 // NEON load / store instructions
147 //===----------------------------------------------------------------------===//
149 // Use VLDM to load a Q register as a D register pair.
150 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
152 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
154 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
156 // Use VSTM to store a Q register as a D register pair.
157 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
159 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
161 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
163 // Classes for VLD* pseudo-instructions with multi-register operands.
164 // These are expanded to real instructions after register allocation.
165 class VLDQPseudo<InstrItinClass itin>
166 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
167 class VLDQWBPseudo<InstrItinClass itin>
168 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
169 (ins addrmode6:$addr, am6offset:$offset), itin,
171 class VLDQQPseudo<InstrItinClass itin>
172 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
173 class VLDQQWBPseudo<InstrItinClass itin>
174 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
175 (ins addrmode6:$addr, am6offset:$offset), itin,
177 class VLDQQQQPseudo<InstrItinClass itin>
178 : PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src),itin,
180 class VLDQQQQWBPseudo<InstrItinClass itin>
181 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
182 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
183 "$addr.addr = $wb, $src = $dst">;
185 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
187 // VLD1 : Vector Load (multiple single elements)
188 class VLD1D<bits<4> op7_4, string Dt>
189 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd),
190 (ins addrmode6:$Rn), IIC_VLD1,
191 "vld1", Dt, "\\{$Vd\\}, $Rn", "", []> {
194 let DecoderMethod = "DecodeVLDInstruction";
196 class VLD1Q<bits<4> op7_4, string Dt>
197 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2),
198 (ins addrmode6:$Rn), IIC_VLD1x2,
199 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
201 let Inst{5-4} = Rn{5-4};
202 let DecoderMethod = "DecodeVLDInstruction";
205 def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
206 def VLD1d16 : VLD1D<{0,1,0,?}, "16">;
207 def VLD1d32 : VLD1D<{1,0,0,?}, "32">;
208 def VLD1d64 : VLD1D<{1,1,0,?}, "64">;
210 def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;
211 def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
212 def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
213 def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
215 def VLD1q8Pseudo : VLDQPseudo<IIC_VLD1x2>;
216 def VLD1q16Pseudo : VLDQPseudo<IIC_VLD1x2>;
217 def VLD1q32Pseudo : VLDQPseudo<IIC_VLD1x2>;
218 def VLD1q64Pseudo : VLDQPseudo<IIC_VLD1x2>;
220 // ...with address register writeback:
221 class VLD1DWB<bits<4> op7_4, string Dt>
222 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd, GPR:$wb),
223 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1u,
224 "vld1", Dt, "\\{$Vd\\}, $Rn$Rm",
225 "$Rn.addr = $wb", []> {
227 let DecoderMethod = "DecodeVLDInstruction";
229 class VLD1QWB<bits<4> op7_4, string Dt>
230 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
231 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x2u,
232 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
233 "$Rn.addr = $wb", []> {
234 let Inst{5-4} = Rn{5-4};
235 let DecoderMethod = "DecodeVLDInstruction";
238 def VLD1d8_UPD : VLD1DWB<{0,0,0,?}, "8">;
239 def VLD1d16_UPD : VLD1DWB<{0,1,0,?}, "16">;
240 def VLD1d32_UPD : VLD1DWB<{1,0,0,?}, "32">;
241 def VLD1d64_UPD : VLD1DWB<{1,1,0,?}, "64">;
243 def VLD1q8_UPD : VLD1QWB<{0,0,?,?}, "8">;
244 def VLD1q16_UPD : VLD1QWB<{0,1,?,?}, "16">;
245 def VLD1q32_UPD : VLD1QWB<{1,0,?,?}, "32">;
246 def VLD1q64_UPD : VLD1QWB<{1,1,?,?}, "64">;
248 def VLD1q8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
249 def VLD1q16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
250 def VLD1q32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
251 def VLD1q64Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
253 // ...with 3 registers (some of these are only for the disassembler):
254 class VLD1D3<bits<4> op7_4, string Dt>
255 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
256 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
257 "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
260 let DecoderMethod = "DecodeVLDInstruction";
262 class VLD1D3WB<bits<4> op7_4, string Dt>
263 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
264 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x3u, "vld1", Dt,
265 "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
267 let DecoderMethod = "DecodeVLDInstruction";
270 def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
271 def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;
272 def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;
273 def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;
275 def VLD1d8T_UPD : VLD1D3WB<{0,0,0,?}, "8">;
276 def VLD1d16T_UPD : VLD1D3WB<{0,1,0,?}, "16">;
277 def VLD1d32T_UPD : VLD1D3WB<{1,0,0,?}, "32">;
278 def VLD1d64T_UPD : VLD1D3WB<{1,1,0,?}, "64">;
280 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
281 def VLD1d64TPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x3u>;
283 // ...with 4 registers (some of these are only for the disassembler):
284 class VLD1D4<bits<4> op7_4, string Dt>
285 : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
286 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
287 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
289 let Inst{5-4} = Rn{5-4};
290 let DecoderMethod = "DecodeVLDInstruction";
292 class VLD1D4WB<bits<4> op7_4, string Dt>
293 : NLdSt<0,0b10,0b0010,op7_4,
294 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
295 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x4u, "vld1", Dt,
296 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", "$Rn.addr = $wb",
298 let Inst{5-4} = Rn{5-4};
299 let DecoderMethod = "DecodeVLDInstruction";
302 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
303 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;
304 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;
305 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;
307 def VLD1d8Q_UPD : VLD1D4WB<{0,0,?,?}, "8">;
308 def VLD1d16Q_UPD : VLD1D4WB<{0,1,?,?}, "16">;
309 def VLD1d32Q_UPD : VLD1D4WB<{1,0,?,?}, "32">;
310 def VLD1d64Q_UPD : VLD1D4WB<{1,1,?,?}, "64">;
312 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
313 def VLD1d64QPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x4u>;
315 // VLD2 : Vector Load (multiple 2-element structures)
316 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
317 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
318 (ins addrmode6:$Rn), IIC_VLD2,
319 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
321 let Inst{5-4} = Rn{5-4};
322 let DecoderMethod = "DecodeVLDInstruction";
324 class VLD2Q<bits<4> op7_4, string Dt>
325 : NLdSt<0, 0b10, 0b0011, op7_4,
326 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
327 (ins addrmode6:$Rn), IIC_VLD2x2,
328 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
330 let Inst{5-4} = Rn{5-4};
331 let DecoderMethod = "DecodeVLDInstruction";
334 def VLD2d8 : VLD2D<0b1000, {0,0,?,?}, "8">;
335 def VLD2d16 : VLD2D<0b1000, {0,1,?,?}, "16">;
336 def VLD2d32 : VLD2D<0b1000, {1,0,?,?}, "32">;
338 def VLD2q8 : VLD2Q<{0,0,?,?}, "8">;
339 def VLD2q16 : VLD2Q<{0,1,?,?}, "16">;
340 def VLD2q32 : VLD2Q<{1,0,?,?}, "32">;
342 def VLD2d8Pseudo : VLDQPseudo<IIC_VLD2>;
343 def VLD2d16Pseudo : VLDQPseudo<IIC_VLD2>;
344 def VLD2d32Pseudo : VLDQPseudo<IIC_VLD2>;
346 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
347 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
348 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
350 // ...with address register writeback:
351 class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
352 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
353 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2u,
354 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
355 "$Rn.addr = $wb", []> {
356 let Inst{5-4} = Rn{5-4};
357 let DecoderMethod = "DecodeVLDInstruction";
359 class VLD2QWB<bits<4> op7_4, string Dt>
360 : NLdSt<0, 0b10, 0b0011, op7_4,
361 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
362 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2x2u,
363 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
364 "$Rn.addr = $wb", []> {
365 let Inst{5-4} = Rn{5-4};
366 let DecoderMethod = "DecodeVLDInstruction";
369 def VLD2d8_UPD : VLD2DWB<0b1000, {0,0,?,?}, "8">;
370 def VLD2d16_UPD : VLD2DWB<0b1000, {0,1,?,?}, "16">;
371 def VLD2d32_UPD : VLD2DWB<0b1000, {1,0,?,?}, "32">;
373 def VLD2q8_UPD : VLD2QWB<{0,0,?,?}, "8">;
374 def VLD2q16_UPD : VLD2QWB<{0,1,?,?}, "16">;
375 def VLD2q32_UPD : VLD2QWB<{1,0,?,?}, "32">;
377 def VLD2d8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
378 def VLD2d16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
379 def VLD2d32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
381 def VLD2q8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
382 def VLD2q16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
383 def VLD2q32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
385 // ...with double-spaced registers (for disassembly only):
386 def VLD2b8 : VLD2D<0b1001, {0,0,?,?}, "8">;
387 def VLD2b16 : VLD2D<0b1001, {0,1,?,?}, "16">;
388 def VLD2b32 : VLD2D<0b1001, {1,0,?,?}, "32">;
389 def VLD2b8_UPD : VLD2DWB<0b1001, {0,0,?,?}, "8">;
390 def VLD2b16_UPD : VLD2DWB<0b1001, {0,1,?,?}, "16">;
391 def VLD2b32_UPD : VLD2DWB<0b1001, {1,0,?,?}, "32">;
393 // VLD3 : Vector Load (multiple 3-element structures)
394 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
395 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
396 (ins addrmode6:$Rn), IIC_VLD3,
397 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
400 let DecoderMethod = "DecodeVLDInstruction";
403 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
404 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
405 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
407 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
408 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
409 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
411 // ...with address register writeback:
412 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
413 : NLdSt<0, 0b10, op11_8, op7_4,
414 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
415 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
416 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
417 "$Rn.addr = $wb", []> {
419 let DecoderMethod = "DecodeVLDInstruction";
422 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
423 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
424 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
426 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
427 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
428 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
430 // ...with double-spaced registers:
431 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
432 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
433 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
434 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
435 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
436 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
438 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
439 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
440 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
442 // ...alternate versions to be allocated odd register numbers:
443 def VLD3q8oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
444 def VLD3q16oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
445 def VLD3q32oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
447 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
448 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
449 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
451 // VLD4 : Vector Load (multiple 4-element structures)
452 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
453 : NLdSt<0, 0b10, op11_8, op7_4,
454 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
455 (ins addrmode6:$Rn), IIC_VLD4,
456 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
458 let Inst{5-4} = Rn{5-4};
459 let DecoderMethod = "DecodeVLDInstruction";
462 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
463 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
464 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
466 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
467 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
468 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
470 // ...with address register writeback:
471 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
472 : NLdSt<0, 0b10, op11_8, op7_4,
473 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
474 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u,
475 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
476 "$Rn.addr = $wb", []> {
477 let Inst{5-4} = Rn{5-4};
478 let DecoderMethod = "DecodeVLDInstruction";
481 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
482 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
483 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
485 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
486 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
487 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
489 // ...with double-spaced registers:
490 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
491 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
492 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
493 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
494 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
495 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
497 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
498 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
499 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
501 // ...alternate versions to be allocated odd register numbers:
502 def VLD4q8oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
503 def VLD4q16oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
504 def VLD4q32oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
506 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
507 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
508 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
510 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
512 // Classes for VLD*LN pseudo-instructions with multi-register operands.
513 // These are expanded to real instructions after register allocation.
514 class VLDQLNPseudo<InstrItinClass itin>
515 : PseudoNLdSt<(outs QPR:$dst),
516 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
517 itin, "$src = $dst">;
518 class VLDQLNWBPseudo<InstrItinClass itin>
519 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
520 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
521 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
522 class VLDQQLNPseudo<InstrItinClass itin>
523 : PseudoNLdSt<(outs QQPR:$dst),
524 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
525 itin, "$src = $dst">;
526 class VLDQQLNWBPseudo<InstrItinClass itin>
527 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
528 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
529 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
530 class VLDQQQQLNPseudo<InstrItinClass itin>
531 : PseudoNLdSt<(outs QQQQPR:$dst),
532 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
533 itin, "$src = $dst">;
534 class VLDQQQQLNWBPseudo<InstrItinClass itin>
535 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
536 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
537 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
539 // VLD1LN : Vector Load (single element to one lane)
540 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
542 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
543 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
544 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
546 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
547 (i32 (LoadOp addrmode6:$Rn)),
550 let DecoderMethod = "DecodeVLD1LN";
552 class VLD1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
554 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
555 (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane),
556 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
558 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
559 (i32 (LoadOp addrmode6oneL32:$Rn)),
562 let DecoderMethod = "DecodeVLD1LN";
564 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
565 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
566 (i32 (LoadOp addrmode6:$addr)),
570 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
571 let Inst{7-5} = lane{2-0};
573 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
574 let Inst{7-6} = lane{1-0};
577 def VLD1LNd32 : VLD1LN32<0b1000, {?,0,?,?}, "32", v2i32, load> {
578 let Inst{7} = lane{0};
583 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
584 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
585 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
587 def : Pat<(vector_insert (v2f32 DPR:$src),
588 (f32 (load addrmode6:$addr)), imm:$lane),
589 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
590 def : Pat<(vector_insert (v4f32 QPR:$src),
591 (f32 (load addrmode6:$addr)), imm:$lane),
592 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
594 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
596 // ...with address register writeback:
597 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
598 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
599 (ins addrmode6:$Rn, am6offset:$Rm,
600 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
601 "\\{$Vd[$lane]\\}, $Rn$Rm",
602 "$src = $Vd, $Rn.addr = $wb", []> {
603 let DecoderMethod = "DecodeVLD1LN";
606 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
607 let Inst{7-5} = lane{2-0};
609 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
610 let Inst{7-6} = lane{1-0};
613 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
614 let Inst{7} = lane{0};
619 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
620 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
621 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
623 // VLD2LN : Vector Load (single 2-element structure to one lane)
624 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
625 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
626 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
627 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
628 "$src1 = $Vd, $src2 = $dst2", []> {
631 let DecoderMethod = "DecodeVLD2LN";
634 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
635 let Inst{7-5} = lane{2-0};
637 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
638 let Inst{7-6} = lane{1-0};
640 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
641 let Inst{7} = lane{0};
644 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
645 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
646 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
648 // ...with double-spaced registers:
649 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
650 let Inst{7-6} = lane{1-0};
652 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
653 let Inst{7} = lane{0};
656 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
657 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
659 // ...with address register writeback:
660 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
661 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
662 (ins addrmode6:$Rn, am6offset:$Rm,
663 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
664 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
665 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
667 let DecoderMethod = "DecodeVLD2LN";
670 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
671 let Inst{7-5} = lane{2-0};
673 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
674 let Inst{7-6} = lane{1-0};
676 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
677 let Inst{7} = lane{0};
680 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
681 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
682 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
684 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
685 let Inst{7-6} = lane{1-0};
687 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
688 let Inst{7} = lane{0};
691 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
692 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
694 // VLD3LN : Vector Load (single 3-element structure to one lane)
695 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
696 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
697 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
698 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
699 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
700 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
702 let DecoderMethod = "DecodeVLD3LN";
705 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
706 let Inst{7-5} = lane{2-0};
708 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
709 let Inst{7-6} = lane{1-0};
711 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
712 let Inst{7} = lane{0};
715 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
716 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
717 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
719 // ...with double-spaced registers:
720 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
721 let Inst{7-6} = lane{1-0};
723 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
724 let Inst{7} = lane{0};
727 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
728 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
730 // ...with address register writeback:
731 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
732 : NLdStLn<1, 0b10, op11_8, op7_4,
733 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
734 (ins addrmode6:$Rn, am6offset:$Rm,
735 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
736 IIC_VLD3lnu, "vld3", Dt,
737 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
738 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
740 let DecoderMethod = "DecodeVLD3LN";
743 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
744 let Inst{7-5} = lane{2-0};
746 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
747 let Inst{7-6} = lane{1-0};
749 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
750 let Inst{7} = lane{0};
753 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
754 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
755 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
757 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
758 let Inst{7-6} = lane{1-0};
760 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
761 let Inst{7} = lane{0};
764 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
765 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
767 // VLD4LN : Vector Load (single 4-element structure to one lane)
768 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
769 : NLdStLn<1, 0b10, op11_8, op7_4,
770 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
771 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
772 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
773 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
774 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
777 let DecoderMethod = "DecodeVLD4LN";
780 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
781 let Inst{7-5} = lane{2-0};
783 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
784 let Inst{7-6} = lane{1-0};
786 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
787 let Inst{7} = lane{0};
791 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
792 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
793 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
795 // ...with double-spaced registers:
796 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
797 let Inst{7-6} = lane{1-0};
799 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
800 let Inst{7} = lane{0};
804 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
805 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
807 // ...with address register writeback:
808 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
809 : NLdStLn<1, 0b10, op11_8, op7_4,
810 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
811 (ins addrmode6:$Rn, am6offset:$Rm,
812 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
813 IIC_VLD4lnu, "vld4", Dt,
814 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
815 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
818 let DecoderMethod = "DecodeVLD4LN" ;
821 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
822 let Inst{7-5} = lane{2-0};
824 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
825 let Inst{7-6} = lane{1-0};
827 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
828 let Inst{7} = lane{0};
832 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
833 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
834 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
836 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
837 let Inst{7-6} = lane{1-0};
839 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
840 let Inst{7} = lane{0};
844 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
845 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
847 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
849 // VLD1DUP : Vector Load (single element to all lanes)
850 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
851 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd), (ins addrmode6dup:$Rn),
852 IIC_VLD1dup, "vld1", Dt, "\\{$Vd[]\\}, $Rn", "",
853 [(set DPR:$Vd, (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
856 let DecoderMethod = "DecodeVLD1DupInstruction";
858 class VLD1QDUPPseudo<ValueType Ty, PatFrag LoadOp> : VLDQPseudo<IIC_VLD1dup> {
859 let Pattern = [(set QPR:$dst,
860 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$addr)))))];
863 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
864 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;
865 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;
867 def VLD1DUPq8Pseudo : VLD1QDUPPseudo<v16i8, extloadi8>;
868 def VLD1DUPq16Pseudo : VLD1QDUPPseudo<v8i16, extloadi16>;
869 def VLD1DUPq32Pseudo : VLD1QDUPPseudo<v4i32, load>;
871 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
872 (VLD1DUPd32 addrmode6:$addr)>;
873 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
874 (VLD1DUPq32Pseudo addrmode6:$addr)>;
876 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
878 class VLD1QDUP<bits<4> op7_4, string Dt>
879 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2),
880 (ins addrmode6dup:$Rn), IIC_VLD1dup,
881 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
884 let DecoderMethod = "DecodeVLD1DupInstruction";
887 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8">;
888 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16">;
889 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32">;
891 // ...with address register writeback:
892 class VLD1DUPWB<bits<4> op7_4, string Dt>
893 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, GPR:$wb),
894 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
895 "vld1", Dt, "\\{$Vd[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
897 let DecoderMethod = "DecodeVLD1DupInstruction";
899 class VLD1QDUPWB<bits<4> op7_4, string Dt>
900 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
901 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
902 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
904 let DecoderMethod = "DecodeVLD1DupInstruction";
907 def VLD1DUPd8_UPD : VLD1DUPWB<{0,0,0,0}, "8">;
908 def VLD1DUPd16_UPD : VLD1DUPWB<{0,1,0,?}, "16">;
909 def VLD1DUPd32_UPD : VLD1DUPWB<{1,0,0,?}, "32">;
911 def VLD1DUPq8_UPD : VLD1QDUPWB<{0,0,1,0}, "8">;
912 def VLD1DUPq16_UPD : VLD1QDUPWB<{0,1,1,?}, "16">;
913 def VLD1DUPq32_UPD : VLD1QDUPWB<{1,0,1,?}, "32">;
915 def VLD1DUPq8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
916 def VLD1DUPq16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
917 def VLD1DUPq32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
919 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
920 class VLD2DUP<bits<4> op7_4, string Dt>
921 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2),
922 (ins addrmode6dup:$Rn), IIC_VLD2dup,
923 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
926 let DecoderMethod = "DecodeVLD2DupInstruction";
929 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8">;
930 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16">;
931 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32">;
933 def VLD2DUPd8Pseudo : VLDQPseudo<IIC_VLD2dup>;
934 def VLD2DUPd16Pseudo : VLDQPseudo<IIC_VLD2dup>;
935 def VLD2DUPd32Pseudo : VLDQPseudo<IIC_VLD2dup>;
937 // ...with double-spaced registers (not used for codegen):
938 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8">;
939 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16">;
940 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32">;
942 // ...with address register writeback:
943 class VLD2DUPWB<bits<4> op7_4, string Dt>
944 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
945 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD2dupu,
946 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
948 let DecoderMethod = "DecodeVLD2DupInstruction";
951 def VLD2DUPd8_UPD : VLD2DUPWB<{0,0,0,0}, "8">;
952 def VLD2DUPd16_UPD : VLD2DUPWB<{0,1,0,?}, "16">;
953 def VLD2DUPd32_UPD : VLD2DUPWB<{1,0,0,?}, "32">;
955 def VLD2DUPd8x2_UPD : VLD2DUPWB<{0,0,1,0}, "8">;
956 def VLD2DUPd16x2_UPD : VLD2DUPWB<{0,1,1,?}, "16">;
957 def VLD2DUPd32x2_UPD : VLD2DUPWB<{1,0,1,?}, "32">;
959 def VLD2DUPd8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
960 def VLD2DUPd16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
961 def VLD2DUPd32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
963 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
964 class VLD3DUP<bits<4> op7_4, string Dt>
965 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
966 (ins addrmode6dup:$Rn), IIC_VLD3dup,
967 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
970 let DecoderMethod = "DecodeVLD3DupInstruction";
973 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
974 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
975 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
977 def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>;
978 def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
979 def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
981 // ...with double-spaced registers (not used for codegen):
982 def VLD3DUPd8x2 : VLD3DUP<{0,0,1,?}, "8">;
983 def VLD3DUPd16x2 : VLD3DUP<{0,1,1,?}, "16">;
984 def VLD3DUPd32x2 : VLD3DUP<{1,0,1,?}, "32">;
986 // ...with address register writeback:
987 class VLD3DUPWB<bits<4> op7_4, string Dt>
988 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
989 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu,
990 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
991 "$Rn.addr = $wb", []> {
993 let DecoderMethod = "DecodeVLD3DupInstruction";
996 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;
997 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">;
998 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">;
1000 def VLD3DUPd8x2_UPD : VLD3DUPWB<{0,0,1,0}, "8">;
1001 def VLD3DUPd16x2_UPD : VLD3DUPWB<{0,1,1,?}, "16">;
1002 def VLD3DUPd32x2_UPD : VLD3DUPWB<{1,0,1,?}, "32">;
1004 def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1005 def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1006 def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1008 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1009 class VLD4DUP<bits<4> op7_4, string Dt>
1010 : NLdSt<1, 0b10, 0b1111, op7_4,
1011 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1012 (ins addrmode6dup:$Rn), IIC_VLD4dup,
1013 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
1015 let Inst{4} = Rn{4};
1016 let DecoderMethod = "DecodeVLD4DupInstruction";
1019 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1020 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1021 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1023 def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1024 def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1025 def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1027 // ...with double-spaced registers (not used for codegen):
1028 def VLD4DUPd8x2 : VLD4DUP<{0,0,1,?}, "8">;
1029 def VLD4DUPd16x2 : VLD4DUP<{0,1,1,?}, "16">;
1030 def VLD4DUPd32x2 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1032 // ...with address register writeback:
1033 class VLD4DUPWB<bits<4> op7_4, string Dt>
1034 : NLdSt<1, 0b10, 0b1111, op7_4,
1035 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1036 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
1037 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
1038 "$Rn.addr = $wb", []> {
1039 let Inst{4} = Rn{4};
1040 let DecoderMethod = "DecodeVLD4DupInstruction";
1043 def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">;
1044 def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">;
1045 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1047 def VLD4DUPd8x2_UPD : VLD4DUPWB<{0,0,1,0}, "8">;
1048 def VLD4DUPd16x2_UPD : VLD4DUPWB<{0,1,1,?}, "16">;
1049 def VLD4DUPd32x2_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1051 def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1052 def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1053 def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1055 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1057 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1059 // Classes for VST* pseudo-instructions with multi-register operands.
1060 // These are expanded to real instructions after register allocation.
1061 class VSTQPseudo<InstrItinClass itin>
1062 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1063 class VSTQWBPseudo<InstrItinClass itin>
1064 : PseudoNLdSt<(outs GPR:$wb),
1065 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1066 "$addr.addr = $wb">;
1067 class VSTQQPseudo<InstrItinClass itin>
1068 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
1069 class VSTQQWBPseudo<InstrItinClass itin>
1070 : PseudoNLdSt<(outs GPR:$wb),
1071 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
1072 "$addr.addr = $wb">;
1073 class VSTQQQQPseudo<InstrItinClass itin>
1074 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src), itin, "">;
1075 class VSTQQQQWBPseudo<InstrItinClass itin>
1076 : PseudoNLdSt<(outs GPR:$wb),
1077 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
1078 "$addr.addr = $wb">;
1080 // VST1 : Vector Store (multiple single elements)
1081 class VST1D<bits<4> op7_4, string Dt>
1082 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, DPR:$Vd),
1083 IIC_VST1, "vst1", Dt, "\\{$Vd\\}, $Rn", "", []> {
1085 let Inst{4} = Rn{4};
1086 let DecoderMethod = "DecodeVSTInstruction";
1088 class VST1Q<bits<4> op7_4, string Dt>
1089 : NLdSt<0,0b00,0b1010,op7_4, (outs),
1090 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2), IIC_VST1x2,
1091 "vst1", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1093 let Inst{5-4} = Rn{5-4};
1094 let DecoderMethod = "DecodeVSTInstruction";
1097 def VST1d8 : VST1D<{0,0,0,?}, "8">;
1098 def VST1d16 : VST1D<{0,1,0,?}, "16">;
1099 def VST1d32 : VST1D<{1,0,0,?}, "32">;
1100 def VST1d64 : VST1D<{1,1,0,?}, "64">;
1102 def VST1q8 : VST1Q<{0,0,?,?}, "8">;
1103 def VST1q16 : VST1Q<{0,1,?,?}, "16">;
1104 def VST1q32 : VST1Q<{1,0,?,?}, "32">;
1105 def VST1q64 : VST1Q<{1,1,?,?}, "64">;
1107 def VST1q8Pseudo : VSTQPseudo<IIC_VST1x2>;
1108 def VST1q16Pseudo : VSTQPseudo<IIC_VST1x2>;
1109 def VST1q32Pseudo : VSTQPseudo<IIC_VST1x2>;
1110 def VST1q64Pseudo : VSTQPseudo<IIC_VST1x2>;
1112 // ...with address register writeback:
1113 class VST1DWB<bits<4> op7_4, string Dt>
1114 : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
1115 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd), IIC_VST1u,
1116 "vst1", Dt, "\\{$Vd\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
1117 let Inst{4} = Rn{4};
1118 let DecoderMethod = "DecodeVSTInstruction";
1120 class VST1QWB<bits<4> op7_4, string Dt>
1121 : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),
1122 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
1123 IIC_VST1x2u, "vst1", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
1124 "$Rn.addr = $wb", []> {
1125 let Inst{5-4} = Rn{5-4};
1126 let DecoderMethod = "DecodeVSTInstruction";
1129 def VST1d8_UPD : VST1DWB<{0,0,0,?}, "8">;
1130 def VST1d16_UPD : VST1DWB<{0,1,0,?}, "16">;
1131 def VST1d32_UPD : VST1DWB<{1,0,0,?}, "32">;
1132 def VST1d64_UPD : VST1DWB<{1,1,0,?}, "64">;
1134 def VST1q8_UPD : VST1QWB<{0,0,?,?}, "8">;
1135 def VST1q16_UPD : VST1QWB<{0,1,?,?}, "16">;
1136 def VST1q32_UPD : VST1QWB<{1,0,?,?}, "32">;
1137 def VST1q64_UPD : VST1QWB<{1,1,?,?}, "64">;
1139 def VST1q8Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1140 def VST1q16Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1141 def VST1q32Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1142 def VST1q64Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1144 // ...with 3 registers (some of these are only for the disassembler):
1145 class VST1D3<bits<4> op7_4, string Dt>
1146 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1147 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3),
1148 IIC_VST1x3, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1150 let Inst{4} = Rn{4};
1151 let DecoderMethod = "DecodeVSTInstruction";
1153 class VST1D3WB<bits<4> op7_4, string Dt>
1154 : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
1155 (ins addrmode6:$Rn, am6offset:$Rm,
1156 DPR:$Vd, DPR:$src2, DPR:$src3),
1157 IIC_VST1x3u, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1158 "$Rn.addr = $wb", []> {
1159 let Inst{4} = Rn{4};
1160 let DecoderMethod = "DecodeVSTInstruction";
1163 def VST1d8T : VST1D3<{0,0,0,?}, "8">;
1164 def VST1d16T : VST1D3<{0,1,0,?}, "16">;
1165 def VST1d32T : VST1D3<{1,0,0,?}, "32">;
1166 def VST1d64T : VST1D3<{1,1,0,?}, "64">;
1168 def VST1d8T_UPD : VST1D3WB<{0,0,0,?}, "8">;
1169 def VST1d16T_UPD : VST1D3WB<{0,1,0,?}, "16">;
1170 def VST1d32T_UPD : VST1D3WB<{1,0,0,?}, "32">;
1171 def VST1d64T_UPD : VST1D3WB<{1,1,0,?}, "64">;
1173 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
1174 def VST1d64TPseudo_UPD : VSTQQWBPseudo<IIC_VST1x3u>;
1176 // ...with 4 registers (some of these are only for the disassembler):
1177 class VST1D4<bits<4> op7_4, string Dt>
1178 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1179 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1180 IIC_VST1x4, "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", "",
1183 let Inst{5-4} = Rn{5-4};
1184 let DecoderMethod = "DecodeVSTInstruction";
1186 class VST1D4WB<bits<4> op7_4, string Dt>
1187 : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
1188 (ins addrmode6:$Rn, am6offset:$Rm,
1189 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST1x4u,
1190 "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1191 "$Rn.addr = $wb", []> {
1192 let Inst{5-4} = Rn{5-4};
1193 let DecoderMethod = "DecodeVSTInstruction";
1196 def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
1197 def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
1198 def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
1199 def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
1201 def VST1d8Q_UPD : VST1D4WB<{0,0,?,?}, "8">;
1202 def VST1d16Q_UPD : VST1D4WB<{0,1,?,?}, "16">;
1203 def VST1d32Q_UPD : VST1D4WB<{1,0,?,?}, "32">;
1204 def VST1d64Q_UPD : VST1D4WB<{1,1,?,?}, "64">;
1206 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
1207 def VST1d64QPseudo_UPD : VSTQQWBPseudo<IIC_VST1x4u>;
1209 // VST2 : Vector Store (multiple 2-element structures)
1210 class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
1211 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1212 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2),
1213 IIC_VST2, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1215 let Inst{5-4} = Rn{5-4};
1216 let DecoderMethod = "DecodeVSTInstruction";
1218 class VST2Q<bits<4> op7_4, string Dt>
1219 : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
1220 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1221 IIC_VST2x2, "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1224 let Inst{5-4} = Rn{5-4};
1225 let DecoderMethod = "DecodeVSTInstruction";
1228 def VST2d8 : VST2D<0b1000, {0,0,?,?}, "8">;
1229 def VST2d16 : VST2D<0b1000, {0,1,?,?}, "16">;
1230 def VST2d32 : VST2D<0b1000, {1,0,?,?}, "32">;
1232 def VST2q8 : VST2Q<{0,0,?,?}, "8">;
1233 def VST2q16 : VST2Q<{0,1,?,?}, "16">;
1234 def VST2q32 : VST2Q<{1,0,?,?}, "32">;
1236 def VST2d8Pseudo : VSTQPseudo<IIC_VST2>;
1237 def VST2d16Pseudo : VSTQPseudo<IIC_VST2>;
1238 def VST2d32Pseudo : VSTQPseudo<IIC_VST2>;
1240 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
1241 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
1242 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
1244 // ...with address register writeback:
1245 class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1246 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1247 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
1248 IIC_VST2u, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
1249 "$Rn.addr = $wb", []> {
1250 let Inst{5-4} = Rn{5-4};
1251 let DecoderMethod = "DecodeVSTInstruction";
1253 class VST2QWB<bits<4> op7_4, string Dt>
1254 : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1255 (ins addrmode6:$Rn, am6offset:$Rm,
1256 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST2x2u,
1257 "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1258 "$Rn.addr = $wb", []> {
1259 let Inst{5-4} = Rn{5-4};
1260 let DecoderMethod = "DecodeVSTInstruction";
1263 def VST2d8_UPD : VST2DWB<0b1000, {0,0,?,?}, "8">;
1264 def VST2d16_UPD : VST2DWB<0b1000, {0,1,?,?}, "16">;
1265 def VST2d32_UPD : VST2DWB<0b1000, {1,0,?,?}, "32">;
1267 def VST2q8_UPD : VST2QWB<{0,0,?,?}, "8">;
1268 def VST2q16_UPD : VST2QWB<{0,1,?,?}, "16">;
1269 def VST2q32_UPD : VST2QWB<{1,0,?,?}, "32">;
1271 def VST2d8Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1272 def VST2d16Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1273 def VST2d32Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1275 def VST2q8Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1276 def VST2q16Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1277 def VST2q32Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1279 // ...with double-spaced registers (for disassembly only):
1280 def VST2b8 : VST2D<0b1001, {0,0,?,?}, "8">;
1281 def VST2b16 : VST2D<0b1001, {0,1,?,?}, "16">;
1282 def VST2b32 : VST2D<0b1001, {1,0,?,?}, "32">;
1283 def VST2b8_UPD : VST2DWB<0b1001, {0,0,?,?}, "8">;
1284 def VST2b16_UPD : VST2DWB<0b1001, {0,1,?,?}, "16">;
1285 def VST2b32_UPD : VST2DWB<0b1001, {1,0,?,?}, "32">;
1287 // VST3 : Vector Store (multiple 3-element structures)
1288 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1289 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1290 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1291 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1293 let Inst{4} = Rn{4};
1294 let DecoderMethod = "DecodeVSTInstruction";
1297 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1298 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1299 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
1301 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1302 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1303 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
1305 // ...with address register writeback:
1306 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1307 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1308 (ins addrmode6:$Rn, am6offset:$Rm,
1309 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1310 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1311 "$Rn.addr = $wb", []> {
1312 let Inst{4} = Rn{4};
1313 let DecoderMethod = "DecodeVSTInstruction";
1316 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1317 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1318 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
1320 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1321 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1322 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1324 // ...with double-spaced registers:
1325 def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1326 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1327 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1328 def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1329 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1330 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
1332 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1333 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1334 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1336 // ...alternate versions to be allocated odd register numbers:
1337 def VST3q8oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1338 def VST3q16oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1339 def VST3q32oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1341 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1342 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1343 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1345 // VST4 : Vector Store (multiple 4-element structures)
1346 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1347 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1348 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1349 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1352 let Inst{5-4} = Rn{5-4};
1353 let DecoderMethod = "DecodeVSTInstruction";
1356 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1357 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1358 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
1360 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1361 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1362 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
1364 // ...with address register writeback:
1365 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1366 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1367 (ins addrmode6:$Rn, am6offset:$Rm,
1368 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1369 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1370 "$Rn.addr = $wb", []> {
1371 let Inst{5-4} = Rn{5-4};
1372 let DecoderMethod = "DecodeVSTInstruction";
1375 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
1376 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
1377 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
1379 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1380 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1381 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1383 // ...with double-spaced registers:
1384 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
1385 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
1386 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
1387 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
1388 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
1389 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
1391 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1392 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1393 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1395 // ...alternate versions to be allocated odd register numbers:
1396 def VST4q8oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1397 def VST4q16oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1398 def VST4q32oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1400 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1401 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1402 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1404 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1406 // Classes for VST*LN pseudo-instructions with multi-register operands.
1407 // These are expanded to real instructions after register allocation.
1408 class VSTQLNPseudo<InstrItinClass itin>
1409 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1411 class VSTQLNWBPseudo<InstrItinClass itin>
1412 : PseudoNLdSt<(outs GPR:$wb),
1413 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1414 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1415 class VSTQQLNPseudo<InstrItinClass itin>
1416 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1418 class VSTQQLNWBPseudo<InstrItinClass itin>
1419 : PseudoNLdSt<(outs GPR:$wb),
1420 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1421 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1422 class VSTQQQQLNPseudo<InstrItinClass itin>
1423 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1425 class VSTQQQQLNWBPseudo<InstrItinClass itin>
1426 : PseudoNLdSt<(outs GPR:$wb),
1427 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1428 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1430 // VST1LN : Vector Store (single element from one lane)
1431 class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1432 PatFrag StoreOp, SDNode ExtractOp>
1433 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1434 (ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane),
1435 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1436 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6:$Rn)]> {
1438 let DecoderMethod = "DecodeVST1LN";
1440 class VST1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1441 PatFrag StoreOp, SDNode ExtractOp>
1442 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1443 (ins addrmode6oneL32:$Rn, DPR:$Vd, nohash_imm:$lane),
1444 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1445 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6oneL32:$Rn)]>{
1447 let DecoderMethod = "DecodeVST1LN";
1449 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1450 : VSTQLNPseudo<IIC_VST1ln> {
1451 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1455 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
1457 let Inst{7-5} = lane{2-0};
1459 def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
1461 let Inst{7-6} = lane{1-0};
1462 let Inst{4} = Rn{5};
1465 def VST1LNd32 : VST1LN32<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt> {
1466 let Inst{7} = lane{0};
1467 let Inst{5-4} = Rn{5-4};
1470 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
1471 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
1472 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
1474 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
1475 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1476 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
1477 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1479 // ...with address register writeback:
1480 class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1481 PatFrag StoreOp, SDNode ExtractOp>
1482 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1483 (ins addrmode6:$Rn, am6offset:$Rm,
1484 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
1485 "\\{$Vd[$lane]\\}, $Rn$Rm",
1487 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
1488 addrmode6:$Rn, am6offset:$Rm))]> {
1489 let DecoderMethod = "DecodeVST1LN";
1491 class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1492 : VSTQLNWBPseudo<IIC_VST1lnu> {
1493 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1494 addrmode6:$addr, am6offset:$offset))];
1497 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8,
1499 let Inst{7-5} = lane{2-0};
1501 def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16", v4i16, post_truncsti16,
1503 let Inst{7-6} = lane{1-0};
1504 let Inst{4} = Rn{5};
1506 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32", v2i32, post_store,
1508 let Inst{7} = lane{0};
1509 let Inst{5-4} = Rn{5-4};
1512 def VST1LNq8Pseudo_UPD : VST1QLNWBPseudo<v16i8, post_truncsti8, NEONvgetlaneu>;
1513 def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,NEONvgetlaneu>;
1514 def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
1516 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1518 // VST2LN : Vector Store (single 2-element structure from one lane)
1519 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1520 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1521 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
1522 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
1525 let Inst{4} = Rn{4};
1526 let DecoderMethod = "DecodeVST2LN";
1529 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
1530 let Inst{7-5} = lane{2-0};
1532 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
1533 let Inst{7-6} = lane{1-0};
1535 def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
1536 let Inst{7} = lane{0};
1539 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1540 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1541 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1543 // ...with double-spaced registers:
1544 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
1545 let Inst{7-6} = lane{1-0};
1546 let Inst{4} = Rn{4};
1548 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
1549 let Inst{7} = lane{0};
1550 let Inst{4} = Rn{4};
1553 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1554 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1556 // ...with address register writeback:
1557 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1558 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1559 (ins addrmode6:$addr, am6offset:$offset,
1560 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
1561 "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset",
1562 "$addr.addr = $wb", []> {
1563 let Inst{4} = Rn{4};
1564 let DecoderMethod = "DecodeVST2LN";
1567 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
1568 let Inst{7-5} = lane{2-0};
1570 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
1571 let Inst{7-6} = lane{1-0};
1573 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
1574 let Inst{7} = lane{0};
1577 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1578 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1579 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1581 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
1582 let Inst{7-6} = lane{1-0};
1584 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
1585 let Inst{7} = lane{0};
1588 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1589 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1591 // VST3LN : Vector Store (single 3-element structure from one lane)
1592 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1593 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1594 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
1595 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
1596 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
1598 let DecoderMethod = "DecodeVST3LN";
1601 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
1602 let Inst{7-5} = lane{2-0};
1604 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
1605 let Inst{7-6} = lane{1-0};
1607 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
1608 let Inst{7} = lane{0};
1611 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1612 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1613 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1615 // ...with double-spaced registers:
1616 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
1617 let Inst{7-6} = lane{1-0};
1619 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
1620 let Inst{7} = lane{0};
1623 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1624 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1626 // ...with address register writeback:
1627 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1628 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1629 (ins addrmode6:$Rn, am6offset:$Rm,
1630 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1631 IIC_VST3lnu, "vst3", Dt,
1632 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
1633 "$Rn.addr = $wb", []> {
1634 let DecoderMethod = "DecodeVST3LN";
1637 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
1638 let Inst{7-5} = lane{2-0};
1640 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
1641 let Inst{7-6} = lane{1-0};
1643 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
1644 let Inst{7} = lane{0};
1647 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1648 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1649 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1651 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
1652 let Inst{7-6} = lane{1-0};
1654 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
1655 let Inst{7} = lane{0};
1658 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1659 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1661 // VST4LN : Vector Store (single 4-element structure from one lane)
1662 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1663 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1664 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
1665 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
1666 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
1669 let Inst{4} = Rn{4};
1670 let DecoderMethod = "DecodeVST4LN";
1673 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
1674 let Inst{7-5} = lane{2-0};
1676 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
1677 let Inst{7-6} = lane{1-0};
1679 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
1680 let Inst{7} = lane{0};
1681 let Inst{5} = Rn{5};
1684 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1685 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1686 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1688 // ...with double-spaced registers:
1689 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
1690 let Inst{7-6} = lane{1-0};
1692 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
1693 let Inst{7} = lane{0};
1694 let Inst{5} = Rn{5};
1697 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1698 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1700 // ...with address register writeback:
1701 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1702 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1703 (ins addrmode6:$Rn, am6offset:$Rm,
1704 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1705 IIC_VST4lnu, "vst4", Dt,
1706 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
1707 "$Rn.addr = $wb", []> {
1708 let Inst{4} = Rn{4};
1709 let DecoderMethod = "DecodeVST4LN";
1712 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
1713 let Inst{7-5} = lane{2-0};
1715 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
1716 let Inst{7-6} = lane{1-0};
1718 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
1719 let Inst{7} = lane{0};
1720 let Inst{5} = Rn{5};
1723 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1724 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1725 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1727 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
1728 let Inst{7-6} = lane{1-0};
1730 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
1731 let Inst{7} = lane{0};
1732 let Inst{5} = Rn{5};
1735 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1736 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1738 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1741 //===----------------------------------------------------------------------===//
1742 // NEON pattern fragments
1743 //===----------------------------------------------------------------------===//
1745 // Extract D sub-registers of Q registers.
1746 def DSubReg_i8_reg : SDNodeXForm<imm, [{
1747 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1748 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
1750 def DSubReg_i16_reg : SDNodeXForm<imm, [{
1751 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1752 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
1754 def DSubReg_i32_reg : SDNodeXForm<imm, [{
1755 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1756 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
1758 def DSubReg_f64_reg : SDNodeXForm<imm, [{
1759 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1760 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
1763 // Extract S sub-registers of Q/D registers.
1764 def SSubReg_f32_reg : SDNodeXForm<imm, [{
1765 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
1766 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
1769 // Translate lane numbers from Q registers to D subregs.
1770 def SubReg_i8_lane : SDNodeXForm<imm, [{
1771 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
1773 def SubReg_i16_lane : SDNodeXForm<imm, [{
1774 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
1776 def SubReg_i32_lane : SDNodeXForm<imm, [{
1777 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
1780 //===----------------------------------------------------------------------===//
1781 // Instruction Classes
1782 //===----------------------------------------------------------------------===//
1784 // Basic 2-register operations: double- and quad-register.
1785 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1786 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1787 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1788 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
1789 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
1790 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
1791 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1792 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1793 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1794 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
1795 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
1796 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
1798 // Basic 2-register intrinsics, both double- and quad-register.
1799 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1800 bits<2> op17_16, bits<5> op11_7, bit op4,
1801 InstrItinClass itin, string OpcodeStr, string Dt,
1802 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1803 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
1804 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1805 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
1806 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1807 bits<2> op17_16, bits<5> op11_7, bit op4,
1808 InstrItinClass itin, string OpcodeStr, string Dt,
1809 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1810 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
1811 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1812 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
1814 // Narrow 2-register operations.
1815 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1816 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1817 InstrItinClass itin, string OpcodeStr, string Dt,
1818 ValueType TyD, ValueType TyQ, SDNode OpNode>
1819 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
1820 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1821 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
1823 // Narrow 2-register intrinsics.
1824 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1825 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1826 InstrItinClass itin, string OpcodeStr, string Dt,
1827 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
1828 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
1829 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1830 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
1832 // Long 2-register operations (currently only used for VMOVL).
1833 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1834 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1835 InstrItinClass itin, string OpcodeStr, string Dt,
1836 ValueType TyQ, ValueType TyD, SDNode OpNode>
1837 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
1838 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1839 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
1841 // Long 2-register intrinsics.
1842 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1843 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1844 InstrItinClass itin, string OpcodeStr, string Dt,
1845 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
1846 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
1847 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1848 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
1850 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
1851 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
1852 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
1853 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
1854 OpcodeStr, Dt, "$Vd, $Vm",
1855 "$src1 = $Vd, $src2 = $Vm", []>;
1856 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
1857 InstrItinClass itin, string OpcodeStr, string Dt>
1858 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
1859 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
1860 "$src1 = $Vd, $src2 = $Vm", []>;
1862 // Basic 3-register operations: double- and quad-register.
1863 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1864 InstrItinClass itin, string OpcodeStr, string Dt,
1865 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1866 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1867 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1868 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1869 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
1870 let isCommutable = Commutable;
1872 // Same as N3VD but no data type.
1873 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1874 InstrItinClass itin, string OpcodeStr,
1875 ValueType ResTy, ValueType OpTy,
1876 SDNode OpNode, bit Commutable>
1877 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
1878 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1879 OpcodeStr, "$Vd, $Vn, $Vm", "",
1880 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
1881 let isCommutable = Commutable;
1884 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
1885 InstrItinClass itin, string OpcodeStr, string Dt,
1886 ValueType Ty, SDNode ShOp>
1887 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
1888 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1889 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1891 (Ty (ShOp (Ty DPR:$Vn),
1892 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
1893 let isCommutable = 0;
1895 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
1896 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1897 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
1898 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1899 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm[$lane]","",
1901 (Ty (ShOp (Ty DPR:$Vn),
1902 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
1903 let isCommutable = 0;
1906 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1907 InstrItinClass itin, string OpcodeStr, string Dt,
1908 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1909 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1910 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1911 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1912 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
1913 let isCommutable = Commutable;
1915 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1916 InstrItinClass itin, string OpcodeStr,
1917 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1918 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
1919 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1920 OpcodeStr, "$Vd, $Vn, $Vm", "",
1921 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
1922 let isCommutable = Commutable;
1924 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
1925 InstrItinClass itin, string OpcodeStr, string Dt,
1926 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1927 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
1928 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1929 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1930 [(set (ResTy QPR:$Vd),
1931 (ResTy (ShOp (ResTy QPR:$Vn),
1932 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
1934 let isCommutable = 0;
1936 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
1937 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1938 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
1939 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1940 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm[$lane]","",
1941 [(set (ResTy QPR:$Vd),
1942 (ResTy (ShOp (ResTy QPR:$Vn),
1943 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
1945 let isCommutable = 0;
1948 // Basic 3-register intrinsics, both double- and quad-register.
1949 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1950 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1951 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1952 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1953 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
1954 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1955 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
1956 let isCommutable = Commutable;
1958 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1959 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1960 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
1961 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1962 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1964 (Ty (IntOp (Ty DPR:$Vn),
1965 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
1967 let isCommutable = 0;
1969 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1970 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1971 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
1972 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1973 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1975 (Ty (IntOp (Ty DPR:$Vn),
1976 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
1977 let isCommutable = 0;
1979 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1980 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1981 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1982 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1983 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
1984 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
1985 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
1986 let isCommutable = 0;
1989 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1990 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1991 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1992 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1993 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
1994 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1995 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
1996 let isCommutable = Commutable;
1998 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1999 string OpcodeStr, string Dt,
2000 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2001 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2002 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2003 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2004 [(set (ResTy QPR:$Vd),
2005 (ResTy (IntOp (ResTy QPR:$Vn),
2006 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2008 let isCommutable = 0;
2010 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2011 string OpcodeStr, string Dt,
2012 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2013 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2014 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2015 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2016 [(set (ResTy QPR:$Vd),
2017 (ResTy (IntOp (ResTy QPR:$Vn),
2018 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2020 let isCommutable = 0;
2022 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2023 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2024 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2025 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2026 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
2027 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2028 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
2029 let isCommutable = 0;
2032 // Multiply-Add/Sub operations: double- and quad-register.
2033 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2034 InstrItinClass itin, string OpcodeStr, string Dt,
2035 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode>
2036 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2037 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2038 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2039 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2040 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
2042 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2043 string OpcodeStr, string Dt,
2044 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
2045 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2047 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2049 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2051 (Ty (ShOp (Ty DPR:$src1),
2053 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2055 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2056 string OpcodeStr, string Dt,
2057 ValueType Ty, SDNode MulOp, SDNode ShOp>
2058 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2060 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2062 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2064 (Ty (ShOp (Ty DPR:$src1),
2066 (Ty (NEONvduplane (Ty DPR_8:$Vm),
2069 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2070 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
2071 SDPatternOperator MulOp, SDPatternOperator OpNode>
2072 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2073 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2074 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2075 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2076 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
2077 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2078 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2079 SDPatternOperator MulOp, SDPatternOperator ShOp>
2080 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2082 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2084 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2085 [(set (ResTy QPR:$Vd),
2086 (ResTy (ShOp (ResTy QPR:$src1),
2087 (ResTy (MulOp QPR:$Vn,
2088 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2090 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2091 string OpcodeStr, string Dt,
2092 ValueType ResTy, ValueType OpTy,
2093 SDNode MulOp, SDNode ShOp>
2094 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2096 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2098 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2099 [(set (ResTy QPR:$Vd),
2100 (ResTy (ShOp (ResTy QPR:$src1),
2101 (ResTy (MulOp QPR:$Vn,
2102 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2105 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
2106 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2107 InstrItinClass itin, string OpcodeStr, string Dt,
2108 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2109 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2110 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2111 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2112 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2113 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
2114 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2115 InstrItinClass itin, string OpcodeStr, string Dt,
2116 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2117 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2118 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2119 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2120 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2121 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2123 // Neon 3-argument intrinsics, both double- and quad-register.
2124 // The destination register is also used as the first source operand register.
2125 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2126 InstrItinClass itin, string OpcodeStr, string Dt,
2127 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2128 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2129 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2130 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2131 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2132 (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2133 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2134 InstrItinClass itin, string OpcodeStr, string Dt,
2135 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2136 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2137 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2138 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2139 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2140 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2142 // Long Multiply-Add/Sub operations.
2143 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2144 InstrItinClass itin, string OpcodeStr, string Dt,
2145 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2146 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2147 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2148 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2149 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2150 (TyQ (MulOp (TyD DPR:$Vn),
2151 (TyD DPR:$Vm)))))]>;
2152 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2153 InstrItinClass itin, string OpcodeStr, string Dt,
2154 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2155 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2156 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2158 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2160 (OpNode (TyQ QPR:$src1),
2161 (TyQ (MulOp (TyD DPR:$Vn),
2162 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),
2164 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2165 InstrItinClass itin, string OpcodeStr, string Dt,
2166 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2167 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2168 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2170 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2172 (OpNode (TyQ QPR:$src1),
2173 (TyQ (MulOp (TyD DPR:$Vn),
2174 (TyD (NEONvduplane (TyD DPR_8:$Vm),
2177 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
2178 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2179 InstrItinClass itin, string OpcodeStr, string Dt,
2180 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2182 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2183 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2184 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2185 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2186 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2187 (TyD DPR:$Vm)))))))]>;
2189 // Neon Long 3-argument intrinsic. The destination register is
2190 // a quad-register and is also used as the first source operand register.
2191 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2192 InstrItinClass itin, string OpcodeStr, string Dt,
2193 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
2194 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2195 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2196 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2198 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2199 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2200 string OpcodeStr, string Dt,
2201 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2202 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2204 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2206 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2207 [(set (ResTy QPR:$Vd),
2208 (ResTy (IntOp (ResTy QPR:$src1),
2210 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2212 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2213 InstrItinClass itin, string OpcodeStr, string Dt,
2214 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2215 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2217 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2219 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2220 [(set (ResTy QPR:$Vd),
2221 (ResTy (IntOp (ResTy QPR:$src1),
2223 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2226 // Narrowing 3-register intrinsics.
2227 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2228 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
2229 Intrinsic IntOp, bit Commutable>
2230 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2231 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2232 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2233 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2234 let isCommutable = Commutable;
2237 // Long 3-register operations.
2238 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2239 InstrItinClass itin, string OpcodeStr, string Dt,
2240 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
2241 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2242 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2243 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2244 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2245 let isCommutable = Commutable;
2247 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2248 InstrItinClass itin, string OpcodeStr, string Dt,
2249 ValueType TyQ, ValueType TyD, SDNode OpNode>
2250 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2251 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2252 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2254 (TyQ (OpNode (TyD DPR:$Vn),
2255 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
2256 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2257 InstrItinClass itin, string OpcodeStr, string Dt,
2258 ValueType TyQ, ValueType TyD, SDNode OpNode>
2259 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2260 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2261 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2263 (TyQ (OpNode (TyD DPR:$Vn),
2264 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
2266 // Long 3-register operations with explicitly extended operands.
2267 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2268 InstrItinClass itin, string OpcodeStr, string Dt,
2269 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
2271 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2272 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2273 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2274 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
2275 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2276 let isCommutable = Commutable;
2279 // Long 3-register intrinsics with explicit extend (VABDL).
2280 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2281 InstrItinClass itin, string OpcodeStr, string Dt,
2282 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2284 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2285 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2286 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2287 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2288 (TyD DPR:$Vm))))))]> {
2289 let isCommutable = Commutable;
2292 // Long 3-register intrinsics.
2293 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2294 InstrItinClass itin, string OpcodeStr, string Dt,
2295 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
2296 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2297 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2298 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2299 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2300 let isCommutable = Commutable;
2302 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2303 string OpcodeStr, string Dt,
2304 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2305 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2306 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2307 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2308 [(set (ResTy QPR:$Vd),
2309 (ResTy (IntOp (OpTy DPR:$Vn),
2310 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2312 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2313 InstrItinClass itin, string OpcodeStr, string Dt,
2314 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2315 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2316 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2317 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2318 [(set (ResTy QPR:$Vd),
2319 (ResTy (IntOp (OpTy DPR:$Vn),
2320 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2323 // Wide 3-register operations.
2324 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2325 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
2326 SDNode OpNode, SDNode ExtOp, bit Commutable>
2327 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2328 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
2329 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2330 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
2331 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2332 let isCommutable = Commutable;
2335 // Pairwise long 2-register intrinsics, both double- and quad-register.
2336 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2337 bits<2> op17_16, bits<5> op11_7, bit op4,
2338 string OpcodeStr, string Dt,
2339 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2340 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2341 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2342 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2343 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2344 bits<2> op17_16, bits<5> op11_7, bit op4,
2345 string OpcodeStr, string Dt,
2346 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2347 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2348 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2349 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2351 // Pairwise long 2-register accumulate intrinsics,
2352 // both double- and quad-register.
2353 // The destination register is also used as the first source operand register.
2354 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2355 bits<2> op17_16, bits<5> op11_7, bit op4,
2356 string OpcodeStr, string Dt,
2357 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2358 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
2359 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
2360 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2361 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
2362 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2363 bits<2> op17_16, bits<5> op11_7, bit op4,
2364 string OpcodeStr, string Dt,
2365 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2366 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
2367 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
2368 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2369 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
2371 // Shift by immediate,
2372 // both double- and quad-register.
2373 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2374 Format f, InstrItinClass itin, Operand ImmTy,
2375 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2376 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2377 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
2378 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2379 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
2380 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2381 Format f, InstrItinClass itin, Operand ImmTy,
2382 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2383 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2384 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
2385 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2386 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
2388 // Long shift by immediate.
2389 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2390 string OpcodeStr, string Dt,
2391 ValueType ResTy, ValueType OpTy, SDNode OpNode>
2392 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2393 (outs QPR:$Vd), (ins DPR:$Vm, i32imm:$SIMM), N2RegVShLFrm,
2394 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2395 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm),
2396 (i32 imm:$SIMM))))]>;
2398 // Narrow shift by immediate.
2399 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2400 InstrItinClass itin, string OpcodeStr, string Dt,
2401 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode>
2402 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2403 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
2404 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2405 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
2406 (i32 imm:$SIMM))))]>;
2408 // Shift right by immediate and accumulate,
2409 // both double- and quad-register.
2410 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2411 Operand ImmTy, string OpcodeStr, string Dt,
2412 ValueType Ty, SDNode ShOp>
2413 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2414 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2415 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2416 [(set DPR:$Vd, (Ty (add DPR:$src1,
2417 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
2418 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2419 Operand ImmTy, string OpcodeStr, string Dt,
2420 ValueType Ty, SDNode ShOp>
2421 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2422 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2423 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2424 [(set QPR:$Vd, (Ty (add QPR:$src1,
2425 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
2427 // Shift by immediate and insert,
2428 // both double- and quad-register.
2429 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2430 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2431 ValueType Ty,SDNode ShOp>
2432 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2433 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiD,
2434 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2435 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
2436 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2437 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2438 ValueType Ty,SDNode ShOp>
2439 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2440 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiQ,
2441 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2442 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
2444 // Convert, with fractional bits immediate,
2445 // both double- and quad-register.
2446 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2447 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2449 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2450 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2451 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2452 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
2453 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2454 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2456 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2457 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2458 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2459 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
2461 //===----------------------------------------------------------------------===//
2463 //===----------------------------------------------------------------------===//
2465 // Abbreviations used in multiclass suffixes:
2466 // Q = quarter int (8 bit) elements
2467 // H = half int (16 bit) elements
2468 // S = single int (32 bit) elements
2469 // D = double int (64 bit) elements
2471 // Neon 2-register vector operations and intrinsics.
2473 // Neon 2-register comparisons.
2474 // source operand element sizes of 8, 16 and 32 bits:
2475 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2476 bits<5> op11_7, bit op4, string opc, string Dt,
2477 string asm, SDNode OpNode> {
2478 // 64-bit vector types.
2479 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
2480 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2481 opc, !strconcat(Dt, "8"), asm, "",
2482 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
2483 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
2484 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2485 opc, !strconcat(Dt, "16"), asm, "",
2486 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>;
2487 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2488 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2489 opc, !strconcat(Dt, "32"), asm, "",
2490 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>;
2491 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2492 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2493 opc, "f32", asm, "",
2494 [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> {
2495 let Inst{10} = 1; // overwrite F = 1
2498 // 128-bit vector types.
2499 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
2500 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2501 opc, !strconcat(Dt, "8"), asm, "",
2502 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
2503 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
2504 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2505 opc, !strconcat(Dt, "16"), asm, "",
2506 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
2507 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2508 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2509 opc, !strconcat(Dt, "32"), asm, "",
2510 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
2511 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2512 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2513 opc, "f32", asm, "",
2514 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
2515 let Inst{10} = 1; // overwrite F = 1
2520 // Neon 2-register vector intrinsics,
2521 // element sizes of 8, 16 and 32 bits:
2522 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2523 bits<5> op11_7, bit op4,
2524 InstrItinClass itinD, InstrItinClass itinQ,
2525 string OpcodeStr, string Dt, Intrinsic IntOp> {
2526 // 64-bit vector types.
2527 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2528 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2529 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2530 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
2531 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2532 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
2534 // 128-bit vector types.
2535 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2536 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
2537 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2538 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
2539 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2540 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
2544 // Neon Narrowing 2-register vector operations,
2545 // source operand element sizes of 16, 32 and 64 bits:
2546 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2547 bits<5> op11_7, bit op6, bit op4,
2548 InstrItinClass itin, string OpcodeStr, string Dt,
2550 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2551 itin, OpcodeStr, !strconcat(Dt, "16"),
2552 v8i8, v8i16, OpNode>;
2553 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2554 itin, OpcodeStr, !strconcat(Dt, "32"),
2555 v4i16, v4i32, OpNode>;
2556 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2557 itin, OpcodeStr, !strconcat(Dt, "64"),
2558 v2i32, v2i64, OpNode>;
2561 // Neon Narrowing 2-register vector intrinsics,
2562 // source operand element sizes of 16, 32 and 64 bits:
2563 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2564 bits<5> op11_7, bit op6, bit op4,
2565 InstrItinClass itin, string OpcodeStr, string Dt,
2567 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2568 itin, OpcodeStr, !strconcat(Dt, "16"),
2569 v8i8, v8i16, IntOp>;
2570 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2571 itin, OpcodeStr, !strconcat(Dt, "32"),
2572 v4i16, v4i32, IntOp>;
2573 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2574 itin, OpcodeStr, !strconcat(Dt, "64"),
2575 v2i32, v2i64, IntOp>;
2579 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
2580 // source operand element sizes of 16, 32 and 64 bits:
2581 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
2582 string OpcodeStr, string Dt, SDNode OpNode> {
2583 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2584 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
2585 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2586 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2587 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2588 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2592 // Neon 3-register vector operations.
2594 // First with only element sizes of 8, 16 and 32 bits:
2595 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2596 InstrItinClass itinD16, InstrItinClass itinD32,
2597 InstrItinClass itinQ16, InstrItinClass itinQ32,
2598 string OpcodeStr, string Dt,
2599 SDNode OpNode, bit Commutable = 0> {
2600 // 64-bit vector types.
2601 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
2602 OpcodeStr, !strconcat(Dt, "8"),
2603 v8i8, v8i8, OpNode, Commutable>;
2604 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
2605 OpcodeStr, !strconcat(Dt, "16"),
2606 v4i16, v4i16, OpNode, Commutable>;
2607 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
2608 OpcodeStr, !strconcat(Dt, "32"),
2609 v2i32, v2i32, OpNode, Commutable>;
2611 // 128-bit vector types.
2612 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
2613 OpcodeStr, !strconcat(Dt, "8"),
2614 v16i8, v16i8, OpNode, Commutable>;
2615 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
2616 OpcodeStr, !strconcat(Dt, "16"),
2617 v8i16, v8i16, OpNode, Commutable>;
2618 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
2619 OpcodeStr, !strconcat(Dt, "32"),
2620 v4i32, v4i32, OpNode, Commutable>;
2623 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
2624 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2626 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
2628 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2629 v8i16, v4i16, ShOp>;
2630 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
2631 v4i32, v2i32, ShOp>;
2634 // ....then also with element size 64 bits:
2635 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2636 InstrItinClass itinD, InstrItinClass itinQ,
2637 string OpcodeStr, string Dt,
2638 SDNode OpNode, bit Commutable = 0>
2639 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
2640 OpcodeStr, Dt, OpNode, Commutable> {
2641 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
2642 OpcodeStr, !strconcat(Dt, "64"),
2643 v1i64, v1i64, OpNode, Commutable>;
2644 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
2645 OpcodeStr, !strconcat(Dt, "64"),
2646 v2i64, v2i64, OpNode, Commutable>;
2650 // Neon 3-register vector intrinsics.
2652 // First with only element sizes of 16 and 32 bits:
2653 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2654 InstrItinClass itinD16, InstrItinClass itinD32,
2655 InstrItinClass itinQ16, InstrItinClass itinQ32,
2656 string OpcodeStr, string Dt,
2657 Intrinsic IntOp, bit Commutable = 0> {
2658 // 64-bit vector types.
2659 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
2660 OpcodeStr, !strconcat(Dt, "16"),
2661 v4i16, v4i16, IntOp, Commutable>;
2662 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
2663 OpcodeStr, !strconcat(Dt, "32"),
2664 v2i32, v2i32, IntOp, Commutable>;
2666 // 128-bit vector types.
2667 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2668 OpcodeStr, !strconcat(Dt, "16"),
2669 v8i16, v8i16, IntOp, Commutable>;
2670 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2671 OpcodeStr, !strconcat(Dt, "32"),
2672 v4i32, v4i32, IntOp, Commutable>;
2674 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2675 InstrItinClass itinD16, InstrItinClass itinD32,
2676 InstrItinClass itinQ16, InstrItinClass itinQ32,
2677 string OpcodeStr, string Dt,
2679 // 64-bit vector types.
2680 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
2681 OpcodeStr, !strconcat(Dt, "16"),
2682 v4i16, v4i16, IntOp>;
2683 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
2684 OpcodeStr, !strconcat(Dt, "32"),
2685 v2i32, v2i32, IntOp>;
2687 // 128-bit vector types.
2688 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2689 OpcodeStr, !strconcat(Dt, "16"),
2690 v8i16, v8i16, IntOp>;
2691 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2692 OpcodeStr, !strconcat(Dt, "32"),
2693 v4i32, v4i32, IntOp>;
2696 multiclass N3VIntSL_HS<bits<4> op11_8,
2697 InstrItinClass itinD16, InstrItinClass itinD32,
2698 InstrItinClass itinQ16, InstrItinClass itinQ32,
2699 string OpcodeStr, string Dt, Intrinsic IntOp> {
2700 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
2701 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
2702 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
2703 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
2704 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
2705 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
2706 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
2707 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
2710 // ....then also with element size of 8 bits:
2711 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2712 InstrItinClass itinD16, InstrItinClass itinD32,
2713 InstrItinClass itinQ16, InstrItinClass itinQ32,
2714 string OpcodeStr, string Dt,
2715 Intrinsic IntOp, bit Commutable = 0>
2716 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2717 OpcodeStr, Dt, IntOp, Commutable> {
2718 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
2719 OpcodeStr, !strconcat(Dt, "8"),
2720 v8i8, v8i8, IntOp, Commutable>;
2721 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2722 OpcodeStr, !strconcat(Dt, "8"),
2723 v16i8, v16i8, IntOp, Commutable>;
2725 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2726 InstrItinClass itinD16, InstrItinClass itinD32,
2727 InstrItinClass itinQ16, InstrItinClass itinQ32,
2728 string OpcodeStr, string Dt,
2730 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2731 OpcodeStr, Dt, IntOp> {
2732 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
2733 OpcodeStr, !strconcat(Dt, "8"),
2735 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2736 OpcodeStr, !strconcat(Dt, "8"),
2737 v16i8, v16i8, IntOp>;
2741 // ....then also with element size of 64 bits:
2742 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2743 InstrItinClass itinD16, InstrItinClass itinD32,
2744 InstrItinClass itinQ16, InstrItinClass itinQ32,
2745 string OpcodeStr, string Dt,
2746 Intrinsic IntOp, bit Commutable = 0>
2747 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2748 OpcodeStr, Dt, IntOp, Commutable> {
2749 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
2750 OpcodeStr, !strconcat(Dt, "64"),
2751 v1i64, v1i64, IntOp, Commutable>;
2752 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2753 OpcodeStr, !strconcat(Dt, "64"),
2754 v2i64, v2i64, IntOp, Commutable>;
2756 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2757 InstrItinClass itinD16, InstrItinClass itinD32,
2758 InstrItinClass itinQ16, InstrItinClass itinQ32,
2759 string OpcodeStr, string Dt,
2761 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2762 OpcodeStr, Dt, IntOp> {
2763 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
2764 OpcodeStr, !strconcat(Dt, "64"),
2765 v1i64, v1i64, IntOp>;
2766 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2767 OpcodeStr, !strconcat(Dt, "64"),
2768 v2i64, v2i64, IntOp>;
2771 // Neon Narrowing 3-register vector intrinsics,
2772 // source operand element sizes of 16, 32 and 64 bits:
2773 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2774 string OpcodeStr, string Dt,
2775 Intrinsic IntOp, bit Commutable = 0> {
2776 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
2777 OpcodeStr, !strconcat(Dt, "16"),
2778 v8i8, v8i16, IntOp, Commutable>;
2779 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
2780 OpcodeStr, !strconcat(Dt, "32"),
2781 v4i16, v4i32, IntOp, Commutable>;
2782 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
2783 OpcodeStr, !strconcat(Dt, "64"),
2784 v2i32, v2i64, IntOp, Commutable>;
2788 // Neon Long 3-register vector operations.
2790 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2791 InstrItinClass itin16, InstrItinClass itin32,
2792 string OpcodeStr, string Dt,
2793 SDNode OpNode, bit Commutable = 0> {
2794 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
2795 OpcodeStr, !strconcat(Dt, "8"),
2796 v8i16, v8i8, OpNode, Commutable>;
2797 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
2798 OpcodeStr, !strconcat(Dt, "16"),
2799 v4i32, v4i16, OpNode, Commutable>;
2800 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
2801 OpcodeStr, !strconcat(Dt, "32"),
2802 v2i64, v2i32, OpNode, Commutable>;
2805 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
2806 InstrItinClass itin, string OpcodeStr, string Dt,
2808 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
2809 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2810 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
2811 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2814 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2815 InstrItinClass itin16, InstrItinClass itin32,
2816 string OpcodeStr, string Dt,
2817 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2818 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
2819 OpcodeStr, !strconcat(Dt, "8"),
2820 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2821 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
2822 OpcodeStr, !strconcat(Dt, "16"),
2823 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2824 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
2825 OpcodeStr, !strconcat(Dt, "32"),
2826 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2829 // Neon Long 3-register vector intrinsics.
2831 // First with only element sizes of 16 and 32 bits:
2832 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2833 InstrItinClass itin16, InstrItinClass itin32,
2834 string OpcodeStr, string Dt,
2835 Intrinsic IntOp, bit Commutable = 0> {
2836 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
2837 OpcodeStr, !strconcat(Dt, "16"),
2838 v4i32, v4i16, IntOp, Commutable>;
2839 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
2840 OpcodeStr, !strconcat(Dt, "32"),
2841 v2i64, v2i32, IntOp, Commutable>;
2844 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
2845 InstrItinClass itin, string OpcodeStr, string Dt,
2847 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
2848 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2849 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
2850 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2853 // ....then also with element size of 8 bits:
2854 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2855 InstrItinClass itin16, InstrItinClass itin32,
2856 string OpcodeStr, string Dt,
2857 Intrinsic IntOp, bit Commutable = 0>
2858 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
2859 IntOp, Commutable> {
2860 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
2861 OpcodeStr, !strconcat(Dt, "8"),
2862 v8i16, v8i8, IntOp, Commutable>;
2865 // ....with explicit extend (VABDL).
2866 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2867 InstrItinClass itin, string OpcodeStr, string Dt,
2868 Intrinsic IntOp, SDNode ExtOp, bit Commutable = 0> {
2869 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
2870 OpcodeStr, !strconcat(Dt, "8"),
2871 v8i16, v8i8, IntOp, ExtOp, Commutable>;
2872 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
2873 OpcodeStr, !strconcat(Dt, "16"),
2874 v4i32, v4i16, IntOp, ExtOp, Commutable>;
2875 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
2876 OpcodeStr, !strconcat(Dt, "32"),
2877 v2i64, v2i32, IntOp, ExtOp, Commutable>;
2881 // Neon Wide 3-register vector intrinsics,
2882 // source operand element sizes of 8, 16 and 32 bits:
2883 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2884 string OpcodeStr, string Dt,
2885 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2886 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
2887 OpcodeStr, !strconcat(Dt, "8"),
2888 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2889 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
2890 OpcodeStr, !strconcat(Dt, "16"),
2891 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2892 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
2893 OpcodeStr, !strconcat(Dt, "32"),
2894 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2898 // Neon Multiply-Op vector operations,
2899 // element sizes of 8, 16 and 32 bits:
2900 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2901 InstrItinClass itinD16, InstrItinClass itinD32,
2902 InstrItinClass itinQ16, InstrItinClass itinQ32,
2903 string OpcodeStr, string Dt, SDNode OpNode> {
2904 // 64-bit vector types.
2905 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
2906 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
2907 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
2908 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
2909 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
2910 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
2912 // 128-bit vector types.
2913 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
2914 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
2915 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
2916 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
2917 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
2918 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
2921 multiclass N3VMulOpSL_HS<bits<4> op11_8,
2922 InstrItinClass itinD16, InstrItinClass itinD32,
2923 InstrItinClass itinQ16, InstrItinClass itinQ32,
2924 string OpcodeStr, string Dt, SDNode ShOp> {
2925 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
2926 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
2927 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
2928 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
2929 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
2930 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
2932 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
2933 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
2937 // Neon Intrinsic-Op vector operations,
2938 // element sizes of 8, 16 and 32 bits:
2939 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2940 InstrItinClass itinD, InstrItinClass itinQ,
2941 string OpcodeStr, string Dt, Intrinsic IntOp,
2943 // 64-bit vector types.
2944 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
2945 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
2946 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
2947 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
2948 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
2949 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
2951 // 128-bit vector types.
2952 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
2953 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
2954 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
2955 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
2956 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
2957 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
2960 // Neon 3-argument intrinsics,
2961 // element sizes of 8, 16 and 32 bits:
2962 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2963 InstrItinClass itinD, InstrItinClass itinQ,
2964 string OpcodeStr, string Dt, Intrinsic IntOp> {
2965 // 64-bit vector types.
2966 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
2967 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2968 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
2969 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
2970 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
2971 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
2973 // 128-bit vector types.
2974 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
2975 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
2976 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
2977 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
2978 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
2979 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
2983 // Neon Long Multiply-Op vector operations,
2984 // element sizes of 8, 16 and 32 bits:
2985 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2986 InstrItinClass itin16, InstrItinClass itin32,
2987 string OpcodeStr, string Dt, SDNode MulOp,
2989 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
2990 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
2991 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
2992 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
2993 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
2994 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
2997 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
2998 string Dt, SDNode MulOp, SDNode OpNode> {
2999 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
3000 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
3001 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
3002 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3006 // Neon Long 3-argument intrinsics.
3008 // First with only element sizes of 16 and 32 bits:
3009 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3010 InstrItinClass itin16, InstrItinClass itin32,
3011 string OpcodeStr, string Dt, Intrinsic IntOp> {
3012 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
3013 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3014 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
3015 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3018 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
3019 string OpcodeStr, string Dt, Intrinsic IntOp> {
3020 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
3021 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
3022 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
3023 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3026 // ....then also with element size of 8 bits:
3027 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3028 InstrItinClass itin16, InstrItinClass itin32,
3029 string OpcodeStr, string Dt, Intrinsic IntOp>
3030 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
3031 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
3032 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
3035 // ....with explicit extend (VABAL).
3036 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3037 InstrItinClass itin, string OpcodeStr, string Dt,
3038 Intrinsic IntOp, SDNode ExtOp, SDNode OpNode> {
3039 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
3040 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
3041 IntOp, ExtOp, OpNode>;
3042 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
3043 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
3044 IntOp, ExtOp, OpNode>;
3045 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
3046 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
3047 IntOp, ExtOp, OpNode>;
3051 // Neon Pairwise long 2-register intrinsics,
3052 // element sizes of 8, 16 and 32 bits:
3053 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3054 bits<5> op11_7, bit op4,
3055 string OpcodeStr, string Dt, Intrinsic IntOp> {
3056 // 64-bit vector types.
3057 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3058 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3059 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3060 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3061 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3062 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3064 // 128-bit vector types.
3065 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3066 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3067 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3068 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3069 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3070 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3074 // Neon Pairwise long 2-register accumulate intrinsics,
3075 // element sizes of 8, 16 and 32 bits:
3076 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3077 bits<5> op11_7, bit op4,
3078 string OpcodeStr, string Dt, Intrinsic IntOp> {
3079 // 64-bit vector types.
3080 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3081 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3082 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3083 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3084 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3085 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3087 // 128-bit vector types.
3088 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3089 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3090 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3091 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3092 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3093 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3097 // Neon 2-register vector shift by immediate,
3098 // with f of either N2RegVShLFrm or N2RegVShRFrm
3099 // element sizes of 8, 16, 32 and 64 bits:
3100 multiclass N2VShL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3101 InstrItinClass itin, string OpcodeStr, string Dt,
3103 // 64-bit vector types.
3104 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3105 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3106 let Inst{21-19} = 0b001; // imm6 = 001xxx
3108 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3109 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3110 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3112 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3113 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3114 let Inst{21} = 0b1; // imm6 = 1xxxxx
3116 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3117 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3120 // 128-bit vector types.
3121 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3122 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3123 let Inst{21-19} = 0b001; // imm6 = 001xxx
3125 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3126 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3127 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3129 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3130 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3131 let Inst{21} = 0b1; // imm6 = 1xxxxx
3133 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3134 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3137 multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3138 InstrItinClass itin, string OpcodeStr, string Dt,
3140 // 64-bit vector types.
3141 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3142 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3143 let Inst{21-19} = 0b001; // imm6 = 001xxx
3145 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3146 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3147 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3149 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3150 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3151 let Inst{21} = 0b1; // imm6 = 1xxxxx
3153 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3154 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3157 // 128-bit vector types.
3158 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3159 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3160 let Inst{21-19} = 0b001; // imm6 = 001xxx
3162 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3163 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3164 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3166 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3167 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3168 let Inst{21} = 0b1; // imm6 = 1xxxxx
3170 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3171 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3175 // Neon Shift-Accumulate vector operations,
3176 // element sizes of 8, 16, 32 and 64 bits:
3177 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3178 string OpcodeStr, string Dt, SDNode ShOp> {
3179 // 64-bit vector types.
3180 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3181 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
3182 let Inst{21-19} = 0b001; // imm6 = 001xxx
3184 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3185 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
3186 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3188 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3189 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
3190 let Inst{21} = 0b1; // imm6 = 1xxxxx
3192 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3193 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
3196 // 128-bit vector types.
3197 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3198 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
3199 let Inst{21-19} = 0b001; // imm6 = 001xxx
3201 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3202 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
3203 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3205 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3206 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
3207 let Inst{21} = 0b1; // imm6 = 1xxxxx
3209 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3210 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
3214 // Neon Shift-Insert vector operations,
3215 // with f of either N2RegVShLFrm or N2RegVShRFrm
3216 // element sizes of 8, 16, 32 and 64 bits:
3217 multiclass N2VShInsL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3219 // 64-bit vector types.
3220 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3221 N2RegVShLFrm, OpcodeStr, "8", v8i8, NEONvsli> {
3222 let Inst{21-19} = 0b001; // imm6 = 001xxx
3224 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3225 N2RegVShLFrm, OpcodeStr, "16", v4i16, NEONvsli> {
3226 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3228 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3229 N2RegVShLFrm, OpcodeStr, "32", v2i32, NEONvsli> {
3230 let Inst{21} = 0b1; // imm6 = 1xxxxx
3232 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, i32imm,
3233 N2RegVShLFrm, OpcodeStr, "64", v1i64, NEONvsli>;
3236 // 128-bit vector types.
3237 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3238 N2RegVShLFrm, OpcodeStr, "8", v16i8, NEONvsli> {
3239 let Inst{21-19} = 0b001; // imm6 = 001xxx
3241 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3242 N2RegVShLFrm, OpcodeStr, "16", v8i16, NEONvsli> {
3243 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3245 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3246 N2RegVShLFrm, OpcodeStr, "32", v4i32, NEONvsli> {
3247 let Inst{21} = 0b1; // imm6 = 1xxxxx
3249 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, i32imm,
3250 N2RegVShLFrm, OpcodeStr, "64", v2i64, NEONvsli>;
3253 multiclass N2VShInsR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3255 // 64-bit vector types.
3256 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3257 N2RegVShRFrm, OpcodeStr, "8", v8i8, NEONvsri> {
3258 let Inst{21-19} = 0b001; // imm6 = 001xxx
3260 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3261 N2RegVShRFrm, OpcodeStr, "16", v4i16, NEONvsri> {
3262 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3264 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3265 N2RegVShRFrm, OpcodeStr, "32", v2i32, NEONvsri> {
3266 let Inst{21} = 0b1; // imm6 = 1xxxxx
3268 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3269 N2RegVShRFrm, OpcodeStr, "64", v1i64, NEONvsri>;
3272 // 128-bit vector types.
3273 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3274 N2RegVShRFrm, OpcodeStr, "8", v16i8, NEONvsri> {
3275 let Inst{21-19} = 0b001; // imm6 = 001xxx
3277 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3278 N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsri> {
3279 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3281 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3282 N2RegVShRFrm, OpcodeStr, "32", v4i32, NEONvsri> {
3283 let Inst{21} = 0b1; // imm6 = 1xxxxx
3285 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3286 N2RegVShRFrm, OpcodeStr, "64", v2i64, NEONvsri>;
3290 // Neon Shift Long operations,
3291 // element sizes of 8, 16, 32 bits:
3292 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3293 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
3294 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3295 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
3296 let Inst{21-19} = 0b001; // imm6 = 001xxx
3298 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3299 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
3300 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3302 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3303 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
3304 let Inst{21} = 0b1; // imm6 = 1xxxxx
3308 // Neon Shift Narrow operations,
3309 // element sizes of 16, 32, 64 bits:
3310 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3311 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
3313 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3314 OpcodeStr, !strconcat(Dt, "16"),
3315 v8i8, v8i16, shr_imm8, OpNode> {
3316 let Inst{21-19} = 0b001; // imm6 = 001xxx
3318 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3319 OpcodeStr, !strconcat(Dt, "32"),
3320 v4i16, v4i32, shr_imm16, OpNode> {
3321 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3323 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3324 OpcodeStr, !strconcat(Dt, "64"),
3325 v2i32, v2i64, shr_imm32, OpNode> {
3326 let Inst{21} = 0b1; // imm6 = 1xxxxx
3330 //===----------------------------------------------------------------------===//
3331 // Instruction Definitions.
3332 //===----------------------------------------------------------------------===//
3334 // Vector Add Operations.
3336 // VADD : Vector Add (integer and floating-point)
3337 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
3339 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
3340 v2f32, v2f32, fadd, 1>;
3341 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
3342 v4f32, v4f32, fadd, 1>;
3343 // VADDL : Vector Add Long (Q = D + D)
3344 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3345 "vaddl", "s", add, sext, 1>;
3346 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3347 "vaddl", "u", add, zext, 1>;
3348 // VADDW : Vector Add Wide (Q = Q + D)
3349 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
3350 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
3351 // VHADD : Vector Halving Add
3352 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
3353 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3354 "vhadd", "s", int_arm_neon_vhadds, 1>;
3355 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
3356 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3357 "vhadd", "u", int_arm_neon_vhaddu, 1>;
3358 // VRHADD : Vector Rounding Halving Add
3359 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
3360 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3361 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
3362 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
3363 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3364 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
3365 // VQADD : Vector Saturating Add
3366 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
3367 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3368 "vqadd", "s", int_arm_neon_vqadds, 1>;
3369 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
3370 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3371 "vqadd", "u", int_arm_neon_vqaddu, 1>;
3372 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
3373 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
3374 int_arm_neon_vaddhn, 1>;
3375 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
3376 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
3377 int_arm_neon_vraddhn, 1>;
3379 // Vector Multiply Operations.
3381 // VMUL : Vector Multiply (integer, polynomial and floating-point)
3382 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
3383 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
3384 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
3385 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
3386 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
3387 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
3388 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
3389 v2f32, v2f32, fmul, 1>;
3390 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
3391 v4f32, v4f32, fmul, 1>;
3392 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
3393 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
3394 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
3397 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
3398 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
3399 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
3400 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3401 (DSubReg_i16_reg imm:$lane))),
3402 (SubReg_i16_lane imm:$lane)))>;
3403 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
3404 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
3405 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
3406 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3407 (DSubReg_i32_reg imm:$lane))),
3408 (SubReg_i32_lane imm:$lane)))>;
3409 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
3410 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
3411 (v4f32 (VMULslfq (v4f32 QPR:$src1),
3412 (v2f32 (EXTRACT_SUBREG QPR:$src2,
3413 (DSubReg_i32_reg imm:$lane))),
3414 (SubReg_i32_lane imm:$lane)))>;
3416 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
3417 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
3418 IIC_VMULi16Q, IIC_VMULi32Q,
3419 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
3420 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
3421 IIC_VMULi16Q, IIC_VMULi32Q,
3422 "vqdmulh", "s", int_arm_neon_vqdmulh>;
3423 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
3424 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3426 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
3427 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3428 (DSubReg_i16_reg imm:$lane))),
3429 (SubReg_i16_lane imm:$lane)))>;
3430 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
3431 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3433 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
3434 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3435 (DSubReg_i32_reg imm:$lane))),
3436 (SubReg_i32_lane imm:$lane)))>;
3438 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
3439 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
3440 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
3441 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
3442 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
3443 IIC_VMULi16Q, IIC_VMULi32Q,
3444 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
3445 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
3446 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3448 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
3449 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3450 (DSubReg_i16_reg imm:$lane))),
3451 (SubReg_i16_lane imm:$lane)))>;
3452 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
3453 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3455 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
3456 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3457 (DSubReg_i32_reg imm:$lane))),
3458 (SubReg_i32_lane imm:$lane)))>;
3460 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
3461 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3462 "vmull", "s", NEONvmulls, 1>;
3463 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3464 "vmull", "u", NEONvmullu, 1>;
3465 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
3466 v8i16, v8i8, int_arm_neon_vmullp, 1>;
3467 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
3468 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
3470 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
3471 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
3472 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
3473 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
3474 "vqdmull", "s", int_arm_neon_vqdmull>;
3476 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
3478 // VMLA : Vector Multiply Accumulate (integer and floating-point)
3479 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3480 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3481 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
3482 v2f32, fmul_su, fadd_mlx>,
3483 Requires<[HasNEON, UseFPVMLx]>;
3484 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
3485 v4f32, fmul_su, fadd_mlx>,
3486 Requires<[HasNEON, UseFPVMLx]>;
3487 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
3488 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3489 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
3490 v2f32, fmul_su, fadd_mlx>,
3491 Requires<[HasNEON, UseFPVMLx]>;
3492 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
3493 v4f32, v2f32, fmul_su, fadd_mlx>,
3494 Requires<[HasNEON, UseFPVMLx]>;
3496 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
3497 (mul (v8i16 QPR:$src2),
3498 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3499 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3500 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3501 (DSubReg_i16_reg imm:$lane))),
3502 (SubReg_i16_lane imm:$lane)))>;
3504 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
3505 (mul (v4i32 QPR:$src2),
3506 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3507 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3508 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3509 (DSubReg_i32_reg imm:$lane))),
3510 (SubReg_i32_lane imm:$lane)))>;
3512 def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1),
3513 (fmul_su (v4f32 QPR:$src2),
3514 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3515 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
3517 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3518 (DSubReg_i32_reg imm:$lane))),
3519 (SubReg_i32_lane imm:$lane)))>,
3520 Requires<[HasNEON, UseFPVMLx]>;
3522 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
3523 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3524 "vmlal", "s", NEONvmulls, add>;
3525 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3526 "vmlal", "u", NEONvmullu, add>;
3528 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
3529 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
3531 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
3532 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3533 "vqdmlal", "s", int_arm_neon_vqdmlal>;
3534 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
3536 // VMLS : Vector Multiply Subtract (integer and floating-point)
3537 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3538 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3539 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
3540 v2f32, fmul_su, fsub_mlx>,
3541 Requires<[HasNEON, UseFPVMLx]>;
3542 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
3543 v4f32, fmul_su, fsub_mlx>,
3544 Requires<[HasNEON, UseFPVMLx]>;
3545 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
3546 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3547 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
3548 v2f32, fmul_su, fsub_mlx>,
3549 Requires<[HasNEON, UseFPVMLx]>;
3550 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
3551 v4f32, v2f32, fmul_su, fsub_mlx>,
3552 Requires<[HasNEON, UseFPVMLx]>;
3554 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
3555 (mul (v8i16 QPR:$src2),
3556 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3557 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3558 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3559 (DSubReg_i16_reg imm:$lane))),
3560 (SubReg_i16_lane imm:$lane)))>;
3562 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
3563 (mul (v4i32 QPR:$src2),
3564 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3565 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3566 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3567 (DSubReg_i32_reg imm:$lane))),
3568 (SubReg_i32_lane imm:$lane)))>;
3570 def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1),
3571 (fmul_su (v4f32 QPR:$src2),
3572 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3573 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
3574 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3575 (DSubReg_i32_reg imm:$lane))),
3576 (SubReg_i32_lane imm:$lane)))>,
3577 Requires<[HasNEON, UseFPVMLx]>;
3579 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
3580 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3581 "vmlsl", "s", NEONvmulls, sub>;
3582 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3583 "vmlsl", "u", NEONvmullu, sub>;
3585 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
3586 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
3588 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
3589 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
3590 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3591 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3593 // Vector Subtract Operations.
3595 // VSUB : Vector Subtract (integer and floating-point)
3596 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
3597 "vsub", "i", sub, 0>;
3598 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
3599 v2f32, v2f32, fsub, 0>;
3600 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
3601 v4f32, v4f32, fsub, 0>;
3602 // VSUBL : Vector Subtract Long (Q = D - D)
3603 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3604 "vsubl", "s", sub, sext, 0>;
3605 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3606 "vsubl", "u", sub, zext, 0>;
3607 // VSUBW : Vector Subtract Wide (Q = Q - D)
3608 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
3609 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
3610 // VHSUB : Vector Halving Subtract
3611 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
3612 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3613 "vhsub", "s", int_arm_neon_vhsubs, 0>;
3614 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
3615 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3616 "vhsub", "u", int_arm_neon_vhsubu, 0>;
3617 // VQSUB : Vector Saturing Subtract
3618 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
3619 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3620 "vqsub", "s", int_arm_neon_vqsubs, 0>;
3621 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
3622 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3623 "vqsub", "u", int_arm_neon_vqsubu, 0>;
3624 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
3625 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
3626 int_arm_neon_vsubhn, 0>;
3627 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
3628 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
3629 int_arm_neon_vrsubhn, 0>;
3631 // Vector Comparisons.
3633 // VCEQ : Vector Compare Equal
3634 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3635 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
3636 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
3638 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
3641 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
3642 "$Vd, $Vm, #0", NEONvceqz>;
3644 // VCGE : Vector Compare Greater Than or Equal
3645 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3646 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
3647 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3648 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
3649 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
3651 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
3654 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
3655 "$Vd, $Vm, #0", NEONvcgez>;
3656 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
3657 "$Vd, $Vm, #0", NEONvclez>;
3659 // VCGT : Vector Compare Greater Than
3660 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3661 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
3662 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3663 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
3664 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
3666 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
3669 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
3670 "$Vd, $Vm, #0", NEONvcgtz>;
3671 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
3672 "$Vd, $Vm, #0", NEONvcltz>;
3674 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
3675 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
3676 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
3677 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
3678 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
3679 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
3680 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
3681 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
3682 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
3683 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
3684 // VTST : Vector Test Bits
3685 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
3686 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
3688 // Vector Bitwise Operations.
3690 def vnotd : PatFrag<(ops node:$in),
3691 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
3692 def vnotq : PatFrag<(ops node:$in),
3693 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
3696 // VAND : Vector Bitwise AND
3697 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
3698 v2i32, v2i32, and, 1>;
3699 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
3700 v4i32, v4i32, and, 1>;
3702 // VEOR : Vector Bitwise Exclusive OR
3703 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
3704 v2i32, v2i32, xor, 1>;
3705 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
3706 v4i32, v4i32, xor, 1>;
3708 // VORR : Vector Bitwise OR
3709 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
3710 v2i32, v2i32, or, 1>;
3711 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
3712 v4i32, v4i32, or, 1>;
3714 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
3715 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3717 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3719 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3720 let Inst{9} = SIMM{9};
3723 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
3724 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3726 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3728 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3729 let Inst{10-9} = SIMM{10-9};
3732 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
3733 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3735 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3737 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3738 let Inst{9} = SIMM{9};
3741 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
3742 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3744 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3746 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3747 let Inst{10-9} = SIMM{10-9};
3751 // VBIC : Vector Bitwise Bit Clear (AND NOT)
3752 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
3753 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
3754 "vbic", "$Vd, $Vn, $Vm", "",
3755 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
3756 (vnotd DPR:$Vm))))]>;
3757 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
3758 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
3759 "vbic", "$Vd, $Vn, $Vm", "",
3760 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
3761 (vnotq QPR:$Vm))))]>;
3763 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
3764 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3766 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3768 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3769 let Inst{9} = SIMM{9};
3772 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
3773 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3775 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3777 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3778 let Inst{10-9} = SIMM{10-9};
3781 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
3782 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3784 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3786 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3787 let Inst{9} = SIMM{9};
3790 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
3791 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3793 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3795 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3796 let Inst{10-9} = SIMM{10-9};
3799 // VORN : Vector Bitwise OR NOT
3800 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
3801 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
3802 "vorn", "$Vd, $Vn, $Vm", "",
3803 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
3804 (vnotd DPR:$Vm))))]>;
3805 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
3806 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
3807 "vorn", "$Vd, $Vn, $Vm", "",
3808 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
3809 (vnotq QPR:$Vm))))]>;
3811 // VMVN : Vector Bitwise NOT (Immediate)
3813 let isReMaterializable = 1 in {
3815 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
3816 (ins nModImm:$SIMM), IIC_VMOVImm,
3817 "vmvn", "i16", "$Vd, $SIMM", "",
3818 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
3819 let Inst{9} = SIMM{9};
3822 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
3823 (ins nModImm:$SIMM), IIC_VMOVImm,
3824 "vmvn", "i16", "$Vd, $SIMM", "",
3825 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
3826 let Inst{9} = SIMM{9};
3829 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
3830 (ins nModImm:$SIMM), IIC_VMOVImm,
3831 "vmvn", "i32", "$Vd, $SIMM", "",
3832 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
3833 let Inst{11-8} = SIMM{11-8};
3836 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
3837 (ins nModImm:$SIMM), IIC_VMOVImm,
3838 "vmvn", "i32", "$Vd, $SIMM", "",
3839 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
3840 let Inst{11-8} = SIMM{11-8};
3844 // VMVN : Vector Bitwise NOT
3845 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
3846 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
3847 "vmvn", "$Vd, $Vm", "",
3848 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
3849 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
3850 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
3851 "vmvn", "$Vd, $Vm", "",
3852 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
3853 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
3854 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
3856 // VBSL : Vector Bitwise Select
3857 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
3858 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3859 N3RegFrm, IIC_VCNTiD,
3860 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3862 (v2i32 (NEONvbsl DPR:$src1, DPR:$Vn, DPR:$Vm)))]>;
3864 def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
3865 (and DPR:$Vm, (vnotd DPR:$Vd)))),
3866 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>;
3868 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
3869 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3870 N3RegFrm, IIC_VCNTiQ,
3871 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3873 (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>;
3875 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
3876 (and QPR:$Vm, (vnotq QPR:$Vd)))),
3877 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
3879 // VBIF : Vector Bitwise Insert if False
3880 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
3881 // FIXME: This instruction's encoding MAY NOT BE correct.
3882 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
3883 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3884 N3RegFrm, IIC_VBINiD,
3885 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3886 [/* For disassembly only; pattern left blank */]>;
3887 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
3888 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3889 N3RegFrm, IIC_VBINiQ,
3890 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3891 [/* For disassembly only; pattern left blank */]>;
3893 // VBIT : Vector Bitwise Insert if True
3894 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
3895 // FIXME: This instruction's encoding MAY NOT BE correct.
3896 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
3897 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3898 N3RegFrm, IIC_VBINiD,
3899 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3900 [/* For disassembly only; pattern left blank */]>;
3901 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
3902 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3903 N3RegFrm, IIC_VBINiQ,
3904 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3905 [/* For disassembly only; pattern left blank */]>;
3907 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
3908 // for equivalent operations with different register constraints; it just
3911 // Vector Absolute Differences.
3913 // VABD : Vector Absolute Difference
3914 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
3915 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3916 "vabd", "s", int_arm_neon_vabds, 1>;
3917 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
3918 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3919 "vabd", "u", int_arm_neon_vabdu, 1>;
3920 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
3921 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
3922 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
3923 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
3925 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
3926 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
3927 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
3928 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
3929 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
3931 // VABA : Vector Absolute Difference and Accumulate
3932 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3933 "vaba", "s", int_arm_neon_vabds, add>;
3934 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3935 "vaba", "u", int_arm_neon_vabdu, add>;
3937 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
3938 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
3939 "vabal", "s", int_arm_neon_vabds, zext, add>;
3940 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
3941 "vabal", "u", int_arm_neon_vabdu, zext, add>;
3943 // Vector Maximum and Minimum.
3945 // VMAX : Vector Maximum
3946 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
3947 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3948 "vmax", "s", int_arm_neon_vmaxs, 1>;
3949 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
3950 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3951 "vmax", "u", int_arm_neon_vmaxu, 1>;
3952 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
3954 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
3955 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
3957 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
3959 // VMIN : Vector Minimum
3960 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
3961 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3962 "vmin", "s", int_arm_neon_vmins, 1>;
3963 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
3964 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3965 "vmin", "u", int_arm_neon_vminu, 1>;
3966 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
3968 v2f32, v2f32, int_arm_neon_vmins, 1>;
3969 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
3971 v4f32, v4f32, int_arm_neon_vmins, 1>;
3973 // Vector Pairwise Operations.
3975 // VPADD : Vector Pairwise Add
3976 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3978 v8i8, v8i8, int_arm_neon_vpadd, 0>;
3979 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3981 v4i16, v4i16, int_arm_neon_vpadd, 0>;
3982 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3984 v2i32, v2i32, int_arm_neon_vpadd, 0>;
3985 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
3986 IIC_VPBIND, "vpadd", "f32",
3987 v2f32, v2f32, int_arm_neon_vpadd, 0>;
3989 // VPADDL : Vector Pairwise Add Long
3990 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
3991 int_arm_neon_vpaddls>;
3992 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
3993 int_arm_neon_vpaddlu>;
3995 // VPADAL : Vector Pairwise Add and Accumulate Long
3996 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
3997 int_arm_neon_vpadals>;
3998 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
3999 int_arm_neon_vpadalu>;
4001 // VPMAX : Vector Pairwise Maximum
4002 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4003 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
4004 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4005 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
4006 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4007 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
4008 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4009 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
4010 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4011 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
4012 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4013 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
4014 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
4015 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
4017 // VPMIN : Vector Pairwise Minimum
4018 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4019 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
4020 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4021 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
4022 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4023 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
4024 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4025 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
4026 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4027 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
4028 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4029 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
4030 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
4031 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
4033 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
4035 // VRECPE : Vector Reciprocal Estimate
4036 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4037 IIC_VUNAD, "vrecpe", "u32",
4038 v2i32, v2i32, int_arm_neon_vrecpe>;
4039 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4040 IIC_VUNAQ, "vrecpe", "u32",
4041 v4i32, v4i32, int_arm_neon_vrecpe>;
4042 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4043 IIC_VUNAD, "vrecpe", "f32",
4044 v2f32, v2f32, int_arm_neon_vrecpe>;
4045 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4046 IIC_VUNAQ, "vrecpe", "f32",
4047 v4f32, v4f32, int_arm_neon_vrecpe>;
4049 // VRECPS : Vector Reciprocal Step
4050 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4051 IIC_VRECSD, "vrecps", "f32",
4052 v2f32, v2f32, int_arm_neon_vrecps, 1>;
4053 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4054 IIC_VRECSQ, "vrecps", "f32",
4055 v4f32, v4f32, int_arm_neon_vrecps, 1>;
4057 // VRSQRTE : Vector Reciprocal Square Root Estimate
4058 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4059 IIC_VUNAD, "vrsqrte", "u32",
4060 v2i32, v2i32, int_arm_neon_vrsqrte>;
4061 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4062 IIC_VUNAQ, "vrsqrte", "u32",
4063 v4i32, v4i32, int_arm_neon_vrsqrte>;
4064 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4065 IIC_VUNAD, "vrsqrte", "f32",
4066 v2f32, v2f32, int_arm_neon_vrsqrte>;
4067 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4068 IIC_VUNAQ, "vrsqrte", "f32",
4069 v4f32, v4f32, int_arm_neon_vrsqrte>;
4071 // VRSQRTS : Vector Reciprocal Square Root Step
4072 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4073 IIC_VRECSD, "vrsqrts", "f32",
4074 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
4075 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4076 IIC_VRECSQ, "vrsqrts", "f32",
4077 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
4081 // VSHL : Vector Shift
4082 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
4083 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4084 "vshl", "s", int_arm_neon_vshifts>;
4085 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
4086 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4087 "vshl", "u", int_arm_neon_vshiftu>;
4089 // VSHL : Vector Shift Left (Immediate)
4090 defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
4092 // VSHR : Vector Shift Right (Immediate)
4093 defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s",NEONvshrs>;
4094 defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u",NEONvshru>;
4096 // VSHLL : Vector Shift Left Long
4097 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
4098 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
4100 // VSHLL : Vector Shift Left Long (with maximum shift count)
4101 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
4102 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
4103 ValueType OpTy, SDNode OpNode>
4104 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
4105 ResTy, OpTy, OpNode> {
4106 let Inst{21-16} = op21_16;
4107 let DecoderMethod = "DecodeVSHLMaxInstruction";
4109 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
4110 v8i16, v8i8, NEONvshlli>;
4111 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
4112 v4i32, v4i16, NEONvshlli>;
4113 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
4114 v2i64, v2i32, NEONvshlli>;
4116 // VSHRN : Vector Shift Right and Narrow
4117 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
4120 // VRSHL : Vector Rounding Shift
4121 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
4122 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4123 "vrshl", "s", int_arm_neon_vrshifts>;
4124 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
4125 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4126 "vrshl", "u", int_arm_neon_vrshiftu>;
4127 // VRSHR : Vector Rounding Shift Right
4128 defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s",NEONvrshrs>;
4129 defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u",NEONvrshru>;
4131 // VRSHRN : Vector Rounding Shift Right and Narrow
4132 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
4135 // VQSHL : Vector Saturating Shift
4136 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
4137 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4138 "vqshl", "s", int_arm_neon_vqshifts>;
4139 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
4140 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4141 "vqshl", "u", int_arm_neon_vqshiftu>;
4142 // VQSHL : Vector Saturating Shift Left (Immediate)
4143 defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls>;
4144 defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu>;
4146 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
4147 defm VQSHLsu : N2VShL_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu>;
4149 // VQSHRN : Vector Saturating Shift Right and Narrow
4150 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
4152 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
4155 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
4156 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
4159 // VQRSHL : Vector Saturating Rounding Shift
4160 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
4161 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4162 "vqrshl", "s", int_arm_neon_vqrshifts>;
4163 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
4164 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4165 "vqrshl", "u", int_arm_neon_vqrshiftu>;
4167 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
4168 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
4170 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
4173 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
4174 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
4177 // VSRA : Vector Shift Right and Accumulate
4178 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
4179 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
4180 // VRSRA : Vector Rounding Shift Right and Accumulate
4181 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
4182 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
4184 // VSLI : Vector Shift Left and Insert
4185 defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">;
4187 // VSRI : Vector Shift Right and Insert
4188 defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;
4190 // Vector Absolute and Saturating Absolute.
4192 // VABS : Vector Absolute Value
4193 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
4194 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
4196 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4197 IIC_VUNAD, "vabs", "f32",
4198 v2f32, v2f32, int_arm_neon_vabs>;
4199 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4200 IIC_VUNAQ, "vabs", "f32",
4201 v4f32, v4f32, int_arm_neon_vabs>;
4203 // VQABS : Vector Saturating Absolute Value
4204 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
4205 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
4206 int_arm_neon_vqabs>;
4210 def vnegd : PatFrag<(ops node:$in),
4211 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
4212 def vnegq : PatFrag<(ops node:$in),
4213 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
4215 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4216 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
4217 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
4218 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
4219 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4220 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
4221 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
4222 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
4224 // VNEG : Vector Negate (integer)
4225 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
4226 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
4227 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
4228 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
4229 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
4230 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
4232 // VNEG : Vector Negate (floating-point)
4233 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
4234 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
4235 "vneg", "f32", "$Vd, $Vm", "",
4236 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
4237 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
4238 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
4239 "vneg", "f32", "$Vd, $Vm", "",
4240 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
4242 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
4243 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
4244 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
4245 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
4246 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
4247 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
4249 // VQNEG : Vector Saturating Negate
4250 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
4251 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
4252 int_arm_neon_vqneg>;
4254 // Vector Bit Counting Operations.
4256 // VCLS : Vector Count Leading Sign Bits
4257 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
4258 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
4260 // VCLZ : Vector Count Leading Zeros
4261 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
4262 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
4264 // VCNT : Vector Count One Bits
4265 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4266 IIC_VCNTiD, "vcnt", "8",
4267 v8i8, v8i8, int_arm_neon_vcnt>;
4268 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4269 IIC_VCNTiQ, "vcnt", "8",
4270 v16i8, v16i8, int_arm_neon_vcnt>;
4272 // Vector Swap -- for disassembly only.
4273 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
4274 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
4275 "vswp", "$Vd, $Vm", "", []>;
4276 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
4277 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
4278 "vswp", "$Vd, $Vm", "", []>;
4280 // Vector Move Operations.
4282 // VMOV : Vector Move (Register)
4283 def : InstAlias<"vmov${p} $Vd, $Vm",
4284 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
4285 def : InstAlias<"vmov${p} $Vd, $Vm",
4286 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
4288 // VMOV : Vector Move (Immediate)
4290 let isReMaterializable = 1 in {
4291 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
4292 (ins nModImm:$SIMM), IIC_VMOVImm,
4293 "vmov", "i8", "$Vd, $SIMM", "",
4294 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
4295 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
4296 (ins nModImm:$SIMM), IIC_VMOVImm,
4297 "vmov", "i8", "$Vd, $SIMM", "",
4298 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
4300 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
4301 (ins nModImm:$SIMM), IIC_VMOVImm,
4302 "vmov", "i16", "$Vd, $SIMM", "",
4303 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
4304 let Inst{9} = SIMM{9};
4307 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
4308 (ins nModImm:$SIMM), IIC_VMOVImm,
4309 "vmov", "i16", "$Vd, $SIMM", "",
4310 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
4311 let Inst{9} = SIMM{9};
4314 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
4315 (ins nModImm:$SIMM), IIC_VMOVImm,
4316 "vmov", "i32", "$Vd, $SIMM", "",
4317 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
4318 let Inst{11-8} = SIMM{11-8};
4321 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
4322 (ins nModImm:$SIMM), IIC_VMOVImm,
4323 "vmov", "i32", "$Vd, $SIMM", "",
4324 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
4325 let Inst{11-8} = SIMM{11-8};
4328 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
4329 (ins nModImm:$SIMM), IIC_VMOVImm,
4330 "vmov", "i64", "$Vd, $SIMM", "",
4331 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
4332 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
4333 (ins nModImm:$SIMM), IIC_VMOVImm,
4334 "vmov", "i64", "$Vd, $SIMM", "",
4335 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
4336 } // isReMaterializable
4338 // VMOV : Vector Get Lane (move scalar to ARM core register)
4340 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
4341 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4342 IIC_VMOVSI, "vmov", "s8", "$R, $V[$lane]",
4343 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
4345 let Inst{21} = lane{2};
4346 let Inst{6-5} = lane{1-0};
4348 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
4349 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4350 IIC_VMOVSI, "vmov", "s16", "$R, $V[$lane]",
4351 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
4353 let Inst{21} = lane{1};
4354 let Inst{6} = lane{0};
4356 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
4357 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4358 IIC_VMOVSI, "vmov", "u8", "$R, $V[$lane]",
4359 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
4361 let Inst{21} = lane{2};
4362 let Inst{6-5} = lane{1-0};
4364 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
4365 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4366 IIC_VMOVSI, "vmov", "u16", "$R, $V[$lane]",
4367 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
4369 let Inst{21} = lane{1};
4370 let Inst{6} = lane{0};
4372 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
4373 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4374 IIC_VMOVSI, "vmov", "32", "$R, $V[$lane]",
4375 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
4377 let Inst{21} = lane{0};
4379 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
4380 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
4381 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4382 (DSubReg_i8_reg imm:$lane))),
4383 (SubReg_i8_lane imm:$lane))>;
4384 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
4385 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4386 (DSubReg_i16_reg imm:$lane))),
4387 (SubReg_i16_lane imm:$lane))>;
4388 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
4389 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4390 (DSubReg_i8_reg imm:$lane))),
4391 (SubReg_i8_lane imm:$lane))>;
4392 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
4393 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4394 (DSubReg_i16_reg imm:$lane))),
4395 (SubReg_i16_lane imm:$lane))>;
4396 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
4397 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
4398 (DSubReg_i32_reg imm:$lane))),
4399 (SubReg_i32_lane imm:$lane))>;
4400 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
4401 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
4402 (SSubReg_f32_reg imm:$src2))>;
4403 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
4404 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
4405 (SSubReg_f32_reg imm:$src2))>;
4406 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
4407 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4408 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
4409 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4412 // VMOV : Vector Set Lane (move ARM core register to scalar)
4414 let Constraints = "$src1 = $V" in {
4415 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
4416 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4417 IIC_VMOVISL, "vmov", "8", "$V[$lane], $R",
4418 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
4419 GPR:$R, imm:$lane))]> {
4420 let Inst{21} = lane{2};
4421 let Inst{6-5} = lane{1-0};
4423 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
4424 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4425 IIC_VMOVISL, "vmov", "16", "$V[$lane], $R",
4426 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
4427 GPR:$R, imm:$lane))]> {
4428 let Inst{21} = lane{1};
4429 let Inst{6} = lane{0};
4431 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
4432 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4433 IIC_VMOVISL, "vmov", "32", "$V[$lane], $R",
4434 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
4435 GPR:$R, imm:$lane))]> {
4436 let Inst{21} = lane{0};
4439 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
4440 (v16i8 (INSERT_SUBREG QPR:$src1,
4441 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
4442 (DSubReg_i8_reg imm:$lane))),
4443 GPR:$src2, (SubReg_i8_lane imm:$lane))),
4444 (DSubReg_i8_reg imm:$lane)))>;
4445 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
4446 (v8i16 (INSERT_SUBREG QPR:$src1,
4447 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
4448 (DSubReg_i16_reg imm:$lane))),
4449 GPR:$src2, (SubReg_i16_lane imm:$lane))),
4450 (DSubReg_i16_reg imm:$lane)))>;
4451 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
4452 (v4i32 (INSERT_SUBREG QPR:$src1,
4453 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
4454 (DSubReg_i32_reg imm:$lane))),
4455 GPR:$src2, (SubReg_i32_lane imm:$lane))),
4456 (DSubReg_i32_reg imm:$lane)))>;
4458 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
4459 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
4460 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4461 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
4462 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
4463 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4465 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4466 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4467 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4468 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4470 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
4471 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4472 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
4473 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
4474 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
4475 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4477 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
4478 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4479 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
4480 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4481 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
4482 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4484 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
4485 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4486 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4488 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
4489 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
4490 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4492 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
4493 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4494 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4497 // VDUP : Vector Duplicate (from ARM core register to all elements)
4499 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4500 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
4501 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4502 [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4503 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4504 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
4505 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4506 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4508 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
4509 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
4510 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
4511 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
4512 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
4513 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
4515 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32d GPR:$R)>;
4516 def : Pat<(v4f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32q GPR:$R)>;
4518 // VDUP : Vector Duplicate Lane (from scalar to all elements)
4520 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
4522 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, nohash_imm:$lane),
4523 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm[$lane]",
4524 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
4526 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
4527 ValueType ResTy, ValueType OpTy>
4528 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, nohash_imm:$lane),
4529 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm[$lane]",
4530 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
4533 // Inst{19-16} is partially specified depending on the element size.
4535 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8> {
4536 let Inst{19-17} = lane{2-0};
4538 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16> {
4539 let Inst{19-18} = lane{1-0};
4541 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32> {
4542 let Inst{19} = lane{0};
4544 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8> {
4545 let Inst{19-17} = lane{2-0};
4547 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16> {
4548 let Inst{19-18} = lane{1-0};
4550 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32> {
4551 let Inst{19} = lane{0};
4554 def : Pat<(v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
4555 (VDUPLN32d DPR:$Vm, imm:$lane)>;
4557 def : Pat<(v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
4558 (VDUPLN32q DPR:$Vm, imm:$lane)>;
4560 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
4561 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
4562 (DSubReg_i8_reg imm:$lane))),
4563 (SubReg_i8_lane imm:$lane)))>;
4564 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
4565 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
4566 (DSubReg_i16_reg imm:$lane))),
4567 (SubReg_i16_lane imm:$lane)))>;
4568 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
4569 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
4570 (DSubReg_i32_reg imm:$lane))),
4571 (SubReg_i32_lane imm:$lane)))>;
4572 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
4573 (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src,
4574 (DSubReg_i32_reg imm:$lane))),
4575 (SubReg_i32_lane imm:$lane)))>;
4577 def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4578 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
4579 def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4580 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
4582 // VMOVN : Vector Narrowing Move
4583 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
4584 "vmovn", "i", trunc>;
4585 // VQMOVN : Vector Saturating Narrowing Move
4586 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
4587 "vqmovn", "s", int_arm_neon_vqmovns>;
4588 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
4589 "vqmovn", "u", int_arm_neon_vqmovnu>;
4590 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
4591 "vqmovun", "s", int_arm_neon_vqmovnsu>;
4592 // VMOVL : Vector Lengthening Move
4593 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
4594 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
4596 // Vector Conversions.
4598 // VCVT : Vector Convert Between Floating-Point and Integers
4599 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4600 v2i32, v2f32, fp_to_sint>;
4601 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4602 v2i32, v2f32, fp_to_uint>;
4603 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4604 v2f32, v2i32, sint_to_fp>;
4605 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4606 v2f32, v2i32, uint_to_fp>;
4608 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4609 v4i32, v4f32, fp_to_sint>;
4610 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4611 v4i32, v4f32, fp_to_uint>;
4612 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4613 v4f32, v4i32, sint_to_fp>;
4614 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4615 v4f32, v4i32, uint_to_fp>;
4617 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
4618 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4619 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
4620 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4621 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
4622 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4623 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
4624 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4625 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
4627 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4628 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
4629 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4630 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
4631 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4632 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
4633 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4634 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
4636 // VCVT : Vector Convert Between Half-Precision and Single-Precision.
4637 def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
4638 IIC_VUNAQ, "vcvt", "f16.f32",
4639 v4i16, v4f32, int_arm_neon_vcvtfp2hf>,
4640 Requires<[HasNEON, HasFP16]>;
4641 def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
4642 IIC_VUNAQ, "vcvt", "f32.f16",
4643 v4f32, v4i16, int_arm_neon_vcvthf2fp>,
4644 Requires<[HasNEON, HasFP16]>;
4648 // VREV64 : Vector Reverse elements within 64-bit doublewords
4650 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4651 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
4652 (ins DPR:$Vm), IIC_VMOVD,
4653 OpcodeStr, Dt, "$Vd, $Vm", "",
4654 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
4655 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4656 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
4657 (ins QPR:$Vm), IIC_VMOVQ,
4658 OpcodeStr, Dt, "$Vd, $Vm", "",
4659 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
4661 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
4662 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
4663 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
4664 def : Pat<(v2f32 (NEONvrev64 (v2f32 DPR:$Vm))), (VREV64d32 DPR:$Vm)>;
4666 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
4667 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
4668 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
4669 def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>;
4671 // VREV32 : Vector Reverse elements within 32-bit words
4673 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4674 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
4675 (ins DPR:$Vm), IIC_VMOVD,
4676 OpcodeStr, Dt, "$Vd, $Vm", "",
4677 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
4678 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4679 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
4680 (ins QPR:$Vm), IIC_VMOVQ,
4681 OpcodeStr, Dt, "$Vd, $Vm", "",
4682 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
4684 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
4685 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
4687 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
4688 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
4690 // VREV16 : Vector Reverse elements within 16-bit halfwords
4692 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4693 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
4694 (ins DPR:$Vm), IIC_VMOVD,
4695 OpcodeStr, Dt, "$Vd, $Vm", "",
4696 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
4697 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4698 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
4699 (ins QPR:$Vm), IIC_VMOVQ,
4700 OpcodeStr, Dt, "$Vd, $Vm", "",
4701 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
4703 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
4704 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
4706 // Other Vector Shuffles.
4708 // Aligned extractions: really just dropping registers
4710 class AlignedVEXTq<ValueType DestTy, ValueType SrcTy, SDNodeXForm LaneCVT>
4711 : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))),
4712 (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>;
4714 def : AlignedVEXTq<v8i8, v16i8, DSubReg_i8_reg>;
4716 def : AlignedVEXTq<v4i16, v8i16, DSubReg_i16_reg>;
4718 def : AlignedVEXTq<v2i32, v4i32, DSubReg_i32_reg>;
4720 def : AlignedVEXTq<v1i64, v2i64, DSubReg_f64_reg>;
4722 def : AlignedVEXTq<v2f32, v4f32, DSubReg_i32_reg>;
4725 // VEXT : Vector Extract
4727 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
4728 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
4729 (ins DPR:$Vn, DPR:$Vm, i32imm:$index), NVExtFrm,
4730 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4731 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
4732 (Ty DPR:$Vm), imm:$index)))]> {
4734 let Inst{11-8} = index{3-0};
4737 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
4738 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
4739 (ins QPR:$Vn, QPR:$Vm, i32imm:$index), NVExtFrm,
4740 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4741 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
4742 (Ty QPR:$Vm), imm:$index)))]> {
4744 let Inst{11-8} = index{3-0};
4747 def VEXTd8 : VEXTd<"vext", "8", v8i8> {
4748 let Inst{11-8} = index{3-0};
4750 def VEXTd16 : VEXTd<"vext", "16", v4i16> {
4751 let Inst{11-9} = index{2-0};
4754 def VEXTd32 : VEXTd<"vext", "32", v2i32> {
4755 let Inst{11-10} = index{1-0};
4756 let Inst{9-8} = 0b00;
4758 def : Pat<(v2f32 (NEONvext (v2f32 DPR:$Vn),
4761 (VEXTd32 DPR:$Vn, DPR:$Vm, imm:$index)>;
4763 def VEXTq8 : VEXTq<"vext", "8", v16i8> {
4764 let Inst{11-8} = index{3-0};
4766 def VEXTq16 : VEXTq<"vext", "16", v8i16> {
4767 let Inst{11-9} = index{2-0};
4770 def VEXTq32 : VEXTq<"vext", "32", v4i32> {
4771 let Inst{11-10} = index{1-0};
4772 let Inst{9-8} = 0b00;
4774 def : Pat<(v4f32 (NEONvext (v4f32 QPR:$Vn),
4777 (VEXTq32 QPR:$Vn, QPR:$Vm, imm:$index)>;
4779 // VTRN : Vector Transpose
4781 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
4782 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
4783 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
4785 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
4786 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
4787 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
4789 // VUZP : Vector Unzip (Deinterleave)
4791 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
4792 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
4793 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
4795 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
4796 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
4797 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
4799 // VZIP : Vector Zip (Interleave)
4801 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
4802 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
4803 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
4805 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
4806 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
4807 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
4809 // Vector Table Lookup and Table Extension.
4811 // VTBL : Vector Table Lookup
4812 let DecoderMethod = "DecodeTBLInstruction" in {
4814 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
4815 (ins DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
4816 "vtbl", "8", "$Vd, \\{$Vn\\}, $Vm", "",
4817 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 DPR:$Vn, DPR:$Vm)))]>;
4818 let hasExtraSrcRegAllocReq = 1 in {
4820 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
4821 (ins DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTB2,
4822 "vtbl", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "", []>;
4824 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
4825 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm), NVTBLFrm, IIC_VTB3,
4826 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm", "", []>;
4828 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
4829 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm),
4831 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm", "", []>;
4832 } // hasExtraSrcRegAllocReq = 1
4835 : PseudoNeonI<(outs DPR:$dst), (ins QPR:$tbl, DPR:$src), IIC_VTB2, "", []>;
4837 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
4839 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
4841 // VTBX : Vector Table Extension
4843 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
4844 (ins DPR:$orig, DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
4845 "vtbx", "8", "$Vd, \\{$Vn\\}, $Vm", "$orig = $Vd",
4846 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
4847 DPR:$orig, DPR:$Vn, DPR:$Vm)))]>;
4848 let hasExtraSrcRegAllocReq = 1 in {
4850 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
4851 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
4852 "vtbx", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "$orig = $Vd", []>;
4854 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
4855 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm),
4856 NVTBLFrm, IIC_VTBX3,
4857 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm",
4860 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd), (ins DPR:$orig, DPR:$Vn,
4861 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
4862 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm",
4864 } // hasExtraSrcRegAllocReq = 1
4867 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QPR:$tbl, DPR:$src),
4868 IIC_VTBX2, "$orig = $dst", []>;
4870 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4871 IIC_VTBX3, "$orig = $dst", []>;
4873 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4874 IIC_VTBX4, "$orig = $dst", []>;
4875 } // DecoderMethod = "DecodeTBLInstruction"
4877 //===----------------------------------------------------------------------===//
4878 // NEON instructions for single-precision FP math
4879 //===----------------------------------------------------------------------===//
4881 class N2VSPat<SDNode OpNode, NeonI Inst>
4882 : NEONFPPat<(f32 (OpNode SPR:$a)),
4884 (v2f32 (COPY_TO_REGCLASS (Inst
4886 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4887 SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>;
4889 class N3VSPat<SDNode OpNode, NeonI Inst>
4890 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
4892 (v2f32 (COPY_TO_REGCLASS (Inst
4894 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4897 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4898 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
4900 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
4901 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
4903 (v2f32 (COPY_TO_REGCLASS (Inst
4905 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4908 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4911 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4912 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
4914 def : N3VSPat<fadd, VADDfd>;
4915 def : N3VSPat<fsub, VSUBfd>;
4916 def : N3VSPat<fmul, VMULfd>;
4917 def : N3VSMulOpPat<fmul, fadd, VMLAfd>,
4918 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
4919 def : N3VSMulOpPat<fmul, fsub, VMLSfd>,
4920 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
4921 def : N2VSPat<fabs, VABSfd>;
4922 def : N2VSPat<fneg, VNEGfd>;
4923 def : N3VSPat<NEONfmax, VMAXfd>;
4924 def : N3VSPat<NEONfmin, VMINfd>;
4925 def : N2VSPat<arm_ftosi, VCVTf2sd>;
4926 def : N2VSPat<arm_ftoui, VCVTf2ud>;
4927 def : N2VSPat<arm_sitof, VCVTs2fd>;
4928 def : N2VSPat<arm_uitof, VCVTu2fd>;
4930 //===----------------------------------------------------------------------===//
4931 // Non-Instruction Patterns
4932 //===----------------------------------------------------------------------===//
4935 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
4936 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
4937 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
4938 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
4939 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
4940 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
4941 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
4942 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
4943 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
4944 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
4945 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
4946 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
4947 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
4948 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
4949 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
4950 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
4951 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
4952 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
4953 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
4954 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
4955 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
4956 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
4957 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
4958 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
4959 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
4960 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
4961 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
4962 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
4963 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
4964 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
4966 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
4967 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
4968 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
4969 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
4970 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
4971 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
4972 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
4973 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
4974 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
4975 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
4976 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
4977 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
4978 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
4979 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
4980 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
4981 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
4982 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
4983 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
4984 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
4985 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
4986 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
4987 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
4988 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
4989 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
4990 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
4991 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
4992 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
4993 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
4994 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
4995 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;