1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
70 // VDUPLANE can produce a quad-register result from a double-register source,
71 // so the result is not constrained to match the source.
72 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
73 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
76 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
77 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
78 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
80 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
81 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
82 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
83 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
85 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
86 SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>]>;
87 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
88 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
89 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
91 //===----------------------------------------------------------------------===//
92 // NEON operand definitions
93 //===----------------------------------------------------------------------===//
95 // addrmode_neonldstm := reg
97 /* TODO: Take advantage of vldm.
98 def addrmode_neonldstm : Operand<i32>,
99 ComplexPattern<i32, 2, "SelectAddrModeNeonLdStM", []> {
100 let PrintMethod = "printAddrNeonLdStMOperand";
101 let MIOperandInfo = (ops GPR, i32imm);
105 def h8imm : Operand<i8> {
106 let PrintMethod = "printHex8ImmOperand";
108 def h16imm : Operand<i16> {
109 let PrintMethod = "printHex16ImmOperand";
111 def h32imm : Operand<i32> {
112 let PrintMethod = "printHex32ImmOperand";
114 def h64imm : Operand<i64> {
115 let PrintMethod = "printHex64ImmOperand";
118 //===----------------------------------------------------------------------===//
119 // NEON load / store instructions
120 //===----------------------------------------------------------------------===//
122 /* TODO: Take advantage of vldm.
123 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
124 def VLDMD : NI<(outs),
125 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
127 "vldm", "${addr:submode} ${addr:base}, $dst1",
129 let Inst{27-25} = 0b110;
131 let Inst{11-9} = 0b101;
134 def VLDMS : NI<(outs),
135 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
137 "vldm", "${addr:submode} ${addr:base}, $dst1",
139 let Inst{27-25} = 0b110;
141 let Inst{11-9} = 0b101;
146 // Use vldmia to load a Q register as a D register pair.
147 def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr),
149 "vldmia", "$addr, ${dst:dregpair}",
150 [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]> {
151 let Inst{27-25} = 0b110;
152 let Inst{24} = 0; // P bit
153 let Inst{23} = 1; // U bit
155 let Inst{11-8} = 0b1011;
158 // Use vstmia to store a Q register as a D register pair.
159 def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr),
161 "vstmia", "$addr, ${src:dregpair}",
162 [(store (v2f64 QPR:$src), addrmode4:$addr)]> {
163 let Inst{27-25} = 0b110;
164 let Inst{24} = 0; // P bit
165 let Inst{23} = 1; // U bit
167 let Inst{11-8} = 0b1011;
170 // VLD1 : Vector Load (multiple single elements)
171 class VLD1D<bits<4> op7_4, string OpcodeStr, string Dt,
172 ValueType Ty, Intrinsic IntOp>
173 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst), (ins addrmode6:$addr), IIC_VLD1,
174 OpcodeStr, Dt, "\\{$dst\\}, $addr", "",
175 [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
176 class VLD1Q<bits<4> op7_4, string OpcodeStr, string Dt,
177 ValueType Ty, Intrinsic IntOp>
178 : NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst), (ins addrmode6:$addr), IIC_VLD1,
179 OpcodeStr, Dt, "${dst:dregpair}, $addr", "",
180 [(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
182 def VLD1d8 : VLD1D<0b0000, "vld1", "8", v8i8, int_arm_neon_vld1>;
183 def VLD1d16 : VLD1D<0b0100, "vld1", "16", v4i16, int_arm_neon_vld1>;
184 def VLD1d32 : VLD1D<0b1000, "vld1", "32", v2i32, int_arm_neon_vld1>;
185 def VLD1df : VLD1D<0b1000, "vld1", "32", v2f32, int_arm_neon_vld1>;
186 def VLD1d64 : VLD1D<0b1100, "vld1", "64", v1i64, int_arm_neon_vld1>;
188 def VLD1q8 : VLD1Q<0b0000, "vld1", "8", v16i8, int_arm_neon_vld1>;
189 def VLD1q16 : VLD1Q<0b0100, "vld1", "16", v8i16, int_arm_neon_vld1>;
190 def VLD1q32 : VLD1Q<0b1000, "vld1", "32", v4i32, int_arm_neon_vld1>;
191 def VLD1qf : VLD1Q<0b1000, "vld1", "32", v4f32, int_arm_neon_vld1>;
192 def VLD1q64 : VLD1Q<0b1100, "vld1", "64", v2i64, int_arm_neon_vld1>;
194 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
196 // VLD2 : Vector Load (multiple 2-element structures)
197 class VLD2D<bits<4> op7_4, string OpcodeStr, string Dt>
198 : NLdSt<0,0b10,0b1000,op7_4, (outs DPR:$dst1, DPR:$dst2),
199 (ins addrmode6:$addr), IIC_VLD2,
200 OpcodeStr, Dt, "\\{$dst1, $dst2\\}, $addr", "", []>;
201 class VLD2Q<bits<4> op7_4, string OpcodeStr, string Dt>
202 : NLdSt<0,0b10,0b0011,op7_4,
203 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
204 (ins addrmode6:$addr), IIC_VLD2,
205 OpcodeStr, Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr",
208 def VLD2d8 : VLD2D<0b0000, "vld2", "8">;
209 def VLD2d16 : VLD2D<0b0100, "vld2", "16">;
210 def VLD2d32 : VLD2D<0b1000, "vld2", "32">;
211 def VLD2d64 : NLdSt<0,0b10,0b1010,0b1100, (outs DPR:$dst1, DPR:$dst2),
212 (ins addrmode6:$addr), IIC_VLD1,
213 "vld1", "64", "\\{$dst1, $dst2\\}, $addr", "", []>;
215 def VLD2q8 : VLD2Q<0b0000, "vld2", "8">;
216 def VLD2q16 : VLD2Q<0b0100, "vld2", "16">;
217 def VLD2q32 : VLD2Q<0b1000, "vld2", "32">;
219 // VLD3 : Vector Load (multiple 3-element structures)
220 class VLD3D<bits<4> op7_4, string OpcodeStr, string Dt>
221 : NLdSt<0,0b10,0b0100,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
222 (ins addrmode6:$addr), IIC_VLD3,
223 OpcodeStr, Dt, "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
224 class VLD3WB<bits<4> op7_4, string OpcodeStr, string Dt>
225 : NLdSt<0,0b10,0b0101,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
226 (ins addrmode6:$addr), IIC_VLD3,
227 OpcodeStr, Dt, "\\{$dst1, $dst2, $dst3\\}, $addr",
228 "$addr.addr = $wb", []>;
230 def VLD3d8 : VLD3D<0b0000, "vld3", "8">;
231 def VLD3d16 : VLD3D<0b0100, "vld3", "16">;
232 def VLD3d32 : VLD3D<0b1000, "vld3", "32">;
233 def VLD3d64 : NLdSt<0,0b10,0b0110,0b1100,
234 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
235 (ins addrmode6:$addr), IIC_VLD1,
236 "vld1", "64", "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
238 // vld3 to double-spaced even registers.
239 def VLD3q8a : VLD3WB<0b0000, "vld3", "8">;
240 def VLD3q16a : VLD3WB<0b0100, "vld3", "16">;
241 def VLD3q32a : VLD3WB<0b1000, "vld3", "32">;
243 // vld3 to double-spaced odd registers.
244 def VLD3q8b : VLD3WB<0b0000, "vld3", "8">;
245 def VLD3q16b : VLD3WB<0b0100, "vld3", "16">;
246 def VLD3q32b : VLD3WB<0b1000, "vld3", "32">;
248 // VLD4 : Vector Load (multiple 4-element structures)
249 class VLD4D<bits<4> op7_4, string OpcodeStr, string Dt>
250 : NLdSt<0,0b10,0b0000,op7_4,
251 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
252 (ins addrmode6:$addr), IIC_VLD4,
253 OpcodeStr, Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr",
255 class VLD4WB<bits<4> op7_4, string OpcodeStr, string Dt>
256 : NLdSt<0,0b10,0b0001,op7_4,
257 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
258 (ins addrmode6:$addr), IIC_VLD4,
259 OpcodeStr, Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr",
260 "$addr.addr = $wb", []>;
262 def VLD4d8 : VLD4D<0b0000, "vld4", "8">;
263 def VLD4d16 : VLD4D<0b0100, "vld4", "16">;
264 def VLD4d32 : VLD4D<0b1000, "vld4", "32">;
265 def VLD4d64 : NLdSt<0,0b10,0b0010,0b1100,
266 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
267 (ins addrmode6:$addr), IIC_VLD1,
268 "vld1", "64", "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr",
271 // vld4 to double-spaced even registers.
272 def VLD4q8a : VLD4WB<0b0000, "vld4", "8">;
273 def VLD4q16a : VLD4WB<0b0100, "vld4", "16">;
274 def VLD4q32a : VLD4WB<0b1000, "vld4", "32">;
276 // vld4 to double-spaced odd registers.
277 def VLD4q8b : VLD4WB<0b0000, "vld4", "8">;
278 def VLD4q16b : VLD4WB<0b0100, "vld4", "16">;
279 def VLD4q32b : VLD4WB<0b1000, "vld4", "32">;
281 // VLD1LN : Vector Load (single element to one lane)
282 // FIXME: Not yet implemented.
284 // VLD2LN : Vector Load (single 2-element structure to one lane)
285 class VLD2LN<bits<4> op11_8, string OpcodeStr, string Dt>
286 : NLdSt<1,0b10,op11_8,{?,?,?,?}, (outs DPR:$dst1, DPR:$dst2),
287 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
289 OpcodeStr, Dt, "\\{$dst1[$lane], $dst2[$lane]\\}, $addr",
290 "$src1 = $dst1, $src2 = $dst2", []>;
292 // vld2 to single-spaced registers.
293 def VLD2LNd8 : VLD2LN<0b0001, "vld2", "8">;
294 def VLD2LNd16 : VLD2LN<0b0101, "vld2", "16"> {
297 def VLD2LNd32 : VLD2LN<0b1001, "vld2", "32"> {
301 // vld2 to double-spaced even registers.
302 def VLD2LNq16a: VLD2LN<0b0101, "vld2", "16"> {
305 def VLD2LNq32a: VLD2LN<0b1001, "vld2", "32"> {
309 // vld2 to double-spaced odd registers.
310 def VLD2LNq16b: VLD2LN<0b0101, "vld2", "16"> {
313 def VLD2LNq32b: VLD2LN<0b1001, "vld2", "32"> {
317 // VLD3LN : Vector Load (single 3-element structure to one lane)
318 class VLD3LN<bits<4> op11_8, string OpcodeStr, string Dt>
319 : NLdSt<1,0b10,op11_8,{?,?,?,?}, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
320 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
321 nohash_imm:$lane), IIC_VLD3,
323 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr",
324 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
326 // vld3 to single-spaced registers.
327 def VLD3LNd8 : VLD3LN<0b0010, "vld3", "8"> {
330 def VLD3LNd16 : VLD3LN<0b0110, "vld3", "16"> {
331 let Inst{5-4} = 0b00;
333 def VLD3LNd32 : VLD3LN<0b1010, "vld3", "32"> {
334 let Inst{6-4} = 0b000;
337 // vld3 to double-spaced even registers.
338 def VLD3LNq16a: VLD3LN<0b0110, "vld3", "16"> {
339 let Inst{5-4} = 0b10;
341 def VLD3LNq32a: VLD3LN<0b1010, "vld3", "32"> {
342 let Inst{6-4} = 0b100;
345 // vld3 to double-spaced odd registers.
346 def VLD3LNq16b: VLD3LN<0b0110, "vld3", "16"> {
347 let Inst{5-4} = 0b10;
349 def VLD3LNq32b: VLD3LN<0b1010, "vld3", "32"> {
350 let Inst{6-4} = 0b100;
353 // VLD4LN : Vector Load (single 4-element structure to one lane)
354 class VLD4LN<bits<4> op11_8, string OpcodeStr, string Dt>
355 : NLdSt<1,0b10,op11_8,{?,?,?,?},
356 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
357 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
358 nohash_imm:$lane), IIC_VLD4,
360 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr",
361 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
363 // vld4 to single-spaced registers.
364 def VLD4LNd8 : VLD4LN<0b0011, "vld4", "8">;
365 def VLD4LNd16 : VLD4LN<0b0111, "vld4", "16"> {
368 def VLD4LNd32 : VLD4LN<0b1011, "vld4", "32"> {
372 // vld4 to double-spaced even registers.
373 def VLD4LNq16a: VLD4LN<0b0111, "vld4", "16"> {
376 def VLD4LNq32a: VLD4LN<0b1011, "vld4", "32"> {
380 // vld4 to double-spaced odd registers.
381 def VLD4LNq16b: VLD4LN<0b0111, "vld4", "16"> {
384 def VLD4LNq32b: VLD4LN<0b1011, "vld4", "32"> {
388 // VLD1DUP : Vector Load (single element to all lanes)
389 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
390 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
391 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
392 // FIXME: Not yet implemented.
393 } // mayLoad = 1, hasExtraDefRegAllocReq = 1
395 // VST1 : Vector Store (multiple single elements)
396 class VST1D<bits<4> op7_4, string OpcodeStr, string Dt,
397 ValueType Ty, Intrinsic IntOp>
398 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src), IIC_VST,
399 OpcodeStr, Dt, "\\{$src\\}, $addr", "",
400 [(IntOp addrmode6:$addr, (Ty DPR:$src))]>;
401 class VST1Q<bits<4> op7_4, string OpcodeStr, string Dt,
402 ValueType Ty, Intrinsic IntOp>
403 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$addr, QPR:$src), IIC_VST,
404 OpcodeStr, Dt, "${src:dregpair}, $addr", "",
405 [(IntOp addrmode6:$addr, (Ty QPR:$src))]>;
407 let hasExtraSrcRegAllocReq = 1 in {
408 def VST1d8 : VST1D<0b0000, "vst1", "8", v8i8, int_arm_neon_vst1>;
409 def VST1d16 : VST1D<0b0100, "vst1", "16", v4i16, int_arm_neon_vst1>;
410 def VST1d32 : VST1D<0b1000, "vst1", "32", v2i32, int_arm_neon_vst1>;
411 def VST1df : VST1D<0b1000, "vst1", "32", v2f32, int_arm_neon_vst1>;
412 def VST1d64 : VST1D<0b1100, "vst1", "64", v1i64, int_arm_neon_vst1>;
414 def VST1q8 : VST1Q<0b0000, "vst1", "8", v16i8, int_arm_neon_vst1>;
415 def VST1q16 : VST1Q<0b0100, "vst1", "16", v8i16, int_arm_neon_vst1>;
416 def VST1q32 : VST1Q<0b1000, "vst1", "32", v4i32, int_arm_neon_vst1>;
417 def VST1qf : VST1Q<0b1000, "vst1", "32", v4f32, int_arm_neon_vst1>;
418 def VST1q64 : VST1Q<0b1100, "vst1", "64", v2i64, int_arm_neon_vst1>;
419 } // hasExtraSrcRegAllocReq
421 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
423 // VST2 : Vector Store (multiple 2-element structures)
424 class VST2D<bits<4> op7_4, string OpcodeStr, string Dt>
425 : NLdSt<0,0b00,0b1000,op7_4, (outs),
426 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
427 OpcodeStr, Dt, "\\{$src1, $src2\\}, $addr", "", []>;
428 class VST2Q<bits<4> op7_4, string OpcodeStr, string Dt>
429 : NLdSt<0,0b00,0b0011,op7_4, (outs),
430 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
432 OpcodeStr, Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
435 def VST2d8 : VST2D<0b0000, "vst2", "8">;
436 def VST2d16 : VST2D<0b0100, "vst2", "16">;
437 def VST2d32 : VST2D<0b1000, "vst2", "32">;
438 def VST2d64 : NLdSt<0,0b00,0b1010,0b1100, (outs),
439 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
440 "vst1", "64", "\\{$src1, $src2\\}, $addr", "", []>;
442 def VST2q8 : VST2Q<0b0000, "vst2", "8">;
443 def VST2q16 : VST2Q<0b0100, "vst2", "16">;
444 def VST2q32 : VST2Q<0b1000, "vst2", "32">;
446 // VST3 : Vector Store (multiple 3-element structures)
447 class VST3D<bits<4> op7_4, string OpcodeStr, string Dt>
448 : NLdSt<0,0b00,0b0100,op7_4, (outs),
449 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
450 OpcodeStr, Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>;
451 class VST3WB<bits<4> op7_4, string OpcodeStr, string Dt>
452 : NLdSt<0,0b00,0b0101,op7_4, (outs GPR:$wb),
453 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
454 OpcodeStr, Dt, "\\{$src1, $src2, $src3\\}, $addr",
455 "$addr.addr = $wb", []>;
457 def VST3d8 : VST3D<0b0000, "vst3", "8">;
458 def VST3d16 : VST3D<0b0100, "vst3", "16">;
459 def VST3d32 : VST3D<0b1000, "vst3", "32">;
460 def VST3d64 : NLdSt<0,0b00,0b0110,0b1100, (outs),
461 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
463 "vst1", "64", "\\{$src1, $src2, $src3\\}, $addr", "", []>;
465 // vst3 to double-spaced even registers.
466 def VST3q8a : VST3WB<0b0000, "vst3", "8">;
467 def VST3q16a : VST3WB<0b0100, "vst3", "16">;
468 def VST3q32a : VST3WB<0b1000, "vst3", "32">;
470 // vst3 to double-spaced odd registers.
471 def VST3q8b : VST3WB<0b0000, "vst3", "8">;
472 def VST3q16b : VST3WB<0b0100, "vst3", "16">;
473 def VST3q32b : VST3WB<0b1000, "vst3", "32">;
475 // VST4 : Vector Store (multiple 4-element structures)
476 class VST4D<bits<4> op7_4, string OpcodeStr, string Dt>
477 : NLdSt<0,0b00,0b0000,op7_4, (outs),
478 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
480 OpcodeStr, Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
482 class VST4WB<bits<4> op7_4, string OpcodeStr, string Dt>
483 : NLdSt<0,0b00,0b0001,op7_4, (outs GPR:$wb),
484 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
486 OpcodeStr, Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
487 "$addr.addr = $wb", []>;
489 def VST4d8 : VST4D<0b0000, "vst4", "8">;
490 def VST4d16 : VST4D<0b0100, "vst4", "16">;
491 def VST4d32 : VST4D<0b1000, "vst4", "32">;
492 def VST4d64 : NLdSt<0,0b00,0b0010,0b1100, (outs),
493 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
495 "vst1", "64", "\\{$src1, $src2, $src3, $src4\\}, $addr",
498 // vst4 to double-spaced even registers.
499 def VST4q8a : VST4WB<0b0000, "vst4", "8">;
500 def VST4q16a : VST4WB<0b0100, "vst4", "16">;
501 def VST4q32a : VST4WB<0b1000, "vst4", "32">;
503 // vst4 to double-spaced odd registers.
504 def VST4q8b : VST4WB<0b0000, "vst4", "8">;
505 def VST4q16b : VST4WB<0b0100, "vst4", "16">;
506 def VST4q32b : VST4WB<0b1000, "vst4", "32">;
508 // VST1LN : Vector Store (single element from one lane)
509 // FIXME: Not yet implemented.
511 // VST2LN : Vector Store (single 2-element structure from one lane)
512 class VST2LN<bits<4> op11_8, string OpcodeStr, string Dt>
513 : NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs),
514 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
516 OpcodeStr, Dt, "\\{$src1[$lane], $src2[$lane]\\}, $addr",
519 // vst2 to single-spaced registers.
520 def VST2LNd8 : VST2LN<0b0001, "vst2", "8">;
521 def VST2LNd16 : VST2LN<0b0101, "vst2", "16"> {
524 def VST2LNd32 : VST2LN<0b1001, "vst2", "32"> {
528 // vst2 to double-spaced even registers.
529 def VST2LNq16a: VST2LN<0b0101, "vst2", "16"> {
532 def VST2LNq32a: VST2LN<0b1001, "vst2", "32"> {
536 // vst2 to double-spaced odd registers.
537 def VST2LNq16b: VST2LN<0b0101, "vst2", "16"> {
540 def VST2LNq32b: VST2LN<0b1001, "vst2", "32"> {
544 // VST3LN : Vector Store (single 3-element structure from one lane)
545 class VST3LN<bits<4> op11_8, string OpcodeStr, string Dt>
546 : NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs),
547 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
548 nohash_imm:$lane), IIC_VST,
550 "\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr", "", []>;
552 // vst3 to single-spaced registers.
553 def VST3LNd8 : VST3LN<0b0010, "vst3", "8"> {
556 def VST3LNd16 : VST3LN<0b0110, "vst3", "16"> {
557 let Inst{5-4} = 0b00;
559 def VST3LNd32 : VST3LN<0b1010, "vst3", "32"> {
560 let Inst{6-4} = 0b000;
563 // vst3 to double-spaced even registers.
564 def VST3LNq16a: VST3LN<0b0110, "vst3", "16"> {
565 let Inst{5-4} = 0b10;
567 def VST3LNq32a: VST3LN<0b1010, "vst3", "32"> {
568 let Inst{6-4} = 0b100;
571 // vst3 to double-spaced odd registers.
572 def VST3LNq16b: VST3LN<0b0110, "vst3", "16"> {
573 let Inst{5-4} = 0b10;
575 def VST3LNq32b: VST3LN<0b1010, "vst3", "32"> {
576 let Inst{6-4} = 0b100;
579 // VST4LN : Vector Store (single 4-element structure from one lane)
580 class VST4LN<bits<4> op11_8, string OpcodeStr, string Dt>
581 : NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs),
582 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
583 nohash_imm:$lane), IIC_VST,
585 "\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr",
588 // vst4 to single-spaced registers.
589 def VST4LNd8 : VST4LN<0b0011, "vst4", "8">;
590 def VST4LNd16 : VST4LN<0b0111, "vst4", "16"> {
593 def VST4LNd32 : VST4LN<0b1011, "vst4", "32"> {
597 // vst4 to double-spaced even registers.
598 def VST4LNq16a: VST4LN<0b0111, "vst4", "16"> {
601 def VST4LNq32a: VST4LN<0b1011, "vst4", "32"> {
605 // vst4 to double-spaced odd registers.
606 def VST4LNq16b: VST4LN<0b0111, "vst4", "16"> {
609 def VST4LNq32b: VST4LN<0b1011, "vst4", "32"> {
613 } // mayStore = 1, hasExtraSrcRegAllocReq = 1
616 //===----------------------------------------------------------------------===//
617 // NEON pattern fragments
618 //===----------------------------------------------------------------------===//
620 // Extract D sub-registers of Q registers.
621 // (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
622 def DSubReg_i8_reg : SDNodeXForm<imm, [{
623 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
625 def DSubReg_i16_reg : SDNodeXForm<imm, [{
626 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
628 def DSubReg_i32_reg : SDNodeXForm<imm, [{
629 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
631 def DSubReg_f64_reg : SDNodeXForm<imm, [{
632 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
634 def DSubReg_f64_other_reg : SDNodeXForm<imm, [{
635 return CurDAG->getTargetConstant(5 + (1 - N->getZExtValue()), MVT::i32);
638 // Extract S sub-registers of Q/D registers.
639 // (arm_ssubreg_0 is 1; arm_ssubreg_1 is 2; etc.)
640 def SSubReg_f32_reg : SDNodeXForm<imm, [{
641 return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32);
644 // Translate lane numbers from Q registers to D subregs.
645 def SubReg_i8_lane : SDNodeXForm<imm, [{
646 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
648 def SubReg_i16_lane : SDNodeXForm<imm, [{
649 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
651 def SubReg_i32_lane : SDNodeXForm<imm, [{
652 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
655 //===----------------------------------------------------------------------===//
656 // Instruction Classes
657 //===----------------------------------------------------------------------===//
659 // Basic 2-register operations, both double- and quad-register.
660 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
661 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,string Dt,
662 ValueType ResTy, ValueType OpTy, SDNode OpNode>
663 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
664 (ins DPR:$src), IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "",
665 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
666 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
667 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,string Dt,
668 ValueType ResTy, ValueType OpTy, SDNode OpNode>
669 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
670 (ins QPR:$src), IIC_VUNAQ, OpcodeStr, Dt, "$dst, $src", "",
671 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
673 // Basic 2-register operations, scalar single-precision.
674 class N2VDs<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
675 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,string Dt,
676 ValueType ResTy, ValueType OpTy, SDNode OpNode>
677 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
678 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
679 IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
681 class N2VDsPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
682 : NEONFPPat<(ResTy (OpNode SPR:$a)),
684 (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
687 // Basic 2-register intrinsics, both double- and quad-register.
688 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
689 bits<2> op17_16, bits<5> op11_7, bit op4,
690 InstrItinClass itin, string OpcodeStr, string Dt,
691 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
692 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
693 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
694 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
695 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
696 bits<2> op17_16, bits<5> op11_7, bit op4,
697 InstrItinClass itin, string OpcodeStr, string Dt,
698 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
699 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
700 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
701 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
703 // Basic 2-register intrinsics, scalar single-precision
704 class N2VDInts<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
705 bits<2> op17_16, bits<5> op11_7, bit op4,
706 InstrItinClass itin, string OpcodeStr, string Dt,
707 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
708 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
709 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), itin,
710 OpcodeStr, Dt, "$dst, $src", "", []>;
712 class N2VDIntsPat<SDNode OpNode, NeonI Inst>
713 : NEONFPPat<(f32 (OpNode SPR:$a)),
715 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
718 // Narrow 2-register intrinsics.
719 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
720 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
721 InstrItinClass itin, string OpcodeStr, string Dt,
722 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
723 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
724 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
725 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
727 // Long 2-register intrinsics (currently only used for VMOVL).
728 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
729 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
730 InstrItinClass itin, string OpcodeStr, string Dt,
731 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
732 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$dst),
733 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
734 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
736 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
737 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
738 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
739 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
740 OpcodeStr, Dt, "$dst1, $dst2",
741 "$src1 = $dst1, $src2 = $dst2", []>;
742 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
743 InstrItinClass itin, string OpcodeStr, string Dt>
744 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
745 (ins QPR:$src1, QPR:$src2), itin,
746 OpcodeStr, Dt, "$dst1, $dst2",
747 "$src1 = $dst1, $src2 = $dst2", []>;
749 // Basic 3-register operations, both double- and quad-register.
750 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
751 InstrItinClass itin, string OpcodeStr, string Dt,
752 ValueType ResTy, ValueType OpTy,
753 SDNode OpNode, bit Commutable>
754 : N3V<op24, op23, op21_20, op11_8, 0, op4,
755 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
756 OpcodeStr, Dt, "$dst, $src1, $src2", "",
757 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
758 let isCommutable = Commutable;
760 // Same as N3VD but no data type.
761 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
762 InstrItinClass itin, string OpcodeStr,
763 ValueType ResTy, ValueType OpTy,
764 SDNode OpNode, bit Commutable>
765 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
766 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
767 OpcodeStr, "$dst, $src1, $src2", "",
768 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
769 let isCommutable = Commutable;
771 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
772 InstrItinClass itin, string OpcodeStr, string Dt,
773 ValueType Ty, SDNode ShOp>
774 : N3V<0, 1, op21_20, op11_8, 1, 0,
775 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
776 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
778 (Ty (ShOp (Ty DPR:$src1),
779 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
781 let isCommutable = 0;
783 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
784 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
785 : N3V<0, 1, op21_20, op11_8, 1, 0,
786 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
788 OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
790 (Ty (ShOp (Ty DPR:$src1),
791 (Ty (NEONvduplane (Ty DPR_8:$src2),
793 let isCommutable = 0;
796 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
797 InstrItinClass itin, string OpcodeStr, string Dt,
798 ValueType ResTy, ValueType OpTy,
799 SDNode OpNode, bit Commutable>
800 : N3V<op24, op23, op21_20, op11_8, 1, op4,
801 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
802 OpcodeStr, Dt, "$dst, $src1, $src2", "",
803 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
804 let isCommutable = Commutable;
806 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
807 InstrItinClass itin, string OpcodeStr,
808 ValueType ResTy, ValueType OpTy,
809 SDNode OpNode, bit Commutable>
810 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
811 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
812 OpcodeStr, "$dst, $src1, $src2", "",
813 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
814 let isCommutable = Commutable;
816 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
817 InstrItinClass itin, string OpcodeStr, string Dt,
818 ValueType ResTy, ValueType OpTy, SDNode ShOp>
819 : N3V<1, 1, op21_20, op11_8, 1, 0,
820 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
821 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
822 [(set (ResTy QPR:$dst),
823 (ResTy (ShOp (ResTy QPR:$src1),
824 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
826 let isCommutable = 0;
828 class N3VQSL16<bits<2> op21_20, bits<4> op11_8,
829 string OpcodeStr, string Dt,
830 ValueType ResTy, ValueType OpTy, SDNode ShOp>
831 : N3V<1, 1, op21_20, op11_8, 1, 0,
832 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
834 OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
835 [(set (ResTy QPR:$dst),
836 (ResTy (ShOp (ResTy QPR:$src1),
837 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
839 let isCommutable = 0;
842 // Basic 3-register operations, scalar single-precision
843 class N3VDs<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
844 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
845 SDNode OpNode, bit Commutable>
846 : N3V<op24, op23, op21_20, op11_8, 0, op4,
847 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), IIC_VBIND,
848 OpcodeStr, Dt, "$dst, $src1, $src2", "", []> {
849 let isCommutable = Commutable;
851 class N3VDsPat<SDNode OpNode, NeonI Inst>
852 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
854 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
855 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
858 // Basic 3-register intrinsics, both double- and quad-register.
859 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
860 InstrItinClass itin, string OpcodeStr, string Dt,
861 ValueType ResTy, ValueType OpTy,
862 Intrinsic IntOp, bit Commutable>
863 : N3V<op24, op23, op21_20, op11_8, 0, op4,
864 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
865 OpcodeStr, Dt, "$dst, $src1, $src2", "",
866 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
867 let isCommutable = Commutable;
869 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
870 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
871 : N3V<0, 1, op21_20, op11_8, 1, 0,
872 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
873 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
875 (Ty (IntOp (Ty DPR:$src1),
876 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
878 let isCommutable = 0;
880 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
881 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
882 : N3V<0, 1, op21_20, op11_8, 1, 0,
883 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
884 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
886 (Ty (IntOp (Ty DPR:$src1),
887 (Ty (NEONvduplane (Ty DPR_8:$src2),
889 let isCommutable = 0;
892 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
893 InstrItinClass itin, string OpcodeStr, string Dt,
894 ValueType ResTy, ValueType OpTy,
895 Intrinsic IntOp, bit Commutable>
896 : N3V<op24, op23, op21_20, op11_8, 1, op4,
897 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
898 OpcodeStr, Dt, "$dst, $src1, $src2", "",
899 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
900 let isCommutable = Commutable;
902 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
903 string OpcodeStr, string Dt,
904 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
905 : N3V<1, 1, op21_20, op11_8, 1, 0,
906 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
907 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
908 [(set (ResTy QPR:$dst),
909 (ResTy (IntOp (ResTy QPR:$src1),
910 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
912 let isCommutable = 0;
914 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
915 string OpcodeStr, string Dt,
916 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
917 : N3V<1, 1, op21_20, op11_8, 1, 0,
918 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
919 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
920 [(set (ResTy QPR:$dst),
921 (ResTy (IntOp (ResTy QPR:$src1),
922 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
924 let isCommutable = 0;
927 // Multiply-Add/Sub operations, both double- and quad-register.
928 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
929 InstrItinClass itin, string OpcodeStr, string Dt,
930 ValueType Ty, SDNode MulOp, SDNode OpNode>
931 : N3V<op24, op23, op21_20, op11_8, 0, op4,
932 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin,
933 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
934 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
935 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
936 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
937 string OpcodeStr, string Dt,
938 ValueType Ty, SDNode MulOp, SDNode ShOp>
939 : N3V<0, 1, op21_20, op11_8, 1, 0,
941 (ins DPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
942 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
944 (Ty (ShOp (Ty DPR:$src1),
945 (Ty (MulOp DPR:$src2,
946 (Ty (NEONvduplane (Ty DPR_VFP2:$src3),
948 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
949 string OpcodeStr, string Dt,
950 ValueType Ty, SDNode MulOp, SDNode ShOp>
951 : N3V<0, 1, op21_20, op11_8, 1, 0,
953 (ins DPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
954 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
956 (Ty (ShOp (Ty DPR:$src1),
957 (Ty (MulOp DPR:$src2,
958 (Ty (NEONvduplane (Ty DPR_8:$src3),
961 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
962 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
963 SDNode MulOp, SDNode OpNode>
964 : N3V<op24, op23, op21_20, op11_8, 1, op4,
965 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin,
966 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
967 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
968 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
969 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
970 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
971 SDNode MulOp, SDNode ShOp>
972 : N3V<1, 1, op21_20, op11_8, 1, 0,
974 (ins QPR:$src1, QPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
975 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
976 [(set (ResTy QPR:$dst),
977 (ResTy (ShOp (ResTy QPR:$src1),
978 (ResTy (MulOp QPR:$src2,
979 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src3),
981 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
982 string OpcodeStr, string Dt,
983 ValueType ResTy, ValueType OpTy,
984 SDNode MulOp, SDNode ShOp>
985 : N3V<1, 1, op21_20, op11_8, 1, 0,
987 (ins QPR:$src1, QPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
988 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
989 [(set (ResTy QPR:$dst),
990 (ResTy (ShOp (ResTy QPR:$src1),
991 (ResTy (MulOp QPR:$src2,
992 (ResTy (NEONvduplane (OpTy DPR_8:$src3),
995 // Multiply-Add/Sub operations, scalar single-precision
996 class N3VDMulOps<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
997 InstrItinClass itin, string OpcodeStr, string Dt,
998 ValueType Ty, SDNode MulOp, SDNode OpNode>
999 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1000 (outs DPR_VFP2:$dst),
1001 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), itin,
1002 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst", []>;
1004 class N3VDMulOpsPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
1005 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
1007 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$acc, arm_ssubreg_0),
1008 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
1009 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
1012 // Neon 3-argument intrinsics, both double- and quad-register.
1013 // The destination register is also used as the first source operand register.
1014 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1015 InstrItinClass itin, string OpcodeStr, string Dt,
1016 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1017 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1018 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin,
1019 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1020 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
1021 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
1022 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1023 InstrItinClass itin, string OpcodeStr, string Dt,
1024 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1025 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1026 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin,
1027 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1028 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
1029 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
1031 // Neon Long 3-argument intrinsic. The destination register is
1032 // a quad-register and is also used as the first source operand register.
1033 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1034 InstrItinClass itin, string OpcodeStr, string Dt,
1035 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
1036 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1037 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), itin,
1038 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1040 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
1041 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1042 string OpcodeStr, string Dt,
1043 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1044 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1046 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
1047 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1048 [(set (ResTy QPR:$dst),
1049 (ResTy (IntOp (ResTy QPR:$src1),
1051 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src3),
1053 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1054 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1056 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1058 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
1059 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1060 [(set (ResTy QPR:$dst),
1061 (ResTy (IntOp (ResTy QPR:$src1),
1063 (OpTy (NEONvduplane (OpTy DPR_8:$src3),
1067 // Narrowing 3-register intrinsics.
1068 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1069 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
1070 Intrinsic IntOp, bit Commutable>
1071 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1072 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VBINi4D,
1073 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1074 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
1075 let isCommutable = Commutable;
1078 // Long 3-register intrinsics.
1079 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1080 InstrItinClass itin, string OpcodeStr, string Dt,
1081 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
1082 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1083 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
1084 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1085 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
1086 let isCommutable = Commutable;
1088 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1089 string OpcodeStr, string Dt,
1090 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1091 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1092 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1093 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1094 [(set (ResTy QPR:$dst),
1095 (ResTy (IntOp (OpTy DPR:$src1),
1096 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1098 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1099 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1101 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1102 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1103 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1104 [(set (ResTy QPR:$dst),
1105 (ResTy (IntOp (OpTy DPR:$src1),
1106 (OpTy (NEONvduplane (OpTy DPR_8:$src2),
1109 // Wide 3-register intrinsics.
1110 class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1111 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
1112 Intrinsic IntOp, bit Commutable>
1113 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1114 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), IIC_VSUBiD,
1115 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1116 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
1117 let isCommutable = Commutable;
1120 // Pairwise long 2-register intrinsics, both double- and quad-register.
1121 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1122 bits<2> op17_16, bits<5> op11_7, bit op4,
1123 string OpcodeStr, string Dt,
1124 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1125 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1126 (ins DPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
1127 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
1128 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1129 bits<2> op17_16, bits<5> op11_7, bit op4,
1130 string OpcodeStr, string Dt,
1131 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1132 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1133 (ins QPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
1134 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
1136 // Pairwise long 2-register accumulate intrinsics,
1137 // both double- and quad-register.
1138 // The destination register is also used as the first source operand register.
1139 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1140 bits<2> op17_16, bits<5> op11_7, bit op4,
1141 string OpcodeStr, string Dt,
1142 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1143 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
1144 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), IIC_VPALiD,
1145 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
1146 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
1147 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1148 bits<2> op17_16, bits<5> op11_7, bit op4,
1149 string OpcodeStr, string Dt,
1150 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1151 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
1152 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VPALiQ,
1153 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
1154 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
1156 // Shift by immediate,
1157 // both double- and quad-register.
1158 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1159 InstrItinClass itin, string OpcodeStr, string Dt,
1160 ValueType Ty, SDNode OpNode>
1161 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1162 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), itin,
1163 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1164 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
1165 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1166 InstrItinClass itin, string OpcodeStr, string Dt,
1167 ValueType Ty, SDNode OpNode>
1168 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1169 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin,
1170 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1171 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
1173 // Long shift by immediate.
1174 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1175 string OpcodeStr, string Dt,
1176 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1177 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1178 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VSHLiD,
1179 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1180 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
1181 (i32 imm:$SIMM))))]>;
1183 // Narrow shift by immediate.
1184 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1185 InstrItinClass itin, string OpcodeStr, string Dt,
1186 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1187 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1188 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin,
1189 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1190 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
1191 (i32 imm:$SIMM))))]>;
1193 // Shift right by immediate and accumulate,
1194 // both double- and quad-register.
1195 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1196 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1197 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1198 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), IIC_VPALiD,
1199 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1200 [(set DPR:$dst, (Ty (add DPR:$src1,
1201 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
1202 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1203 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1204 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1205 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), IIC_VPALiD,
1206 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1207 [(set QPR:$dst, (Ty (add QPR:$src1,
1208 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
1210 // Shift by immediate and insert,
1211 // both double- and quad-register.
1212 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1213 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1214 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1215 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), IIC_VSHLiD,
1216 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1217 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
1218 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1219 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1220 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1221 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), IIC_VSHLiQ,
1222 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1223 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
1225 // Convert, with fractional bits immediate,
1226 // both double- and quad-register.
1227 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1228 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1230 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1231 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VUNAD,
1232 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1233 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
1234 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1235 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1237 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1238 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), IIC_VUNAQ,
1239 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1240 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
1242 //===----------------------------------------------------------------------===//
1244 //===----------------------------------------------------------------------===//
1246 // Abbreviations used in multiclass suffixes:
1247 // Q = quarter int (8 bit) elements
1248 // H = half int (16 bit) elements
1249 // S = single int (32 bit) elements
1250 // D = double int (64 bit) elements
1252 // Neon 3-register vector operations.
1254 // First with only element sizes of 8, 16 and 32 bits:
1255 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1256 InstrItinClass itinD16, InstrItinClass itinD32,
1257 InstrItinClass itinQ16, InstrItinClass itinQ32,
1258 string OpcodeStr, string Dt,
1259 SDNode OpNode, bit Commutable = 0> {
1260 // 64-bit vector types.
1261 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
1262 OpcodeStr, !strconcat(Dt, "8"),
1263 v8i8, v8i8, OpNode, Commutable>;
1264 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
1265 OpcodeStr, !strconcat(Dt, "16"),
1266 v4i16, v4i16, OpNode, Commutable>;
1267 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
1268 OpcodeStr, !strconcat(Dt, "32"),
1269 v2i32, v2i32, OpNode, Commutable>;
1271 // 128-bit vector types.
1272 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
1273 OpcodeStr, !strconcat(Dt, "8"),
1274 v16i8, v16i8, OpNode, Commutable>;
1275 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
1276 OpcodeStr, !strconcat(Dt, "16"),
1277 v8i16, v8i16, OpNode, Commutable>;
1278 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
1279 OpcodeStr, !strconcat(Dt, "32"),
1280 v4i32, v4i32, OpNode, Commutable>;
1283 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
1284 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1286 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
1288 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1289 v8i16, v4i16, ShOp>;
1290 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
1291 v4i32, v2i32, ShOp>;
1294 // ....then also with element size 64 bits:
1295 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1296 InstrItinClass itinD, InstrItinClass itinQ,
1297 string OpcodeStr, string Dt,
1298 SDNode OpNode, bit Commutable = 0>
1299 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
1300 OpcodeStr, Dt, OpNode, Commutable> {
1301 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
1302 OpcodeStr, !strconcat(Dt, "64"),
1303 v1i64, v1i64, OpNode, Commutable>;
1304 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
1305 OpcodeStr, !strconcat(Dt, "64"),
1306 v2i64, v2i64, OpNode, Commutable>;
1310 // Neon Narrowing 2-register vector intrinsics,
1311 // source operand element sizes of 16, 32 and 64 bits:
1312 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1313 bits<5> op11_7, bit op6, bit op4,
1314 InstrItinClass itin, string OpcodeStr, string Dt,
1316 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
1317 itin, OpcodeStr, !strconcat(Dt, "16"),
1318 v8i8, v8i16, IntOp>;
1319 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
1320 itin, OpcodeStr, !strconcat(Dt, "32"),
1321 v4i16, v4i32, IntOp>;
1322 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
1323 itin, OpcodeStr, !strconcat(Dt, "64"),
1324 v2i32, v2i64, IntOp>;
1328 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
1329 // source operand element sizes of 16, 32 and 64 bits:
1330 multiclass N2VLInt_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
1331 string OpcodeStr, string Dt, Intrinsic IntOp> {
1332 def v8i16 : N2VLInt<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1333 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
1334 def v4i32 : N2VLInt<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1335 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1336 def v2i64 : N2VLInt<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1337 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1341 // Neon 3-register vector intrinsics.
1343 // First with only element sizes of 16 and 32 bits:
1344 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1345 InstrItinClass itinD16, InstrItinClass itinD32,
1346 InstrItinClass itinQ16, InstrItinClass itinQ32,
1347 string OpcodeStr, string Dt,
1348 Intrinsic IntOp, bit Commutable = 0> {
1349 // 64-bit vector types.
1350 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, itinD16,
1351 OpcodeStr, !strconcat(Dt, "16"),
1352 v4i16, v4i16, IntOp, Commutable>;
1353 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, itinD32,
1354 OpcodeStr, !strconcat(Dt, "32"),
1355 v2i32, v2i32, IntOp, Commutable>;
1357 // 128-bit vector types.
1358 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, itinQ16,
1359 OpcodeStr, !strconcat(Dt, "16"),
1360 v8i16, v8i16, IntOp, Commutable>;
1361 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, itinQ32,
1362 OpcodeStr, !strconcat(Dt, "32"),
1363 v4i32, v4i32, IntOp, Commutable>;
1366 multiclass N3VIntSL_HS<bits<4> op11_8,
1367 InstrItinClass itinD16, InstrItinClass itinD32,
1368 InstrItinClass itinQ16, InstrItinClass itinQ32,
1369 string OpcodeStr, string Dt, Intrinsic IntOp> {
1370 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
1371 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
1372 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
1373 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
1374 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
1375 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
1376 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
1377 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
1380 // ....then also with element size of 8 bits:
1381 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1382 InstrItinClass itinD16, InstrItinClass itinD32,
1383 InstrItinClass itinQ16, InstrItinClass itinQ32,
1384 string OpcodeStr, string Dt,
1385 Intrinsic IntOp, bit Commutable = 0>
1386 : N3VInt_HS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
1387 OpcodeStr, Dt, IntOp, Commutable> {
1388 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, itinD16,
1389 OpcodeStr, !strconcat(Dt, "8"),
1390 v8i8, v8i8, IntOp, Commutable>;
1391 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, itinQ16,
1392 OpcodeStr, !strconcat(Dt, "8"),
1393 v16i8, v16i8, IntOp, Commutable>;
1396 // ....then also with element size of 64 bits:
1397 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1398 InstrItinClass itinD16, InstrItinClass itinD32,
1399 InstrItinClass itinQ16, InstrItinClass itinQ32,
1400 string OpcodeStr, string Dt,
1401 Intrinsic IntOp, bit Commutable = 0>
1402 : N3VInt_QHS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
1403 OpcodeStr, Dt, IntOp, Commutable> {
1404 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, itinD32,
1405 OpcodeStr, !strconcat(Dt, "64"),
1406 v1i64, v1i64, IntOp, Commutable>;
1407 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, itinQ32,
1408 OpcodeStr, !strconcat(Dt, "64"),
1409 v2i64, v2i64, IntOp, Commutable>;
1413 // Neon Narrowing 3-register vector intrinsics,
1414 // source operand element sizes of 16, 32 and 64 bits:
1415 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1416 string OpcodeStr, string Dt,
1417 Intrinsic IntOp, bit Commutable = 0> {
1418 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
1419 OpcodeStr, !strconcat(Dt, "16"),
1420 v8i8, v8i16, IntOp, Commutable>;
1421 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
1422 OpcodeStr, !strconcat(Dt, "32"),
1423 v4i16, v4i32, IntOp, Commutable>;
1424 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
1425 OpcodeStr, !strconcat(Dt, "64"),
1426 v2i32, v2i64, IntOp, Commutable>;
1430 // Neon Long 3-register vector intrinsics.
1432 // First with only element sizes of 16 and 32 bits:
1433 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1434 InstrItinClass itin, string OpcodeStr, string Dt,
1435 Intrinsic IntOp, bit Commutable = 0> {
1436 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin,
1437 OpcodeStr, !strconcat(Dt, "16"),
1438 v4i32, v4i16, IntOp, Commutable>;
1439 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin,
1440 OpcodeStr, !strconcat(Dt, "32"),
1441 v2i64, v2i32, IntOp, Commutable>;
1444 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
1445 InstrItinClass itin, string OpcodeStr, string Dt,
1447 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
1448 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1449 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
1450 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1453 // ....then also with element size of 8 bits:
1454 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1455 InstrItinClass itin, string OpcodeStr, string Dt,
1456 Intrinsic IntOp, bit Commutable = 0>
1457 : N3VLInt_HS<op24, op23, op11_8, op4, itin, OpcodeStr, Dt,
1458 IntOp, Commutable> {
1459 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin,
1460 OpcodeStr, !strconcat(Dt, "8"),
1461 v8i16, v8i8, IntOp, Commutable>;
1465 // Neon Wide 3-register vector intrinsics,
1466 // source operand element sizes of 8, 16 and 32 bits:
1467 multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1468 string OpcodeStr, string Dt,
1469 Intrinsic IntOp, bit Commutable = 0> {
1470 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4,
1471 OpcodeStr, !strconcat(Dt, "8"),
1472 v8i16, v8i8, IntOp, Commutable>;
1473 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4,
1474 OpcodeStr, !strconcat(Dt, "16"),
1475 v4i32, v4i16, IntOp, Commutable>;
1476 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4,
1477 OpcodeStr, !strconcat(Dt, "32"),
1478 v2i64, v2i32, IntOp, Commutable>;
1482 // Neon Multiply-Op vector operations,
1483 // element sizes of 8, 16 and 32 bits:
1484 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1485 InstrItinClass itinD16, InstrItinClass itinD32,
1486 InstrItinClass itinQ16, InstrItinClass itinQ32,
1487 string OpcodeStr, string Dt, SDNode OpNode> {
1488 // 64-bit vector types.
1489 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
1490 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
1491 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
1492 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
1493 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
1494 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
1496 // 128-bit vector types.
1497 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
1498 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
1499 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
1500 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
1501 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
1502 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
1505 multiclass N3VMulOpSL_HS<bits<4> op11_8,
1506 InstrItinClass itinD16, InstrItinClass itinD32,
1507 InstrItinClass itinQ16, InstrItinClass itinQ32,
1508 string OpcodeStr, string Dt, SDNode ShOp> {
1509 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
1510 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
1511 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
1512 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
1513 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
1514 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, mul, ShOp>;
1515 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
1516 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, mul, ShOp>;
1519 // Neon 3-argument intrinsics,
1520 // element sizes of 8, 16 and 32 bits:
1521 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1522 string OpcodeStr, string Dt, Intrinsic IntOp> {
1523 // 64-bit vector types.
1524 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16D,
1525 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
1526 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
1527 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
1528 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32D,
1529 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
1531 // 128-bit vector types.
1532 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16Q,
1533 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
1534 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16Q,
1535 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
1536 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32Q,
1537 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
1541 // Neon Long 3-argument intrinsics.
1543 // First with only element sizes of 16 and 32 bits:
1544 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1545 string OpcodeStr, string Dt, Intrinsic IntOp> {
1546 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
1547 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1548 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi16D,
1549 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1552 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
1553 string OpcodeStr, string Dt, Intrinsic IntOp> {
1554 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
1555 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
1556 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
1557 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1560 // ....then also with element size of 8 bits:
1561 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1562 string OpcodeStr, string Dt, Intrinsic IntOp>
1563 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, Dt, IntOp> {
1564 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16D,
1565 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
1569 // Neon 2-register vector intrinsics,
1570 // element sizes of 8, 16 and 32 bits:
1571 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1572 bits<5> op11_7, bit op4,
1573 InstrItinClass itinD, InstrItinClass itinQ,
1574 string OpcodeStr, string Dt, Intrinsic IntOp> {
1575 // 64-bit vector types.
1576 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1577 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
1578 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1579 itinD, OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
1580 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1581 itinD, OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
1583 // 128-bit vector types.
1584 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1585 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
1586 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1587 itinQ, OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
1588 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1589 itinQ, OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
1593 // Neon Pairwise long 2-register intrinsics,
1594 // element sizes of 8, 16 and 32 bits:
1595 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1596 bits<5> op11_7, bit op4,
1597 string OpcodeStr, string Dt, Intrinsic IntOp> {
1598 // 64-bit vector types.
1599 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1600 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
1601 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1602 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
1603 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1604 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
1606 // 128-bit vector types.
1607 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1608 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
1609 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1610 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
1611 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1612 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
1616 // Neon Pairwise long 2-register accumulate intrinsics,
1617 // element sizes of 8, 16 and 32 bits:
1618 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1619 bits<5> op11_7, bit op4,
1620 string OpcodeStr, string Dt, Intrinsic IntOp> {
1621 // 64-bit vector types.
1622 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1623 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
1624 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1625 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
1626 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1627 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
1629 // 128-bit vector types.
1630 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1631 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
1632 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1633 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
1634 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1635 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
1639 // Neon 2-register vector shift by immediate,
1640 // element sizes of 8, 16, 32 and 64 bits:
1641 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1642 InstrItinClass itin, string OpcodeStr, string Dt,
1644 // 64-bit vector types.
1645 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
1646 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
1647 let Inst{21-19} = 0b001; // imm6 = 001xxx
1649 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
1650 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
1651 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1653 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
1654 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
1655 let Inst{21} = 0b1; // imm6 = 1xxxxx
1657 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, itin,
1658 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
1661 // 128-bit vector types.
1662 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
1663 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
1664 let Inst{21-19} = 0b001; // imm6 = 001xxx
1666 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
1667 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
1668 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1670 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
1671 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
1672 let Inst{21} = 0b1; // imm6 = 1xxxxx
1674 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, itin,
1675 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
1680 // Neon Shift-Accumulate vector operations,
1681 // element sizes of 8, 16, 32 and 64 bits:
1682 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1683 string OpcodeStr, string Dt, SDNode ShOp> {
1684 // 64-bit vector types.
1685 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1686 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
1687 let Inst{21-19} = 0b001; // imm6 = 001xxx
1689 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1690 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
1691 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1693 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1694 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
1695 let Inst{21} = 0b1; // imm6 = 1xxxxx
1697 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4,
1698 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
1701 // 128-bit vector types.
1702 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1703 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
1704 let Inst{21-19} = 0b001; // imm6 = 001xxx
1706 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1707 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
1708 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1710 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1711 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
1712 let Inst{21} = 0b1; // imm6 = 1xxxxx
1714 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4,
1715 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
1720 // Neon Shift-Insert vector operations,
1721 // element sizes of 8, 16, 32 and 64 bits:
1722 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1723 string OpcodeStr, SDNode ShOp> {
1724 // 64-bit vector types.
1725 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4,
1726 OpcodeStr, "8", v8i8, ShOp> {
1727 let Inst{21-19} = 0b001; // imm6 = 001xxx
1729 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4,
1730 OpcodeStr, "16", v4i16, ShOp> {
1731 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1733 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4,
1734 OpcodeStr, "32", v2i32, ShOp> {
1735 let Inst{21} = 0b1; // imm6 = 1xxxxx
1737 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4,
1738 OpcodeStr, "64", v1i64, ShOp>;
1741 // 128-bit vector types.
1742 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4,
1743 OpcodeStr, "8", v16i8, ShOp> {
1744 let Inst{21-19} = 0b001; // imm6 = 001xxx
1746 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4,
1747 OpcodeStr, "16", v8i16, ShOp> {
1748 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1750 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4,
1751 OpcodeStr, "32", v4i32, ShOp> {
1752 let Inst{21} = 0b1; // imm6 = 1xxxxx
1754 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4,
1755 OpcodeStr, "64", v2i64, ShOp>;
1759 // Neon Shift Long operations,
1760 // element sizes of 8, 16, 32 bits:
1761 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
1762 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
1763 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1764 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
1765 let Inst{21-19} = 0b001; // imm6 = 001xxx
1767 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1768 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
1769 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1771 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1772 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
1773 let Inst{21} = 0b1; // imm6 = 1xxxxx
1777 // Neon Shift Narrow operations,
1778 // element sizes of 16, 32, 64 bits:
1779 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
1780 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
1782 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1783 OpcodeStr, !strconcat(Dt, "16"), v8i8, v8i16, OpNode> {
1784 let Inst{21-19} = 0b001; // imm6 = 001xxx
1786 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1787 OpcodeStr, !strconcat(Dt, "32"), v4i16, v4i32, OpNode> {
1788 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1790 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1791 OpcodeStr, !strconcat(Dt, "64"), v2i32, v2i64, OpNode> {
1792 let Inst{21} = 0b1; // imm6 = 1xxxxx
1796 //===----------------------------------------------------------------------===//
1797 // Instruction Definitions.
1798 //===----------------------------------------------------------------------===//
1800 // Vector Add Operations.
1802 // VADD : Vector Add (integer and floating-point)
1803 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
1805 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
1806 v2f32, v2f32, fadd, 1>;
1807 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
1808 v4f32, v4f32, fadd, 1>;
1809 // VADDL : Vector Add Long (Q = D + D)
1810 defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, IIC_VSHLiD, "vaddl", "s",
1811 int_arm_neon_vaddls, 1>;
1812 defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, IIC_VSHLiD, "vaddl", "u",
1813 int_arm_neon_vaddlu, 1>;
1814 // VADDW : Vector Add Wide (Q = Q + D)
1815 defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw", "s", int_arm_neon_vaddws, 0>;
1816 defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw", "u", int_arm_neon_vaddwu, 0>;
1817 // VHADD : Vector Halving Add
1818 defm VHADDs : N3VInt_QHS<0,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1819 IIC_VBINi4Q, "vhadd", "s", int_arm_neon_vhadds, 1>;
1820 defm VHADDu : N3VInt_QHS<1,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1821 IIC_VBINi4Q, "vhadd", "u", int_arm_neon_vhaddu, 1>;
1822 // VRHADD : Vector Rounding Halving Add
1823 defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1824 IIC_VBINi4Q, "vrhadd", "s", int_arm_neon_vrhadds, 1>;
1825 defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1826 IIC_VBINi4Q, "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
1827 // VQADD : Vector Saturating Add
1828 defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1829 IIC_VBINi4Q, "vqadd", "s", int_arm_neon_vqadds, 1>;
1830 defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1831 IIC_VBINi4Q, "vqadd", "u", int_arm_neon_vqaddu, 1>;
1832 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
1833 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
1834 int_arm_neon_vaddhn, 1>;
1835 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
1836 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
1837 int_arm_neon_vraddhn, 1>;
1839 // Vector Multiply Operations.
1841 // VMUL : Vector Multiply (integer, polynomial and floating-point)
1842 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
1843 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
1844 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16D, "vmul", "p8",
1845 v8i8, v8i8, int_arm_neon_vmulp, 1>;
1846 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16Q, "vmul", "p8",
1847 v16i8, v16i8, int_arm_neon_vmulp, 1>;
1848 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VBIND, "vmul", "f32",
1849 v2f32, v2f32, fmul, 1>;
1850 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VBINQ, "vmul", "f32",
1851 v4f32, v4f32, fmul, 1>;
1852 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
1853 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
1854 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32, v2f32, fmul>;
1855 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
1856 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
1857 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
1858 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1859 (DSubReg_i16_reg imm:$lane))),
1860 (SubReg_i16_lane imm:$lane)))>;
1861 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
1862 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
1863 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
1864 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1865 (DSubReg_i32_reg imm:$lane))),
1866 (SubReg_i32_lane imm:$lane)))>;
1867 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
1868 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
1869 (v4f32 (VMULslfq (v4f32 QPR:$src1),
1870 (v2f32 (EXTRACT_SUBREG QPR:$src2,
1871 (DSubReg_i32_reg imm:$lane))),
1872 (SubReg_i32_lane imm:$lane)))>;
1874 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
1875 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
1876 IIC_VMULi16Q, IIC_VMULi32Q,
1877 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
1878 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
1879 IIC_VMULi16Q, IIC_VMULi32Q,
1880 "vqdmulh", "s", int_arm_neon_vqdmulh>;
1881 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
1882 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
1884 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
1885 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1886 (DSubReg_i16_reg imm:$lane))),
1887 (SubReg_i16_lane imm:$lane)))>;
1888 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
1889 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
1891 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
1892 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1893 (DSubReg_i32_reg imm:$lane))),
1894 (SubReg_i32_lane imm:$lane)))>;
1896 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
1897 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
1898 IIC_VMULi16Q, IIC_VMULi32Q,
1899 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
1900 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
1901 IIC_VMULi16Q, IIC_VMULi32Q,
1902 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
1903 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
1904 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
1906 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
1907 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1908 (DSubReg_i16_reg imm:$lane))),
1909 (SubReg_i16_lane imm:$lane)))>;
1910 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
1911 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
1913 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
1914 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1915 (DSubReg_i32_reg imm:$lane))),
1916 (SubReg_i32_lane imm:$lane)))>;
1918 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
1919 defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, IIC_VMULi16D, "vmull", "s",
1920 int_arm_neon_vmulls, 1>;
1921 defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, IIC_VMULi16D, "vmull", "u",
1922 int_arm_neon_vmullu, 1>;
1923 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
1924 v8i16, v8i8, int_arm_neon_vmullp, 1>;
1925 defm VMULLsls : N3VLIntSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s",
1926 int_arm_neon_vmulls>;
1927 defm VMULLslu : N3VLIntSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u",
1928 int_arm_neon_vmullu>;
1930 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
1931 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, "vqdmull", "s",
1932 int_arm_neon_vqdmull, 1>;
1933 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D, "vqdmull", "s",
1934 int_arm_neon_vqdmull>;
1936 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
1938 // VMLA : Vector Multiply Accumulate (integer and floating-point)
1939 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
1940 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
1941 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
1943 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
1945 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
1946 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
1947 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
1949 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
1950 v4f32, v2f32, fmul, fadd>;
1952 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
1953 (mul (v8i16 QPR:$src2),
1954 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
1955 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1),
1957 (v4i16 (EXTRACT_SUBREG QPR:$src3,
1958 (DSubReg_i16_reg imm:$lane))),
1959 (SubReg_i16_lane imm:$lane)))>;
1961 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
1962 (mul (v4i32 QPR:$src2),
1963 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
1964 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1),
1966 (v2i32 (EXTRACT_SUBREG QPR:$src3,
1967 (DSubReg_i32_reg imm:$lane))),
1968 (SubReg_i32_lane imm:$lane)))>;
1970 def : Pat<(v4f32 (fadd (v4f32 QPR:$src1),
1971 (fmul (v4f32 QPR:$src2),
1972 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
1973 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
1975 (v2f32 (EXTRACT_SUBREG QPR:$src3,
1976 (DSubReg_i32_reg imm:$lane))),
1977 (SubReg_i32_lane imm:$lane)))>;
1979 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
1980 defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal", "s", int_arm_neon_vmlals>;
1981 defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal", "u", int_arm_neon_vmlalu>;
1983 defm VMLALsls : N3VLInt3SL_HS<0, 0b0010, "vmlal", "s", int_arm_neon_vmlals>;
1984 defm VMLALslu : N3VLInt3SL_HS<1, 0b0010, "vmlal", "u", int_arm_neon_vmlalu>;
1986 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
1987 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal", "s",
1988 int_arm_neon_vqdmlal>;
1989 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
1991 // VMLS : Vector Multiply Subtract (integer and floating-point)
1992 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
1993 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
1994 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
1996 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
1998 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
1999 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
2000 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
2002 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
2003 v4f32, v2f32, fmul, fsub>;
2005 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
2006 (mul (v8i16 QPR:$src2),
2007 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
2008 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1),
2010 (v4i16 (EXTRACT_SUBREG QPR:$src3,
2011 (DSubReg_i16_reg imm:$lane))),
2012 (SubReg_i16_lane imm:$lane)))>;
2014 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
2015 (mul (v4i32 QPR:$src2),
2016 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
2017 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1),
2019 (v2i32 (EXTRACT_SUBREG QPR:$src3,
2020 (DSubReg_i32_reg imm:$lane))),
2021 (SubReg_i32_lane imm:$lane)))>;
2023 def : Pat<(v4f32 (fsub (v4f32 QPR:$src1),
2024 (fmul (v4f32 QPR:$src2),
2025 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
2026 (v4f32 (VMLSslfq (v4f32 QPR:$src1),
2028 (v2f32 (EXTRACT_SUBREG QPR:$src3,
2029 (DSubReg_i32_reg imm:$lane))),
2030 (SubReg_i32_lane imm:$lane)))>;
2032 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
2033 defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl", "s", int_arm_neon_vmlsls>;
2034 defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl", "u", int_arm_neon_vmlslu>;
2036 defm VMLSLsls : N3VLInt3SL_HS<0, 0b0110, "vmlsl", "s", int_arm_neon_vmlsls>;
2037 defm VMLSLslu : N3VLInt3SL_HS<1, 0b0110, "vmlsl", "u", int_arm_neon_vmlslu>;
2039 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
2040 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl", "s",
2041 int_arm_neon_vqdmlsl>;
2042 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
2044 // Vector Subtract Operations.
2046 // VSUB : Vector Subtract (integer and floating-point)
2047 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
2048 "vsub", "i", sub, 0>;
2049 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
2050 v2f32, v2f32, fsub, 0>;
2051 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
2052 v4f32, v4f32, fsub, 0>;
2053 // VSUBL : Vector Subtract Long (Q = D - D)
2054 defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, IIC_VSHLiD, "vsubl", "s",
2055 int_arm_neon_vsubls, 1>;
2056 defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, IIC_VSHLiD, "vsubl", "u",
2057 int_arm_neon_vsublu, 1>;
2058 // VSUBW : Vector Subtract Wide (Q = Q - D)
2059 defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw", "s", int_arm_neon_vsubws, 0>;
2060 defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw", "u", int_arm_neon_vsubwu, 0>;
2061 // VHSUB : Vector Halving Subtract
2062 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D,
2063 IIC_VBINi4Q, IIC_VBINi4Q,
2064 "vhsub", "s", int_arm_neon_vhsubs, 0>;
2065 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D,
2066 IIC_VBINi4Q, IIC_VBINi4Q,
2067 "vhsub", "u", int_arm_neon_vhsubu, 0>;
2068 // VQSUB : Vector Saturing Subtract
2069 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D,
2070 IIC_VBINi4Q, IIC_VBINi4Q,
2071 "vqsub", "s", int_arm_neon_vqsubs, 0>;
2072 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D,
2073 IIC_VBINi4Q, IIC_VBINi4Q,
2074 "vqsub", "u", int_arm_neon_vqsubu, 0>;
2075 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
2076 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
2077 int_arm_neon_vsubhn, 0>;
2078 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
2079 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
2080 int_arm_neon_vrsubhn, 0>;
2082 // Vector Comparisons.
2084 // VCEQ : Vector Compare Equal
2085 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2086 IIC_VBINi4Q, "vceq", "i", NEONvceq, 1>;
2087 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
2089 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
2091 // VCGE : Vector Compare Greater Than or Equal
2092 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2093 IIC_VBINi4Q, "vcge", "s", NEONvcge, 0>;
2094 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2095 IIC_VBINi4Q, "vcge", "u", NEONvcgeu, 0>;
2096 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32",
2097 v2i32, v2f32, NEONvcge, 0>;
2098 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
2100 // VCGT : Vector Compare Greater Than
2101 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2102 IIC_VBINi4Q, "vcgt", "s", NEONvcgt, 0>;
2103 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2104 IIC_VBINi4Q, "vcgt", "u", NEONvcgtu, 0>;
2105 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
2107 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
2109 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
2110 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, IIC_VBIND, "vacge", "f32",
2111 v2i32, v2f32, int_arm_neon_vacged, 0>;
2112 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, IIC_VBINQ, "vacge", "f32",
2113 v4i32, v4f32, int_arm_neon_vacgeq, 0>;
2114 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
2115 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, IIC_VBIND, "vacgt", "f32",
2116 v2i32, v2f32, int_arm_neon_vacgtd, 0>;
2117 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, IIC_VBINQ, "vacgt", "f32",
2118 v4i32, v4f32, int_arm_neon_vacgtq, 0>;
2119 // VTST : Vector Test Bits
2120 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2121 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
2123 // Vector Bitwise Operations.
2125 // VAND : Vector Bitwise AND
2126 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
2127 v2i32, v2i32, and, 1>;
2128 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
2129 v4i32, v4i32, and, 1>;
2131 // VEOR : Vector Bitwise Exclusive OR
2132 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
2133 v2i32, v2i32, xor, 1>;
2134 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
2135 v4i32, v4i32, xor, 1>;
2137 // VORR : Vector Bitwise OR
2138 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
2139 v2i32, v2i32, or, 1>;
2140 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
2141 v4i32, v4i32, or, 1>;
2143 // VBIC : Vector Bitwise Bit Clear (AND NOT)
2144 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2145 (ins DPR:$src1, DPR:$src2), IIC_VBINiD,
2146 "vbic", "$dst, $src1, $src2", "",
2147 [(set DPR:$dst, (v2i32 (and DPR:$src1,
2148 (vnot_conv DPR:$src2))))]>;
2149 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2150 (ins QPR:$src1, QPR:$src2), IIC_VBINiQ,
2151 "vbic", "$dst, $src1, $src2", "",
2152 [(set QPR:$dst, (v4i32 (and QPR:$src1,
2153 (vnot_conv QPR:$src2))))]>;
2155 // VORN : Vector Bitwise OR NOT
2156 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
2157 (ins DPR:$src1, DPR:$src2), IIC_VBINiD,
2158 "vorn", "$dst, $src1, $src2", "",
2159 [(set DPR:$dst, (v2i32 (or DPR:$src1,
2160 (vnot_conv DPR:$src2))))]>;
2161 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
2162 (ins QPR:$src1, QPR:$src2), IIC_VBINiQ,
2163 "vorn", "$dst, $src1, $src2", "",
2164 [(set QPR:$dst, (v4i32 (or QPR:$src1,
2165 (vnot_conv QPR:$src2))))]>;
2167 // VMVN : Vector Bitwise NOT
2168 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
2169 (outs DPR:$dst), (ins DPR:$src), IIC_VSHLiD,
2170 "vmvn", "$dst, $src", "",
2171 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>;
2172 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
2173 (outs QPR:$dst), (ins QPR:$src), IIC_VSHLiD,
2174 "vmvn", "$dst, $src", "",
2175 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>;
2176 def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>;
2177 def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>;
2179 // VBSL : Vector Bitwise Select
2180 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2181 (ins DPR:$src1, DPR:$src2, DPR:$src3), IIC_VCNTiD,
2182 "vbsl", "$dst, $src2, $src3", "$src1 = $dst",
2184 (v2i32 (or (and DPR:$src2, DPR:$src1),
2185 (and DPR:$src3, (vnot_conv DPR:$src1)))))]>;
2186 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2187 (ins QPR:$src1, QPR:$src2, QPR:$src3), IIC_VCNTiQ,
2188 "vbsl", "$dst, $src2, $src3", "$src1 = $dst",
2190 (v4i32 (or (and QPR:$src2, QPR:$src1),
2191 (and QPR:$src3, (vnot_conv QPR:$src1)))))]>;
2193 // VBIF : Vector Bitwise Insert if False
2194 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
2195 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
2196 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
2197 IIC_VBINiD, "vbif", "$dst, $src2, $src3", "$src1 = $dst",
2198 [/* For disassembly only; pattern left blank */]>;
2199 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
2200 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
2201 IIC_VBINiQ, "vbif", "$dst, $src2, $src3", "$src1 = $dst",
2202 [/* For disassembly only; pattern left blank */]>;
2204 // VBIT : Vector Bitwise Insert if True
2205 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
2206 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
2207 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
2208 IIC_VBINiD, "vbit", "$dst, $src2, $src3", "$src1 = $dst",
2209 [/* For disassembly only; pattern left blank */]>;
2210 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
2211 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
2212 IIC_VBINiQ, "vbit", "$dst, $src2, $src3", "$src1 = $dst",
2213 [/* For disassembly only; pattern left blank */]>;
2215 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
2216 // for equivalent operations with different register constraints; it just
2219 // Vector Absolute Differences.
2221 // VABD : Vector Absolute Difference
2222 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D,
2223 IIC_VBINi4Q, IIC_VBINi4Q,
2224 "vabd", "s", int_arm_neon_vabds, 0>;
2225 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D,
2226 IIC_VBINi4Q, IIC_VBINi4Q,
2227 "vabd", "u", int_arm_neon_vabdu, 0>;
2228 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, IIC_VBIND,
2229 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 0>;
2230 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, IIC_VBINQ,
2231 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 0>;
2233 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
2234 defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, IIC_VBINi4Q,
2235 "vabdl", "s", int_arm_neon_vabdls, 0>;
2236 defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, IIC_VBINi4Q,
2237 "vabdl", "u", int_arm_neon_vabdlu, 0>;
2239 // VABA : Vector Absolute Difference and Accumulate
2240 defm VABAs : N3VInt3_QHS<0,0,0b0111,1, "vaba", "s", int_arm_neon_vabas>;
2241 defm VABAu : N3VInt3_QHS<1,0,0b0111,1, "vaba", "u", int_arm_neon_vabau>;
2243 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
2244 defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal", "s", int_arm_neon_vabals>;
2245 defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal", "u", int_arm_neon_vabalu>;
2247 // Vector Maximum and Minimum.
2249 // VMAX : Vector Maximum
2250 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2251 IIC_VBINi4Q, "vmax", "s", int_arm_neon_vmaxs, 1>;
2252 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2253 IIC_VBINi4Q, "vmax", "u", int_arm_neon_vmaxu, 1>;
2254 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, IIC_VBIND, "vmax", "f32",
2255 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
2256 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, IIC_VBINQ, "vmax", "f32",
2257 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
2259 // VMIN : Vector Minimum
2260 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2261 IIC_VBINi4Q, "vmin", "s", int_arm_neon_vmins, 1>;
2262 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2263 IIC_VBINi4Q, "vmin", "u", int_arm_neon_vminu, 1>;
2264 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, IIC_VBIND, "vmin", "f32",
2265 v2f32, v2f32, int_arm_neon_vmins, 1>;
2266 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, IIC_VBINQ, "vmin", "f32",
2267 v4f32, v4f32, int_arm_neon_vmins, 1>;
2269 // Vector Pairwise Operations.
2271 // VPADD : Vector Pairwise Add
2272 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, IIC_VBINiD, "vpadd", "i8",
2273 v8i8, v8i8, int_arm_neon_vpadd, 0>;
2274 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, IIC_VBINiD, "vpadd", "i16",
2275 v4i16, v4i16, int_arm_neon_vpadd, 0>;
2276 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, IIC_VBINiD, "vpadd", "i32",
2277 v2i32, v2i32, int_arm_neon_vpadd, 0>;
2278 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, IIC_VBIND, "vpadd", "f32",
2279 v2f32, v2f32, int_arm_neon_vpadd, 0>;
2281 // VPADDL : Vector Pairwise Add Long
2282 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
2283 int_arm_neon_vpaddls>;
2284 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
2285 int_arm_neon_vpaddlu>;
2287 // VPADAL : Vector Pairwise Add and Accumulate Long
2288 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
2289 int_arm_neon_vpadals>;
2290 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
2291 int_arm_neon_vpadalu>;
2293 // VPMAX : Vector Pairwise Maximum
2294 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax", "s8",
2295 v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
2296 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax", "s16",
2297 v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
2298 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax", "s32",
2299 v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
2300 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax", "u8",
2301 v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
2302 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax", "u16",
2303 v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
2304 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax", "u32",
2305 v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
2306 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, IIC_VBINi4D, "vpmax", "f32",
2307 v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
2309 // VPMIN : Vector Pairwise Minimum
2310 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin", "s8",
2311 v8i8, v8i8, int_arm_neon_vpmins, 0>;
2312 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin", "s16",
2313 v4i16, v4i16, int_arm_neon_vpmins, 0>;
2314 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin", "s32",
2315 v2i32, v2i32, int_arm_neon_vpmins, 0>;
2316 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin", "u8",
2317 v8i8, v8i8, int_arm_neon_vpminu, 0>;
2318 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin", "u16",
2319 v4i16, v4i16, int_arm_neon_vpminu, 0>;
2320 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin", "u32",
2321 v2i32, v2i32, int_arm_neon_vpminu, 0>;
2322 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, IIC_VBINi4D, "vpmin", "f32",
2323 v2f32, v2f32, int_arm_neon_vpmins, 0>;
2325 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
2327 // VRECPE : Vector Reciprocal Estimate
2328 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
2329 IIC_VUNAD, "vrecpe", "u32",
2330 v2i32, v2i32, int_arm_neon_vrecpe>;
2331 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
2332 IIC_VUNAQ, "vrecpe", "u32",
2333 v4i32, v4i32, int_arm_neon_vrecpe>;
2334 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
2335 IIC_VUNAD, "vrecpe", "f32",
2336 v2f32, v2f32, int_arm_neon_vrecpe>;
2337 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
2338 IIC_VUNAQ, "vrecpe", "f32",
2339 v4f32, v4f32, int_arm_neon_vrecpe>;
2341 // VRECPS : Vector Reciprocal Step
2342 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1,
2343 IIC_VRECSD, "vrecps", "f32",
2344 v2f32, v2f32, int_arm_neon_vrecps, 1>;
2345 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1,
2346 IIC_VRECSQ, "vrecps", "f32",
2347 v4f32, v4f32, int_arm_neon_vrecps, 1>;
2349 // VRSQRTE : Vector Reciprocal Square Root Estimate
2350 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
2351 IIC_VUNAD, "vrsqrte", "u32",
2352 v2i32, v2i32, int_arm_neon_vrsqrte>;
2353 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
2354 IIC_VUNAQ, "vrsqrte", "u32",
2355 v4i32, v4i32, int_arm_neon_vrsqrte>;
2356 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
2357 IIC_VUNAD, "vrsqrte", "f32",
2358 v2f32, v2f32, int_arm_neon_vrsqrte>;
2359 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
2360 IIC_VUNAQ, "vrsqrte", "f32",
2361 v4f32, v4f32, int_arm_neon_vrsqrte>;
2363 // VRSQRTS : Vector Reciprocal Square Root Step
2364 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1,
2365 IIC_VRECSD, "vrsqrts", "f32",
2366 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
2367 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1,
2368 IIC_VRECSQ, "vrsqrts", "f32",
2369 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
2373 // VSHL : Vector Shift
2374 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
2375 IIC_VSHLiQ, "vshl", "s", int_arm_neon_vshifts, 0>;
2376 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
2377 IIC_VSHLiQ, "vshl", "u", int_arm_neon_vshiftu, 0>;
2378 // VSHL : Vector Shift Left (Immediate)
2379 defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
2380 // VSHR : Vector Shift Right (Immediate)
2381 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", NEONvshrs>;
2382 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", NEONvshru>;
2384 // VSHLL : Vector Shift Left Long
2385 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
2386 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
2388 // VSHLL : Vector Shift Left Long (with maximum shift count)
2389 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
2390 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
2391 ValueType OpTy, SDNode OpNode>
2392 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
2393 ResTy, OpTy, OpNode> {
2394 let Inst{21-16} = op21_16;
2396 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
2397 v8i16, v8i8, NEONvshlli>;
2398 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
2399 v4i32, v4i16, NEONvshlli>;
2400 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
2401 v2i64, v2i32, NEONvshlli>;
2403 // VSHRN : Vector Shift Right and Narrow
2404 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i", NEONvshrn>;
2406 // VRSHL : Vector Rounding Shift
2407 defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2408 IIC_VSHLi4Q, "vrshl", "s", int_arm_neon_vrshifts, 0>;
2409 defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2410 IIC_VSHLi4Q, "vrshl", "u", int_arm_neon_vrshiftu, 0>;
2411 // VRSHR : Vector Rounding Shift Right
2412 defm VRSHRs : N2VSh_QHSD<0, 1, 0b0010, 1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs>;
2413 defm VRSHRu : N2VSh_QHSD<1, 1, 0b0010, 1, IIC_VSHLi4D, "vrshr", "u", NEONvrshru>;
2415 // VRSHRN : Vector Rounding Shift Right and Narrow
2416 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
2419 // VQSHL : Vector Saturating Shift
2420 defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2421 IIC_VSHLi4Q, "vqshl", "s", int_arm_neon_vqshifts, 0>;
2422 defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2423 IIC_VSHLi4Q, "vqshl", "u", int_arm_neon_vqshiftu, 0>;
2424 // VQSHL : Vector Saturating Shift Left (Immediate)
2425 defm VQSHLsi : N2VSh_QHSD<0, 1, 0b0111, 1, IIC_VSHLi4D, "vqshl", "s", NEONvqshls>;
2426 defm VQSHLui : N2VSh_QHSD<1, 1, 0b0111, 1, IIC_VSHLi4D, "vqshl", "u", NEONvqshlu>;
2427 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
2428 defm VQSHLsu : N2VSh_QHSD<1, 1, 0b0110, 1, IIC_VSHLi4D, "vqshlu", "s", NEONvqshlsu>;
2430 // VQSHRN : Vector Saturating Shift Right and Narrow
2431 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
2433 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
2436 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
2437 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
2440 // VQRSHL : Vector Saturating Rounding Shift
2441 defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2442 IIC_VSHLi4Q, "vqrshl", "s",
2443 int_arm_neon_vqrshifts, 0>;
2444 defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2445 IIC_VSHLi4Q, "vqrshl", "u",
2446 int_arm_neon_vqrshiftu, 0>;
2448 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
2449 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
2451 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
2454 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
2455 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
2458 // VSRA : Vector Shift Right and Accumulate
2459 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
2460 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
2461 // VRSRA : Vector Rounding Shift Right and Accumulate
2462 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
2463 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
2465 // VSLI : Vector Shift Left and Insert
2466 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli", NEONvsli>;
2467 // VSRI : Vector Shift Right and Insert
2468 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri", NEONvsri>;
2470 // Vector Absolute and Saturating Absolute.
2472 // VABS : Vector Absolute Value
2473 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
2474 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
2476 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2477 IIC_VUNAD, "vabs", "f32",
2478 v2f32, v2f32, int_arm_neon_vabs>;
2479 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2480 IIC_VUNAQ, "vabs", "f32",
2481 v4f32, v4f32, int_arm_neon_vabs>;
2483 // VQABS : Vector Saturating Absolute Value
2484 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
2485 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
2486 int_arm_neon_vqabs>;
2490 def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
2491 def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>;
2493 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
2494 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
2495 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
2496 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>;
2497 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
2498 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
2499 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
2500 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>;
2502 // VNEG : Vector Negate
2503 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
2504 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
2505 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
2506 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
2507 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
2508 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
2510 // VNEG : Vector Negate (floating-point)
2511 def VNEGf32d : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
2512 (outs DPR:$dst), (ins DPR:$src), IIC_VUNAD,
2513 "vneg", "f32", "$dst, $src", "",
2514 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
2515 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
2516 (outs QPR:$dst), (ins QPR:$src), IIC_VUNAQ,
2517 "vneg", "f32", "$dst, $src", "",
2518 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
2520 def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
2521 def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
2522 def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>;
2523 def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>;
2524 def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>;
2525 def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>;
2527 // VQNEG : Vector Saturating Negate
2528 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
2529 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
2530 int_arm_neon_vqneg>;
2532 // Vector Bit Counting Operations.
2534 // VCLS : Vector Count Leading Sign Bits
2535 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
2536 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
2538 // VCLZ : Vector Count Leading Zeros
2539 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
2540 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
2542 // VCNT : Vector Count One Bits
2543 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2544 IIC_VCNTiD, "vcnt", "8",
2545 v8i8, v8i8, int_arm_neon_vcnt>;
2546 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2547 IIC_VCNTiQ, "vcnt", "8",
2548 v16i8, v16i8, int_arm_neon_vcnt>;
2550 // Vector Move Operations.
2552 // VMOV : Vector Move (Register)
2554 def VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
2555 IIC_VMOVD, "vmov", "$dst, $src", "", []>;
2556 def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
2557 IIC_VMOVD, "vmov", "$dst, $src", "", []>;
2559 // VMOV : Vector Move (Immediate)
2561 // VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
2562 def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
2563 return ARM::getVMOVImm(N, 1, *CurDAG);
2565 def vmovImm8 : PatLeaf<(build_vector), [{
2566 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
2569 // VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
2570 def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
2571 return ARM::getVMOVImm(N, 2, *CurDAG);
2573 def vmovImm16 : PatLeaf<(build_vector), [{
2574 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
2575 }], VMOV_get_imm16>;
2577 // VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
2578 def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
2579 return ARM::getVMOVImm(N, 4, *CurDAG);
2581 def vmovImm32 : PatLeaf<(build_vector), [{
2582 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
2583 }], VMOV_get_imm32>;
2585 // VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
2586 def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
2587 return ARM::getVMOVImm(N, 8, *CurDAG);
2589 def vmovImm64 : PatLeaf<(build_vector), [{
2590 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
2591 }], VMOV_get_imm64>;
2593 // Note: Some of the cmode bits in the following VMOV instructions need to
2594 // be encoded based on the immed values.
2596 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
2597 (ins h8imm:$SIMM), IIC_VMOVImm,
2598 "vmov", "i8", "$dst, $SIMM", "",
2599 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
2600 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
2601 (ins h8imm:$SIMM), IIC_VMOVImm,
2602 "vmov", "i8", "$dst, $SIMM", "",
2603 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
2605 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,?}, 0, 0, {?}, 1, (outs DPR:$dst),
2606 (ins h16imm:$SIMM), IIC_VMOVImm,
2607 "vmov", "i16", "$dst, $SIMM", "",
2608 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
2609 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,?}, 0, 1, {?}, 1, (outs QPR:$dst),
2610 (ins h16imm:$SIMM), IIC_VMOVImm,
2611 "vmov", "i16", "$dst, $SIMM", "",
2612 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
2614 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, {?}, 1, (outs DPR:$dst),
2615 (ins h32imm:$SIMM), IIC_VMOVImm,
2616 "vmov", "i32", "$dst, $SIMM", "",
2617 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
2618 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, {?}, 1, (outs QPR:$dst),
2619 (ins h32imm:$SIMM), IIC_VMOVImm,
2620 "vmov", "i32", "$dst, $SIMM", "",
2621 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
2623 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
2624 (ins h64imm:$SIMM), IIC_VMOVImm,
2625 "vmov", "i64", "$dst, $SIMM", "",
2626 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
2627 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
2628 (ins h64imm:$SIMM), IIC_VMOVImm,
2629 "vmov", "i64", "$dst, $SIMM", "",
2630 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
2632 // VMOV : Vector Get Lane (move scalar to ARM core register)
2634 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
2635 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2636 IIC_VMOVSI, "vmov", "s8", "$dst, $src[$lane]",
2637 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
2639 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
2640 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2641 IIC_VMOVSI, "vmov", "s16", "$dst, $src[$lane]",
2642 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
2644 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
2645 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2646 IIC_VMOVSI, "vmov", "u8", "$dst, $src[$lane]",
2647 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
2649 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
2650 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2651 IIC_VMOVSI, "vmov", "u16", "$dst, $src[$lane]",
2652 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
2654 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
2655 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2656 IIC_VMOVSI, "vmov", "32", "$dst, $src[$lane]",
2657 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
2659 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
2660 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
2661 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2662 (DSubReg_i8_reg imm:$lane))),
2663 (SubReg_i8_lane imm:$lane))>;
2664 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
2665 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2666 (DSubReg_i16_reg imm:$lane))),
2667 (SubReg_i16_lane imm:$lane))>;
2668 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
2669 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2670 (DSubReg_i8_reg imm:$lane))),
2671 (SubReg_i8_lane imm:$lane))>;
2672 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
2673 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2674 (DSubReg_i16_reg imm:$lane))),
2675 (SubReg_i16_lane imm:$lane))>;
2676 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
2677 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
2678 (DSubReg_i32_reg imm:$lane))),
2679 (SubReg_i32_lane imm:$lane))>;
2680 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
2681 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1), DPR_VFP2)),
2682 (SSubReg_f32_reg imm:$src2))>;
2683 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
2684 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1), QPR_VFP2)),
2685 (SSubReg_f32_reg imm:$src2))>;
2686 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
2687 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2688 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
2689 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2692 // VMOV : Vector Set Lane (move ARM core register to scalar)
2694 let Constraints = "$src1 = $dst" in {
2695 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$dst),
2696 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2697 IIC_VMOVISL, "vmov", "8", "$dst[$lane], $src2",
2698 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
2699 GPR:$src2, imm:$lane))]>;
2700 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$dst),
2701 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2702 IIC_VMOVISL, "vmov", "16", "$dst[$lane], $src2",
2703 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
2704 GPR:$src2, imm:$lane))]>;
2705 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$dst),
2706 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2707 IIC_VMOVISL, "vmov", "32", "$dst[$lane], $src2",
2708 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
2709 GPR:$src2, imm:$lane))]>;
2711 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
2712 (v16i8 (INSERT_SUBREG QPR:$src1,
2713 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
2714 (DSubReg_i8_reg imm:$lane))),
2715 GPR:$src2, (SubReg_i8_lane imm:$lane)),
2716 (DSubReg_i8_reg imm:$lane)))>;
2717 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
2718 (v8i16 (INSERT_SUBREG QPR:$src1,
2719 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
2720 (DSubReg_i16_reg imm:$lane))),
2721 GPR:$src2, (SubReg_i16_lane imm:$lane)),
2722 (DSubReg_i16_reg imm:$lane)))>;
2723 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
2724 (v4i32 (INSERT_SUBREG QPR:$src1,
2725 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
2726 (DSubReg_i32_reg imm:$lane))),
2727 GPR:$src2, (SubReg_i32_lane imm:$lane)),
2728 (DSubReg_i32_reg imm:$lane)))>;
2730 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
2731 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
2732 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
2733 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
2734 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
2735 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
2737 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
2738 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
2739 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
2740 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
2742 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
2743 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
2744 def : Pat<(v2f64 (scalar_to_vector DPR:$src)),
2745 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, arm_dsubreg_0)>;
2746 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
2747 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
2749 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
2750 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2751 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
2752 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2753 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
2754 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2756 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
2757 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
2758 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2760 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
2761 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
2762 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2764 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
2765 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
2766 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2769 // VDUP : Vector Duplicate (from ARM core register to all elements)
2771 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
2772 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
2773 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
2774 [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
2775 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
2776 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
2777 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
2778 [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
2780 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
2781 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
2782 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
2783 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
2784 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
2785 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
2787 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
2788 IIC_VMOVIS, "vdup", "32", "$dst, $src",
2789 [(set DPR:$dst, (v2f32 (NEONvdup
2790 (f32 (bitconvert GPR:$src)))))]>;
2791 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
2792 IIC_VMOVIS, "vdup", "32", "$dst, $src",
2793 [(set QPR:$dst, (v4f32 (NEONvdup
2794 (f32 (bitconvert GPR:$src)))))]>;
2796 // VDUP : Vector Duplicate Lane (from scalar to all elements)
2798 class VDUPLND<bits<2> op19_18, bits<2> op17_16,
2799 string OpcodeStr, string Dt, ValueType Ty>
2800 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
2801 (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
2802 OpcodeStr, Dt, "$dst, $src[$lane]", "",
2803 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
2805 class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, string Dt,
2806 ValueType ResTy, ValueType OpTy>
2807 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
2808 (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
2809 OpcodeStr, Dt, "$dst, $src[$lane]", "",
2810 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src), imm:$lane)))]>;
2812 // Inst{19-16} is partially specified depending on the element size.
2814 def VDUPLN8d : VDUPLND<{?,?}, {?,1}, "vdup", "8", v8i8>;
2815 def VDUPLN16d : VDUPLND<{?,?}, {1,0}, "vdup", "16", v4i16>;
2816 def VDUPLN32d : VDUPLND<{?,1}, {0,0}, "vdup", "32", v2i32>;
2817 def VDUPLNfd : VDUPLND<{?,1}, {0,0}, "vdup", "32", v2f32>;
2818 def VDUPLN8q : VDUPLNQ<{?,?}, {?,1}, "vdup", "8", v16i8, v8i8>;
2819 def VDUPLN16q : VDUPLNQ<{?,?}, {1,0}, "vdup", "16", v8i16, v4i16>;
2820 def VDUPLN32q : VDUPLNQ<{?,1}, {0,0}, "vdup", "32", v4i32, v2i32>;
2821 def VDUPLNfq : VDUPLNQ<{?,1}, {0,0}, "vdup", "32", v4f32, v2f32>;
2823 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
2824 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
2825 (DSubReg_i8_reg imm:$lane))),
2826 (SubReg_i8_lane imm:$lane)))>;
2827 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
2828 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
2829 (DSubReg_i16_reg imm:$lane))),
2830 (SubReg_i16_lane imm:$lane)))>;
2831 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
2832 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
2833 (DSubReg_i32_reg imm:$lane))),
2834 (SubReg_i32_lane imm:$lane)))>;
2835 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
2836 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
2837 (DSubReg_i32_reg imm:$lane))),
2838 (SubReg_i32_lane imm:$lane)))>;
2840 def VDUPfdf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 0, 0,
2841 (outs DPR:$dst), (ins SPR:$src),
2842 IIC_VMOVD, "vdup", "32", "$dst, ${src:lane}", "",
2843 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
2845 def VDUPfqf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 1, 0,
2846 (outs QPR:$dst), (ins SPR:$src),
2847 IIC_VMOVD, "vdup", "32", "$dst, ${src:lane}", "",
2848 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
2850 def : Pat<(v2i64 (NEONvduplane (v2i64 QPR:$src), imm:$lane)),
2851 (INSERT_SUBREG QPR:$src,
2852 (i64 (EXTRACT_SUBREG QPR:$src, (DSubReg_f64_reg imm:$lane))),
2853 (DSubReg_f64_other_reg imm:$lane))>;
2854 def : Pat<(v2f64 (NEONvduplane (v2f64 QPR:$src), imm:$lane)),
2855 (INSERT_SUBREG QPR:$src,
2856 (f64 (EXTRACT_SUBREG QPR:$src, (DSubReg_f64_reg imm:$lane))),
2857 (DSubReg_f64_other_reg imm:$lane))>;
2859 // VMOVN : Vector Narrowing Move
2860 defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVD,
2861 "vmovn", "i", int_arm_neon_vmovn>;
2862 // VQMOVN : Vector Saturating Narrowing Move
2863 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
2864 "vqmovn", "s", int_arm_neon_vqmovns>;
2865 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
2866 "vqmovn", "u", int_arm_neon_vqmovnu>;
2867 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
2868 "vqmovun", "s", int_arm_neon_vqmovnsu>;
2869 // VMOVL : Vector Lengthening Move
2870 defm VMOVLs : N2VLInt_QHS<0b01,0b10100,0,1, "vmovl", "s",
2871 int_arm_neon_vmovls>;
2872 defm VMOVLu : N2VLInt_QHS<0b11,0b10100,0,1, "vmovl", "u",
2873 int_arm_neon_vmovlu>;
2875 // Vector Conversions.
2877 // VCVT : Vector Convert Between Floating-Point and Integers
2878 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
2879 v2i32, v2f32, fp_to_sint>;
2880 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
2881 v2i32, v2f32, fp_to_uint>;
2882 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
2883 v2f32, v2i32, sint_to_fp>;
2884 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
2885 v2f32, v2i32, uint_to_fp>;
2887 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
2888 v4i32, v4f32, fp_to_sint>;
2889 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
2890 v4i32, v4f32, fp_to_uint>;
2891 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
2892 v4f32, v4i32, sint_to_fp>;
2893 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
2894 v4f32, v4i32, uint_to_fp>;
2896 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
2897 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
2898 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
2899 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
2900 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
2901 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
2902 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
2903 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
2904 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
2906 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
2907 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
2908 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
2909 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
2910 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
2911 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
2912 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
2913 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
2917 // VREV64 : Vector Reverse elements within 64-bit doublewords
2919 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
2920 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
2921 (ins DPR:$src), IIC_VMOVD,
2922 OpcodeStr, Dt, "$dst, $src", "",
2923 [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
2924 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
2925 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
2926 (ins QPR:$src), IIC_VMOVD,
2927 OpcodeStr, Dt, "$dst, $src", "",
2928 [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
2930 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
2931 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
2932 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
2933 def VREV64df : VREV64D<0b10, "vrev64", "32", v2f32>;
2935 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
2936 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
2937 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
2938 def VREV64qf : VREV64Q<0b10, "vrev64", "32", v4f32>;
2940 // VREV32 : Vector Reverse elements within 32-bit words
2942 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
2943 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
2944 (ins DPR:$src), IIC_VMOVD,
2945 OpcodeStr, Dt, "$dst, $src", "",
2946 [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
2947 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
2948 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
2949 (ins QPR:$src), IIC_VMOVD,
2950 OpcodeStr, Dt, "$dst, $src", "",
2951 [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
2953 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
2954 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
2956 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
2957 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
2959 // VREV16 : Vector Reverse elements within 16-bit halfwords
2961 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
2962 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
2963 (ins DPR:$src), IIC_VMOVD,
2964 OpcodeStr, Dt, "$dst, $src", "",
2965 [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
2966 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
2967 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
2968 (ins QPR:$src), IIC_VMOVD,
2969 OpcodeStr, Dt, "$dst, $src", "",
2970 [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
2972 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
2973 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
2975 // Other Vector Shuffles.
2977 // VEXT : Vector Extract
2979 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
2980 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$dst),
2981 (ins DPR:$lhs, DPR:$rhs, i32imm:$index), IIC_VEXTD,
2982 OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
2983 [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
2984 (Ty DPR:$rhs), imm:$index)))]>;
2986 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
2987 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$dst),
2988 (ins QPR:$lhs, QPR:$rhs, i32imm:$index), IIC_VEXTQ,
2989 OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
2990 [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
2991 (Ty QPR:$rhs), imm:$index)))]>;
2993 def VEXTd8 : VEXTd<"vext", "8", v8i8>;
2994 def VEXTd16 : VEXTd<"vext", "16", v4i16>;
2995 def VEXTd32 : VEXTd<"vext", "32", v2i32>;
2996 def VEXTdf : VEXTd<"vext", "32", v2f32>;
2998 def VEXTq8 : VEXTq<"vext", "8", v16i8>;
2999 def VEXTq16 : VEXTq<"vext", "16", v8i16>;
3000 def VEXTq32 : VEXTq<"vext", "32", v4i32>;
3001 def VEXTqf : VEXTq<"vext", "32", v4f32>;
3003 // VTRN : Vector Transpose
3005 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
3006 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
3007 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
3009 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
3010 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
3011 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
3013 // VUZP : Vector Unzip (Deinterleave)
3015 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
3016 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
3017 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
3019 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
3020 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
3021 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
3023 // VZIP : Vector Zip (Interleave)
3025 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
3026 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
3027 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
3029 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
3030 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
3031 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
3033 // Vector Table Lookup and Table Extension.
3035 // VTBL : Vector Table Lookup
3037 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
3038 (ins DPR:$tbl1, DPR:$src), IIC_VTB1,
3039 "vtbl", "8", "$dst, \\{$tbl1\\}, $src", "",
3040 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
3041 let hasExtraSrcRegAllocReq = 1 in {
3043 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
3044 (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTB2,
3045 "vtbl", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "",
3046 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl2
3047 DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
3049 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
3050 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTB3,
3051 "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src", "",
3052 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl3
3053 DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
3055 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
3056 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTB4,
3057 "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src", "",
3058 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl4 DPR:$tbl1, DPR:$tbl2,
3059 DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
3060 } // hasExtraSrcRegAllocReq = 1
3062 // VTBX : Vector Table Extension
3064 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
3065 (ins DPR:$orig, DPR:$tbl1, DPR:$src), IIC_VTBX1,
3066 "vtbx", "8", "$dst, \\{$tbl1\\}, $src", "$orig = $dst",
3067 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
3068 DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
3069 let hasExtraSrcRegAllocReq = 1 in {
3071 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
3072 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTBX2,
3073 "vtbx", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "$orig = $dst",
3074 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx2
3075 DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
3077 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
3078 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTBX3,
3079 "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src", "$orig = $dst",
3080 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx3 DPR:$orig, DPR:$tbl1,
3081 DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
3083 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
3084 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTBX4,
3085 "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src",
3087 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx4 DPR:$orig, DPR:$tbl1,
3088 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
3089 } // hasExtraSrcRegAllocReq = 1
3091 //===----------------------------------------------------------------------===//
3092 // NEON instructions for single-precision FP math
3093 //===----------------------------------------------------------------------===//
3095 // These need separate instructions because they must use DPR_VFP2 register
3096 // class which have SPR sub-registers.
3098 // Vector Add Operations used for single-precision FP
3099 let neverHasSideEffects = 1 in
3100 def VADDfd_sfp : N3VDs<0, 0, 0b00, 0b1101, 0, "vadd", "f32", v2f32, v2f32, fadd,1>;
3101 def : N3VDsPat<fadd, VADDfd_sfp>;
3103 // Vector Sub Operations used for single-precision FP
3104 let neverHasSideEffects = 1 in
3105 def VSUBfd_sfp : N3VDs<0, 0, 0b10, 0b1101, 0, "vsub", "f32", v2f32, v2f32, fsub,0>;
3106 def : N3VDsPat<fsub, VSUBfd_sfp>;
3108 // Vector Multiply Operations used for single-precision FP
3109 let neverHasSideEffects = 1 in
3110 def VMULfd_sfp : N3VDs<1, 0, 0b00, 0b1101, 1, "vmul", "f32", v2f32, v2f32, fmul,1>;
3111 def : N3VDsPat<fmul, VMULfd_sfp>;
3113 // Vector Multiply-Accumulate/Subtract used for single-precision FP
3114 // vml[as].f32 can cause 4-8 cycle stalls in following ASIMD instructions, so
3115 // we want to avoid them for now. e.g., alternating vmla/vadd instructions.
3117 //let neverHasSideEffects = 1 in
3118 //def VMLAfd_sfp : N3VDMulOps<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32", v2f32,fmul,fadd>;
3119 //def : N3VDMulOpsPat<fmul, fadd, VMLAfd_sfp>;
3121 //let neverHasSideEffects = 1 in
3122 //def VMLSfd_sfp : N3VDMulOps<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32", v2f32,fmul,fsub>;
3123 //def : N3VDMulOpsPat<fmul, fsub, VMLSfd_sfp>;
3125 // Vector Absolute used for single-precision FP
3126 let neverHasSideEffects = 1 in
3127 def VABSfd_sfp : N2VDInts<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
3128 IIC_VUNAD, "vabs", "f32",
3129 v2f32, v2f32, int_arm_neon_vabs>;
3130 def : N2VDIntsPat<fabs, VABSfd_sfp>;
3132 // Vector Negate used for single-precision FP
3133 let neverHasSideEffects = 1 in
3134 def VNEGf32d_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
3135 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
3136 "vneg", "f32", "$dst, $src", "", []>;
3137 def : N2VDIntsPat<fneg, VNEGf32d_sfp>;
3139 // Vector Convert between single-precision FP and integer
3140 let neverHasSideEffects = 1 in
3141 def VCVTf2sd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3142 v2i32, v2f32, fp_to_sint>;
3143 def : N2VDsPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
3145 let neverHasSideEffects = 1 in
3146 def VCVTf2ud_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3147 v2i32, v2f32, fp_to_uint>;
3148 def : N2VDsPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
3150 let neverHasSideEffects = 1 in
3151 def VCVTs2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3152 v2f32, v2i32, sint_to_fp>;
3153 def : N2VDsPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
3155 let neverHasSideEffects = 1 in
3156 def VCVTu2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3157 v2f32, v2i32, uint_to_fp>;
3158 def : N2VDsPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
3160 //===----------------------------------------------------------------------===//
3161 // Non-Instruction Patterns
3162 //===----------------------------------------------------------------------===//
3165 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
3166 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
3167 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
3168 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
3169 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
3170 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
3171 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
3172 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
3173 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
3174 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
3175 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
3176 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
3177 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
3178 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
3179 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
3180 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
3181 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
3182 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
3183 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
3184 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
3185 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
3186 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
3187 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
3188 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
3189 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
3190 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
3191 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
3192 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
3193 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
3194 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
3196 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
3197 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
3198 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
3199 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
3200 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
3201 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
3202 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
3203 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
3204 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
3205 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
3206 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
3207 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
3208 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
3209 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
3210 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
3211 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
3212 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
3213 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
3214 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
3215 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
3216 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
3217 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
3218 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
3219 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
3220 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
3221 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
3222 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
3223 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
3224 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
3225 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;