1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
69 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
70 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
72 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
74 def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
75 def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
77 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
79 // VDUPLANE can produce a quad-register result from a double-register source,
80 // so the result is not constrained to match the source.
81 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
82 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
85 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
86 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
87 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
89 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
90 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
91 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
92 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
94 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
97 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
98 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
99 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
101 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
102 SDTCisSameAs<1, 2>]>;
103 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
104 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
106 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
107 SDTCisSameAs<0, 2>]>;
108 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
109 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
111 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
112 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
113 unsigned EltBits = 0;
114 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
115 return (EltBits == 32 && EltVal == 0);
118 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
119 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
120 unsigned EltBits = 0;
121 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
122 return (EltBits == 8 && EltVal == 0xff);
125 //===----------------------------------------------------------------------===//
126 // NEON operand definitions
127 //===----------------------------------------------------------------------===//
129 def nModImm : Operand<i32> {
130 let PrintMethod = "printNEONModImmOperand";
133 //===----------------------------------------------------------------------===//
134 // NEON load / store instructions
135 //===----------------------------------------------------------------------===//
137 // Use VLDM to load a Q register as a D register pair.
138 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
140 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn, ldstm_mode:$mode),
142 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
144 // Use VSTM to store a Q register as a D register pair.
145 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
147 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn, ldstm_mode:$mode),
149 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
151 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
153 // Classes for VLD* pseudo-instructions with multi-register operands.
154 // These are expanded to real instructions after register allocation.
155 class VLDQPseudo<InstrItinClass itin>
156 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
157 class VLDQWBPseudo<InstrItinClass itin>
158 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
159 (ins addrmode6:$addr, am6offset:$offset), itin,
161 class VLDQQPseudo<InstrItinClass itin>
162 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
163 class VLDQQWBPseudo<InstrItinClass itin>
164 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
165 (ins addrmode6:$addr, am6offset:$offset), itin,
167 class VLDQQQQWBPseudo<InstrItinClass itin>
168 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
169 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
170 "$addr.addr = $wb, $src = $dst">;
172 // VLD1 : Vector Load (multiple single elements)
173 class VLD1D<bits<4> op7_4, string Dt>
174 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd),
175 (ins addrmode6:$Rn), IIC_VLD1,
176 "vld1", Dt, "\\{$Vd\\}, $Rn", "", []> {
180 class VLD1Q<bits<4> op7_4, string Dt>
181 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2),
182 (ins addrmode6:$Rn), IIC_VLD1x2,
183 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
185 let Inst{5-4} = Rn{5-4};
188 def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
189 def VLD1d16 : VLD1D<{0,1,0,?}, "16">;
190 def VLD1d32 : VLD1D<{1,0,0,?}, "32">;
191 def VLD1d64 : VLD1D<{1,1,0,?}, "64">;
193 def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;
194 def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
195 def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
196 def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
198 def VLD1q8Pseudo : VLDQPseudo<IIC_VLD1x2>;
199 def VLD1q16Pseudo : VLDQPseudo<IIC_VLD1x2>;
200 def VLD1q32Pseudo : VLDQPseudo<IIC_VLD1x2>;
201 def VLD1q64Pseudo : VLDQPseudo<IIC_VLD1x2>;
203 // ...with address register writeback:
204 class VLD1DWB<bits<4> op7_4, string Dt>
205 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd, GPR:$wb),
206 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1u,
207 "vld1", Dt, "\\{$Vd\\}, $Rn$Rm",
208 "$Rn.addr = $wb", []> {
211 class VLD1QWB<bits<4> op7_4, string Dt>
212 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
213 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x2u,
214 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
215 "$Rn.addr = $wb", []> {
216 let Inst{5-4} = Rn{5-4};
219 def VLD1d8_UPD : VLD1DWB<{0,0,0,?}, "8">;
220 def VLD1d16_UPD : VLD1DWB<{0,1,0,?}, "16">;
221 def VLD1d32_UPD : VLD1DWB<{1,0,0,?}, "32">;
222 def VLD1d64_UPD : VLD1DWB<{1,1,0,?}, "64">;
224 def VLD1q8_UPD : VLD1QWB<{0,0,?,?}, "8">;
225 def VLD1q16_UPD : VLD1QWB<{0,1,?,?}, "16">;
226 def VLD1q32_UPD : VLD1QWB<{1,0,?,?}, "32">;
227 def VLD1q64_UPD : VLD1QWB<{1,1,?,?}, "64">;
229 def VLD1q8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
230 def VLD1q16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
231 def VLD1q32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
232 def VLD1q64Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
234 // ...with 3 registers (some of these are only for the disassembler):
235 class VLD1D3<bits<4> op7_4, string Dt>
236 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
237 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
238 "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
242 class VLD1D3WB<bits<4> op7_4, string Dt>
243 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
244 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x3u, "vld1", Dt,
245 "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
249 def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
250 def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;
251 def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;
252 def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;
254 def VLD1d8T_UPD : VLD1D3WB<{0,0,0,?}, "8">;
255 def VLD1d16T_UPD : VLD1D3WB<{0,1,0,?}, "16">;
256 def VLD1d32T_UPD : VLD1D3WB<{1,0,0,?}, "32">;
257 def VLD1d64T_UPD : VLD1D3WB<{1,1,0,?}, "64">;
259 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
260 def VLD1d64TPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x3u>;
262 // ...with 4 registers (some of these are only for the disassembler):
263 class VLD1D4<bits<4> op7_4, string Dt>
264 : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
265 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
266 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
268 let Inst{5-4} = Rn{5-4};
270 class VLD1D4WB<bits<4> op7_4, string Dt>
271 : NLdSt<0,0b10,0b0010,op7_4,
272 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
273 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4, "vld1", Dt,
274 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", "$Rn.addr = $wb",
276 let Inst{5-4} = Rn{5-4};
279 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
280 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;
281 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;
282 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;
284 def VLD1d8Q_UPD : VLD1D4WB<{0,0,?,?}, "8">;
285 def VLD1d16Q_UPD : VLD1D4WB<{0,1,?,?}, "16">;
286 def VLD1d32Q_UPD : VLD1D4WB<{1,0,?,?}, "32">;
287 def VLD1d64Q_UPD : VLD1D4WB<{1,1,?,?}, "64">;
289 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
290 def VLD1d64QPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x4u>;
292 // VLD2 : Vector Load (multiple 2-element structures)
293 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
294 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
295 (ins addrmode6:$Rn), IIC_VLD2,
296 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
298 let Inst{5-4} = Rn{5-4};
300 class VLD2Q<bits<4> op7_4, string Dt>
301 : NLdSt<0, 0b10, 0b0011, op7_4,
302 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
303 (ins addrmode6:$Rn), IIC_VLD2x2,
304 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
306 let Inst{5-4} = Rn{5-4};
309 def VLD2d8 : VLD2D<0b1000, {0,0,?,?}, "8">;
310 def VLD2d16 : VLD2D<0b1000, {0,1,?,?}, "16">;
311 def VLD2d32 : VLD2D<0b1000, {1,0,?,?}, "32">;
313 def VLD2q8 : VLD2Q<{0,0,?,?}, "8">;
314 def VLD2q16 : VLD2Q<{0,1,?,?}, "16">;
315 def VLD2q32 : VLD2Q<{1,0,?,?}, "32">;
317 def VLD2d8Pseudo : VLDQPseudo<IIC_VLD2>;
318 def VLD2d16Pseudo : VLDQPseudo<IIC_VLD2>;
319 def VLD2d32Pseudo : VLDQPseudo<IIC_VLD2>;
321 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
322 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
323 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
325 // ...with address register writeback:
326 class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
327 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
328 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2u,
329 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
330 "$Rn.addr = $wb", []> {
331 let Inst{5-4} = Rn{5-4};
333 class VLD2QWB<bits<4> op7_4, string Dt>
334 : NLdSt<0, 0b10, 0b0011, op7_4,
335 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
336 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2x2u,
337 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
338 "$Rn.addr = $wb", []> {
339 let Inst{5-4} = Rn{5-4};
342 def VLD2d8_UPD : VLD2DWB<0b1000, {0,0,?,?}, "8">;
343 def VLD2d16_UPD : VLD2DWB<0b1000, {0,1,?,?}, "16">;
344 def VLD2d32_UPD : VLD2DWB<0b1000, {1,0,?,?}, "32">;
346 def VLD2q8_UPD : VLD2QWB<{0,0,?,?}, "8">;
347 def VLD2q16_UPD : VLD2QWB<{0,1,?,?}, "16">;
348 def VLD2q32_UPD : VLD2QWB<{1,0,?,?}, "32">;
350 def VLD2d8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
351 def VLD2d16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
352 def VLD2d32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
354 def VLD2q8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
355 def VLD2q16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
356 def VLD2q32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
358 // ...with double-spaced registers (for disassembly only):
359 def VLD2b8 : VLD2D<0b1001, {0,0,?,?}, "8">;
360 def VLD2b16 : VLD2D<0b1001, {0,1,?,?}, "16">;
361 def VLD2b32 : VLD2D<0b1001, {1,0,?,?}, "32">;
362 def VLD2b8_UPD : VLD2DWB<0b1001, {0,0,?,?}, "8">;
363 def VLD2b16_UPD : VLD2DWB<0b1001, {0,1,?,?}, "16">;
364 def VLD2b32_UPD : VLD2DWB<0b1001, {1,0,?,?}, "32">;
366 // VLD3 : Vector Load (multiple 3-element structures)
367 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
368 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
369 (ins addrmode6:$Rn), IIC_VLD3,
370 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
375 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
376 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
377 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
379 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
380 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
381 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
383 // ...with address register writeback:
384 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
385 : NLdSt<0, 0b10, op11_8, op7_4,
386 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
387 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
388 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
389 "$Rn.addr = $wb", []> {
393 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
394 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
395 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
397 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
398 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
399 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
401 // ...with double-spaced registers (non-updating versions for disassembly only):
402 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
403 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
404 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
405 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
406 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
407 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
409 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
410 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
411 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
413 // ...alternate versions to be allocated odd register numbers:
414 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
415 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
416 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
418 // VLD4 : Vector Load (multiple 4-element structures)
419 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
420 : NLdSt<0, 0b10, op11_8, op7_4,
421 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
422 (ins addrmode6:$Rn), IIC_VLD4,
423 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
425 let Inst{5-4} = Rn{5-4};
428 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
429 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
430 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
432 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
433 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
434 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
436 // ...with address register writeback:
437 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
438 : NLdSt<0, 0b10, op11_8, op7_4,
439 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
440 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4,
441 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
442 "$Rn.addr = $wb", []> {
443 let Inst{5-4} = Rn{5-4};
446 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
447 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
448 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
450 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
451 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
452 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
454 // ...with double-spaced registers (non-updating versions for disassembly only):
455 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
456 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
457 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
458 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
459 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
460 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
462 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
463 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
464 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
466 // ...alternate versions to be allocated odd register numbers:
467 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
468 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
469 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
471 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
473 // Classes for VLD*LN pseudo-instructions with multi-register operands.
474 // These are expanded to real instructions after register allocation.
475 class VLDQLNPseudo<InstrItinClass itin>
476 : PseudoNLdSt<(outs QPR:$dst),
477 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
478 itin, "$src = $dst">;
479 class VLDQLNWBPseudo<InstrItinClass itin>
480 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
481 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
482 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
483 class VLDQQLNPseudo<InstrItinClass itin>
484 : PseudoNLdSt<(outs QQPR:$dst),
485 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
486 itin, "$src = $dst">;
487 class VLDQQLNWBPseudo<InstrItinClass itin>
488 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
489 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
490 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
491 class VLDQQQQLNPseudo<InstrItinClass itin>
492 : PseudoNLdSt<(outs QQQQPR:$dst),
493 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
494 itin, "$src = $dst">;
495 class VLDQQQQLNWBPseudo<InstrItinClass itin>
496 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
497 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
498 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
500 // VLD1LN : Vector Load (single element to one lane)
501 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
503 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
504 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
505 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
507 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
508 (i32 (LoadOp addrmode6:$Rn)),
512 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
513 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
514 (i32 (LoadOp addrmode6:$addr)),
518 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
519 let Inst{7-5} = lane{2-0};
521 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
522 let Inst{7-6} = lane{1-0};
525 def VLD1LNd32 : VLD1LN<0b1000, {?,0,?,?}, "32", v2i32, load> {
526 let Inst{7} = lane{0};
531 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
532 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
533 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
535 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
537 // ...with address register writeback:
538 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
539 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
540 (ins addrmode6:$Rn, am6offset:$Rm,
541 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
542 "\\{$Vd[$lane]\\}, $Rn$Rm",
543 "$src = $Vd, $Rn.addr = $wb", []>;
545 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
546 let Inst{7-5} = lane{2-0};
548 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
549 let Inst{7-6} = lane{1-0};
552 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
553 let Inst{7} = lane{0};
558 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
559 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
560 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
562 // VLD2LN : Vector Load (single 2-element structure to one lane)
563 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
564 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
565 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
566 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
567 "$src1 = $Vd, $src2 = $dst2", []> {
572 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
573 let Inst{7-5} = lane{2-0};
575 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
576 let Inst{7-6} = lane{1-0};
578 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
579 let Inst{7} = lane{0};
582 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
583 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
584 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
586 // ...with double-spaced registers:
587 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
588 let Inst{7-6} = lane{1-0};
590 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
591 let Inst{7} = lane{0};
594 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
595 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
597 // ...with address register writeback:
598 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
599 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
600 (ins addrmode6:$Rn, am6offset:$Rm,
601 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
602 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
603 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
607 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
608 let Inst{7-5} = lane{2-0};
610 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
611 let Inst{7-6} = lane{1-0};
613 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
614 let Inst{7} = lane{0};
617 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
618 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
619 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
621 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
622 let Inst{7-6} = lane{1-0};
624 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
625 let Inst{7} = lane{0};
628 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
629 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
631 // VLD3LN : Vector Load (single 3-element structure to one lane)
632 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
633 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
634 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
635 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
636 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
637 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
641 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
642 let Inst{7-5} = lane{2-0};
644 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
645 let Inst{7-6} = lane{1-0};
647 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
648 let Inst{7} = lane{0};
651 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
652 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
653 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
655 // ...with double-spaced registers:
656 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
657 let Inst{7-6} = lane{1-0};
659 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
660 let Inst{7} = lane{0};
663 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
664 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
666 // ...with address register writeback:
667 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
668 : NLdStLn<1, 0b10, op11_8, op7_4,
669 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
670 (ins addrmode6:$Rn, am6offset:$Rm,
671 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
672 IIC_VLD3lnu, "vld3", Dt,
673 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
674 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
677 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
678 let Inst{7-5} = lane{2-0};
680 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
681 let Inst{7-6} = lane{1-0};
683 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
684 let Inst{7} = lane{0};
687 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
688 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
689 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
691 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
692 let Inst{7-6} = lane{1-0};
694 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
695 let Inst{7} = lane{0};
698 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
699 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
701 // VLD4LN : Vector Load (single 4-element structure to one lane)
702 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
703 : NLdStLn<1, 0b10, op11_8, op7_4,
704 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
705 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
706 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
707 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
708 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
713 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
714 let Inst{7-5} = lane{2-0};
716 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
717 let Inst{7-6} = lane{1-0};
719 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
720 let Inst{7} = lane{0};
724 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
725 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
726 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
728 // ...with double-spaced registers:
729 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
730 let Inst{7-6} = lane{1-0};
732 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
733 let Inst{7} = lane{0};
737 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
738 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
740 // ...with address register writeback:
741 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
742 : NLdStLn<1, 0b10, op11_8, op7_4,
743 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
744 (ins addrmode6:$Rn, am6offset:$Rm,
745 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
746 IIC_VLD4ln, "vld4", Dt,
747 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
748 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
753 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
754 let Inst{7-5} = lane{2-0};
756 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
757 let Inst{7-6} = lane{1-0};
759 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
760 let Inst{7} = lane{0};
764 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
765 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
766 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
768 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
769 let Inst{7-6} = lane{1-0};
771 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
772 let Inst{7} = lane{0};
776 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
777 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
779 // VLD1DUP : Vector Load (single element to all lanes)
780 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
781 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
782 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
783 // FIXME: Not yet implemented.
784 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
786 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
788 // Classes for VST* pseudo-instructions with multi-register operands.
789 // These are expanded to real instructions after register allocation.
790 class VSTQPseudo<InstrItinClass itin>
791 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
792 class VSTQWBPseudo<InstrItinClass itin>
793 : PseudoNLdSt<(outs GPR:$wb),
794 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
796 class VSTQQPseudo<InstrItinClass itin>
797 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
798 class VSTQQWBPseudo<InstrItinClass itin>
799 : PseudoNLdSt<(outs GPR:$wb),
800 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
802 class VSTQQQQWBPseudo<InstrItinClass itin>
803 : PseudoNLdSt<(outs GPR:$wb),
804 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
807 // VST1 : Vector Store (multiple single elements)
808 class VST1D<bits<4> op7_4, string Dt>
809 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, DPR:$Vd),
810 IIC_VST1, "vst1", Dt, "\\{$Vd\\}, $Rn", "", []> {
814 class VST1Q<bits<4> op7_4, string Dt>
815 : NLdSt<0,0b00,0b1010,op7_4, (outs),
816 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2), IIC_VST1x2,
817 "vst1", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
819 let Inst{5-4} = Rn{5-4};
822 def VST1d8 : VST1D<{0,0,0,?}, "8">;
823 def VST1d16 : VST1D<{0,1,0,?}, "16">;
824 def VST1d32 : VST1D<{1,0,0,?}, "32">;
825 def VST1d64 : VST1D<{1,1,0,?}, "64">;
827 def VST1q8 : VST1Q<{0,0,?,?}, "8">;
828 def VST1q16 : VST1Q<{0,1,?,?}, "16">;
829 def VST1q32 : VST1Q<{1,0,?,?}, "32">;
830 def VST1q64 : VST1Q<{1,1,?,?}, "64">;
832 def VST1q8Pseudo : VSTQPseudo<IIC_VST1x2>;
833 def VST1q16Pseudo : VSTQPseudo<IIC_VST1x2>;
834 def VST1q32Pseudo : VSTQPseudo<IIC_VST1x2>;
835 def VST1q64Pseudo : VSTQPseudo<IIC_VST1x2>;
837 // ...with address register writeback:
838 class VST1DWB<bits<4> op7_4, string Dt>
839 : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
840 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd), IIC_VST1u,
841 "vst1", Dt, "\\{$Vd\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
844 class VST1QWB<bits<4> op7_4, string Dt>
845 : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),
846 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
847 IIC_VST1x2u, "vst1", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
848 "$Rn.addr = $wb", []> {
849 let Inst{5-4} = Rn{5-4};
852 def VST1d8_UPD : VST1DWB<{0,0,0,?}, "8">;
853 def VST1d16_UPD : VST1DWB<{0,1,0,?}, "16">;
854 def VST1d32_UPD : VST1DWB<{1,0,0,?}, "32">;
855 def VST1d64_UPD : VST1DWB<{1,1,0,?}, "64">;
857 def VST1q8_UPD : VST1QWB<{0,0,?,?}, "8">;
858 def VST1q16_UPD : VST1QWB<{0,1,?,?}, "16">;
859 def VST1q32_UPD : VST1QWB<{1,0,?,?}, "32">;
860 def VST1q64_UPD : VST1QWB<{1,1,?,?}, "64">;
862 def VST1q8Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
863 def VST1q16Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
864 def VST1q32Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
865 def VST1q64Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
867 // ...with 3 registers (some of these are only for the disassembler):
868 class VST1D3<bits<4> op7_4, string Dt>
869 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
870 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3),
871 IIC_VST1x3, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
875 class VST1D3WB<bits<4> op7_4, string Dt>
876 : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
877 (ins addrmode6:$Rn, am6offset:$Rm,
878 DPR:$Vd, DPR:$src2, DPR:$src3),
879 IIC_VST1x3u, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
880 "$Rn.addr = $wb", []> {
884 def VST1d8T : VST1D3<{0,0,0,?}, "8">;
885 def VST1d16T : VST1D3<{0,1,0,?}, "16">;
886 def VST1d32T : VST1D3<{1,0,0,?}, "32">;
887 def VST1d64T : VST1D3<{1,1,0,?}, "64">;
889 def VST1d8T_UPD : VST1D3WB<{0,0,0,?}, "8">;
890 def VST1d16T_UPD : VST1D3WB<{0,1,0,?}, "16">;
891 def VST1d32T_UPD : VST1D3WB<{1,0,0,?}, "32">;
892 def VST1d64T_UPD : VST1D3WB<{1,1,0,?}, "64">;
894 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
895 def VST1d64TPseudo_UPD : VSTQQWBPseudo<IIC_VST1x3u>;
897 // ...with 4 registers (some of these are only for the disassembler):
898 class VST1D4<bits<4> op7_4, string Dt>
899 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
900 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
901 IIC_VST1x4, "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", "",
904 let Inst{5-4} = Rn{5-4};
906 class VST1D4WB<bits<4> op7_4, string Dt>
907 : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
908 (ins addrmode6:$Rn, am6offset:$Rm,
909 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST1x4u,
910 "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
911 "$Rn.addr = $wb", []> {
912 let Inst{5-4} = Rn{5-4};
915 def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
916 def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
917 def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
918 def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
920 def VST1d8Q_UPD : VST1D4WB<{0,0,?,?}, "8">;
921 def VST1d16Q_UPD : VST1D4WB<{0,1,?,?}, "16">;
922 def VST1d32Q_UPD : VST1D4WB<{1,0,?,?}, "32">;
923 def VST1d64Q_UPD : VST1D4WB<{1,1,?,?}, "64">;
925 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
926 def VST1d64QPseudo_UPD : VSTQQWBPseudo<IIC_VST1x4u>;
928 // VST2 : Vector Store (multiple 2-element structures)
929 class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
930 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
931 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2),
932 IIC_VST2, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
934 let Inst{5-4} = Rn{5-4};
936 class VST2Q<bits<4> op7_4, string Dt>
937 : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
938 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
939 IIC_VST2x2, "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
942 let Inst{5-4} = Rn{5-4};
945 def VST2d8 : VST2D<0b1000, {0,0,?,?}, "8">;
946 def VST2d16 : VST2D<0b1000, {0,1,?,?}, "16">;
947 def VST2d32 : VST2D<0b1000, {1,0,?,?}, "32">;
949 def VST2q8 : VST2Q<{0,0,?,?}, "8">;
950 def VST2q16 : VST2Q<{0,1,?,?}, "16">;
951 def VST2q32 : VST2Q<{1,0,?,?}, "32">;
953 def VST2d8Pseudo : VSTQPseudo<IIC_VST2>;
954 def VST2d16Pseudo : VSTQPseudo<IIC_VST2>;
955 def VST2d32Pseudo : VSTQPseudo<IIC_VST2>;
957 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
958 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
959 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
961 // ...with address register writeback:
962 class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
963 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
964 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
965 IIC_VST2u, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
966 "$Rn.addr = $wb", []> {
967 let Inst{5-4} = Rn{5-4};
969 class VST2QWB<bits<4> op7_4, string Dt>
970 : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
971 (ins addrmode6:$Rn, am6offset:$Rm,
972 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST2x2u,
973 "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
974 "$Rn.addr = $wb", []> {
975 let Inst{5-4} = Rn{5-4};
978 def VST2d8_UPD : VST2DWB<0b1000, {0,0,?,?}, "8">;
979 def VST2d16_UPD : VST2DWB<0b1000, {0,1,?,?}, "16">;
980 def VST2d32_UPD : VST2DWB<0b1000, {1,0,?,?}, "32">;
982 def VST2q8_UPD : VST2QWB<{0,0,?,?}, "8">;
983 def VST2q16_UPD : VST2QWB<{0,1,?,?}, "16">;
984 def VST2q32_UPD : VST2QWB<{1,0,?,?}, "32">;
986 def VST2d8Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
987 def VST2d16Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
988 def VST2d32Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
990 def VST2q8Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
991 def VST2q16Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
992 def VST2q32Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
994 // ...with double-spaced registers (for disassembly only):
995 def VST2b8 : VST2D<0b1001, {0,0,?,?}, "8">;
996 def VST2b16 : VST2D<0b1001, {0,1,?,?}, "16">;
997 def VST2b32 : VST2D<0b1001, {1,0,?,?}, "32">;
998 def VST2b8_UPD : VST2DWB<0b1001, {0,0,?,?}, "8">;
999 def VST2b16_UPD : VST2DWB<0b1001, {0,1,?,?}, "16">;
1000 def VST2b32_UPD : VST2DWB<0b1001, {1,0,?,?}, "32">;
1002 // VST3 : Vector Store (multiple 3-element structures)
1003 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1004 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1005 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1006 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1008 let Inst{4} = Rn{4};
1011 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1012 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1013 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
1015 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1016 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1017 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
1019 // ...with address register writeback:
1020 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1021 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1022 (ins addrmode6:$Rn, am6offset:$Rm,
1023 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1024 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1025 "$Rn.addr = $wb", []> {
1026 let Inst{4} = Rn{4};
1029 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1030 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1031 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
1033 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1034 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1035 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1037 // ...with double-spaced registers (non-updating versions for disassembly only):
1038 def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1039 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1040 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1041 def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1042 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1043 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
1045 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1046 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1047 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1049 // ...alternate versions to be allocated odd register numbers:
1050 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1051 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1052 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1054 // VST4 : Vector Store (multiple 4-element structures)
1055 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1056 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1057 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1058 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1061 let Inst{5-4} = Rn{5-4};
1064 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1065 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1066 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
1068 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1069 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1070 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
1072 // ...with address register writeback:
1073 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1074 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1075 (ins addrmode6:$Rn, am6offset:$Rm,
1076 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1077 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1078 "$Rn.addr = $wb", []> {
1079 let Inst{5-4} = Rn{5-4};
1082 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
1083 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
1084 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
1086 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1087 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1088 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1090 // ...with double-spaced registers (non-updating versions for disassembly only):
1091 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
1092 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
1093 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
1094 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
1095 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
1096 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
1098 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1099 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1100 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1102 // ...alternate versions to be allocated odd register numbers:
1103 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1104 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1105 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1107 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1109 // Classes for VST*LN pseudo-instructions with multi-register operands.
1110 // These are expanded to real instructions after register allocation.
1111 class VSTQLNPseudo<InstrItinClass itin>
1112 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1114 class VSTQLNWBPseudo<InstrItinClass itin>
1115 : PseudoNLdSt<(outs GPR:$wb),
1116 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1117 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1118 class VSTQQLNPseudo<InstrItinClass itin>
1119 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1121 class VSTQQLNWBPseudo<InstrItinClass itin>
1122 : PseudoNLdSt<(outs GPR:$wb),
1123 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1124 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1125 class VSTQQQQLNPseudo<InstrItinClass itin>
1126 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1128 class VSTQQQQLNWBPseudo<InstrItinClass itin>
1129 : PseudoNLdSt<(outs GPR:$wb),
1130 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1131 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1133 // VST1LN : Vector Store (single element from one lane)
1134 class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1135 PatFrag StoreOp, SDNode ExtractOp>
1136 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1137 (ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane),
1138 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1139 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6:$Rn)]> {
1142 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1143 : VSTQLNPseudo<IIC_VST1ln> {
1144 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1148 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
1150 let Inst{7-5} = lane{2-0};
1152 def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
1154 let Inst{7-6} = lane{1-0};
1155 let Inst{4} = Rn{5};
1157 def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt> {
1158 let Inst{7} = lane{0};
1159 let Inst{5-4} = Rn{5-4};
1162 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
1163 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
1164 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
1166 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1168 // ...with address register writeback:
1169 class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1170 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1171 (ins addrmode6:$Rn, am6offset:$Rm,
1172 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
1173 "\\{$Vd[$lane]\\}, $Rn$Rm",
1174 "$Rn.addr = $wb", []>;
1176 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8"> {
1177 let Inst{7-5} = lane{2-0};
1179 def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16"> {
1180 let Inst{7-6} = lane{1-0};
1181 let Inst{4} = Rn{5};
1183 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32"> {
1184 let Inst{7} = lane{0};
1185 let Inst{5-4} = Rn{5-4};
1188 def VST1LNq8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST1lnu>;
1189 def VST1LNq16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST1lnu>;
1190 def VST1LNq32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST1lnu>;
1192 // VST2LN : Vector Store (single 2-element structure from one lane)
1193 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1194 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1195 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
1196 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
1199 let Inst{4} = Rn{4};
1202 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
1203 let Inst{7-5} = lane{2-0};
1205 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
1206 let Inst{7-6} = lane{1-0};
1208 def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
1209 let Inst{7} = lane{0};
1212 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1213 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1214 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1216 // ...with double-spaced registers:
1217 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
1218 let Inst{7-6} = lane{1-0};
1219 let Inst{4} = Rn{4};
1221 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
1222 let Inst{7} = lane{0};
1223 let Inst{4} = Rn{4};
1226 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1227 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1229 // ...with address register writeback:
1230 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1231 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1232 (ins addrmode6:$addr, am6offset:$offset,
1233 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
1234 "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset",
1235 "$addr.addr = $wb", []> {
1236 let Inst{4} = Rn{4};
1239 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
1240 let Inst{7-5} = lane{2-0};
1242 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
1243 let Inst{7-6} = lane{1-0};
1245 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
1246 let Inst{7} = lane{0};
1249 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1250 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1251 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1253 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
1254 let Inst{7-6} = lane{1-0};
1256 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
1257 let Inst{7} = lane{0};
1260 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1261 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1263 // VST3LN : Vector Store (single 3-element structure from one lane)
1264 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1265 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1266 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
1267 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
1268 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
1272 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
1273 let Inst{7-5} = lane{2-0};
1275 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
1276 let Inst{7-6} = lane{1-0};
1278 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
1279 let Inst{7} = lane{0};
1282 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1283 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1284 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1286 // ...with double-spaced registers:
1287 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
1288 let Inst{7-6} = lane{1-0};
1290 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
1291 let Inst{7} = lane{0};
1294 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1295 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1297 // ...with address register writeback:
1298 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1299 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1300 (ins addrmode6:$Rn, am6offset:$Rm,
1301 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1302 IIC_VST3lnu, "vst3", Dt,
1303 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
1304 "$Rn.addr = $wb", []>;
1306 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
1307 let Inst{7-5} = lane{2-0};
1309 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
1310 let Inst{7-6} = lane{1-0};
1312 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
1313 let Inst{7} = lane{0};
1316 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1317 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1318 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1320 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
1321 let Inst{7-6} = lane{1-0};
1323 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
1324 let Inst{7} = lane{0};
1327 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1328 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1330 // VST4LN : Vector Store (single 4-element structure from one lane)
1331 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1332 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1333 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
1334 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
1335 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
1338 let Inst{4} = Rn{4};
1341 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
1342 let Inst{7-5} = lane{2-0};
1344 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
1345 let Inst{7-6} = lane{1-0};
1347 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
1348 let Inst{7} = lane{0};
1349 let Inst{5} = Rn{5};
1352 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1353 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1354 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1356 // ...with double-spaced registers:
1357 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
1358 let Inst{7-6} = lane{1-0};
1360 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
1361 let Inst{7} = lane{0};
1362 let Inst{5} = Rn{5};
1365 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1366 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1368 // ...with address register writeback:
1369 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1370 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1371 (ins addrmode6:$Rn, am6offset:$Rm,
1372 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1373 IIC_VST4lnu, "vst4", Dt,
1374 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
1375 "$Rn.addr = $wb", []> {
1376 let Inst{4} = Rn{4};
1379 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
1380 let Inst{7-5} = lane{2-0};
1382 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
1383 let Inst{7-6} = lane{1-0};
1385 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
1386 let Inst{7} = lane{0};
1387 let Inst{5} = Rn{5};
1390 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1391 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1392 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1394 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
1395 let Inst{7-6} = lane{1-0};
1397 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
1398 let Inst{7} = lane{0};
1399 let Inst{5} = Rn{5};
1402 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1403 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1405 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1408 //===----------------------------------------------------------------------===//
1409 // NEON pattern fragments
1410 //===----------------------------------------------------------------------===//
1412 // Extract D sub-registers of Q registers.
1413 def DSubReg_i8_reg : SDNodeXForm<imm, [{
1414 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1415 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
1417 def DSubReg_i16_reg : SDNodeXForm<imm, [{
1418 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1419 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
1421 def DSubReg_i32_reg : SDNodeXForm<imm, [{
1422 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1423 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
1425 def DSubReg_f64_reg : SDNodeXForm<imm, [{
1426 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1427 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
1430 // Extract S sub-registers of Q/D registers.
1431 def SSubReg_f32_reg : SDNodeXForm<imm, [{
1432 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
1433 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
1436 // Translate lane numbers from Q registers to D subregs.
1437 def SubReg_i8_lane : SDNodeXForm<imm, [{
1438 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
1440 def SubReg_i16_lane : SDNodeXForm<imm, [{
1441 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
1443 def SubReg_i32_lane : SDNodeXForm<imm, [{
1444 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
1447 //===----------------------------------------------------------------------===//
1448 // Instruction Classes
1449 //===----------------------------------------------------------------------===//
1451 // Basic 2-register operations: single-, double- and quad-register.
1452 class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1453 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1454 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1455 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
1456 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
1457 IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
1458 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1459 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1460 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1461 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1462 (ins DPR:$src), IIC_VUNAD, OpcodeStr, Dt,"$dst, $src", "",
1463 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
1464 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1465 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1466 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1467 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1468 (ins QPR:$src), IIC_VUNAQ, OpcodeStr, Dt,"$dst, $src", "",
1469 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
1471 // Basic 2-register intrinsics, both double- and quad-register.
1472 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1473 bits<2> op17_16, bits<5> op11_7, bit op4,
1474 InstrItinClass itin, string OpcodeStr, string Dt,
1475 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1476 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1477 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1478 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
1479 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1480 bits<2> op17_16, bits<5> op11_7, bit op4,
1481 InstrItinClass itin, string OpcodeStr, string Dt,
1482 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1483 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1484 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1485 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
1487 // Narrow 2-register operations.
1488 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1489 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1490 InstrItinClass itin, string OpcodeStr, string Dt,
1491 ValueType TyD, ValueType TyQ, SDNode OpNode>
1492 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
1493 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1494 [(set DPR:$dst, (TyD (OpNode (TyQ QPR:$src))))]>;
1496 // Narrow 2-register intrinsics.
1497 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1498 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1499 InstrItinClass itin, string OpcodeStr, string Dt,
1500 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
1501 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
1502 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1503 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
1505 // Long 2-register operations (currently only used for VMOVL).
1506 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1507 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1508 InstrItinClass itin, string OpcodeStr, string Dt,
1509 ValueType TyQ, ValueType TyD, SDNode OpNode>
1510 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$dst),
1511 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1512 [(set QPR:$dst, (TyQ (OpNode (TyD DPR:$src))))]>;
1514 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
1515 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
1516 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
1517 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
1518 OpcodeStr, Dt, "$dst1, $dst2",
1519 "$src1 = $dst1, $src2 = $dst2", []>;
1520 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
1521 InstrItinClass itin, string OpcodeStr, string Dt>
1522 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
1523 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$dst1, $dst2",
1524 "$src1 = $dst1, $src2 = $dst2", []>;
1526 // Basic 3-register operations: single-, double- and quad-register.
1527 class N3VS<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1528 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1529 SDNode OpNode, bit Commutable>
1530 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1531 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm,
1532 IIC_VBIND, OpcodeStr, Dt, "$dst, $src1, $src2", "", []> {
1533 let isCommutable = Commutable;
1536 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1537 InstrItinClass itin, string OpcodeStr, string Dt,
1538 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1539 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1540 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1541 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1542 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
1543 let isCommutable = Commutable;
1545 // Same as N3VD but no data type.
1546 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1547 InstrItinClass itin, string OpcodeStr,
1548 ValueType ResTy, ValueType OpTy,
1549 SDNode OpNode, bit Commutable>
1550 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
1551 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1552 OpcodeStr, "$dst, $src1, $src2", "",
1553 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]>{
1554 let isCommutable = Commutable;
1557 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
1558 InstrItinClass itin, string OpcodeStr, string Dt,
1559 ValueType Ty, SDNode ShOp>
1560 : N3V<0, 1, op21_20, op11_8, 1, 0,
1561 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1562 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1563 [(set (Ty DPR:$dst),
1564 (Ty (ShOp (Ty DPR:$src1),
1565 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),imm:$lane)))))]> {
1566 let isCommutable = 0;
1568 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
1569 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1570 : N3V<0, 1, op21_20, op11_8, 1, 0,
1571 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1572 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$dst, $src1, $src2[$lane]","",
1573 [(set (Ty DPR:$dst),
1574 (Ty (ShOp (Ty DPR:$src1),
1575 (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
1576 let isCommutable = 0;
1579 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1580 InstrItinClass itin, string OpcodeStr, string Dt,
1581 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1582 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1583 (outs QPR:$Qd), (ins QPR:$Qn, QPR:$Qm), N3RegFrm, itin,
1584 OpcodeStr, Dt, "$Qd, $Qn, $Qm", "",
1585 [(set QPR:$Qd, (ResTy (OpNode (OpTy QPR:$Qn), (OpTy QPR:$Qm))))]> {
1586 let isCommutable = Commutable;
1588 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1589 InstrItinClass itin, string OpcodeStr,
1590 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1591 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
1592 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, itin,
1593 OpcodeStr, "$dst, $src1, $src2", "",
1594 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]>{
1595 let isCommutable = Commutable;
1597 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
1598 InstrItinClass itin, string OpcodeStr, string Dt,
1599 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1600 : N3V<1, 1, op21_20, op11_8, 1, 0,
1601 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1602 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1603 [(set (ResTy QPR:$dst),
1604 (ResTy (ShOp (ResTy QPR:$src1),
1605 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1607 let isCommutable = 0;
1609 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
1610 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1611 : N3V<1, 1, op21_20, op11_8, 1, 0,
1612 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1613 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$dst, $src1, $src2[$lane]","",
1614 [(set (ResTy QPR:$dst),
1615 (ResTy (ShOp (ResTy QPR:$src1),
1616 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
1618 let isCommutable = 0;
1621 // Basic 3-register intrinsics, both double- and quad-register.
1622 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1623 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1624 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1625 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1626 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
1627 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1628 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
1629 let isCommutable = Commutable;
1631 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1632 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1633 : N3V<0, 1, op21_20, op11_8, 1, 0,
1634 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1635 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1636 [(set (Ty DPR:$dst),
1637 (Ty (IntOp (Ty DPR:$src1),
1638 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
1640 let isCommutable = 0;
1642 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1643 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1644 : N3V<0, 1, op21_20, op11_8, 1, 0,
1645 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1646 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1647 [(set (Ty DPR:$dst),
1648 (Ty (IntOp (Ty DPR:$src1),
1649 (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
1650 let isCommutable = 0;
1652 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1653 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1654 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1655 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1656 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
1657 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
1658 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
1659 let isCommutable = 0;
1662 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1663 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1664 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1665 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1666 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
1667 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1668 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
1669 let isCommutable = Commutable;
1671 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1672 string OpcodeStr, string Dt,
1673 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1674 : N3V<1, 1, op21_20, op11_8, 1, 0,
1675 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1676 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1677 [(set (ResTy QPR:$dst),
1678 (ResTy (IntOp (ResTy QPR:$src1),
1679 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1681 let isCommutable = 0;
1683 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1684 string OpcodeStr, string Dt,
1685 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1686 : N3V<1, 1, op21_20, op11_8, 1, 0,
1687 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1688 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1689 [(set (ResTy QPR:$dst),
1690 (ResTy (IntOp (ResTy QPR:$src1),
1691 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
1693 let isCommutable = 0;
1695 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1696 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1697 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1698 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1699 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
1700 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
1701 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
1702 let isCommutable = 0;
1705 // Multiply-Add/Sub operations: single-, double- and quad-register.
1706 class N3VSMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1707 InstrItinClass itin, string OpcodeStr, string Dt,
1708 ValueType Ty, SDNode MulOp, SDNode OpNode>
1709 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1710 (outs DPR_VFP2:$dst),
1711 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), N3RegFrm, itin,
1712 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst", []>;
1714 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1715 InstrItinClass itin, string OpcodeStr, string Dt,
1716 ValueType Ty, SDNode MulOp, SDNode OpNode>
1717 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1718 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1719 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1720 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
1721 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
1723 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1724 string OpcodeStr, string Dt,
1725 ValueType Ty, SDNode MulOp, SDNode ShOp>
1726 : N3V<0, 1, op21_20, op11_8, 1, 0,
1728 (ins DPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1730 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1731 [(set (Ty DPR:$dst),
1732 (Ty (ShOp (Ty DPR:$src1),
1733 (Ty (MulOp DPR:$src2,
1734 (Ty (NEONvduplane (Ty DPR_VFP2:$src3),
1736 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1737 string OpcodeStr, string Dt,
1738 ValueType Ty, SDNode MulOp, SDNode ShOp>
1739 : N3V<0, 1, op21_20, op11_8, 1, 0,
1741 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1743 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
1745 (Ty (ShOp (Ty DPR:$src1),
1747 (Ty (NEONvduplane (Ty DPR_8:$Vm),
1750 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1751 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
1752 SDNode MulOp, SDNode OpNode>
1753 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1754 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1755 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1756 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
1757 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
1758 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1759 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1760 SDNode MulOp, SDNode ShOp>
1761 : N3V<1, 1, op21_20, op11_8, 1, 0,
1763 (ins QPR:$src1, QPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1765 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1766 [(set (ResTy QPR:$dst),
1767 (ResTy (ShOp (ResTy QPR:$src1),
1768 (ResTy (MulOp QPR:$src2,
1769 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src3),
1771 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1772 string OpcodeStr, string Dt,
1773 ValueType ResTy, ValueType OpTy,
1774 SDNode MulOp, SDNode ShOp>
1775 : N3V<1, 1, op21_20, op11_8, 1, 0,
1777 (ins QPR:$src1, QPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1779 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1780 [(set (ResTy QPR:$dst),
1781 (ResTy (ShOp (ResTy QPR:$src1),
1782 (ResTy (MulOp QPR:$src2,
1783 (ResTy (NEONvduplane (OpTy DPR_8:$src3),
1786 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
1787 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1788 InstrItinClass itin, string OpcodeStr, string Dt,
1789 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
1790 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1791 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1792 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1793 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
1794 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
1795 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1796 InstrItinClass itin, string OpcodeStr, string Dt,
1797 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
1798 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1799 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1800 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1801 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
1802 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
1804 // Neon 3-argument intrinsics, both double- and quad-register.
1805 // The destination register is also used as the first source operand register.
1806 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1807 InstrItinClass itin, string OpcodeStr, string Dt,
1808 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1809 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1810 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1811 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1812 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
1813 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
1814 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1815 InstrItinClass itin, string OpcodeStr, string Dt,
1816 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1817 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1818 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), N3RegFrm, itin,
1819 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1820 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
1821 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
1823 // Long Multiply-Add/Sub operations.
1824 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1825 InstrItinClass itin, string OpcodeStr, string Dt,
1826 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
1827 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1828 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1829 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1830 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
1831 (TyQ (MulOp (TyD DPR:$Vn),
1832 (TyD DPR:$Vm)))))]>;
1833 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
1834 InstrItinClass itin, string OpcodeStr, string Dt,
1835 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
1836 : N3V<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$dst),
1837 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1839 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1841 (OpNode (TyQ QPR:$src1),
1842 (TyQ (MulOp (TyD DPR:$src2),
1843 (TyD (NEONvduplane (TyD DPR_VFP2:$src3),
1845 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1846 InstrItinClass itin, string OpcodeStr, string Dt,
1847 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
1848 : N3V<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$dst),
1849 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1851 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1853 (OpNode (TyQ QPR:$src1),
1854 (TyQ (MulOp (TyD DPR:$src2),
1855 (TyD (NEONvduplane (TyD DPR_8:$src3),
1858 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
1859 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1860 InstrItinClass itin, string OpcodeStr, string Dt,
1861 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
1863 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1864 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1865 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1866 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
1867 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
1868 (TyD DPR:$Vm)))))))]>;
1870 // Neon Long 3-argument intrinsic. The destination register is
1871 // a quad-register and is also used as the first source operand register.
1872 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1873 InstrItinClass itin, string OpcodeStr, string Dt,
1874 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
1875 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1876 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1877 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1879 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
1880 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1881 string OpcodeStr, string Dt,
1882 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1883 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1885 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1887 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1888 [(set (ResTy QPR:$dst),
1889 (ResTy (IntOp (ResTy QPR:$src1),
1891 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src3),
1893 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1894 InstrItinClass itin, string OpcodeStr, string Dt,
1895 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1896 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1898 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1900 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1901 [(set (ResTy QPR:$dst),
1902 (ResTy (IntOp (ResTy QPR:$src1),
1904 (OpTy (NEONvduplane (OpTy DPR_8:$src3),
1907 // Narrowing 3-register intrinsics.
1908 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1909 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
1910 Intrinsic IntOp, bit Commutable>
1911 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1912 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINi4D,
1913 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1914 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
1915 let isCommutable = Commutable;
1918 // Long 3-register operations.
1919 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1920 InstrItinClass itin, string OpcodeStr, string Dt,
1921 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
1922 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1923 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1924 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1925 [(set QPR:$dst, (TyQ (OpNode (TyD DPR:$src1), (TyD DPR:$src2))))]> {
1926 let isCommutable = Commutable;
1928 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
1929 InstrItinClass itin, string OpcodeStr, string Dt,
1930 ValueType TyQ, ValueType TyD, SDNode OpNode>
1931 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1932 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1933 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1935 (TyQ (OpNode (TyD DPR:$src1),
1936 (TyD (NEONvduplane (TyD DPR_VFP2:$src2),imm:$lane)))))]>;
1937 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1938 InstrItinClass itin, string OpcodeStr, string Dt,
1939 ValueType TyQ, ValueType TyD, SDNode OpNode>
1940 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1941 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1942 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1944 (TyQ (OpNode (TyD DPR:$src1),
1945 (TyD (NEONvduplane (TyD DPR_8:$src2), imm:$lane)))))]>;
1947 // Long 3-register operations with explicitly extended operands.
1948 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1949 InstrItinClass itin, string OpcodeStr, string Dt,
1950 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
1952 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1953 (outs QPR:$Qd), (ins DPR:$Dn, DPR:$Dm), N3RegFrm, itin,
1954 OpcodeStr, Dt, "$Qd, $Dn, $Dm", "",
1955 [(set QPR:$Qd, (OpNode (TyQ (ExtOp (TyD DPR:$Dn))),
1956 (TyQ (ExtOp (TyD DPR:$Dm)))))]> {
1957 let isCommutable = Commutable;
1960 // Long 3-register intrinsics with explicit extend (VABDL).
1961 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1962 InstrItinClass itin, string OpcodeStr, string Dt,
1963 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
1965 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1966 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1967 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1968 [(set QPR:$dst, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$src1),
1969 (TyD DPR:$src2))))))]> {
1970 let isCommutable = Commutable;
1973 // Long 3-register intrinsics.
1974 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1975 InstrItinClass itin, string OpcodeStr, string Dt,
1976 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
1977 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1978 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1979 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1980 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
1981 let isCommutable = Commutable;
1983 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1984 string OpcodeStr, string Dt,
1985 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1986 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1987 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1988 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1989 [(set (ResTy QPR:$dst),
1990 (ResTy (IntOp (OpTy DPR:$src1),
1991 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1993 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1994 InstrItinClass itin, string OpcodeStr, string Dt,
1995 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1996 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1997 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1998 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1999 [(set (ResTy QPR:$dst),
2000 (ResTy (IntOp (OpTy DPR:$src1),
2001 (OpTy (NEONvduplane (OpTy DPR_8:$src2),
2004 // Wide 3-register operations.
2005 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2006 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
2007 SDNode OpNode, SDNode ExtOp, bit Commutable>
2008 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2009 (outs QPR:$Qd), (ins QPR:$Qn, DPR:$Dm), N3RegFrm, IIC_VSUBiD,
2010 OpcodeStr, Dt, "$Qd, $Qn, $Dm", "",
2011 [(set QPR:$Qd, (OpNode (TyQ QPR:$Qn),
2012 (TyQ (ExtOp (TyD DPR:$Dm)))))]> {
2013 let isCommutable = Commutable;
2016 // Pairwise long 2-register intrinsics, both double- and quad-register.
2017 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2018 bits<2> op17_16, bits<5> op11_7, bit op4,
2019 string OpcodeStr, string Dt,
2020 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2021 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
2022 (ins DPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
2023 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
2024 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2025 bits<2> op17_16, bits<5> op11_7, bit op4,
2026 string OpcodeStr, string Dt,
2027 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2028 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
2029 (ins QPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
2030 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
2032 // Pairwise long 2-register accumulate intrinsics,
2033 // both double- and quad-register.
2034 // The destination register is also used as the first source operand register.
2035 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2036 bits<2> op17_16, bits<5> op11_7, bit op4,
2037 string OpcodeStr, string Dt,
2038 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2039 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
2040 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
2041 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2042 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
2043 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2044 bits<2> op17_16, bits<5> op11_7, bit op4,
2045 string OpcodeStr, string Dt,
2046 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2047 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
2048 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
2049 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2050 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
2052 // Shift by immediate,
2053 // both double- and quad-register.
2054 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2055 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2056 ValueType Ty, SDNode OpNode>
2057 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2058 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), f, itin,
2059 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
2060 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
2061 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2062 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2063 ValueType Ty, SDNode OpNode>
2064 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2065 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), f, itin,
2066 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
2067 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
2069 // Long shift by immediate.
2070 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2071 string OpcodeStr, string Dt,
2072 ValueType ResTy, ValueType OpTy, SDNode OpNode>
2073 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2074 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), N2RegVShLFrm,
2075 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
2076 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
2077 (i32 imm:$SIMM))))]>;
2079 // Narrow shift by immediate.
2080 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2081 InstrItinClass itin, string OpcodeStr, string Dt,
2082 ValueType ResTy, ValueType OpTy, SDNode OpNode>
2083 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2084 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), N2RegVShRFrm, itin,
2085 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
2086 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
2087 (i32 imm:$SIMM))))]>;
2089 // Shift right by immediate and accumulate,
2090 // both double- and quad-register.
2091 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2092 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2093 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2094 (ins DPR:$src1, DPR:$Vm, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2095 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2096 [(set DPR:$Vd, (Ty (add DPR:$src1,
2097 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
2098 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2099 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2100 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2101 (ins QPR:$src1, QPR:$Vm, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2102 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2103 [(set QPR:$Vd, (Ty (add QPR:$src1,
2104 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
2106 // Shift by immediate and insert,
2107 // both double- and quad-register.
2108 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2109 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
2110 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2111 (ins DPR:$src1, DPR:$Vm, i32imm:$SIMM), f, IIC_VSHLiD,
2112 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2113 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
2114 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2115 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
2116 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2117 (ins QPR:$src1, QPR:$Vm, i32imm:$SIMM), f, IIC_VSHLiQ,
2118 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2119 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
2121 // Convert, with fractional bits immediate,
2122 // both double- and quad-register.
2123 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2124 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2126 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2127 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2128 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2129 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
2130 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2131 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2133 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2134 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2135 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2136 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
2138 //===----------------------------------------------------------------------===//
2140 //===----------------------------------------------------------------------===//
2142 // Abbreviations used in multiclass suffixes:
2143 // Q = quarter int (8 bit) elements
2144 // H = half int (16 bit) elements
2145 // S = single int (32 bit) elements
2146 // D = double int (64 bit) elements
2148 // Neon 2-register vector operations -- for disassembly only.
2150 // First with only element sizes of 8, 16 and 32 bits:
2151 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2152 bits<5> op11_7, bit op4, string opc, string Dt,
2154 // 64-bit vector types.
2155 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
2156 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
2157 opc, !strconcat(Dt, "8"), asm, "", []>;
2158 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
2159 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
2160 opc, !strconcat(Dt, "16"), asm, "", []>;
2161 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2162 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
2163 opc, !strconcat(Dt, "32"), asm, "", []>;
2164 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2165 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
2166 opc, "f32", asm, "", []> {
2167 let Inst{10} = 1; // overwrite F = 1
2170 // 128-bit vector types.
2171 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
2172 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
2173 opc, !strconcat(Dt, "8"), asm, "", []>;
2174 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
2175 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
2176 opc, !strconcat(Dt, "16"), asm, "", []>;
2177 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2178 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
2179 opc, !strconcat(Dt, "32"), asm, "", []>;
2180 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2181 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
2182 opc, "f32", asm, "", []> {
2183 let Inst{10} = 1; // overwrite F = 1
2187 // Neon 3-register vector operations.
2189 // First with only element sizes of 8, 16 and 32 bits:
2190 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2191 InstrItinClass itinD16, InstrItinClass itinD32,
2192 InstrItinClass itinQ16, InstrItinClass itinQ32,
2193 string OpcodeStr, string Dt,
2194 SDNode OpNode, bit Commutable = 0> {
2195 // 64-bit vector types.
2196 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
2197 OpcodeStr, !strconcat(Dt, "8"),
2198 v8i8, v8i8, OpNode, Commutable>;
2199 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
2200 OpcodeStr, !strconcat(Dt, "16"),
2201 v4i16, v4i16, OpNode, Commutable>;
2202 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
2203 OpcodeStr, !strconcat(Dt, "32"),
2204 v2i32, v2i32, OpNode, Commutable>;
2206 // 128-bit vector types.
2207 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
2208 OpcodeStr, !strconcat(Dt, "8"),
2209 v16i8, v16i8, OpNode, Commutable>;
2210 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
2211 OpcodeStr, !strconcat(Dt, "16"),
2212 v8i16, v8i16, OpNode, Commutable>;
2213 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
2214 OpcodeStr, !strconcat(Dt, "32"),
2215 v4i32, v4i32, OpNode, Commutable>;
2218 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
2219 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2221 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
2223 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2224 v8i16, v4i16, ShOp>;
2225 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
2226 v4i32, v2i32, ShOp>;
2229 // ....then also with element size 64 bits:
2230 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2231 InstrItinClass itinD, InstrItinClass itinQ,
2232 string OpcodeStr, string Dt,
2233 SDNode OpNode, bit Commutable = 0>
2234 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
2235 OpcodeStr, Dt, OpNode, Commutable> {
2236 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
2237 OpcodeStr, !strconcat(Dt, "64"),
2238 v1i64, v1i64, OpNode, Commutable>;
2239 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
2240 OpcodeStr, !strconcat(Dt, "64"),
2241 v2i64, v2i64, OpNode, Commutable>;
2245 // Neon Narrowing 2-register vector operations,
2246 // source operand element sizes of 16, 32 and 64 bits:
2247 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2248 bits<5> op11_7, bit op6, bit op4,
2249 InstrItinClass itin, string OpcodeStr, string Dt,
2251 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2252 itin, OpcodeStr, !strconcat(Dt, "16"),
2253 v8i8, v8i16, OpNode>;
2254 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2255 itin, OpcodeStr, !strconcat(Dt, "32"),
2256 v4i16, v4i32, OpNode>;
2257 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2258 itin, OpcodeStr, !strconcat(Dt, "64"),
2259 v2i32, v2i64, OpNode>;
2262 // Neon Narrowing 2-register vector intrinsics,
2263 // source operand element sizes of 16, 32 and 64 bits:
2264 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2265 bits<5> op11_7, bit op6, bit op4,
2266 InstrItinClass itin, string OpcodeStr, string Dt,
2268 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2269 itin, OpcodeStr, !strconcat(Dt, "16"),
2270 v8i8, v8i16, IntOp>;
2271 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2272 itin, OpcodeStr, !strconcat(Dt, "32"),
2273 v4i16, v4i32, IntOp>;
2274 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2275 itin, OpcodeStr, !strconcat(Dt, "64"),
2276 v2i32, v2i64, IntOp>;
2280 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
2281 // source operand element sizes of 16, 32 and 64 bits:
2282 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
2283 string OpcodeStr, string Dt, SDNode OpNode> {
2284 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2285 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
2286 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2287 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2288 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2289 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2293 // Neon 3-register vector intrinsics.
2295 // First with only element sizes of 16 and 32 bits:
2296 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2297 InstrItinClass itinD16, InstrItinClass itinD32,
2298 InstrItinClass itinQ16, InstrItinClass itinQ32,
2299 string OpcodeStr, string Dt,
2300 Intrinsic IntOp, bit Commutable = 0> {
2301 // 64-bit vector types.
2302 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
2303 OpcodeStr, !strconcat(Dt, "16"),
2304 v4i16, v4i16, IntOp, Commutable>;
2305 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
2306 OpcodeStr, !strconcat(Dt, "32"),
2307 v2i32, v2i32, IntOp, Commutable>;
2309 // 128-bit vector types.
2310 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2311 OpcodeStr, !strconcat(Dt, "16"),
2312 v8i16, v8i16, IntOp, Commutable>;
2313 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2314 OpcodeStr, !strconcat(Dt, "32"),
2315 v4i32, v4i32, IntOp, Commutable>;
2317 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2318 InstrItinClass itinD16, InstrItinClass itinD32,
2319 InstrItinClass itinQ16, InstrItinClass itinQ32,
2320 string OpcodeStr, string Dt,
2322 // 64-bit vector types.
2323 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
2324 OpcodeStr, !strconcat(Dt, "16"),
2325 v4i16, v4i16, IntOp>;
2326 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
2327 OpcodeStr, !strconcat(Dt, "32"),
2328 v2i32, v2i32, IntOp>;
2330 // 128-bit vector types.
2331 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2332 OpcodeStr, !strconcat(Dt, "16"),
2333 v8i16, v8i16, IntOp>;
2334 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2335 OpcodeStr, !strconcat(Dt, "32"),
2336 v4i32, v4i32, IntOp>;
2339 multiclass N3VIntSL_HS<bits<4> op11_8,
2340 InstrItinClass itinD16, InstrItinClass itinD32,
2341 InstrItinClass itinQ16, InstrItinClass itinQ32,
2342 string OpcodeStr, string Dt, Intrinsic IntOp> {
2343 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
2344 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
2345 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
2346 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
2347 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
2348 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
2349 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
2350 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
2353 // ....then also with element size of 8 bits:
2354 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2355 InstrItinClass itinD16, InstrItinClass itinD32,
2356 InstrItinClass itinQ16, InstrItinClass itinQ32,
2357 string OpcodeStr, string Dt,
2358 Intrinsic IntOp, bit Commutable = 0>
2359 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2360 OpcodeStr, Dt, IntOp, Commutable> {
2361 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
2362 OpcodeStr, !strconcat(Dt, "8"),
2363 v8i8, v8i8, IntOp, Commutable>;
2364 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2365 OpcodeStr, !strconcat(Dt, "8"),
2366 v16i8, v16i8, IntOp, Commutable>;
2368 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2369 InstrItinClass itinD16, InstrItinClass itinD32,
2370 InstrItinClass itinQ16, InstrItinClass itinQ32,
2371 string OpcodeStr, string Dt,
2373 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2374 OpcodeStr, Dt, IntOp> {
2375 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
2376 OpcodeStr, !strconcat(Dt, "8"),
2378 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2379 OpcodeStr, !strconcat(Dt, "8"),
2380 v16i8, v16i8, IntOp>;
2384 // ....then also with element size of 64 bits:
2385 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2386 InstrItinClass itinD16, InstrItinClass itinD32,
2387 InstrItinClass itinQ16, InstrItinClass itinQ32,
2388 string OpcodeStr, string Dt,
2389 Intrinsic IntOp, bit Commutable = 0>
2390 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2391 OpcodeStr, Dt, IntOp, Commutable> {
2392 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
2393 OpcodeStr, !strconcat(Dt, "64"),
2394 v1i64, v1i64, IntOp, Commutable>;
2395 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2396 OpcodeStr, !strconcat(Dt, "64"),
2397 v2i64, v2i64, IntOp, Commutable>;
2399 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2400 InstrItinClass itinD16, InstrItinClass itinD32,
2401 InstrItinClass itinQ16, InstrItinClass itinQ32,
2402 string OpcodeStr, string Dt,
2404 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2405 OpcodeStr, Dt, IntOp> {
2406 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
2407 OpcodeStr, !strconcat(Dt, "64"),
2408 v1i64, v1i64, IntOp>;
2409 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2410 OpcodeStr, !strconcat(Dt, "64"),
2411 v2i64, v2i64, IntOp>;
2414 // Neon Narrowing 3-register vector intrinsics,
2415 // source operand element sizes of 16, 32 and 64 bits:
2416 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2417 string OpcodeStr, string Dt,
2418 Intrinsic IntOp, bit Commutable = 0> {
2419 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
2420 OpcodeStr, !strconcat(Dt, "16"),
2421 v8i8, v8i16, IntOp, Commutable>;
2422 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
2423 OpcodeStr, !strconcat(Dt, "32"),
2424 v4i16, v4i32, IntOp, Commutable>;
2425 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
2426 OpcodeStr, !strconcat(Dt, "64"),
2427 v2i32, v2i64, IntOp, Commutable>;
2431 // Neon Long 3-register vector operations.
2433 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2434 InstrItinClass itin16, InstrItinClass itin32,
2435 string OpcodeStr, string Dt,
2436 SDNode OpNode, bit Commutable = 0> {
2437 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
2438 OpcodeStr, !strconcat(Dt, "8"),
2439 v8i16, v8i8, OpNode, Commutable>;
2440 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
2441 OpcodeStr, !strconcat(Dt, "16"),
2442 v4i32, v4i16, OpNode, Commutable>;
2443 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
2444 OpcodeStr, !strconcat(Dt, "32"),
2445 v2i64, v2i32, OpNode, Commutable>;
2448 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
2449 InstrItinClass itin, string OpcodeStr, string Dt,
2451 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
2452 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2453 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
2454 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2457 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2458 InstrItinClass itin16, InstrItinClass itin32,
2459 string OpcodeStr, string Dt,
2460 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2461 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
2462 OpcodeStr, !strconcat(Dt, "8"),
2463 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2464 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
2465 OpcodeStr, !strconcat(Dt, "16"),
2466 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2467 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
2468 OpcodeStr, !strconcat(Dt, "32"),
2469 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2472 // Neon Long 3-register vector intrinsics.
2474 // First with only element sizes of 16 and 32 bits:
2475 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2476 InstrItinClass itin16, InstrItinClass itin32,
2477 string OpcodeStr, string Dt,
2478 Intrinsic IntOp, bit Commutable = 0> {
2479 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
2480 OpcodeStr, !strconcat(Dt, "16"),
2481 v4i32, v4i16, IntOp, Commutable>;
2482 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
2483 OpcodeStr, !strconcat(Dt, "32"),
2484 v2i64, v2i32, IntOp, Commutable>;
2487 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
2488 InstrItinClass itin, string OpcodeStr, string Dt,
2490 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
2491 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2492 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
2493 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2496 // ....then also with element size of 8 bits:
2497 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2498 InstrItinClass itin16, InstrItinClass itin32,
2499 string OpcodeStr, string Dt,
2500 Intrinsic IntOp, bit Commutable = 0>
2501 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
2502 IntOp, Commutable> {
2503 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
2504 OpcodeStr, !strconcat(Dt, "8"),
2505 v8i16, v8i8, IntOp, Commutable>;
2508 // ....with explicit extend (VABDL).
2509 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2510 InstrItinClass itin, string OpcodeStr, string Dt,
2511 Intrinsic IntOp, SDNode ExtOp, bit Commutable = 0> {
2512 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
2513 OpcodeStr, !strconcat(Dt, "8"),
2514 v8i16, v8i8, IntOp, ExtOp, Commutable>;
2515 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
2516 OpcodeStr, !strconcat(Dt, "16"),
2517 v4i32, v4i16, IntOp, ExtOp, Commutable>;
2518 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
2519 OpcodeStr, !strconcat(Dt, "32"),
2520 v2i64, v2i32, IntOp, ExtOp, Commutable>;
2524 // Neon Wide 3-register vector intrinsics,
2525 // source operand element sizes of 8, 16 and 32 bits:
2526 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2527 string OpcodeStr, string Dt,
2528 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2529 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
2530 OpcodeStr, !strconcat(Dt, "8"),
2531 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2532 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
2533 OpcodeStr, !strconcat(Dt, "16"),
2534 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2535 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
2536 OpcodeStr, !strconcat(Dt, "32"),
2537 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2541 // Neon Multiply-Op vector operations,
2542 // element sizes of 8, 16 and 32 bits:
2543 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2544 InstrItinClass itinD16, InstrItinClass itinD32,
2545 InstrItinClass itinQ16, InstrItinClass itinQ32,
2546 string OpcodeStr, string Dt, SDNode OpNode> {
2547 // 64-bit vector types.
2548 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
2549 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
2550 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
2551 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
2552 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
2553 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
2555 // 128-bit vector types.
2556 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
2557 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
2558 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
2559 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
2560 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
2561 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
2564 multiclass N3VMulOpSL_HS<bits<4> op11_8,
2565 InstrItinClass itinD16, InstrItinClass itinD32,
2566 InstrItinClass itinQ16, InstrItinClass itinQ32,
2567 string OpcodeStr, string Dt, SDNode ShOp> {
2568 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
2569 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
2570 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
2571 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
2572 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
2573 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
2575 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
2576 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
2580 // Neon Intrinsic-Op vector operations,
2581 // element sizes of 8, 16 and 32 bits:
2582 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2583 InstrItinClass itinD, InstrItinClass itinQ,
2584 string OpcodeStr, string Dt, Intrinsic IntOp,
2586 // 64-bit vector types.
2587 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
2588 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
2589 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
2590 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
2591 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
2592 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
2594 // 128-bit vector types.
2595 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
2596 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
2597 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
2598 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
2599 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
2600 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
2603 // Neon 3-argument intrinsics,
2604 // element sizes of 8, 16 and 32 bits:
2605 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2606 InstrItinClass itinD, InstrItinClass itinQ,
2607 string OpcodeStr, string Dt, Intrinsic IntOp> {
2608 // 64-bit vector types.
2609 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
2610 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2611 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
2612 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
2613 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
2614 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
2616 // 128-bit vector types.
2617 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
2618 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
2619 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
2620 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
2621 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
2622 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
2626 // Neon Long Multiply-Op vector operations,
2627 // element sizes of 8, 16 and 32 bits:
2628 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2629 InstrItinClass itin16, InstrItinClass itin32,
2630 string OpcodeStr, string Dt, SDNode MulOp,
2632 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
2633 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
2634 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
2635 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
2636 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
2637 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
2640 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
2641 string Dt, SDNode MulOp, SDNode OpNode> {
2642 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
2643 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
2644 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
2645 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
2649 // Neon Long 3-argument intrinsics.
2651 // First with only element sizes of 16 and 32 bits:
2652 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2653 InstrItinClass itin16, InstrItinClass itin32,
2654 string OpcodeStr, string Dt, Intrinsic IntOp> {
2655 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
2656 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2657 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
2658 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2661 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
2662 string OpcodeStr, string Dt, Intrinsic IntOp> {
2663 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
2664 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
2665 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
2666 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2669 // ....then also with element size of 8 bits:
2670 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2671 InstrItinClass itin16, InstrItinClass itin32,
2672 string OpcodeStr, string Dt, Intrinsic IntOp>
2673 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
2674 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
2675 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
2678 // ....with explicit extend (VABAL).
2679 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2680 InstrItinClass itin, string OpcodeStr, string Dt,
2681 Intrinsic IntOp, SDNode ExtOp, SDNode OpNode> {
2682 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
2683 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
2684 IntOp, ExtOp, OpNode>;
2685 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
2686 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
2687 IntOp, ExtOp, OpNode>;
2688 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
2689 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
2690 IntOp, ExtOp, OpNode>;
2694 // Neon 2-register vector intrinsics,
2695 // element sizes of 8, 16 and 32 bits:
2696 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2697 bits<5> op11_7, bit op4,
2698 InstrItinClass itinD, InstrItinClass itinQ,
2699 string OpcodeStr, string Dt, Intrinsic IntOp> {
2700 // 64-bit vector types.
2701 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2702 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2703 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2704 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
2705 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2706 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
2708 // 128-bit vector types.
2709 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2710 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
2711 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2712 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
2713 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2714 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
2718 // Neon Pairwise long 2-register intrinsics,
2719 // element sizes of 8, 16 and 32 bits:
2720 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2721 bits<5> op11_7, bit op4,
2722 string OpcodeStr, string Dt, Intrinsic IntOp> {
2723 // 64-bit vector types.
2724 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2725 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
2726 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2727 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
2728 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2729 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
2731 // 128-bit vector types.
2732 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2733 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
2734 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2735 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
2736 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2737 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
2741 // Neon Pairwise long 2-register accumulate intrinsics,
2742 // element sizes of 8, 16 and 32 bits:
2743 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2744 bits<5> op11_7, bit op4,
2745 string OpcodeStr, string Dt, Intrinsic IntOp> {
2746 // 64-bit vector types.
2747 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2748 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
2749 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2750 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
2751 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2752 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
2754 // 128-bit vector types.
2755 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2756 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
2757 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2758 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
2759 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2760 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
2764 // Neon 2-register vector shift by immediate,
2765 // with f of either N2RegVShLFrm or N2RegVShRFrm
2766 // element sizes of 8, 16, 32 and 64 bits:
2767 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2768 InstrItinClass itin, string OpcodeStr, string Dt,
2769 SDNode OpNode, Format f> {
2770 // 64-bit vector types.
2771 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2772 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
2773 let Inst{21-19} = 0b001; // imm6 = 001xxx
2775 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2776 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
2777 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2779 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2780 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
2781 let Inst{21} = 0b1; // imm6 = 1xxxxx
2783 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, f, itin,
2784 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
2787 // 128-bit vector types.
2788 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
2789 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
2790 let Inst{21-19} = 0b001; // imm6 = 001xxx
2792 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
2793 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
2794 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2796 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
2797 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
2798 let Inst{21} = 0b1; // imm6 = 1xxxxx
2800 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, f, itin,
2801 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
2805 // Neon Shift-Accumulate vector operations,
2806 // element sizes of 8, 16, 32 and 64 bits:
2807 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2808 string OpcodeStr, string Dt, SDNode ShOp> {
2809 // 64-bit vector types.
2810 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4,
2811 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
2812 let Inst{21-19} = 0b001; // imm6 = 001xxx
2814 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4,
2815 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
2816 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2818 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4,
2819 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
2820 let Inst{21} = 0b1; // imm6 = 1xxxxx
2822 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4,
2823 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
2826 // 128-bit vector types.
2827 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4,
2828 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
2829 let Inst{21-19} = 0b001; // imm6 = 001xxx
2831 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4,
2832 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
2833 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2835 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4,
2836 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
2837 let Inst{21} = 0b1; // imm6 = 1xxxxx
2839 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4,
2840 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
2845 // Neon Shift-Insert vector operations,
2846 // with f of either N2RegVShLFrm or N2RegVShRFrm
2847 // element sizes of 8, 16, 32 and 64 bits:
2848 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2849 string OpcodeStr, SDNode ShOp,
2851 // 64-bit vector types.
2852 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4,
2853 f, OpcodeStr, "8", v8i8, ShOp> {
2854 let Inst{21-19} = 0b001; // imm6 = 001xxx
2856 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4,
2857 f, OpcodeStr, "16", v4i16, ShOp> {
2858 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2860 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4,
2861 f, OpcodeStr, "32", v2i32, ShOp> {
2862 let Inst{21} = 0b1; // imm6 = 1xxxxx
2864 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4,
2865 f, OpcodeStr, "64", v1i64, ShOp>;
2868 // 128-bit vector types.
2869 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4,
2870 f, OpcodeStr, "8", v16i8, ShOp> {
2871 let Inst{21-19} = 0b001; // imm6 = 001xxx
2873 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4,
2874 f, OpcodeStr, "16", v8i16, ShOp> {
2875 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2877 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4,
2878 f, OpcodeStr, "32", v4i32, ShOp> {
2879 let Inst{21} = 0b1; // imm6 = 1xxxxx
2881 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4,
2882 f, OpcodeStr, "64", v2i64, ShOp>;
2886 // Neon Shift Long operations,
2887 // element sizes of 8, 16, 32 bits:
2888 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
2889 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
2890 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
2891 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
2892 let Inst{21-19} = 0b001; // imm6 = 001xxx
2894 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
2895 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
2896 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2898 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
2899 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
2900 let Inst{21} = 0b1; // imm6 = 1xxxxx
2904 // Neon Shift Narrow operations,
2905 // element sizes of 16, 32, 64 bits:
2906 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
2907 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
2909 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
2910 OpcodeStr, !strconcat(Dt, "16"), v8i8, v8i16, OpNode> {
2911 let Inst{21-19} = 0b001; // imm6 = 001xxx
2913 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
2914 OpcodeStr, !strconcat(Dt, "32"), v4i16, v4i32, OpNode> {
2915 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2917 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
2918 OpcodeStr, !strconcat(Dt, "64"), v2i32, v2i64, OpNode> {
2919 let Inst{21} = 0b1; // imm6 = 1xxxxx
2923 //===----------------------------------------------------------------------===//
2924 // Instruction Definitions.
2925 //===----------------------------------------------------------------------===//
2927 // Vector Add Operations.
2929 // VADD : Vector Add (integer and floating-point)
2930 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
2932 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
2933 v2f32, v2f32, fadd, 1>;
2934 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
2935 v4f32, v4f32, fadd, 1>;
2936 // VADDL : Vector Add Long (Q = D + D)
2937 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
2938 "vaddl", "s", add, sext, 1>;
2939 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
2940 "vaddl", "u", add, zext, 1>;
2941 // VADDW : Vector Add Wide (Q = Q + D)
2942 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
2943 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
2944 // VHADD : Vector Halving Add
2945 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
2946 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2947 "vhadd", "s", int_arm_neon_vhadds, 1>;
2948 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
2949 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2950 "vhadd", "u", int_arm_neon_vhaddu, 1>;
2951 // VRHADD : Vector Rounding Halving Add
2952 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
2953 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2954 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
2955 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
2956 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2957 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
2958 // VQADD : Vector Saturating Add
2959 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
2960 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2961 "vqadd", "s", int_arm_neon_vqadds, 1>;
2962 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
2963 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2964 "vqadd", "u", int_arm_neon_vqaddu, 1>;
2965 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
2966 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
2967 int_arm_neon_vaddhn, 1>;
2968 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
2969 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
2970 int_arm_neon_vraddhn, 1>;
2972 // Vector Multiply Operations.
2974 // VMUL : Vector Multiply (integer, polynomial and floating-point)
2975 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
2976 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
2977 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
2978 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
2979 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
2980 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
2981 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
2982 v2f32, v2f32, fmul, 1>;
2983 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
2984 v4f32, v4f32, fmul, 1>;
2985 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
2986 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
2987 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
2990 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
2991 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
2992 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
2993 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2994 (DSubReg_i16_reg imm:$lane))),
2995 (SubReg_i16_lane imm:$lane)))>;
2996 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
2997 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
2998 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
2999 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3000 (DSubReg_i32_reg imm:$lane))),
3001 (SubReg_i32_lane imm:$lane)))>;
3002 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
3003 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
3004 (v4f32 (VMULslfq (v4f32 QPR:$src1),
3005 (v2f32 (EXTRACT_SUBREG QPR:$src2,
3006 (DSubReg_i32_reg imm:$lane))),
3007 (SubReg_i32_lane imm:$lane)))>;
3009 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
3010 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
3011 IIC_VMULi16Q, IIC_VMULi32Q,
3012 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
3013 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
3014 IIC_VMULi16Q, IIC_VMULi32Q,
3015 "vqdmulh", "s", int_arm_neon_vqdmulh>;
3016 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
3017 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3019 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
3020 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3021 (DSubReg_i16_reg imm:$lane))),
3022 (SubReg_i16_lane imm:$lane)))>;
3023 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
3024 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3026 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
3027 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3028 (DSubReg_i32_reg imm:$lane))),
3029 (SubReg_i32_lane imm:$lane)))>;
3031 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
3032 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
3033 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
3034 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
3035 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
3036 IIC_VMULi16Q, IIC_VMULi32Q,
3037 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
3038 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
3039 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3041 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
3042 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3043 (DSubReg_i16_reg imm:$lane))),
3044 (SubReg_i16_lane imm:$lane)))>;
3045 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
3046 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3048 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
3049 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3050 (DSubReg_i32_reg imm:$lane))),
3051 (SubReg_i32_lane imm:$lane)))>;
3053 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
3054 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3055 "vmull", "s", NEONvmulls, 1>;
3056 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3057 "vmull", "u", NEONvmullu, 1>;
3058 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
3059 v8i16, v8i8, int_arm_neon_vmullp, 1>;
3060 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
3061 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
3063 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
3064 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
3065 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
3066 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
3067 "vqdmull", "s", int_arm_neon_vqdmull>;
3069 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
3071 // VMLA : Vector Multiply Accumulate (integer and floating-point)
3072 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3073 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3074 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
3076 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
3078 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
3079 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3080 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
3082 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
3083 v4f32, v2f32, fmul, fadd>;
3085 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
3086 (mul (v8i16 QPR:$src2),
3087 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3088 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3089 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3090 (DSubReg_i16_reg imm:$lane))),
3091 (SubReg_i16_lane imm:$lane)))>;
3093 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
3094 (mul (v4i32 QPR:$src2),
3095 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3096 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3097 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3098 (DSubReg_i32_reg imm:$lane))),
3099 (SubReg_i32_lane imm:$lane)))>;
3101 def : Pat<(v4f32 (fadd (v4f32 QPR:$src1),
3102 (fmul (v4f32 QPR:$src2),
3103 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3104 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
3106 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3107 (DSubReg_i32_reg imm:$lane))),
3108 (SubReg_i32_lane imm:$lane)))>;
3110 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
3111 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3112 "vmlal", "s", NEONvmulls, add>;
3113 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3114 "vmlal", "u", NEONvmullu, add>;
3116 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
3117 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
3119 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
3120 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3121 "vqdmlal", "s", int_arm_neon_vqdmlal>;
3122 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
3124 // VMLS : Vector Multiply Subtract (integer and floating-point)
3125 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3126 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3127 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
3129 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
3131 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
3132 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3133 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
3135 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
3136 v4f32, v2f32, fmul, fsub>;
3138 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
3139 (mul (v8i16 QPR:$src2),
3140 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3141 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3142 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3143 (DSubReg_i16_reg imm:$lane))),
3144 (SubReg_i16_lane imm:$lane)))>;
3146 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
3147 (mul (v4i32 QPR:$src2),
3148 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3149 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3150 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3151 (DSubReg_i32_reg imm:$lane))),
3152 (SubReg_i32_lane imm:$lane)))>;
3154 def : Pat<(v4f32 (fsub (v4f32 QPR:$src1),
3155 (fmul (v4f32 QPR:$src2),
3156 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3157 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
3158 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3159 (DSubReg_i32_reg imm:$lane))),
3160 (SubReg_i32_lane imm:$lane)))>;
3162 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
3163 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3164 "vmlsl", "s", NEONvmulls, sub>;
3165 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3166 "vmlsl", "u", NEONvmullu, sub>;
3168 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
3169 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
3171 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
3172 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
3173 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3174 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3176 // Vector Subtract Operations.
3178 // VSUB : Vector Subtract (integer and floating-point)
3179 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
3180 "vsub", "i", sub, 0>;
3181 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
3182 v2f32, v2f32, fsub, 0>;
3183 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
3184 v4f32, v4f32, fsub, 0>;
3185 // VSUBL : Vector Subtract Long (Q = D - D)
3186 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3187 "vsubl", "s", sub, sext, 0>;
3188 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3189 "vsubl", "u", sub, zext, 0>;
3190 // VSUBW : Vector Subtract Wide (Q = Q - D)
3191 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
3192 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
3193 // VHSUB : Vector Halving Subtract
3194 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
3195 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3196 "vhsub", "s", int_arm_neon_vhsubs, 0>;
3197 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
3198 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3199 "vhsub", "u", int_arm_neon_vhsubu, 0>;
3200 // VQSUB : Vector Saturing Subtract
3201 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
3202 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3203 "vqsub", "s", int_arm_neon_vqsubs, 0>;
3204 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
3205 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3206 "vqsub", "u", int_arm_neon_vqsubu, 0>;
3207 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
3208 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
3209 int_arm_neon_vsubhn, 0>;
3210 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
3211 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
3212 int_arm_neon_vrsubhn, 0>;
3214 // Vector Comparisons.
3216 // VCEQ : Vector Compare Equal
3217 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3218 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
3219 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
3221 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
3223 // For disassembly only.
3224 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
3227 // VCGE : Vector Compare Greater Than or Equal
3228 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3229 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
3230 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3231 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
3232 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
3234 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
3236 // For disassembly only.
3237 // FIXME: This instruction's encoding MAY NOT BE correct.
3238 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
3240 // For disassembly only.
3241 // FIXME: This instruction's encoding MAY NOT BE correct.
3242 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
3245 // VCGT : Vector Compare Greater Than
3246 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3247 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
3248 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3249 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
3250 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
3252 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
3254 // For disassembly only.
3255 // FIXME: This instruction's encoding MAY NOT BE correct.
3256 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
3258 // For disassembly only.
3259 // FIXME: This instruction's encoding MAY NOT BE correct.
3260 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
3263 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
3264 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
3265 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
3266 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
3267 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
3268 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
3269 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
3270 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
3271 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
3272 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
3273 // VTST : Vector Test Bits
3274 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
3275 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
3277 // Vector Bitwise Operations.
3279 def vnotd : PatFrag<(ops node:$in),
3280 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
3281 def vnotq : PatFrag<(ops node:$in),
3282 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
3285 // VAND : Vector Bitwise AND
3286 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
3287 v2i32, v2i32, and, 1>;
3288 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
3289 v4i32, v4i32, and, 1>;
3291 // VEOR : Vector Bitwise Exclusive OR
3292 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
3293 v2i32, v2i32, xor, 1>;
3294 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
3295 v4i32, v4i32, xor, 1>;
3297 // VORR : Vector Bitwise OR
3298 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
3299 v2i32, v2i32, or, 1>;
3300 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
3301 v4i32, v4i32, or, 1>;
3303 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
3304 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3306 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3308 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3309 let Inst{9} = SIMM{9};
3312 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
3313 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3315 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3317 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3318 let Inst{10-9} = SIMM{10-9};
3321 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
3322 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3324 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3326 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3327 let Inst{9} = SIMM{9};
3330 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
3331 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3333 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3335 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3336 let Inst{10-9} = SIMM{10-9};
3340 // VBIC : Vector Bitwise Bit Clear (AND NOT)
3341 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
3342 (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD,
3343 "vbic", "$dst, $src1, $src2", "",
3344 [(set DPR:$dst, (v2i32 (and DPR:$src1,
3345 (vnotd DPR:$src2))))]>;
3346 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
3347 (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINiQ,
3348 "vbic", "$dst, $src1, $src2", "",
3349 [(set QPR:$dst, (v4i32 (and QPR:$src1,
3350 (vnotq QPR:$src2))))]>;
3352 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
3353 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3355 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3357 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3358 let Inst{9} = SIMM{9};
3361 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
3362 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3364 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3366 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3367 let Inst{10-9} = SIMM{10-9};
3370 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
3371 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3373 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3375 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3376 let Inst{9} = SIMM{9};
3379 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
3380 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3382 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3384 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3385 let Inst{10-9} = SIMM{10-9};
3388 // VORN : Vector Bitwise OR NOT
3389 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
3390 (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD,
3391 "vorn", "$dst, $src1, $src2", "",
3392 [(set DPR:$dst, (v2i32 (or DPR:$src1,
3393 (vnotd DPR:$src2))))]>;
3394 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
3395 (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINiQ,
3396 "vorn", "$dst, $src1, $src2", "",
3397 [(set QPR:$dst, (v4i32 (or QPR:$src1,
3398 (vnotq QPR:$src2))))]>;
3400 // VMVN : Vector Bitwise NOT (Immediate)
3402 let isReMaterializable = 1 in {
3404 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$dst),
3405 (ins nModImm:$SIMM), IIC_VMOVImm,
3406 "vmvn", "i16", "$dst, $SIMM", "",
3407 [(set DPR:$dst, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
3408 let Inst{9} = SIMM{9};
3411 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$dst),
3412 (ins nModImm:$SIMM), IIC_VMOVImm,
3413 "vmvn", "i16", "$dst, $SIMM", "",
3414 [(set QPR:$dst, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
3415 let Inst{9} = SIMM{9};
3418 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$dst),
3419 (ins nModImm:$SIMM), IIC_VMOVImm,
3420 "vmvn", "i32", "$dst, $SIMM", "",
3421 [(set DPR:$dst, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
3422 let Inst{11-8} = SIMM{11-8};
3425 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$dst),
3426 (ins nModImm:$SIMM), IIC_VMOVImm,
3427 "vmvn", "i32", "$dst, $SIMM", "",
3428 [(set QPR:$dst, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
3429 let Inst{11-8} = SIMM{11-8};
3433 // VMVN : Vector Bitwise NOT
3434 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
3435 (outs DPR:$dst), (ins DPR:$src), IIC_VSUBiD,
3436 "vmvn", "$dst, $src", "",
3437 [(set DPR:$dst, (v2i32 (vnotd DPR:$src)))]>;
3438 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
3439 (outs QPR:$dst), (ins QPR:$src), IIC_VSUBiD,
3440 "vmvn", "$dst, $src", "",
3441 [(set QPR:$dst, (v4i32 (vnotq QPR:$src)))]>;
3442 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
3443 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
3445 // VBSL : Vector Bitwise Select
3446 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
3447 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3448 N3RegFrm, IIC_VCNTiD,
3449 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3451 (v2i32 (or (and DPR:$Vn, DPR:$src1),
3452 (and DPR:$Vm, (vnotd DPR:$src1)))))]>;
3453 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
3454 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3455 N3RegFrm, IIC_VCNTiQ,
3456 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3458 (v4i32 (or (and QPR:$Vn, QPR:$src1),
3459 (and QPR:$Vm, (vnotq QPR:$src1)))))]>;
3461 // VBIF : Vector Bitwise Insert if False
3462 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
3463 // FIXME: This instruction's encoding MAY NOT BE correct.
3464 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
3465 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3466 N3RegFrm, IIC_VBINiD,
3467 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3468 [/* For disassembly only; pattern left blank */]>;
3469 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
3470 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3471 N3RegFrm, IIC_VBINiQ,
3472 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3473 [/* For disassembly only; pattern left blank */]>;
3475 // VBIT : Vector Bitwise Insert if True
3476 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
3477 // FIXME: This instruction's encoding MAY NOT BE correct.
3478 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
3479 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3480 N3RegFrm, IIC_VBINiD,
3481 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3482 [/* For disassembly only; pattern left blank */]>;
3483 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
3484 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3485 N3RegFrm, IIC_VBINiQ,
3486 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3487 [/* For disassembly only; pattern left blank */]>;
3489 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
3490 // for equivalent operations with different register constraints; it just
3493 // Vector Absolute Differences.
3495 // VABD : Vector Absolute Difference
3496 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
3497 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3498 "vabd", "s", int_arm_neon_vabds, 1>;
3499 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
3500 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3501 "vabd", "u", int_arm_neon_vabdu, 1>;
3502 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
3503 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
3504 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
3505 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
3507 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
3508 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
3509 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
3510 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
3511 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
3513 // VABA : Vector Absolute Difference and Accumulate
3514 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3515 "vaba", "s", int_arm_neon_vabds, add>;
3516 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3517 "vaba", "u", int_arm_neon_vabdu, add>;
3519 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
3520 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
3521 "vabal", "s", int_arm_neon_vabds, zext, add>;
3522 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
3523 "vabal", "u", int_arm_neon_vabdu, zext, add>;
3525 // Vector Maximum and Minimum.
3527 // VMAX : Vector Maximum
3528 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
3529 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3530 "vmax", "s", int_arm_neon_vmaxs, 1>;
3531 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
3532 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3533 "vmax", "u", int_arm_neon_vmaxu, 1>;
3534 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
3536 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
3537 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
3539 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
3541 // VMIN : Vector Minimum
3542 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
3543 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3544 "vmin", "s", int_arm_neon_vmins, 1>;
3545 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
3546 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3547 "vmin", "u", int_arm_neon_vminu, 1>;
3548 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
3550 v2f32, v2f32, int_arm_neon_vmins, 1>;
3551 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
3553 v4f32, v4f32, int_arm_neon_vmins, 1>;
3555 // Vector Pairwise Operations.
3557 // VPADD : Vector Pairwise Add
3558 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3560 v8i8, v8i8, int_arm_neon_vpadd, 0>;
3561 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3563 v4i16, v4i16, int_arm_neon_vpadd, 0>;
3564 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3566 v2i32, v2i32, int_arm_neon_vpadd, 0>;
3567 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
3568 IIC_VPBIND, "vpadd", "f32",
3569 v2f32, v2f32, int_arm_neon_vpadd, 0>;
3571 // VPADDL : Vector Pairwise Add Long
3572 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
3573 int_arm_neon_vpaddls>;
3574 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
3575 int_arm_neon_vpaddlu>;
3577 // VPADAL : Vector Pairwise Add and Accumulate Long
3578 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
3579 int_arm_neon_vpadals>;
3580 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
3581 int_arm_neon_vpadalu>;
3583 // VPMAX : Vector Pairwise Maximum
3584 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3585 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
3586 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3587 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
3588 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3589 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
3590 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3591 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
3592 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3593 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
3594 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3595 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
3596 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
3597 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
3599 // VPMIN : Vector Pairwise Minimum
3600 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3601 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
3602 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3603 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
3604 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3605 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
3606 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3607 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
3608 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3609 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
3610 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3611 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
3612 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
3613 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
3615 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
3617 // VRECPE : Vector Reciprocal Estimate
3618 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
3619 IIC_VUNAD, "vrecpe", "u32",
3620 v2i32, v2i32, int_arm_neon_vrecpe>;
3621 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
3622 IIC_VUNAQ, "vrecpe", "u32",
3623 v4i32, v4i32, int_arm_neon_vrecpe>;
3624 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
3625 IIC_VUNAD, "vrecpe", "f32",
3626 v2f32, v2f32, int_arm_neon_vrecpe>;
3627 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
3628 IIC_VUNAQ, "vrecpe", "f32",
3629 v4f32, v4f32, int_arm_neon_vrecpe>;
3631 // VRECPS : Vector Reciprocal Step
3632 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
3633 IIC_VRECSD, "vrecps", "f32",
3634 v2f32, v2f32, int_arm_neon_vrecps, 1>;
3635 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
3636 IIC_VRECSQ, "vrecps", "f32",
3637 v4f32, v4f32, int_arm_neon_vrecps, 1>;
3639 // VRSQRTE : Vector Reciprocal Square Root Estimate
3640 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
3641 IIC_VUNAD, "vrsqrte", "u32",
3642 v2i32, v2i32, int_arm_neon_vrsqrte>;
3643 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
3644 IIC_VUNAQ, "vrsqrte", "u32",
3645 v4i32, v4i32, int_arm_neon_vrsqrte>;
3646 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
3647 IIC_VUNAD, "vrsqrte", "f32",
3648 v2f32, v2f32, int_arm_neon_vrsqrte>;
3649 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
3650 IIC_VUNAQ, "vrsqrte", "f32",
3651 v4f32, v4f32, int_arm_neon_vrsqrte>;
3653 // VRSQRTS : Vector Reciprocal Square Root Step
3654 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
3655 IIC_VRECSD, "vrsqrts", "f32",
3656 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
3657 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
3658 IIC_VRECSQ, "vrsqrts", "f32",
3659 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
3663 // VSHL : Vector Shift
3664 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
3665 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
3666 "vshl", "s", int_arm_neon_vshifts>;
3667 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
3668 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
3669 "vshl", "u", int_arm_neon_vshiftu>;
3670 // VSHL : Vector Shift Left (Immediate)
3671 defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl,
3673 // VSHR : Vector Shift Right (Immediate)
3674 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", NEONvshrs,
3676 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", NEONvshru,
3679 // VSHLL : Vector Shift Left Long
3680 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
3681 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
3683 // VSHLL : Vector Shift Left Long (with maximum shift count)
3684 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
3685 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
3686 ValueType OpTy, SDNode OpNode>
3687 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
3688 ResTy, OpTy, OpNode> {
3689 let Inst{21-16} = op21_16;
3691 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
3692 v8i16, v8i8, NEONvshlli>;
3693 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
3694 v4i32, v4i16, NEONvshlli>;
3695 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
3696 v2i64, v2i32, NEONvshlli>;
3698 // VSHRN : Vector Shift Right and Narrow
3699 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
3702 // VRSHL : Vector Rounding Shift
3703 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
3704 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3705 "vrshl", "s", int_arm_neon_vrshifts>;
3706 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
3707 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3708 "vrshl", "u", int_arm_neon_vrshiftu>;
3709 // VRSHR : Vector Rounding Shift Right
3710 defm VRSHRs : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs,
3712 defm VRSHRu : N2VSh_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", NEONvrshru,
3715 // VRSHRN : Vector Rounding Shift Right and Narrow
3716 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
3719 // VQSHL : Vector Saturating Shift
3720 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
3721 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3722 "vqshl", "s", int_arm_neon_vqshifts>;
3723 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
3724 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3725 "vqshl", "u", int_arm_neon_vqshiftu>;
3726 // VQSHL : Vector Saturating Shift Left (Immediate)
3727 defm VQSHLsi : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls,
3729 defm VQSHLui : N2VSh_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu,
3731 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
3732 defm VQSHLsu : N2VSh_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu,
3735 // VQSHRN : Vector Saturating Shift Right and Narrow
3736 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
3738 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
3741 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
3742 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
3745 // VQRSHL : Vector Saturating Rounding Shift
3746 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
3747 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3748 "vqrshl", "s", int_arm_neon_vqrshifts>;
3749 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
3750 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3751 "vqrshl", "u", int_arm_neon_vqrshiftu>;
3753 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
3754 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
3756 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
3759 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
3760 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
3763 // VSRA : Vector Shift Right and Accumulate
3764 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
3765 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
3766 // VRSRA : Vector Rounding Shift Right and Accumulate
3767 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
3768 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
3770 // VSLI : Vector Shift Left and Insert
3771 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli", NEONvsli, N2RegVShLFrm>;
3772 // VSRI : Vector Shift Right and Insert
3773 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri", NEONvsri, N2RegVShRFrm>;
3775 // Vector Absolute and Saturating Absolute.
3777 // VABS : Vector Absolute Value
3778 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
3779 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
3781 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
3782 IIC_VUNAD, "vabs", "f32",
3783 v2f32, v2f32, int_arm_neon_vabs>;
3784 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
3785 IIC_VUNAQ, "vabs", "f32",
3786 v4f32, v4f32, int_arm_neon_vabs>;
3788 // VQABS : Vector Saturating Absolute Value
3789 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
3790 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
3791 int_arm_neon_vqabs>;
3795 def vnegd : PatFrag<(ops node:$in),
3796 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
3797 def vnegq : PatFrag<(ops node:$in),
3798 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
3800 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
3801 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
3802 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
3803 [(set DPR:$dst, (Ty (vnegd DPR:$src)))]>;
3804 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
3805 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
3806 IIC_VSHLiQ, OpcodeStr, Dt, "$dst, $src", "",
3807 [(set QPR:$dst, (Ty (vnegq QPR:$src)))]>;
3809 // VNEG : Vector Negate (integer)
3810 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
3811 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
3812 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
3813 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
3814 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
3815 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
3817 // VNEG : Vector Negate (floating-point)
3818 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
3819 (outs DPR:$dst), (ins DPR:$src), IIC_VUNAD,
3820 "vneg", "f32", "$dst, $src", "",
3821 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
3822 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
3823 (outs QPR:$dst), (ins QPR:$src), IIC_VUNAQ,
3824 "vneg", "f32", "$dst, $src", "",
3825 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
3827 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
3828 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
3829 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
3830 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
3831 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
3832 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
3834 // VQNEG : Vector Saturating Negate
3835 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
3836 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
3837 int_arm_neon_vqneg>;
3839 // Vector Bit Counting Operations.
3841 // VCLS : Vector Count Leading Sign Bits
3842 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
3843 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
3845 // VCLZ : Vector Count Leading Zeros
3846 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
3847 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
3849 // VCNT : Vector Count One Bits
3850 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
3851 IIC_VCNTiD, "vcnt", "8",
3852 v8i8, v8i8, int_arm_neon_vcnt>;
3853 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
3854 IIC_VCNTiQ, "vcnt", "8",
3855 v16i8, v16i8, int_arm_neon_vcnt>;
3857 // Vector Swap -- for disassembly only.
3858 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
3859 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
3860 "vswp", "$dst, $src", "", []>;
3861 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
3862 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
3863 "vswp", "$dst, $src", "", []>;
3865 // Vector Move Operations.
3867 // VMOV : Vector Move (Register)
3869 let neverHasSideEffects = 1 in {
3870 def VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
3871 N3RegFrm, IIC_VMOV, "vmov", "$dst, $src", "", []>;
3872 def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
3873 N3RegFrm, IIC_VMOV, "vmov", "$dst, $src", "", []>;
3875 // Pseudo vector move instructions for QQ and QQQQ registers. This should
3876 // be expanded after register allocation is completed.
3877 def VMOVQQ : PseudoInst<(outs QQPR:$dst), (ins QQPR:$src),
3878 NoItinerary, "", []>;
3880 def VMOVQQQQ : PseudoInst<(outs QQQQPR:$dst), (ins QQQQPR:$src),
3881 NoItinerary, "", []>;
3882 } // neverHasSideEffects
3884 // VMOV : Vector Move (Immediate)
3886 let isReMaterializable = 1 in {
3887 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
3888 (ins nModImm:$SIMM), IIC_VMOVImm,
3889 "vmov", "i8", "$dst, $SIMM", "",
3890 [(set DPR:$dst, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
3891 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
3892 (ins nModImm:$SIMM), IIC_VMOVImm,
3893 "vmov", "i8", "$dst, $SIMM", "",
3894 [(set QPR:$dst, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
3896 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$dst),
3897 (ins nModImm:$SIMM), IIC_VMOVImm,
3898 "vmov", "i16", "$dst, $SIMM", "",
3899 [(set DPR:$dst, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
3900 let Inst{9} = SIMM{9};
3903 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$dst),
3904 (ins nModImm:$SIMM), IIC_VMOVImm,
3905 "vmov", "i16", "$dst, $SIMM", "",
3906 [(set QPR:$dst, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
3907 let Inst{9} = SIMM{9};
3910 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$dst),
3911 (ins nModImm:$SIMM), IIC_VMOVImm,
3912 "vmov", "i32", "$dst, $SIMM", "",
3913 [(set DPR:$dst, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
3914 let Inst{11-8} = SIMM{11-8};
3917 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$dst),
3918 (ins nModImm:$SIMM), IIC_VMOVImm,
3919 "vmov", "i32", "$dst, $SIMM", "",
3920 [(set QPR:$dst, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
3921 let Inst{11-8} = SIMM{11-8};
3924 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
3925 (ins nModImm:$SIMM), IIC_VMOVImm,
3926 "vmov", "i64", "$dst, $SIMM", "",
3927 [(set DPR:$dst, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
3928 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
3929 (ins nModImm:$SIMM), IIC_VMOVImm,
3930 "vmov", "i64", "$dst, $SIMM", "",
3931 [(set QPR:$dst, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
3932 } // isReMaterializable
3934 // VMOV : Vector Get Lane (move scalar to ARM core register)
3936 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
3937 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
3938 IIC_VMOVSI, "vmov", "s8", "$R, $V[$lane]",
3939 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
3941 let Inst{21} = lane{2};
3942 let Inst{6-5} = lane{1-0};
3944 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
3945 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
3946 IIC_VMOVSI, "vmov", "s16", "$R, $V[$lane]",
3947 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
3949 let Inst{21} = lane{1};
3950 let Inst{6} = lane{0};
3952 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
3953 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
3954 IIC_VMOVSI, "vmov", "u8", "$R, $V[$lane]",
3955 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
3957 let Inst{21} = lane{2};
3958 let Inst{6-5} = lane{1-0};
3960 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
3961 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
3962 IIC_VMOVSI, "vmov", "u16", "$R, $V[$lane]",
3963 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
3965 let Inst{21} = lane{1};
3966 let Inst{6} = lane{0};
3968 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
3969 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
3970 IIC_VMOVSI, "vmov", "32", "$R, $V[$lane]",
3971 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
3973 let Inst{21} = lane{0};
3975 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
3976 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
3977 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
3978 (DSubReg_i8_reg imm:$lane))),
3979 (SubReg_i8_lane imm:$lane))>;
3980 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
3981 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
3982 (DSubReg_i16_reg imm:$lane))),
3983 (SubReg_i16_lane imm:$lane))>;
3984 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
3985 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
3986 (DSubReg_i8_reg imm:$lane))),
3987 (SubReg_i8_lane imm:$lane))>;
3988 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
3989 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
3990 (DSubReg_i16_reg imm:$lane))),
3991 (SubReg_i16_lane imm:$lane))>;
3992 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
3993 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
3994 (DSubReg_i32_reg imm:$lane))),
3995 (SubReg_i32_lane imm:$lane))>;
3996 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
3997 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
3998 (SSubReg_f32_reg imm:$src2))>;
3999 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
4000 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
4001 (SSubReg_f32_reg imm:$src2))>;
4002 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
4003 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4004 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
4005 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4008 // VMOV : Vector Set Lane (move ARM core register to scalar)
4010 let Constraints = "$src1 = $V" in {
4011 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
4012 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4013 IIC_VMOVISL, "vmov", "8", "$V[$lane], $R",
4014 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
4015 GPR:$R, imm:$lane))]> {
4016 let Inst{21} = lane{2};
4017 let Inst{6-5} = lane{1-0};
4019 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
4020 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4021 IIC_VMOVISL, "vmov", "16", "$V[$lane], $R",
4022 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
4023 GPR:$R, imm:$lane))]> {
4024 let Inst{21} = lane{1};
4025 let Inst{6} = lane{0};
4027 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
4028 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4029 IIC_VMOVISL, "vmov", "32", "$V[$lane], $R",
4030 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
4031 GPR:$R, imm:$lane))]> {
4032 let Inst{21} = lane{0};
4035 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
4036 (v16i8 (INSERT_SUBREG QPR:$src1,
4037 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
4038 (DSubReg_i8_reg imm:$lane))),
4039 GPR:$src2, (SubReg_i8_lane imm:$lane))),
4040 (DSubReg_i8_reg imm:$lane)))>;
4041 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
4042 (v8i16 (INSERT_SUBREG QPR:$src1,
4043 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
4044 (DSubReg_i16_reg imm:$lane))),
4045 GPR:$src2, (SubReg_i16_lane imm:$lane))),
4046 (DSubReg_i16_reg imm:$lane)))>;
4047 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
4048 (v4i32 (INSERT_SUBREG QPR:$src1,
4049 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
4050 (DSubReg_i32_reg imm:$lane))),
4051 GPR:$src2, (SubReg_i32_lane imm:$lane))),
4052 (DSubReg_i32_reg imm:$lane)))>;
4054 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
4055 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
4056 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4057 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
4058 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
4059 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4061 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4062 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4063 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4064 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4066 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
4067 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4068 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
4069 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
4070 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
4071 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4073 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
4074 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4075 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
4076 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4077 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
4078 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4080 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
4081 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4082 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4084 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
4085 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
4086 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4088 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
4089 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4090 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4093 // VDUP : Vector Duplicate (from ARM core register to all elements)
4095 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4096 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
4097 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
4098 [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
4099 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4100 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
4101 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
4102 [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
4104 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
4105 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
4106 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
4107 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
4108 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
4109 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
4111 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
4112 IIC_VMOVIS, "vdup", "32", "$dst, $src",
4113 [(set DPR:$dst, (v2f32 (NEONvdup
4114 (f32 (bitconvert GPR:$src)))))]>;
4115 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
4116 IIC_VMOVIS, "vdup", "32", "$dst, $src",
4117 [(set QPR:$dst, (v4f32 (NEONvdup
4118 (f32 (bitconvert GPR:$src)))))]>;
4120 // VDUP : Vector Duplicate Lane (from scalar to all elements)
4122 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
4124 : NVDupLane<op19_16, 0, (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane),
4125 IIC_VMOVD, OpcodeStr, Dt, "$dst, $src[$lane]",
4126 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
4128 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
4129 ValueType ResTy, ValueType OpTy>
4130 : NVDupLane<op19_16, 1, (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane),
4131 IIC_VMOVQ, OpcodeStr, Dt, "$dst, $src[$lane]",
4132 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src),
4135 // Inst{19-16} is partially specified depending on the element size.
4137 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8> {
4138 let Inst{19-17} = lane{2-0};
4140 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16> {
4141 let Inst{19-18} = lane{1-0};
4143 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32> {
4144 let Inst{19} = lane{0};
4146 def VDUPLNfd : VDUPLND<{?,1,0,0}, "vdup", "32", v2f32> {
4147 let Inst{19} = lane{0};
4149 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8> {
4150 let Inst{19-17} = lane{2-0};
4152 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16> {
4153 let Inst{19-18} = lane{1-0};
4155 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32> {
4156 let Inst{19} = lane{0};
4158 def VDUPLNfq : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4f32, v2f32> {
4159 let Inst{19} = lane{0};
4162 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
4163 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
4164 (DSubReg_i8_reg imm:$lane))),
4165 (SubReg_i8_lane imm:$lane)))>;
4166 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
4167 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
4168 (DSubReg_i16_reg imm:$lane))),
4169 (SubReg_i16_lane imm:$lane)))>;
4170 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
4171 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
4172 (DSubReg_i32_reg imm:$lane))),
4173 (SubReg_i32_lane imm:$lane)))>;
4174 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
4175 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
4176 (DSubReg_i32_reg imm:$lane))),
4177 (SubReg_i32_lane imm:$lane)))>;
4179 def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4180 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
4181 def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4182 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
4184 // VMOVN : Vector Narrowing Move
4185 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
4186 "vmovn", "i", trunc>;
4187 // VQMOVN : Vector Saturating Narrowing Move
4188 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
4189 "vqmovn", "s", int_arm_neon_vqmovns>;
4190 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
4191 "vqmovn", "u", int_arm_neon_vqmovnu>;
4192 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
4193 "vqmovun", "s", int_arm_neon_vqmovnsu>;
4194 // VMOVL : Vector Lengthening Move
4195 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
4196 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
4198 // Vector Conversions.
4200 // VCVT : Vector Convert Between Floating-Point and Integers
4201 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4202 v2i32, v2f32, fp_to_sint>;
4203 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4204 v2i32, v2f32, fp_to_uint>;
4205 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4206 v2f32, v2i32, sint_to_fp>;
4207 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4208 v2f32, v2i32, uint_to_fp>;
4210 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4211 v4i32, v4f32, fp_to_sint>;
4212 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4213 v4i32, v4f32, fp_to_uint>;
4214 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4215 v4f32, v4i32, sint_to_fp>;
4216 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4217 v4f32, v4i32, uint_to_fp>;
4219 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
4220 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4221 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
4222 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4223 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
4224 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4225 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
4226 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4227 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
4229 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4230 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
4231 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4232 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
4233 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4234 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
4235 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4236 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
4240 // VREV64 : Vector Reverse elements within 64-bit doublewords
4242 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4243 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
4244 (ins DPR:$src), IIC_VMOVD,
4245 OpcodeStr, Dt, "$dst, $src", "",
4246 [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
4247 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4248 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
4249 (ins QPR:$src), IIC_VMOVQ,
4250 OpcodeStr, Dt, "$dst, $src", "",
4251 [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
4253 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
4254 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
4255 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
4256 def VREV64df : VREV64D<0b10, "vrev64", "32", v2f32>;
4258 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
4259 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
4260 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
4261 def VREV64qf : VREV64Q<0b10, "vrev64", "32", v4f32>;
4263 // VREV32 : Vector Reverse elements within 32-bit words
4265 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4266 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
4267 (ins DPR:$src), IIC_VMOVD,
4268 OpcodeStr, Dt, "$dst, $src", "",
4269 [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
4270 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4271 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
4272 (ins QPR:$src), IIC_VMOVQ,
4273 OpcodeStr, Dt, "$dst, $src", "",
4274 [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
4276 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
4277 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
4279 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
4280 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
4282 // VREV16 : Vector Reverse elements within 16-bit halfwords
4284 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4285 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
4286 (ins DPR:$src), IIC_VMOVD,
4287 OpcodeStr, Dt, "$dst, $src", "",
4288 [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
4289 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4290 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
4291 (ins QPR:$src), IIC_VMOVQ,
4292 OpcodeStr, Dt, "$dst, $src", "",
4293 [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
4295 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
4296 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
4298 // Other Vector Shuffles.
4300 // VEXT : Vector Extract
4302 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
4303 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$dst),
4304 (ins DPR:$lhs, DPR:$rhs, i32imm:$index), NVExtFrm,
4305 IIC_VEXTD, OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
4306 [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
4307 (Ty DPR:$rhs), imm:$index)))]> {
4309 let Inst{11-8} = index{3-0};
4312 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
4313 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$dst),
4314 (ins QPR:$lhs, QPR:$rhs, i32imm:$index), NVExtFrm,
4315 IIC_VEXTQ, OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
4316 [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
4317 (Ty QPR:$rhs), imm:$index)))]> {
4319 let Inst{11-8} = index{3-0};
4322 def VEXTd8 : VEXTd<"vext", "8", v8i8> {
4323 let Inst{11-8} = index{3-0};
4325 def VEXTd16 : VEXTd<"vext", "16", v4i16> {
4326 let Inst{11-9} = index{2-0};
4329 def VEXTd32 : VEXTd<"vext", "32", v2i32> {
4330 let Inst{11-10} = index{1-0};
4331 let Inst{9-8} = 0b00;
4333 def VEXTdf : VEXTd<"vext", "32", v2f32> {
4334 let Inst{11} = index{0};
4335 let Inst{10-8} = 0b000;
4338 def VEXTq8 : VEXTq<"vext", "8", v16i8> {
4339 let Inst{11-8} = index{3-0};
4341 def VEXTq16 : VEXTq<"vext", "16", v8i16> {
4342 let Inst{11-9} = index{2-0};
4345 def VEXTq32 : VEXTq<"vext", "32", v4i32> {
4346 let Inst{11-10} = index{1-0};
4347 let Inst{9-8} = 0b00;
4349 def VEXTqf : VEXTq<"vext", "32", v4f32> {
4350 let Inst{11} = index{0};
4351 let Inst{10-8} = 0b000;
4354 // VTRN : Vector Transpose
4356 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
4357 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
4358 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
4360 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
4361 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
4362 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
4364 // VUZP : Vector Unzip (Deinterleave)
4366 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
4367 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
4368 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
4370 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
4371 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
4372 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
4374 // VZIP : Vector Zip (Interleave)
4376 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
4377 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
4378 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
4380 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
4381 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
4382 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
4384 // Vector Table Lookup and Table Extension.
4386 // VTBL : Vector Table Lookup
4388 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
4389 (ins DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
4390 "vtbl", "8", "$Vd, \\{$Vn\\}, $Vm", "",
4391 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 DPR:$Vn, DPR:$Vm)))]>;
4392 let hasExtraSrcRegAllocReq = 1 in {
4394 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
4395 (ins DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTB2,
4396 "vtbl", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "", []>;
4398 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
4399 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm), NVTBLFrm, IIC_VTB3,
4400 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm", "", []>;
4402 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
4403 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm),
4405 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm", "", []>;
4406 } // hasExtraSrcRegAllocReq = 1
4409 : PseudoNeonI<(outs DPR:$dst), (ins QPR:$tbl, DPR:$src), IIC_VTB2, "", []>;
4411 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
4413 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
4415 // VTBX : Vector Table Extension
4417 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
4418 (ins DPR:$orig, DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
4419 "vtbx", "8", "$Vd, \\{$Vn\\}, $Vm", "$orig = $Vd",
4420 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
4421 DPR:$orig, DPR:$Vn, DPR:$Vm)))]>;
4422 let hasExtraSrcRegAllocReq = 1 in {
4424 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
4425 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
4426 "vtbx", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "$orig = $Vd", []>;
4428 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
4429 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm),
4430 NVTBLFrm, IIC_VTBX3,
4431 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm",
4434 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd), (ins DPR:$orig, DPR:$Vn,
4435 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
4436 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm",
4438 } // hasExtraSrcRegAllocReq = 1
4441 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QPR:$tbl, DPR:$src),
4442 IIC_VTBX2, "$orig = $dst", []>;
4444 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4445 IIC_VTBX3, "$orig = $dst", []>;
4447 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4448 IIC_VTBX4, "$orig = $dst", []>;
4450 //===----------------------------------------------------------------------===//
4451 // NEON instructions for single-precision FP math
4452 //===----------------------------------------------------------------------===//
4454 class N2VSPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
4455 : NEONFPPat<(ResTy (OpNode SPR:$a)),
4456 (EXTRACT_SUBREG (OpTy (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)),
4460 class N3VSPat<SDNode OpNode, NeonI Inst>
4461 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
4462 (EXTRACT_SUBREG (v2f32
4463 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
4465 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
4469 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
4470 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
4471 (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
4473 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
4475 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
4479 // These need separate instructions because they must use DPR_VFP2 register
4480 // class which have SPR sub-registers.
4482 // Vector Add Operations used for single-precision FP
4483 let neverHasSideEffects = 1 in
4484 def VADDfd_sfp : N3VS<0,0,0b00,0b1101,0, "vadd", "f32", v2f32, v2f32, fadd, 1>;
4485 def : N3VSPat<fadd, VADDfd_sfp>;
4487 // Vector Sub Operations used for single-precision FP
4488 let neverHasSideEffects = 1 in
4489 def VSUBfd_sfp : N3VS<0,0,0b10,0b1101,0, "vsub", "f32", v2f32, v2f32, fsub, 0>;
4490 def : N3VSPat<fsub, VSUBfd_sfp>;
4492 // Vector Multiply Operations used for single-precision FP
4493 let neverHasSideEffects = 1 in
4494 def VMULfd_sfp : N3VS<1,0,0b00,0b1101,1, "vmul", "f32", v2f32, v2f32, fmul, 1>;
4495 def : N3VSPat<fmul, VMULfd_sfp>;
4497 // Vector Multiply-Accumulate/Subtract used for single-precision FP
4498 // vml[as].f32 can cause 4-8 cycle stalls in following ASIMD instructions, so
4499 // we want to avoid them for now. e.g., alternating vmla/vadd instructions.
4501 //let neverHasSideEffects = 1 in
4502 //def VMLAfd_sfp : N3VSMulOp<0,0,0b00,0b1101,1, IIC_VMACD, "vmla", "f32",
4503 // v2f32, fmul, fadd>;
4504 //def : N3VSMulOpPat<fmul, fadd, VMLAfd_sfp>;
4506 //let neverHasSideEffects = 1 in
4507 //def VMLSfd_sfp : N3VSMulOp<0,0,0b10,0b1101,1, IIC_VMACD, "vmls", "f32",
4508 // v2f32, fmul, fsub>;
4509 //def : N3VSMulOpPat<fmul, fsub, VMLSfd_sfp>;
4511 // Vector Absolute used for single-precision FP
4512 let neverHasSideEffects = 1 in
4513 def VABSfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01110, 0, 0,
4514 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
4515 "vabs", "f32", "$dst, $src", "", []>;
4516 def : N2VSPat<fabs, f32, v2f32, VABSfd_sfp>;
4518 // Vector Negate used for single-precision FP
4519 let neverHasSideEffects = 1 in
4520 def VNEGfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
4521 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
4522 "vneg", "f32", "$dst, $src", "", []>;
4523 def : N2VSPat<fneg, f32, v2f32, VNEGfd_sfp>;
4525 // Vector Maximum used for single-precision FP
4526 let neverHasSideEffects = 1 in
4527 def VMAXfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
4528 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm, IIC_VBIND,
4529 "vmax", "f32", "$dst, $src1, $src2", "", []>;
4530 def : N3VSPat<NEONfmax, VMAXfd_sfp>;
4532 // Vector Minimum used for single-precision FP
4533 let neverHasSideEffects = 1 in
4534 def VMINfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
4535 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm, IIC_VBIND,
4536 "vmin", "f32", "$dst, $src1, $src2", "", []>;
4537 def : N3VSPat<NEONfmin, VMINfd_sfp>;
4539 // Vector Convert between single-precision FP and integer
4540 let neverHasSideEffects = 1 in
4541 def VCVTf2sd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4542 v2i32, v2f32, fp_to_sint>;
4543 def : N2VSPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
4545 let neverHasSideEffects = 1 in
4546 def VCVTf2ud_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4547 v2i32, v2f32, fp_to_uint>;
4548 def : N2VSPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
4550 let neverHasSideEffects = 1 in
4551 def VCVTs2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4552 v2f32, v2i32, sint_to_fp>;
4553 def : N2VSPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
4555 let neverHasSideEffects = 1 in
4556 def VCVTu2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4557 v2f32, v2i32, uint_to_fp>;
4558 def : N2VSPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
4560 //===----------------------------------------------------------------------===//
4561 // Non-Instruction Patterns
4562 //===----------------------------------------------------------------------===//
4565 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
4566 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
4567 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
4568 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
4569 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
4570 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
4571 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
4572 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
4573 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
4574 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
4575 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
4576 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
4577 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
4578 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
4579 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
4580 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
4581 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
4582 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
4583 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
4584 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
4585 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
4586 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
4587 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
4588 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
4589 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
4590 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
4591 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
4592 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
4593 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
4594 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
4596 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
4597 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
4598 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
4599 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
4600 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
4601 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
4602 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
4603 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
4604 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
4605 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
4606 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
4607 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
4608 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
4609 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
4610 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
4611 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
4612 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
4613 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
4614 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
4615 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
4616 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
4617 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
4618 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
4619 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
4620 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
4621 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
4622 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
4623 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
4624 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
4625 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;