1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
70 // VDUPLANE can produce a quad-register result from a double-register source,
71 // so the result is not constrained to match the source.
72 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
73 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
76 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
77 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
78 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
80 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
81 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
82 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
83 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
85 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
86 SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>]>;
87 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
88 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
89 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
91 //===----------------------------------------------------------------------===//
92 // NEON operand definitions
93 //===----------------------------------------------------------------------===//
95 // addrmode_neonldstm := reg
97 /* TODO: Take advantage of vldm.
98 def addrmode_neonldstm : Operand<i32>,
99 ComplexPattern<i32, 2, "SelectAddrModeNeonLdStM", []> {
100 let PrintMethod = "printAddrNeonLdStMOperand";
101 let MIOperandInfo = (ops GPR, i32imm);
105 //===----------------------------------------------------------------------===//
106 // NEON load / store instructions
107 //===----------------------------------------------------------------------===//
109 /* TODO: Take advantage of vldm.
110 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
111 def VLDMD : NI<(outs),
112 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
114 "vldm${addr:submode} ${addr:base}, $dst1",
116 let Inst{27-25} = 0b110;
118 let Inst{11-9} = 0b101;
121 def VLDMS : NI<(outs),
122 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
124 "vldm${addr:submode} ${addr:base}, $dst1",
126 let Inst{27-25} = 0b110;
128 let Inst{11-9} = 0b101;
133 // Use vldmia to load a Q register as a D register pair.
134 def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr),
136 "vldmia $addr, ${dst:dregpair}",
137 [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]> {
138 let Inst{27-25} = 0b110;
139 let Inst{24} = 0; // P bit
140 let Inst{23} = 1; // U bit
142 let Inst{11-9} = 0b101;
145 // Use vstmia to store a Q register as a D register pair.
146 def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr),
148 "vstmia $addr, ${src:dregpair}",
149 [(store (v2f64 QPR:$src), addrmode4:$addr)]> {
150 let Inst{27-25} = 0b110;
151 let Inst{24} = 0; // P bit
152 let Inst{23} = 1; // U bit
154 let Inst{11-9} = 0b101;
157 // VLD1 : Vector Load (multiple single elements)
158 class VLD1D<bits<4> op7_4, string OpcodeStr, ValueType Ty, Intrinsic IntOp>
159 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst), (ins addrmode6:$addr), IIC_VLD1,
160 !strconcat(OpcodeStr, "\t\\{$dst\\}, $addr"), "",
161 [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
162 class VLD1Q<bits<4> op7_4, string OpcodeStr, ValueType Ty, Intrinsic IntOp>
163 : NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst), (ins addrmode6:$addr), IIC_VLD1,
164 !strconcat(OpcodeStr, "\t${dst:dregpair}, $addr"), "",
165 [(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
167 def VLD1d8 : VLD1D<0b0000, "vld1.8", v8i8, int_arm_neon_vld1>;
168 def VLD1d16 : VLD1D<0b0100, "vld1.16", v4i16, int_arm_neon_vld1>;
169 def VLD1d32 : VLD1D<0b1000, "vld1.32", v2i32, int_arm_neon_vld1>;
170 def VLD1df : VLD1D<0b1000, "vld1.32", v2f32, int_arm_neon_vld1>;
171 def VLD1d64 : VLD1D<0b1100, "vld1.64", v1i64, int_arm_neon_vld1>;
173 def VLD1q8 : VLD1Q<0b0000, "vld1.8", v16i8, int_arm_neon_vld1>;
174 def VLD1q16 : VLD1Q<0b0100, "vld1.16", v8i16, int_arm_neon_vld1>;
175 def VLD1q32 : VLD1Q<0b1000, "vld1.32", v4i32, int_arm_neon_vld1>;
176 def VLD1qf : VLD1Q<0b1000, "vld1.32", v4f32, int_arm_neon_vld1>;
177 def VLD1q64 : VLD1Q<0b1100, "vld1.64", v2i64, int_arm_neon_vld1>;
179 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
181 // VLD2 : Vector Load (multiple 2-element structures)
182 class VLD2D<bits<4> op7_4, string OpcodeStr>
183 : NLdSt<0,0b10,0b1000,op7_4, (outs DPR:$dst1, DPR:$dst2),
184 (ins addrmode6:$addr), IIC_VLD2,
185 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2\\}, $addr"), "", []>;
186 class VLD2Q<bits<4> op7_4, string OpcodeStr>
187 : NLdSt<0,0b10,0b0011,op7_4,
188 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
189 (ins addrmode6:$addr), IIC_VLD2,
190 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"),
193 def VLD2d8 : VLD2D<0b0000, "vld2.8">;
194 def VLD2d16 : VLD2D<0b0100, "vld2.16">;
195 def VLD2d32 : VLD2D<0b1000, "vld2.32">;
196 def VLD2d64 : NLdSt<0,0b10,0b1010,0b1100, (outs DPR:$dst1, DPR:$dst2),
197 (ins addrmode6:$addr), IIC_VLD1,
198 "vld1.64\t\\{$dst1,$dst2\\}, $addr", "", []>;
200 def VLD2q8 : VLD2Q<0b0000, "vld2.8">;
201 def VLD2q16 : VLD2Q<0b0100, "vld2.16">;
202 def VLD2q32 : VLD2Q<0b1000, "vld2.32">;
204 // VLD3 : Vector Load (multiple 3-element structures)
205 class VLD3D<bits<4> op7_4, string OpcodeStr>
206 : NLdSt<0,0b10,0b0100,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
207 (ins addrmode6:$addr), IIC_VLD3,
208 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"), "", []>;
209 class VLD3WB<bits<4> op7_4, string OpcodeStr>
210 : NLdSt<0,0b10,0b0101,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
211 (ins addrmode6:$addr), IIC_VLD3,
212 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"),
213 "$addr.addr = $wb", []>;
215 def VLD3d8 : VLD3D<0b0000, "vld3.8">;
216 def VLD3d16 : VLD3D<0b0100, "vld3.16">;
217 def VLD3d32 : VLD3D<0b1000, "vld3.32">;
218 def VLD3d64 : NLdSt<0,0b10,0b0110,0b1100,
219 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
220 (ins addrmode6:$addr), IIC_VLD1,
221 "vld1.64\t\\{$dst1,$dst2,$dst3\\}, $addr", "", []>;
223 // vld3 to double-spaced even registers.
224 def VLD3q8a : VLD3WB<0b0000, "vld3.8">;
225 def VLD3q16a : VLD3WB<0b0100, "vld3.16">;
226 def VLD3q32a : VLD3WB<0b1000, "vld3.32">;
228 // vld3 to double-spaced odd registers.
229 def VLD3q8b : VLD3WB<0b0000, "vld3.8">;
230 def VLD3q16b : VLD3WB<0b0100, "vld3.16">;
231 def VLD3q32b : VLD3WB<0b1000, "vld3.32">;
233 // VLD4 : Vector Load (multiple 4-element structures)
234 class VLD4D<bits<4> op7_4, string OpcodeStr>
235 : NLdSt<0,0b10,0b0000,op7_4,
236 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
237 (ins addrmode6:$addr), IIC_VLD4,
238 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"),
240 class VLD4WB<bits<4> op7_4, string OpcodeStr>
241 : NLdSt<0,0b10,0b0001,op7_4,
242 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
243 (ins addrmode6:$addr), IIC_VLD4,
244 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"),
245 "$addr.addr = $wb", []>;
247 def VLD4d8 : VLD4D<0b0000, "vld4.8">;
248 def VLD4d16 : VLD4D<0b0100, "vld4.16">;
249 def VLD4d32 : VLD4D<0b1000, "vld4.32">;
251 // vld4 to double-spaced even registers.
252 def VLD4q8a : VLD4WB<0b0000, "vld4.8">;
253 def VLD4q16a : VLD4WB<0b0100, "vld4.16">;
254 def VLD4q32a : VLD4WB<0b1000, "vld4.32">;
256 // vld4 to double-spaced odd registers.
257 def VLD4q8b : VLD4WB<0b0000, "vld4.8">;
258 def VLD4q16b : VLD4WB<0b0100, "vld4.16">;
259 def VLD4q32b : VLD4WB<0b1000, "vld4.32">;
261 // VLD1LN : Vector Load (single element to one lane)
262 // FIXME: Not yet implemented.
264 // VLD2LN : Vector Load (single 2-element structure to one lane)
265 class VLD2LND<bits<4> op11_8, string OpcodeStr>
266 : NLdSt<1,0b10,op11_8,0b0000, (outs DPR:$dst1, DPR:$dst2),
267 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
269 !strconcat(OpcodeStr, "\t\\{$dst1[$lane],$dst2[$lane]\\}, $addr"),
270 "$src1 = $dst1, $src2 = $dst2", []>;
272 def VLD2LNd8 : VLD2LND<0b0001, "vld2.8">;
273 def VLD2LNd16 : VLD2LND<0b0101, "vld2.16">;
274 def VLD2LNd32 : VLD2LND<0b1001, "vld2.32">;
276 // VLD3LN : Vector Load (single 3-element structure to one lane)
277 class VLD3LND<bits<4> op11_8, string OpcodeStr>
278 : NLdSt<1,0b10,op11_8,0b0000, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
279 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
280 nohash_imm:$lane), IIC_VLD3,
281 !strconcat(OpcodeStr,
282 "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane]\\}, $addr"),
283 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
285 def VLD3LNd8 : VLD3LND<0b0010, "vld3.8">;
286 def VLD3LNd16 : VLD3LND<0b0110, "vld3.16">;
287 def VLD3LNd32 : VLD3LND<0b1010, "vld3.32">;
289 // VLD4LN : Vector Load (single 4-element structure to one lane)
290 class VLD4LND<bits<4> op11_8, string OpcodeStr>
291 : NLdSt<1,0b10,op11_8,0b0000,
292 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
293 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
294 nohash_imm:$lane), IIC_VLD4,
295 !strconcat(OpcodeStr,
296 "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane],$dst4[$lane]\\}, $addr"),
297 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
299 def VLD4LNd8 : VLD4LND<0b0011, "vld4.8">;
300 def VLD4LNd16 : VLD4LND<0b0111, "vld4.16">;
301 def VLD4LNd32 : VLD4LND<0b1011, "vld4.32">;
303 // VLD1DUP : Vector Load (single element to all lanes)
304 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
305 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
306 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
307 // FIXME: Not yet implemented.
308 } // mayLoad = 1, hasExtraDefRegAllocReq = 1
310 // VST1 : Vector Store (multiple single elements)
311 class VST1D<bits<4> op7_4, string OpcodeStr, ValueType Ty, Intrinsic IntOp>
312 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src), IIC_VST,
313 !strconcat(OpcodeStr, "\t\\{$src\\}, $addr"), "",
314 [(IntOp addrmode6:$addr, (Ty DPR:$src))]>;
315 class VST1Q<bits<4> op7_4, string OpcodeStr, ValueType Ty, Intrinsic IntOp>
316 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$addr, QPR:$src), IIC_VST,
317 !strconcat(OpcodeStr, "\t${src:dregpair}, $addr"), "",
318 [(IntOp addrmode6:$addr, (Ty QPR:$src))]>;
320 let hasExtraSrcRegAllocReq = 1 in {
321 def VST1d8 : VST1D<0b0000, "vst1.8", v8i8, int_arm_neon_vst1>;
322 def VST1d16 : VST1D<0b0100, "vst1.16", v4i16, int_arm_neon_vst1>;
323 def VST1d32 : VST1D<0b1000, "vst1.32", v2i32, int_arm_neon_vst1>;
324 def VST1df : VST1D<0b1000, "vst1.32", v2f32, int_arm_neon_vst1>;
325 def VST1d64 : VST1D<0b1100, "vst1.64", v1i64, int_arm_neon_vst1>;
327 def VST1q8 : VST1Q<0b0000, "vst1.8", v16i8, int_arm_neon_vst1>;
328 def VST1q16 : VST1Q<0b0100, "vst1.16", v8i16, int_arm_neon_vst1>;
329 def VST1q32 : VST1Q<0b1000, "vst1.32", v4i32, int_arm_neon_vst1>;
330 def VST1qf : VST1Q<0b1000, "vst1.32", v4f32, int_arm_neon_vst1>;
331 def VST1q64 : VST1Q<0b1100, "vst1.64", v2i64, int_arm_neon_vst1>;
332 } // hasExtraSrcRegAllocReq
334 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
336 // VST2 : Vector Store (multiple 2-element structures)
337 class VST2D<bits<4> op7_4, string OpcodeStr>
338 : NLdSt<0,0b00,0b1000,op7_4, (outs),
339 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
340 !strconcat(OpcodeStr, "\t\\{$src1,$src2\\}, $addr"), "", []>;
341 class VST2Q<bits<4> op7_4, string OpcodeStr>
342 : NLdSt<0,0b00,0b0011,op7_4, (outs),
343 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
345 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"),
348 def VST2d8 : VST2D<0b0000, "vst2.8">;
349 def VST2d16 : VST2D<0b0100, "vst2.16">;
350 def VST2d32 : VST2D<0b1000, "vst2.32">;
352 def VST2q8 : VST2Q<0b0000, "vst2.8">;
353 def VST2q16 : VST2Q<0b0100, "vst2.16">;
354 def VST2q32 : VST2Q<0b1000, "vst2.32">;
356 // VST3 : Vector Store (multiple 3-element structures)
357 class VST3D<bits<4> op7_4, string OpcodeStr>
358 : NLdSt<0,0b00,0b0100,op7_4, (outs),
359 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
360 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"), "", []>;
361 class VST3WB<bits<4> op7_4, string OpcodeStr>
362 : NLdSt<0,0b00,0b0101,op7_4, (outs GPR:$wb),
363 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
364 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"),
365 "$addr.addr = $wb", []>;
367 def VST3d8 : VST3D<0b0000, "vst3.8">;
368 def VST3d16 : VST3D<0b0100, "vst3.16">;
369 def VST3d32 : VST3D<0b1000, "vst3.32">;
371 // vst3 to double-spaced even registers.
372 def VST3q8a : VST3WB<0b0000, "vst3.8">;
373 def VST3q16a : VST3WB<0b0100, "vst3.16">;
374 def VST3q32a : VST3WB<0b1000, "vst3.32">;
376 // vst3 to double-spaced odd registers.
377 def VST3q8b : VST3WB<0b0000, "vst3.8">;
378 def VST3q16b : VST3WB<0b0100, "vst3.16">;
379 def VST3q32b : VST3WB<0b1000, "vst3.32">;
381 // VST4 : Vector Store (multiple 4-element structures)
382 class VST4D<bits<4> op7_4, string OpcodeStr>
383 : NLdSt<0,0b00,0b0000,op7_4, (outs),
384 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
386 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"),
388 class VST4WB<bits<4> op7_4, string OpcodeStr>
389 : NLdSt<0,0b00,0b0001,op7_4, (outs GPR:$wb),
390 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
392 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"),
393 "$addr.addr = $wb", []>;
395 def VST4d8 : VST4D<0b0000, "vst4.8">;
396 def VST4d16 : VST4D<0b0100, "vst4.16">;
397 def VST4d32 : VST4D<0b1000, "vst4.32">;
399 // vst4 to double-spaced even registers.
400 def VST4q8a : VST4WB<0b0000, "vst4.8">;
401 def VST4q16a : VST4WB<0b0100, "vst4.16">;
402 def VST4q32a : VST4WB<0b1000, "vst4.32">;
404 // vst4 to double-spaced odd registers.
405 def VST4q8b : VST4WB<0b0000, "vst4.8">;
406 def VST4q16b : VST4WB<0b0100, "vst4.16">;
407 def VST4q32b : VST4WB<0b1000, "vst4.32">;
409 // VST1LN : Vector Store (single element from one lane)
410 // FIXME: Not yet implemented.
412 // VST2LN : Vector Store (single 2-element structure from one lane)
413 class VST2LND<bits<4> op11_8, string OpcodeStr>
414 : NLdSt<1,0b00,op11_8,0b0000, (outs),
415 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
417 !strconcat(OpcodeStr, "\t\\{$src1[$lane],$src2[$lane]\\}, $addr"),
420 def VST2LNd8 : VST2LND<0b0000, "vst2.8">;
421 def VST2LNd16 : VST2LND<0b0100, "vst2.16">;
422 def VST2LNd32 : VST2LND<0b1000, "vst2.32">;
424 // VST3LN : Vector Store (single 3-element structure from one lane)
425 class VST3LND<bits<4> op11_8, string OpcodeStr>
426 : NLdSt<1,0b00,op11_8,0b0000, (outs),
427 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
428 nohash_imm:$lane), IIC_VST,
429 !strconcat(OpcodeStr,
430 "\t\\{$src1[$lane],$src2[$lane],$src3[$lane]\\}, $addr"), "", []>;
432 def VST3LNd8 : VST3LND<0b0010, "vst3.8">;
433 def VST3LNd16 : VST3LND<0b0110, "vst3.16">;
434 def VST3LNd32 : VST3LND<0b1010, "vst3.32">;
436 // VST4LN : Vector Store (single 4-element structure from one lane)
437 class VST4LND<bits<4> op11_8, string OpcodeStr>
438 : NLdSt<1,0b00,op11_8,0b0000, (outs),
439 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
440 nohash_imm:$lane), IIC_VST,
441 !strconcat(OpcodeStr,
442 "\t\\{$src1[$lane],$src2[$lane],$src3[$lane],$src4[$lane]\\}, $addr"),
445 def VST4LNd8 : VST4LND<0b0011, "vst4.8">;
446 def VST4LNd16 : VST4LND<0b0111, "vst4.16">;
447 def VST4LNd32 : VST4LND<0b1011, "vst4.32">;
448 } // mayStore = 1, hasExtraSrcRegAllocReq = 1
451 //===----------------------------------------------------------------------===//
452 // NEON pattern fragments
453 //===----------------------------------------------------------------------===//
455 // Extract D sub-registers of Q registers.
456 // (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
457 def DSubReg_i8_reg : SDNodeXForm<imm, [{
458 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
460 def DSubReg_i16_reg : SDNodeXForm<imm, [{
461 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
463 def DSubReg_i32_reg : SDNodeXForm<imm, [{
464 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
466 def DSubReg_f64_reg : SDNodeXForm<imm, [{
467 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
469 def DSubReg_f64_other_reg : SDNodeXForm<imm, [{
470 return CurDAG->getTargetConstant(5 + (1 - N->getZExtValue()), MVT::i32);
473 // Extract S sub-registers of Q/D registers.
474 // (arm_ssubreg_0 is 1; arm_ssubreg_1 is 2; etc.)
475 def SSubReg_f32_reg : SDNodeXForm<imm, [{
476 return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32);
479 // Translate lane numbers from Q registers to D subregs.
480 def SubReg_i8_lane : SDNodeXForm<imm, [{
481 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
483 def SubReg_i16_lane : SDNodeXForm<imm, [{
484 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
486 def SubReg_i32_lane : SDNodeXForm<imm, [{
487 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
490 //===----------------------------------------------------------------------===//
491 // Instruction Classes
492 //===----------------------------------------------------------------------===//
494 // Basic 2-register operations, both double- and quad-register.
495 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
496 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
497 ValueType ResTy, ValueType OpTy, SDNode OpNode>
498 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
499 (ins DPR:$src), IIC_VUNAD, !strconcat(OpcodeStr, "\t$dst, $src"), "",
500 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
501 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
502 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
503 ValueType ResTy, ValueType OpTy, SDNode OpNode>
504 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
505 (ins QPR:$src), IIC_VUNAQ, !strconcat(OpcodeStr, "\t$dst, $src"), "",
506 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
508 // Basic 2-register operations, scalar single-precision.
509 class N2VDs<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
510 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
511 ValueType ResTy, ValueType OpTy, SDNode OpNode>
512 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
513 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
514 IIC_VUNAD, !strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
516 class N2VDsPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
517 : NEONFPPat<(ResTy (OpNode SPR:$a)),
519 (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
522 // Basic 2-register intrinsics, both double- and quad-register.
523 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
524 bits<2> op17_16, bits<5> op11_7, bit op4,
525 InstrItinClass itin, string OpcodeStr,
526 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
527 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
528 (ins DPR:$src), itin, !strconcat(OpcodeStr, "\t$dst, $src"), "",
529 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
530 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
531 bits<2> op17_16, bits<5> op11_7, bit op4,
532 InstrItinClass itin, string OpcodeStr,
533 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
534 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
535 (ins QPR:$src), itin, !strconcat(OpcodeStr, "\t$dst, $src"), "",
536 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
538 // Basic 2-register intrinsics, scalar single-precision
539 class N2VDInts<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
540 bits<2> op17_16, bits<5> op11_7, bit op4,
541 InstrItinClass itin, string OpcodeStr,
542 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
543 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
544 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), itin,
545 !strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
547 class N2VDIntsPat<SDNode OpNode, NeonI Inst>
548 : NEONFPPat<(f32 (OpNode SPR:$a)),
550 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
553 // Narrow 2-register intrinsics.
554 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
555 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
556 InstrItinClass itin, string OpcodeStr,
557 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
558 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
559 (ins QPR:$src), itin, !strconcat(OpcodeStr, "\t$dst, $src"), "",
560 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
562 // Long 2-register intrinsics. (This is currently only used for VMOVL and is
563 // derived from N2VImm instead of N2V because of the way the size is encoded.)
564 class N2VLInt<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
565 bit op6, bit op4, InstrItinClass itin, string OpcodeStr,
566 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
567 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4, (outs QPR:$dst),
568 (ins DPR:$src), itin, !strconcat(OpcodeStr, "\t$dst, $src"), "",
569 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
571 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
572 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr>
573 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
574 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
575 !strconcat(OpcodeStr, "\t$dst1, $dst2"),
576 "$src1 = $dst1, $src2 = $dst2", []>;
577 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
578 InstrItinClass itin, string OpcodeStr>
579 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
580 (ins QPR:$src1, QPR:$src2), itin,
581 !strconcat(OpcodeStr, "\t$dst1, $dst2"),
582 "$src1 = $dst1, $src2 = $dst2", []>;
584 // Basic 3-register operations, both double- and quad-register.
585 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
586 InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy,
587 SDNode OpNode, bit Commutable>
588 : N3V<op24, op23, op21_20, op11_8, 0, op4,
589 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
590 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
591 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
592 let isCommutable = Commutable;
594 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
595 InstrItinClass itin, string OpcodeStr, ValueType Ty, SDNode ShOp>
596 : N3V<0, 1, op21_20, op11_8, 1, 0,
597 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
598 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
600 (Ty (ShOp (Ty DPR:$src1),
601 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
603 let isCommutable = 0;
605 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
606 string OpcodeStr, ValueType Ty, SDNode ShOp>
607 : N3V<0, 1, op21_20, op11_8, 1, 0,
608 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
610 !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
612 (Ty (ShOp (Ty DPR:$src1),
613 (Ty (NEONvduplane (Ty DPR_8:$src2),
615 let isCommutable = 0;
618 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
619 InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy,
620 SDNode OpNode, bit Commutable>
621 : N3V<op24, op23, op21_20, op11_8, 1, op4,
622 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
623 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
624 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
625 let isCommutable = Commutable;
627 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
628 InstrItinClass itin, string OpcodeStr,
629 ValueType ResTy, ValueType OpTy, SDNode ShOp>
630 : N3V<1, 1, op21_20, op11_8, 1, 0,
631 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
632 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
633 [(set (ResTy QPR:$dst),
634 (ResTy (ShOp (ResTy QPR:$src1),
635 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
637 let isCommutable = 0;
639 class N3VQSL16<bits<2> op21_20, bits<4> op11_8,
640 string OpcodeStr, ValueType ResTy, ValueType OpTy, SDNode ShOp>
641 : N3V<1, 1, op21_20, op11_8, 1, 0,
642 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
644 !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
645 [(set (ResTy QPR:$dst),
646 (ResTy (ShOp (ResTy QPR:$src1),
647 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
649 let isCommutable = 0;
652 // Basic 3-register operations, scalar single-precision
653 class N3VDs<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
654 string OpcodeStr, ValueType ResTy, ValueType OpTy,
655 SDNode OpNode, bit Commutable>
656 : N3V<op24, op23, op21_20, op11_8, 0, op4,
657 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), IIC_VBIND,
658 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", []> {
659 let isCommutable = Commutable;
661 class N3VDsPat<SDNode OpNode, NeonI Inst>
662 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
664 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
665 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
668 // Basic 3-register intrinsics, both double- and quad-register.
669 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
670 InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy,
671 Intrinsic IntOp, bit Commutable>
672 : N3V<op24, op23, op21_20, op11_8, 0, op4,
673 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
674 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
675 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
676 let isCommutable = Commutable;
678 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
679 string OpcodeStr, ValueType Ty, Intrinsic IntOp>
680 : N3V<0, 1, op21_20, op11_8, 1, 0,
681 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
682 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
684 (Ty (IntOp (Ty DPR:$src1),
685 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
687 let isCommutable = 0;
689 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
690 string OpcodeStr, ValueType Ty, Intrinsic IntOp>
691 : N3V<0, 1, op21_20, op11_8, 1, 0,
692 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
693 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
695 (Ty (IntOp (Ty DPR:$src1),
696 (Ty (NEONvduplane (Ty DPR_8:$src2),
698 let isCommutable = 0;
701 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
702 InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy,
703 Intrinsic IntOp, bit Commutable>
704 : N3V<op24, op23, op21_20, op11_8, 1, op4,
705 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
706 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
707 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
708 let isCommutable = Commutable;
710 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
711 string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
712 : N3V<1, 1, op21_20, op11_8, 1, 0,
713 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
714 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
715 [(set (ResTy QPR:$dst),
716 (ResTy (IntOp (ResTy QPR:$src1),
717 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
719 let isCommutable = 0;
721 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
722 string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
723 : N3V<1, 1, op21_20, op11_8, 1, 0,
724 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
725 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
726 [(set (ResTy QPR:$dst),
727 (ResTy (IntOp (ResTy QPR:$src1),
728 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
730 let isCommutable = 0;
733 // Multiply-Add/Sub operations, both double- and quad-register.
734 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
735 InstrItinClass itin, string OpcodeStr,
736 ValueType Ty, SDNode MulOp, SDNode OpNode>
737 : N3V<op24, op23, op21_20, op11_8, 0, op4,
738 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin,
739 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
740 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
741 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
742 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
743 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode ShOp>
744 : N3V<0, 1, op21_20, op11_8, 1, 0,
746 (ins DPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
747 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
749 (Ty (ShOp (Ty DPR:$src1),
750 (Ty (MulOp DPR:$src2,
751 (Ty (NEONvduplane (Ty DPR_VFP2:$src3),
753 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
754 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode ShOp>
755 : N3V<0, 1, op21_20, op11_8, 1, 0,
757 (ins DPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
758 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
760 (Ty (ShOp (Ty DPR:$src1),
761 (Ty (MulOp DPR:$src2,
762 (Ty (NEONvduplane (Ty DPR_8:$src3),
765 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
766 InstrItinClass itin, string OpcodeStr, ValueType Ty,
767 SDNode MulOp, SDNode OpNode>
768 : N3V<op24, op23, op21_20, op11_8, 1, op4,
769 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin,
770 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
771 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
772 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
773 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
774 string OpcodeStr, ValueType ResTy, ValueType OpTy,
775 SDNode MulOp, SDNode ShOp>
776 : N3V<1, 1, op21_20, op11_8, 1, 0,
778 (ins QPR:$src1, QPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
779 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
780 [(set (ResTy QPR:$dst),
781 (ResTy (ShOp (ResTy QPR:$src1),
782 (ResTy (MulOp QPR:$src2,
783 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src3),
785 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
786 string OpcodeStr, ValueType ResTy, ValueType OpTy,
787 SDNode MulOp, SDNode ShOp>
788 : N3V<1, 1, op21_20, op11_8, 1, 0,
790 (ins QPR:$src1, QPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
791 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
792 [(set (ResTy QPR:$dst),
793 (ResTy (ShOp (ResTy QPR:$src1),
794 (ResTy (MulOp QPR:$src2,
795 (ResTy (NEONvduplane (OpTy DPR_8:$src3),
798 // Multiply-Add/Sub operations, scalar single-precision
799 class N3VDMulOps<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
800 InstrItinClass itin, string OpcodeStr,
801 ValueType Ty, SDNode MulOp, SDNode OpNode>
802 : N3V<op24, op23, op21_20, op11_8, 0, op4,
803 (outs DPR_VFP2:$dst),
804 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), itin,
805 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", []>;
807 class N3VDMulOpsPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
808 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
810 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$acc, arm_ssubreg_0),
811 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
812 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
815 // Neon 3-argument intrinsics, both double- and quad-register.
816 // The destination register is also used as the first source operand register.
817 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
818 InstrItinClass itin, string OpcodeStr,
819 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
820 : N3V<op24, op23, op21_20, op11_8, 0, op4,
821 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin,
822 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
823 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
824 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
825 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
826 InstrItinClass itin, string OpcodeStr,
827 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
828 : N3V<op24, op23, op21_20, op11_8, 1, op4,
829 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin,
830 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
831 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
832 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
834 // Neon Long 3-argument intrinsic. The destination register is
835 // a quad-register and is also used as the first source operand register.
836 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
837 InstrItinClass itin, string OpcodeStr,
838 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
839 : N3V<op24, op23, op21_20, op11_8, 0, op4,
840 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), itin,
841 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
843 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
844 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
845 string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
846 : N3V<op24, 1, op21_20, op11_8, 1, 0,
848 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
849 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
850 [(set (ResTy QPR:$dst),
851 (ResTy (IntOp (ResTy QPR:$src1),
853 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src3),
855 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
856 string OpcodeStr, ValueType ResTy, ValueType OpTy,
858 : N3V<op24, 1, op21_20, op11_8, 1, 0,
860 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
861 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
862 [(set (ResTy QPR:$dst),
863 (ResTy (IntOp (ResTy QPR:$src1),
865 (OpTy (NEONvduplane (OpTy DPR_8:$src3),
869 // Narrowing 3-register intrinsics.
870 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
871 string OpcodeStr, ValueType TyD, ValueType TyQ,
872 Intrinsic IntOp, bit Commutable>
873 : N3V<op24, op23, op21_20, op11_8, 0, op4,
874 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VBINi4D,
875 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
876 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
877 let isCommutable = Commutable;
880 // Long 3-register intrinsics.
881 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
882 InstrItinClass itin, string OpcodeStr, ValueType TyQ, ValueType TyD,
883 Intrinsic IntOp, bit Commutable>
884 : N3V<op24, op23, op21_20, op11_8, 0, op4,
885 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
886 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
887 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
888 let isCommutable = Commutable;
890 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
891 string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
892 : N3V<op24, 1, op21_20, op11_8, 1, 0,
893 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
894 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
895 [(set (ResTy QPR:$dst),
896 (ResTy (IntOp (OpTy DPR:$src1),
897 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src2),
899 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
900 string OpcodeStr, ValueType ResTy, ValueType OpTy,
902 : N3V<op24, 1, op21_20, op11_8, 1, 0,
903 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
904 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
905 [(set (ResTy QPR:$dst),
906 (ResTy (IntOp (OpTy DPR:$src1),
907 (OpTy (NEONvduplane (OpTy DPR_8:$src2),
910 // Wide 3-register intrinsics.
911 class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
912 string OpcodeStr, ValueType TyQ, ValueType TyD,
913 Intrinsic IntOp, bit Commutable>
914 : N3V<op24, op23, op21_20, op11_8, 0, op4,
915 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), IIC_VSUBiD,
916 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
917 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
918 let isCommutable = Commutable;
921 // Pairwise long 2-register intrinsics, both double- and quad-register.
922 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
923 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
924 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
925 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
926 (ins DPR:$src), IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "",
927 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
928 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
929 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
930 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
931 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
932 (ins QPR:$src), IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "",
933 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
935 // Pairwise long 2-register accumulate intrinsics,
936 // both double- and quad-register.
937 // The destination register is also used as the first source operand register.
938 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
939 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
940 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
941 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
942 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), IIC_VPALiD,
943 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
944 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
945 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
946 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
947 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
948 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
949 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VPALiQ,
950 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
951 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
953 // Shift by immediate,
954 // both double- and quad-register.
955 class N2VDSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
956 bit op4, InstrItinClass itin, string OpcodeStr,
957 ValueType Ty, SDNode OpNode>
958 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
959 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), itin,
960 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
961 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
962 class N2VQSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
963 bit op4, InstrItinClass itin, string OpcodeStr,
964 ValueType Ty, SDNode OpNode>
965 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
966 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin,
967 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
968 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
970 // Long shift by immediate.
971 class N2VLSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
972 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
973 ValueType OpTy, SDNode OpNode>
974 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
975 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VSHLiD,
976 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
977 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
978 (i32 imm:$SIMM))))]>;
980 // Narrow shift by immediate.
981 class N2VNSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
982 bit op6, bit op4, InstrItinClass itin, string OpcodeStr,
983 ValueType ResTy, ValueType OpTy, SDNode OpNode>
984 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
985 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin,
986 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
987 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
988 (i32 imm:$SIMM))))]>;
990 // Shift right by immediate and accumulate,
991 // both double- and quad-register.
992 class N2VDShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
993 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
994 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
995 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
997 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
998 [(set DPR:$dst, (Ty (add DPR:$src1,
999 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
1000 class N2VQShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
1001 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
1002 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
1003 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
1005 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
1006 [(set QPR:$dst, (Ty (add QPR:$src1,
1007 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
1009 // Shift by immediate and insert,
1010 // both double- and quad-register.
1011 class N2VDShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
1012 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
1013 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
1014 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
1016 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
1017 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
1018 class N2VQShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
1019 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
1020 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
1021 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
1023 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
1024 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
1026 // Convert, with fractional bits immediate,
1027 // both double- and quad-register.
1028 class N2VCvtD<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
1029 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
1031 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
1032 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VUNAD,
1033 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
1034 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
1035 class N2VCvtQ<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
1036 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
1038 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
1039 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), IIC_VUNAQ,
1040 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
1041 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
1043 //===----------------------------------------------------------------------===//
1045 //===----------------------------------------------------------------------===//
1047 // Abbreviations used in multiclass suffixes:
1048 // Q = quarter int (8 bit) elements
1049 // H = half int (16 bit) elements
1050 // S = single int (32 bit) elements
1051 // D = double int (64 bit) elements
1053 // Neon 3-register vector operations.
1055 // First with only element sizes of 8, 16 and 32 bits:
1056 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1057 InstrItinClass itinD16, InstrItinClass itinD32,
1058 InstrItinClass itinQ16, InstrItinClass itinQ32,
1059 string OpcodeStr, SDNode OpNode, bit Commutable = 0> {
1060 // 64-bit vector types.
1061 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
1062 !strconcat(OpcodeStr, "8"), v8i8, v8i8, OpNode, Commutable>;
1063 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
1064 !strconcat(OpcodeStr, "16"), v4i16, v4i16, OpNode, Commutable>;
1065 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
1066 !strconcat(OpcodeStr, "32"), v2i32, v2i32, OpNode, Commutable>;
1068 // 128-bit vector types.
1069 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
1070 !strconcat(OpcodeStr, "8"), v16i8, v16i8, OpNode, Commutable>;
1071 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
1072 !strconcat(OpcodeStr, "16"), v8i16, v8i16, OpNode, Commutable>;
1073 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
1074 !strconcat(OpcodeStr, "32"), v4i32, v4i32, OpNode, Commutable>;
1077 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, SDNode ShOp> {
1078 def v4i16 : N3VDSL16<0b01, op11_8, !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
1079 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
1080 def v8i16 : N3VQSL16<0b01, op11_8, !strconcat(OpcodeStr, "16"), v8i16, v4i16, ShOp>;
1081 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, !strconcat(OpcodeStr, "32"), v4i32, v2i32, ShOp>;
1084 // ....then also with element size 64 bits:
1085 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1086 InstrItinClass itinD, InstrItinClass itinQ,
1087 string OpcodeStr, SDNode OpNode, bit Commutable = 0>
1088 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
1089 OpcodeStr, OpNode, Commutable> {
1090 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
1091 !strconcat(OpcodeStr, "64"), v1i64, v1i64, OpNode, Commutable>;
1092 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
1093 !strconcat(OpcodeStr, "64"), v2i64, v2i64, OpNode, Commutable>;
1097 // Neon Narrowing 2-register vector intrinsics,
1098 // source operand element sizes of 16, 32 and 64 bits:
1099 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1100 bits<5> op11_7, bit op6, bit op4,
1101 InstrItinClass itin, string OpcodeStr,
1103 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
1104 itin, !strconcat(OpcodeStr, "16"), v8i8, v8i16, IntOp>;
1105 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
1106 itin, !strconcat(OpcodeStr, "32"), v4i16, v4i32, IntOp>;
1107 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
1108 itin, !strconcat(OpcodeStr, "64"), v2i32, v2i64, IntOp>;
1112 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
1113 // source operand element sizes of 16, 32 and 64 bits:
1114 multiclass N2VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
1115 bit op4, string OpcodeStr, Intrinsic IntOp> {
1116 def v8i16 : N2VLInt<op24, op23, 0b001000, op11_8, op7, op6, op4,
1117 IIC_VQUNAiD, !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
1118 def v4i32 : N2VLInt<op24, op23, 0b010000, op11_8, op7, op6, op4,
1119 IIC_VQUNAiD, !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
1120 def v2i64 : N2VLInt<op24, op23, 0b100000, op11_8, op7, op6, op4,
1121 IIC_VQUNAiD, !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
1125 // Neon 3-register vector intrinsics.
1127 // First with only element sizes of 16 and 32 bits:
1128 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1129 InstrItinClass itinD16, InstrItinClass itinD32,
1130 InstrItinClass itinQ16, InstrItinClass itinQ32,
1131 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
1132 // 64-bit vector types.
1133 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, itinD16, !strconcat(OpcodeStr,"16"),
1134 v4i16, v4i16, IntOp, Commutable>;
1135 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, itinD32, !strconcat(OpcodeStr,"32"),
1136 v2i32, v2i32, IntOp, Commutable>;
1138 // 128-bit vector types.
1139 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, itinQ16, !strconcat(OpcodeStr,"16"),
1140 v8i16, v8i16, IntOp, Commutable>;
1141 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, itinQ32, !strconcat(OpcodeStr,"32"),
1142 v4i32, v4i32, IntOp, Commutable>;
1145 multiclass N3VIntSL_HS<bits<4> op11_8,
1146 InstrItinClass itinD16, InstrItinClass itinD32,
1147 InstrItinClass itinQ16, InstrItinClass itinQ32,
1148 string OpcodeStr, Intrinsic IntOp> {
1149 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16, !strconcat(OpcodeStr, "16"), v4i16, IntOp>;
1150 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32, !strconcat(OpcodeStr, "32"), v2i32, IntOp>;
1151 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16, !strconcat(OpcodeStr, "16"), v8i16, v4i16, IntOp>;
1152 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32, !strconcat(OpcodeStr, "32"), v4i32, v2i32, IntOp>;
1155 // ....then also with element size of 8 bits:
1156 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1157 InstrItinClass itinD16, InstrItinClass itinD32,
1158 InstrItinClass itinQ16, InstrItinClass itinQ32,
1159 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
1160 : N3VInt_HS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
1161 OpcodeStr, IntOp, Commutable> {
1162 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, itinD16,
1163 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp, Commutable>;
1164 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, itinQ16,
1165 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp, Commutable>;
1168 // ....then also with element size of 64 bits:
1169 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1170 InstrItinClass itinD16, InstrItinClass itinD32,
1171 InstrItinClass itinQ16, InstrItinClass itinQ32,
1172 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
1173 : N3VInt_QHS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
1174 OpcodeStr, IntOp, Commutable> {
1175 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, itinD32,
1176 !strconcat(OpcodeStr,"64"), v1i64, v1i64, IntOp, Commutable>;
1177 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, itinQ32,
1178 !strconcat(OpcodeStr,"64"), v2i64, v2i64, IntOp, Commutable>;
1182 // Neon Narrowing 3-register vector intrinsics,
1183 // source operand element sizes of 16, 32 and 64 bits:
1184 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1185 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
1186 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr,"16"),
1187 v8i8, v8i16, IntOp, Commutable>;
1188 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"32"),
1189 v4i16, v4i32, IntOp, Commutable>;
1190 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"64"),
1191 v2i32, v2i64, IntOp, Commutable>;
1195 // Neon Long 3-register vector intrinsics.
1197 // First with only element sizes of 16 and 32 bits:
1198 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1199 InstrItinClass itin, string OpcodeStr,
1200 Intrinsic IntOp, bit Commutable = 0> {
1201 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin,
1202 !strconcat(OpcodeStr,"16"), v4i32, v4i16, IntOp, Commutable>;
1203 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin,
1204 !strconcat(OpcodeStr,"32"), v2i64, v2i32, IntOp, Commutable>;
1207 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
1208 InstrItinClass itin, string OpcodeStr, Intrinsic IntOp> {
1209 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
1210 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
1211 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
1212 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
1215 // ....then also with element size of 8 bits:
1216 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1217 InstrItinClass itin, string OpcodeStr,
1218 Intrinsic IntOp, bit Commutable = 0>
1219 : N3VLInt_HS<op24, op23, op11_8, op4, itin, OpcodeStr, IntOp, Commutable> {
1220 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin,
1221 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp, Commutable>;
1225 // Neon Wide 3-register vector intrinsics,
1226 // source operand element sizes of 8, 16 and 32 bits:
1227 multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1228 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
1229 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
1230 v8i16, v8i8, IntOp, Commutable>;
1231 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
1232 v4i32, v4i16, IntOp, Commutable>;
1233 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
1234 v2i64, v2i32, IntOp, Commutable>;
1238 // Neon Multiply-Op vector operations,
1239 // element sizes of 8, 16 and 32 bits:
1240 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1241 InstrItinClass itinD16, InstrItinClass itinD32,
1242 InstrItinClass itinQ16, InstrItinClass itinQ32,
1243 string OpcodeStr, SDNode OpNode> {
1244 // 64-bit vector types.
1245 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
1246 !strconcat(OpcodeStr, "8"), v8i8, mul, OpNode>;
1247 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
1248 !strconcat(OpcodeStr, "16"), v4i16, mul, OpNode>;
1249 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
1250 !strconcat(OpcodeStr, "32"), v2i32, mul, OpNode>;
1252 // 128-bit vector types.
1253 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
1254 !strconcat(OpcodeStr, "8"), v16i8, mul, OpNode>;
1255 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
1256 !strconcat(OpcodeStr, "16"), v8i16, mul, OpNode>;
1257 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
1258 !strconcat(OpcodeStr, "32"), v4i32, mul, OpNode>;
1261 multiclass N3VMulOpSL_HS<bits<4> op11_8,
1262 InstrItinClass itinD16, InstrItinClass itinD32,
1263 InstrItinClass itinQ16, InstrItinClass itinQ32,
1264 string OpcodeStr, SDNode ShOp> {
1265 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
1266 !strconcat(OpcodeStr, "16"), v4i16, mul, ShOp>;
1267 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
1268 !strconcat(OpcodeStr, "32"), v2i32, mul, ShOp>;
1269 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
1270 !strconcat(OpcodeStr, "16"), v8i16, v4i16, mul, ShOp>;
1271 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
1272 !strconcat(OpcodeStr, "32"), v4i32, v2i32, mul, ShOp>;
1275 // Neon 3-argument intrinsics,
1276 // element sizes of 8, 16 and 32 bits:
1277 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1278 string OpcodeStr, Intrinsic IntOp> {
1279 // 64-bit vector types.
1280 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16D,
1281 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
1282 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
1283 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
1284 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32D,
1285 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
1287 // 128-bit vector types.
1288 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16Q,
1289 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
1290 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16Q,
1291 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
1292 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32Q,
1293 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
1297 // Neon Long 3-argument intrinsics.
1299 // First with only element sizes of 16 and 32 bits:
1300 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1301 string OpcodeStr, Intrinsic IntOp> {
1302 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
1303 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
1304 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi16D,
1305 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
1308 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
1309 string OpcodeStr, Intrinsic IntOp> {
1310 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
1311 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
1312 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
1313 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
1316 // ....then also with element size of 8 bits:
1317 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1318 string OpcodeStr, Intrinsic IntOp>
1319 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp> {
1320 def v8i16 : N3VLInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
1321 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
1325 // Neon 2-register vector intrinsics,
1326 // element sizes of 8, 16 and 32 bits:
1327 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1328 bits<5> op11_7, bit op4,
1329 InstrItinClass itinD, InstrItinClass itinQ,
1330 string OpcodeStr, Intrinsic IntOp> {
1331 // 64-bit vector types.
1332 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1333 itinD, !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
1334 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1335 itinD, !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
1336 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1337 itinD, !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
1339 // 128-bit vector types.
1340 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1341 itinQ, !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
1342 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1343 itinQ, !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
1344 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1345 itinQ, !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
1349 // Neon Pairwise long 2-register intrinsics,
1350 // element sizes of 8, 16 and 32 bits:
1351 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1352 bits<5> op11_7, bit op4,
1353 string OpcodeStr, Intrinsic IntOp> {
1354 // 64-bit vector types.
1355 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1356 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
1357 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1358 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
1359 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1360 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
1362 // 128-bit vector types.
1363 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1364 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
1365 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1366 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
1367 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1368 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
1372 // Neon Pairwise long 2-register accumulate intrinsics,
1373 // element sizes of 8, 16 and 32 bits:
1374 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1375 bits<5> op11_7, bit op4,
1376 string OpcodeStr, Intrinsic IntOp> {
1377 // 64-bit vector types.
1378 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1379 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
1380 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1381 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
1382 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1383 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
1385 // 128-bit vector types.
1386 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1387 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
1388 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1389 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
1390 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1391 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
1395 // Neon 2-register vector shift by immediate,
1396 // element sizes of 8, 16, 32 and 64 bits:
1397 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1398 InstrItinClass itin, string OpcodeStr, SDNode OpNode> {
1399 // 64-bit vector types.
1400 def v8i8 : N2VDSh<op24, op23, 0b001000, op11_8, 0, op4, itin,
1401 !strconcat(OpcodeStr, "8"), v8i8, OpNode>;
1402 def v4i16 : N2VDSh<op24, op23, 0b010000, op11_8, 0, op4, itin,
1403 !strconcat(OpcodeStr, "16"), v4i16, OpNode>;
1404 def v2i32 : N2VDSh<op24, op23, 0b100000, op11_8, 0, op4, itin,
1405 !strconcat(OpcodeStr, "32"), v2i32, OpNode>;
1406 def v1i64 : N2VDSh<op24, op23, 0b000000, op11_8, 1, op4, itin,
1407 !strconcat(OpcodeStr, "64"), v1i64, OpNode>;
1409 // 128-bit vector types.
1410 def v16i8 : N2VQSh<op24, op23, 0b001000, op11_8, 0, op4, itin,
1411 !strconcat(OpcodeStr, "8"), v16i8, OpNode>;
1412 def v8i16 : N2VQSh<op24, op23, 0b010000, op11_8, 0, op4, itin,
1413 !strconcat(OpcodeStr, "16"), v8i16, OpNode>;
1414 def v4i32 : N2VQSh<op24, op23, 0b100000, op11_8, 0, op4, itin,
1415 !strconcat(OpcodeStr, "32"), v4i32, OpNode>;
1416 def v2i64 : N2VQSh<op24, op23, 0b000000, op11_8, 1, op4, itin,
1417 !strconcat(OpcodeStr, "64"), v2i64, OpNode>;
1421 // Neon Shift-Accumulate vector operations,
1422 // element sizes of 8, 16, 32 and 64 bits:
1423 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1424 string OpcodeStr, SDNode ShOp> {
1425 // 64-bit vector types.
1426 def v8i8 : N2VDShAdd<op24, op23, 0b001000, op11_8, 0, op4,
1427 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
1428 def v4i16 : N2VDShAdd<op24, op23, 0b010000, op11_8, 0, op4,
1429 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
1430 def v2i32 : N2VDShAdd<op24, op23, 0b100000, op11_8, 0, op4,
1431 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
1432 def v1i64 : N2VDShAdd<op24, op23, 0b000000, op11_8, 1, op4,
1433 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
1435 // 128-bit vector types.
1436 def v16i8 : N2VQShAdd<op24, op23, 0b001000, op11_8, 0, op4,
1437 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
1438 def v8i16 : N2VQShAdd<op24, op23, 0b010000, op11_8, 0, op4,
1439 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
1440 def v4i32 : N2VQShAdd<op24, op23, 0b100000, op11_8, 0, op4,
1441 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
1442 def v2i64 : N2VQShAdd<op24, op23, 0b000000, op11_8, 1, op4,
1443 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
1447 // Neon Shift-Insert vector operations,
1448 // element sizes of 8, 16, 32 and 64 bits:
1449 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1450 string OpcodeStr, SDNode ShOp> {
1451 // 64-bit vector types.
1452 def v8i8 : N2VDShIns<op24, op23, 0b001000, op11_8, 0, op4,
1453 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
1454 def v4i16 : N2VDShIns<op24, op23, 0b010000, op11_8, 0, op4,
1455 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
1456 def v2i32 : N2VDShIns<op24, op23, 0b100000, op11_8, 0, op4,
1457 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
1458 def v1i64 : N2VDShIns<op24, op23, 0b000000, op11_8, 1, op4,
1459 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
1461 // 128-bit vector types.
1462 def v16i8 : N2VQShIns<op24, op23, 0b001000, op11_8, 0, op4,
1463 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
1464 def v8i16 : N2VQShIns<op24, op23, 0b010000, op11_8, 0, op4,
1465 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
1466 def v4i32 : N2VQShIns<op24, op23, 0b100000, op11_8, 0, op4,
1467 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
1468 def v2i64 : N2VQShIns<op24, op23, 0b000000, op11_8, 1, op4,
1469 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
1472 //===----------------------------------------------------------------------===//
1473 // Instruction Definitions.
1474 //===----------------------------------------------------------------------===//
1476 // Vector Add Operations.
1478 // VADD : Vector Add (integer and floating-point)
1479 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd.i", add, 1>;
1480 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd.f32", v2f32, v2f32, fadd, 1>;
1481 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd.f32", v4f32, v4f32, fadd, 1>;
1482 // VADDL : Vector Add Long (Q = D + D)
1483 defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, IIC_VSHLiD, "vaddl.s", int_arm_neon_vaddls, 1>;
1484 defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, IIC_VSHLiD, "vaddl.u", int_arm_neon_vaddlu, 1>;
1485 // VADDW : Vector Add Wide (Q = Q + D)
1486 defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw.s", int_arm_neon_vaddws, 0>;
1487 defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw.u", int_arm_neon_vaddwu, 0>;
1488 // VHADD : Vector Halving Add
1489 defm VHADDs : N3VInt_QHS<0,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1490 IIC_VBINi4Q, "vhadd.s", int_arm_neon_vhadds, 1>;
1491 defm VHADDu : N3VInt_QHS<1,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1492 IIC_VBINi4Q, "vhadd.u", int_arm_neon_vhaddu, 1>;
1493 // VRHADD : Vector Rounding Halving Add
1494 defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1495 IIC_VBINi4Q, "vrhadd.s", int_arm_neon_vrhadds, 1>;
1496 defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1497 IIC_VBINi4Q, "vrhadd.u", int_arm_neon_vrhaddu, 1>;
1498 // VQADD : Vector Saturating Add
1499 defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1500 IIC_VBINi4Q, "vqadd.s", int_arm_neon_vqadds, 1>;
1501 defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1502 IIC_VBINi4Q, "vqadd.u", int_arm_neon_vqaddu, 1>;
1503 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
1504 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn.i", int_arm_neon_vaddhn, 1>;
1505 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
1506 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn.i", int_arm_neon_vraddhn, 1>;
1508 // Vector Multiply Operations.
1510 // VMUL : Vector Multiply (integer, polynomial and floating-point)
1511 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D, IIC_VMULi16Q,
1512 IIC_VMULi32Q, "vmul.i", mul, 1>;
1513 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16D, "vmul.p8", v8i8, v8i8,
1514 int_arm_neon_vmulp, 1>;
1515 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16Q, "vmul.p8", v16i8, v16i8,
1516 int_arm_neon_vmulp, 1>;
1517 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VBIND, "vmul.f32", v2f32, v2f32, fmul, 1>;
1518 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VBINQ, "vmul.f32", v4f32, v4f32, fmul, 1>;
1519 defm VMULsl : N3VSL_HS<0b1000, "vmul.i", mul>;
1520 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul.f32", v2f32, fmul>;
1521 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul.f32", v4f32, v2f32, fmul>;
1522 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
1523 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
1524 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
1525 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1526 (DSubReg_i16_reg imm:$lane))),
1527 (SubReg_i16_lane imm:$lane)))>;
1528 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
1529 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
1530 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
1531 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1532 (DSubReg_i32_reg imm:$lane))),
1533 (SubReg_i32_lane imm:$lane)))>;
1534 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
1535 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
1536 (v4f32 (VMULslfq (v4f32 QPR:$src1),
1537 (v2f32 (EXTRACT_SUBREG QPR:$src2,
1538 (DSubReg_i32_reg imm:$lane))),
1539 (SubReg_i32_lane imm:$lane)))>;
1541 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
1542 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
1543 IIC_VMULi16Q, IIC_VMULi32Q,
1544 "vqdmulh.s", int_arm_neon_vqdmulh, 1>;
1545 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
1546 IIC_VMULi16Q, IIC_VMULi32Q,
1547 "vqdmulh.s", int_arm_neon_vqdmulh>;
1548 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
1549 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
1550 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
1551 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1552 (DSubReg_i16_reg imm:$lane))),
1553 (SubReg_i16_lane imm:$lane)))>;
1554 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
1555 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
1556 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
1557 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1558 (DSubReg_i32_reg imm:$lane))),
1559 (SubReg_i32_lane imm:$lane)))>;
1561 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
1562 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
1563 IIC_VMULi16Q, IIC_VMULi32Q,
1564 "vqrdmulh.s", int_arm_neon_vqrdmulh, 1>;
1565 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
1566 IIC_VMULi16Q, IIC_VMULi32Q,
1567 "vqrdmulh.s", int_arm_neon_vqrdmulh>;
1568 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
1569 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
1570 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
1571 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1572 (DSubReg_i16_reg imm:$lane))),
1573 (SubReg_i16_lane imm:$lane)))>;
1574 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
1575 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
1576 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
1577 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1578 (DSubReg_i32_reg imm:$lane))),
1579 (SubReg_i32_lane imm:$lane)))>;
1581 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
1582 defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, IIC_VMULi16D, "vmull.s", int_arm_neon_vmulls, 1>;
1583 defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, IIC_VMULi16D, "vmull.u", int_arm_neon_vmullu, 1>;
1584 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull.p8", v8i16, v8i8,
1585 int_arm_neon_vmullp, 1>;
1586 defm VMULLsls : N3VLIntSL_HS<0, 0b1010, IIC_VMULi16D, "vmull.s", int_arm_neon_vmulls>;
1587 defm VMULLslu : N3VLIntSL_HS<1, 0b1010, IIC_VMULi16D, "vmull.u", int_arm_neon_vmullu>;
1589 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
1590 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, "vqdmull.s", int_arm_neon_vqdmull, 1>;
1591 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D, "vqdmull.s", int_arm_neon_vqdmull>;
1593 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
1595 // VMLA : Vector Multiply Accumulate (integer and floating-point)
1596 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
1597 IIC_VMACi16Q, IIC_VMACi32Q, "vmla.i", add>;
1598 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla.f32", v2f32, fmul, fadd>;
1599 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla.f32", v4f32, fmul, fadd>;
1600 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
1601 IIC_VMACi16Q, IIC_VMACi32Q, "vmla.i", add>;
1602 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla.f32", v2f32, fmul, fadd>;
1603 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla.f32", v4f32, v2f32, fmul, fadd>;
1605 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
1606 (mul (v8i16 QPR:$src2),
1607 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
1608 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1),
1610 (v4i16 (EXTRACT_SUBREG QPR:$src3,
1611 (DSubReg_i16_reg imm:$lane))),
1612 (SubReg_i16_lane imm:$lane)))>;
1614 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
1615 (mul (v4i32 QPR:$src2),
1616 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
1617 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1),
1619 (v2i32 (EXTRACT_SUBREG QPR:$src3,
1620 (DSubReg_i32_reg imm:$lane))),
1621 (SubReg_i32_lane imm:$lane)))>;
1623 def : Pat<(v4f32 (fadd (v4f32 QPR:$src1),
1624 (fmul (v4f32 QPR:$src2),
1625 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
1626 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
1628 (v2f32 (EXTRACT_SUBREG QPR:$src3,
1629 (DSubReg_i32_reg imm:$lane))),
1630 (SubReg_i32_lane imm:$lane)))>;
1632 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
1633 defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal.s", int_arm_neon_vmlals>;
1634 defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal.u", int_arm_neon_vmlalu>;
1636 defm VMLALsls : N3VLInt3SL_HS<0, 0b0010, "vmlal.s", int_arm_neon_vmlals>;
1637 defm VMLALslu : N3VLInt3SL_HS<1, 0b0010, "vmlal.u", int_arm_neon_vmlalu>;
1639 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
1640 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal.s", int_arm_neon_vqdmlal>;
1641 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal.s", int_arm_neon_vqdmlal>;
1643 // VMLS : Vector Multiply Subtract (integer and floating-point)
1644 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
1645 IIC_VMACi16Q, IIC_VMACi32Q, "vmls.i", sub>;
1646 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls.f32", v2f32, fmul, fsub>;
1647 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls.f32", v4f32, fmul, fsub>;
1648 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
1649 IIC_VMACi16Q, IIC_VMACi32Q, "vmls.i", sub>;
1650 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls.f32", v2f32, fmul, fsub>;
1651 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls.f32", v4f32, v2f32, fmul, fsub>;
1653 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
1654 (mul (v8i16 QPR:$src2),
1655 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
1656 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1),
1658 (v4i16 (EXTRACT_SUBREG QPR:$src3,
1659 (DSubReg_i16_reg imm:$lane))),
1660 (SubReg_i16_lane imm:$lane)))>;
1662 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
1663 (mul (v4i32 QPR:$src2),
1664 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
1665 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1),
1667 (v2i32 (EXTRACT_SUBREG QPR:$src3,
1668 (DSubReg_i32_reg imm:$lane))),
1669 (SubReg_i32_lane imm:$lane)))>;
1671 def : Pat<(v4f32 (fsub (v4f32 QPR:$src1),
1672 (fmul (v4f32 QPR:$src2),
1673 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
1674 (v4f32 (VMLSslfq (v4f32 QPR:$src1),
1676 (v2f32 (EXTRACT_SUBREG QPR:$src3,
1677 (DSubReg_i32_reg imm:$lane))),
1678 (SubReg_i32_lane imm:$lane)))>;
1680 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
1681 defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl.s", int_arm_neon_vmlsls>;
1682 defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl.u", int_arm_neon_vmlslu>;
1684 defm VMLSLsls : N3VLInt3SL_HS<0, 0b0110, "vmlsl.s", int_arm_neon_vmlsls>;
1685 defm VMLSLslu : N3VLInt3SL_HS<1, 0b0110, "vmlsl.u", int_arm_neon_vmlslu>;
1687 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
1688 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl.s", int_arm_neon_vqdmlsl>;
1689 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl.s", int_arm_neon_vqdmlsl>;
1691 // Vector Subtract Operations.
1693 // VSUB : Vector Subtract (integer and floating-point)
1694 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ, "vsub.i", sub, 0>;
1695 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub.f32", v2f32, v2f32, fsub, 0>;
1696 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub.f32", v4f32, v4f32, fsub, 0>;
1697 // VSUBL : Vector Subtract Long (Q = D - D)
1698 defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, IIC_VSHLiD, "vsubl.s", int_arm_neon_vsubls, 1>;
1699 defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, IIC_VSHLiD, "vsubl.u", int_arm_neon_vsublu, 1>;
1700 // VSUBW : Vector Subtract Wide (Q = Q - D)
1701 defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw.s", int_arm_neon_vsubws, 0>;
1702 defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw.u", int_arm_neon_vsubwu, 0>;
1703 // VHSUB : Vector Halving Subtract
1704 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1705 IIC_VBINi4Q, "vhsub.s", int_arm_neon_vhsubs, 0>;
1706 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1707 IIC_VBINi4Q, "vhsub.u", int_arm_neon_vhsubu, 0>;
1708 // VQSUB : Vector Saturing Subtract
1709 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1710 IIC_VBINi4Q, "vqsub.s", int_arm_neon_vqsubs, 0>;
1711 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1712 IIC_VBINi4Q, "vqsub.u", int_arm_neon_vqsubu, 0>;
1713 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
1714 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn.i", int_arm_neon_vsubhn, 0>;
1715 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
1716 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn.i", int_arm_neon_vrsubhn, 0>;
1718 // Vector Comparisons.
1720 // VCEQ : Vector Compare Equal
1721 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1722 IIC_VBINi4Q, "vceq.i", NEONvceq, 1>;
1723 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq.f32", v2i32, v2f32, NEONvceq, 1>;
1724 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq.f32", v4i32, v4f32, NEONvceq, 1>;
1725 // VCGE : Vector Compare Greater Than or Equal
1726 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1727 IIC_VBINi4Q, "vcge.s", NEONvcge, 0>;
1728 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1729 IIC_VBINi4Q, "vcge.u", NEONvcgeu, 0>;
1730 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge.f32", v2i32, v2f32, NEONvcge, 0>;
1731 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge.f32", v4i32, v4f32, NEONvcge, 0>;
1732 // VCGT : Vector Compare Greater Than
1733 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1734 IIC_VBINi4Q, "vcgt.s", NEONvcgt, 0>;
1735 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1736 IIC_VBINi4Q, "vcgt.u", NEONvcgtu, 0>;
1737 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt.f32", v2i32, v2f32, NEONvcgt, 0>;
1738 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt.f32", v4i32, v4f32, NEONvcgt, 0>;
1739 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
1740 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, IIC_VBIND, "vacge.f32", v2i32, v2f32,
1741 int_arm_neon_vacged, 0>;
1742 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, IIC_VBINQ, "vacge.f32", v4i32, v4f32,
1743 int_arm_neon_vacgeq, 0>;
1744 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
1745 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, IIC_VBIND, "vacgt.f32", v2i32, v2f32,
1746 int_arm_neon_vacgtd, 0>;
1747 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, IIC_VBINQ, "vacgt.f32", v4i32, v4f32,
1748 int_arm_neon_vacgtq, 0>;
1749 // VTST : Vector Test Bits
1750 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1751 IIC_VBINi4Q, "vtst.i", NEONvtst, 1>;
1753 // Vector Bitwise Operations.
1755 // VAND : Vector Bitwise AND
1756 def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand", v2i32, v2i32, and, 1>;
1757 def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand", v4i32, v4i32, and, 1>;
1759 // VEOR : Vector Bitwise Exclusive OR
1760 def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor", v2i32, v2i32, xor, 1>;
1761 def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor", v4i32, v4i32, xor, 1>;
1763 // VORR : Vector Bitwise OR
1764 def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr", v2i32, v2i32, or, 1>;
1765 def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr", v4i32, v4i32, or, 1>;
1767 // VBIC : Vector Bitwise Bit Clear (AND NOT)
1768 def VBICd : N3V<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1769 (ins DPR:$src1, DPR:$src2), IIC_VBINiD,
1770 "vbic\t$dst, $src1, $src2", "",
1771 [(set DPR:$dst, (v2i32 (and DPR:$src1,
1772 (vnot_conv DPR:$src2))))]>;
1773 def VBICq : N3V<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1774 (ins QPR:$src1, QPR:$src2), IIC_VBINiQ,
1775 "vbic\t$dst, $src1, $src2", "",
1776 [(set QPR:$dst, (v4i32 (and QPR:$src1,
1777 (vnot_conv QPR:$src2))))]>;
1779 // VORN : Vector Bitwise OR NOT
1780 def VORNd : N3V<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
1781 (ins DPR:$src1, DPR:$src2), IIC_VBINiD,
1782 "vorn\t$dst, $src1, $src2", "",
1783 [(set DPR:$dst, (v2i32 (or DPR:$src1,
1784 (vnot_conv DPR:$src2))))]>;
1785 def VORNq : N3V<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
1786 (ins QPR:$src1, QPR:$src2), IIC_VBINiQ,
1787 "vorn\t$dst, $src1, $src2", "",
1788 [(set QPR:$dst, (v4i32 (or QPR:$src1,
1789 (vnot_conv QPR:$src2))))]>;
1791 // VMVN : Vector Bitwise NOT
1792 def VMVNd : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
1793 (outs DPR:$dst), (ins DPR:$src), IIC_VSHLiD,
1794 "vmvn\t$dst, $src", "",
1795 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>;
1796 def VMVNq : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
1797 (outs QPR:$dst), (ins QPR:$src), IIC_VSHLiD,
1798 "vmvn\t$dst, $src", "",
1799 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>;
1800 def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>;
1801 def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>;
1803 // VBSL : Vector Bitwise Select
1804 def VBSLd : N3V<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1805 (ins DPR:$src1, DPR:$src2, DPR:$src3), IIC_VCNTiD,
1806 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1808 (v2i32 (or (and DPR:$src2, DPR:$src1),
1809 (and DPR:$src3, (vnot_conv DPR:$src1)))))]>;
1810 def VBSLq : N3V<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1811 (ins QPR:$src1, QPR:$src2, QPR:$src3), IIC_VCNTiQ,
1812 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1814 (v4i32 (or (and QPR:$src2, QPR:$src1),
1815 (and QPR:$src3, (vnot_conv QPR:$src1)))))]>;
1817 // VBIF : Vector Bitwise Insert if False
1818 // like VBSL but with: "vbif\t$dst, $src3, $src1", "$src2 = $dst",
1819 // VBIT : Vector Bitwise Insert if True
1820 // like VBSL but with: "vbit\t$dst, $src2, $src1", "$src3 = $dst",
1821 // These are not yet implemented. The TwoAddress pass will not go looking
1822 // for equivalent operations with different register constraints; it just
1825 // Vector Absolute Differences.
1827 // VABD : Vector Absolute Difference
1828 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1829 IIC_VBINi4Q, "vabd.s", int_arm_neon_vabds, 0>;
1830 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1831 IIC_VBINi4Q, "vabd.u", int_arm_neon_vabdu, 0>;
1832 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, IIC_VBIND, "vabd.f32", v2f32, v2f32,
1833 int_arm_neon_vabds, 0>;
1834 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vabd.f32", v4f32, v4f32,
1835 int_arm_neon_vabds, 0>;
1837 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
1838 defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, IIC_VBINi4Q, "vabdl.s", int_arm_neon_vabdls, 0>;
1839 defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, IIC_VBINi4Q, "vabdl.u", int_arm_neon_vabdlu, 0>;
1841 // VABA : Vector Absolute Difference and Accumulate
1842 defm VABAs : N3VInt3_QHS<0,1,0b0101,0, "vaba.s", int_arm_neon_vabas>;
1843 defm VABAu : N3VInt3_QHS<1,1,0b0101,0, "vaba.u", int_arm_neon_vabau>;
1845 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
1846 defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal.s", int_arm_neon_vabals>;
1847 defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal.u", int_arm_neon_vabalu>;
1849 // Vector Maximum and Minimum.
1851 // VMAX : Vector Maximum
1852 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1853 IIC_VBINi4Q, "vmax.s", int_arm_neon_vmaxs, 1>;
1854 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1855 IIC_VBINi4Q, "vmax.u", int_arm_neon_vmaxu, 1>;
1856 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, IIC_VBIND, "vmax.f32", v2f32, v2f32,
1857 int_arm_neon_vmaxs, 1>;
1858 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, IIC_VBINQ, "vmax.f32", v4f32, v4f32,
1859 int_arm_neon_vmaxs, 1>;
1861 // VMIN : Vector Minimum
1862 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1863 IIC_VBINi4Q, "vmin.s", int_arm_neon_vmins, 1>;
1864 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1865 IIC_VBINi4Q, "vmin.u", int_arm_neon_vminu, 1>;
1866 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, IIC_VBIND, "vmin.f32", v2f32, v2f32,
1867 int_arm_neon_vmins, 1>;
1868 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, IIC_VBINQ, "vmin.f32", v4f32, v4f32,
1869 int_arm_neon_vmins, 1>;
1871 // Vector Pairwise Operations.
1873 // VPADD : Vector Pairwise Add
1874 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, IIC_VBINiD, "vpadd.i8", v8i8, v8i8,
1875 int_arm_neon_vpadd, 0>;
1876 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, IIC_VBINiD, "vpadd.i16", v4i16, v4i16,
1877 int_arm_neon_vpadd, 0>;
1878 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, IIC_VBINiD, "vpadd.i32", v2i32, v2i32,
1879 int_arm_neon_vpadd, 0>;
1880 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, IIC_VBIND, "vpadd.f32", v2f32, v2f32,
1881 int_arm_neon_vpadd, 0>;
1883 // VPADDL : Vector Pairwise Add Long
1884 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl.s",
1885 int_arm_neon_vpaddls>;
1886 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl.u",
1887 int_arm_neon_vpaddlu>;
1889 // VPADAL : Vector Pairwise Add and Accumulate Long
1890 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpadal.s",
1891 int_arm_neon_vpadals>;
1892 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpadal.u",
1893 int_arm_neon_vpadalu>;
1895 // VPMAX : Vector Pairwise Maximum
1896 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax.s8", v8i8, v8i8,
1897 int_arm_neon_vpmaxs, 0>;
1898 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax.s16", v4i16, v4i16,
1899 int_arm_neon_vpmaxs, 0>;
1900 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax.s32", v2i32, v2i32,
1901 int_arm_neon_vpmaxs, 0>;
1902 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax.u8", v8i8, v8i8,
1903 int_arm_neon_vpmaxu, 0>;
1904 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax.u16", v4i16, v4i16,
1905 int_arm_neon_vpmaxu, 0>;
1906 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax.u32", v2i32, v2i32,
1907 int_arm_neon_vpmaxu, 0>;
1908 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, IIC_VBINi4D, "vpmax.f32", v2f32, v2f32,
1909 int_arm_neon_vpmaxs, 0>;
1911 // VPMIN : Vector Pairwise Minimum
1912 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin.s8", v8i8, v8i8,
1913 int_arm_neon_vpmins, 0>;
1914 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin.s16", v4i16, v4i16,
1915 int_arm_neon_vpmins, 0>;
1916 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin.s32", v2i32, v2i32,
1917 int_arm_neon_vpmins, 0>;
1918 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin.u8", v8i8, v8i8,
1919 int_arm_neon_vpminu, 0>;
1920 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin.u16", v4i16, v4i16,
1921 int_arm_neon_vpminu, 0>;
1922 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin.u32", v2i32, v2i32,
1923 int_arm_neon_vpminu, 0>;
1924 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, IIC_VBINi4D, "vpmin.f32", v2f32, v2f32,
1925 int_arm_neon_vpmins, 0>;
1927 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
1929 // VRECPE : Vector Reciprocal Estimate
1930 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
1931 IIC_VUNAD, "vrecpe.u32",
1932 v2i32, v2i32, int_arm_neon_vrecpe>;
1933 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
1934 IIC_VUNAQ, "vrecpe.u32",
1935 v4i32, v4i32, int_arm_neon_vrecpe>;
1936 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
1937 IIC_VUNAD, "vrecpe.f32",
1938 v2f32, v2f32, int_arm_neon_vrecpe>;
1939 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
1940 IIC_VUNAQ, "vrecpe.f32",
1941 v4f32, v4f32, int_arm_neon_vrecpe>;
1943 // VRECPS : Vector Reciprocal Step
1944 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, IIC_VRECSD, "vrecps.f32", v2f32, v2f32,
1945 int_arm_neon_vrecps, 1>;
1946 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, IIC_VRECSQ, "vrecps.f32", v4f32, v4f32,
1947 int_arm_neon_vrecps, 1>;
1949 // VRSQRTE : Vector Reciprocal Square Root Estimate
1950 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
1951 IIC_VUNAD, "vrsqrte.u32",
1952 v2i32, v2i32, int_arm_neon_vrsqrte>;
1953 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
1954 IIC_VUNAQ, "vrsqrte.u32",
1955 v4i32, v4i32, int_arm_neon_vrsqrte>;
1956 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
1957 IIC_VUNAD, "vrsqrte.f32",
1958 v2f32, v2f32, int_arm_neon_vrsqrte>;
1959 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
1960 IIC_VUNAQ, "vrsqrte.f32",
1961 v4f32, v4f32, int_arm_neon_vrsqrte>;
1963 // VRSQRTS : Vector Reciprocal Square Root Step
1964 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, IIC_VRECSD, "vrsqrts.f32", v2f32, v2f32,
1965 int_arm_neon_vrsqrts, 1>;
1966 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, IIC_VRECSQ, "vrsqrts.f32", v4f32, v4f32,
1967 int_arm_neon_vrsqrts, 1>;
1971 // VSHL : Vector Shift
1972 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
1973 IIC_VSHLiQ, "vshl.s", int_arm_neon_vshifts, 0>;
1974 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
1975 IIC_VSHLiQ, "vshl.u", int_arm_neon_vshiftu, 0>;
1976 // VSHL : Vector Shift Left (Immediate)
1977 defm VSHLi : N2VSh_QHSD<0, 1, 0b0111, 1, IIC_VSHLiD, "vshl.i", NEONvshl>;
1978 // VSHR : Vector Shift Right (Immediate)
1979 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr.s", NEONvshrs>;
1980 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr.u", NEONvshru>;
1982 // VSHLL : Vector Shift Left Long
1983 def VSHLLs8 : N2VLSh<0, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.s8",
1984 v8i16, v8i8, NEONvshlls>;
1985 def VSHLLs16 : N2VLSh<0, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.s16",
1986 v4i32, v4i16, NEONvshlls>;
1987 def VSHLLs32 : N2VLSh<0, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.s32",
1988 v2i64, v2i32, NEONvshlls>;
1989 def VSHLLu8 : N2VLSh<1, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.u8",
1990 v8i16, v8i8, NEONvshllu>;
1991 def VSHLLu16 : N2VLSh<1, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.u16",
1992 v4i32, v4i16, NEONvshllu>;
1993 def VSHLLu32 : N2VLSh<1, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.u32",
1994 v2i64, v2i32, NEONvshllu>;
1996 // VSHLL : Vector Shift Left Long (with maximum shift count)
1997 def VSHLLi8 : N2VLSh<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll.i8",
1998 v8i16, v8i8, NEONvshlli>;
1999 def VSHLLi16 : N2VLSh<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll.i16",
2000 v4i32, v4i16, NEONvshlli>;
2001 def VSHLLi32 : N2VLSh<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll.i32",
2002 v2i64, v2i32, NEONvshlli>;
2004 // VSHRN : Vector Shift Right and Narrow
2005 def VSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 0, 1,
2006 IIC_VSHLiD, "vshrn.i16", v8i8, v8i16, NEONvshrn>;
2007 def VSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 0, 1,
2008 IIC_VSHLiD, "vshrn.i32", v4i16, v4i32, NEONvshrn>;
2009 def VSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 0, 1,
2010 IIC_VSHLiD, "vshrn.i64", v2i32, v2i64, NEONvshrn>;
2012 // VRSHL : Vector Rounding Shift
2013 defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2014 IIC_VSHLi4Q, "vrshl.s", int_arm_neon_vrshifts, 0>;
2015 defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2016 IIC_VSHLi4Q, "vrshl.u", int_arm_neon_vrshiftu, 0>;
2017 // VRSHR : Vector Rounding Shift Right
2018 defm VRSHRs : N2VSh_QHSD<0, 1, 0b0010, 1, IIC_VSHLi4D, "vrshr.s", NEONvrshrs>;
2019 defm VRSHRu : N2VSh_QHSD<1, 1, 0b0010, 1, IIC_VSHLi4D, "vrshr.u", NEONvrshru>;
2021 // VRSHRN : Vector Rounding Shift Right and Narrow
2022 def VRSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 1, 1,
2023 IIC_VSHLi4D, "vrshrn.i16", v8i8, v8i16, NEONvrshrn>;
2024 def VRSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 1, 1,
2025 IIC_VSHLi4D, "vrshrn.i32", v4i16, v4i32, NEONvrshrn>;
2026 def VRSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 1, 1,
2027 IIC_VSHLi4D, "vrshrn.i64", v2i32, v2i64, NEONvrshrn>;
2029 // VQSHL : Vector Saturating Shift
2030 defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2031 IIC_VSHLi4Q, "vqshl.s", int_arm_neon_vqshifts, 0>;
2032 defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2033 IIC_VSHLi4Q, "vqshl.u", int_arm_neon_vqshiftu, 0>;
2034 // VQSHL : Vector Saturating Shift Left (Immediate)
2035 defm VQSHLsi : N2VSh_QHSD<0, 1, 0b0111, 1, IIC_VSHLi4D, "vqshl.s", NEONvqshls>;
2036 defm VQSHLui : N2VSh_QHSD<1, 1, 0b0111, 1, IIC_VSHLi4D, "vqshl.u", NEONvqshlu>;
2037 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
2038 defm VQSHLsu : N2VSh_QHSD<1, 1, 0b0110, 1, IIC_VSHLi4D, "vqshlu.s", NEONvqshlsu>;
2040 // VQSHRN : Vector Saturating Shift Right and Narrow
2041 def VQSHRNs16 : N2VNSh<0, 1, 0b001000, 0b1001, 0, 0, 1,
2042 IIC_VSHLi4D, "vqshrn.s16", v8i8, v8i16, NEONvqshrns>;
2043 def VQSHRNs32 : N2VNSh<0, 1, 0b010000, 0b1001, 0, 0, 1,
2044 IIC_VSHLi4D, "vqshrn.s32", v4i16, v4i32, NEONvqshrns>;
2045 def VQSHRNs64 : N2VNSh<0, 1, 0b100000, 0b1001, 0, 0, 1,
2046 IIC_VSHLi4D, "vqshrn.s64", v2i32, v2i64, NEONvqshrns>;
2047 def VQSHRNu16 : N2VNSh<1, 1, 0b001000, 0b1001, 0, 0, 1,
2048 IIC_VSHLi4D, "vqshrn.u16", v8i8, v8i16, NEONvqshrnu>;
2049 def VQSHRNu32 : N2VNSh<1, 1, 0b010000, 0b1001, 0, 0, 1,
2050 IIC_VSHLi4D, "vqshrn.u32", v4i16, v4i32, NEONvqshrnu>;
2051 def VQSHRNu64 : N2VNSh<1, 1, 0b100000, 0b1001, 0, 0, 1,
2052 IIC_VSHLi4D, "vqshrn.u64", v2i32, v2i64, NEONvqshrnu>;
2054 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
2055 def VQSHRUN16 : N2VNSh<1, 1, 0b001000, 0b1000, 0, 0, 1,
2056 IIC_VSHLi4D, "vqshrun.s16", v8i8, v8i16, NEONvqshrnsu>;
2057 def VQSHRUN32 : N2VNSh<1, 1, 0b010000, 0b1000, 0, 0, 1,
2058 IIC_VSHLi4D, "vqshrun.s32", v4i16, v4i32, NEONvqshrnsu>;
2059 def VQSHRUN64 : N2VNSh<1, 1, 0b100000, 0b1000, 0, 0, 1,
2060 IIC_VSHLi4D, "vqshrun.s64", v2i32, v2i64, NEONvqshrnsu>;
2062 // VQRSHL : Vector Saturating Rounding Shift
2063 defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2064 IIC_VSHLi4Q, "vqrshl.s", int_arm_neon_vqrshifts, 0>;
2065 defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2066 IIC_VSHLi4Q, "vqrshl.u", int_arm_neon_vqrshiftu, 0>;
2068 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
2069 def VQRSHRNs16: N2VNSh<0, 1, 0b001000, 0b1001, 0, 1, 1,
2070 IIC_VSHLi4D, "vqrshrn.s16", v8i8, v8i16, NEONvqrshrns>;
2071 def VQRSHRNs32: N2VNSh<0, 1, 0b010000, 0b1001, 0, 1, 1,
2072 IIC_VSHLi4D, "vqrshrn.s32", v4i16, v4i32, NEONvqrshrns>;
2073 def VQRSHRNs64: N2VNSh<0, 1, 0b100000, 0b1001, 0, 1, 1,
2074 IIC_VSHLi4D, "vqrshrn.s64", v2i32, v2i64, NEONvqrshrns>;
2075 def VQRSHRNu16: N2VNSh<1, 1, 0b001000, 0b1001, 0, 1, 1,
2076 IIC_VSHLi4D, "vqrshrn.u16", v8i8, v8i16, NEONvqrshrnu>;
2077 def VQRSHRNu32: N2VNSh<1, 1, 0b010000, 0b1001, 0, 1, 1,
2078 IIC_VSHLi4D, "vqrshrn.u32", v4i16, v4i32, NEONvqrshrnu>;
2079 def VQRSHRNu64: N2VNSh<1, 1, 0b100000, 0b1001, 0, 1, 1,
2080 IIC_VSHLi4D, "vqrshrn.u64", v2i32, v2i64, NEONvqrshrnu>;
2082 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
2083 def VQRSHRUN16: N2VNSh<1, 1, 0b001000, 0b1000, 0, 1, 1,
2084 IIC_VSHLi4D, "vqrshrun.s16", v8i8, v8i16, NEONvqrshrnsu>;
2085 def VQRSHRUN32: N2VNSh<1, 1, 0b010000, 0b1000, 0, 1, 1,
2086 IIC_VSHLi4D, "vqrshrun.s32", v4i16, v4i32, NEONvqrshrnsu>;
2087 def VQRSHRUN64: N2VNSh<1, 1, 0b100000, 0b1000, 0, 1, 1,
2088 IIC_VSHLi4D, "vqrshrun.s64", v2i32, v2i64, NEONvqrshrnsu>;
2090 // VSRA : Vector Shift Right and Accumulate
2091 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra.s", NEONvshrs>;
2092 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra.u", NEONvshru>;
2093 // VRSRA : Vector Rounding Shift Right and Accumulate
2094 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra.s", NEONvrshrs>;
2095 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra.u", NEONvrshru>;
2097 // VSLI : Vector Shift Left and Insert
2098 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli.", NEONvsli>;
2099 // VSRI : Vector Shift Right and Insert
2100 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri.", NEONvsri>;
2102 // Vector Absolute and Saturating Absolute.
2104 // VABS : Vector Absolute Value
2105 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
2106 IIC_VUNAiD, IIC_VUNAiQ, "vabs.s",
2108 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2109 IIC_VUNAD, "vabs.f32",
2110 v2f32, v2f32, int_arm_neon_vabs>;
2111 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2112 IIC_VUNAQ, "vabs.f32",
2113 v4f32, v4f32, int_arm_neon_vabs>;
2115 // VQABS : Vector Saturating Absolute Value
2116 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
2117 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs.s",
2118 int_arm_neon_vqabs>;
2122 def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
2123 def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>;
2125 class VNEGD<bits<2> size, string OpcodeStr, ValueType Ty>
2126 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
2127 IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "",
2128 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>;
2129 class VNEGQ<bits<2> size, string OpcodeStr, ValueType Ty>
2130 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
2131 IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "",
2132 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>;
2134 // VNEG : Vector Negate
2135 def VNEGs8d : VNEGD<0b00, "vneg.s8", v8i8>;
2136 def VNEGs16d : VNEGD<0b01, "vneg.s16", v4i16>;
2137 def VNEGs32d : VNEGD<0b10, "vneg.s32", v2i32>;
2138 def VNEGs8q : VNEGQ<0b00, "vneg.s8", v16i8>;
2139 def VNEGs16q : VNEGQ<0b01, "vneg.s16", v8i16>;
2140 def VNEGs32q : VNEGQ<0b10, "vneg.s32", v4i32>;
2142 // VNEG : Vector Negate (floating-point)
2143 def VNEGf32d : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
2144 (outs DPR:$dst), (ins DPR:$src), IIC_VUNAD,
2145 "vneg.f32\t$dst, $src", "",
2146 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
2147 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
2148 (outs QPR:$dst), (ins QPR:$src), IIC_VUNAQ,
2149 "vneg.f32\t$dst, $src", "",
2150 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
2152 def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
2153 def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
2154 def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>;
2155 def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>;
2156 def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>;
2157 def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>;
2159 // VQNEG : Vector Saturating Negate
2160 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
2161 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg.s",
2162 int_arm_neon_vqneg>;
2164 // Vector Bit Counting Operations.
2166 // VCLS : Vector Count Leading Sign Bits
2167 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
2168 IIC_VCNTiD, IIC_VCNTiQ, "vcls.s",
2170 // VCLZ : Vector Count Leading Zeros
2171 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
2172 IIC_VCNTiD, IIC_VCNTiQ, "vclz.i",
2174 // VCNT : Vector Count One Bits
2175 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2176 IIC_VCNTiD, "vcnt.8",
2177 v8i8, v8i8, int_arm_neon_vcnt>;
2178 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2179 IIC_VCNTiQ, "vcnt.8",
2180 v16i8, v16i8, int_arm_neon_vcnt>;
2182 // Vector Move Operations.
2184 // VMOV : Vector Move (Register)
2186 def VMOVD : N3V<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
2187 IIC_VMOVD, "vmov\t$dst, $src", "", []>;
2188 def VMOVQ : N3V<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
2189 IIC_VMOVD, "vmov\t$dst, $src", "", []>;
2191 // VMOV : Vector Move (Immediate)
2193 // VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
2194 def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
2195 return ARM::getVMOVImm(N, 1, *CurDAG);
2197 def vmovImm8 : PatLeaf<(build_vector), [{
2198 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
2201 // VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
2202 def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
2203 return ARM::getVMOVImm(N, 2, *CurDAG);
2205 def vmovImm16 : PatLeaf<(build_vector), [{
2206 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
2207 }], VMOV_get_imm16>;
2209 // VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
2210 def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
2211 return ARM::getVMOVImm(N, 4, *CurDAG);
2213 def vmovImm32 : PatLeaf<(build_vector), [{
2214 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
2215 }], VMOV_get_imm32>;
2217 // VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
2218 def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
2219 return ARM::getVMOVImm(N, 8, *CurDAG);
2221 def vmovImm64 : PatLeaf<(build_vector), [{
2222 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
2223 }], VMOV_get_imm64>;
2225 // Note: Some of the cmode bits in the following VMOV instructions need to
2226 // be encoded based on the immed values.
2228 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
2229 (ins i8imm:$SIMM), IIC_VMOVImm,
2230 "vmov.i8\t$dst, $SIMM", "",
2231 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
2232 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
2233 (ins i8imm:$SIMM), IIC_VMOVImm,
2234 "vmov.i8\t$dst, $SIMM", "",
2235 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
2237 def VMOVv4i16 : N1ModImm<1, 0b000, 0b1000, 0, 0, 0, 1, (outs DPR:$dst),
2238 (ins i16imm:$SIMM), IIC_VMOVImm,
2239 "vmov.i16\t$dst, $SIMM", "",
2240 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
2241 def VMOVv8i16 : N1ModImm<1, 0b000, 0b1000, 0, 1, 0, 1, (outs QPR:$dst),
2242 (ins i16imm:$SIMM), IIC_VMOVImm,
2243 "vmov.i16\t$dst, $SIMM", "",
2244 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
2246 def VMOVv2i32 : N1ModImm<1, 0b000, 0b0000, 0, 0, 0, 1, (outs DPR:$dst),
2247 (ins i32imm:$SIMM), IIC_VMOVImm,
2248 "vmov.i32\t$dst, $SIMM", "",
2249 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
2250 def VMOVv4i32 : N1ModImm<1, 0b000, 0b0000, 0, 1, 0, 1, (outs QPR:$dst),
2251 (ins i32imm:$SIMM), IIC_VMOVImm,
2252 "vmov.i32\t$dst, $SIMM", "",
2253 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
2255 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
2256 (ins i64imm:$SIMM), IIC_VMOVImm,
2257 "vmov.i64\t$dst, $SIMM", "",
2258 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
2259 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
2260 (ins i64imm:$SIMM), IIC_VMOVImm,
2261 "vmov.i64\t$dst, $SIMM", "",
2262 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
2264 // VMOV : Vector Get Lane (move scalar to ARM core register)
2266 def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00,
2267 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2268 IIC_VMOVSI, "vmov", ".s8\t$dst, $src[$lane]",
2269 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
2271 def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01,
2272 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2273 IIC_VMOVSI, "vmov", ".s16\t$dst, $src[$lane]",
2274 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
2276 def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00,
2277 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2278 IIC_VMOVSI, "vmov", ".u8\t$dst, $src[$lane]",
2279 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
2281 def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01,
2282 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2283 IIC_VMOVSI, "vmov", ".u16\t$dst, $src[$lane]",
2284 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
2286 def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00,
2287 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2288 IIC_VMOVSI, "vmov", ".32\t$dst, $src[$lane]",
2289 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
2291 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
2292 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
2293 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2294 (DSubReg_i8_reg imm:$lane))),
2295 (SubReg_i8_lane imm:$lane))>;
2296 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
2297 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2298 (DSubReg_i16_reg imm:$lane))),
2299 (SubReg_i16_lane imm:$lane))>;
2300 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
2301 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2302 (DSubReg_i8_reg imm:$lane))),
2303 (SubReg_i8_lane imm:$lane))>;
2304 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
2305 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2306 (DSubReg_i16_reg imm:$lane))),
2307 (SubReg_i16_lane imm:$lane))>;
2308 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
2309 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
2310 (DSubReg_i32_reg imm:$lane))),
2311 (SubReg_i32_lane imm:$lane))>;
2312 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
2313 (EXTRACT_SUBREG (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2),
2314 (SSubReg_f32_reg imm:$src2))>;
2315 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
2316 (EXTRACT_SUBREG (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2),
2317 (SSubReg_f32_reg imm:$src2))>;
2318 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
2319 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2320 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
2321 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2324 // VMOV : Vector Set Lane (move ARM core register to scalar)
2326 let Constraints = "$src1 = $dst" in {
2327 def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst),
2328 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2329 IIC_VMOVISL, "vmov", ".8\t$dst[$lane], $src2",
2330 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
2331 GPR:$src2, imm:$lane))]>;
2332 def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst),
2333 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2334 IIC_VMOVISL, "vmov", ".16\t$dst[$lane], $src2",
2335 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
2336 GPR:$src2, imm:$lane))]>;
2337 def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst),
2338 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2339 IIC_VMOVISL, "vmov", ".32\t$dst[$lane], $src2",
2340 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
2341 GPR:$src2, imm:$lane))]>;
2343 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
2344 (v16i8 (INSERT_SUBREG QPR:$src1,
2345 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
2346 (DSubReg_i8_reg imm:$lane))),
2347 GPR:$src2, (SubReg_i8_lane imm:$lane)),
2348 (DSubReg_i8_reg imm:$lane)))>;
2349 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
2350 (v8i16 (INSERT_SUBREG QPR:$src1,
2351 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
2352 (DSubReg_i16_reg imm:$lane))),
2353 GPR:$src2, (SubReg_i16_lane imm:$lane)),
2354 (DSubReg_i16_reg imm:$lane)))>;
2355 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
2356 (v4i32 (INSERT_SUBREG QPR:$src1,
2357 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
2358 (DSubReg_i32_reg imm:$lane))),
2359 GPR:$src2, (SubReg_i32_lane imm:$lane)),
2360 (DSubReg_i32_reg imm:$lane)))>;
2362 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
2363 (INSERT_SUBREG (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2),
2364 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
2365 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
2366 (INSERT_SUBREG (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2),
2367 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
2369 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
2370 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
2371 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
2372 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
2374 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
2375 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
2376 def : Pat<(v2f64 (scalar_to_vector DPR:$src)),
2377 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, arm_dsubreg_0)>;
2378 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
2379 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
2381 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
2382 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2383 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
2384 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2385 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
2386 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2388 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
2389 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
2390 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2392 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
2393 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
2394 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2396 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
2397 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
2398 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2401 // VDUP : Vector Duplicate (from ARM core register to all elements)
2403 class VDUPD<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
2404 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
2405 IIC_VMOVIS, "vdup", !strconcat(asmSize, "\t$dst, $src"),
2406 [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
2407 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
2408 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
2409 IIC_VMOVIS, "vdup", !strconcat(asmSize, "\t$dst, $src"),
2410 [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
2412 def VDUP8d : VDUPD<0b11101100, 0b00, ".8", v8i8>;
2413 def VDUP16d : VDUPD<0b11101000, 0b01, ".16", v4i16>;
2414 def VDUP32d : VDUPD<0b11101000, 0b00, ".32", v2i32>;
2415 def VDUP8q : VDUPQ<0b11101110, 0b00, ".8", v16i8>;
2416 def VDUP16q : VDUPQ<0b11101010, 0b01, ".16", v8i16>;
2417 def VDUP32q : VDUPQ<0b11101010, 0b00, ".32", v4i32>;
2419 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
2420 IIC_VMOVIS, "vdup", ".32\t$dst, $src",
2421 [(set DPR:$dst, (v2f32 (NEONvdup
2422 (f32 (bitconvert GPR:$src)))))]>;
2423 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
2424 IIC_VMOVIS, "vdup", ".32\t$dst, $src",
2425 [(set QPR:$dst, (v4f32 (NEONvdup
2426 (f32 (bitconvert GPR:$src)))))]>;
2428 // VDUP : Vector Duplicate Lane (from scalar to all elements)
2430 class VDUPLND<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty>
2431 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
2432 (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
2433 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
2434 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
2436 class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr,
2437 ValueType ResTy, ValueType OpTy>
2438 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
2439 (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
2440 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
2441 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src), imm:$lane)))]>;
2443 def VDUPLN8d : VDUPLND<0b00, 0b01, "vdup.8", v8i8>;
2444 def VDUPLN16d : VDUPLND<0b00, 0b10, "vdup.16", v4i16>;
2445 def VDUPLN32d : VDUPLND<0b01, 0b00, "vdup.32", v2i32>;
2446 def VDUPLNfd : VDUPLND<0b01, 0b00, "vdup.32", v2f32>;
2447 def VDUPLN8q : VDUPLNQ<0b00, 0b01, "vdup.8", v16i8, v8i8>;
2448 def VDUPLN16q : VDUPLNQ<0b00, 0b10, "vdup.16", v8i16, v4i16>;
2449 def VDUPLN32q : VDUPLNQ<0b01, 0b00, "vdup.32", v4i32, v2i32>;
2450 def VDUPLNfq : VDUPLNQ<0b01, 0b00, "vdup.32", v4f32, v2f32>;
2452 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
2453 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
2454 (DSubReg_i8_reg imm:$lane))),
2455 (SubReg_i8_lane imm:$lane)))>;
2456 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
2457 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
2458 (DSubReg_i16_reg imm:$lane))),
2459 (SubReg_i16_lane imm:$lane)))>;
2460 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
2461 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
2462 (DSubReg_i32_reg imm:$lane))),
2463 (SubReg_i32_lane imm:$lane)))>;
2464 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
2465 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
2466 (DSubReg_i32_reg imm:$lane))),
2467 (SubReg_i32_lane imm:$lane)))>;
2469 def VDUPfdf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 0, 0,
2470 (outs DPR:$dst), (ins SPR:$src),
2471 IIC_VMOVD, "vdup.32\t$dst, ${src:lane}", "",
2472 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
2474 def VDUPfqf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 1, 0,
2475 (outs QPR:$dst), (ins SPR:$src),
2476 IIC_VMOVD, "vdup.32\t$dst, ${src:lane}", "",
2477 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
2479 def : Pat<(v2i64 (NEONvduplane (v2i64 QPR:$src), imm:$lane)),
2480 (INSERT_SUBREG QPR:$src,
2481 (i64 (EXTRACT_SUBREG QPR:$src, (DSubReg_f64_reg imm:$lane))),
2482 (DSubReg_f64_other_reg imm:$lane))>;
2483 def : Pat<(v2f64 (NEONvduplane (v2f64 QPR:$src), imm:$lane)),
2484 (INSERT_SUBREG QPR:$src,
2485 (f64 (EXTRACT_SUBREG QPR:$src, (DSubReg_f64_reg imm:$lane))),
2486 (DSubReg_f64_other_reg imm:$lane))>;
2488 // VMOVN : Vector Narrowing Move
2489 defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVD, "vmovn.i",
2490 int_arm_neon_vmovn>;
2491 // VQMOVN : Vector Saturating Narrowing Move
2492 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD, "vqmovn.s",
2493 int_arm_neon_vqmovns>;
2494 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD, "vqmovn.u",
2495 int_arm_neon_vqmovnu>;
2496 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD, "vqmovun.s",
2497 int_arm_neon_vqmovnsu>;
2498 // VMOVL : Vector Lengthening Move
2499 defm VMOVLs : N2VLInt_QHS<0,1,0b1010,0,0,1, "vmovl.s", int_arm_neon_vmovls>;
2500 defm VMOVLu : N2VLInt_QHS<1,1,0b1010,0,0,1, "vmovl.u", int_arm_neon_vmovlu>;
2502 // Vector Conversions.
2504 // VCVT : Vector Convert Between Floating-Point and Integers
2505 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
2506 v2i32, v2f32, fp_to_sint>;
2507 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
2508 v2i32, v2f32, fp_to_uint>;
2509 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
2510 v2f32, v2i32, sint_to_fp>;
2511 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
2512 v2f32, v2i32, uint_to_fp>;
2514 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
2515 v4i32, v4f32, fp_to_sint>;
2516 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
2517 v4i32, v4f32, fp_to_uint>;
2518 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
2519 v4f32, v4i32, sint_to_fp>;
2520 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
2521 v4f32, v4i32, uint_to_fp>;
2523 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
2524 // Note: Some of the opcode bits in the following VCVT instructions need to
2525 // be encoded based on the immed values.
2526 def VCVTf2xsd : N2VCvtD<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
2527 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
2528 def VCVTf2xud : N2VCvtD<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
2529 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
2530 def VCVTxs2fd : N2VCvtD<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
2531 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
2532 def VCVTxu2fd : N2VCvtD<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
2533 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
2535 def VCVTf2xsq : N2VCvtQ<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
2536 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
2537 def VCVTf2xuq : N2VCvtQ<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
2538 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
2539 def VCVTxs2fq : N2VCvtQ<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
2540 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
2541 def VCVTxu2fq : N2VCvtQ<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
2542 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
2546 // VREV64 : Vector Reverse elements within 64-bit doublewords
2548 class VREV64D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2549 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
2550 (ins DPR:$src), IIC_VMOVD,
2551 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2552 [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
2553 class VREV64Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2554 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
2555 (ins QPR:$src), IIC_VMOVD,
2556 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2557 [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
2559 def VREV64d8 : VREV64D<0b00, "vrev64.8", v8i8>;
2560 def VREV64d16 : VREV64D<0b01, "vrev64.16", v4i16>;
2561 def VREV64d32 : VREV64D<0b10, "vrev64.32", v2i32>;
2562 def VREV64df : VREV64D<0b10, "vrev64.32", v2f32>;
2564 def VREV64q8 : VREV64Q<0b00, "vrev64.8", v16i8>;
2565 def VREV64q16 : VREV64Q<0b01, "vrev64.16", v8i16>;
2566 def VREV64q32 : VREV64Q<0b10, "vrev64.32", v4i32>;
2567 def VREV64qf : VREV64Q<0b10, "vrev64.32", v4f32>;
2569 // VREV32 : Vector Reverse elements within 32-bit words
2571 class VREV32D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2572 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
2573 (ins DPR:$src), IIC_VMOVD,
2574 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2575 [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
2576 class VREV32Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2577 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
2578 (ins QPR:$src), IIC_VMOVD,
2579 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2580 [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
2582 def VREV32d8 : VREV32D<0b00, "vrev32.8", v8i8>;
2583 def VREV32d16 : VREV32D<0b01, "vrev32.16", v4i16>;
2585 def VREV32q8 : VREV32Q<0b00, "vrev32.8", v16i8>;
2586 def VREV32q16 : VREV32Q<0b01, "vrev32.16", v8i16>;
2588 // VREV16 : Vector Reverse elements within 16-bit halfwords
2590 class VREV16D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2591 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
2592 (ins DPR:$src), IIC_VMOVD,
2593 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2594 [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
2595 class VREV16Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2596 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
2597 (ins QPR:$src), IIC_VMOVD,
2598 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2599 [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
2601 def VREV16d8 : VREV16D<0b00, "vrev16.8", v8i8>;
2602 def VREV16q8 : VREV16Q<0b00, "vrev16.8", v16i8>;
2604 // Other Vector Shuffles.
2606 // VEXT : Vector Extract
2608 class VEXTd<string OpcodeStr, ValueType Ty>
2609 : N3V<0,1,0b11,0b0000,0,0, (outs DPR:$dst),
2610 (ins DPR:$lhs, DPR:$rhs, i32imm:$index), IIC_VEXTD,
2611 !strconcat(OpcodeStr, "\t$dst, $lhs, $rhs, $index"), "",
2612 [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
2613 (Ty DPR:$rhs), imm:$index)))]>;
2615 class VEXTq<string OpcodeStr, ValueType Ty>
2616 : N3V<0,1,0b11,0b0000,1,0, (outs QPR:$dst),
2617 (ins QPR:$lhs, QPR:$rhs, i32imm:$index), IIC_VEXTQ,
2618 !strconcat(OpcodeStr, "\t$dst, $lhs, $rhs, $index"), "",
2619 [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
2620 (Ty QPR:$rhs), imm:$index)))]>;
2622 def VEXTd8 : VEXTd<"vext.8", v8i8>;
2623 def VEXTd16 : VEXTd<"vext.16", v4i16>;
2624 def VEXTd32 : VEXTd<"vext.32", v2i32>;
2625 def VEXTdf : VEXTd<"vext.32", v2f32>;
2627 def VEXTq8 : VEXTq<"vext.8", v16i8>;
2628 def VEXTq16 : VEXTq<"vext.16", v8i16>;
2629 def VEXTq32 : VEXTq<"vext.32", v4i32>;
2630 def VEXTqf : VEXTq<"vext.32", v4f32>;
2632 // VTRN : Vector Transpose
2634 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn.8">;
2635 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn.16">;
2636 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn.32">;
2638 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn.8">;
2639 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn.16">;
2640 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn.32">;
2642 // VUZP : Vector Unzip (Deinterleave)
2644 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp.8">;
2645 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp.16">;
2646 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp.32">;
2648 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp.8">;
2649 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp.16">;
2650 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp.32">;
2652 // VZIP : Vector Zip (Interleave)
2654 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip.8">;
2655 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip.16">;
2656 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip.32">;
2658 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip.8">;
2659 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip.16">;
2660 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip.32">;
2662 // Vector Table Lookup and Table Extension.
2664 // VTBL : Vector Table Lookup
2666 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
2667 (ins DPR:$tbl1, DPR:$src), IIC_VTB1,
2668 "vtbl.8\t$dst, \\{$tbl1\\}, $src", "",
2669 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
2670 let hasExtraSrcRegAllocReq = 1 in {
2672 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
2673 (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTB2,
2674 "vtbl.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "",
2675 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl2
2676 DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
2678 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
2679 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTB3,
2680 "vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "",
2681 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl3
2682 DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
2684 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
2685 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTB4,
2686 "vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "",
2687 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl4 DPR:$tbl1, DPR:$tbl2,
2688 DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
2689 } // hasExtraSrcRegAllocReq = 1
2691 // VTBX : Vector Table Extension
2693 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
2694 (ins DPR:$orig, DPR:$tbl1, DPR:$src), IIC_VTBX1,
2695 "vtbx.8\t$dst, \\{$tbl1\\}, $src", "$orig = $dst",
2696 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
2697 DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
2698 let hasExtraSrcRegAllocReq = 1 in {
2700 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
2701 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTBX2,
2702 "vtbx.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "$orig = $dst",
2703 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx2
2704 DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
2706 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
2707 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTBX3,
2708 "vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "$orig = $dst",
2709 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx3 DPR:$orig, DPR:$tbl1,
2710 DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
2712 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
2713 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTBX4,
2714 "vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "$orig = $dst",
2715 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx4 DPR:$orig, DPR:$tbl1,
2716 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
2717 } // hasExtraSrcRegAllocReq = 1
2719 //===----------------------------------------------------------------------===//
2720 // NEON instructions for single-precision FP math
2721 //===----------------------------------------------------------------------===//
2723 // These need separate instructions because they must use DPR_VFP2 register
2724 // class which have SPR sub-registers.
2726 // Vector Add Operations used for single-precision FP
2727 let neverHasSideEffects = 1 in
2728 def VADDfd_sfp : N3VDs<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd,1>;
2729 def : N3VDsPat<fadd, VADDfd_sfp>;
2731 // Vector Sub Operations used for single-precision FP
2732 let neverHasSideEffects = 1 in
2733 def VSUBfd_sfp : N3VDs<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub,0>;
2734 def : N3VDsPat<fsub, VSUBfd_sfp>;
2736 // Vector Multiply Operations used for single-precision FP
2737 let neverHasSideEffects = 1 in
2738 def VMULfd_sfp : N3VDs<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul,1>;
2739 def : N3VDsPat<fmul, VMULfd_sfp>;
2741 // Vector Multiply-Accumulate/Subtract used for single-precision FP
2742 let neverHasSideEffects = 1 in
2743 def VMLAfd_sfp : N3VDMulOps<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla.f32", v2f32,fmul,fadd>;
2744 def : N3VDMulOpsPat<fmul, fadd, VMLAfd_sfp>;
2746 let neverHasSideEffects = 1 in
2747 def VMLSfd_sfp : N3VDMulOps<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls.f32", v2f32,fmul,fsub>;
2748 def : N3VDMulOpsPat<fmul, fsub, VMLSfd_sfp>;
2750 // Vector Absolute used for single-precision FP
2751 let neverHasSideEffects = 1 in
2752 def VABSfd_sfp : N2VDInts<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2753 IIC_VUNAD, "vabs.f32",
2754 v2f32, v2f32, int_arm_neon_vabs>;
2755 def : N2VDIntsPat<fabs, VABSfd_sfp>;
2757 // Vector Negate used for single-precision FP
2758 let neverHasSideEffects = 1 in
2759 def VNEGf32d_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
2760 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
2761 "vneg.f32\t$dst, $src", "", []>;
2762 def : N2VDIntsPat<fneg, VNEGf32d_sfp>;
2764 // Vector Convert between single-precision FP and integer
2765 let neverHasSideEffects = 1 in
2766 def VCVTf2sd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
2767 v2i32, v2f32, fp_to_sint>;
2768 def : N2VDsPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
2770 let neverHasSideEffects = 1 in
2771 def VCVTf2ud_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
2772 v2i32, v2f32, fp_to_uint>;
2773 def : N2VDsPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
2775 let neverHasSideEffects = 1 in
2776 def VCVTs2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
2777 v2f32, v2i32, sint_to_fp>;
2778 def : N2VDsPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
2780 let neverHasSideEffects = 1 in
2781 def VCVTu2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
2782 v2f32, v2i32, uint_to_fp>;
2783 def : N2VDsPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
2785 //===----------------------------------------------------------------------===//
2786 // Non-Instruction Patterns
2787 //===----------------------------------------------------------------------===//
2790 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
2791 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
2792 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
2793 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
2794 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
2795 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
2796 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
2797 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
2798 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
2799 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
2800 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
2801 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
2802 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
2803 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
2804 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
2805 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
2806 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
2807 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
2808 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
2809 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
2810 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
2811 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
2812 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
2813 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
2814 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
2815 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
2816 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
2817 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
2818 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
2819 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
2821 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
2822 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
2823 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
2824 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
2825 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
2826 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
2827 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
2828 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
2829 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
2830 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
2831 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
2832 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
2833 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
2834 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
2835 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
2836 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
2837 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
2838 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
2839 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
2840 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
2841 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
2842 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
2843 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
2844 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
2845 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
2846 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
2847 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
2848 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
2849 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
2850 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;