1 //===-- ARMInstrNEON.td - NEON support for ARM -------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // NEON-specific Operands.
17 //===----------------------------------------------------------------------===//
18 def nModImm : Operand<i32> {
19 let PrintMethod = "printNEONModImmOperand";
22 def nImmSplatI8AsmOperand : AsmOperandClass { let Name = "NEONi8splat"; }
23 def nImmSplatI8 : Operand<i32> {
24 let PrintMethod = "printNEONModImmOperand";
25 let ParserMatchClass = nImmSplatI8AsmOperand;
27 def nImmSplatI16AsmOperand : AsmOperandClass { let Name = "NEONi16splat"; }
28 def nImmSplatI16 : Operand<i32> {
29 let PrintMethod = "printNEONModImmOperand";
30 let ParserMatchClass = nImmSplatI16AsmOperand;
32 def nImmSplatI32AsmOperand : AsmOperandClass { let Name = "NEONi32splat"; }
33 def nImmSplatI32 : Operand<i32> {
34 let PrintMethod = "printNEONModImmOperand";
35 let ParserMatchClass = nImmSplatI32AsmOperand;
37 def nImmSplatNotI16AsmOperand : AsmOperandClass { let Name = "NEONi16splatNot"; }
38 def nImmSplatNotI16 : Operand<i32> {
39 let ParserMatchClass = nImmSplatNotI16AsmOperand;
41 def nImmSplatNotI32AsmOperand : AsmOperandClass { let Name = "NEONi32splatNot"; }
42 def nImmSplatNotI32 : Operand<i32> {
43 let ParserMatchClass = nImmSplatNotI32AsmOperand;
45 def nImmVMOVI32AsmOperand : AsmOperandClass { let Name = "NEONi32vmov"; }
46 def nImmVMOVI32 : Operand<i32> {
47 let PrintMethod = "printNEONModImmOperand";
48 let ParserMatchClass = nImmVMOVI32AsmOperand;
51 def nImmVMOVI16AsmOperandByteReplicate :
53 let Name = "NEONi16vmovByteReplicate";
54 let PredicateMethod = "isNEONi16ByteReplicate";
55 let RenderMethod = "addNEONvmovByteReplicateOperands";
57 def nImmVMOVI32AsmOperandByteReplicate :
59 let Name = "NEONi32vmovByteReplicate";
60 let PredicateMethod = "isNEONi32ByteReplicate";
61 let RenderMethod = "addNEONvmovByteReplicateOperands";
63 def nImmVMVNI16AsmOperandByteReplicate :
65 let Name = "NEONi16invByteReplicate";
66 let PredicateMethod = "isNEONi16ByteReplicate";
67 let RenderMethod = "addNEONinvByteReplicateOperands";
69 def nImmVMVNI32AsmOperandByteReplicate :
71 let Name = "NEONi32invByteReplicate";
72 let PredicateMethod = "isNEONi32ByteReplicate";
73 let RenderMethod = "addNEONinvByteReplicateOperands";
76 def nImmVMOVI16ByteReplicate : Operand<i32> {
77 let PrintMethod = "printNEONModImmOperand";
78 let ParserMatchClass = nImmVMOVI16AsmOperandByteReplicate;
80 def nImmVMOVI32ByteReplicate : Operand<i32> {
81 let PrintMethod = "printNEONModImmOperand";
82 let ParserMatchClass = nImmVMOVI32AsmOperandByteReplicate;
84 def nImmVMVNI16ByteReplicate : Operand<i32> {
85 let PrintMethod = "printNEONModImmOperand";
86 let ParserMatchClass = nImmVMVNI16AsmOperandByteReplicate;
88 def nImmVMVNI32ByteReplicate : Operand<i32> {
89 let PrintMethod = "printNEONModImmOperand";
90 let ParserMatchClass = nImmVMVNI32AsmOperandByteReplicate;
93 def nImmVMOVI32NegAsmOperand : AsmOperandClass { let Name = "NEONi32vmovNeg"; }
94 def nImmVMOVI32Neg : Operand<i32> {
95 let PrintMethod = "printNEONModImmOperand";
96 let ParserMatchClass = nImmVMOVI32NegAsmOperand;
98 def nImmVMOVF32 : Operand<i32> {
99 let PrintMethod = "printFPImmOperand";
100 let ParserMatchClass = FPImmOperand;
102 def nImmSplatI64AsmOperand : AsmOperandClass { let Name = "NEONi64splat"; }
103 def nImmSplatI64 : Operand<i32> {
104 let PrintMethod = "printNEONModImmOperand";
105 let ParserMatchClass = nImmSplatI64AsmOperand;
108 def VectorIndex8Operand : AsmOperandClass { let Name = "VectorIndex8"; }
109 def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; }
110 def VectorIndex32Operand : AsmOperandClass { let Name = "VectorIndex32"; }
111 def VectorIndex8 : Operand<i32>, ImmLeaf<i32, [{
112 return ((uint64_t)Imm) < 8;
114 let ParserMatchClass = VectorIndex8Operand;
115 let PrintMethod = "printVectorIndex";
116 let MIOperandInfo = (ops i32imm);
118 def VectorIndex16 : Operand<i32>, ImmLeaf<i32, [{
119 return ((uint64_t)Imm) < 4;
121 let ParserMatchClass = VectorIndex16Operand;
122 let PrintMethod = "printVectorIndex";
123 let MIOperandInfo = (ops i32imm);
125 def VectorIndex32 : Operand<i32>, ImmLeaf<i32, [{
126 return ((uint64_t)Imm) < 2;
128 let ParserMatchClass = VectorIndex32Operand;
129 let PrintMethod = "printVectorIndex";
130 let MIOperandInfo = (ops i32imm);
133 // Register list of one D register.
134 def VecListOneDAsmOperand : AsmOperandClass {
135 let Name = "VecListOneD";
136 let ParserMethod = "parseVectorList";
137 let RenderMethod = "addVecListOperands";
139 def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> {
140 let ParserMatchClass = VecListOneDAsmOperand;
142 // Register list of two sequential D registers.
143 def VecListDPairAsmOperand : AsmOperandClass {
144 let Name = "VecListDPair";
145 let ParserMethod = "parseVectorList";
146 let RenderMethod = "addVecListOperands";
148 def VecListDPair : RegisterOperand<DPair, "printVectorListTwo"> {
149 let ParserMatchClass = VecListDPairAsmOperand;
151 // Register list of three sequential D registers.
152 def VecListThreeDAsmOperand : AsmOperandClass {
153 let Name = "VecListThreeD";
154 let ParserMethod = "parseVectorList";
155 let RenderMethod = "addVecListOperands";
157 def VecListThreeD : RegisterOperand<DPR, "printVectorListThree"> {
158 let ParserMatchClass = VecListThreeDAsmOperand;
160 // Register list of four sequential D registers.
161 def VecListFourDAsmOperand : AsmOperandClass {
162 let Name = "VecListFourD";
163 let ParserMethod = "parseVectorList";
164 let RenderMethod = "addVecListOperands";
166 def VecListFourD : RegisterOperand<DPR, "printVectorListFour"> {
167 let ParserMatchClass = VecListFourDAsmOperand;
169 // Register list of two D registers spaced by 2 (two sequential Q registers).
170 def VecListDPairSpacedAsmOperand : AsmOperandClass {
171 let Name = "VecListDPairSpaced";
172 let ParserMethod = "parseVectorList";
173 let RenderMethod = "addVecListOperands";
175 def VecListDPairSpaced : RegisterOperand<DPair, "printVectorListTwoSpaced"> {
176 let ParserMatchClass = VecListDPairSpacedAsmOperand;
178 // Register list of three D registers spaced by 2 (three Q registers).
179 def VecListThreeQAsmOperand : AsmOperandClass {
180 let Name = "VecListThreeQ";
181 let ParserMethod = "parseVectorList";
182 let RenderMethod = "addVecListOperands";
184 def VecListThreeQ : RegisterOperand<DPR, "printVectorListThreeSpaced"> {
185 let ParserMatchClass = VecListThreeQAsmOperand;
187 // Register list of three D registers spaced by 2 (three Q registers).
188 def VecListFourQAsmOperand : AsmOperandClass {
189 let Name = "VecListFourQ";
190 let ParserMethod = "parseVectorList";
191 let RenderMethod = "addVecListOperands";
193 def VecListFourQ : RegisterOperand<DPR, "printVectorListFourSpaced"> {
194 let ParserMatchClass = VecListFourQAsmOperand;
197 // Register list of one D register, with "all lanes" subscripting.
198 def VecListOneDAllLanesAsmOperand : AsmOperandClass {
199 let Name = "VecListOneDAllLanes";
200 let ParserMethod = "parseVectorList";
201 let RenderMethod = "addVecListOperands";
203 def VecListOneDAllLanes : RegisterOperand<DPR, "printVectorListOneAllLanes"> {
204 let ParserMatchClass = VecListOneDAllLanesAsmOperand;
206 // Register list of two D registers, with "all lanes" subscripting.
207 def VecListDPairAllLanesAsmOperand : AsmOperandClass {
208 let Name = "VecListDPairAllLanes";
209 let ParserMethod = "parseVectorList";
210 let RenderMethod = "addVecListOperands";
212 def VecListDPairAllLanes : RegisterOperand<DPair,
213 "printVectorListTwoAllLanes"> {
214 let ParserMatchClass = VecListDPairAllLanesAsmOperand;
216 // Register list of two D registers spaced by 2 (two sequential Q registers).
217 def VecListDPairSpacedAllLanesAsmOperand : AsmOperandClass {
218 let Name = "VecListDPairSpacedAllLanes";
219 let ParserMethod = "parseVectorList";
220 let RenderMethod = "addVecListOperands";
222 def VecListDPairSpacedAllLanes : RegisterOperand<DPair,
223 "printVectorListTwoSpacedAllLanes"> {
224 let ParserMatchClass = VecListDPairSpacedAllLanesAsmOperand;
226 // Register list of three D registers, with "all lanes" subscripting.
227 def VecListThreeDAllLanesAsmOperand : AsmOperandClass {
228 let Name = "VecListThreeDAllLanes";
229 let ParserMethod = "parseVectorList";
230 let RenderMethod = "addVecListOperands";
232 def VecListThreeDAllLanes : RegisterOperand<DPR,
233 "printVectorListThreeAllLanes"> {
234 let ParserMatchClass = VecListThreeDAllLanesAsmOperand;
236 // Register list of three D registers spaced by 2 (three sequential Q regs).
237 def VecListThreeQAllLanesAsmOperand : AsmOperandClass {
238 let Name = "VecListThreeQAllLanes";
239 let ParserMethod = "parseVectorList";
240 let RenderMethod = "addVecListOperands";
242 def VecListThreeQAllLanes : RegisterOperand<DPR,
243 "printVectorListThreeSpacedAllLanes"> {
244 let ParserMatchClass = VecListThreeQAllLanesAsmOperand;
246 // Register list of four D registers, with "all lanes" subscripting.
247 def VecListFourDAllLanesAsmOperand : AsmOperandClass {
248 let Name = "VecListFourDAllLanes";
249 let ParserMethod = "parseVectorList";
250 let RenderMethod = "addVecListOperands";
252 def VecListFourDAllLanes : RegisterOperand<DPR, "printVectorListFourAllLanes"> {
253 let ParserMatchClass = VecListFourDAllLanesAsmOperand;
255 // Register list of four D registers spaced by 2 (four sequential Q regs).
256 def VecListFourQAllLanesAsmOperand : AsmOperandClass {
257 let Name = "VecListFourQAllLanes";
258 let ParserMethod = "parseVectorList";
259 let RenderMethod = "addVecListOperands";
261 def VecListFourQAllLanes : RegisterOperand<DPR,
262 "printVectorListFourSpacedAllLanes"> {
263 let ParserMatchClass = VecListFourQAllLanesAsmOperand;
267 // Register list of one D register, with byte lane subscripting.
268 def VecListOneDByteIndexAsmOperand : AsmOperandClass {
269 let Name = "VecListOneDByteIndexed";
270 let ParserMethod = "parseVectorList";
271 let RenderMethod = "addVecListIndexedOperands";
273 def VecListOneDByteIndexed : Operand<i32> {
274 let ParserMatchClass = VecListOneDByteIndexAsmOperand;
275 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
277 // ...with half-word lane subscripting.
278 def VecListOneDHWordIndexAsmOperand : AsmOperandClass {
279 let Name = "VecListOneDHWordIndexed";
280 let ParserMethod = "parseVectorList";
281 let RenderMethod = "addVecListIndexedOperands";
283 def VecListOneDHWordIndexed : Operand<i32> {
284 let ParserMatchClass = VecListOneDHWordIndexAsmOperand;
285 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
287 // ...with word lane subscripting.
288 def VecListOneDWordIndexAsmOperand : AsmOperandClass {
289 let Name = "VecListOneDWordIndexed";
290 let ParserMethod = "parseVectorList";
291 let RenderMethod = "addVecListIndexedOperands";
293 def VecListOneDWordIndexed : Operand<i32> {
294 let ParserMatchClass = VecListOneDWordIndexAsmOperand;
295 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
298 // Register list of two D registers with byte lane subscripting.
299 def VecListTwoDByteIndexAsmOperand : AsmOperandClass {
300 let Name = "VecListTwoDByteIndexed";
301 let ParserMethod = "parseVectorList";
302 let RenderMethod = "addVecListIndexedOperands";
304 def VecListTwoDByteIndexed : Operand<i32> {
305 let ParserMatchClass = VecListTwoDByteIndexAsmOperand;
306 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
308 // ...with half-word lane subscripting.
309 def VecListTwoDHWordIndexAsmOperand : AsmOperandClass {
310 let Name = "VecListTwoDHWordIndexed";
311 let ParserMethod = "parseVectorList";
312 let RenderMethod = "addVecListIndexedOperands";
314 def VecListTwoDHWordIndexed : Operand<i32> {
315 let ParserMatchClass = VecListTwoDHWordIndexAsmOperand;
316 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
318 // ...with word lane subscripting.
319 def VecListTwoDWordIndexAsmOperand : AsmOperandClass {
320 let Name = "VecListTwoDWordIndexed";
321 let ParserMethod = "parseVectorList";
322 let RenderMethod = "addVecListIndexedOperands";
324 def VecListTwoDWordIndexed : Operand<i32> {
325 let ParserMatchClass = VecListTwoDWordIndexAsmOperand;
326 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
328 // Register list of two Q registers with half-word lane subscripting.
329 def VecListTwoQHWordIndexAsmOperand : AsmOperandClass {
330 let Name = "VecListTwoQHWordIndexed";
331 let ParserMethod = "parseVectorList";
332 let RenderMethod = "addVecListIndexedOperands";
334 def VecListTwoQHWordIndexed : Operand<i32> {
335 let ParserMatchClass = VecListTwoQHWordIndexAsmOperand;
336 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
338 // ...with word lane subscripting.
339 def VecListTwoQWordIndexAsmOperand : AsmOperandClass {
340 let Name = "VecListTwoQWordIndexed";
341 let ParserMethod = "parseVectorList";
342 let RenderMethod = "addVecListIndexedOperands";
344 def VecListTwoQWordIndexed : Operand<i32> {
345 let ParserMatchClass = VecListTwoQWordIndexAsmOperand;
346 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
350 // Register list of three D registers with byte lane subscripting.
351 def VecListThreeDByteIndexAsmOperand : AsmOperandClass {
352 let Name = "VecListThreeDByteIndexed";
353 let ParserMethod = "parseVectorList";
354 let RenderMethod = "addVecListIndexedOperands";
356 def VecListThreeDByteIndexed : Operand<i32> {
357 let ParserMatchClass = VecListThreeDByteIndexAsmOperand;
358 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
360 // ...with half-word lane subscripting.
361 def VecListThreeDHWordIndexAsmOperand : AsmOperandClass {
362 let Name = "VecListThreeDHWordIndexed";
363 let ParserMethod = "parseVectorList";
364 let RenderMethod = "addVecListIndexedOperands";
366 def VecListThreeDHWordIndexed : Operand<i32> {
367 let ParserMatchClass = VecListThreeDHWordIndexAsmOperand;
368 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
370 // ...with word lane subscripting.
371 def VecListThreeDWordIndexAsmOperand : AsmOperandClass {
372 let Name = "VecListThreeDWordIndexed";
373 let ParserMethod = "parseVectorList";
374 let RenderMethod = "addVecListIndexedOperands";
376 def VecListThreeDWordIndexed : Operand<i32> {
377 let ParserMatchClass = VecListThreeDWordIndexAsmOperand;
378 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
380 // Register list of three Q registers with half-word lane subscripting.
381 def VecListThreeQHWordIndexAsmOperand : AsmOperandClass {
382 let Name = "VecListThreeQHWordIndexed";
383 let ParserMethod = "parseVectorList";
384 let RenderMethod = "addVecListIndexedOperands";
386 def VecListThreeQHWordIndexed : Operand<i32> {
387 let ParserMatchClass = VecListThreeQHWordIndexAsmOperand;
388 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
390 // ...with word lane subscripting.
391 def VecListThreeQWordIndexAsmOperand : AsmOperandClass {
392 let Name = "VecListThreeQWordIndexed";
393 let ParserMethod = "parseVectorList";
394 let RenderMethod = "addVecListIndexedOperands";
396 def VecListThreeQWordIndexed : Operand<i32> {
397 let ParserMatchClass = VecListThreeQWordIndexAsmOperand;
398 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
401 // Register list of four D registers with byte lane subscripting.
402 def VecListFourDByteIndexAsmOperand : AsmOperandClass {
403 let Name = "VecListFourDByteIndexed";
404 let ParserMethod = "parseVectorList";
405 let RenderMethod = "addVecListIndexedOperands";
407 def VecListFourDByteIndexed : Operand<i32> {
408 let ParserMatchClass = VecListFourDByteIndexAsmOperand;
409 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
411 // ...with half-word lane subscripting.
412 def VecListFourDHWordIndexAsmOperand : AsmOperandClass {
413 let Name = "VecListFourDHWordIndexed";
414 let ParserMethod = "parseVectorList";
415 let RenderMethod = "addVecListIndexedOperands";
417 def VecListFourDHWordIndexed : Operand<i32> {
418 let ParserMatchClass = VecListFourDHWordIndexAsmOperand;
419 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
421 // ...with word lane subscripting.
422 def VecListFourDWordIndexAsmOperand : AsmOperandClass {
423 let Name = "VecListFourDWordIndexed";
424 let ParserMethod = "parseVectorList";
425 let RenderMethod = "addVecListIndexedOperands";
427 def VecListFourDWordIndexed : Operand<i32> {
428 let ParserMatchClass = VecListFourDWordIndexAsmOperand;
429 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
431 // Register list of four Q registers with half-word lane subscripting.
432 def VecListFourQHWordIndexAsmOperand : AsmOperandClass {
433 let Name = "VecListFourQHWordIndexed";
434 let ParserMethod = "parseVectorList";
435 let RenderMethod = "addVecListIndexedOperands";
437 def VecListFourQHWordIndexed : Operand<i32> {
438 let ParserMatchClass = VecListFourQHWordIndexAsmOperand;
439 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
441 // ...with word lane subscripting.
442 def VecListFourQWordIndexAsmOperand : AsmOperandClass {
443 let Name = "VecListFourQWordIndexed";
444 let ParserMethod = "parseVectorList";
445 let RenderMethod = "addVecListIndexedOperands";
447 def VecListFourQWordIndexed : Operand<i32> {
448 let ParserMatchClass = VecListFourQWordIndexAsmOperand;
449 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
452 def dword_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
453 return cast<LoadSDNode>(N)->getAlignment() >= 8;
455 def dword_alignedstore : PatFrag<(ops node:$val, node:$ptr),
456 (store node:$val, node:$ptr), [{
457 return cast<StoreSDNode>(N)->getAlignment() >= 8;
459 def word_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
460 return cast<LoadSDNode>(N)->getAlignment() == 4;
462 def word_alignedstore : PatFrag<(ops node:$val, node:$ptr),
463 (store node:$val, node:$ptr), [{
464 return cast<StoreSDNode>(N)->getAlignment() == 4;
466 def hword_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
467 return cast<LoadSDNode>(N)->getAlignment() == 2;
469 def hword_alignedstore : PatFrag<(ops node:$val, node:$ptr),
470 (store node:$val, node:$ptr), [{
471 return cast<StoreSDNode>(N)->getAlignment() == 2;
473 def byte_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
474 return cast<LoadSDNode>(N)->getAlignment() == 1;
476 def byte_alignedstore : PatFrag<(ops node:$val, node:$ptr),
477 (store node:$val, node:$ptr), [{
478 return cast<StoreSDNode>(N)->getAlignment() == 1;
480 def non_word_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
481 return cast<LoadSDNode>(N)->getAlignment() < 4;
483 def non_word_alignedstore : PatFrag<(ops node:$val, node:$ptr),
484 (store node:$val, node:$ptr), [{
485 return cast<StoreSDNode>(N)->getAlignment() < 4;
488 //===----------------------------------------------------------------------===//
489 // NEON-specific DAG Nodes.
490 //===----------------------------------------------------------------------===//
492 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
493 def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
495 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
496 def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
497 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
498 def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
499 def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
500 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
501 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
502 def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
503 def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
504 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
505 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
507 // Types for vector shift by immediates. The "SHX" version is for long and
508 // narrow operations where the source and destination vectors have different
509 // types. The "SHINS" version is for shift and insert operations.
510 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
512 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
514 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
515 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
517 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
518 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
519 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
520 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
522 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
523 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
524 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
526 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
527 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
528 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
529 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
530 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
531 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
533 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
534 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
535 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
537 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
538 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
540 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
542 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
543 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
545 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
546 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
547 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
548 def NEONvmovFPImm : SDNode<"ARMISD::VMOVFPIMM", SDTARMVMOVIMM>;
550 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
552 def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
553 def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
555 def NEONvbsl : SDNode<"ARMISD::VBSL",
556 SDTypeProfile<1, 3, [SDTCisVec<0>,
559 SDTCisSameAs<0, 3>]>>;
561 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
563 // VDUPLANE can produce a quad-register result from a double-register source,
564 // so the result is not constrained to match the source.
565 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
566 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
569 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
570 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
571 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
573 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
574 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
575 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
576 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
578 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
580 SDTCisSameAs<0, 3>]>;
581 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
582 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
583 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
585 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
586 SDTCisSameAs<1, 2>]>;
587 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
588 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
590 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
591 SDTCisSameAs<0, 2>]>;
592 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
593 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
595 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
596 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
597 unsigned EltBits = 0;
598 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
599 return (EltBits == 32 && EltVal == 0);
602 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
603 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
604 unsigned EltBits = 0;
605 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
606 return (EltBits == 8 && EltVal == 0xff);
609 //===----------------------------------------------------------------------===//
610 // NEON load / store instructions
611 //===----------------------------------------------------------------------===//
613 // Use VLDM to load a Q register as a D register pair.
614 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
616 : PseudoVFPLdStM<(outs DPair:$dst), (ins GPR:$Rn),
618 [(set DPair:$dst, (v2f64 (load GPR:$Rn)))]>;
620 // Use VSTM to store a Q register as a D register pair.
621 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
623 : PseudoVFPLdStM<(outs), (ins DPair:$src, GPR:$Rn),
625 [(store (v2f64 DPair:$src), GPR:$Rn)]>;
627 // Classes for VLD* pseudo-instructions with multi-register operands.
628 // These are expanded to real instructions after register allocation.
629 class VLDQPseudo<InstrItinClass itin>
630 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
631 class VLDQWBPseudo<InstrItinClass itin>
632 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
633 (ins addrmode6:$addr, am6offset:$offset), itin,
635 class VLDQWBfixedPseudo<InstrItinClass itin>
636 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
637 (ins addrmode6:$addr), itin,
639 class VLDQWBregisterPseudo<InstrItinClass itin>
640 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
641 (ins addrmode6:$addr, rGPR:$offset), itin,
644 class VLDQQPseudo<InstrItinClass itin>
645 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
646 class VLDQQWBPseudo<InstrItinClass itin>
647 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
648 (ins addrmode6:$addr, am6offset:$offset), itin,
650 class VLDQQWBfixedPseudo<InstrItinClass itin>
651 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
652 (ins addrmode6:$addr), itin,
654 class VLDQQWBregisterPseudo<InstrItinClass itin>
655 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
656 (ins addrmode6:$addr, rGPR:$offset), itin,
660 class VLDQQQQPseudo<InstrItinClass itin>
661 : PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src),itin,
663 class VLDQQQQWBPseudo<InstrItinClass itin>
664 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
665 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
666 "$addr.addr = $wb, $src = $dst">;
668 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
670 // VLD1 : Vector Load (multiple single elements)
671 class VLD1D<bits<4> op7_4, string Dt, Operand AddrMode>
672 : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd),
673 (ins AddrMode:$Rn), IIC_VLD1,
674 "vld1", Dt, "$Vd, $Rn", "", []> {
677 let DecoderMethod = "DecodeVLDST1Instruction";
679 class VLD1Q<bits<4> op7_4, string Dt, Operand AddrMode>
680 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd),
681 (ins AddrMode:$Rn), IIC_VLD1x2,
682 "vld1", Dt, "$Vd, $Rn", "", []> {
684 let Inst{5-4} = Rn{5-4};
685 let DecoderMethod = "DecodeVLDST1Instruction";
688 def VLD1d8 : VLD1D<{0,0,0,?}, "8", addrmode6align64>;
689 def VLD1d16 : VLD1D<{0,1,0,?}, "16", addrmode6align64>;
690 def VLD1d32 : VLD1D<{1,0,0,?}, "32", addrmode6align64>;
691 def VLD1d64 : VLD1D<{1,1,0,?}, "64", addrmode6align64>;
693 def VLD1q8 : VLD1Q<{0,0,?,?}, "8", addrmode6align64or128>;
694 def VLD1q16 : VLD1Q<{0,1,?,?}, "16", addrmode6align64or128>;
695 def VLD1q32 : VLD1Q<{1,0,?,?}, "32", addrmode6align64or128>;
696 def VLD1q64 : VLD1Q<{1,1,?,?}, "64", addrmode6align64or128>;
698 // ...with address register writeback:
699 multiclass VLD1DWB<bits<4> op7_4, string Dt, Operand AddrMode> {
700 def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
701 (ins AddrMode:$Rn), IIC_VLD1u,
702 "vld1", Dt, "$Vd, $Rn!",
703 "$Rn.addr = $wb", []> {
704 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
706 let DecoderMethod = "DecodeVLDST1Instruction";
708 def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
709 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1u,
710 "vld1", Dt, "$Vd, $Rn, $Rm",
711 "$Rn.addr = $wb", []> {
713 let DecoderMethod = "DecodeVLDST1Instruction";
716 multiclass VLD1QWB<bits<4> op7_4, string Dt, Operand AddrMode> {
717 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
718 (ins AddrMode:$Rn), IIC_VLD1x2u,
719 "vld1", Dt, "$Vd, $Rn!",
720 "$Rn.addr = $wb", []> {
721 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
722 let Inst{5-4} = Rn{5-4};
723 let DecoderMethod = "DecodeVLDST1Instruction";
725 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
726 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,
727 "vld1", Dt, "$Vd, $Rn, $Rm",
728 "$Rn.addr = $wb", []> {
729 let Inst{5-4} = Rn{5-4};
730 let DecoderMethod = "DecodeVLDST1Instruction";
734 defm VLD1d8wb : VLD1DWB<{0,0,0,?}, "8", addrmode6align64>;
735 defm VLD1d16wb : VLD1DWB<{0,1,0,?}, "16", addrmode6align64>;
736 defm VLD1d32wb : VLD1DWB<{1,0,0,?}, "32", addrmode6align64>;
737 defm VLD1d64wb : VLD1DWB<{1,1,0,?}, "64", addrmode6align64>;
738 defm VLD1q8wb : VLD1QWB<{0,0,?,?}, "8", addrmode6align64or128>;
739 defm VLD1q16wb : VLD1QWB<{0,1,?,?}, "16", addrmode6align64or128>;
740 defm VLD1q32wb : VLD1QWB<{1,0,?,?}, "32", addrmode6align64or128>;
741 defm VLD1q64wb : VLD1QWB<{1,1,?,?}, "64", addrmode6align64or128>;
743 // ...with 3 registers
744 class VLD1D3<bits<4> op7_4, string Dt, Operand AddrMode>
745 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd),
746 (ins AddrMode:$Rn), IIC_VLD1x3, "vld1", Dt,
747 "$Vd, $Rn", "", []> {
750 let DecoderMethod = "DecodeVLDST1Instruction";
752 multiclass VLD1D3WB<bits<4> op7_4, string Dt, Operand AddrMode> {
753 def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
754 (ins AddrMode:$Rn), IIC_VLD1x2u,
755 "vld1", Dt, "$Vd, $Rn!",
756 "$Rn.addr = $wb", []> {
757 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
759 let DecoderMethod = "DecodeVLDST1Instruction";
761 def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
762 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,
763 "vld1", Dt, "$Vd, $Rn, $Rm",
764 "$Rn.addr = $wb", []> {
766 let DecoderMethod = "DecodeVLDST1Instruction";
770 def VLD1d8T : VLD1D3<{0,0,0,?}, "8", addrmode6align64>;
771 def VLD1d16T : VLD1D3<{0,1,0,?}, "16", addrmode6align64>;
772 def VLD1d32T : VLD1D3<{1,0,0,?}, "32", addrmode6align64>;
773 def VLD1d64T : VLD1D3<{1,1,0,?}, "64", addrmode6align64>;
775 defm VLD1d8Twb : VLD1D3WB<{0,0,0,?}, "8", addrmode6align64>;
776 defm VLD1d16Twb : VLD1D3WB<{0,1,0,?}, "16", addrmode6align64>;
777 defm VLD1d32Twb : VLD1D3WB<{1,0,0,?}, "32", addrmode6align64>;
778 defm VLD1d64Twb : VLD1D3WB<{1,1,0,?}, "64", addrmode6align64>;
780 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
781 def VLD1d64TPseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD1x3>;
782 def VLD1d64TPseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD1x3>;
784 // ...with 4 registers
785 class VLD1D4<bits<4> op7_4, string Dt, Operand AddrMode>
786 : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd),
787 (ins AddrMode:$Rn), IIC_VLD1x4, "vld1", Dt,
788 "$Vd, $Rn", "", []> {
790 let Inst{5-4} = Rn{5-4};
791 let DecoderMethod = "DecodeVLDST1Instruction";
793 multiclass VLD1D4WB<bits<4> op7_4, string Dt, Operand AddrMode> {
794 def _fixed : NLdSt<0,0b10,0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb),
795 (ins AddrMode:$Rn), IIC_VLD1x2u,
796 "vld1", Dt, "$Vd, $Rn!",
797 "$Rn.addr = $wb", []> {
798 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
799 let Inst{5-4} = Rn{5-4};
800 let DecoderMethod = "DecodeVLDST1Instruction";
802 def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb),
803 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,
804 "vld1", Dt, "$Vd, $Rn, $Rm",
805 "$Rn.addr = $wb", []> {
806 let Inst{5-4} = Rn{5-4};
807 let DecoderMethod = "DecodeVLDST1Instruction";
811 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8", addrmode6align64or128or256>;
812 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16", addrmode6align64or128or256>;
813 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32", addrmode6align64or128or256>;
814 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64", addrmode6align64or128or256>;
816 defm VLD1d8Qwb : VLD1D4WB<{0,0,?,?}, "8", addrmode6align64or128or256>;
817 defm VLD1d16Qwb : VLD1D4WB<{0,1,?,?}, "16", addrmode6align64or128or256>;
818 defm VLD1d32Qwb : VLD1D4WB<{1,0,?,?}, "32", addrmode6align64or128or256>;
819 defm VLD1d64Qwb : VLD1D4WB<{1,1,?,?}, "64", addrmode6align64or128or256>;
821 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
822 def VLD1d64QPseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD1x4>;
823 def VLD1d64QPseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD1x4>;
825 // VLD2 : Vector Load (multiple 2-element structures)
826 class VLD2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
827 InstrItinClass itin, Operand AddrMode>
828 : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd),
829 (ins AddrMode:$Rn), itin,
830 "vld2", Dt, "$Vd, $Rn", "", []> {
832 let Inst{5-4} = Rn{5-4};
833 let DecoderMethod = "DecodeVLDST2Instruction";
836 def VLD2d8 : VLD2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2,
837 addrmode6align64or128>;
838 def VLD2d16 : VLD2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2,
839 addrmode6align64or128>;
840 def VLD2d32 : VLD2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2,
841 addrmode6align64or128>;
843 def VLD2q8 : VLD2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2,
844 addrmode6align64or128or256>;
845 def VLD2q16 : VLD2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2,
846 addrmode6align64or128or256>;
847 def VLD2q32 : VLD2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2,
848 addrmode6align64or128or256>;
850 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
851 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
852 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
854 // ...with address register writeback:
855 multiclass VLD2WB<bits<4> op11_8, bits<4> op7_4, string Dt,
856 RegisterOperand VdTy, InstrItinClass itin, Operand AddrMode> {
857 def _fixed : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
858 (ins AddrMode:$Rn), itin,
859 "vld2", Dt, "$Vd, $Rn!",
860 "$Rn.addr = $wb", []> {
861 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
862 let Inst{5-4} = Rn{5-4};
863 let DecoderMethod = "DecodeVLDST2Instruction";
865 def _register : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
866 (ins AddrMode:$Rn, rGPR:$Rm), itin,
867 "vld2", Dt, "$Vd, $Rn, $Rm",
868 "$Rn.addr = $wb", []> {
869 let Inst{5-4} = Rn{5-4};
870 let DecoderMethod = "DecodeVLDST2Instruction";
874 defm VLD2d8wb : VLD2WB<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2u,
875 addrmode6align64or128>;
876 defm VLD2d16wb : VLD2WB<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2u,
877 addrmode6align64or128>;
878 defm VLD2d32wb : VLD2WB<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2u,
879 addrmode6align64or128>;
881 defm VLD2q8wb : VLD2WB<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2u,
882 addrmode6align64or128or256>;
883 defm VLD2q16wb : VLD2WB<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2u,
884 addrmode6align64or128or256>;
885 defm VLD2q32wb : VLD2WB<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2u,
886 addrmode6align64or128or256>;
888 def VLD2q8PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
889 def VLD2q16PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
890 def VLD2q32PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
891 def VLD2q8PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
892 def VLD2q16PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
893 def VLD2q32PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
895 // ...with double-spaced registers
896 def VLD2b8 : VLD2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2,
897 addrmode6align64or128>;
898 def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2,
899 addrmode6align64or128>;
900 def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2,
901 addrmode6align64or128>;
902 defm VLD2b8wb : VLD2WB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2u,
903 addrmode6align64or128>;
904 defm VLD2b16wb : VLD2WB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2u,
905 addrmode6align64or128>;
906 defm VLD2b32wb : VLD2WB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2u,
907 addrmode6align64or128>;
909 // VLD3 : Vector Load (multiple 3-element structures)
910 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
911 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
912 (ins addrmode6:$Rn), IIC_VLD3,
913 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
916 let DecoderMethod = "DecodeVLDST3Instruction";
919 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
920 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
921 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
923 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
924 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
925 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
927 // ...with address register writeback:
928 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
929 : NLdSt<0, 0b10, op11_8, op7_4,
930 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
931 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
932 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
933 "$Rn.addr = $wb", []> {
935 let DecoderMethod = "DecodeVLDST3Instruction";
938 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
939 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
940 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
942 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
943 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
944 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
946 // ...with double-spaced registers:
947 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
948 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
949 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
950 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
951 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
952 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
954 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
955 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
956 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
958 // ...alternate versions to be allocated odd register numbers:
959 def VLD3q8oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
960 def VLD3q16oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
961 def VLD3q32oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
963 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
964 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
965 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
967 // VLD4 : Vector Load (multiple 4-element structures)
968 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
969 : NLdSt<0, 0b10, op11_8, op7_4,
970 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
971 (ins addrmode6:$Rn), IIC_VLD4,
972 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
974 let Inst{5-4} = Rn{5-4};
975 let DecoderMethod = "DecodeVLDST4Instruction";
978 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
979 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
980 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
982 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
983 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
984 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
986 // ...with address register writeback:
987 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
988 : NLdSt<0, 0b10, op11_8, op7_4,
989 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
990 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u,
991 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
992 "$Rn.addr = $wb", []> {
993 let Inst{5-4} = Rn{5-4};
994 let DecoderMethod = "DecodeVLDST4Instruction";
997 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
998 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
999 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
1001 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
1002 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
1003 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
1005 // ...with double-spaced registers:
1006 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
1007 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
1008 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
1009 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
1010 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
1011 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
1013 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
1014 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
1015 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
1017 // ...alternate versions to be allocated odd register numbers:
1018 def VLD4q8oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
1019 def VLD4q16oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
1020 def VLD4q32oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
1022 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
1023 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
1024 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
1026 } // mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1
1028 // Classes for VLD*LN pseudo-instructions with multi-register operands.
1029 // These are expanded to real instructions after register allocation.
1030 class VLDQLNPseudo<InstrItinClass itin>
1031 : PseudoNLdSt<(outs QPR:$dst),
1032 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1033 itin, "$src = $dst">;
1034 class VLDQLNWBPseudo<InstrItinClass itin>
1035 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
1036 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1037 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
1038 class VLDQQLNPseudo<InstrItinClass itin>
1039 : PseudoNLdSt<(outs QQPR:$dst),
1040 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1041 itin, "$src = $dst">;
1042 class VLDQQLNWBPseudo<InstrItinClass itin>
1043 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
1044 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1045 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
1046 class VLDQQQQLNPseudo<InstrItinClass itin>
1047 : PseudoNLdSt<(outs QQQQPR:$dst),
1048 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1049 itin, "$src = $dst">;
1050 class VLDQQQQLNWBPseudo<InstrItinClass itin>
1051 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
1052 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1053 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
1055 // VLD1LN : Vector Load (single element to one lane)
1056 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1058 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
1059 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
1060 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
1062 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
1063 (i32 (LoadOp addrmode6:$Rn)),
1066 let DecoderMethod = "DecodeVLD1LN";
1068 class VLD1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1070 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
1071 (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane),
1072 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
1074 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
1075 (i32 (LoadOp addrmode6oneL32:$Rn)),
1078 let DecoderMethod = "DecodeVLD1LN";
1080 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
1081 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
1082 (i32 (LoadOp addrmode6:$addr)),
1086 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
1087 let Inst{7-5} = lane{2-0};
1089 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
1090 let Inst{7-6} = lane{1-0};
1091 let Inst{5-4} = Rn{5-4};
1093 def VLD1LNd32 : VLD1LN32<0b1000, {?,0,?,?}, "32", v2i32, load> {
1094 let Inst{7} = lane{0};
1095 let Inst{5-4} = Rn{5-4};
1098 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
1099 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
1100 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
1102 def : Pat<(vector_insert (v2f32 DPR:$src),
1103 (f32 (load addrmode6:$addr)), imm:$lane),
1104 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1105 def : Pat<(vector_insert (v4f32 QPR:$src),
1106 (f32 (load addrmode6:$addr)), imm:$lane),
1107 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1109 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
1111 // ...with address register writeback:
1112 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1113 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
1114 (ins addrmode6:$Rn, am6offset:$Rm,
1115 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
1116 "\\{$Vd[$lane]\\}, $Rn$Rm",
1117 "$src = $Vd, $Rn.addr = $wb", []> {
1118 let DecoderMethod = "DecodeVLD1LN";
1121 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
1122 let Inst{7-5} = lane{2-0};
1124 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
1125 let Inst{7-6} = lane{1-0};
1126 let Inst{4} = Rn{4};
1128 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
1129 let Inst{7} = lane{0};
1130 let Inst{5} = Rn{4};
1131 let Inst{4} = Rn{4};
1134 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
1135 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
1136 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
1138 // VLD2LN : Vector Load (single 2-element structure to one lane)
1139 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1140 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
1141 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
1142 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
1143 "$src1 = $Vd, $src2 = $dst2", []> {
1145 let Inst{4} = Rn{4};
1146 let DecoderMethod = "DecodeVLD2LN";
1149 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
1150 let Inst{7-5} = lane{2-0};
1152 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
1153 let Inst{7-6} = lane{1-0};
1155 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
1156 let Inst{7} = lane{0};
1159 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
1160 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
1161 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
1163 // ...with double-spaced registers:
1164 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
1165 let Inst{7-6} = lane{1-0};
1167 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
1168 let Inst{7} = lane{0};
1171 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
1172 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
1174 // ...with address register writeback:
1175 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1176 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
1177 (ins addrmode6:$Rn, am6offset:$Rm,
1178 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
1179 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
1180 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
1181 let Inst{4} = Rn{4};
1182 let DecoderMethod = "DecodeVLD2LN";
1185 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
1186 let Inst{7-5} = lane{2-0};
1188 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
1189 let Inst{7-6} = lane{1-0};
1191 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
1192 let Inst{7} = lane{0};
1195 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
1196 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
1197 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
1199 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
1200 let Inst{7-6} = lane{1-0};
1202 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
1203 let Inst{7} = lane{0};
1206 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
1207 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
1209 // VLD3LN : Vector Load (single 3-element structure to one lane)
1210 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1211 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1212 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
1213 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
1214 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
1215 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
1217 let DecoderMethod = "DecodeVLD3LN";
1220 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
1221 let Inst{7-5} = lane{2-0};
1223 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
1224 let Inst{7-6} = lane{1-0};
1226 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
1227 let Inst{7} = lane{0};
1230 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1231 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1232 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1234 // ...with double-spaced registers:
1235 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
1236 let Inst{7-6} = lane{1-0};
1238 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
1239 let Inst{7} = lane{0};
1242 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
1243 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
1245 // ...with address register writeback:
1246 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1247 : NLdStLn<1, 0b10, op11_8, op7_4,
1248 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1249 (ins addrmode6:$Rn, am6offset:$Rm,
1250 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1251 IIC_VLD3lnu, "vld3", Dt,
1252 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
1253 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
1255 let DecoderMethod = "DecodeVLD3LN";
1258 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
1259 let Inst{7-5} = lane{2-0};
1261 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
1262 let Inst{7-6} = lane{1-0};
1264 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
1265 let Inst{7} = lane{0};
1268 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1269 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1270 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1272 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
1273 let Inst{7-6} = lane{1-0};
1275 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
1276 let Inst{7} = lane{0};
1279 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
1280 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
1282 // VLD4LN : Vector Load (single 4-element structure to one lane)
1283 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1284 : NLdStLn<1, 0b10, op11_8, op7_4,
1285 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1286 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
1287 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
1288 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
1289 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
1291 let Inst{4} = Rn{4};
1292 let DecoderMethod = "DecodeVLD4LN";
1295 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
1296 let Inst{7-5} = lane{2-0};
1298 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
1299 let Inst{7-6} = lane{1-0};
1301 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
1302 let Inst{7} = lane{0};
1303 let Inst{5} = Rn{5};
1306 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1307 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1308 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1310 // ...with double-spaced registers:
1311 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
1312 let Inst{7-6} = lane{1-0};
1314 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
1315 let Inst{7} = lane{0};
1316 let Inst{5} = Rn{5};
1319 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
1320 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
1322 // ...with address register writeback:
1323 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1324 : NLdStLn<1, 0b10, op11_8, op7_4,
1325 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1326 (ins addrmode6:$Rn, am6offset:$Rm,
1327 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1328 IIC_VLD4lnu, "vld4", Dt,
1329 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
1330 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
1332 let Inst{4} = Rn{4};
1333 let DecoderMethod = "DecodeVLD4LN" ;
1336 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
1337 let Inst{7-5} = lane{2-0};
1339 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
1340 let Inst{7-6} = lane{1-0};
1342 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
1343 let Inst{7} = lane{0};
1344 let Inst{5} = Rn{5};
1347 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1348 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1349 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1351 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
1352 let Inst{7-6} = lane{1-0};
1354 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
1355 let Inst{7} = lane{0};
1356 let Inst{5} = Rn{5};
1359 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
1360 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
1362 } // mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1
1364 // VLD1DUP : Vector Load (single element to all lanes)
1365 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp,
1367 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd),
1369 IIC_VLD1dup, "vld1", Dt, "$Vd, $Rn", "",
1370 [(set VecListOneDAllLanes:$Vd,
1371 (Ty (NEONvdup (i32 (LoadOp AddrMode:$Rn)))))]> {
1373 let Inst{4} = Rn{4};
1374 let DecoderMethod = "DecodeVLD1DupInstruction";
1376 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8,
1377 addrmode6dupalignNone>;
1378 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16,
1379 addrmode6dupalign16>;
1380 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load,
1381 addrmode6dupalign32>;
1383 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1384 (VLD1DUPd32 addrmode6:$addr)>;
1386 class VLD1QDUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp,
1388 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListDPairAllLanes:$Vd),
1389 (ins AddrMode:$Rn), IIC_VLD1dup,
1390 "vld1", Dt, "$Vd, $Rn", "",
1391 [(set VecListDPairAllLanes:$Vd,
1392 (Ty (NEONvdup (i32 (LoadOp AddrMode:$Rn)))))]> {
1394 let Inst{4} = Rn{4};
1395 let DecoderMethod = "DecodeVLD1DupInstruction";
1398 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8", v16i8, extloadi8,
1399 addrmode6dupalignNone>;
1400 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16", v8i16, extloadi16,
1401 addrmode6dupalign16>;
1402 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32", v4i32, load,
1403 addrmode6dupalign32>;
1405 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1406 (VLD1DUPq32 addrmode6:$addr)>;
1408 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
1409 // ...with address register writeback:
1410 multiclass VLD1DUPWB<bits<4> op7_4, string Dt, Operand AddrMode> {
1411 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1412 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1413 (ins AddrMode:$Rn), IIC_VLD1dupu,
1414 "vld1", Dt, "$Vd, $Rn!",
1415 "$Rn.addr = $wb", []> {
1416 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1417 let Inst{4} = Rn{4};
1418 let DecoderMethod = "DecodeVLD1DupInstruction";
1420 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1421 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1422 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1423 "vld1", Dt, "$Vd, $Rn, $Rm",
1424 "$Rn.addr = $wb", []> {
1425 let Inst{4} = Rn{4};
1426 let DecoderMethod = "DecodeVLD1DupInstruction";
1429 multiclass VLD1QDUPWB<bits<4> op7_4, string Dt, Operand AddrMode> {
1430 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1431 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
1432 (ins AddrMode:$Rn), IIC_VLD1dupu,
1433 "vld1", Dt, "$Vd, $Rn!",
1434 "$Rn.addr = $wb", []> {
1435 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1436 let Inst{4} = Rn{4};
1437 let DecoderMethod = "DecodeVLD1DupInstruction";
1439 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1440 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
1441 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1442 "vld1", Dt, "$Vd, $Rn, $Rm",
1443 "$Rn.addr = $wb", []> {
1444 let Inst{4} = Rn{4};
1445 let DecoderMethod = "DecodeVLD1DupInstruction";
1449 defm VLD1DUPd8wb : VLD1DUPWB<{0,0,0,0}, "8", addrmode6dupalignNone>;
1450 defm VLD1DUPd16wb : VLD1DUPWB<{0,1,0,?}, "16", addrmode6dupalign16>;
1451 defm VLD1DUPd32wb : VLD1DUPWB<{1,0,0,?}, "32", addrmode6dupalign32>;
1453 defm VLD1DUPq8wb : VLD1QDUPWB<{0,0,1,0}, "8", addrmode6dupalignNone>;
1454 defm VLD1DUPq16wb : VLD1QDUPWB<{0,1,1,?}, "16", addrmode6dupalign16>;
1455 defm VLD1DUPq32wb : VLD1QDUPWB<{1,0,1,?}, "32", addrmode6dupalign32>;
1457 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
1458 class VLD2DUP<bits<4> op7_4, string Dt, RegisterOperand VdTy, Operand AddrMode>
1459 : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd),
1460 (ins AddrMode:$Rn), IIC_VLD2dup,
1461 "vld2", Dt, "$Vd, $Rn", "", []> {
1463 let Inst{4} = Rn{4};
1464 let DecoderMethod = "DecodeVLD2DupInstruction";
1467 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListDPairAllLanes,
1468 addrmode6dupalign16>;
1469 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes,
1470 addrmode6dupalign32>;
1471 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes,
1472 addrmode6dupalign64>;
1474 // HACK this one, VLD2DUPd8x2 must be changed at the same time with VLD2b8 or
1475 // "vld2.8 {d0[], d2[]}, [r4:32]" will become "vld2.8 {d0, d2}, [r4:32]".
1476 // ...with double-spaced registers
1477 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListDPairSpacedAllLanes,
1478 addrmode6dupalign16>;
1479 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListDPairSpacedAllLanes,
1480 addrmode6dupalign32>;
1481 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListDPairSpacedAllLanes,
1482 addrmode6dupalign64>;
1484 // ...with address register writeback:
1485 multiclass VLD2DUPWB<bits<4> op7_4, string Dt, RegisterOperand VdTy,
1487 def _fixed : NLdSt<1, 0b10, 0b1101, op7_4,
1488 (outs VdTy:$Vd, GPR:$wb),
1489 (ins AddrMode:$Rn), IIC_VLD2dupu,
1490 "vld2", Dt, "$Vd, $Rn!",
1491 "$Rn.addr = $wb", []> {
1492 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1493 let Inst{4} = Rn{4};
1494 let DecoderMethod = "DecodeVLD2DupInstruction";
1496 def _register : NLdSt<1, 0b10, 0b1101, op7_4,
1497 (outs VdTy:$Vd, GPR:$wb),
1498 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD2dupu,
1499 "vld2", Dt, "$Vd, $Rn, $Rm",
1500 "$Rn.addr = $wb", []> {
1501 let Inst{4} = Rn{4};
1502 let DecoderMethod = "DecodeVLD2DupInstruction";
1506 defm VLD2DUPd8wb : VLD2DUPWB<{0,0,0,0}, "8", VecListDPairAllLanes,
1507 addrmode6dupalign16>;
1508 defm VLD2DUPd16wb : VLD2DUPWB<{0,1,0,?}, "16", VecListDPairAllLanes,
1509 addrmode6dupalign32>;
1510 defm VLD2DUPd32wb : VLD2DUPWB<{1,0,0,?}, "32", VecListDPairAllLanes,
1511 addrmode6dupalign64>;
1513 defm VLD2DUPd8x2wb : VLD2DUPWB<{0,0,1,0}, "8", VecListDPairSpacedAllLanes,
1514 addrmode6dupalign16>;
1515 defm VLD2DUPd16x2wb : VLD2DUPWB<{0,1,1,?}, "16", VecListDPairSpacedAllLanes,
1516 addrmode6dupalign32>;
1517 defm VLD2DUPd32x2wb : VLD2DUPWB<{1,0,1,?}, "32", VecListDPairSpacedAllLanes,
1518 addrmode6dupalign64>;
1520 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
1521 class VLD3DUP<bits<4> op7_4, string Dt>
1522 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1523 (ins addrmode6dup:$Rn), IIC_VLD3dup,
1524 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
1527 let DecoderMethod = "DecodeVLD3DupInstruction";
1530 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
1531 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
1532 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
1534 def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1535 def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1536 def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1538 // ...with double-spaced registers (not used for codegen):
1539 def VLD3DUPq8 : VLD3DUP<{0,0,1,?}, "8">;
1540 def VLD3DUPq16 : VLD3DUP<{0,1,1,?}, "16">;
1541 def VLD3DUPq32 : VLD3DUP<{1,0,1,?}, "32">;
1543 // ...with address register writeback:
1544 class VLD3DUPWB<bits<4> op7_4, string Dt, Operand AddrMode>
1545 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1546 (ins AddrMode:$Rn, am6offset:$Rm), IIC_VLD3dupu,
1547 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
1548 "$Rn.addr = $wb", []> {
1550 let DecoderMethod = "DecodeVLD3DupInstruction";
1553 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8", addrmode6dupalign64>;
1554 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16", addrmode6dupalign64>;
1555 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32", addrmode6dupalign64>;
1557 def VLD3DUPq8_UPD : VLD3DUPWB<{0,0,1,0}, "8", addrmode6dupalign64>;
1558 def VLD3DUPq16_UPD : VLD3DUPWB<{0,1,1,?}, "16", addrmode6dupalign64>;
1559 def VLD3DUPq32_UPD : VLD3DUPWB<{1,0,1,?}, "32", addrmode6dupalign64>;
1561 def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1562 def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1563 def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1565 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1566 class VLD4DUP<bits<4> op7_4, string Dt>
1567 : NLdSt<1, 0b10, 0b1111, op7_4,
1568 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1569 (ins addrmode6dup:$Rn), IIC_VLD4dup,
1570 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
1572 let Inst{4} = Rn{4};
1573 let DecoderMethod = "DecodeVLD4DupInstruction";
1576 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1577 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1578 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1580 def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1581 def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1582 def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1584 // ...with double-spaced registers (not used for codegen):
1585 def VLD4DUPq8 : VLD4DUP<{0,0,1,?}, "8">;
1586 def VLD4DUPq16 : VLD4DUP<{0,1,1,?}, "16">;
1587 def VLD4DUPq32 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1589 // ...with address register writeback:
1590 class VLD4DUPWB<bits<4> op7_4, string Dt>
1591 : NLdSt<1, 0b10, 0b1111, op7_4,
1592 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1593 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
1594 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
1595 "$Rn.addr = $wb", []> {
1596 let Inst{4} = Rn{4};
1597 let DecoderMethod = "DecodeVLD4DupInstruction";
1600 def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">;
1601 def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">;
1602 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1604 def VLD4DUPq8_UPD : VLD4DUPWB<{0,0,1,0}, "8">;
1605 def VLD4DUPq16_UPD : VLD4DUPWB<{0,1,1,?}, "16">;
1606 def VLD4DUPq32_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1608 def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1609 def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1610 def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1612 } // mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1
1614 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
1616 // Classes for VST* pseudo-instructions with multi-register operands.
1617 // These are expanded to real instructions after register allocation.
1618 class VSTQPseudo<InstrItinClass itin>
1619 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1620 class VSTQWBPseudo<InstrItinClass itin>
1621 : PseudoNLdSt<(outs GPR:$wb),
1622 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1623 "$addr.addr = $wb">;
1624 class VSTQWBfixedPseudo<InstrItinClass itin>
1625 : PseudoNLdSt<(outs GPR:$wb),
1626 (ins addrmode6:$addr, QPR:$src), itin,
1627 "$addr.addr = $wb">;
1628 class VSTQWBregisterPseudo<InstrItinClass itin>
1629 : PseudoNLdSt<(outs GPR:$wb),
1630 (ins addrmode6:$addr, rGPR:$offset, QPR:$src), itin,
1631 "$addr.addr = $wb">;
1632 class VSTQQPseudo<InstrItinClass itin>
1633 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
1634 class VSTQQWBPseudo<InstrItinClass itin>
1635 : PseudoNLdSt<(outs GPR:$wb),
1636 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
1637 "$addr.addr = $wb">;
1638 class VSTQQWBfixedPseudo<InstrItinClass itin>
1639 : PseudoNLdSt<(outs GPR:$wb),
1640 (ins addrmode6:$addr, QQPR:$src), itin,
1641 "$addr.addr = $wb">;
1642 class VSTQQWBregisterPseudo<InstrItinClass itin>
1643 : PseudoNLdSt<(outs GPR:$wb),
1644 (ins addrmode6:$addr, rGPR:$offset, QQPR:$src), itin,
1645 "$addr.addr = $wb">;
1647 class VSTQQQQPseudo<InstrItinClass itin>
1648 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src), itin, "">;
1649 class VSTQQQQWBPseudo<InstrItinClass itin>
1650 : PseudoNLdSt<(outs GPR:$wb),
1651 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
1652 "$addr.addr = $wb">;
1654 // VST1 : Vector Store (multiple single elements)
1655 class VST1D<bits<4> op7_4, string Dt, Operand AddrMode>
1656 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins AddrMode:$Rn, VecListOneD:$Vd),
1657 IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []> {
1659 let Inst{4} = Rn{4};
1660 let DecoderMethod = "DecodeVLDST1Instruction";
1662 class VST1Q<bits<4> op7_4, string Dt, Operand AddrMode>
1663 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins AddrMode:$Rn, VecListDPair:$Vd),
1664 IIC_VST1x2, "vst1", Dt, "$Vd, $Rn", "", []> {
1666 let Inst{5-4} = Rn{5-4};
1667 let DecoderMethod = "DecodeVLDST1Instruction";
1670 def VST1d8 : VST1D<{0,0,0,?}, "8", addrmode6align64>;
1671 def VST1d16 : VST1D<{0,1,0,?}, "16", addrmode6align64>;
1672 def VST1d32 : VST1D<{1,0,0,?}, "32", addrmode6align64>;
1673 def VST1d64 : VST1D<{1,1,0,?}, "64", addrmode6align64>;
1675 def VST1q8 : VST1Q<{0,0,?,?}, "8", addrmode6align64or128>;
1676 def VST1q16 : VST1Q<{0,1,?,?}, "16", addrmode6align64or128>;
1677 def VST1q32 : VST1Q<{1,0,?,?}, "32", addrmode6align64or128>;
1678 def VST1q64 : VST1Q<{1,1,?,?}, "64", addrmode6align64or128>;
1680 // ...with address register writeback:
1681 multiclass VST1DWB<bits<4> op7_4, string Dt, Operand AddrMode> {
1682 def _fixed : NLdSt<0,0b00, 0b0111,op7_4, (outs GPR:$wb),
1683 (ins AddrMode:$Rn, VecListOneD:$Vd), IIC_VLD1u,
1684 "vst1", Dt, "$Vd, $Rn!",
1685 "$Rn.addr = $wb", []> {
1686 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1687 let Inst{4} = Rn{4};
1688 let DecoderMethod = "DecodeVLDST1Instruction";
1690 def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb),
1691 (ins AddrMode:$Rn, rGPR:$Rm, VecListOneD:$Vd),
1693 "vst1", Dt, "$Vd, $Rn, $Rm",
1694 "$Rn.addr = $wb", []> {
1695 let Inst{4} = Rn{4};
1696 let DecoderMethod = "DecodeVLDST1Instruction";
1699 multiclass VST1QWB<bits<4> op7_4, string Dt, Operand AddrMode> {
1700 def _fixed : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1701 (ins AddrMode:$Rn, VecListDPair:$Vd), IIC_VLD1x2u,
1702 "vst1", Dt, "$Vd, $Rn!",
1703 "$Rn.addr = $wb", []> {
1704 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1705 let Inst{5-4} = Rn{5-4};
1706 let DecoderMethod = "DecodeVLDST1Instruction";
1708 def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1709 (ins AddrMode:$Rn, rGPR:$Rm, VecListDPair:$Vd),
1711 "vst1", Dt, "$Vd, $Rn, $Rm",
1712 "$Rn.addr = $wb", []> {
1713 let Inst{5-4} = Rn{5-4};
1714 let DecoderMethod = "DecodeVLDST1Instruction";
1718 defm VST1d8wb : VST1DWB<{0,0,0,?}, "8", addrmode6align64>;
1719 defm VST1d16wb : VST1DWB<{0,1,0,?}, "16", addrmode6align64>;
1720 defm VST1d32wb : VST1DWB<{1,0,0,?}, "32", addrmode6align64>;
1721 defm VST1d64wb : VST1DWB<{1,1,0,?}, "64", addrmode6align64>;
1723 defm VST1q8wb : VST1QWB<{0,0,?,?}, "8", addrmode6align64or128>;
1724 defm VST1q16wb : VST1QWB<{0,1,?,?}, "16", addrmode6align64or128>;
1725 defm VST1q32wb : VST1QWB<{1,0,?,?}, "32", addrmode6align64or128>;
1726 defm VST1q64wb : VST1QWB<{1,1,?,?}, "64", addrmode6align64or128>;
1728 // ...with 3 registers
1729 class VST1D3<bits<4> op7_4, string Dt, Operand AddrMode>
1730 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1731 (ins AddrMode:$Rn, VecListThreeD:$Vd),
1732 IIC_VST1x3, "vst1", Dt, "$Vd, $Rn", "", []> {
1734 let Inst{4} = Rn{4};
1735 let DecoderMethod = "DecodeVLDST1Instruction";
1737 multiclass VST1D3WB<bits<4> op7_4, string Dt, Operand AddrMode> {
1738 def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1739 (ins AddrMode:$Rn, VecListThreeD:$Vd), IIC_VLD1x3u,
1740 "vst1", Dt, "$Vd, $Rn!",
1741 "$Rn.addr = $wb", []> {
1742 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1743 let Inst{5-4} = Rn{5-4};
1744 let DecoderMethod = "DecodeVLDST1Instruction";
1746 def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1747 (ins AddrMode:$Rn, rGPR:$Rm, VecListThreeD:$Vd),
1749 "vst1", Dt, "$Vd, $Rn, $Rm",
1750 "$Rn.addr = $wb", []> {
1751 let Inst{5-4} = Rn{5-4};
1752 let DecoderMethod = "DecodeVLDST1Instruction";
1756 def VST1d8T : VST1D3<{0,0,0,?}, "8", addrmode6align64>;
1757 def VST1d16T : VST1D3<{0,1,0,?}, "16", addrmode6align64>;
1758 def VST1d32T : VST1D3<{1,0,0,?}, "32", addrmode6align64>;
1759 def VST1d64T : VST1D3<{1,1,0,?}, "64", addrmode6align64>;
1761 defm VST1d8Twb : VST1D3WB<{0,0,0,?}, "8", addrmode6align64>;
1762 defm VST1d16Twb : VST1D3WB<{0,1,0,?}, "16", addrmode6align64>;
1763 defm VST1d32Twb : VST1D3WB<{1,0,0,?}, "32", addrmode6align64>;
1764 defm VST1d64Twb : VST1D3WB<{1,1,0,?}, "64", addrmode6align64>;
1766 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
1767 def VST1d64TPseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST1x3u>;
1768 def VST1d64TPseudoWB_register : VSTQQWBPseudo<IIC_VST1x3u>;
1770 // ...with 4 registers
1771 class VST1D4<bits<4> op7_4, string Dt, Operand AddrMode>
1772 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1773 (ins AddrMode:$Rn, VecListFourD:$Vd),
1774 IIC_VST1x4, "vst1", Dt, "$Vd, $Rn", "",
1777 let Inst{5-4} = Rn{5-4};
1778 let DecoderMethod = "DecodeVLDST1Instruction";
1780 multiclass VST1D4WB<bits<4> op7_4, string Dt, Operand AddrMode> {
1781 def _fixed : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1782 (ins AddrMode:$Rn, VecListFourD:$Vd), IIC_VLD1x4u,
1783 "vst1", Dt, "$Vd, $Rn!",
1784 "$Rn.addr = $wb", []> {
1785 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1786 let Inst{5-4} = Rn{5-4};
1787 let DecoderMethod = "DecodeVLDST1Instruction";
1789 def _register : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1790 (ins AddrMode:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1792 "vst1", Dt, "$Vd, $Rn, $Rm",
1793 "$Rn.addr = $wb", []> {
1794 let Inst{5-4} = Rn{5-4};
1795 let DecoderMethod = "DecodeVLDST1Instruction";
1799 def VST1d8Q : VST1D4<{0,0,?,?}, "8", addrmode6align64or128or256>;
1800 def VST1d16Q : VST1D4<{0,1,?,?}, "16", addrmode6align64or128or256>;
1801 def VST1d32Q : VST1D4<{1,0,?,?}, "32", addrmode6align64or128or256>;
1802 def VST1d64Q : VST1D4<{1,1,?,?}, "64", addrmode6align64or128or256>;
1804 defm VST1d8Qwb : VST1D4WB<{0,0,?,?}, "8", addrmode6align64or128or256>;
1805 defm VST1d16Qwb : VST1D4WB<{0,1,?,?}, "16", addrmode6align64or128or256>;
1806 defm VST1d32Qwb : VST1D4WB<{1,0,?,?}, "32", addrmode6align64or128or256>;
1807 defm VST1d64Qwb : VST1D4WB<{1,1,?,?}, "64", addrmode6align64or128or256>;
1809 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
1810 def VST1d64QPseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST1x4u>;
1811 def VST1d64QPseudoWB_register : VSTQQWBPseudo<IIC_VST1x4u>;
1813 // VST2 : Vector Store (multiple 2-element structures)
1814 class VST2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
1815 InstrItinClass itin, Operand AddrMode>
1816 : NLdSt<0, 0b00, op11_8, op7_4, (outs), (ins AddrMode:$Rn, VdTy:$Vd),
1817 itin, "vst2", Dt, "$Vd, $Rn", "", []> {
1819 let Inst{5-4} = Rn{5-4};
1820 let DecoderMethod = "DecodeVLDST2Instruction";
1823 def VST2d8 : VST2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VST2,
1824 addrmode6align64or128>;
1825 def VST2d16 : VST2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VST2,
1826 addrmode6align64or128>;
1827 def VST2d32 : VST2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VST2,
1828 addrmode6align64or128>;
1830 def VST2q8 : VST2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VST2x2,
1831 addrmode6align64or128or256>;
1832 def VST2q16 : VST2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VST2x2,
1833 addrmode6align64or128or256>;
1834 def VST2q32 : VST2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VST2x2,
1835 addrmode6align64or128or256>;
1837 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
1838 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
1839 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
1841 // ...with address register writeback:
1842 multiclass VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt,
1843 RegisterOperand VdTy, Operand AddrMode> {
1844 def _fixed : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1845 (ins AddrMode:$Rn, VdTy:$Vd), IIC_VLD1u,
1846 "vst2", Dt, "$Vd, $Rn!",
1847 "$Rn.addr = $wb", []> {
1848 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1849 let Inst{5-4} = Rn{5-4};
1850 let DecoderMethod = "DecodeVLDST2Instruction";
1852 def _register : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1853 (ins AddrMode:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u,
1854 "vst2", Dt, "$Vd, $Rn, $Rm",
1855 "$Rn.addr = $wb", []> {
1856 let Inst{5-4} = Rn{5-4};
1857 let DecoderMethod = "DecodeVLDST2Instruction";
1860 multiclass VST2QWB<bits<4> op7_4, string Dt, Operand AddrMode> {
1861 def _fixed : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1862 (ins AddrMode:$Rn, VecListFourD:$Vd), IIC_VLD1u,
1863 "vst2", Dt, "$Vd, $Rn!",
1864 "$Rn.addr = $wb", []> {
1865 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1866 let Inst{5-4} = Rn{5-4};
1867 let DecoderMethod = "DecodeVLDST2Instruction";
1869 def _register : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1870 (ins AddrMode:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1872 "vst2", Dt, "$Vd, $Rn, $Rm",
1873 "$Rn.addr = $wb", []> {
1874 let Inst{5-4} = Rn{5-4};
1875 let DecoderMethod = "DecodeVLDST2Instruction";
1879 defm VST2d8wb : VST2DWB<0b1000, {0,0,?,?}, "8", VecListDPair,
1880 addrmode6align64or128>;
1881 defm VST2d16wb : VST2DWB<0b1000, {0,1,?,?}, "16", VecListDPair,
1882 addrmode6align64or128>;
1883 defm VST2d32wb : VST2DWB<0b1000, {1,0,?,?}, "32", VecListDPair,
1884 addrmode6align64or128>;
1886 defm VST2q8wb : VST2QWB<{0,0,?,?}, "8", addrmode6align64or128or256>;
1887 defm VST2q16wb : VST2QWB<{0,1,?,?}, "16", addrmode6align64or128or256>;
1888 defm VST2q32wb : VST2QWB<{1,0,?,?}, "32", addrmode6align64or128or256>;
1890 def VST2q8PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1891 def VST2q16PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1892 def VST2q32PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1893 def VST2q8PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1894 def VST2q16PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1895 def VST2q32PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1897 // ...with double-spaced registers
1898 def VST2b8 : VST2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VST2,
1899 addrmode6align64or128>;
1900 def VST2b16 : VST2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VST2,
1901 addrmode6align64or128>;
1902 def VST2b32 : VST2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VST2,
1903 addrmode6align64or128>;
1904 defm VST2b8wb : VST2DWB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced,
1905 addrmode6align64or128>;
1906 defm VST2b16wb : VST2DWB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced,
1907 addrmode6align64or128>;
1908 defm VST2b32wb : VST2DWB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced,
1909 addrmode6align64or128>;
1911 // VST3 : Vector Store (multiple 3-element structures)
1912 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1913 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1914 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1915 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1917 let Inst{4} = Rn{4};
1918 let DecoderMethod = "DecodeVLDST3Instruction";
1921 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1922 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1923 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
1925 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1926 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1927 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
1929 // ...with address register writeback:
1930 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1931 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1932 (ins addrmode6:$Rn, am6offset:$Rm,
1933 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1934 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1935 "$Rn.addr = $wb", []> {
1936 let Inst{4} = Rn{4};
1937 let DecoderMethod = "DecodeVLDST3Instruction";
1940 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1941 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1942 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
1944 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1945 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1946 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1948 // ...with double-spaced registers:
1949 def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1950 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1951 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1952 def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1953 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1954 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
1956 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1957 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1958 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1960 // ...alternate versions to be allocated odd register numbers:
1961 def VST3q8oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1962 def VST3q16oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1963 def VST3q32oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1965 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1966 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1967 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1969 // VST4 : Vector Store (multiple 4-element structures)
1970 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1971 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1972 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1973 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1976 let Inst{5-4} = Rn{5-4};
1977 let DecoderMethod = "DecodeVLDST4Instruction";
1980 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1981 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1982 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
1984 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1985 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1986 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
1988 // ...with address register writeback:
1989 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1990 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1991 (ins addrmode6:$Rn, am6offset:$Rm,
1992 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1993 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1994 "$Rn.addr = $wb", []> {
1995 let Inst{5-4} = Rn{5-4};
1996 let DecoderMethod = "DecodeVLDST4Instruction";
1999 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
2000 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
2001 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
2003 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
2004 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
2005 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
2007 // ...with double-spaced registers:
2008 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
2009 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
2010 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
2011 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
2012 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
2013 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
2015 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
2016 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
2017 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
2019 // ...alternate versions to be allocated odd register numbers:
2020 def VST4q8oddPseudo : VSTQQQQPseudo<IIC_VST4>;
2021 def VST4q16oddPseudo : VSTQQQQPseudo<IIC_VST4>;
2022 def VST4q32oddPseudo : VSTQQQQPseudo<IIC_VST4>;
2024 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
2025 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
2026 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
2028 } // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1
2030 // Classes for VST*LN pseudo-instructions with multi-register operands.
2031 // These are expanded to real instructions after register allocation.
2032 class VSTQLNPseudo<InstrItinClass itin>
2033 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
2035 class VSTQLNWBPseudo<InstrItinClass itin>
2036 : PseudoNLdSt<(outs GPR:$wb),
2037 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
2038 nohash_imm:$lane), itin, "$addr.addr = $wb">;
2039 class VSTQQLNPseudo<InstrItinClass itin>
2040 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
2042 class VSTQQLNWBPseudo<InstrItinClass itin>
2043 : PseudoNLdSt<(outs GPR:$wb),
2044 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
2045 nohash_imm:$lane), itin, "$addr.addr = $wb">;
2046 class VSTQQQQLNPseudo<InstrItinClass itin>
2047 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
2049 class VSTQQQQLNWBPseudo<InstrItinClass itin>
2050 : PseudoNLdSt<(outs GPR:$wb),
2051 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
2052 nohash_imm:$lane), itin, "$addr.addr = $wb">;
2054 // VST1LN : Vector Store (single element from one lane)
2055 class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
2056 PatFrag StoreOp, SDNode ExtractOp, Operand AddrMode>
2057 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2058 (ins AddrMode:$Rn, DPR:$Vd, nohash_imm:$lane),
2059 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
2060 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), AddrMode:$Rn)]> {
2062 let DecoderMethod = "DecodeVST1LN";
2064 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
2065 : VSTQLNPseudo<IIC_VST1ln> {
2066 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
2070 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
2071 NEONvgetlaneu, addrmode6> {
2072 let Inst{7-5} = lane{2-0};
2074 def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
2075 NEONvgetlaneu, addrmode6> {
2076 let Inst{7-6} = lane{1-0};
2077 let Inst{4} = Rn{4};
2080 def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt,
2082 let Inst{7} = lane{0};
2083 let Inst{5-4} = Rn{5-4};
2086 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
2087 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
2088 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
2090 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
2091 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
2092 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
2093 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
2095 // ...with address register writeback:
2096 class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
2097 PatFrag StoreOp, SDNode ExtractOp, Operand AdrMode>
2098 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2099 (ins AdrMode:$Rn, am6offset:$Rm,
2100 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
2101 "\\{$Vd[$lane]\\}, $Rn$Rm",
2103 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
2104 AdrMode:$Rn, am6offset:$Rm))]> {
2105 let DecoderMethod = "DecodeVST1LN";
2107 class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
2108 : VSTQLNWBPseudo<IIC_VST1lnu> {
2109 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
2110 addrmode6:$addr, am6offset:$offset))];
2113 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8,
2114 NEONvgetlaneu, addrmode6> {
2115 let Inst{7-5} = lane{2-0};
2117 def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16", v4i16, post_truncsti16,
2118 NEONvgetlaneu, addrmode6> {
2119 let Inst{7-6} = lane{1-0};
2120 let Inst{4} = Rn{4};
2122 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32", v2i32, post_store,
2123 extractelt, addrmode6oneL32> {
2124 let Inst{7} = lane{0};
2125 let Inst{5-4} = Rn{5-4};
2128 def VST1LNq8Pseudo_UPD : VST1QLNWBPseudo<v16i8, post_truncsti8, NEONvgetlaneu>;
2129 def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,NEONvgetlaneu>;
2130 def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
2132 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
2134 // VST2LN : Vector Store (single 2-element structure from one lane)
2135 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2136 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2137 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
2138 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
2141 let Inst{4} = Rn{4};
2142 let DecoderMethod = "DecodeVST2LN";
2145 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
2146 let Inst{7-5} = lane{2-0};
2148 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
2149 let Inst{7-6} = lane{1-0};
2151 def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
2152 let Inst{7} = lane{0};
2155 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
2156 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
2157 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
2159 // ...with double-spaced registers:
2160 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
2161 let Inst{7-6} = lane{1-0};
2162 let Inst{4} = Rn{4};
2164 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
2165 let Inst{7} = lane{0};
2166 let Inst{4} = Rn{4};
2169 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
2170 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
2172 // ...with address register writeback:
2173 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2174 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2175 (ins addrmode6:$Rn, am6offset:$Rm,
2176 DPR:$Vd, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
2177 "\\{$Vd[$lane], $src2[$lane]\\}, $Rn$Rm",
2178 "$Rn.addr = $wb", []> {
2179 let Inst{4} = Rn{4};
2180 let DecoderMethod = "DecodeVST2LN";
2183 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
2184 let Inst{7-5} = lane{2-0};
2186 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
2187 let Inst{7-6} = lane{1-0};
2189 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
2190 let Inst{7} = lane{0};
2193 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2194 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2195 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2197 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
2198 let Inst{7-6} = lane{1-0};
2200 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
2201 let Inst{7} = lane{0};
2204 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
2205 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
2207 // VST3LN : Vector Store (single 3-element structure from one lane)
2208 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2209 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2210 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
2211 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
2212 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
2214 let DecoderMethod = "DecodeVST3LN";
2217 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
2218 let Inst{7-5} = lane{2-0};
2220 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
2221 let Inst{7-6} = lane{1-0};
2223 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
2224 let Inst{7} = lane{0};
2227 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2228 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2229 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2231 // ...with double-spaced registers:
2232 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
2233 let Inst{7-6} = lane{1-0};
2235 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
2236 let Inst{7} = lane{0};
2239 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
2240 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
2242 // ...with address register writeback:
2243 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2244 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2245 (ins addrmode6:$Rn, am6offset:$Rm,
2246 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
2247 IIC_VST3lnu, "vst3", Dt,
2248 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
2249 "$Rn.addr = $wb", []> {
2250 let DecoderMethod = "DecodeVST3LN";
2253 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
2254 let Inst{7-5} = lane{2-0};
2256 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
2257 let Inst{7-6} = lane{1-0};
2259 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
2260 let Inst{7} = lane{0};
2263 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2264 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2265 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2267 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
2268 let Inst{7-6} = lane{1-0};
2270 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
2271 let Inst{7} = lane{0};
2274 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
2275 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
2277 // VST4LN : Vector Store (single 4-element structure from one lane)
2278 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2279 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2280 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
2281 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
2282 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
2285 let Inst{4} = Rn{4};
2286 let DecoderMethod = "DecodeVST4LN";
2289 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
2290 let Inst{7-5} = lane{2-0};
2292 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
2293 let Inst{7-6} = lane{1-0};
2295 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
2296 let Inst{7} = lane{0};
2297 let Inst{5} = Rn{5};
2300 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2301 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2302 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2304 // ...with double-spaced registers:
2305 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
2306 let Inst{7-6} = lane{1-0};
2308 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
2309 let Inst{7} = lane{0};
2310 let Inst{5} = Rn{5};
2313 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
2314 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
2316 // ...with address register writeback:
2317 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2318 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2319 (ins addrmode6:$Rn, am6offset:$Rm,
2320 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
2321 IIC_VST4lnu, "vst4", Dt,
2322 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
2323 "$Rn.addr = $wb", []> {
2324 let Inst{4} = Rn{4};
2325 let DecoderMethod = "DecodeVST4LN";
2328 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
2329 let Inst{7-5} = lane{2-0};
2331 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
2332 let Inst{7-6} = lane{1-0};
2334 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
2335 let Inst{7} = lane{0};
2336 let Inst{5} = Rn{5};
2339 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2340 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2341 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2343 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
2344 let Inst{7-6} = lane{1-0};
2346 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
2347 let Inst{7} = lane{0};
2348 let Inst{5} = Rn{5};
2351 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
2352 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
2354 } // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1
2356 // Use vld1/vst1 for unaligned f64 load / store
2357 def : Pat<(f64 (hword_alignedload addrmode6:$addr)),
2358 (VLD1d16 addrmode6:$addr)>, Requires<[IsLE]>;
2359 def : Pat<(hword_alignedstore (f64 DPR:$value), addrmode6:$addr),
2360 (VST1d16 addrmode6:$addr, DPR:$value)>, Requires<[IsLE]>;
2361 def : Pat<(f64 (byte_alignedload addrmode6:$addr)),
2362 (VLD1d8 addrmode6:$addr)>, Requires<[IsLE]>;
2363 def : Pat<(byte_alignedstore (f64 DPR:$value), addrmode6:$addr),
2364 (VST1d8 addrmode6:$addr, DPR:$value)>, Requires<[IsLE]>;
2365 def : Pat<(f64 (non_word_alignedload addrmode6:$addr)),
2366 (VLD1d64 addrmode6:$addr)>, Requires<[IsBE]>;
2367 def : Pat<(non_word_alignedstore (f64 DPR:$value), addrmode6:$addr),
2368 (VST1d64 addrmode6:$addr, DPR:$value)>, Requires<[IsBE]>;
2370 // Use vld1/vst1 for Q and QQ. Also use them for unaligned v2f64
2371 // load / store if it's legal.
2372 def : Pat<(v2f64 (dword_alignedload addrmode6:$addr)),
2373 (VLD1q64 addrmode6:$addr)>;
2374 def : Pat<(dword_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2375 (VST1q64 addrmode6:$addr, QPR:$value)>;
2376 def : Pat<(v2f64 (word_alignedload addrmode6:$addr)),
2377 (VLD1q32 addrmode6:$addr)>, Requires<[IsLE]>;
2378 def : Pat<(word_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2379 (VST1q32 addrmode6:$addr, QPR:$value)>, Requires<[IsLE]>;
2380 def : Pat<(v2f64 (hword_alignedload addrmode6:$addr)),
2381 (VLD1q16 addrmode6:$addr)>, Requires<[IsLE]>;
2382 def : Pat<(hword_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2383 (VST1q16 addrmode6:$addr, QPR:$value)>, Requires<[IsLE]>;
2384 def : Pat<(v2f64 (byte_alignedload addrmode6:$addr)),
2385 (VLD1q8 addrmode6:$addr)>, Requires<[IsLE]>;
2386 def : Pat<(byte_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2387 (VST1q8 addrmode6:$addr, QPR:$value)>, Requires<[IsLE]>;
2389 //===----------------------------------------------------------------------===//
2390 // NEON pattern fragments
2391 //===----------------------------------------------------------------------===//
2393 // Extract D sub-registers of Q registers.
2394 def DSubReg_i8_reg : SDNodeXForm<imm, [{
2395 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2396 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, SDLoc(N),
2399 def DSubReg_i16_reg : SDNodeXForm<imm, [{
2400 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2401 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, SDLoc(N),
2404 def DSubReg_i32_reg : SDNodeXForm<imm, [{
2405 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2406 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, SDLoc(N),
2409 def DSubReg_f64_reg : SDNodeXForm<imm, [{
2410 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2411 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), SDLoc(N),
2415 // Extract S sub-registers of Q/D registers.
2416 def SSubReg_f32_reg : SDNodeXForm<imm, [{
2417 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
2418 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), SDLoc(N),
2422 // Translate lane numbers from Q registers to D subregs.
2423 def SubReg_i8_lane : SDNodeXForm<imm, [{
2424 return CurDAG->getTargetConstant(N->getZExtValue() & 7, SDLoc(N), MVT::i32);
2426 def SubReg_i16_lane : SDNodeXForm<imm, [{
2427 return CurDAG->getTargetConstant(N->getZExtValue() & 3, SDLoc(N), MVT::i32);
2429 def SubReg_i32_lane : SDNodeXForm<imm, [{
2430 return CurDAG->getTargetConstant(N->getZExtValue() & 1, SDLoc(N), MVT::i32);
2433 //===----------------------------------------------------------------------===//
2434 // Instruction Classes
2435 //===----------------------------------------------------------------------===//
2437 // Basic 2-register operations: double- and quad-register.
2438 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2439 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
2440 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2441 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2442 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
2443 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
2444 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2445 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
2446 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2447 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2448 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
2449 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
2451 // Basic 2-register intrinsics, both double- and quad-register.
2452 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2453 bits<2> op17_16, bits<5> op11_7, bit op4,
2454 InstrItinClass itin, string OpcodeStr, string Dt,
2455 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2456 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2457 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2458 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2459 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2460 bits<2> op17_16, bits<5> op11_7, bit op4,
2461 InstrItinClass itin, string OpcodeStr, string Dt,
2462 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2463 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2464 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2465 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2467 // Same as above, but not predicated.
2468 class N2VDIntnp<bits<2> op17_16, bits<3> op10_8, bit op7,
2469 InstrItinClass itin, string OpcodeStr, string Dt,
2470 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2471 : N2Vnp<0b10, op17_16, op10_8, op7, 0, (outs DPR:$Vd), (ins DPR:$Vm),
2472 itin, OpcodeStr, Dt,
2473 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2475 class N2VQIntnp<bits<2> op17_16, bits<3> op10_8, bit op7,
2476 InstrItinClass itin, string OpcodeStr, string Dt,
2477 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2478 : N2Vnp<0b10, op17_16, op10_8, op7, 1, (outs QPR:$Vd), (ins QPR:$Vm),
2479 itin, OpcodeStr, Dt,
2480 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2482 // Similar to NV2VQIntnp with some more encoding bits exposed (crypto).
2483 class N2VQIntXnp<bits<2> op19_18, bits<2> op17_16, bits<3> op10_8, bit op6,
2484 bit op7, InstrItinClass itin, string OpcodeStr, string Dt,
2485 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2486 : N2Vnp<op19_18, op17_16, op10_8, op7, op6, (outs QPR:$Vd), (ins QPR:$Vm),
2487 itin, OpcodeStr, Dt,
2488 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2490 // Same as N2VQIntXnp but with Vd as a src register.
2491 class N2VQIntX2np<bits<2> op19_18, bits<2> op17_16, bits<3> op10_8, bit op6,
2492 bit op7, InstrItinClass itin, string OpcodeStr, string Dt,
2493 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2494 : N2Vnp<op19_18, op17_16, op10_8, op7, op6,
2495 (outs QPR:$Vd), (ins QPR:$src, QPR:$Vm),
2496 itin, OpcodeStr, Dt,
2497 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vm))))]> {
2498 let Constraints = "$src = $Vd";
2501 // Narrow 2-register operations.
2502 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2503 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2504 InstrItinClass itin, string OpcodeStr, string Dt,
2505 ValueType TyD, ValueType TyQ, SDNode OpNode>
2506 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2507 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2508 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
2510 // Narrow 2-register intrinsics.
2511 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2512 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2513 InstrItinClass itin, string OpcodeStr, string Dt,
2514 ValueType TyD, ValueType TyQ, SDPatternOperator IntOp>
2515 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2516 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2517 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
2519 // Long 2-register operations (currently only used for VMOVL).
2520 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2521 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2522 InstrItinClass itin, string OpcodeStr, string Dt,
2523 ValueType TyQ, ValueType TyD, SDNode OpNode>
2524 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2525 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2526 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
2528 // Long 2-register intrinsics.
2529 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2530 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2531 InstrItinClass itin, string OpcodeStr, string Dt,
2532 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp>
2533 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2534 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2535 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
2537 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
2538 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
2539 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
2540 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
2541 OpcodeStr, Dt, "$Vd, $Vm",
2542 "$src1 = $Vd, $src2 = $Vm", []>;
2543 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
2544 InstrItinClass itin, string OpcodeStr, string Dt>
2545 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
2546 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
2547 "$src1 = $Vd, $src2 = $Vm", []>;
2549 // Basic 3-register operations: double- and quad-register.
2550 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2551 InstrItinClass itin, string OpcodeStr, string Dt,
2552 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2553 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2554 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2555 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2556 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2557 // All of these have a two-operand InstAlias.
2558 let TwoOperandAliasConstraint = "$Vn = $Vd";
2559 let isCommutable = Commutable;
2561 // Same as N3VD but no data type.
2562 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2563 InstrItinClass itin, string OpcodeStr,
2564 ValueType ResTy, ValueType OpTy,
2565 SDNode OpNode, bit Commutable>
2566 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
2567 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2568 OpcodeStr, "$Vd, $Vn, $Vm", "",
2569 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
2570 // All of these have a two-operand InstAlias.
2571 let TwoOperandAliasConstraint = "$Vn = $Vd";
2572 let isCommutable = Commutable;
2575 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
2576 InstrItinClass itin, string OpcodeStr, string Dt,
2577 ValueType Ty, SDNode ShOp>
2578 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2579 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2580 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2582 (Ty (ShOp (Ty DPR:$Vn),
2583 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
2584 // All of these have a two-operand InstAlias.
2585 let TwoOperandAliasConstraint = "$Vn = $Vd";
2586 let isCommutable = 0;
2588 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
2589 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2590 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2591 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2592 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane","",
2594 (Ty (ShOp (Ty DPR:$Vn),
2595 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2596 // All of these have a two-operand InstAlias.
2597 let TwoOperandAliasConstraint = "$Vn = $Vd";
2598 let isCommutable = 0;
2601 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2602 InstrItinClass itin, string OpcodeStr, string Dt,
2603 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2604 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2605 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2606 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2607 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2608 // All of these have a two-operand InstAlias.
2609 let TwoOperandAliasConstraint = "$Vn = $Vd";
2610 let isCommutable = Commutable;
2612 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2613 InstrItinClass itin, string OpcodeStr,
2614 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2615 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
2616 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2617 OpcodeStr, "$Vd, $Vn, $Vm", "",
2618 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
2619 // All of these have a two-operand InstAlias.
2620 let TwoOperandAliasConstraint = "$Vn = $Vd";
2621 let isCommutable = Commutable;
2623 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
2624 InstrItinClass itin, string OpcodeStr, string Dt,
2625 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2626 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2627 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2628 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2629 [(set (ResTy QPR:$Vd),
2630 (ResTy (ShOp (ResTy QPR:$Vn),
2631 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2633 // All of these have a two-operand InstAlias.
2634 let TwoOperandAliasConstraint = "$Vn = $Vd";
2635 let isCommutable = 0;
2637 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
2638 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2639 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2640 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2641 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane", "",
2642 [(set (ResTy QPR:$Vd),
2643 (ResTy (ShOp (ResTy QPR:$Vn),
2644 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2646 // All of these have a two-operand InstAlias.
2647 let TwoOperandAliasConstraint = "$Vn = $Vd";
2648 let isCommutable = 0;
2651 // Basic 3-register intrinsics, both double- and quad-register.
2652 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2653 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2654 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp, bit Commutable>
2655 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2656 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
2657 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2658 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2659 // All of these have a two-operand InstAlias.
2660 let TwoOperandAliasConstraint = "$Vn = $Vd";
2661 let isCommutable = Commutable;
2664 class N3VDIntnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2665 bit op4, Format f, InstrItinClass itin, string OpcodeStr,
2666 string Dt, ValueType ResTy, ValueType OpTy,
2667 SDPatternOperator IntOp, bit Commutable>
2668 : N3Vnp<op27_23, op21_20, op11_8, op6, op4,
2669 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, OpcodeStr, Dt,
2670 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2672 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2673 string OpcodeStr, string Dt, ValueType Ty, SDPatternOperator IntOp>
2674 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2675 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2676 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2678 (Ty (IntOp (Ty DPR:$Vn),
2679 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2681 let isCommutable = 0;
2684 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2685 string OpcodeStr, string Dt, ValueType Ty, SDPatternOperator IntOp>
2686 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2687 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2688 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2690 (Ty (IntOp (Ty DPR:$Vn),
2691 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2692 let isCommutable = 0;
2694 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2695 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2696 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2697 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2698 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
2699 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2700 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
2701 let TwoOperandAliasConstraint = "$Vm = $Vd";
2702 let isCommutable = 0;
2705 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2706 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2707 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp, bit Commutable>
2708 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2709 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
2710 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2711 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2712 // All of these have a two-operand InstAlias.
2713 let TwoOperandAliasConstraint = "$Vn = $Vd";
2714 let isCommutable = Commutable;
2717 class N3VQIntnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2718 bit op4, Format f, InstrItinClass itin, string OpcodeStr,
2719 string Dt, ValueType ResTy, ValueType OpTy,
2720 SDPatternOperator IntOp, bit Commutable>
2721 : N3Vnp<op27_23, op21_20, op11_8, op6, op4,
2722 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin, OpcodeStr, Dt,
2723 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2725 // Same as N3VQIntnp but with Vd as a src register.
2726 class N3VQInt3np<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2727 bit op4, Format f, InstrItinClass itin, string OpcodeStr,
2728 string Dt, ValueType ResTy, ValueType OpTy,
2729 SDPatternOperator IntOp, bit Commutable>
2730 : N3Vnp<op27_23, op21_20, op11_8, op6, op4,
2731 (outs QPR:$Vd), (ins QPR:$src, QPR:$Vn, QPR:$Vm),
2732 f, itin, OpcodeStr, Dt,
2733 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vn),
2734 (OpTy QPR:$Vm))))]> {
2735 let Constraints = "$src = $Vd";
2738 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2739 string OpcodeStr, string Dt,
2740 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2741 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2742 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2743 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2744 [(set (ResTy QPR:$Vd),
2745 (ResTy (IntOp (ResTy QPR:$Vn),
2746 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2748 let isCommutable = 0;
2750 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2751 string OpcodeStr, string Dt,
2752 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2753 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2754 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2755 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2756 [(set (ResTy QPR:$Vd),
2757 (ResTy (IntOp (ResTy QPR:$Vn),
2758 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2760 let isCommutable = 0;
2762 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2763 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2764 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2765 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2766 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
2767 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2768 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
2769 let TwoOperandAliasConstraint = "$Vm = $Vd";
2770 let isCommutable = 0;
2773 // Multiply-Add/Sub operations: double- and quad-register.
2774 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2775 InstrItinClass itin, string OpcodeStr, string Dt,
2776 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode>
2777 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2778 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2779 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2780 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2781 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
2783 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2784 string OpcodeStr, string Dt,
2785 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
2786 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2788 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2790 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2792 (Ty (ShOp (Ty DPR:$src1),
2794 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2796 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2797 string OpcodeStr, string Dt,
2798 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
2799 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2801 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2803 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2805 (Ty (ShOp (Ty DPR:$src1),
2807 (Ty (NEONvduplane (Ty DPR_8:$Vm),
2810 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2811 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
2812 SDPatternOperator MulOp, SDPatternOperator OpNode>
2813 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2814 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2815 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2816 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2817 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
2818 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2819 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2820 SDPatternOperator MulOp, SDPatternOperator ShOp>
2821 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2823 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2825 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2826 [(set (ResTy QPR:$Vd),
2827 (ResTy (ShOp (ResTy QPR:$src1),
2828 (ResTy (MulOp QPR:$Vn,
2829 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2831 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2832 string OpcodeStr, string Dt,
2833 ValueType ResTy, ValueType OpTy,
2834 SDPatternOperator MulOp, SDPatternOperator ShOp>
2835 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2837 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2839 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2840 [(set (ResTy QPR:$Vd),
2841 (ResTy (ShOp (ResTy QPR:$src1),
2842 (ResTy (MulOp QPR:$Vn,
2843 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2846 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
2847 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2848 InstrItinClass itin, string OpcodeStr, string Dt,
2849 ValueType Ty, SDPatternOperator IntOp, SDNode OpNode>
2850 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2851 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2852 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2853 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2854 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
2855 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2856 InstrItinClass itin, string OpcodeStr, string Dt,
2857 ValueType Ty, SDPatternOperator IntOp, SDNode OpNode>
2858 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2859 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2860 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2861 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2862 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2864 // Neon 3-argument intrinsics, both double- and quad-register.
2865 // The destination register is also used as the first source operand register.
2866 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2867 InstrItinClass itin, string OpcodeStr, string Dt,
2868 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2869 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2870 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2871 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2872 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2873 (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2874 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2875 InstrItinClass itin, string OpcodeStr, string Dt,
2876 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2877 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2878 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2879 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2880 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2881 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2883 // Long Multiply-Add/Sub operations.
2884 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2885 InstrItinClass itin, string OpcodeStr, string Dt,
2886 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2887 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2888 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2889 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2890 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2891 (TyQ (MulOp (TyD DPR:$Vn),
2892 (TyD DPR:$Vm)))))]>;
2893 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2894 InstrItinClass itin, string OpcodeStr, string Dt,
2895 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2896 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2897 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2899 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2901 (OpNode (TyQ QPR:$src1),
2902 (TyQ (MulOp (TyD DPR:$Vn),
2903 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),
2905 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2906 InstrItinClass itin, string OpcodeStr, string Dt,
2907 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2908 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2909 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2911 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2913 (OpNode (TyQ QPR:$src1),
2914 (TyQ (MulOp (TyD DPR:$Vn),
2915 (TyD (NEONvduplane (TyD DPR_8:$Vm),
2918 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
2919 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2920 InstrItinClass itin, string OpcodeStr, string Dt,
2921 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp,
2923 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2924 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2925 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2926 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2927 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2928 (TyD DPR:$Vm)))))))]>;
2930 // Neon Long 3-argument intrinsic. The destination register is
2931 // a quad-register and is also used as the first source operand register.
2932 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2933 InstrItinClass itin, string OpcodeStr, string Dt,
2934 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp>
2935 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2936 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2937 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2939 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2940 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2941 string OpcodeStr, string Dt,
2942 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2943 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2945 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2947 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2948 [(set (ResTy QPR:$Vd),
2949 (ResTy (IntOp (ResTy QPR:$src1),
2951 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2953 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2954 InstrItinClass itin, string OpcodeStr, string Dt,
2955 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2956 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2958 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2960 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2961 [(set (ResTy QPR:$Vd),
2962 (ResTy (IntOp (ResTy QPR:$src1),
2964 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2967 // Narrowing 3-register intrinsics.
2968 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2969 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
2970 SDPatternOperator IntOp, bit Commutable>
2971 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2972 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2973 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2974 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2975 let isCommutable = Commutable;
2978 // Long 3-register operations.
2979 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2980 InstrItinClass itin, string OpcodeStr, string Dt,
2981 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
2982 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2983 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2984 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2985 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2986 let isCommutable = Commutable;
2989 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2990 InstrItinClass itin, string OpcodeStr, string Dt,
2991 ValueType TyQ, ValueType TyD, SDNode OpNode>
2992 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2993 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2994 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2996 (TyQ (OpNode (TyD DPR:$Vn),
2997 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
2998 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2999 InstrItinClass itin, string OpcodeStr, string Dt,
3000 ValueType TyQ, ValueType TyD, SDNode OpNode>
3001 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
3002 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
3003 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3005 (TyQ (OpNode (TyD DPR:$Vn),
3006 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
3008 // Long 3-register operations with explicitly extended operands.
3009 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
3010 InstrItinClass itin, string OpcodeStr, string Dt,
3011 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
3013 : N3V<op24, op23, op21_20, op11_8, 0, op4,
3014 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3015 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3016 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
3017 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
3018 let isCommutable = Commutable;
3021 // Long 3-register intrinsics with explicit extend (VABDL).
3022 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
3023 InstrItinClass itin, string OpcodeStr, string Dt,
3024 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp,
3026 : N3V<op24, op23, op21_20, op11_8, 0, op4,
3027 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3028 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3029 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
3030 (TyD DPR:$Vm))))))]> {
3031 let isCommutable = Commutable;
3034 // Long 3-register intrinsics.
3035 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
3036 InstrItinClass itin, string OpcodeStr, string Dt,
3037 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, bit Commutable>
3038 : N3V<op24, op23, op21_20, op11_8, 0, op4,
3039 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3040 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3041 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
3042 let isCommutable = Commutable;
3045 // Same as above, but not predicated.
3046 class N3VLIntnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
3047 bit op4, InstrItinClass itin, string OpcodeStr,
3048 string Dt, ValueType ResTy, ValueType OpTy,
3049 SDPatternOperator IntOp, bit Commutable>
3050 : N3Vnp<op27_23, op21_20, op11_8, op6, op4,
3051 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, OpcodeStr, Dt,
3052 [(set QPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
3054 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
3055 string OpcodeStr, string Dt,
3056 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
3057 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
3058 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
3059 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3060 [(set (ResTy QPR:$Vd),
3061 (ResTy (IntOp (OpTy DPR:$Vn),
3062 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
3064 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
3065 InstrItinClass itin, string OpcodeStr, string Dt,
3066 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
3067 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
3068 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
3069 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3070 [(set (ResTy QPR:$Vd),
3071 (ResTy (IntOp (OpTy DPR:$Vn),
3072 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
3075 // Wide 3-register operations.
3076 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
3077 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
3078 SDNode OpNode, SDNode ExtOp, bit Commutable>
3079 : N3V<op24, op23, op21_20, op11_8, 0, op4,
3080 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
3081 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3082 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
3083 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
3084 // All of these have a two-operand InstAlias.
3085 let TwoOperandAliasConstraint = "$Vn = $Vd";
3086 let isCommutable = Commutable;
3089 // Pairwise long 2-register intrinsics, both double- and quad-register.
3090 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
3091 bits<2> op17_16, bits<5> op11_7, bit op4,
3092 string OpcodeStr, string Dt,
3093 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
3094 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
3095 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
3096 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
3097 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
3098 bits<2> op17_16, bits<5> op11_7, bit op4,
3099 string OpcodeStr, string Dt,
3100 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
3101 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
3102 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
3103 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
3105 // Pairwise long 2-register accumulate intrinsics,
3106 // both double- and quad-register.
3107 // The destination register is also used as the first source operand register.
3108 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
3109 bits<2> op17_16, bits<5> op11_7, bit op4,
3110 string OpcodeStr, string Dt,
3111 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
3112 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
3113 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
3114 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
3115 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
3116 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
3117 bits<2> op17_16, bits<5> op11_7, bit op4,
3118 string OpcodeStr, string Dt,
3119 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
3120 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
3121 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
3122 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
3123 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
3125 // Shift by immediate,
3126 // both double- and quad-register.
3127 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3128 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3129 Format f, InstrItinClass itin, Operand ImmTy,
3130 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
3131 : N2VImm<op24, op23, op11_8, op7, 0, op4,
3132 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
3133 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3134 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
3135 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3136 Format f, InstrItinClass itin, Operand ImmTy,
3137 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
3138 : N2VImm<op24, op23, op11_8, op7, 1, op4,
3139 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
3140 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3141 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
3144 // Long shift by immediate.
3145 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
3146 string OpcodeStr, string Dt,
3147 ValueType ResTy, ValueType OpTy, Operand ImmTy,
3148 SDPatternOperator OpNode>
3149 : N2VImm<op24, op23, op11_8, op7, op6, op4,
3150 (outs QPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), N2RegVShLFrm,
3151 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3152 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm), ImmTy:$SIMM)))]>;
3154 // Narrow shift by immediate.
3155 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
3156 InstrItinClass itin, string OpcodeStr, string Dt,
3157 ValueType ResTy, ValueType OpTy, Operand ImmTy,
3158 SDPatternOperator OpNode>
3159 : N2VImm<op24, op23, op11_8, op7, op6, op4,
3160 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
3161 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3162 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
3163 (i32 ImmTy:$SIMM))))]>;
3165 // Shift right by immediate and accumulate,
3166 // both double- and quad-register.
3167 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3168 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3169 Operand ImmTy, string OpcodeStr, string Dt,
3170 ValueType Ty, SDNode ShOp>
3171 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
3172 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
3173 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3174 [(set DPR:$Vd, (Ty (add DPR:$src1,
3175 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
3176 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3177 Operand ImmTy, string OpcodeStr, string Dt,
3178 ValueType Ty, SDNode ShOp>
3179 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
3180 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
3181 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3182 [(set QPR:$Vd, (Ty (add QPR:$src1,
3183 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
3186 // Shift by immediate and insert,
3187 // both double- and quad-register.
3188 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3189 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3190 Operand ImmTy, Format f, string OpcodeStr, string Dt,
3191 ValueType Ty,SDNode ShOp>
3192 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
3193 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiD,
3194 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3195 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
3196 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3197 Operand ImmTy, Format f, string OpcodeStr, string Dt,
3198 ValueType Ty,SDNode ShOp>
3199 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
3200 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiQ,
3201 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3202 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
3205 // Convert, with fractional bits immediate,
3206 // both double- and quad-register.
3207 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3208 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
3209 SDPatternOperator IntOp>
3210 : N2VImm<op24, op23, op11_8, op7, 0, op4,
3211 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
3212 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3213 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
3214 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3215 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
3216 SDPatternOperator IntOp>
3217 : N2VImm<op24, op23, op11_8, op7, 1, op4,
3218 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
3219 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3220 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
3222 //===----------------------------------------------------------------------===//
3224 //===----------------------------------------------------------------------===//
3226 // Abbreviations used in multiclass suffixes:
3227 // Q = quarter int (8 bit) elements
3228 // H = half int (16 bit) elements
3229 // S = single int (32 bit) elements
3230 // D = double int (64 bit) elements
3232 // Neon 2-register vector operations and intrinsics.
3234 // Neon 2-register comparisons.
3235 // source operand element sizes of 8, 16 and 32 bits:
3236 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3237 bits<5> op11_7, bit op4, string opc, string Dt,
3238 string asm, SDNode OpNode> {
3239 // 64-bit vector types.
3240 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
3241 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3242 opc, !strconcat(Dt, "8"), asm, "",
3243 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
3244 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
3245 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3246 opc, !strconcat(Dt, "16"), asm, "",
3247 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>;
3248 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
3249 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3250 opc, !strconcat(Dt, "32"), asm, "",
3251 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>;
3252 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
3253 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3254 opc, "f32", asm, "",
3255 [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> {
3256 let Inst{10} = 1; // overwrite F = 1
3259 // 128-bit vector types.
3260 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
3261 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3262 opc, !strconcat(Dt, "8"), asm, "",
3263 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
3264 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
3265 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3266 opc, !strconcat(Dt, "16"), asm, "",
3267 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
3268 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
3269 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3270 opc, !strconcat(Dt, "32"), asm, "",
3271 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
3272 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
3273 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3274 opc, "f32", asm, "",
3275 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
3276 let Inst{10} = 1; // overwrite F = 1
3281 // Neon 2-register vector intrinsics,
3282 // element sizes of 8, 16 and 32 bits:
3283 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3284 bits<5> op11_7, bit op4,
3285 InstrItinClass itinD, InstrItinClass itinQ,
3286 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3287 // 64-bit vector types.
3288 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3289 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
3290 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3291 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
3292 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3293 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
3295 // 128-bit vector types.
3296 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3297 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
3298 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3299 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
3300 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3301 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
3305 // Neon Narrowing 2-register vector operations,
3306 // source operand element sizes of 16, 32 and 64 bits:
3307 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3308 bits<5> op11_7, bit op6, bit op4,
3309 InstrItinClass itin, string OpcodeStr, string Dt,
3311 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
3312 itin, OpcodeStr, !strconcat(Dt, "16"),
3313 v8i8, v8i16, OpNode>;
3314 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3315 itin, OpcodeStr, !strconcat(Dt, "32"),
3316 v4i16, v4i32, OpNode>;
3317 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
3318 itin, OpcodeStr, !strconcat(Dt, "64"),
3319 v2i32, v2i64, OpNode>;
3322 // Neon Narrowing 2-register vector intrinsics,
3323 // source operand element sizes of 16, 32 and 64 bits:
3324 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3325 bits<5> op11_7, bit op6, bit op4,
3326 InstrItinClass itin, string OpcodeStr, string Dt,
3327 SDPatternOperator IntOp> {
3328 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
3329 itin, OpcodeStr, !strconcat(Dt, "16"),
3330 v8i8, v8i16, IntOp>;
3331 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3332 itin, OpcodeStr, !strconcat(Dt, "32"),
3333 v4i16, v4i32, IntOp>;
3334 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
3335 itin, OpcodeStr, !strconcat(Dt, "64"),
3336 v2i32, v2i64, IntOp>;
3340 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
3341 // source operand element sizes of 16, 32 and 64 bits:
3342 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
3343 string OpcodeStr, string Dt, SDNode OpNode> {
3344 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3345 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
3346 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3347 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
3348 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3349 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
3353 // Neon 3-register vector operations.
3355 // First with only element sizes of 8, 16 and 32 bits:
3356 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3357 InstrItinClass itinD16, InstrItinClass itinD32,
3358 InstrItinClass itinQ16, InstrItinClass itinQ32,
3359 string OpcodeStr, string Dt,
3360 SDNode OpNode, bit Commutable = 0> {
3361 // 64-bit vector types.
3362 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
3363 OpcodeStr, !strconcat(Dt, "8"),
3364 v8i8, v8i8, OpNode, Commutable>;
3365 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
3366 OpcodeStr, !strconcat(Dt, "16"),
3367 v4i16, v4i16, OpNode, Commutable>;
3368 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
3369 OpcodeStr, !strconcat(Dt, "32"),
3370 v2i32, v2i32, OpNode, Commutable>;
3372 // 128-bit vector types.
3373 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
3374 OpcodeStr, !strconcat(Dt, "8"),
3375 v16i8, v16i8, OpNode, Commutable>;
3376 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
3377 OpcodeStr, !strconcat(Dt, "16"),
3378 v8i16, v8i16, OpNode, Commutable>;
3379 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
3380 OpcodeStr, !strconcat(Dt, "32"),
3381 v4i32, v4i32, OpNode, Commutable>;
3384 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, SDNode ShOp> {
3385 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, "i16", v4i16, ShOp>;
3386 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, "i32", v2i32, ShOp>;
3387 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, "i16", v8i16, v4i16, ShOp>;
3388 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, "i32",
3389 v4i32, v2i32, ShOp>;
3392 // ....then also with element size 64 bits:
3393 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3394 InstrItinClass itinD, InstrItinClass itinQ,
3395 string OpcodeStr, string Dt,
3396 SDNode OpNode, bit Commutable = 0>
3397 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
3398 OpcodeStr, Dt, OpNode, Commutable> {
3399 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
3400 OpcodeStr, !strconcat(Dt, "64"),
3401 v1i64, v1i64, OpNode, Commutable>;
3402 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
3403 OpcodeStr, !strconcat(Dt, "64"),
3404 v2i64, v2i64, OpNode, Commutable>;
3408 // Neon 3-register vector intrinsics.
3410 // First with only element sizes of 16 and 32 bits:
3411 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3412 InstrItinClass itinD16, InstrItinClass itinD32,
3413 InstrItinClass itinQ16, InstrItinClass itinQ32,
3414 string OpcodeStr, string Dt,
3415 SDPatternOperator IntOp, bit Commutable = 0> {
3416 // 64-bit vector types.
3417 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
3418 OpcodeStr, !strconcat(Dt, "16"),
3419 v4i16, v4i16, IntOp, Commutable>;
3420 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
3421 OpcodeStr, !strconcat(Dt, "32"),
3422 v2i32, v2i32, IntOp, Commutable>;
3424 // 128-bit vector types.
3425 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3426 OpcodeStr, !strconcat(Dt, "16"),
3427 v8i16, v8i16, IntOp, Commutable>;
3428 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3429 OpcodeStr, !strconcat(Dt, "32"),
3430 v4i32, v4i32, IntOp, Commutable>;
3432 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3433 InstrItinClass itinD16, InstrItinClass itinD32,
3434 InstrItinClass itinQ16, InstrItinClass itinQ32,
3435 string OpcodeStr, string Dt,
3436 SDPatternOperator IntOp> {
3437 // 64-bit vector types.
3438 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
3439 OpcodeStr, !strconcat(Dt, "16"),
3440 v4i16, v4i16, IntOp>;
3441 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
3442 OpcodeStr, !strconcat(Dt, "32"),
3443 v2i32, v2i32, IntOp>;
3445 // 128-bit vector types.
3446 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3447 OpcodeStr, !strconcat(Dt, "16"),
3448 v8i16, v8i16, IntOp>;
3449 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3450 OpcodeStr, !strconcat(Dt, "32"),
3451 v4i32, v4i32, IntOp>;
3454 multiclass N3VIntSL_HS<bits<4> op11_8,
3455 InstrItinClass itinD16, InstrItinClass itinD32,
3456 InstrItinClass itinQ16, InstrItinClass itinQ32,
3457 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3458 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
3459 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
3460 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
3461 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
3462 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
3463 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
3464 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
3465 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
3468 // ....then also with element size of 8 bits:
3469 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3470 InstrItinClass itinD16, InstrItinClass itinD32,
3471 InstrItinClass itinQ16, InstrItinClass itinQ32,
3472 string OpcodeStr, string Dt,
3473 SDPatternOperator IntOp, bit Commutable = 0>
3474 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3475 OpcodeStr, Dt, IntOp, Commutable> {
3476 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
3477 OpcodeStr, !strconcat(Dt, "8"),
3478 v8i8, v8i8, IntOp, Commutable>;
3479 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
3480 OpcodeStr, !strconcat(Dt, "8"),
3481 v16i8, v16i8, IntOp, Commutable>;
3483 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3484 InstrItinClass itinD16, InstrItinClass itinD32,
3485 InstrItinClass itinQ16, InstrItinClass itinQ32,
3486 string OpcodeStr, string Dt,
3487 SDPatternOperator IntOp>
3488 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3489 OpcodeStr, Dt, IntOp> {
3490 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
3491 OpcodeStr, !strconcat(Dt, "8"),
3493 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
3494 OpcodeStr, !strconcat(Dt, "8"),
3495 v16i8, v16i8, IntOp>;
3499 // ....then also with element size of 64 bits:
3500 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3501 InstrItinClass itinD16, InstrItinClass itinD32,
3502 InstrItinClass itinQ16, InstrItinClass itinQ32,
3503 string OpcodeStr, string Dt,
3504 SDPatternOperator IntOp, bit Commutable = 0>
3505 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3506 OpcodeStr, Dt, IntOp, Commutable> {
3507 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
3508 OpcodeStr, !strconcat(Dt, "64"),
3509 v1i64, v1i64, IntOp, Commutable>;
3510 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3511 OpcodeStr, !strconcat(Dt, "64"),
3512 v2i64, v2i64, IntOp, Commutable>;
3514 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3515 InstrItinClass itinD16, InstrItinClass itinD32,
3516 InstrItinClass itinQ16, InstrItinClass itinQ32,
3517 string OpcodeStr, string Dt,
3518 SDPatternOperator IntOp>
3519 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3520 OpcodeStr, Dt, IntOp> {
3521 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
3522 OpcodeStr, !strconcat(Dt, "64"),
3523 v1i64, v1i64, IntOp>;
3524 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3525 OpcodeStr, !strconcat(Dt, "64"),
3526 v2i64, v2i64, IntOp>;
3529 // Neon Narrowing 3-register vector intrinsics,
3530 // source operand element sizes of 16, 32 and 64 bits:
3531 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3532 string OpcodeStr, string Dt,
3533 SDPatternOperator IntOp, bit Commutable = 0> {
3534 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
3535 OpcodeStr, !strconcat(Dt, "16"),
3536 v8i8, v8i16, IntOp, Commutable>;
3537 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
3538 OpcodeStr, !strconcat(Dt, "32"),
3539 v4i16, v4i32, IntOp, Commutable>;
3540 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
3541 OpcodeStr, !strconcat(Dt, "64"),
3542 v2i32, v2i64, IntOp, Commutable>;
3546 // Neon Long 3-register vector operations.
3548 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3549 InstrItinClass itin16, InstrItinClass itin32,
3550 string OpcodeStr, string Dt,
3551 SDNode OpNode, bit Commutable = 0> {
3552 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
3553 OpcodeStr, !strconcat(Dt, "8"),
3554 v8i16, v8i8, OpNode, Commutable>;
3555 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
3556 OpcodeStr, !strconcat(Dt, "16"),
3557 v4i32, v4i16, OpNode, Commutable>;
3558 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
3559 OpcodeStr, !strconcat(Dt, "32"),
3560 v2i64, v2i32, OpNode, Commutable>;
3563 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
3564 InstrItinClass itin, string OpcodeStr, string Dt,
3566 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
3567 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
3568 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
3569 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
3572 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3573 InstrItinClass itin16, InstrItinClass itin32,
3574 string OpcodeStr, string Dt,
3575 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3576 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
3577 OpcodeStr, !strconcat(Dt, "8"),
3578 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3579 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
3580 OpcodeStr, !strconcat(Dt, "16"),
3581 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3582 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
3583 OpcodeStr, !strconcat(Dt, "32"),
3584 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3587 // Neon Long 3-register vector intrinsics.
3589 // First with only element sizes of 16 and 32 bits:
3590 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3591 InstrItinClass itin16, InstrItinClass itin32,
3592 string OpcodeStr, string Dt,
3593 SDPatternOperator IntOp, bit Commutable = 0> {
3594 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
3595 OpcodeStr, !strconcat(Dt, "16"),
3596 v4i32, v4i16, IntOp, Commutable>;
3597 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
3598 OpcodeStr, !strconcat(Dt, "32"),
3599 v2i64, v2i32, IntOp, Commutable>;
3602 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
3603 InstrItinClass itin, string OpcodeStr, string Dt,
3604 SDPatternOperator IntOp> {
3605 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
3606 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3607 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
3608 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3611 // ....then also with element size of 8 bits:
3612 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3613 InstrItinClass itin16, InstrItinClass itin32,
3614 string OpcodeStr, string Dt,
3615 SDPatternOperator IntOp, bit Commutable = 0>
3616 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
3617 IntOp, Commutable> {
3618 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
3619 OpcodeStr, !strconcat(Dt, "8"),
3620 v8i16, v8i8, IntOp, Commutable>;
3623 // ....with explicit extend (VABDL).
3624 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3625 InstrItinClass itin, string OpcodeStr, string Dt,
3626 SDPatternOperator IntOp, SDNode ExtOp, bit Commutable = 0> {
3627 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
3628 OpcodeStr, !strconcat(Dt, "8"),
3629 v8i16, v8i8, IntOp, ExtOp, Commutable>;
3630 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
3631 OpcodeStr, !strconcat(Dt, "16"),
3632 v4i32, v4i16, IntOp, ExtOp, Commutable>;
3633 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
3634 OpcodeStr, !strconcat(Dt, "32"),
3635 v2i64, v2i32, IntOp, ExtOp, Commutable>;
3639 // Neon Wide 3-register vector intrinsics,
3640 // source operand element sizes of 8, 16 and 32 bits:
3641 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3642 string OpcodeStr, string Dt,
3643 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3644 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
3645 OpcodeStr, !strconcat(Dt, "8"),
3646 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3647 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
3648 OpcodeStr, !strconcat(Dt, "16"),
3649 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3650 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
3651 OpcodeStr, !strconcat(Dt, "32"),
3652 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3656 // Neon Multiply-Op vector operations,
3657 // element sizes of 8, 16 and 32 bits:
3658 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3659 InstrItinClass itinD16, InstrItinClass itinD32,
3660 InstrItinClass itinQ16, InstrItinClass itinQ32,
3661 string OpcodeStr, string Dt, SDNode OpNode> {
3662 // 64-bit vector types.
3663 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
3664 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
3665 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
3666 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
3667 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
3668 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
3670 // 128-bit vector types.
3671 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
3672 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
3673 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
3674 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
3675 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
3676 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
3679 multiclass N3VMulOpSL_HS<bits<4> op11_8,
3680 InstrItinClass itinD16, InstrItinClass itinD32,
3681 InstrItinClass itinQ16, InstrItinClass itinQ32,
3682 string OpcodeStr, string Dt, SDPatternOperator ShOp> {
3683 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
3684 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
3685 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
3686 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
3687 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
3688 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
3690 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
3691 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
3695 // Neon Intrinsic-Op vector operations,
3696 // element sizes of 8, 16 and 32 bits:
3697 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3698 InstrItinClass itinD, InstrItinClass itinQ,
3699 string OpcodeStr, string Dt, SDPatternOperator IntOp,
3701 // 64-bit vector types.
3702 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
3703 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
3704 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
3705 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
3706 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
3707 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
3709 // 128-bit vector types.
3710 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
3711 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
3712 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
3713 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
3714 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
3715 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
3718 // Neon 3-argument intrinsics,
3719 // element sizes of 16 and 32 bits:
3720 multiclass N3VInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3721 InstrItinClass itinD16, InstrItinClass itinD32,
3722 InstrItinClass itinQ16, InstrItinClass itinQ32,
3723 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3724 // 64-bit vector types.
3725 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD16,
3726 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
3727 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD32,
3728 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
3730 // 128-bit vector types.
3731 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ16,
3732 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
3733 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ32,
3734 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
3737 // element sizes of 8, 16 and 32 bits:
3738 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3739 InstrItinClass itinD16, InstrItinClass itinD32,
3740 InstrItinClass itinQ16, InstrItinClass itinQ32,
3741 string OpcodeStr, string Dt, SDPatternOperator IntOp>
3742 :N3VInt3_HS <op24, op23, op11_8, op4, itinD16, itinD32,
3743 itinQ16, itinQ32, OpcodeStr, Dt, IntOp>{
3744 // 64-bit vector types.
3745 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD16,
3746 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
3747 // 128-bit vector types.
3748 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ16,
3749 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
3752 // Neon Long Multiply-Op vector operations,
3753 // element sizes of 8, 16 and 32 bits:
3754 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3755 InstrItinClass itin16, InstrItinClass itin32,
3756 string OpcodeStr, string Dt, SDNode MulOp,
3758 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
3759 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
3760 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
3761 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
3762 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
3763 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3766 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
3767 string Dt, SDNode MulOp, SDNode OpNode> {
3768 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
3769 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
3770 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
3771 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3775 // Neon Long 3-argument intrinsics.
3777 // First with only element sizes of 16 and 32 bits:
3778 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3779 InstrItinClass itin16, InstrItinClass itin32,
3780 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3781 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
3782 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3783 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
3784 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3787 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
3788 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3789 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
3790 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
3791 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
3792 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3795 // ....then also with element size of 8 bits:
3796 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3797 InstrItinClass itin16, InstrItinClass itin32,
3798 string OpcodeStr, string Dt, SDPatternOperator IntOp>
3799 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
3800 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
3801 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
3804 // ....with explicit extend (VABAL).
3805 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3806 InstrItinClass itin, string OpcodeStr, string Dt,
3807 SDPatternOperator IntOp, SDNode ExtOp, SDNode OpNode> {
3808 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
3809 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
3810 IntOp, ExtOp, OpNode>;
3811 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
3812 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
3813 IntOp, ExtOp, OpNode>;
3814 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
3815 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
3816 IntOp, ExtOp, OpNode>;
3820 // Neon Pairwise long 2-register intrinsics,
3821 // element sizes of 8, 16 and 32 bits:
3822 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3823 bits<5> op11_7, bit op4,
3824 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3825 // 64-bit vector types.
3826 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3827 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3828 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3829 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3830 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3831 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3833 // 128-bit vector types.
3834 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3835 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3836 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3837 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3838 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3839 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3843 // Neon Pairwise long 2-register accumulate intrinsics,
3844 // element sizes of 8, 16 and 32 bits:
3845 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3846 bits<5> op11_7, bit op4,
3847 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3848 // 64-bit vector types.
3849 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3850 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3851 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3852 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3853 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3854 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3856 // 128-bit vector types.
3857 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3858 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3859 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3860 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3861 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3862 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3866 // Neon 2-register vector shift by immediate,
3867 // with f of either N2RegVShLFrm or N2RegVShRFrm
3868 // element sizes of 8, 16, 32 and 64 bits:
3869 multiclass N2VShL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3870 InstrItinClass itin, string OpcodeStr, string Dt,
3872 // 64-bit vector types.
3873 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3874 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3875 let Inst{21-19} = 0b001; // imm6 = 001xxx
3877 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3878 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3879 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3881 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3882 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3883 let Inst{21} = 0b1; // imm6 = 1xxxxx
3885 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3886 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3889 // 128-bit vector types.
3890 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3891 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3892 let Inst{21-19} = 0b001; // imm6 = 001xxx
3894 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3895 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3896 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3898 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3899 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3900 let Inst{21} = 0b1; // imm6 = 1xxxxx
3902 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3903 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3906 multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3907 InstrItinClass itin, string OpcodeStr, string Dt,
3908 string baseOpc, SDNode OpNode> {
3909 // 64-bit vector types.
3910 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3911 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3912 let Inst{21-19} = 0b001; // imm6 = 001xxx
3914 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3915 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3916 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3918 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3919 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3920 let Inst{21} = 0b1; // imm6 = 1xxxxx
3922 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3923 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3926 // 128-bit vector types.
3927 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3928 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3929 let Inst{21-19} = 0b001; // imm6 = 001xxx
3931 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3932 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3933 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3935 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3936 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3937 let Inst{21} = 0b1; // imm6 = 1xxxxx
3939 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3940 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3944 // Neon Shift-Accumulate vector operations,
3945 // element sizes of 8, 16, 32 and 64 bits:
3946 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3947 string OpcodeStr, string Dt, SDNode ShOp> {
3948 // 64-bit vector types.
3949 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3950 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
3951 let Inst{21-19} = 0b001; // imm6 = 001xxx
3953 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3954 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
3955 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3957 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3958 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
3959 let Inst{21} = 0b1; // imm6 = 1xxxxx
3961 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3962 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
3965 // 128-bit vector types.
3966 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3967 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
3968 let Inst{21-19} = 0b001; // imm6 = 001xxx
3970 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3971 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
3972 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3974 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3975 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
3976 let Inst{21} = 0b1; // imm6 = 1xxxxx
3978 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3979 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
3983 // Neon Shift-Insert vector operations,
3984 // with f of either N2RegVShLFrm or N2RegVShRFrm
3985 // element sizes of 8, 16, 32 and 64 bits:
3986 multiclass N2VShInsL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3988 // 64-bit vector types.
3989 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3990 N2RegVShLFrm, OpcodeStr, "8", v8i8, NEONvsli> {
3991 let Inst{21-19} = 0b001; // imm6 = 001xxx
3993 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3994 N2RegVShLFrm, OpcodeStr, "16", v4i16, NEONvsli> {
3995 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3997 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3998 N2RegVShLFrm, OpcodeStr, "32", v2i32, NEONvsli> {
3999 let Inst{21} = 0b1; // imm6 = 1xxxxx
4001 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, i32imm,
4002 N2RegVShLFrm, OpcodeStr, "64", v1i64, NEONvsli>;
4005 // 128-bit vector types.
4006 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
4007 N2RegVShLFrm, OpcodeStr, "8", v16i8, NEONvsli> {
4008 let Inst{21-19} = 0b001; // imm6 = 001xxx
4010 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
4011 N2RegVShLFrm, OpcodeStr, "16", v8i16, NEONvsli> {
4012 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4014 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
4015 N2RegVShLFrm, OpcodeStr, "32", v4i32, NEONvsli> {
4016 let Inst{21} = 0b1; // imm6 = 1xxxxx
4018 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, i32imm,
4019 N2RegVShLFrm, OpcodeStr, "64", v2i64, NEONvsli>;
4022 multiclass N2VShInsR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
4024 // 64-bit vector types.
4025 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm8,
4026 N2RegVShRFrm, OpcodeStr, "8", v8i8, NEONvsri> {
4027 let Inst{21-19} = 0b001; // imm6 = 001xxx
4029 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm16,
4030 N2RegVShRFrm, OpcodeStr, "16", v4i16, NEONvsri> {
4031 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4033 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm32,
4034 N2RegVShRFrm, OpcodeStr, "32", v2i32, NEONvsri> {
4035 let Inst{21} = 0b1; // imm6 = 1xxxxx
4037 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, shr_imm64,
4038 N2RegVShRFrm, OpcodeStr, "64", v1i64, NEONvsri>;
4041 // 128-bit vector types.
4042 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm8,
4043 N2RegVShRFrm, OpcodeStr, "8", v16i8, NEONvsri> {
4044 let Inst{21-19} = 0b001; // imm6 = 001xxx
4046 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm16,
4047 N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsri> {
4048 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4050 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm32,
4051 N2RegVShRFrm, OpcodeStr, "32", v4i32, NEONvsri> {
4052 let Inst{21} = 0b1; // imm6 = 1xxxxx
4054 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, shr_imm64,
4055 N2RegVShRFrm, OpcodeStr, "64", v2i64, NEONvsri>;
4059 // Neon Shift Long operations,
4060 // element sizes of 8, 16, 32 bits:
4061 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
4062 bit op4, string OpcodeStr, string Dt,
4063 SDPatternOperator OpNode> {
4064 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
4065 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, imm1_7, OpNode> {
4066 let Inst{21-19} = 0b001; // imm6 = 001xxx
4068 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
4069 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, imm1_15, OpNode> {
4070 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4072 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
4073 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, imm1_31, OpNode> {
4074 let Inst{21} = 0b1; // imm6 = 1xxxxx
4078 // Neon Shift Narrow operations,
4079 // element sizes of 16, 32, 64 bits:
4080 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
4081 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
4082 SDPatternOperator OpNode> {
4083 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
4084 OpcodeStr, !strconcat(Dt, "16"),
4085 v8i8, v8i16, shr_imm8, OpNode> {
4086 let Inst{21-19} = 0b001; // imm6 = 001xxx
4088 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
4089 OpcodeStr, !strconcat(Dt, "32"),
4090 v4i16, v4i32, shr_imm16, OpNode> {
4091 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4093 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
4094 OpcodeStr, !strconcat(Dt, "64"),
4095 v2i32, v2i64, shr_imm32, OpNode> {
4096 let Inst{21} = 0b1; // imm6 = 1xxxxx
4100 //===----------------------------------------------------------------------===//
4101 // Instruction Definitions.
4102 //===----------------------------------------------------------------------===//
4104 // Vector Add Operations.
4106 // VADD : Vector Add (integer and floating-point)
4107 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
4109 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
4110 v2f32, v2f32, fadd, 1>;
4111 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
4112 v4f32, v4f32, fadd, 1>;
4113 // VADDL : Vector Add Long (Q = D + D)
4114 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
4115 "vaddl", "s", add, sext, 1>;
4116 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
4117 "vaddl", "u", add, zext, 1>;
4118 // VADDW : Vector Add Wide (Q = Q + D)
4119 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
4120 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
4121 // VHADD : Vector Halving Add
4122 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
4123 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4124 "vhadd", "s", int_arm_neon_vhadds, 1>;
4125 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
4126 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4127 "vhadd", "u", int_arm_neon_vhaddu, 1>;
4128 // VRHADD : Vector Rounding Halving Add
4129 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
4130 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4131 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
4132 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
4133 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4134 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
4135 // VQADD : Vector Saturating Add
4136 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
4137 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4138 "vqadd", "s", int_arm_neon_vqadds, 1>;
4139 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
4140 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4141 "vqadd", "u", int_arm_neon_vqaddu, 1>;
4142 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
4143 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i", null_frag, 1>;
4144 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
4145 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
4146 int_arm_neon_vraddhn, 1>;
4148 def : Pat<(v8i8 (trunc (NEONvshru (add (v8i16 QPR:$Vn), QPR:$Vm), 8))),
4149 (VADDHNv8i8 QPR:$Vn, QPR:$Vm)>;
4150 def : Pat<(v4i16 (trunc (NEONvshru (add (v4i32 QPR:$Vn), QPR:$Vm), 16))),
4151 (VADDHNv4i16 QPR:$Vn, QPR:$Vm)>;
4152 def : Pat<(v2i32 (trunc (NEONvshru (add (v2i64 QPR:$Vn), QPR:$Vm), 32))),
4153 (VADDHNv2i32 QPR:$Vn, QPR:$Vm)>;
4155 // Vector Multiply Operations.
4157 // VMUL : Vector Multiply (integer, polynomial and floating-point)
4158 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
4159 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
4160 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
4161 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
4162 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
4163 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
4164 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
4165 v2f32, v2f32, fmul, 1>;
4166 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
4167 v4f32, v4f32, fmul, 1>;
4168 defm VMULsl : N3VSL_HS<0b1000, "vmul", mul>;
4169 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
4170 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
4173 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
4174 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
4175 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
4176 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4177 (DSubReg_i16_reg imm:$lane))),
4178 (SubReg_i16_lane imm:$lane)))>;
4179 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
4180 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
4181 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
4182 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4183 (DSubReg_i32_reg imm:$lane))),
4184 (SubReg_i32_lane imm:$lane)))>;
4185 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
4186 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
4187 (v4f32 (VMULslfq (v4f32 QPR:$src1),
4188 (v2f32 (EXTRACT_SUBREG QPR:$src2,
4189 (DSubReg_i32_reg imm:$lane))),
4190 (SubReg_i32_lane imm:$lane)))>;
4193 def : Pat<(v2f32 (fmul DPR:$Rn, (NEONvdup (f32 SPR:$Rm)))),
4195 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0),
4197 def : Pat<(v4f32 (fmul QPR:$Rn, (NEONvdup (f32 SPR:$Rm)))),
4199 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0),
4203 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
4204 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
4205 IIC_VMULi16Q, IIC_VMULi32Q,
4206 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
4207 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
4208 IIC_VMULi16Q, IIC_VMULi32Q,
4209 "vqdmulh", "s", int_arm_neon_vqdmulh>;
4210 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
4211 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
4213 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
4214 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4215 (DSubReg_i16_reg imm:$lane))),
4216 (SubReg_i16_lane imm:$lane)))>;
4217 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
4218 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
4220 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
4221 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4222 (DSubReg_i32_reg imm:$lane))),
4223 (SubReg_i32_lane imm:$lane)))>;
4225 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
4226 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
4227 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
4228 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
4229 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
4230 IIC_VMULi16Q, IIC_VMULi32Q,
4231 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
4232 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
4233 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
4235 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
4236 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4237 (DSubReg_i16_reg imm:$lane))),
4238 (SubReg_i16_lane imm:$lane)))>;
4239 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
4240 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
4242 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
4243 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4244 (DSubReg_i32_reg imm:$lane))),
4245 (SubReg_i32_lane imm:$lane)))>;
4247 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
4248 let PostEncoderMethod = "NEONThumb2DataIPostEncoder",
4249 DecoderNamespace = "NEONData" in {
4250 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
4251 "vmull", "s", NEONvmulls, 1>;
4252 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
4253 "vmull", "u", NEONvmullu, 1>;
4254 def VMULLp8 : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
4255 v8i16, v8i8, int_arm_neon_vmullp, 1>;
4256 def VMULLp64 : N3VLIntnp<0b00101, 0b10, 0b1110, 0, 0, NoItinerary,
4257 "vmull", "p64", v2i64, v1i64, int_arm_neon_vmullp, 1>,
4258 Requires<[HasV8, HasCrypto]>;
4260 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
4261 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
4263 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
4264 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
4265 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
4266 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
4267 "vqdmull", "s", int_arm_neon_vqdmull>;
4269 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
4271 // VMLA : Vector Multiply Accumulate (integer and floating-point)
4272 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
4273 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
4274 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
4275 v2f32, fmul_su, fadd_mlx>,
4276 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4277 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
4278 v4f32, fmul_su, fadd_mlx>,
4279 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4280 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
4281 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
4282 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
4283 v2f32, fmul_su, fadd_mlx>,
4284 Requires<[HasNEON, UseFPVMLx]>;
4285 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
4286 v4f32, v2f32, fmul_su, fadd_mlx>,
4287 Requires<[HasNEON, UseFPVMLx]>;
4289 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
4290 (mul (v8i16 QPR:$src2),
4291 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4292 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
4293 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4294 (DSubReg_i16_reg imm:$lane))),
4295 (SubReg_i16_lane imm:$lane)))>;
4297 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
4298 (mul (v4i32 QPR:$src2),
4299 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4300 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
4301 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4302 (DSubReg_i32_reg imm:$lane))),
4303 (SubReg_i32_lane imm:$lane)))>;
4305 def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1),
4306 (fmul_su (v4f32 QPR:$src2),
4307 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
4308 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
4310 (v2f32 (EXTRACT_SUBREG QPR:$src3,
4311 (DSubReg_i32_reg imm:$lane))),
4312 (SubReg_i32_lane imm:$lane)))>,
4313 Requires<[HasNEON, UseFPVMLx]>;
4315 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
4316 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
4317 "vmlal", "s", NEONvmulls, add>;
4318 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
4319 "vmlal", "u", NEONvmullu, add>;
4321 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
4322 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
4324 let Predicates = [HasNEON, HasV8_1a] in {
4325 // v8.1a Neon Rounding Double Multiply-Op vector operations,
4326 // VQRDMLAH : Vector Saturating Rounding Doubling Multiply Accumulate Long
4328 defm VQRDMLAH : N3VInt3_HS<1, 0, 0b1011, 1, IIC_VMACi16D, IIC_VMACi32D,
4329 IIC_VMACi16Q, IIC_VMACi32Q, "vqrdmlah", "s",
4331 def : Pat<(v4i16 (int_arm_neon_vqadds
4333 (v4i16 (int_arm_neon_vqrdmulh (v4i16 DPR:$Vn),
4334 (v4i16 DPR:$Vm))))),
4335 (v4i16 (VQRDMLAHv4i16 DPR:$src1, DPR:$Vn, DPR:$Vm))>;
4336 def : Pat<(v2i32 (int_arm_neon_vqadds
4338 (v2i32 (int_arm_neon_vqrdmulh (v2i32 DPR:$Vn),
4339 (v2i32 DPR:$Vm))))),
4340 (v2i32 (VQRDMLAHv2i32 DPR:$src1, DPR:$Vn, DPR:$Vm))>;
4341 def : Pat<(v8i16 (int_arm_neon_vqadds
4343 (v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$Vn),
4344 (v8i16 QPR:$Vm))))),
4345 (v8i16 (VQRDMLAHv8i16 QPR:$src1, QPR:$Vn, QPR:$Vm))>;
4346 def : Pat<(v4i32 (int_arm_neon_vqadds
4348 (v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$Vn),
4349 (v4i32 QPR:$Vm))))),
4350 (v4i32 (VQRDMLAHv4i32 QPR:$src1, QPR:$Vn, QPR:$Vm))>;
4352 defm VQRDMLAHsl : N3VMulOpSL_HS<0b1110, IIC_VMACi16D, IIC_VMACi32D,
4353 IIC_VMACi16Q, IIC_VMACi32Q, "vqrdmlah", "s",
4355 def : Pat<(v4i16 (int_arm_neon_vqadds
4357 (v4i16 (int_arm_neon_vqrdmulh
4359 (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm),
4361 (v4i16 (VQRDMLAHslv4i16 DPR:$src1, DPR:$Vn, DPR_8:$Vm,
4363 def : Pat<(v2i32 (int_arm_neon_vqadds
4365 (v2i32 (int_arm_neon_vqrdmulh
4367 (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm),
4369 (v2i32 (VQRDMLAHslv2i32 DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm,
4371 def : Pat<(v8i16 (int_arm_neon_vqadds
4373 (v8i16 (int_arm_neon_vqrdmulh
4375 (v8i16 (NEONvduplane (v8i16 QPR:$src3),
4377 (v8i16 (VQRDMLAHslv8i16 (v8i16 QPR:$src1),
4379 (v4i16 (EXTRACT_SUBREG
4381 (DSubReg_i16_reg imm:$lane))),
4382 (SubReg_i16_lane imm:$lane)))>;
4383 def : Pat<(v4i32 (int_arm_neon_vqadds
4385 (v4i32 (int_arm_neon_vqrdmulh
4387 (v4i32 (NEONvduplane (v4i32 QPR:$src3),
4389 (v4i32 (VQRDMLAHslv4i32 (v4i32 QPR:$src1),
4391 (v2i32 (EXTRACT_SUBREG
4393 (DSubReg_i32_reg imm:$lane))),
4394 (SubReg_i32_lane imm:$lane)))>;
4396 // VQRDMLSH : Vector Saturating Rounding Doubling Multiply Subtract Long
4398 defm VQRDMLSH : N3VInt3_HS<1, 0, 0b1100, 1, IIC_VMACi16D, IIC_VMACi32D,
4399 IIC_VMACi16Q, IIC_VMACi32Q, "vqrdmlsh", "s",
4401 def : Pat<(v4i16 (int_arm_neon_vqsubs
4403 (v4i16 (int_arm_neon_vqrdmulh (v4i16 DPR:$Vn),
4404 (v4i16 DPR:$Vm))))),
4405 (v4i16 (VQRDMLSHv4i16 DPR:$src1, DPR:$Vn, DPR:$Vm))>;
4406 def : Pat<(v2i32 (int_arm_neon_vqsubs
4408 (v2i32 (int_arm_neon_vqrdmulh (v2i32 DPR:$Vn),
4409 (v2i32 DPR:$Vm))))),
4410 (v2i32 (VQRDMLSHv2i32 DPR:$src1, DPR:$Vn, DPR:$Vm))>;
4411 def : Pat<(v8i16 (int_arm_neon_vqsubs
4413 (v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$Vn),
4414 (v8i16 QPR:$Vm))))),
4415 (v8i16 (VQRDMLSHv8i16 QPR:$src1, QPR:$Vn, QPR:$Vm))>;
4416 def : Pat<(v4i32 (int_arm_neon_vqsubs
4418 (v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$Vn),
4419 (v4i32 QPR:$Vm))))),
4420 (v4i32 (VQRDMLSHv4i32 QPR:$src1, QPR:$Vn, QPR:$Vm))>;
4422 defm VQRDMLSHsl : N3VMulOpSL_HS<0b1111, IIC_VMACi16D, IIC_VMACi32D,
4423 IIC_VMACi16Q, IIC_VMACi32Q, "vqrdmlsh", "s",
4425 def : Pat<(v4i16 (int_arm_neon_vqsubs
4427 (v4i16 (int_arm_neon_vqrdmulh
4429 (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm),
4431 (v4i16 (VQRDMLSHslv4i16 DPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane))>;
4432 def : Pat<(v2i32 (int_arm_neon_vqsubs
4434 (v2i32 (int_arm_neon_vqrdmulh
4436 (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm),
4438 (v2i32 (VQRDMLSHslv2i32 DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm,
4440 def : Pat<(v8i16 (int_arm_neon_vqsubs
4442 (v8i16 (int_arm_neon_vqrdmulh
4444 (v8i16 (NEONvduplane (v8i16 QPR:$src3),
4446 (v8i16 (VQRDMLSHslv8i16 (v8i16 QPR:$src1),
4448 (v4i16 (EXTRACT_SUBREG
4450 (DSubReg_i16_reg imm:$lane))),
4451 (SubReg_i16_lane imm:$lane)))>;
4452 def : Pat<(v4i32 (int_arm_neon_vqsubs
4454 (v4i32 (int_arm_neon_vqrdmulh
4456 (v4i32 (NEONvduplane (v4i32 QPR:$src3),
4458 (v4i32 (VQRDMLSHslv4i32 (v4i32 QPR:$src1),
4460 (v2i32 (EXTRACT_SUBREG
4462 (DSubReg_i32_reg imm:$lane))),
4463 (SubReg_i32_lane imm:$lane)))>;
4465 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
4466 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
4467 "vqdmlal", "s", null_frag>;
4468 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", null_frag>;
4470 def : Pat<(v4i32 (int_arm_neon_vqadds (v4i32 QPR:$src1),
4471 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4472 (v4i16 DPR:$Vm))))),
4473 (VQDMLALv4i32 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4474 def : Pat<(v2i64 (int_arm_neon_vqadds (v2i64 QPR:$src1),
4475 (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn),
4476 (v2i32 DPR:$Vm))))),
4477 (VQDMLALv2i64 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4478 def : Pat<(v4i32 (int_arm_neon_vqadds (v4i32 QPR:$src1),
4479 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4480 (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm),
4482 (VQDMLALslv4i16 QPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane)>;
4483 def : Pat<(v2i64 (int_arm_neon_vqadds (v2i64 QPR:$src1),
4484 (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn),
4485 (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm),
4487 (VQDMLALslv2i32 QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane)>;
4489 // VMLS : Vector Multiply Subtract (integer and floating-point)
4490 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
4491 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
4492 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
4493 v2f32, fmul_su, fsub_mlx>,
4494 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4495 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
4496 v4f32, fmul_su, fsub_mlx>,
4497 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4498 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
4499 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
4500 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
4501 v2f32, fmul_su, fsub_mlx>,
4502 Requires<[HasNEON, UseFPVMLx]>;
4503 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
4504 v4f32, v2f32, fmul_su, fsub_mlx>,
4505 Requires<[HasNEON, UseFPVMLx]>;
4507 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
4508 (mul (v8i16 QPR:$src2),
4509 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4510 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
4511 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4512 (DSubReg_i16_reg imm:$lane))),
4513 (SubReg_i16_lane imm:$lane)))>;
4515 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
4516 (mul (v4i32 QPR:$src2),
4517 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4518 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
4519 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4520 (DSubReg_i32_reg imm:$lane))),
4521 (SubReg_i32_lane imm:$lane)))>;
4523 def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1),
4524 (fmul_su (v4f32 QPR:$src2),
4525 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
4526 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
4527 (v2f32 (EXTRACT_SUBREG QPR:$src3,
4528 (DSubReg_i32_reg imm:$lane))),
4529 (SubReg_i32_lane imm:$lane)))>,
4530 Requires<[HasNEON, UseFPVMLx]>;
4532 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
4533 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
4534 "vmlsl", "s", NEONvmulls, sub>;
4535 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
4536 "vmlsl", "u", NEONvmullu, sub>;
4538 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
4539 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
4541 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
4542 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
4543 "vqdmlsl", "s", null_frag>;
4544 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b0111, "vqdmlsl", "s", null_frag>;
4546 def : Pat<(v4i32 (int_arm_neon_vqsubs (v4i32 QPR:$src1),
4547 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4548 (v4i16 DPR:$Vm))))),
4549 (VQDMLSLv4i32 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4550 def : Pat<(v2i64 (int_arm_neon_vqsubs (v2i64 QPR:$src1),
4551 (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn),
4552 (v2i32 DPR:$Vm))))),
4553 (VQDMLSLv2i64 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4554 def : Pat<(v4i32 (int_arm_neon_vqsubs (v4i32 QPR:$src1),
4555 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4556 (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm),
4558 (VQDMLSLslv4i16 QPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane)>;
4559 def : Pat<(v2i64 (int_arm_neon_vqsubs (v2i64 QPR:$src1),
4560 (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn),
4561 (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm),
4563 (VQDMLSLslv2i32 QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane)>;
4565 // Fused Vector Multiply-Accumulate and Fused Multiply-Subtract Operations.
4566 def VFMAfd : N3VDMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACD, "vfma", "f32",
4567 v2f32, fmul_su, fadd_mlx>,
4568 Requires<[HasNEON,HasVFP4,UseFusedMAC]>;
4570 def VFMAfq : N3VQMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACQ, "vfma", "f32",
4571 v4f32, fmul_su, fadd_mlx>,
4572 Requires<[HasNEON,HasVFP4,UseFusedMAC]>;
4574 // Fused Vector Multiply Subtract (floating-point)
4575 def VFMSfd : N3VDMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACD, "vfms", "f32",
4576 v2f32, fmul_su, fsub_mlx>,
4577 Requires<[HasNEON,HasVFP4,UseFusedMAC]>;
4578 def VFMSfq : N3VQMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACQ, "vfms", "f32",
4579 v4f32, fmul_su, fsub_mlx>,
4580 Requires<[HasNEON,HasVFP4,UseFusedMAC]>;
4582 // Match @llvm.fma.* intrinsics
4583 def : Pat<(v2f32 (fma DPR:$Vn, DPR:$Vm, DPR:$src1)),
4584 (VFMAfd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4585 Requires<[HasVFP4]>;
4586 def : Pat<(v4f32 (fma QPR:$Vn, QPR:$Vm, QPR:$src1)),
4587 (VFMAfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4588 Requires<[HasVFP4]>;
4589 def : Pat<(v2f32 (fma (fneg DPR:$Vn), DPR:$Vm, DPR:$src1)),
4590 (VFMSfd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4591 Requires<[HasVFP4]>;
4592 def : Pat<(v4f32 (fma (fneg QPR:$Vn), QPR:$Vm, QPR:$src1)),
4593 (VFMSfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4594 Requires<[HasVFP4]>;
4596 // Vector Subtract Operations.
4598 // VSUB : Vector Subtract (integer and floating-point)
4599 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
4600 "vsub", "i", sub, 0>;
4601 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
4602 v2f32, v2f32, fsub, 0>;
4603 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
4604 v4f32, v4f32, fsub, 0>;
4605 // VSUBL : Vector Subtract Long (Q = D - D)
4606 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
4607 "vsubl", "s", sub, sext, 0>;
4608 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
4609 "vsubl", "u", sub, zext, 0>;
4610 // VSUBW : Vector Subtract Wide (Q = Q - D)
4611 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
4612 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
4613 // VHSUB : Vector Halving Subtract
4614 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
4615 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4616 "vhsub", "s", int_arm_neon_vhsubs, 0>;
4617 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
4618 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4619 "vhsub", "u", int_arm_neon_vhsubu, 0>;
4620 // VQSUB : Vector Saturing Subtract
4621 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
4622 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4623 "vqsub", "s", int_arm_neon_vqsubs, 0>;
4624 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
4625 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4626 "vqsub", "u", int_arm_neon_vqsubu, 0>;
4627 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
4628 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i", null_frag, 0>;
4629 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
4630 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
4631 int_arm_neon_vrsubhn, 0>;
4633 def : Pat<(v8i8 (trunc (NEONvshru (sub (v8i16 QPR:$Vn), QPR:$Vm), 8))),
4634 (VSUBHNv8i8 QPR:$Vn, QPR:$Vm)>;
4635 def : Pat<(v4i16 (trunc (NEONvshru (sub (v4i32 QPR:$Vn), QPR:$Vm), 16))),
4636 (VSUBHNv4i16 QPR:$Vn, QPR:$Vm)>;
4637 def : Pat<(v2i32 (trunc (NEONvshru (sub (v2i64 QPR:$Vn), QPR:$Vm), 32))),
4638 (VSUBHNv2i32 QPR:$Vn, QPR:$Vm)>;
4640 // Vector Comparisons.
4642 // VCEQ : Vector Compare Equal
4643 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4644 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
4645 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
4647 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
4650 let TwoOperandAliasConstraint = "$Vm = $Vd" in
4651 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
4652 "$Vd, $Vm, #0", NEONvceqz>;
4654 // VCGE : Vector Compare Greater Than or Equal
4655 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4656 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
4657 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4658 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
4659 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
4661 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
4664 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
4665 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
4666 "$Vd, $Vm, #0", NEONvcgez>;
4667 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
4668 "$Vd, $Vm, #0", NEONvclez>;
4671 // VCGT : Vector Compare Greater Than
4672 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4673 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
4674 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4675 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
4676 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
4678 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
4681 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
4682 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
4683 "$Vd, $Vm, #0", NEONvcgtz>;
4684 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
4685 "$Vd, $Vm, #0", NEONvcltz>;
4688 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
4689 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
4690 "f32", v2i32, v2f32, int_arm_neon_vacge, 0>;
4691 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
4692 "f32", v4i32, v4f32, int_arm_neon_vacge, 0>;
4693 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
4694 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
4695 "f32", v2i32, v2f32, int_arm_neon_vacgt, 0>;
4696 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
4697 "f32", v4i32, v4f32, int_arm_neon_vacgt, 0>;
4698 // VTST : Vector Test Bits
4699 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
4700 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
4702 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vn, $Vm",
4703 (VACGTd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
4704 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vn, $Vm",
4705 (VACGTq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
4706 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vn, $Vm",
4707 (VACGEd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
4708 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vn, $Vm",
4709 (VACGEq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
4711 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vm",
4712 (VACGTd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
4713 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vm",
4714 (VACGTq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
4715 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vm",
4716 (VACGEd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
4717 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vm",
4718 (VACGEq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
4720 // Vector Bitwise Operations.
4722 def vnotd : PatFrag<(ops node:$in),
4723 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
4724 def vnotq : PatFrag<(ops node:$in),
4725 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
4728 // VAND : Vector Bitwise AND
4729 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
4730 v2i32, v2i32, and, 1>;
4731 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
4732 v4i32, v4i32, and, 1>;
4734 // VEOR : Vector Bitwise Exclusive OR
4735 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
4736 v2i32, v2i32, xor, 1>;
4737 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
4738 v4i32, v4i32, xor, 1>;
4740 // VORR : Vector Bitwise OR
4741 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
4742 v2i32, v2i32, or, 1>;
4743 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
4744 v4i32, v4i32, or, 1>;
4746 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
4747 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4749 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4751 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4752 let Inst{9} = SIMM{9};
4755 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
4756 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4758 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4760 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4761 let Inst{10-9} = SIMM{10-9};
4764 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
4765 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4767 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4769 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4770 let Inst{9} = SIMM{9};
4773 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
4774 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4776 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4778 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4779 let Inst{10-9} = SIMM{10-9};
4783 // VBIC : Vector Bitwise Bit Clear (AND NOT)
4784 let TwoOperandAliasConstraint = "$Vn = $Vd" in {
4785 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4786 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
4787 "vbic", "$Vd, $Vn, $Vm", "",
4788 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
4789 (vnotd DPR:$Vm))))]>;
4790 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4791 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4792 "vbic", "$Vd, $Vn, $Vm", "",
4793 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
4794 (vnotq QPR:$Vm))))]>;
4797 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
4798 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4800 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4802 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4803 let Inst{9} = SIMM{9};
4806 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
4807 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4809 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4811 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4812 let Inst{10-9} = SIMM{10-9};
4815 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
4816 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4818 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4820 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4821 let Inst{9} = SIMM{9};
4824 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
4825 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4827 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4829 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4830 let Inst{10-9} = SIMM{10-9};
4833 // VORN : Vector Bitwise OR NOT
4834 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
4835 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
4836 "vorn", "$Vd, $Vn, $Vm", "",
4837 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
4838 (vnotd DPR:$Vm))))]>;
4839 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
4840 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4841 "vorn", "$Vd, $Vn, $Vm", "",
4842 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
4843 (vnotq QPR:$Vm))))]>;
4845 // VMVN : Vector Bitwise NOT (Immediate)
4847 let isReMaterializable = 1 in {
4849 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
4850 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4851 "vmvn", "i16", "$Vd, $SIMM", "",
4852 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
4853 let Inst{9} = SIMM{9};
4856 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
4857 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4858 "vmvn", "i16", "$Vd, $SIMM", "",
4859 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
4860 let Inst{9} = SIMM{9};
4863 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
4864 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4865 "vmvn", "i32", "$Vd, $SIMM", "",
4866 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
4867 let Inst{11-8} = SIMM{11-8};
4870 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
4871 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4872 "vmvn", "i32", "$Vd, $SIMM", "",
4873 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
4874 let Inst{11-8} = SIMM{11-8};
4878 // VMVN : Vector Bitwise NOT
4879 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
4880 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
4881 "vmvn", "$Vd, $Vm", "",
4882 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
4883 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
4884 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
4885 "vmvn", "$Vd, $Vm", "",
4886 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
4887 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
4888 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
4890 // VBSL : Vector Bitwise Select
4891 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4892 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4893 N3RegFrm, IIC_VCNTiD,
4894 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4896 (v2i32 (NEONvbsl DPR:$src1, DPR:$Vn, DPR:$Vm)))]>;
4897 def : Pat<(v8i8 (int_arm_neon_vbsl (v8i8 DPR:$src1),
4898 (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))),
4899 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4900 Requires<[HasNEON]>;
4901 def : Pat<(v4i16 (int_arm_neon_vbsl (v4i16 DPR:$src1),
4902 (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))),
4903 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4904 Requires<[HasNEON]>;
4905 def : Pat<(v2i32 (int_arm_neon_vbsl (v2i32 DPR:$src1),
4906 (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))),
4907 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4908 Requires<[HasNEON]>;
4909 def : Pat<(v2f32 (int_arm_neon_vbsl (v2f32 DPR:$src1),
4910 (v2f32 DPR:$Vn), (v2f32 DPR:$Vm))),
4911 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4912 Requires<[HasNEON]>;
4913 def : Pat<(v1i64 (int_arm_neon_vbsl (v1i64 DPR:$src1),
4914 (v1i64 DPR:$Vn), (v1i64 DPR:$Vm))),
4915 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4916 Requires<[HasNEON]>;
4918 def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
4919 (and DPR:$Vm, (vnotd DPR:$Vd)))),
4920 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>,
4921 Requires<[HasNEON]>;
4923 def : Pat<(v1i64 (or (and DPR:$Vn, DPR:$Vd),
4924 (and DPR:$Vm, (vnotd DPR:$Vd)))),
4925 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>,
4926 Requires<[HasNEON]>;
4928 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4929 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4930 N3RegFrm, IIC_VCNTiQ,
4931 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4933 (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>;
4935 def : Pat<(v16i8 (int_arm_neon_vbsl (v16i8 QPR:$src1),
4936 (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))),
4937 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4938 Requires<[HasNEON]>;
4939 def : Pat<(v8i16 (int_arm_neon_vbsl (v8i16 QPR:$src1),
4940 (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))),
4941 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4942 Requires<[HasNEON]>;
4943 def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 QPR:$src1),
4944 (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))),
4945 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4946 Requires<[HasNEON]>;
4947 def : Pat<(v4f32 (int_arm_neon_vbsl (v4f32 QPR:$src1),
4948 (v4f32 QPR:$Vn), (v4f32 QPR:$Vm))),
4949 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4950 Requires<[HasNEON]>;
4951 def : Pat<(v2i64 (int_arm_neon_vbsl (v2i64 QPR:$src1),
4952 (v2i64 QPR:$Vn), (v2i64 QPR:$Vm))),
4953 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4954 Requires<[HasNEON]>;
4956 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
4957 (and QPR:$Vm, (vnotq QPR:$Vd)))),
4958 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>,
4959 Requires<[HasNEON]>;
4960 def : Pat<(v2i64 (or (and QPR:$Vn, QPR:$Vd),
4961 (and QPR:$Vm, (vnotq QPR:$Vd)))),
4962 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>,
4963 Requires<[HasNEON]>;
4965 // VBIF : Vector Bitwise Insert if False
4966 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
4967 // FIXME: This instruction's encoding MAY NOT BE correct.
4968 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
4969 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4970 N3RegFrm, IIC_VBINiD,
4971 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4973 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
4974 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4975 N3RegFrm, IIC_VBINiQ,
4976 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4979 // VBIT : Vector Bitwise Insert if True
4980 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
4981 // FIXME: This instruction's encoding MAY NOT BE correct.
4982 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
4983 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4984 N3RegFrm, IIC_VBINiD,
4985 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4987 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
4988 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4989 N3RegFrm, IIC_VBINiQ,
4990 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4993 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
4994 // for equivalent operations with different register constraints; it just
4997 // Vector Absolute Differences.
4999 // VABD : Vector Absolute Difference
5000 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
5001 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
5002 "vabd", "s", int_arm_neon_vabds, 1>;
5003 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
5004 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
5005 "vabd", "u", int_arm_neon_vabdu, 1>;
5006 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
5007 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
5008 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
5009 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
5011 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
5012 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
5013 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
5014 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
5015 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
5017 // VABA : Vector Absolute Difference and Accumulate
5018 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
5019 "vaba", "s", int_arm_neon_vabds, add>;
5020 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
5021 "vaba", "u", int_arm_neon_vabdu, add>;
5023 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
5024 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
5025 "vabal", "s", int_arm_neon_vabds, zext, add>;
5026 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
5027 "vabal", "u", int_arm_neon_vabdu, zext, add>;
5029 // Vector Maximum and Minimum.
5031 // VMAX : Vector Maximum
5032 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
5033 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
5034 "vmax", "s", int_arm_neon_vmaxs, 1>;
5035 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
5036 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
5037 "vmax", "u", int_arm_neon_vmaxu, 1>;
5038 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
5040 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
5041 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
5043 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
5046 let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
5047 def VMAXNMND : N3VDIntnp<0b00110, 0b00, 0b1111, 0, 1,
5048 N3RegFrm, NoItinerary, "vmaxnm", "f32",
5049 v2f32, v2f32, int_arm_neon_vmaxnm, 1>,
5050 Requires<[HasV8, HasNEON]>;
5051 def VMAXNMNQ : N3VQIntnp<0b00110, 0b00, 0b1111, 1, 1,
5052 N3RegFrm, NoItinerary, "vmaxnm", "f32",
5053 v4f32, v4f32, int_arm_neon_vmaxnm, 1>,
5054 Requires<[HasV8, HasNEON]>;
5057 // VMIN : Vector Minimum
5058 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
5059 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
5060 "vmin", "s", int_arm_neon_vmins, 1>;
5061 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
5062 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
5063 "vmin", "u", int_arm_neon_vminu, 1>;
5064 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
5066 v2f32, v2f32, int_arm_neon_vmins, 1>;
5067 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
5069 v4f32, v4f32, int_arm_neon_vmins, 1>;
5072 let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
5073 def VMINNMND : N3VDIntnp<0b00110, 0b10, 0b1111, 0, 1,
5074 N3RegFrm, NoItinerary, "vminnm", "f32",
5075 v2f32, v2f32, int_arm_neon_vminnm, 1>,
5076 Requires<[HasV8, HasNEON]>;
5077 def VMINNMNQ : N3VQIntnp<0b00110, 0b10, 0b1111, 1, 1,
5078 N3RegFrm, NoItinerary, "vminnm", "f32",
5079 v4f32, v4f32, int_arm_neon_vminnm, 1>,
5080 Requires<[HasV8, HasNEON]>;
5083 // Vector Pairwise Operations.
5085 // VPADD : Vector Pairwise Add
5086 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
5088 v8i8, v8i8, int_arm_neon_vpadd, 0>;
5089 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
5091 v4i16, v4i16, int_arm_neon_vpadd, 0>;
5092 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
5094 v2i32, v2i32, int_arm_neon_vpadd, 0>;
5095 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
5096 IIC_VPBIND, "vpadd", "f32",
5097 v2f32, v2f32, int_arm_neon_vpadd, 0>;
5099 // VPADDL : Vector Pairwise Add Long
5100 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
5101 int_arm_neon_vpaddls>;
5102 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
5103 int_arm_neon_vpaddlu>;
5105 // VPADAL : Vector Pairwise Add and Accumulate Long
5106 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
5107 int_arm_neon_vpadals>;
5108 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
5109 int_arm_neon_vpadalu>;
5111 // VPMAX : Vector Pairwise Maximum
5112 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
5113 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
5114 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
5115 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
5116 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
5117 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
5118 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
5119 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
5120 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
5121 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
5122 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
5123 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
5124 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
5125 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
5127 // VPMIN : Vector Pairwise Minimum
5128 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
5129 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
5130 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
5131 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
5132 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
5133 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
5134 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
5135 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
5136 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
5137 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
5138 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
5139 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
5140 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
5141 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
5143 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
5145 // VRECPE : Vector Reciprocal Estimate
5146 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
5147 IIC_VUNAD, "vrecpe", "u32",
5148 v2i32, v2i32, int_arm_neon_vrecpe>;
5149 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
5150 IIC_VUNAQ, "vrecpe", "u32",
5151 v4i32, v4i32, int_arm_neon_vrecpe>;
5152 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
5153 IIC_VUNAD, "vrecpe", "f32",
5154 v2f32, v2f32, int_arm_neon_vrecpe>;
5155 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
5156 IIC_VUNAQ, "vrecpe", "f32",
5157 v4f32, v4f32, int_arm_neon_vrecpe>;
5159 // VRECPS : Vector Reciprocal Step
5160 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
5161 IIC_VRECSD, "vrecps", "f32",
5162 v2f32, v2f32, int_arm_neon_vrecps, 1>;
5163 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
5164 IIC_VRECSQ, "vrecps", "f32",
5165 v4f32, v4f32, int_arm_neon_vrecps, 1>;
5167 // VRSQRTE : Vector Reciprocal Square Root Estimate
5168 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
5169 IIC_VUNAD, "vrsqrte", "u32",
5170 v2i32, v2i32, int_arm_neon_vrsqrte>;
5171 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
5172 IIC_VUNAQ, "vrsqrte", "u32",
5173 v4i32, v4i32, int_arm_neon_vrsqrte>;
5174 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
5175 IIC_VUNAD, "vrsqrte", "f32",
5176 v2f32, v2f32, int_arm_neon_vrsqrte>;
5177 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
5178 IIC_VUNAQ, "vrsqrte", "f32",
5179 v4f32, v4f32, int_arm_neon_vrsqrte>;
5181 // VRSQRTS : Vector Reciprocal Square Root Step
5182 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
5183 IIC_VRECSD, "vrsqrts", "f32",
5184 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
5185 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
5186 IIC_VRECSQ, "vrsqrts", "f32",
5187 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
5191 // VSHL : Vector Shift
5192 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
5193 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
5194 "vshl", "s", int_arm_neon_vshifts>;
5195 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
5196 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
5197 "vshl", "u", int_arm_neon_vshiftu>;
5199 // VSHL : Vector Shift Left (Immediate)
5200 defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
5202 // VSHR : Vector Shift Right (Immediate)
5203 defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", "VSHRs",
5205 defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", "VSHRu",
5208 // VSHLL : Vector Shift Left Long
5209 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s",
5210 PatFrag<(ops node:$LHS, node:$RHS), (NEONvshl (sext node:$LHS), node:$RHS)>>;
5211 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u",
5212 PatFrag<(ops node:$LHS, node:$RHS), (NEONvshl (zext node:$LHS), node:$RHS)>>;
5214 // VSHLL : Vector Shift Left Long (with maximum shift count)
5215 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
5216 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
5217 ValueType OpTy, Operand ImmTy>
5218 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
5219 ResTy, OpTy, ImmTy, null_frag> {
5220 let Inst{21-16} = op21_16;
5221 let DecoderMethod = "DecodeVSHLMaxInstruction";
5223 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
5225 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
5226 v4i32, v4i16, imm16>;
5227 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
5228 v2i64, v2i32, imm32>;
5230 def : Pat<(v8i16 (NEONvshl (zext (v8i8 DPR:$Rn)), (i32 8))),
5231 (VSHLLi8 DPR:$Rn, 8)>;
5232 def : Pat<(v4i32 (NEONvshl (zext (v4i16 DPR:$Rn)), (i32 16))),
5233 (VSHLLi16 DPR:$Rn, 16)>;
5234 def : Pat<(v2i64 (NEONvshl (zext (v2i32 DPR:$Rn)), (i32 32))),
5235 (VSHLLi32 DPR:$Rn, 32)>;
5236 def : Pat<(v8i16 (NEONvshl (sext (v8i8 DPR:$Rn)), (i32 8))),
5237 (VSHLLi8 DPR:$Rn, 8)>;
5238 def : Pat<(v4i32 (NEONvshl (sext (v4i16 DPR:$Rn)), (i32 16))),
5239 (VSHLLi16 DPR:$Rn, 16)>;
5240 def : Pat<(v2i64 (NEONvshl (sext (v2i32 DPR:$Rn)), (i32 32))),
5241 (VSHLLi32 DPR:$Rn, 32)>;
5243 // VSHRN : Vector Shift Right and Narrow
5244 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
5245 PatFrag<(ops node:$Rn, node:$amt),
5246 (trunc (NEONvshrs node:$Rn, node:$amt))>>;
5248 def : Pat<(v8i8 (trunc (NEONvshru (v8i16 QPR:$Vn), shr_imm8:$amt))),
5249 (VSHRNv8i8 QPR:$Vn, shr_imm8:$amt)>;
5250 def : Pat<(v4i16 (trunc (NEONvshru (v4i32 QPR:$Vn), shr_imm16:$amt))),
5251 (VSHRNv4i16 QPR:$Vn, shr_imm16:$amt)>;
5252 def : Pat<(v2i32 (trunc (NEONvshru (v2i64 QPR:$Vn), shr_imm32:$amt))),
5253 (VSHRNv2i32 QPR:$Vn, shr_imm32:$amt)>;
5255 // VRSHL : Vector Rounding Shift
5256 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
5257 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5258 "vrshl", "s", int_arm_neon_vrshifts>;
5259 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
5260 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5261 "vrshl", "u", int_arm_neon_vrshiftu>;
5262 // VRSHR : Vector Rounding Shift Right
5263 defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", "VRSHRs",
5265 defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", "VRSHRu",
5268 // VRSHRN : Vector Rounding Shift Right and Narrow
5269 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
5272 // VQSHL : Vector Saturating Shift
5273 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
5274 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5275 "vqshl", "s", int_arm_neon_vqshifts>;
5276 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
5277 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5278 "vqshl", "u", int_arm_neon_vqshiftu>;
5279 // VQSHL : Vector Saturating Shift Left (Immediate)
5280 defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls>;
5281 defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu>;
5283 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
5284 defm VQSHLsu : N2VShL_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu>;
5286 // VQSHRN : Vector Saturating Shift Right and Narrow
5287 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
5289 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
5292 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
5293 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
5296 // VQRSHL : Vector Saturating Rounding Shift
5297 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
5298 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5299 "vqrshl", "s", int_arm_neon_vqrshifts>;
5300 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
5301 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5302 "vqrshl", "u", int_arm_neon_vqrshiftu>;
5304 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
5305 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
5307 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
5310 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
5311 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
5314 // VSRA : Vector Shift Right and Accumulate
5315 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
5316 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
5317 // VRSRA : Vector Rounding Shift Right and Accumulate
5318 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
5319 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
5321 // VSLI : Vector Shift Left and Insert
5322 defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">;
5324 // VSRI : Vector Shift Right and Insert
5325 defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;
5327 // Vector Absolute and Saturating Absolute.
5329 // VABS : Vector Absolute Value
5330 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
5331 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
5333 def VABSfd : N2VD<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
5335 v2f32, v2f32, fabs>;
5336 def VABSfq : N2VQ<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
5338 v4f32, v4f32, fabs>;
5340 def : Pat<(xor (v2i32 (bitconvert (v8i8 (NEONvshrs DPR:$src, (i32 7))))),
5341 (v2i32 (bitconvert (v8i8 (add DPR:$src,
5342 (NEONvshrs DPR:$src, (i32 7))))))),
5343 (VABSv8i8 DPR:$src)>;
5344 def : Pat<(xor (v2i32 (bitconvert (v4i16 (NEONvshrs DPR:$src, (i32 15))))),
5345 (v2i32 (bitconvert (v4i16 (add DPR:$src,
5346 (NEONvshrs DPR:$src, (i32 15))))))),
5347 (VABSv4i16 DPR:$src)>;
5348 def : Pat<(xor (v2i32 (NEONvshrs DPR:$src, (i32 31))),
5349 (v2i32 (add DPR:$src, (NEONvshrs DPR:$src, (i32 31))))),
5350 (VABSv2i32 DPR:$src)>;
5351 def : Pat<(xor (v4i32 (bitconvert (v16i8 (NEONvshrs QPR:$src, (i32 7))))),
5352 (v4i32 (bitconvert (v16i8 (add QPR:$src,
5353 (NEONvshrs QPR:$src, (i32 7))))))),
5354 (VABSv16i8 QPR:$src)>;
5355 def : Pat<(xor (v4i32 (bitconvert (v8i16 (NEONvshrs QPR:$src, (i32 15))))),
5356 (v4i32 (bitconvert (v8i16 (add QPR:$src,
5357 (NEONvshrs QPR:$src, (i32 15))))))),
5358 (VABSv8i16 QPR:$src)>;
5359 def : Pat<(xor (v4i32 (NEONvshrs QPR:$src, (i32 31))),
5360 (v4i32 (add QPR:$src, (NEONvshrs QPR:$src, (i32 31))))),
5361 (VABSv4i32 QPR:$src)>;
5363 // VQABS : Vector Saturating Absolute Value
5364 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
5365 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
5366 int_arm_neon_vqabs>;
5370 def vnegd : PatFrag<(ops node:$in),
5371 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
5372 def vnegq : PatFrag<(ops node:$in),
5373 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
5375 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
5376 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
5377 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
5378 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
5379 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
5380 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
5381 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
5382 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
5384 // VNEG : Vector Negate (integer)
5385 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
5386 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
5387 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
5388 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
5389 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
5390 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
5392 // VNEG : Vector Negate (floating-point)
5393 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
5394 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
5395 "vneg", "f32", "$Vd, $Vm", "",
5396 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
5397 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
5398 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
5399 "vneg", "f32", "$Vd, $Vm", "",
5400 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
5402 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
5403 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
5404 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
5405 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
5406 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
5407 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
5409 // VQNEG : Vector Saturating Negate
5410 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
5411 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
5412 int_arm_neon_vqneg>;
5414 // Vector Bit Counting Operations.
5416 // VCLS : Vector Count Leading Sign Bits
5417 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
5418 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
5420 // VCLZ : Vector Count Leading Zeros
5421 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
5422 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
5424 // VCNT : Vector Count One Bits
5425 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
5426 IIC_VCNTiD, "vcnt", "8",
5428 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
5429 IIC_VCNTiQ, "vcnt", "8",
5430 v16i8, v16i8, ctpop>;
5433 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
5434 (outs DPR:$Vd, DPR:$Vm), (ins DPR:$in1, DPR:$in2),
5435 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
5437 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
5438 (outs QPR:$Vd, QPR:$Vm), (ins QPR:$in1, QPR:$in2),
5439 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
5442 // Vector Move Operations.
5444 // VMOV : Vector Move (Register)
5445 def : NEONInstAlias<"vmov${p} $Vd, $Vm",
5446 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
5447 def : NEONInstAlias<"vmov${p} $Vd, $Vm",
5448 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
5450 // VMOV : Vector Move (Immediate)
5452 let isReMaterializable = 1 in {
5453 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
5454 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
5455 "vmov", "i8", "$Vd, $SIMM", "",
5456 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
5457 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
5458 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
5459 "vmov", "i8", "$Vd, $SIMM", "",
5460 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
5462 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
5463 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
5464 "vmov", "i16", "$Vd, $SIMM", "",
5465 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
5466 let Inst{9} = SIMM{9};
5469 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
5470 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
5471 "vmov", "i16", "$Vd, $SIMM", "",
5472 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
5473 let Inst{9} = SIMM{9};
5476 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
5477 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
5478 "vmov", "i32", "$Vd, $SIMM", "",
5479 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
5480 let Inst{11-8} = SIMM{11-8};
5483 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
5484 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
5485 "vmov", "i32", "$Vd, $SIMM", "",
5486 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
5487 let Inst{11-8} = SIMM{11-8};
5490 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
5491 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
5492 "vmov", "i64", "$Vd, $SIMM", "",
5493 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
5494 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
5495 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
5496 "vmov", "i64", "$Vd, $SIMM", "",
5497 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
5499 def VMOVv2f32 : N1ModImm<1, 0b000, 0b1111, 0, 0, 0, 1, (outs DPR:$Vd),
5500 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
5501 "vmov", "f32", "$Vd, $SIMM", "",
5502 [(set DPR:$Vd, (v2f32 (NEONvmovFPImm timm:$SIMM)))]>;
5503 def VMOVv4f32 : N1ModImm<1, 0b000, 0b1111, 0, 1, 0, 1, (outs QPR:$Vd),
5504 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
5505 "vmov", "f32", "$Vd, $SIMM", "",
5506 [(set QPR:$Vd, (v4f32 (NEONvmovFPImm timm:$SIMM)))]>;
5507 } // isReMaterializable
5509 // Add support for bytes replication feature, so it could be GAS compatible.
5510 // E.g. instructions below:
5511 // "vmov.i32 d0, 0xffffffff"
5512 // "vmov.i32 d0, 0xabababab"
5513 // "vmov.i16 d0, 0xabab"
5514 // are incorrect, but we could deal with such cases.
5515 // For last two instructions, for example, it should emit:
5516 // "vmov.i8 d0, 0xab"
5517 def : NEONInstAlias<"vmov${p}.i16 $Vd, $Vm",
5518 (VMOVv8i8 DPR:$Vd, nImmVMOVI16ByteReplicate:$Vm, pred:$p)>;
5519 def : NEONInstAlias<"vmov${p}.i32 $Vd, $Vm",
5520 (VMOVv8i8 DPR:$Vd, nImmVMOVI32ByteReplicate:$Vm, pred:$p)>;
5521 def : NEONInstAlias<"vmov${p}.i16 $Vd, $Vm",
5522 (VMOVv16i8 QPR:$Vd, nImmVMOVI16ByteReplicate:$Vm, pred:$p)>;
5523 def : NEONInstAlias<"vmov${p}.i32 $Vd, $Vm",
5524 (VMOVv16i8 QPR:$Vd, nImmVMOVI32ByteReplicate:$Vm, pred:$p)>;
5526 // Also add same support for VMVN instructions. So instruction:
5527 // "vmvn.i32 d0, 0xabababab"
5529 // "vmov.i8 d0, 0x54"
5530 def : NEONInstAlias<"vmvn${p}.i16 $Vd, $Vm",
5531 (VMOVv8i8 DPR:$Vd, nImmVMVNI16ByteReplicate:$Vm, pred:$p)>;
5532 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $Vm",
5533 (VMOVv8i8 DPR:$Vd, nImmVMVNI32ByteReplicate:$Vm, pred:$p)>;
5534 def : NEONInstAlias<"vmvn${p}.i16 $Vd, $Vm",
5535 (VMOVv16i8 QPR:$Vd, nImmVMVNI16ByteReplicate:$Vm, pred:$p)>;
5536 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $Vm",
5537 (VMOVv16i8 QPR:$Vd, nImmVMVNI32ByteReplicate:$Vm, pred:$p)>;
5539 // On some CPUs the two instructions "vmov.i32 dD, #0" and "vmov.i32 qD, #0"
5540 // require zero cycles to execute so they should be used wherever possible for
5541 // setting a register to zero.
5543 // Even without these pseudo-insts we would probably end up with the correct
5544 // instruction, but we could not mark the general ones with "isAsCheapAsAMove"
5545 // since they are sometimes rather expensive (in general).
5547 let AddedComplexity = 50, isAsCheapAsAMove = 1, isReMaterializable = 1 in {
5548 def VMOVD0 : ARMPseudoExpand<(outs DPR:$Vd), (ins), 4, IIC_VMOVImm,
5549 [(set DPR:$Vd, (v2i32 NEONimmAllZerosV))],
5550 (VMOVv2i32 DPR:$Vd, 0, (ops 14, zero_reg))>,
5552 def VMOVQ0 : ARMPseudoExpand<(outs QPR:$Vd), (ins), 4, IIC_VMOVImm,
5553 [(set QPR:$Vd, (v4i32 NEONimmAllZerosV))],
5554 (VMOVv4i32 QPR:$Vd, 0, (ops 14, zero_reg))>,
5558 // VMOV : Vector Get Lane (move scalar to ARM core register)
5560 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
5561 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
5562 IIC_VMOVSI, "vmov", "s8", "$R, $V$lane",
5563 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
5565 let Inst{21} = lane{2};
5566 let Inst{6-5} = lane{1-0};
5568 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
5569 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
5570 IIC_VMOVSI, "vmov", "s16", "$R, $V$lane",
5571 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
5573 let Inst{21} = lane{1};
5574 let Inst{6} = lane{0};
5576 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
5577 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
5578 IIC_VMOVSI, "vmov", "u8", "$R, $V$lane",
5579 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
5581 let Inst{21} = lane{2};
5582 let Inst{6-5} = lane{1-0};
5584 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
5585 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
5586 IIC_VMOVSI, "vmov", "u16", "$R, $V$lane",
5587 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
5589 let Inst{21} = lane{1};
5590 let Inst{6} = lane{0};
5592 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
5593 (outs GPR:$R), (ins DPR:$V, VectorIndex32:$lane),
5594 IIC_VMOVSI, "vmov", "32", "$R, $V$lane",
5595 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
5597 Requires<[HasVFP2, HasFastVGETLNi32]> {
5598 let Inst{21} = lane{0};
5600 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
5601 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
5602 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
5603 (DSubReg_i8_reg imm:$lane))),
5604 (SubReg_i8_lane imm:$lane))>;
5605 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
5606 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
5607 (DSubReg_i16_reg imm:$lane))),
5608 (SubReg_i16_lane imm:$lane))>;
5609 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
5610 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
5611 (DSubReg_i8_reg imm:$lane))),
5612 (SubReg_i8_lane imm:$lane))>;
5613 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
5614 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
5615 (DSubReg_i16_reg imm:$lane))),
5616 (SubReg_i16_lane imm:$lane))>;
5617 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
5618 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
5619 (DSubReg_i32_reg imm:$lane))),
5620 (SubReg_i32_lane imm:$lane))>,
5621 Requires<[HasNEON, HasFastVGETLNi32]>;
5622 def : Pat<(extractelt (v2i32 DPR:$src), imm:$lane),
5624 (i32 (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane))), GPR)>,
5625 Requires<[HasNEON, HasSlowVGETLNi32]>;
5626 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
5628 (i32 (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane))), GPR)>,
5629 Requires<[HasNEON, HasSlowVGETLNi32]>;
5630 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
5631 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
5632 (SSubReg_f32_reg imm:$src2))>;
5633 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
5634 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
5635 (SSubReg_f32_reg imm:$src2))>;
5636 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
5637 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
5638 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
5639 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
5642 // VMOV : Vector Set Lane (move ARM core register to scalar)
5644 let Constraints = "$src1 = $V" in {
5645 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
5646 (ins DPR:$src1, GPR:$R, VectorIndex8:$lane),
5647 IIC_VMOVISL, "vmov", "8", "$V$lane, $R",
5648 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
5649 GPR:$R, imm:$lane))]> {
5650 let Inst{21} = lane{2};
5651 let Inst{6-5} = lane{1-0};
5653 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
5654 (ins DPR:$src1, GPR:$R, VectorIndex16:$lane),
5655 IIC_VMOVISL, "vmov", "16", "$V$lane, $R",
5656 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
5657 GPR:$R, imm:$lane))]> {
5658 let Inst{21} = lane{1};
5659 let Inst{6} = lane{0};
5661 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
5662 (ins DPR:$src1, GPR:$R, VectorIndex32:$lane),
5663 IIC_VMOVISL, "vmov", "32", "$V$lane, $R",
5664 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
5665 GPR:$R, imm:$lane))]>,
5666 Requires<[HasVFP2]> {
5667 let Inst{21} = lane{0};
5668 // This instruction is equivalent as
5669 // $V = INSERT_SUBREG $src1, $R, translateImmToSubIdx($imm)
5670 let isInsertSubreg = 1;
5673 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
5674 (v16i8 (INSERT_SUBREG QPR:$src1,
5675 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
5676 (DSubReg_i8_reg imm:$lane))),
5677 GPR:$src2, (SubReg_i8_lane imm:$lane))),
5678 (DSubReg_i8_reg imm:$lane)))>;
5679 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
5680 (v8i16 (INSERT_SUBREG QPR:$src1,
5681 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
5682 (DSubReg_i16_reg imm:$lane))),
5683 GPR:$src2, (SubReg_i16_lane imm:$lane))),
5684 (DSubReg_i16_reg imm:$lane)))>;
5685 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
5686 (v4i32 (INSERT_SUBREG QPR:$src1,
5687 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
5688 (DSubReg_i32_reg imm:$lane))),
5689 GPR:$src2, (SubReg_i32_lane imm:$lane))),
5690 (DSubReg_i32_reg imm:$lane)))>;
5692 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
5693 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
5694 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
5695 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
5696 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
5697 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
5699 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
5700 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
5701 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
5702 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
5704 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
5705 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
5706 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
5707 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
5708 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
5709 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
5711 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
5712 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5713 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
5714 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5715 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
5716 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5718 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
5719 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
5720 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
5722 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
5723 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
5724 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
5726 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
5727 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
5728 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
5731 // VDUP : Vector Duplicate (from ARM core register to all elements)
5733 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
5734 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
5735 IIC_VMOVIS, "vdup", Dt, "$V, $R",
5736 [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
5737 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
5738 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
5739 IIC_VMOVIS, "vdup", Dt, "$V, $R",
5740 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
5742 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
5743 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
5744 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>,
5745 Requires<[HasNEON, HasFastVDUP32]>;
5746 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
5747 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
5748 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
5750 // NEONvdup patterns for uarchs with fast VDUP.32.
5751 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32d GPR:$R)>,
5752 Requires<[HasNEON,HasFastVDUP32]>;
5753 def : Pat<(v4f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32q GPR:$R)>;
5755 // NEONvdup patterns for uarchs with slow VDUP.32 - use VMOVDRR instead.
5756 def : Pat<(v2i32 (NEONvdup (i32 GPR:$R))), (VMOVDRR GPR:$R, GPR:$R)>,
5757 Requires<[HasNEON,HasSlowVDUP32]>;
5758 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VMOVDRR GPR:$R, GPR:$R)>,
5759 Requires<[HasNEON,HasSlowVDUP32]>;
5761 // VDUP : Vector Duplicate Lane (from scalar to all elements)
5763 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
5764 ValueType Ty, Operand IdxTy>
5765 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
5766 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm$lane",
5767 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
5769 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
5770 ValueType ResTy, ValueType OpTy, Operand IdxTy>
5771 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
5772 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm$lane",
5773 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
5774 VectorIndex32:$lane)))]>;
5776 // Inst{19-16} is partially specified depending on the element size.
5778 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8, VectorIndex8> {
5780 let Inst{19-17} = lane{2-0};
5782 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16, VectorIndex16> {
5784 let Inst{19-18} = lane{1-0};
5786 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32, VectorIndex32> {
5788 let Inst{19} = lane{0};
5790 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8, VectorIndex8> {
5792 let Inst{19-17} = lane{2-0};
5794 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16, VectorIndex16> {
5796 let Inst{19-18} = lane{1-0};
5798 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32, VectorIndex32> {
5800 let Inst{19} = lane{0};
5803 def : Pat<(v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
5804 (VDUPLN32d DPR:$Vm, imm:$lane)>;
5806 def : Pat<(v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
5807 (VDUPLN32q DPR:$Vm, imm:$lane)>;
5809 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
5810 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
5811 (DSubReg_i8_reg imm:$lane))),
5812 (SubReg_i8_lane imm:$lane)))>;
5813 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
5814 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
5815 (DSubReg_i16_reg imm:$lane))),
5816 (SubReg_i16_lane imm:$lane)))>;
5817 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
5818 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
5819 (DSubReg_i32_reg imm:$lane))),
5820 (SubReg_i32_lane imm:$lane)))>;
5821 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
5822 (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src,
5823 (DSubReg_i32_reg imm:$lane))),
5824 (SubReg_i32_lane imm:$lane)))>;
5826 def : Pat<(v2f32 (NEONvdup (f32 SPR:$src))),
5827 (v2f32 (VDUPLN32d (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
5828 SPR:$src, ssub_0), (i32 0)))>;
5829 def : Pat<(v4f32 (NEONvdup (f32 SPR:$src))),
5830 (v4f32 (VDUPLN32q (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
5831 SPR:$src, ssub_0), (i32 0)))>;
5833 // VMOVN : Vector Narrowing Move
5834 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
5835 "vmovn", "i", trunc>;
5836 // VQMOVN : Vector Saturating Narrowing Move
5837 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
5838 "vqmovn", "s", int_arm_neon_vqmovns>;
5839 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
5840 "vqmovn", "u", int_arm_neon_vqmovnu>;
5841 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
5842 "vqmovun", "s", int_arm_neon_vqmovnsu>;
5843 // VMOVL : Vector Lengthening Move
5844 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
5845 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
5846 def : Pat<(v8i16 (anyext (v8i8 DPR:$Vm))), (VMOVLuv8i16 DPR:$Vm)>;
5847 def : Pat<(v4i32 (anyext (v4i16 DPR:$Vm))), (VMOVLuv4i32 DPR:$Vm)>;
5848 def : Pat<(v2i64 (anyext (v2i32 DPR:$Vm))), (VMOVLuv2i64 DPR:$Vm)>;
5850 // Vector Conversions.
5852 // VCVT : Vector Convert Between Floating-Point and Integers
5853 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
5854 v2i32, v2f32, fp_to_sint>;
5855 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
5856 v2i32, v2f32, fp_to_uint>;
5857 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
5858 v2f32, v2i32, sint_to_fp>;
5859 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
5860 v2f32, v2i32, uint_to_fp>;
5862 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
5863 v4i32, v4f32, fp_to_sint>;
5864 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
5865 v4i32, v4f32, fp_to_uint>;
5866 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
5867 v4f32, v4i32, sint_to_fp>;
5868 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
5869 v4f32, v4i32, uint_to_fp>;
5872 multiclass VCVT_FPI<string op, bits<3> op10_8, SDPatternOperator IntS,
5873 SDPatternOperator IntU> {
5874 let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
5875 def SD : N2VDIntnp<0b11, op10_8, 0, NoItinerary, !strconcat("vcvt", op),
5876 "s32.f32", v2i32, v2f32, IntS>, Requires<[HasV8, HasNEON]>;
5877 def SQ : N2VQIntnp<0b11, op10_8, 0, NoItinerary, !strconcat("vcvt", op),
5878 "s32.f32", v4i32, v4f32, IntS>, Requires<[HasV8, HasNEON]>;
5879 def UD : N2VDIntnp<0b11, op10_8, 1, NoItinerary, !strconcat("vcvt", op),
5880 "u32.f32", v2i32, v2f32, IntU>, Requires<[HasV8, HasNEON]>;
5881 def UQ : N2VQIntnp<0b11, op10_8, 1, NoItinerary, !strconcat("vcvt", op),
5882 "u32.f32", v4i32, v4f32, IntU>, Requires<[HasV8, HasNEON]>;
5886 defm VCVTAN : VCVT_FPI<"a", 0b000, int_arm_neon_vcvtas, int_arm_neon_vcvtau>;
5887 defm VCVTNN : VCVT_FPI<"n", 0b001, int_arm_neon_vcvtns, int_arm_neon_vcvtnu>;
5888 defm VCVTPN : VCVT_FPI<"p", 0b010, int_arm_neon_vcvtps, int_arm_neon_vcvtpu>;
5889 defm VCVTMN : VCVT_FPI<"m", 0b011, int_arm_neon_vcvtms, int_arm_neon_vcvtmu>;
5891 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
5892 let DecoderMethod = "DecodeVCVTD" in {
5893 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
5894 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
5895 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
5896 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
5897 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
5898 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
5899 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
5900 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
5903 let DecoderMethod = "DecodeVCVTQ" in {
5904 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
5905 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
5906 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
5907 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
5908 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
5909 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
5910 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
5911 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
5914 def : NEONInstAlias<"vcvt${p}.s32.f32 $Dd, $Dm, #0",
5915 (VCVTf2sd DPR:$Dd, DPR:$Dm, pred:$p)>;
5916 def : NEONInstAlias<"vcvt${p}.u32.f32 $Dd, $Dm, #0",
5917 (VCVTf2ud DPR:$Dd, DPR:$Dm, pred:$p)>;
5918 def : NEONInstAlias<"vcvt${p}.f32.s32 $Dd, $Dm, #0",
5919 (VCVTs2fd DPR:$Dd, DPR:$Dm, pred:$p)>;
5920 def : NEONInstAlias<"vcvt${p}.f32.u32 $Dd, $Dm, #0",
5921 (VCVTu2fd DPR:$Dd, DPR:$Dm, pred:$p)>;
5923 def : NEONInstAlias<"vcvt${p}.s32.f32 $Qd, $Qm, #0",
5924 (VCVTf2sq QPR:$Qd, QPR:$Qm, pred:$p)>;
5925 def : NEONInstAlias<"vcvt${p}.u32.f32 $Qd, $Qm, #0",
5926 (VCVTf2uq QPR:$Qd, QPR:$Qm, pred:$p)>;
5927 def : NEONInstAlias<"vcvt${p}.f32.s32 $Qd, $Qm, #0",
5928 (VCVTs2fq QPR:$Qd, QPR:$Qm, pred:$p)>;
5929 def : NEONInstAlias<"vcvt${p}.f32.u32 $Qd, $Qm, #0",
5930 (VCVTu2fq QPR:$Qd, QPR:$Qm, pred:$p)>;
5933 // VCVT : Vector Convert Between Half-Precision and Single-Precision.
5934 def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
5935 IIC_VUNAQ, "vcvt", "f16.f32",
5936 v4i16, v4f32, int_arm_neon_vcvtfp2hf>,
5937 Requires<[HasNEON, HasFP16]>;
5938 def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
5939 IIC_VUNAQ, "vcvt", "f32.f16",
5940 v4f32, v4i16, int_arm_neon_vcvthf2fp>,
5941 Requires<[HasNEON, HasFP16]>;
5945 // VREV64 : Vector Reverse elements within 64-bit doublewords
5947 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5948 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
5949 (ins DPR:$Vm), IIC_VMOVD,
5950 OpcodeStr, Dt, "$Vd, $Vm", "",
5951 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
5952 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5953 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
5954 (ins QPR:$Vm), IIC_VMOVQ,
5955 OpcodeStr, Dt, "$Vd, $Vm", "",
5956 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
5958 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
5959 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
5960 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
5961 def : Pat<(v2f32 (NEONvrev64 (v2f32 DPR:$Vm))), (VREV64d32 DPR:$Vm)>;
5963 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
5964 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
5965 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
5966 def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>;
5968 // VREV32 : Vector Reverse elements within 32-bit words
5970 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5971 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
5972 (ins DPR:$Vm), IIC_VMOVD,
5973 OpcodeStr, Dt, "$Vd, $Vm", "",
5974 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
5975 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5976 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
5977 (ins QPR:$Vm), IIC_VMOVQ,
5978 OpcodeStr, Dt, "$Vd, $Vm", "",
5979 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
5981 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
5982 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
5984 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
5985 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
5987 // VREV16 : Vector Reverse elements within 16-bit halfwords
5989 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5990 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
5991 (ins DPR:$Vm), IIC_VMOVD,
5992 OpcodeStr, Dt, "$Vd, $Vm", "",
5993 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
5994 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5995 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
5996 (ins QPR:$Vm), IIC_VMOVQ,
5997 OpcodeStr, Dt, "$Vd, $Vm", "",
5998 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
6000 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
6001 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
6003 // Other Vector Shuffles.
6005 // Aligned extractions: really just dropping registers
6007 class AlignedVEXTq<ValueType DestTy, ValueType SrcTy, SDNodeXForm LaneCVT>
6008 : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))),
6009 (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>;
6011 def : AlignedVEXTq<v8i8, v16i8, DSubReg_i8_reg>;
6013 def : AlignedVEXTq<v4i16, v8i16, DSubReg_i16_reg>;
6015 def : AlignedVEXTq<v2i32, v4i32, DSubReg_i32_reg>;
6017 def : AlignedVEXTq<v1i64, v2i64, DSubReg_f64_reg>;
6019 def : AlignedVEXTq<v2f32, v4f32, DSubReg_i32_reg>;
6022 // VEXT : Vector Extract
6025 // All of these have a two-operand InstAlias.
6026 let TwoOperandAliasConstraint = "$Vn = $Vd" in {
6027 class VEXTd<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
6028 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
6029 (ins DPR:$Vn, DPR:$Vm, immTy:$index), NVExtFrm,
6030 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
6031 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
6032 (Ty DPR:$Vm), imm:$index)))]> {
6035 let Inst{10-8} = index{2-0};
6038 class VEXTq<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
6039 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
6040 (ins QPR:$Vn, QPR:$Vm, imm0_15:$index), NVExtFrm,
6041 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
6042 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
6043 (Ty QPR:$Vm), imm:$index)))]> {
6045 let Inst{11-8} = index{3-0};
6049 def VEXTd8 : VEXTd<"vext", "8", v8i8, imm0_7> {
6050 let Inst{10-8} = index{2-0};
6052 def VEXTd16 : VEXTd<"vext", "16", v4i16, imm0_3> {
6053 let Inst{10-9} = index{1-0};
6056 def VEXTd32 : VEXTd<"vext", "32", v2i32, imm0_1> {
6057 let Inst{10} = index{0};
6058 let Inst{9-8} = 0b00;
6060 def : Pat<(v2f32 (NEONvext (v2f32 DPR:$Vn),
6063 (VEXTd32 DPR:$Vn, DPR:$Vm, imm:$index)>;
6065 def VEXTq8 : VEXTq<"vext", "8", v16i8, imm0_15> {
6066 let Inst{11-8} = index{3-0};
6068 def VEXTq16 : VEXTq<"vext", "16", v8i16, imm0_7> {
6069 let Inst{11-9} = index{2-0};
6072 def VEXTq32 : VEXTq<"vext", "32", v4i32, imm0_3> {
6073 let Inst{11-10} = index{1-0};
6074 let Inst{9-8} = 0b00;
6076 def VEXTq64 : VEXTq<"vext", "64", v2i64, imm0_1> {
6077 let Inst{11} = index{0};
6078 let Inst{10-8} = 0b000;
6080 def : Pat<(v4f32 (NEONvext (v4f32 QPR:$Vn),
6083 (VEXTq32 QPR:$Vn, QPR:$Vm, imm:$index)>;
6085 // VTRN : Vector Transpose
6087 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
6088 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
6089 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
6091 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
6092 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
6093 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
6095 // VUZP : Vector Unzip (Deinterleave)
6097 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
6098 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
6099 // vuzp.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
6100 def : NEONInstAlias<"vuzp${p}.32 $Dd, $Dm",
6101 (VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p)>;
6103 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
6104 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
6105 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
6107 // VZIP : Vector Zip (Interleave)
6109 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
6110 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
6111 // vzip.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
6112 def : NEONInstAlias<"vzip${p}.32 $Dd, $Dm",
6113 (VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p)>;
6115 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
6116 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
6117 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
6119 // Vector Table Lookup and Table Extension.
6121 // VTBL : Vector Table Lookup
6122 let DecoderMethod = "DecodeTBLInstruction" in {
6124 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
6125 (ins VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
6126 "vtbl", "8", "$Vd, $Vn, $Vm", "",
6127 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 VecListOneD:$Vn, DPR:$Vm)))]>;
6128 let hasExtraSrcRegAllocReq = 1 in {
6130 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
6131 (ins VecListDPair:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB2,
6132 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
6134 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
6135 (ins VecListThreeD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB3,
6136 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
6138 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
6139 (ins VecListFourD:$Vn, DPR:$Vm),
6141 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
6142 } // hasExtraSrcRegAllocReq = 1
6145 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
6147 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
6149 // VTBX : Vector Table Extension
6151 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
6152 (ins DPR:$orig, VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
6153 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd",
6154 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
6155 DPR:$orig, VecListOneD:$Vn, DPR:$Vm)))]>;
6156 let hasExtraSrcRegAllocReq = 1 in {
6158 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
6159 (ins DPR:$orig, VecListDPair:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
6160 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd", []>;
6162 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
6163 (ins DPR:$orig, VecListThreeD:$Vn, DPR:$Vm),
6164 NVTBLFrm, IIC_VTBX3,
6165 "vtbx", "8", "$Vd, $Vn, $Vm",
6168 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd),
6169 (ins DPR:$orig, VecListFourD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
6170 "vtbx", "8", "$Vd, $Vn, $Vm",
6172 } // hasExtraSrcRegAllocReq = 1
6175 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
6176 IIC_VTBX3, "$orig = $dst", []>;
6178 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
6179 IIC_VTBX4, "$orig = $dst", []>;
6180 } // DecoderMethod = "DecodeTBLInstruction"
6182 // VRINT : Vector Rounding
6183 multiclass VRINT_FPI<string op, bits<3> op9_7, SDPatternOperator Int> {
6184 let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
6185 def D : N2VDIntnp<0b10, 0b100, 0, NoItinerary,
6186 !strconcat("vrint", op), "f32",
6187 v2f32, v2f32, Int>, Requires<[HasV8, HasNEON]> {
6188 let Inst{9-7} = op9_7;
6190 def Q : N2VQIntnp<0b10, 0b100, 0, NoItinerary,
6191 !strconcat("vrint", op), "f32",
6192 v4f32, v4f32, Int>, Requires<[HasV8, HasNEON]> {
6193 let Inst{9-7} = op9_7;
6197 def : NEONInstAlias<!strconcat("vrint", op, ".f32.f32\t$Dd, $Dm"),
6198 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm)>;
6199 def : NEONInstAlias<!strconcat("vrint", op, ".f32.f32\t$Qd, $Qm"),
6200 (!cast<Instruction>(NAME#"Q") QPR:$Qd, QPR:$Qm)>;
6203 defm VRINTNN : VRINT_FPI<"n", 0b000, int_arm_neon_vrintn>;
6204 defm VRINTXN : VRINT_FPI<"x", 0b001, int_arm_neon_vrintx>;
6205 defm VRINTAN : VRINT_FPI<"a", 0b010, int_arm_neon_vrinta>;
6206 defm VRINTZN : VRINT_FPI<"z", 0b011, int_arm_neon_vrintz>;
6207 defm VRINTMN : VRINT_FPI<"m", 0b101, int_arm_neon_vrintm>;
6208 defm VRINTPN : VRINT_FPI<"p", 0b111, int_arm_neon_vrintp>;
6210 // Cryptography instructions
6211 let PostEncoderMethod = "NEONThumb2DataIPostEncoder",
6212 DecoderNamespace = "v8Crypto", hasSideEffects = 0 in {
6213 class AES<string op, bit op7, bit op6, SDPatternOperator Int>
6214 : N2VQIntXnp<0b00, 0b00, 0b011, op6, op7, NoItinerary,
6215 !strconcat("aes", op), "8", v16i8, v16i8, Int>,
6216 Requires<[HasV8, HasCrypto]>;
6217 class AES2Op<string op, bit op7, bit op6, SDPatternOperator Int>
6218 : N2VQIntX2np<0b00, 0b00, 0b011, op6, op7, NoItinerary,
6219 !strconcat("aes", op), "8", v16i8, v16i8, Int>,
6220 Requires<[HasV8, HasCrypto]>;
6221 class N2SHA<string op, bits<2> op17_16, bits<3> op10_8, bit op7, bit op6,
6222 SDPatternOperator Int>
6223 : N2VQIntXnp<0b10, op17_16, op10_8, op6, op7, NoItinerary,
6224 !strconcat("sha", op), "32", v4i32, v4i32, Int>,
6225 Requires<[HasV8, HasCrypto]>;
6226 class N2SHA2Op<string op, bits<2> op17_16, bits<3> op10_8, bit op7, bit op6,
6227 SDPatternOperator Int>
6228 : N2VQIntX2np<0b10, op17_16, op10_8, op6, op7, NoItinerary,
6229 !strconcat("sha", op), "32", v4i32, v4i32, Int>,
6230 Requires<[HasV8, HasCrypto]>;
6231 class N3SHA3Op<string op, bits<5> op27_23, bits<2> op21_20, SDPatternOperator Int>
6232 : N3VQInt3np<op27_23, op21_20, 0b1100, 1, 0, N3RegFrm, NoItinerary,
6233 !strconcat("sha", op), "32", v4i32, v4i32, Int, 0>,
6234 Requires<[HasV8, HasCrypto]>;
6237 def AESD : AES2Op<"d", 0, 1, int_arm_neon_aesd>;
6238 def AESE : AES2Op<"e", 0, 0, int_arm_neon_aese>;
6239 def AESIMC : AES<"imc", 1, 1, int_arm_neon_aesimc>;
6240 def AESMC : AES<"mc", 1, 0, int_arm_neon_aesmc>;
6242 def SHA1H : N2SHA<"1h", 0b01, 0b010, 1, 1, null_frag>;
6243 def SHA1SU1 : N2SHA2Op<"1su1", 0b10, 0b011, 1, 0, int_arm_neon_sha1su1>;
6244 def SHA256SU0 : N2SHA2Op<"256su0", 0b10, 0b011, 1, 1, int_arm_neon_sha256su0>;
6245 def SHA1C : N3SHA3Op<"1c", 0b00100, 0b00, null_frag>;
6246 def SHA1M : N3SHA3Op<"1m", 0b00100, 0b10, null_frag>;
6247 def SHA1P : N3SHA3Op<"1p", 0b00100, 0b01, null_frag>;
6248 def SHA1SU0 : N3SHA3Op<"1su0", 0b00100, 0b11, int_arm_neon_sha1su0>;
6249 def SHA256H : N3SHA3Op<"256h", 0b00110, 0b00, int_arm_neon_sha256h>;
6250 def SHA256H2 : N3SHA3Op<"256h2", 0b00110, 0b01, int_arm_neon_sha256h2>;
6251 def SHA256SU1 : N3SHA3Op<"256su1", 0b00110, 0b10, int_arm_neon_sha256su1>;
6253 def : Pat<(i32 (int_arm_neon_sha1h i32:$Rn)),
6254 (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG
6255 (SHA1H (SUBREG_TO_REG (i64 0),
6256 (f32 (COPY_TO_REGCLASS i32:$Rn, SPR)),
6260 def : Pat<(v4i32 (int_arm_neon_sha1c v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk)),
6261 (SHA1C v4i32:$hash_abcd,
6262 (SUBREG_TO_REG (i64 0),
6263 (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)),
6267 def : Pat<(v4i32 (int_arm_neon_sha1m v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk)),
6268 (SHA1M v4i32:$hash_abcd,
6269 (SUBREG_TO_REG (i64 0),
6270 (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)),
6274 def : Pat<(v4i32 (int_arm_neon_sha1p v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk)),
6275 (SHA1P v4i32:$hash_abcd,
6276 (SUBREG_TO_REG (i64 0),
6277 (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)),
6281 //===----------------------------------------------------------------------===//
6282 // NEON instructions for single-precision FP math
6283 //===----------------------------------------------------------------------===//
6285 class N2VSPat<SDNode OpNode, NeonI Inst>
6286 : NEONFPPat<(f32 (OpNode SPR:$a)),
6288 (v2f32 (COPY_TO_REGCLASS (Inst
6290 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
6291 SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>;
6293 class N3VSPat<SDNode OpNode, NeonI Inst>
6294 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
6296 (v2f32 (COPY_TO_REGCLASS (Inst
6298 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
6301 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
6302 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
6304 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
6305 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
6307 (v2f32 (COPY_TO_REGCLASS (Inst
6309 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
6312 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
6315 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
6316 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
6318 class NVCVTIFPat<SDNode OpNode, NeonI Inst>
6319 : NEONFPPat<(f32 (OpNode GPR:$a)),
6320 (f32 (EXTRACT_SUBREG
6323 (v2f32 (IMPLICIT_DEF)),
6324 (i32 (COPY_TO_REGCLASS GPR:$a, SPR)), ssub_0))),
6326 class NVCVTFIPat<SDNode OpNode, NeonI Inst>
6327 : NEONFPPat<(i32 (OpNode SPR:$a)),
6328 (i32 (EXTRACT_SUBREG
6329 (v2f32 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
6333 def : N3VSPat<fadd, VADDfd>;
6334 def : N3VSPat<fsub, VSUBfd>;
6335 def : N3VSPat<fmul, VMULfd>;
6336 def : N3VSMulOpPat<fmul, fadd, VMLAfd>,
6337 Requires<[HasNEON, UseNEONForFP, UseFPVMLx, DontUseFusedMAC]>;
6338 def : N3VSMulOpPat<fmul, fsub, VMLSfd>,
6339 Requires<[HasNEON, UseNEONForFP, UseFPVMLx, DontUseFusedMAC]>;
6340 def : N3VSMulOpPat<fmul, fadd, VFMAfd>,
6341 Requires<[HasVFP4, UseNEONForFP, UseFusedMAC]>;
6342 def : N3VSMulOpPat<fmul, fsub, VFMSfd>,
6343 Requires<[HasVFP4, UseNEONForFP, UseFusedMAC]>;
6344 def : N2VSPat<fabs, VABSfd>;
6345 def : N2VSPat<fneg, VNEGfd>;
6346 def : N3VSPat<NEONfmax, VMAXfd>;
6347 def : N3VSPat<NEONfmin, VMINfd>;
6348 def : NVCVTFIPat<fp_to_sint, VCVTf2sd>;
6349 def : NVCVTFIPat<fp_to_uint, VCVTf2ud>;
6350 def : NVCVTIFPat<sint_to_fp, VCVTs2fd>;
6351 def : NVCVTIFPat<uint_to_fp, VCVTu2fd>;
6353 // NEON doesn't have any f64 conversions, so provide patterns to make
6354 // sure the VFP conversions match when extracting from a vector.
6355 def : VFPPat<(f64 (sint_to_fp (extractelt (v2i32 DPR:$src), imm:$lane))),
6356 (VSITOD (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))>;
6357 def : VFPPat<(f64 (sint_to_fp (extractelt (v4i32 QPR:$src), imm:$lane))),
6358 (VSITOD (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane)))>;
6359 def : VFPPat<(f64 (uint_to_fp (extractelt (v2i32 DPR:$src), imm:$lane))),
6360 (VUITOD (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))>;
6361 def : VFPPat<(f64 (uint_to_fp (extractelt (v4i32 QPR:$src), imm:$lane))),
6362 (VUITOD (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane)))>;
6365 // Prefer VMOVDRR for i32 -> f32 bitcasts, it can write all DPR registers.
6366 def : Pat<(f32 (bitconvert GPR:$a)),
6367 (EXTRACT_SUBREG (VMOVDRR GPR:$a, GPR:$a), ssub_0)>,
6368 Requires<[HasNEON, DontUseVMOVSR]>;
6370 //===----------------------------------------------------------------------===//
6371 // Non-Instruction Patterns
6372 //===----------------------------------------------------------------------===//
6375 let Predicates = [IsLE] in {
6376 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
6377 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
6378 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
6380 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
6381 let Predicates = [IsLE] in {
6382 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
6383 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
6384 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
6385 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
6386 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
6388 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
6389 let Predicates = [IsLE] in {
6390 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
6391 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
6392 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
6393 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
6394 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
6395 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
6396 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
6397 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
6398 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
6399 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
6401 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
6402 let Predicates = [IsLE] in {
6403 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
6404 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
6405 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
6406 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
6407 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
6408 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
6410 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
6411 let Predicates = [IsLE] in {
6412 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
6413 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
6416 let Predicates = [IsLE] in {
6417 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
6418 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
6419 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
6421 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
6422 let Predicates = [IsLE] in {
6423 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
6424 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
6425 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
6426 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
6427 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
6429 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
6430 let Predicates = [IsLE] in {
6431 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
6432 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
6433 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
6434 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
6435 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
6436 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
6437 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
6438 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
6439 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
6440 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
6441 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
6443 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
6444 let Predicates = [IsLE] in {
6445 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
6446 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
6447 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
6449 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
6450 let Predicates = [IsLE] in {
6451 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
6452 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
6453 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
6454 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
6457 let Predicates = [IsBE] in {
6458 // 64 bit conversions
6459 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (VREV64d32 DPR:$src)>;
6460 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (VREV64d16 DPR:$src)>;
6461 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (VREV64d8 DPR:$src)>;
6462 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (VREV64d32 DPR:$src)>;
6463 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (VREV64d32 DPR:$src)>;
6464 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (VREV32d16 DPR:$src)>;
6465 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (VREV32d8 DPR:$src)>;
6466 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (VREV64d32 DPR:$src)>;
6467 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (VREV64d16 DPR:$src)>;
6468 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (VREV32d16 DPR:$src)>;
6469 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (VREV16d8 DPR:$src)>;
6470 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (VREV64d16 DPR:$src)>;
6471 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (VREV32d16 DPR:$src)>;
6472 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (VREV64d8 DPR:$src)>;
6473 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (VREV32d8 DPR:$src)>;
6474 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (VREV16d8 DPR:$src)>;
6475 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (VREV64d8 DPR:$src)>;
6476 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (VREV32d8 DPR:$src)>;
6477 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (VREV64d32 DPR:$src)>;
6478 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (VREV64d16 DPR:$src)>;
6479 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (VREV64d8 DPR:$src)>;
6480 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (VREV64d32 DPR:$src)>;
6481 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (VREV64d32 DPR:$src)>;
6482 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (VREV64d32 DPR:$src)>;
6483 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (VREV32d16 DPR:$src)>;
6484 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (VREV32d8 DPR:$src)>;
6486 // 128 bit conversions
6487 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (VREV64q32 QPR:$src)>;
6488 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (VREV64q16 QPR:$src)>;
6489 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (VREV64q8 QPR:$src)>;
6490 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (VREV64q32 QPR:$src)>;
6491 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (VREV64q32 QPR:$src)>;
6492 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (VREV32q16 QPR:$src)>;
6493 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (VREV32q8 QPR:$src)>;
6494 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (VREV64q32 QPR:$src)>;
6495 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (VREV64q16 QPR:$src)>;
6496 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (VREV32q16 QPR:$src)>;
6497 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (VREV16q8 QPR:$src)>;
6498 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (VREV64q16 QPR:$src)>;
6499 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (VREV32q16 QPR:$src)>;
6500 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (VREV64q8 QPR:$src)>;
6501 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (VREV32q8 QPR:$src)>;
6502 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (VREV16q8 QPR:$src)>;
6503 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (VREV64q8 QPR:$src)>;
6504 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (VREV32q8 QPR:$src)>;
6505 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (VREV64q32 QPR:$src)>;
6506 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (VREV32q16 QPR:$src)>;
6507 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (VREV32q8 QPR:$src)>;
6508 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (VREV64q32 QPR:$src)>;
6509 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (VREV64q32 QPR:$src)>;
6510 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (VREV64q16 QPR:$src)>;
6511 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (VREV64q8 QPR:$src)>;
6512 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (VREV64q32 QPR:$src)>;
6515 // Fold extracting an element out of a v2i32 into a vfp register.
6516 def : Pat<(f32 (bitconvert (i32 (extractelt (v2i32 DPR:$src), imm:$lane)))),
6517 (f32 (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))>;
6519 // Vector lengthening move with load, matching extending loads.
6521 // extload, zextload and sextload for a standard lengthening load. Example:
6522 // Lengthen_Single<"8", "i16", "8"> =
6523 // Pat<(v8i16 (extloadvi8 addrmode6:$addr))
6524 // (VMOVLuv8i16 (VLD1d8 addrmode6:$addr,
6525 // (f64 (IMPLICIT_DEF)), (i32 0)))>;
6526 multiclass Lengthen_Single<string DestLanes, string DestTy, string SrcTy> {
6527 let AddedComplexity = 10 in {
6528 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6529 (!cast<PatFrag>("extloadvi" # SrcTy) addrmode6:$addr)),
6530 (!cast<Instruction>("VMOVLuv" # DestLanes # DestTy)
6531 (!cast<Instruction>("VLD1d" # SrcTy) addrmode6:$addr))>;
6533 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6534 (!cast<PatFrag>("zextloadvi" # SrcTy) addrmode6:$addr)),
6535 (!cast<Instruction>("VMOVLuv" # DestLanes # DestTy)
6536 (!cast<Instruction>("VLD1d" # SrcTy) addrmode6:$addr))>;
6538 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6539 (!cast<PatFrag>("sextloadvi" # SrcTy) addrmode6:$addr)),
6540 (!cast<Instruction>("VMOVLsv" # DestLanes # DestTy)
6541 (!cast<Instruction>("VLD1d" # SrcTy) addrmode6:$addr))>;
6545 // extload, zextload and sextload for a lengthening load which only uses
6546 // half the lanes available. Example:
6547 // Lengthen_HalfSingle<"4", "i16", "8", "i16", "i8"> =
6548 // Pat<(v4i16 (extloadvi8 addrmode6oneL32:$addr)),
6549 // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr,
6550 // (f64 (IMPLICIT_DEF)), (i32 0))),
6552 multiclass Lengthen_HalfSingle<string DestLanes, string DestTy, string SrcTy,
6553 string InsnLanes, string InsnTy> {
6554 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6555 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)),
6556 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
6557 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6559 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6560 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)),
6561 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
6562 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6564 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6565 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)),
6566 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # InsnLanes # InsnTy)
6567 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6571 // The following class definition is basically a copy of the
6572 // Lengthen_HalfSingle definition above, however with an additional parameter
6573 // "RevLanes" to select the correct VREV32dXX instruction. This is to convert
6574 // data loaded by VLD1LN into proper vector format in big endian mode.
6575 multiclass Lengthen_HalfSingle_Big_Endian<string DestLanes, string DestTy, string SrcTy,
6576 string InsnLanes, string InsnTy, string RevLanes> {
6577 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6578 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)),
6579 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
6580 (!cast<Instruction>("VREV32d" # RevLanes)
6581 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))),
6583 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6584 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)),
6585 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
6586 (!cast<Instruction>("VREV32d" # RevLanes)
6587 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))),
6589 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6590 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)),
6591 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # InsnLanes # InsnTy)
6592 (!cast<Instruction>("VREV32d" # RevLanes)
6593 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))),
6597 // extload, zextload and sextload for a lengthening load followed by another
6598 // lengthening load, to quadruple the initial length.
6600 // Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32"> =
6601 // Pat<(v4i32 (extloadvi8 addrmode6oneL32:$addr))
6602 // (EXTRACT_SUBREG (VMOVLuv4i32
6603 // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr,
6604 // (f64 (IMPLICIT_DEF)),
6608 multiclass Lengthen_Double<string DestLanes, string DestTy, string SrcTy,
6609 string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
6611 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6612 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)),
6613 (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6614 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6615 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6617 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6618 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)),
6619 (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6620 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6621 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6623 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6624 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)),
6625 (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
6626 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
6627 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6631 // The following class definition is basically a copy of the
6632 // Lengthen_Double definition above, however with an additional parameter
6633 // "RevLanes" to select the correct VREV32dXX instruction. This is to convert
6634 // data loaded by VLD1LN into proper vector format in big endian mode.
6635 multiclass Lengthen_Double_Big_Endian<string DestLanes, string DestTy, string SrcTy,
6636 string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
6637 string Insn2Ty, string RevLanes> {
6638 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6639 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)),
6640 (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6641 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6642 (!cast<Instruction>("VREV32d" # RevLanes)
6643 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))),
6645 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6646 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)),
6647 (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6648 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6649 (!cast<Instruction>("VREV32d" # RevLanes)
6650 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))),
6652 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6653 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)),
6654 (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
6655 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
6656 (!cast<Instruction>("VREV32d" # RevLanes)
6657 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))),
6661 // extload, zextload and sextload for a lengthening load followed by another
6662 // lengthening load, to quadruple the initial length, but which ends up only
6663 // requiring half the available lanes (a 64-bit outcome instead of a 128-bit).
6665 // Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32"> =
6666 // Pat<(v2i32 (extloadvi8 addrmode6:$addr))
6667 // (EXTRACT_SUBREG (VMOVLuv4i32
6668 // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd16 addrmode6:$addr,
6669 // (f64 (IMPLICIT_DEF)), (i32 0))),
6672 multiclass Lengthen_HalfDouble<string DestLanes, string DestTy, string SrcTy,
6673 string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
6675 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6676 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6:$addr)),
6677 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6678 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6679 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6682 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6683 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6:$addr)),
6684 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6685 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6686 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6689 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6690 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6:$addr)),
6691 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
6692 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
6693 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6698 // The following class definition is basically a copy of the
6699 // Lengthen_HalfDouble definition above, however with an additional VREV16d8
6700 // instruction to convert data loaded by VLD1LN into proper vector format
6701 // in big endian mode.
6702 multiclass Lengthen_HalfDouble_Big_Endian<string DestLanes, string DestTy, string SrcTy,
6703 string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
6705 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6706 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6:$addr)),
6707 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6708 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6709 (!cast<Instruction>("VREV16d8")
6710 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))),
6713 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6714 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6:$addr)),
6715 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6716 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6717 (!cast<Instruction>("VREV16d8")
6718 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))),
6721 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6722 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6:$addr)),
6723 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
6724 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
6725 (!cast<Instruction>("VREV16d8")
6726 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))),
6731 defm : Lengthen_Single<"8", "i16", "8">; // v8i8 -> v8i16
6732 defm : Lengthen_Single<"4", "i32", "16">; // v4i16 -> v4i32
6733 defm : Lengthen_Single<"2", "i64", "32">; // v2i32 -> v2i64
6735 let Predicates = [IsLE] in {
6736 defm : Lengthen_HalfSingle<"4", "i16", "i8", "8", "i16">; // v4i8 -> v4i16
6737 defm : Lengthen_HalfSingle<"2", "i32", "i16", "4", "i32">; // v2i16 -> v2i32
6739 // Double lengthening - v4i8 -> v4i16 -> v4i32
6740 defm : Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32">;
6741 // v2i8 -> v2i16 -> v2i32
6742 defm : Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32">;
6743 // v2i16 -> v2i32 -> v2i64
6744 defm : Lengthen_Double<"2", "i64", "i16", "4", "i32", "2", "i64">;
6747 let Predicates = [IsBE] in {
6748 defm : Lengthen_HalfSingle_Big_Endian<"4", "i16", "i8", "8", "i16", "8">; // v4i8 -> v4i16
6749 defm : Lengthen_HalfSingle_Big_Endian<"2", "i32", "i16", "4", "i32", "16">; // v2i16 -> v2i32
6751 // Double lengthening - v4i8 -> v4i16 -> v4i32
6752 defm : Lengthen_Double_Big_Endian<"4", "i32", "i8", "8", "i16", "4", "i32", "8">;
6753 // v2i8 -> v2i16 -> v2i32
6754 defm : Lengthen_HalfDouble_Big_Endian<"2", "i32", "i8", "8", "i16", "4", "i32">;
6755 // v2i16 -> v2i32 -> v2i64
6756 defm : Lengthen_Double_Big_Endian<"2", "i64", "i16", "4", "i32", "2", "i64", "16">;
6759 // Triple lengthening - v2i8 -> v2i16 -> v2i32 -> v2i64
6760 let Predicates = [IsLE] in {
6761 def : Pat<(v2i64 (extloadvi8 addrmode6:$addr)),
6762 (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
6763 (VLD1LNd16 addrmode6:$addr,
6764 (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
6765 def : Pat<(v2i64 (zextloadvi8 addrmode6:$addr)),
6766 (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
6767 (VLD1LNd16 addrmode6:$addr,
6768 (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
6769 def : Pat<(v2i64 (sextloadvi8 addrmode6:$addr)),
6770 (VMOVLsv2i64 (EXTRACT_SUBREG (VMOVLsv4i32 (EXTRACT_SUBREG (VMOVLsv8i16
6771 (VLD1LNd16 addrmode6:$addr,
6772 (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
6774 // The following patterns are basically a copy of the patterns above,
6775 // however with an additional VREV16d instruction to convert data
6776 // loaded by VLD1LN into proper vector format in big endian mode.
6777 let Predicates = [IsBE] in {
6778 def : Pat<(v2i64 (extloadvi8 addrmode6:$addr)),
6779 (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
6780 (!cast<Instruction>("VREV16d8")
6781 (VLD1LNd16 addrmode6:$addr,
6782 (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)), dsub_0))>;
6783 def : Pat<(v2i64 (zextloadvi8 addrmode6:$addr)),
6784 (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
6785 (!cast<Instruction>("VREV16d8")
6786 (VLD1LNd16 addrmode6:$addr,
6787 (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)), dsub_0))>;
6788 def : Pat<(v2i64 (sextloadvi8 addrmode6:$addr)),
6789 (VMOVLsv2i64 (EXTRACT_SUBREG (VMOVLsv4i32 (EXTRACT_SUBREG (VMOVLsv8i16
6790 (!cast<Instruction>("VREV16d8")
6791 (VLD1LNd16 addrmode6:$addr,
6792 (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)), dsub_0))>;
6795 //===----------------------------------------------------------------------===//
6796 // Assembler aliases
6799 def : VFP2InstAlias<"fmdhr${p} $Dd, $Rn",
6800 (VSETLNi32 DPR:$Dd, GPR:$Rn, 1, pred:$p)>;
6801 def : VFP2InstAlias<"fmdlr${p} $Dd, $Rn",
6802 (VSETLNi32 DPR:$Dd, GPR:$Rn, 0, pred:$p)>;
6804 // VAND/VBIC/VEOR/VORR accept but do not require a type suffix.
6805 defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
6806 (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6807 defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
6808 (VANDq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6809 defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
6810 (VBICd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6811 defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
6812 (VBICq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6813 defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
6814 (VEORd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6815 defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
6816 (VEORq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6817 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
6818 (VORRd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6819 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
6820 (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6821 // ... two-operand aliases
6822 defm : NEONDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",
6823 (VANDd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6824 defm : NEONDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",
6825 (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6826 defm : NEONDTAnyInstAlias<"veor${p}", "$Vdn, $Vm",
6827 (VEORd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6828 defm : NEONDTAnyInstAlias<"veor${p}", "$Vdn, $Vm",
6829 (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6830 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
6831 (VORRd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6832 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
6833 (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6835 def : NEONInstAlias<"vand${p}.i16 $Vd, $imm",
6836 (VBICiv4i16 DPR:$Vd, nImmSplatNotI16:$imm, pred:$p)>;
6837 def : NEONInstAlias<"vand${p}.i32 $Vd, $imm",
6838 (VBICiv2i32 DPR:$Vd, nImmSplatNotI32:$imm, pred:$p)>;
6839 def : NEONInstAlias<"vand${p}.i16 $Vd, $imm",
6840 (VBICiv8i16 QPR:$Vd, nImmSplatNotI16:$imm, pred:$p)>;
6841 def : NEONInstAlias<"vand${p}.i32 $Vd, $imm",
6842 (VBICiv4i32 QPR:$Vd, nImmSplatNotI32:$imm, pred:$p)>;
6845 // VLD1 single-lane pseudo-instructions. These need special handling for
6846 // the lane index that an InstAlias can't handle, so we use these instead.
6847 def VLD1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr",
6848 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6850 def VLD1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr",
6851 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6853 def VLD1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr",
6854 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6857 def VLD1LNdWB_fixed_Asm_8 :
6858 NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr!",
6859 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6861 def VLD1LNdWB_fixed_Asm_16 :
6862 NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr!",
6863 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6865 def VLD1LNdWB_fixed_Asm_32 :
6866 NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr!",
6867 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6869 def VLD1LNdWB_register_Asm_8 :
6870 NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr, $Rm",
6871 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6872 rGPR:$Rm, pred:$p)>;
6873 def VLD1LNdWB_register_Asm_16 :
6874 NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr, $Rm",
6875 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6876 rGPR:$Rm, pred:$p)>;
6877 def VLD1LNdWB_register_Asm_32 :
6878 NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr, $Rm",
6879 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6880 rGPR:$Rm, pred:$p)>;
6883 // VST1 single-lane pseudo-instructions. These need special handling for
6884 // the lane index that an InstAlias can't handle, so we use these instead.
6885 def VST1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr",
6886 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6888 def VST1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr",
6889 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6891 def VST1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr",
6892 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6895 def VST1LNdWB_fixed_Asm_8 :
6896 NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr!",
6897 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6899 def VST1LNdWB_fixed_Asm_16 :
6900 NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr!",
6901 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6903 def VST1LNdWB_fixed_Asm_32 :
6904 NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr!",
6905 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6907 def VST1LNdWB_register_Asm_8 :
6908 NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr, $Rm",
6909 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6910 rGPR:$Rm, pred:$p)>;
6911 def VST1LNdWB_register_Asm_16 :
6912 NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr, $Rm",
6913 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6914 rGPR:$Rm, pred:$p)>;
6915 def VST1LNdWB_register_Asm_32 :
6916 NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr, $Rm",
6917 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6918 rGPR:$Rm, pred:$p)>;
6920 // VLD2 single-lane pseudo-instructions. These need special handling for
6921 // the lane index that an InstAlias can't handle, so we use these instead.
6922 def VLD2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr",
6923 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
6925 def VLD2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr",
6926 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
6928 def VLD2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr",
6929 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr, pred:$p)>;
6930 def VLD2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr",
6931 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
6933 def VLD2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr",
6934 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
6937 def VLD2LNdWB_fixed_Asm_8 :
6938 NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr!",
6939 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
6941 def VLD2LNdWB_fixed_Asm_16 :
6942 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!",
6943 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
6945 def VLD2LNdWB_fixed_Asm_32 :
6946 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!",
6947 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,
6949 def VLD2LNqWB_fixed_Asm_16 :
6950 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!",
6951 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
6953 def VLD2LNqWB_fixed_Asm_32 :
6954 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!",
6955 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
6957 def VLD2LNdWB_register_Asm_8 :
6958 NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr, $Rm",
6959 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
6960 rGPR:$Rm, pred:$p)>;
6961 def VLD2LNdWB_register_Asm_16 :
6962 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm",
6963 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
6964 rGPR:$Rm, pred:$p)>;
6965 def VLD2LNdWB_register_Asm_32 :
6966 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm",
6967 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,
6968 rGPR:$Rm, pred:$p)>;
6969 def VLD2LNqWB_register_Asm_16 :
6970 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm",
6971 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
6972 rGPR:$Rm, pred:$p)>;
6973 def VLD2LNqWB_register_Asm_32 :
6974 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm",
6975 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
6976 rGPR:$Rm, pred:$p)>;
6979 // VST2 single-lane pseudo-instructions. These need special handling for
6980 // the lane index that an InstAlias can't handle, so we use these instead.
6981 def VST2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr",
6982 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
6984 def VST2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr",
6985 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
6987 def VST2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr",
6988 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,
6990 def VST2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr",
6991 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
6993 def VST2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr",
6994 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
6997 def VST2LNdWB_fixed_Asm_8 :
6998 NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr!",
6999 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
7001 def VST2LNdWB_fixed_Asm_16 :
7002 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!",
7003 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
7005 def VST2LNdWB_fixed_Asm_32 :
7006 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!",
7007 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,
7009 def VST2LNqWB_fixed_Asm_16 :
7010 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!",
7011 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
7013 def VST2LNqWB_fixed_Asm_32 :
7014 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!",
7015 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
7017 def VST2LNdWB_register_Asm_8 :
7018 NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr, $Rm",
7019 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
7020 rGPR:$Rm, pred:$p)>;
7021 def VST2LNdWB_register_Asm_16 :
7022 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm",
7023 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
7024 rGPR:$Rm, pred:$p)>;
7025 def VST2LNdWB_register_Asm_32 :
7026 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm",
7027 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,
7028 rGPR:$Rm, pred:$p)>;
7029 def VST2LNqWB_register_Asm_16 :
7030 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm",
7031 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
7032 rGPR:$Rm, pred:$p)>;
7033 def VST2LNqWB_register_Asm_32 :
7034 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm",
7035 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
7036 rGPR:$Rm, pred:$p)>;
7038 // VLD3 all-lanes pseudo-instructions. These need special handling for
7039 // the lane index that an InstAlias can't handle, so we use these instead.
7040 def VLD3DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
7041 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
7043 def VLD3DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
7044 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
7046 def VLD3DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
7047 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
7049 def VLD3DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
7050 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
7052 def VLD3DUPqAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
7053 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
7055 def VLD3DUPqAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
7056 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
7059 def VLD3DUPdWB_fixed_Asm_8 :
7060 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
7061 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
7063 def VLD3DUPdWB_fixed_Asm_16 :
7064 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
7065 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
7067 def VLD3DUPdWB_fixed_Asm_32 :
7068 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
7069 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
7071 def VLD3DUPqWB_fixed_Asm_8 :
7072 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
7073 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
7075 def VLD3DUPqWB_fixed_Asm_16 :
7076 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
7077 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
7079 def VLD3DUPqWB_fixed_Asm_32 :
7080 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
7081 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
7083 def VLD3DUPdWB_register_Asm_8 :
7084 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
7085 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
7086 rGPR:$Rm, pred:$p)>;
7087 def VLD3DUPdWB_register_Asm_16 :
7088 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
7089 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
7090 rGPR:$Rm, pred:$p)>;
7091 def VLD3DUPdWB_register_Asm_32 :
7092 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
7093 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
7094 rGPR:$Rm, pred:$p)>;
7095 def VLD3DUPqWB_register_Asm_8 :
7096 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
7097 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
7098 rGPR:$Rm, pred:$p)>;
7099 def VLD3DUPqWB_register_Asm_16 :
7100 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
7101 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
7102 rGPR:$Rm, pred:$p)>;
7103 def VLD3DUPqWB_register_Asm_32 :
7104 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
7105 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
7106 rGPR:$Rm, pred:$p)>;
7109 // VLD3 single-lane pseudo-instructions. These need special handling for
7110 // the lane index that an InstAlias can't handle, so we use these instead.
7111 def VLD3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
7112 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
7114 def VLD3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
7115 (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr,
7117 def VLD3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
7118 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
7120 def VLD3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
7121 (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr,
7123 def VLD3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
7124 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
7127 def VLD3LNdWB_fixed_Asm_8 :
7128 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
7129 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
7131 def VLD3LNdWB_fixed_Asm_16 :
7132 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
7133 (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr,
7135 def VLD3LNdWB_fixed_Asm_32 :
7136 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
7137 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
7139 def VLD3LNqWB_fixed_Asm_16 :
7140 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
7141 (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr,
7143 def VLD3LNqWB_fixed_Asm_32 :
7144 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
7145 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
7147 def VLD3LNdWB_register_Asm_8 :
7148 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
7149 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
7150 rGPR:$Rm, pred:$p)>;
7151 def VLD3LNdWB_register_Asm_16 :
7152 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
7153 (ins VecListThreeDHWordIndexed:$list,
7154 addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>;
7155 def VLD3LNdWB_register_Asm_32 :
7156 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
7157 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
7158 rGPR:$Rm, pred:$p)>;
7159 def VLD3LNqWB_register_Asm_16 :
7160 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
7161 (ins VecListThreeQHWordIndexed:$list,
7162 addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>;
7163 def VLD3LNqWB_register_Asm_32 :
7164 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
7165 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
7166 rGPR:$Rm, pred:$p)>;
7168 // VLD3 multiple structure pseudo-instructions. These need special handling for
7169 // the vector operands that the normal instructions don't yet model.
7170 // FIXME: Remove these when the register classes and instructions are updated.
7171 def VLD3dAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
7172 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
7173 def VLD3dAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
7174 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
7175 def VLD3dAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
7176 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
7177 def VLD3qAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
7178 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
7179 def VLD3qAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
7180 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
7181 def VLD3qAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
7182 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
7184 def VLD3dWB_fixed_Asm_8 :
7185 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
7186 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
7187 def VLD3dWB_fixed_Asm_16 :
7188 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
7189 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
7190 def VLD3dWB_fixed_Asm_32 :
7191 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
7192 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
7193 def VLD3qWB_fixed_Asm_8 :
7194 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
7195 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
7196 def VLD3qWB_fixed_Asm_16 :
7197 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
7198 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
7199 def VLD3qWB_fixed_Asm_32 :
7200 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
7201 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
7202 def VLD3dWB_register_Asm_8 :
7203 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
7204 (ins VecListThreeD:$list, addrmode6align64:$addr,
7205 rGPR:$Rm, pred:$p)>;
7206 def VLD3dWB_register_Asm_16 :
7207 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
7208 (ins VecListThreeD:$list, addrmode6align64:$addr,
7209 rGPR:$Rm, pred:$p)>;
7210 def VLD3dWB_register_Asm_32 :
7211 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
7212 (ins VecListThreeD:$list, addrmode6align64:$addr,
7213 rGPR:$Rm, pred:$p)>;
7214 def VLD3qWB_register_Asm_8 :
7215 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
7216 (ins VecListThreeQ:$list, addrmode6align64:$addr,
7217 rGPR:$Rm, pred:$p)>;
7218 def VLD3qWB_register_Asm_16 :
7219 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
7220 (ins VecListThreeQ:$list, addrmode6align64:$addr,
7221 rGPR:$Rm, pred:$p)>;
7222 def VLD3qWB_register_Asm_32 :
7223 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
7224 (ins VecListThreeQ:$list, addrmode6align64:$addr,
7225 rGPR:$Rm, pred:$p)>;
7227 // VST3 single-lane pseudo-instructions. These need special handling for
7228 // the lane index that an InstAlias can't handle, so we use these instead.
7229 def VST3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
7230 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
7232 def VST3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
7233 (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr,
7235 def VST3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
7236 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
7238 def VST3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
7239 (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr,
7241 def VST3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
7242 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
7245 def VST3LNdWB_fixed_Asm_8 :
7246 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
7247 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
7249 def VST3LNdWB_fixed_Asm_16 :
7250 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
7251 (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr,
7253 def VST3LNdWB_fixed_Asm_32 :
7254 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
7255 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
7257 def VST3LNqWB_fixed_Asm_16 :
7258 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
7259 (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr,
7261 def VST3LNqWB_fixed_Asm_32 :
7262 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
7263 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
7265 def VST3LNdWB_register_Asm_8 :
7266 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
7267 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
7268 rGPR:$Rm, pred:$p)>;
7269 def VST3LNdWB_register_Asm_16 :
7270 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
7271 (ins VecListThreeDHWordIndexed:$list,
7272 addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>;
7273 def VST3LNdWB_register_Asm_32 :
7274 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
7275 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
7276 rGPR:$Rm, pred:$p)>;
7277 def VST3LNqWB_register_Asm_16 :
7278 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
7279 (ins VecListThreeQHWordIndexed:$list,
7280 addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>;
7281 def VST3LNqWB_register_Asm_32 :
7282 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
7283 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
7284 rGPR:$Rm, pred:$p)>;
7287 // VST3 multiple structure pseudo-instructions. These need special handling for
7288 // the vector operands that the normal instructions don't yet model.
7289 // FIXME: Remove these when the register classes and instructions are updated.
7290 def VST3dAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
7291 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
7292 def VST3dAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
7293 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
7294 def VST3dAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
7295 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
7296 def VST3qAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
7297 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
7298 def VST3qAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
7299 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
7300 def VST3qAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
7301 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
7303 def VST3dWB_fixed_Asm_8 :
7304 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
7305 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
7306 def VST3dWB_fixed_Asm_16 :
7307 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
7308 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
7309 def VST3dWB_fixed_Asm_32 :
7310 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
7311 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
7312 def VST3qWB_fixed_Asm_8 :
7313 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
7314 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
7315 def VST3qWB_fixed_Asm_16 :
7316 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
7317 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
7318 def VST3qWB_fixed_Asm_32 :
7319 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
7320 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
7321 def VST3dWB_register_Asm_8 :
7322 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
7323 (ins VecListThreeD:$list, addrmode6align64:$addr,
7324 rGPR:$Rm, pred:$p)>;
7325 def VST3dWB_register_Asm_16 :
7326 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
7327 (ins VecListThreeD:$list, addrmode6align64:$addr,
7328 rGPR:$Rm, pred:$p)>;
7329 def VST3dWB_register_Asm_32 :
7330 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
7331 (ins VecListThreeD:$list, addrmode6align64:$addr,
7332 rGPR:$Rm, pred:$p)>;
7333 def VST3qWB_register_Asm_8 :
7334 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
7335 (ins VecListThreeQ:$list, addrmode6align64:$addr,
7336 rGPR:$Rm, pred:$p)>;
7337 def VST3qWB_register_Asm_16 :
7338 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
7339 (ins VecListThreeQ:$list, addrmode6align64:$addr,
7340 rGPR:$Rm, pred:$p)>;
7341 def VST3qWB_register_Asm_32 :
7342 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
7343 (ins VecListThreeQ:$list, addrmode6align64:$addr,
7344 rGPR:$Rm, pred:$p)>;
7346 // VLD4 all-lanes pseudo-instructions. These need special handling for
7347 // the lane index that an InstAlias can't handle, so we use these instead.
7348 def VLD4DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
7349 (ins VecListFourDAllLanes:$list, addrmode6dupalign32:$addr,
7351 def VLD4DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
7352 (ins VecListFourDAllLanes:$list, addrmode6dupalign64:$addr,
7354 def VLD4DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
7355 (ins VecListFourDAllLanes:$list, addrmode6dupalign64or128:$addr,
7357 def VLD4DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
7358 (ins VecListFourQAllLanes:$list, addrmode6dupalign32:$addr,
7360 def VLD4DUPqAsm_16: NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
7361 (ins VecListFourQAllLanes:$list, addrmode6dupalign64:$addr,
7363 def VLD4DUPqAsm_32: NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
7364 (ins VecListFourQAllLanes:$list, addrmode6dupalign64or128:$addr,
7367 def VLD4DUPdWB_fixed_Asm_8 :
7368 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
7369 (ins VecListFourDAllLanes:$list, addrmode6dupalign32:$addr,
7371 def VLD4DUPdWB_fixed_Asm_16 :
7372 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
7373 (ins VecListFourDAllLanes:$list, addrmode6dupalign64:$addr,
7375 def VLD4DUPdWB_fixed_Asm_32 :
7376 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
7377 (ins VecListFourDAllLanes:$list, addrmode6dupalign64or128:$addr,
7379 def VLD4DUPqWB_fixed_Asm_8 :
7380 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
7381 (ins VecListFourQAllLanes:$list, addrmode6dupalign32:$addr,
7383 def VLD4DUPqWB_fixed_Asm_16 :
7384 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
7385 (ins VecListFourQAllLanes:$list, addrmode6dupalign64:$addr,
7387 def VLD4DUPqWB_fixed_Asm_32 :
7388 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
7389 (ins VecListFourQAllLanes:$list, addrmode6dupalign64or128:$addr,
7391 def VLD4DUPdWB_register_Asm_8 :
7392 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
7393 (ins VecListFourDAllLanes:$list, addrmode6dupalign32:$addr,
7394 rGPR:$Rm, pred:$p)>;
7395 def VLD4DUPdWB_register_Asm_16 :
7396 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
7397 (ins VecListFourDAllLanes:$list, addrmode6dupalign64:$addr,
7398 rGPR:$Rm, pred:$p)>;
7399 def VLD4DUPdWB_register_Asm_32 :
7400 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
7401 (ins VecListFourDAllLanes:$list,
7402 addrmode6dupalign64or128:$addr, rGPR:$Rm, pred:$p)>;
7403 def VLD4DUPqWB_register_Asm_8 :
7404 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
7405 (ins VecListFourQAllLanes:$list, addrmode6dupalign32:$addr,
7406 rGPR:$Rm, pred:$p)>;
7407 def VLD4DUPqWB_register_Asm_16 :
7408 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
7409 (ins VecListFourQAllLanes:$list, addrmode6dupalign64:$addr,
7410 rGPR:$Rm, pred:$p)>;
7411 def VLD4DUPqWB_register_Asm_32 :
7412 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
7413 (ins VecListFourQAllLanes:$list,
7414 addrmode6dupalign64or128:$addr, rGPR:$Rm, pred:$p)>;
7417 // VLD4 single-lane pseudo-instructions. These need special handling for
7418 // the lane index that an InstAlias can't handle, so we use these instead.
7419 def VLD4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
7420 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
7422 def VLD4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
7423 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
7425 def VLD4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
7426 (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr,
7428 def VLD4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
7429 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
7431 def VLD4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
7432 (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr,
7435 def VLD4LNdWB_fixed_Asm_8 :
7436 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
7437 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
7439 def VLD4LNdWB_fixed_Asm_16 :
7440 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
7441 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
7443 def VLD4LNdWB_fixed_Asm_32 :
7444 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
7445 (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr,
7447 def VLD4LNqWB_fixed_Asm_16 :
7448 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
7449 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
7451 def VLD4LNqWB_fixed_Asm_32 :
7452 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
7453 (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr,
7455 def VLD4LNdWB_register_Asm_8 :
7456 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
7457 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
7458 rGPR:$Rm, pred:$p)>;
7459 def VLD4LNdWB_register_Asm_16 :
7460 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
7461 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
7462 rGPR:$Rm, pred:$p)>;
7463 def VLD4LNdWB_register_Asm_32 :
7464 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
7465 (ins VecListFourDWordIndexed:$list,
7466 addrmode6align64or128:$addr, rGPR:$Rm, pred:$p)>;
7467 def VLD4LNqWB_register_Asm_16 :
7468 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
7469 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
7470 rGPR:$Rm, pred:$p)>;
7471 def VLD4LNqWB_register_Asm_32 :
7472 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
7473 (ins VecListFourQWordIndexed:$list,
7474 addrmode6align64or128:$addr, rGPR:$Rm, pred:$p)>;
7478 // VLD4 multiple structure pseudo-instructions. These need special handling for
7479 // the vector operands that the normal instructions don't yet model.
7480 // FIXME: Remove these when the register classes and instructions are updated.
7481 def VLD4dAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
7482 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7484 def VLD4dAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
7485 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7487 def VLD4dAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
7488 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7490 def VLD4qAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
7491 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7493 def VLD4qAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
7494 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7496 def VLD4qAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
7497 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7500 def VLD4dWB_fixed_Asm_8 :
7501 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
7502 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7504 def VLD4dWB_fixed_Asm_16 :
7505 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
7506 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7508 def VLD4dWB_fixed_Asm_32 :
7509 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
7510 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7512 def VLD4qWB_fixed_Asm_8 :
7513 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
7514 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7516 def VLD4qWB_fixed_Asm_16 :
7517 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
7518 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7520 def VLD4qWB_fixed_Asm_32 :
7521 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
7522 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7524 def VLD4dWB_register_Asm_8 :
7525 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
7526 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7527 rGPR:$Rm, pred:$p)>;
7528 def VLD4dWB_register_Asm_16 :
7529 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
7530 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7531 rGPR:$Rm, pred:$p)>;
7532 def VLD4dWB_register_Asm_32 :
7533 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
7534 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7535 rGPR:$Rm, pred:$p)>;
7536 def VLD4qWB_register_Asm_8 :
7537 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
7538 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7539 rGPR:$Rm, pred:$p)>;
7540 def VLD4qWB_register_Asm_16 :
7541 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
7542 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7543 rGPR:$Rm, pred:$p)>;
7544 def VLD4qWB_register_Asm_32 :
7545 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
7546 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7547 rGPR:$Rm, pred:$p)>;
7549 // VST4 single-lane pseudo-instructions. These need special handling for
7550 // the lane index that an InstAlias can't handle, so we use these instead.
7551 def VST4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
7552 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
7554 def VST4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
7555 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
7557 def VST4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
7558 (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr,
7560 def VST4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
7561 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
7563 def VST4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
7564 (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr,
7567 def VST4LNdWB_fixed_Asm_8 :
7568 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
7569 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
7571 def VST4LNdWB_fixed_Asm_16 :
7572 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
7573 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
7575 def VST4LNdWB_fixed_Asm_32 :
7576 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
7577 (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr,
7579 def VST4LNqWB_fixed_Asm_16 :
7580 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
7581 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
7583 def VST4LNqWB_fixed_Asm_32 :
7584 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
7585 (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr,
7587 def VST4LNdWB_register_Asm_8 :
7588 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
7589 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
7590 rGPR:$Rm, pred:$p)>;
7591 def VST4LNdWB_register_Asm_16 :
7592 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
7593 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
7594 rGPR:$Rm, pred:$p)>;
7595 def VST4LNdWB_register_Asm_32 :
7596 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
7597 (ins VecListFourDWordIndexed:$list,
7598 addrmode6align64or128:$addr, rGPR:$Rm, pred:$p)>;
7599 def VST4LNqWB_register_Asm_16 :
7600 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
7601 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
7602 rGPR:$Rm, pred:$p)>;
7603 def VST4LNqWB_register_Asm_32 :
7604 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
7605 (ins VecListFourQWordIndexed:$list,
7606 addrmode6align64or128:$addr, rGPR:$Rm, pred:$p)>;
7609 // VST4 multiple structure pseudo-instructions. These need special handling for
7610 // the vector operands that the normal instructions don't yet model.
7611 // FIXME: Remove these when the register classes and instructions are updated.
7612 def VST4dAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
7613 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7615 def VST4dAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
7616 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7618 def VST4dAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
7619 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7621 def VST4qAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
7622 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7624 def VST4qAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
7625 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7627 def VST4qAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
7628 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7631 def VST4dWB_fixed_Asm_8 :
7632 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
7633 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7635 def VST4dWB_fixed_Asm_16 :
7636 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
7637 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7639 def VST4dWB_fixed_Asm_32 :
7640 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
7641 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7643 def VST4qWB_fixed_Asm_8 :
7644 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
7645 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7647 def VST4qWB_fixed_Asm_16 :
7648 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
7649 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7651 def VST4qWB_fixed_Asm_32 :
7652 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
7653 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7655 def VST4dWB_register_Asm_8 :
7656 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
7657 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7658 rGPR:$Rm, pred:$p)>;
7659 def VST4dWB_register_Asm_16 :
7660 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
7661 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7662 rGPR:$Rm, pred:$p)>;
7663 def VST4dWB_register_Asm_32 :
7664 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
7665 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7666 rGPR:$Rm, pred:$p)>;
7667 def VST4qWB_register_Asm_8 :
7668 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
7669 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7670 rGPR:$Rm, pred:$p)>;
7671 def VST4qWB_register_Asm_16 :
7672 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
7673 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7674 rGPR:$Rm, pred:$p)>;
7675 def VST4qWB_register_Asm_32 :
7676 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
7677 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7678 rGPR:$Rm, pred:$p)>;
7680 // VMOV/VMVN takes an optional datatype suffix
7681 defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
7682 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
7683 defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
7684 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
7686 defm : NEONDTAnyInstAlias<"vmvn${p}", "$Vd, $Vm",
7687 (VMVNd DPR:$Vd, DPR:$Vm, pred:$p)>;
7688 defm : NEONDTAnyInstAlias<"vmvn${p}", "$Vd, $Vm",
7689 (VMVNq QPR:$Vd, QPR:$Vm, pred:$p)>;
7691 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
7692 // D-register versions.
7693 def : NEONInstAlias<"vcle${p}.s8 $Dd, $Dn, $Dm",
7694 (VCGEsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7695 def : NEONInstAlias<"vcle${p}.s16 $Dd, $Dn, $Dm",
7696 (VCGEsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7697 def : NEONInstAlias<"vcle${p}.s32 $Dd, $Dn, $Dm",
7698 (VCGEsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7699 def : NEONInstAlias<"vcle${p}.u8 $Dd, $Dn, $Dm",
7700 (VCGEuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7701 def : NEONInstAlias<"vcle${p}.u16 $Dd, $Dn, $Dm",
7702 (VCGEuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7703 def : NEONInstAlias<"vcle${p}.u32 $Dd, $Dn, $Dm",
7704 (VCGEuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7705 def : NEONInstAlias<"vcle${p}.f32 $Dd, $Dn, $Dm",
7706 (VCGEfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7707 // Q-register versions.
7708 def : NEONInstAlias<"vcle${p}.s8 $Qd, $Qn, $Qm",
7709 (VCGEsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7710 def : NEONInstAlias<"vcle${p}.s16 $Qd, $Qn, $Qm",
7711 (VCGEsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7712 def : NEONInstAlias<"vcle${p}.s32 $Qd, $Qn, $Qm",
7713 (VCGEsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7714 def : NEONInstAlias<"vcle${p}.u8 $Qd, $Qn, $Qm",
7715 (VCGEuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7716 def : NEONInstAlias<"vcle${p}.u16 $Qd, $Qn, $Qm",
7717 (VCGEuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7718 def : NEONInstAlias<"vcle${p}.u32 $Qd, $Qn, $Qm",
7719 (VCGEuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7720 def : NEONInstAlias<"vcle${p}.f32 $Qd, $Qn, $Qm",
7721 (VCGEfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7723 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
7724 // D-register versions.
7725 def : NEONInstAlias<"vclt${p}.s8 $Dd, $Dn, $Dm",
7726 (VCGTsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7727 def : NEONInstAlias<"vclt${p}.s16 $Dd, $Dn, $Dm",
7728 (VCGTsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7729 def : NEONInstAlias<"vclt${p}.s32 $Dd, $Dn, $Dm",
7730 (VCGTsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7731 def : NEONInstAlias<"vclt${p}.u8 $Dd, $Dn, $Dm",
7732 (VCGTuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7733 def : NEONInstAlias<"vclt${p}.u16 $Dd, $Dn, $Dm",
7734 (VCGTuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7735 def : NEONInstAlias<"vclt${p}.u32 $Dd, $Dn, $Dm",
7736 (VCGTuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7737 def : NEONInstAlias<"vclt${p}.f32 $Dd, $Dn, $Dm",
7738 (VCGTfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7739 // Q-register versions.
7740 def : NEONInstAlias<"vclt${p}.s8 $Qd, $Qn, $Qm",
7741 (VCGTsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7742 def : NEONInstAlias<"vclt${p}.s16 $Qd, $Qn, $Qm",
7743 (VCGTsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7744 def : NEONInstAlias<"vclt${p}.s32 $Qd, $Qn, $Qm",
7745 (VCGTsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7746 def : NEONInstAlias<"vclt${p}.u8 $Qd, $Qn, $Qm",
7747 (VCGTuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7748 def : NEONInstAlias<"vclt${p}.u16 $Qd, $Qn, $Qm",
7749 (VCGTuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7750 def : NEONInstAlias<"vclt${p}.u32 $Qd, $Qn, $Qm",
7751 (VCGTuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7752 def : NEONInstAlias<"vclt${p}.f32 $Qd, $Qn, $Qm",
7753 (VCGTfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7755 // VSWP allows, but does not require, a type suffix.
7756 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
7757 (VSWPd DPR:$Vd, DPR:$Vm, pred:$p)>;
7758 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
7759 (VSWPq QPR:$Vd, QPR:$Vm, pred:$p)>;
7761 // VBIF, VBIT, and VBSL allow, but do not require, a type suffix.
7762 defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm",
7763 (VBIFd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
7764 defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm",
7765 (VBITd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
7766 defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm",
7767 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
7768 defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm",
7769 (VBIFq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
7770 defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm",
7771 (VBITq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
7772 defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm",
7773 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
7775 // "vmov Rd, #-imm" can be handled via "vmvn".
7776 def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
7777 (VMVNv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
7778 def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
7779 (VMVNv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
7780 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
7781 (VMOVv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
7782 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
7783 (VMOVv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
7785 // 'gas' compatibility aliases for quad-word instructions. Strictly speaking,
7786 // these should restrict to just the Q register variants, but the register
7787 // classes are enough to match correctly regardless, so we keep it simple
7788 // and just use MnemonicAlias.
7789 def : NEONMnemonicAlias<"vbicq", "vbic">;
7790 def : NEONMnemonicAlias<"vandq", "vand">;
7791 def : NEONMnemonicAlias<"veorq", "veor">;
7792 def : NEONMnemonicAlias<"vorrq", "vorr">;
7794 def : NEONMnemonicAlias<"vmovq", "vmov">;
7795 def : NEONMnemonicAlias<"vmvnq", "vmvn">;
7796 // Explicit versions for floating point so that the FPImm variants get
7797 // handled early. The parser gets confused otherwise.
7798 def : NEONMnemonicAlias<"vmovq.f32", "vmov.f32">;
7799 def : NEONMnemonicAlias<"vmovq.f64", "vmov.f64">;
7801 def : NEONMnemonicAlias<"vaddq", "vadd">;
7802 def : NEONMnemonicAlias<"vsubq", "vsub">;
7804 def : NEONMnemonicAlias<"vminq", "vmin">;
7805 def : NEONMnemonicAlias<"vmaxq", "vmax">;
7807 def : NEONMnemonicAlias<"vmulq", "vmul">;
7809 def : NEONMnemonicAlias<"vabsq", "vabs">;
7811 def : NEONMnemonicAlias<"vshlq", "vshl">;
7812 def : NEONMnemonicAlias<"vshrq", "vshr">;
7814 def : NEONMnemonicAlias<"vcvtq", "vcvt">;
7816 def : NEONMnemonicAlias<"vcleq", "vcle">;
7817 def : NEONMnemonicAlias<"vceqq", "vceq">;
7819 def : NEONMnemonicAlias<"vzipq", "vzip">;
7820 def : NEONMnemonicAlias<"vswpq", "vswp">;
7822 def : NEONMnemonicAlias<"vrecpeq.f32", "vrecpe.f32">;
7823 def : NEONMnemonicAlias<"vrecpeq.u32", "vrecpe.u32">;
7826 // Alias for loading floating point immediates that aren't representable
7827 // using the vmov.f32 encoding but the bitpattern is representable using
7828 // the .i32 encoding.
7829 def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
7830 (VMOVv4i32 QPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;
7831 def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
7832 (VMOVv2i32 DPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;