1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
19 def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
21 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
22 def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
23 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
24 def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
25 def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
26 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
27 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
28 def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
29 def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
30 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
31 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
33 // Types for vector shift by immediates. The "SHX" version is for long and
34 // narrow operations where the source and destination vectors have different
35 // types. The "SHINS" version is for shift and insert operations.
36 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
38 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
40 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
43 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
44 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
45 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
46 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
47 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
48 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
49 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
51 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
52 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
53 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
55 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
56 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
57 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
58 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
59 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
60 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
62 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
63 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
64 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
66 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
67 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
69 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
71 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
72 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
74 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
75 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
76 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
78 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
80 def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
81 def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
83 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
85 // VDUPLANE can produce a quad-register result from a double-register source,
86 // so the result is not constrained to match the source.
87 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
88 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
91 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
92 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
93 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
95 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
96 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
97 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
98 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
100 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
102 SDTCisSameAs<0, 3>]>;
103 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
104 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
105 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
107 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
108 SDTCisSameAs<1, 2>]>;
109 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
110 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
112 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
113 SDTCisSameAs<0, 2>]>;
114 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
115 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
117 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
118 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
119 unsigned EltBits = 0;
120 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
121 return (EltBits == 32 && EltVal == 0);
124 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
125 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
126 unsigned EltBits = 0;
127 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
128 return (EltBits == 8 && EltVal == 0xff);
131 //===----------------------------------------------------------------------===//
132 // NEON operand definitions
133 //===----------------------------------------------------------------------===//
135 def nModImm : Operand<i32> {
136 let PrintMethod = "printNEONModImmOperand";
139 //===----------------------------------------------------------------------===//
140 // NEON load / store instructions
141 //===----------------------------------------------------------------------===//
143 // Use VLDM to load a Q register as a D register pair.
144 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
146 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
148 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
150 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
152 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
154 // Use VSTM to store a Q register as a D register pair.
155 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
157 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
159 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
161 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
163 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
165 // Classes for VLD* pseudo-instructions with multi-register operands.
166 // These are expanded to real instructions after register allocation.
167 class VLDQPseudo<InstrItinClass itin>
168 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
169 class VLDQWBPseudo<InstrItinClass itin>
170 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
171 (ins addrmode6:$addr, am6offset:$offset), itin,
173 class VLDQQPseudo<InstrItinClass itin>
174 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
175 class VLDQQWBPseudo<InstrItinClass itin>
176 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
177 (ins addrmode6:$addr, am6offset:$offset), itin,
179 class VLDQQQQWBPseudo<InstrItinClass itin>
180 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
181 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
182 "$addr.addr = $wb, $src = $dst">;
184 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
186 // VLD1 : Vector Load (multiple single elements)
187 class VLD1D<bits<4> op7_4, string Dt>
188 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd),
189 (ins addrmode6:$Rn), IIC_VLD1,
190 "vld1", Dt, "\\{$Vd\\}, $Rn", "", []> {
194 class VLD1Q<bits<4> op7_4, string Dt>
195 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2),
196 (ins addrmode6:$Rn), IIC_VLD1x2,
197 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
199 let Inst{5-4} = Rn{5-4};
202 def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
203 def VLD1d16 : VLD1D<{0,1,0,?}, "16">;
204 def VLD1d32 : VLD1D<{1,0,0,?}, "32">;
205 def VLD1d64 : VLD1D<{1,1,0,?}, "64">;
207 def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;
208 def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
209 def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
210 def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
212 def VLD1q8Pseudo : VLDQPseudo<IIC_VLD1x2>;
213 def VLD1q16Pseudo : VLDQPseudo<IIC_VLD1x2>;
214 def VLD1q32Pseudo : VLDQPseudo<IIC_VLD1x2>;
215 def VLD1q64Pseudo : VLDQPseudo<IIC_VLD1x2>;
217 // ...with address register writeback:
218 class VLD1DWB<bits<4> op7_4, string Dt>
219 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd, GPR:$wb),
220 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1u,
221 "vld1", Dt, "\\{$Vd\\}, $Rn$Rm",
222 "$Rn.addr = $wb", []> {
225 class VLD1QWB<bits<4> op7_4, string Dt>
226 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
227 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x2u,
228 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
229 "$Rn.addr = $wb", []> {
230 let Inst{5-4} = Rn{5-4};
233 def VLD1d8_UPD : VLD1DWB<{0,0,0,?}, "8">;
234 def VLD1d16_UPD : VLD1DWB<{0,1,0,?}, "16">;
235 def VLD1d32_UPD : VLD1DWB<{1,0,0,?}, "32">;
236 def VLD1d64_UPD : VLD1DWB<{1,1,0,?}, "64">;
238 def VLD1q8_UPD : VLD1QWB<{0,0,?,?}, "8">;
239 def VLD1q16_UPD : VLD1QWB<{0,1,?,?}, "16">;
240 def VLD1q32_UPD : VLD1QWB<{1,0,?,?}, "32">;
241 def VLD1q64_UPD : VLD1QWB<{1,1,?,?}, "64">;
243 def VLD1q8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
244 def VLD1q16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
245 def VLD1q32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
246 def VLD1q64Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
248 // ...with 3 registers (some of these are only for the disassembler):
249 class VLD1D3<bits<4> op7_4, string Dt>
250 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
251 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
252 "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
256 class VLD1D3WB<bits<4> op7_4, string Dt>
257 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
258 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x3u, "vld1", Dt,
259 "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
263 def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
264 def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;
265 def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;
266 def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;
268 def VLD1d8T_UPD : VLD1D3WB<{0,0,0,?}, "8">;
269 def VLD1d16T_UPD : VLD1D3WB<{0,1,0,?}, "16">;
270 def VLD1d32T_UPD : VLD1D3WB<{1,0,0,?}, "32">;
271 def VLD1d64T_UPD : VLD1D3WB<{1,1,0,?}, "64">;
273 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
274 def VLD1d64TPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x3u>;
276 // ...with 4 registers (some of these are only for the disassembler):
277 class VLD1D4<bits<4> op7_4, string Dt>
278 : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
279 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
280 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
282 let Inst{5-4} = Rn{5-4};
284 class VLD1D4WB<bits<4> op7_4, string Dt>
285 : NLdSt<0,0b10,0b0010,op7_4,
286 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
287 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4, "vld1", Dt,
288 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", "$Rn.addr = $wb",
290 let Inst{5-4} = Rn{5-4};
293 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
294 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;
295 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;
296 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;
298 def VLD1d8Q_UPD : VLD1D4WB<{0,0,?,?}, "8">;
299 def VLD1d16Q_UPD : VLD1D4WB<{0,1,?,?}, "16">;
300 def VLD1d32Q_UPD : VLD1D4WB<{1,0,?,?}, "32">;
301 def VLD1d64Q_UPD : VLD1D4WB<{1,1,?,?}, "64">;
303 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
304 def VLD1d64QPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x4u>;
306 // VLD2 : Vector Load (multiple 2-element structures)
307 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
308 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
309 (ins addrmode6:$Rn), IIC_VLD2,
310 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
312 let Inst{5-4} = Rn{5-4};
314 class VLD2Q<bits<4> op7_4, string Dt>
315 : NLdSt<0, 0b10, 0b0011, op7_4,
316 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
317 (ins addrmode6:$Rn), IIC_VLD2x2,
318 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
320 let Inst{5-4} = Rn{5-4};
323 def VLD2d8 : VLD2D<0b1000, {0,0,?,?}, "8">;
324 def VLD2d16 : VLD2D<0b1000, {0,1,?,?}, "16">;
325 def VLD2d32 : VLD2D<0b1000, {1,0,?,?}, "32">;
327 def VLD2q8 : VLD2Q<{0,0,?,?}, "8">;
328 def VLD2q16 : VLD2Q<{0,1,?,?}, "16">;
329 def VLD2q32 : VLD2Q<{1,0,?,?}, "32">;
331 def VLD2d8Pseudo : VLDQPseudo<IIC_VLD2>;
332 def VLD2d16Pseudo : VLDQPseudo<IIC_VLD2>;
333 def VLD2d32Pseudo : VLDQPseudo<IIC_VLD2>;
335 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
336 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
337 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
339 // ...with address register writeback:
340 class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
341 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
342 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2u,
343 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
344 "$Rn.addr = $wb", []> {
345 let Inst{5-4} = Rn{5-4};
347 class VLD2QWB<bits<4> op7_4, string Dt>
348 : NLdSt<0, 0b10, 0b0011, op7_4,
349 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
350 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2x2u,
351 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
352 "$Rn.addr = $wb", []> {
353 let Inst{5-4} = Rn{5-4};
356 def VLD2d8_UPD : VLD2DWB<0b1000, {0,0,?,?}, "8">;
357 def VLD2d16_UPD : VLD2DWB<0b1000, {0,1,?,?}, "16">;
358 def VLD2d32_UPD : VLD2DWB<0b1000, {1,0,?,?}, "32">;
360 def VLD2q8_UPD : VLD2QWB<{0,0,?,?}, "8">;
361 def VLD2q16_UPD : VLD2QWB<{0,1,?,?}, "16">;
362 def VLD2q32_UPD : VLD2QWB<{1,0,?,?}, "32">;
364 def VLD2d8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
365 def VLD2d16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
366 def VLD2d32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
368 def VLD2q8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
369 def VLD2q16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
370 def VLD2q32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
372 // ...with double-spaced registers (for disassembly only):
373 def VLD2b8 : VLD2D<0b1001, {0,0,?,?}, "8">;
374 def VLD2b16 : VLD2D<0b1001, {0,1,?,?}, "16">;
375 def VLD2b32 : VLD2D<0b1001, {1,0,?,?}, "32">;
376 def VLD2b8_UPD : VLD2DWB<0b1001, {0,0,?,?}, "8">;
377 def VLD2b16_UPD : VLD2DWB<0b1001, {0,1,?,?}, "16">;
378 def VLD2b32_UPD : VLD2DWB<0b1001, {1,0,?,?}, "32">;
380 // VLD3 : Vector Load (multiple 3-element structures)
381 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
382 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
383 (ins addrmode6:$Rn), IIC_VLD3,
384 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
389 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
390 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
391 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
393 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
394 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
395 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
397 // ...with address register writeback:
398 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
399 : NLdSt<0, 0b10, op11_8, op7_4,
400 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
401 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
402 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
403 "$Rn.addr = $wb", []> {
407 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
408 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
409 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
411 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
412 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
413 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
415 // ...with double-spaced registers (non-updating versions for disassembly only):
416 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
417 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
418 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
419 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
420 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
421 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
423 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
424 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
425 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
427 // ...alternate versions to be allocated odd register numbers:
428 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
429 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
430 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
432 // VLD4 : Vector Load (multiple 4-element structures)
433 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
434 : NLdSt<0, 0b10, op11_8, op7_4,
435 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
436 (ins addrmode6:$Rn), IIC_VLD4,
437 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
439 let Inst{5-4} = Rn{5-4};
442 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
443 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
444 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
446 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
447 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
448 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
450 // ...with address register writeback:
451 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
452 : NLdSt<0, 0b10, op11_8, op7_4,
453 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
454 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4,
455 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
456 "$Rn.addr = $wb", []> {
457 let Inst{5-4} = Rn{5-4};
460 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
461 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
462 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
464 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
465 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
466 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
468 // ...with double-spaced registers (non-updating versions for disassembly only):
469 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
470 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
471 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
472 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
473 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
474 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
476 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
477 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
478 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
480 // ...alternate versions to be allocated odd register numbers:
481 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
482 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
483 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
485 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
487 // Classes for VLD*LN pseudo-instructions with multi-register operands.
488 // These are expanded to real instructions after register allocation.
489 class VLDQLNPseudo<InstrItinClass itin>
490 : PseudoNLdSt<(outs QPR:$dst),
491 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
492 itin, "$src = $dst">;
493 class VLDQLNWBPseudo<InstrItinClass itin>
494 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
495 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
496 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
497 class VLDQQLNPseudo<InstrItinClass itin>
498 : PseudoNLdSt<(outs QQPR:$dst),
499 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
500 itin, "$src = $dst">;
501 class VLDQQLNWBPseudo<InstrItinClass itin>
502 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
503 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
504 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
505 class VLDQQQQLNPseudo<InstrItinClass itin>
506 : PseudoNLdSt<(outs QQQQPR:$dst),
507 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
508 itin, "$src = $dst">;
509 class VLDQQQQLNWBPseudo<InstrItinClass itin>
510 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
511 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
512 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
514 // VLD1LN : Vector Load (single element to one lane)
515 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
517 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
518 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
519 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
521 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
522 (i32 (LoadOp addrmode6:$Rn)),
526 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
527 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
528 (i32 (LoadOp addrmode6:$addr)),
532 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
533 let Inst{7-5} = lane{2-0};
535 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
536 let Inst{7-6} = lane{1-0};
539 def VLD1LNd32 : VLD1LN<0b1000, {?,0,?,?}, "32", v2i32, load> {
540 let Inst{7} = lane{0};
545 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
546 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
547 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
549 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
551 // ...with address register writeback:
552 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
553 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
554 (ins addrmode6:$Rn, am6offset:$Rm,
555 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
556 "\\{$Vd[$lane]\\}, $Rn$Rm",
557 "$src = $Vd, $Rn.addr = $wb", []>;
559 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
560 let Inst{7-5} = lane{2-0};
562 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
563 let Inst{7-6} = lane{1-0};
566 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
567 let Inst{7} = lane{0};
572 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
573 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
574 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
576 // VLD2LN : Vector Load (single 2-element structure to one lane)
577 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
578 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
579 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
580 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
581 "$src1 = $Vd, $src2 = $dst2", []> {
586 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
587 let Inst{7-5} = lane{2-0};
589 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
590 let Inst{7-6} = lane{1-0};
592 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
593 let Inst{7} = lane{0};
596 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
597 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
598 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
600 // ...with double-spaced registers:
601 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
602 let Inst{7-6} = lane{1-0};
604 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
605 let Inst{7} = lane{0};
608 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
609 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
611 // ...with address register writeback:
612 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
613 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
614 (ins addrmode6:$Rn, am6offset:$Rm,
615 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
616 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
617 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
621 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
622 let Inst{7-5} = lane{2-0};
624 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
625 let Inst{7-6} = lane{1-0};
627 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
628 let Inst{7} = lane{0};
631 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
632 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
633 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
635 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
636 let Inst{7-6} = lane{1-0};
638 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
639 let Inst{7} = lane{0};
642 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
643 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
645 // VLD3LN : Vector Load (single 3-element structure to one lane)
646 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
647 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
648 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
649 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
650 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
651 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
655 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
656 let Inst{7-5} = lane{2-0};
658 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
659 let Inst{7-6} = lane{1-0};
661 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
662 let Inst{7} = lane{0};
665 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
666 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
667 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
669 // ...with double-spaced registers:
670 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
671 let Inst{7-6} = lane{1-0};
673 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
674 let Inst{7} = lane{0};
677 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
678 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
680 // ...with address register writeback:
681 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
682 : NLdStLn<1, 0b10, op11_8, op7_4,
683 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
684 (ins addrmode6:$Rn, am6offset:$Rm,
685 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
686 IIC_VLD3lnu, "vld3", Dt,
687 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
688 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
691 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
692 let Inst{7-5} = lane{2-0};
694 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
695 let Inst{7-6} = lane{1-0};
697 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
698 let Inst{7} = lane{0};
701 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
702 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
703 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
705 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
706 let Inst{7-6} = lane{1-0};
708 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
709 let Inst{7} = lane{0};
712 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
713 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
715 // VLD4LN : Vector Load (single 4-element structure to one lane)
716 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
717 : NLdStLn<1, 0b10, op11_8, op7_4,
718 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
719 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
720 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
721 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
722 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
727 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
728 let Inst{7-5} = lane{2-0};
730 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
731 let Inst{7-6} = lane{1-0};
733 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
734 let Inst{7} = lane{0};
738 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
739 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
740 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
742 // ...with double-spaced registers:
743 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
744 let Inst{7-6} = lane{1-0};
746 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
747 let Inst{7} = lane{0};
751 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
752 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
754 // ...with address register writeback:
755 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
756 : NLdStLn<1, 0b10, op11_8, op7_4,
757 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
758 (ins addrmode6:$Rn, am6offset:$Rm,
759 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
760 IIC_VLD4ln, "vld4", Dt,
761 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
762 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
767 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
768 let Inst{7-5} = lane{2-0};
770 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
771 let Inst{7-6} = lane{1-0};
773 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
774 let Inst{7} = lane{0};
778 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
779 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
780 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
782 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
783 let Inst{7-6} = lane{1-0};
785 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
786 let Inst{7} = lane{0};
790 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
791 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
793 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
795 // VLD1DUP : Vector Load (single element to all lanes)
796 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
797 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd), (ins addrmode6dup:$Rn),
798 IIC_VLD1dup, "vld1", Dt, "\\{$Vd[]\\}, $Rn", "",
799 [(set DPR:$Vd, (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
803 class VLD1QDUPPseudo<ValueType Ty, PatFrag LoadOp> : VLDQPseudo<IIC_VLD1dup> {
804 let Pattern = [(set QPR:$dst,
805 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$addr)))))];
808 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
809 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;
810 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;
812 def VLD1DUPq8Pseudo : VLD1QDUPPseudo<v16i8, extloadi8>;
813 def VLD1DUPq16Pseudo : VLD1QDUPPseudo<v8i16, extloadi16>;
814 def VLD1DUPq32Pseudo : VLD1QDUPPseudo<v4i32, load>;
816 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
818 class VLD1QDUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
819 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2),
820 (ins addrmode6dup:$Rn), IIC_VLD1dup,
821 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
826 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8", v16i8, extloadi8>;
827 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16", v8i16, extloadi16>;
828 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32", v4i32, load>;
830 // ...with address register writeback:
831 class VLD1DUPWB<bits<4> op7_4, string Dt>
832 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, GPR:$wb),
833 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
834 "vld1", Dt, "\\{$Vd[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
837 class VLD1QDUPWB<bits<4> op7_4, string Dt>
838 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
839 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
840 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
844 def VLD1DUPd8_UPD : VLD1DUPWB<{0,0,0,0}, "8">;
845 def VLD1DUPd16_UPD : VLD1DUPWB<{0,1,0,?}, "16">;
846 def VLD1DUPd32_UPD : VLD1DUPWB<{1,0,0,?}, "32">;
848 def VLD1DUPq8_UPD : VLD1QDUPWB<{0,0,1,0}, "8">;
849 def VLD1DUPq16_UPD : VLD1QDUPWB<{0,1,1,?}, "16">;
850 def VLD1DUPq32_UPD : VLD1QDUPWB<{1,0,1,?}, "32">;
852 def VLD1DUPq8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
853 def VLD1DUPq16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
854 def VLD1DUPq32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
856 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
857 class VLD2DUP<bits<4> op7_4, string Dt>
858 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2),
859 (ins addrmode6dup:$Rn), IIC_VLD2dup,
860 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
865 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8">;
866 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16">;
867 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32">;
869 def VLD2DUPd8Pseudo : VLDQPseudo<IIC_VLD2dup>;
870 def VLD2DUPd16Pseudo : VLDQPseudo<IIC_VLD2dup>;
871 def VLD2DUPd32Pseudo : VLDQPseudo<IIC_VLD2dup>;
873 // ...with double-spaced registers (not used for codegen):
874 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8">;
875 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16">;
876 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32">;
878 // ...with address register writeback:
879 class VLD2DUPWB<bits<4> op7_4, string Dt>
880 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
881 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD2dupu,
882 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
886 def VLD2DUPd8_UPD : VLD2DUPWB<{0,0,0,0}, "8">;
887 def VLD2DUPd16_UPD : VLD2DUPWB<{0,1,0,?}, "16">;
888 def VLD2DUPd32_UPD : VLD2DUPWB<{1,0,0,?}, "32">;
890 def VLD2DUPd8x2_UPD : VLD2DUPWB<{0,0,1,0}, "8">;
891 def VLD2DUPd16x2_UPD : VLD2DUPWB<{0,1,1,?}, "16">;
892 def VLD2DUPd32x2_UPD : VLD2DUPWB<{1,0,1,?}, "32">;
894 def VLD2DUPd8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
895 def VLD2DUPd16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
896 def VLD2DUPd32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
898 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
899 class VLD3DUP<bits<4> op7_4, string Dt>
900 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
901 (ins addrmode6dup:$Rn), IIC_VLD3dup,
902 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
907 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
908 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
909 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
911 def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>;
912 def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
913 def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
915 // ...with double-spaced registers (not used for codegen):
916 def VLD3DUPd8x2 : VLD3DUP<{0,0,1,?}, "8">;
917 def VLD3DUPd16x2 : VLD3DUP<{0,1,1,?}, "16">;
918 def VLD3DUPd32x2 : VLD3DUP<{1,0,1,?}, "32">;
920 // ...with address register writeback:
921 class VLD3DUPWB<bits<4> op7_4, string Dt>
922 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
923 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu,
924 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
925 "$Rn.addr = $wb", []> {
929 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;
930 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">;
931 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">;
933 def VLD3DUPd8x2_UPD : VLD3DUPWB<{0,0,1,0}, "8">;
934 def VLD3DUPd16x2_UPD : VLD3DUPWB<{0,1,1,?}, "16">;
935 def VLD3DUPd32x2_UPD : VLD3DUPWB<{1,0,1,?}, "32">;
937 def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
938 def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
939 def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
941 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
942 class VLD4DUP<bits<4> op7_4, string Dt>
943 : NLdSt<1, 0b10, 0b1111, op7_4,
944 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
945 (ins addrmode6dup:$Rn), IIC_VLD4dup,
946 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
951 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
952 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
953 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
955 def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>;
956 def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>;
957 def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>;
959 // ...with double-spaced registers (not used for codegen):
960 def VLD4DUPd8x2 : VLD4DUP<{0,0,1,?}, "8">;
961 def VLD4DUPd16x2 : VLD4DUP<{0,1,1,?}, "16">;
962 def VLD4DUPd32x2 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
964 // ...with address register writeback:
965 class VLD4DUPWB<bits<4> op7_4, string Dt>
966 : NLdSt<1, 0b10, 0b1111, op7_4,
967 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
968 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
969 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
970 "$Rn.addr = $wb", []> {
974 def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">;
975 def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">;
976 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
978 def VLD4DUPd8x2_UPD : VLD4DUPWB<{0,0,1,0}, "8">;
979 def VLD4DUPd16x2_UPD : VLD4DUPWB<{0,1,1,?}, "16">;
980 def VLD4DUPd32x2_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
982 def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
983 def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
984 def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
986 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
988 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
990 // Classes for VST* pseudo-instructions with multi-register operands.
991 // These are expanded to real instructions after register allocation.
992 class VSTQPseudo<InstrItinClass itin>
993 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
994 class VSTQWBPseudo<InstrItinClass itin>
995 : PseudoNLdSt<(outs GPR:$wb),
996 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
998 class VSTQQPseudo<InstrItinClass itin>
999 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
1000 class VSTQQWBPseudo<InstrItinClass itin>
1001 : PseudoNLdSt<(outs GPR:$wb),
1002 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
1003 "$addr.addr = $wb">;
1004 class VSTQQQQWBPseudo<InstrItinClass itin>
1005 : PseudoNLdSt<(outs GPR:$wb),
1006 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
1007 "$addr.addr = $wb">;
1009 // VST1 : Vector Store (multiple single elements)
1010 class VST1D<bits<4> op7_4, string Dt>
1011 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, DPR:$Vd),
1012 IIC_VST1, "vst1", Dt, "\\{$Vd\\}, $Rn", "", []> {
1014 let Inst{4} = Rn{4};
1016 class VST1Q<bits<4> op7_4, string Dt>
1017 : NLdSt<0,0b00,0b1010,op7_4, (outs),
1018 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2), IIC_VST1x2,
1019 "vst1", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1021 let Inst{5-4} = Rn{5-4};
1024 def VST1d8 : VST1D<{0,0,0,?}, "8">;
1025 def VST1d16 : VST1D<{0,1,0,?}, "16">;
1026 def VST1d32 : VST1D<{1,0,0,?}, "32">;
1027 def VST1d64 : VST1D<{1,1,0,?}, "64">;
1029 def VST1q8 : VST1Q<{0,0,?,?}, "8">;
1030 def VST1q16 : VST1Q<{0,1,?,?}, "16">;
1031 def VST1q32 : VST1Q<{1,0,?,?}, "32">;
1032 def VST1q64 : VST1Q<{1,1,?,?}, "64">;
1034 def VST1q8Pseudo : VSTQPseudo<IIC_VST1x2>;
1035 def VST1q16Pseudo : VSTQPseudo<IIC_VST1x2>;
1036 def VST1q32Pseudo : VSTQPseudo<IIC_VST1x2>;
1037 def VST1q64Pseudo : VSTQPseudo<IIC_VST1x2>;
1039 // ...with address register writeback:
1040 class VST1DWB<bits<4> op7_4, string Dt>
1041 : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
1042 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd), IIC_VST1u,
1043 "vst1", Dt, "\\{$Vd\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
1044 let Inst{4} = Rn{4};
1046 class VST1QWB<bits<4> op7_4, string Dt>
1047 : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),
1048 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
1049 IIC_VST1x2u, "vst1", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
1050 "$Rn.addr = $wb", []> {
1051 let Inst{5-4} = Rn{5-4};
1054 def VST1d8_UPD : VST1DWB<{0,0,0,?}, "8">;
1055 def VST1d16_UPD : VST1DWB<{0,1,0,?}, "16">;
1056 def VST1d32_UPD : VST1DWB<{1,0,0,?}, "32">;
1057 def VST1d64_UPD : VST1DWB<{1,1,0,?}, "64">;
1059 def VST1q8_UPD : VST1QWB<{0,0,?,?}, "8">;
1060 def VST1q16_UPD : VST1QWB<{0,1,?,?}, "16">;
1061 def VST1q32_UPD : VST1QWB<{1,0,?,?}, "32">;
1062 def VST1q64_UPD : VST1QWB<{1,1,?,?}, "64">;
1064 def VST1q8Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1065 def VST1q16Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1066 def VST1q32Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1067 def VST1q64Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1069 // ...with 3 registers (some of these are only for the disassembler):
1070 class VST1D3<bits<4> op7_4, string Dt>
1071 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1072 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3),
1073 IIC_VST1x3, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1075 let Inst{4} = Rn{4};
1077 class VST1D3WB<bits<4> op7_4, string Dt>
1078 : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
1079 (ins addrmode6:$Rn, am6offset:$Rm,
1080 DPR:$Vd, DPR:$src2, DPR:$src3),
1081 IIC_VST1x3u, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1082 "$Rn.addr = $wb", []> {
1083 let Inst{4} = Rn{4};
1086 def VST1d8T : VST1D3<{0,0,0,?}, "8">;
1087 def VST1d16T : VST1D3<{0,1,0,?}, "16">;
1088 def VST1d32T : VST1D3<{1,0,0,?}, "32">;
1089 def VST1d64T : VST1D3<{1,1,0,?}, "64">;
1091 def VST1d8T_UPD : VST1D3WB<{0,0,0,?}, "8">;
1092 def VST1d16T_UPD : VST1D3WB<{0,1,0,?}, "16">;
1093 def VST1d32T_UPD : VST1D3WB<{1,0,0,?}, "32">;
1094 def VST1d64T_UPD : VST1D3WB<{1,1,0,?}, "64">;
1096 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
1097 def VST1d64TPseudo_UPD : VSTQQWBPseudo<IIC_VST1x3u>;
1099 // ...with 4 registers (some of these are only for the disassembler):
1100 class VST1D4<bits<4> op7_4, string Dt>
1101 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1102 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1103 IIC_VST1x4, "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", "",
1106 let Inst{5-4} = Rn{5-4};
1108 class VST1D4WB<bits<4> op7_4, string Dt>
1109 : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
1110 (ins addrmode6:$Rn, am6offset:$Rm,
1111 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST1x4u,
1112 "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1113 "$Rn.addr = $wb", []> {
1114 let Inst{5-4} = Rn{5-4};
1117 def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
1118 def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
1119 def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
1120 def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
1122 def VST1d8Q_UPD : VST1D4WB<{0,0,?,?}, "8">;
1123 def VST1d16Q_UPD : VST1D4WB<{0,1,?,?}, "16">;
1124 def VST1d32Q_UPD : VST1D4WB<{1,0,?,?}, "32">;
1125 def VST1d64Q_UPD : VST1D4WB<{1,1,?,?}, "64">;
1127 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
1128 def VST1d64QPseudo_UPD : VSTQQWBPseudo<IIC_VST1x4u>;
1130 // VST2 : Vector Store (multiple 2-element structures)
1131 class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
1132 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1133 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2),
1134 IIC_VST2, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1136 let Inst{5-4} = Rn{5-4};
1138 class VST2Q<bits<4> op7_4, string Dt>
1139 : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
1140 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1141 IIC_VST2x2, "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1144 let Inst{5-4} = Rn{5-4};
1147 def VST2d8 : VST2D<0b1000, {0,0,?,?}, "8">;
1148 def VST2d16 : VST2D<0b1000, {0,1,?,?}, "16">;
1149 def VST2d32 : VST2D<0b1000, {1,0,?,?}, "32">;
1151 def VST2q8 : VST2Q<{0,0,?,?}, "8">;
1152 def VST2q16 : VST2Q<{0,1,?,?}, "16">;
1153 def VST2q32 : VST2Q<{1,0,?,?}, "32">;
1155 def VST2d8Pseudo : VSTQPseudo<IIC_VST2>;
1156 def VST2d16Pseudo : VSTQPseudo<IIC_VST2>;
1157 def VST2d32Pseudo : VSTQPseudo<IIC_VST2>;
1159 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
1160 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
1161 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
1163 // ...with address register writeback:
1164 class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1165 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1166 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
1167 IIC_VST2u, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
1168 "$Rn.addr = $wb", []> {
1169 let Inst{5-4} = Rn{5-4};
1171 class VST2QWB<bits<4> op7_4, string Dt>
1172 : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1173 (ins addrmode6:$Rn, am6offset:$Rm,
1174 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST2x2u,
1175 "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1176 "$Rn.addr = $wb", []> {
1177 let Inst{5-4} = Rn{5-4};
1180 def VST2d8_UPD : VST2DWB<0b1000, {0,0,?,?}, "8">;
1181 def VST2d16_UPD : VST2DWB<0b1000, {0,1,?,?}, "16">;
1182 def VST2d32_UPD : VST2DWB<0b1000, {1,0,?,?}, "32">;
1184 def VST2q8_UPD : VST2QWB<{0,0,?,?}, "8">;
1185 def VST2q16_UPD : VST2QWB<{0,1,?,?}, "16">;
1186 def VST2q32_UPD : VST2QWB<{1,0,?,?}, "32">;
1188 def VST2d8Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1189 def VST2d16Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1190 def VST2d32Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1192 def VST2q8Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1193 def VST2q16Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1194 def VST2q32Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1196 // ...with double-spaced registers (for disassembly only):
1197 def VST2b8 : VST2D<0b1001, {0,0,?,?}, "8">;
1198 def VST2b16 : VST2D<0b1001, {0,1,?,?}, "16">;
1199 def VST2b32 : VST2D<0b1001, {1,0,?,?}, "32">;
1200 def VST2b8_UPD : VST2DWB<0b1001, {0,0,?,?}, "8">;
1201 def VST2b16_UPD : VST2DWB<0b1001, {0,1,?,?}, "16">;
1202 def VST2b32_UPD : VST2DWB<0b1001, {1,0,?,?}, "32">;
1204 // VST3 : Vector Store (multiple 3-element structures)
1205 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1206 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1207 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1208 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1210 let Inst{4} = Rn{4};
1213 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1214 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1215 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
1217 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1218 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1219 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
1221 // ...with address register writeback:
1222 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1223 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1224 (ins addrmode6:$Rn, am6offset:$Rm,
1225 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1226 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1227 "$Rn.addr = $wb", []> {
1228 let Inst{4} = Rn{4};
1231 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1232 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1233 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
1235 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1236 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1237 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1239 // ...with double-spaced registers (non-updating versions for disassembly only):
1240 def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1241 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1242 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1243 def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1244 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1245 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
1247 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1248 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1249 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1251 // ...alternate versions to be allocated odd register numbers:
1252 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1253 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1254 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1256 // VST4 : Vector Store (multiple 4-element structures)
1257 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1258 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1259 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1260 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1263 let Inst{5-4} = Rn{5-4};
1266 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1267 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1268 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
1270 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1271 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1272 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
1274 // ...with address register writeback:
1275 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1276 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1277 (ins addrmode6:$Rn, am6offset:$Rm,
1278 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1279 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1280 "$Rn.addr = $wb", []> {
1281 let Inst{5-4} = Rn{5-4};
1284 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
1285 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
1286 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
1288 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1289 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1290 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1292 // ...with double-spaced registers (non-updating versions for disassembly only):
1293 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
1294 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
1295 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
1296 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
1297 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
1298 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
1300 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1301 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1302 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1304 // ...alternate versions to be allocated odd register numbers:
1305 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1306 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1307 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1309 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1311 // Classes for VST*LN pseudo-instructions with multi-register operands.
1312 // These are expanded to real instructions after register allocation.
1313 class VSTQLNPseudo<InstrItinClass itin>
1314 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1316 class VSTQLNWBPseudo<InstrItinClass itin>
1317 : PseudoNLdSt<(outs GPR:$wb),
1318 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1319 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1320 class VSTQQLNPseudo<InstrItinClass itin>
1321 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1323 class VSTQQLNWBPseudo<InstrItinClass itin>
1324 : PseudoNLdSt<(outs GPR:$wb),
1325 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1326 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1327 class VSTQQQQLNPseudo<InstrItinClass itin>
1328 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1330 class VSTQQQQLNWBPseudo<InstrItinClass itin>
1331 : PseudoNLdSt<(outs GPR:$wb),
1332 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1333 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1335 // VST1LN : Vector Store (single element from one lane)
1336 class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1337 PatFrag StoreOp, SDNode ExtractOp>
1338 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1339 (ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane),
1340 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1341 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6:$Rn)]> {
1344 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1345 : VSTQLNPseudo<IIC_VST1ln> {
1346 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1350 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
1352 let Inst{7-5} = lane{2-0};
1354 def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
1356 let Inst{7-6} = lane{1-0};
1357 let Inst{4} = Rn{5};
1359 def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt> {
1360 let Inst{7} = lane{0};
1361 let Inst{5-4} = Rn{5-4};
1364 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
1365 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
1366 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
1368 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1370 // ...with address register writeback:
1371 class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1372 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1373 (ins addrmode6:$Rn, am6offset:$Rm,
1374 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
1375 "\\{$Vd[$lane]\\}, $Rn$Rm",
1376 "$Rn.addr = $wb", []>;
1378 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8"> {
1379 let Inst{7-5} = lane{2-0};
1381 def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16"> {
1382 let Inst{7-6} = lane{1-0};
1383 let Inst{4} = Rn{5};
1385 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32"> {
1386 let Inst{7} = lane{0};
1387 let Inst{5-4} = Rn{5-4};
1390 def VST1LNq8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST1lnu>;
1391 def VST1LNq16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST1lnu>;
1392 def VST1LNq32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST1lnu>;
1394 // VST2LN : Vector Store (single 2-element structure from one lane)
1395 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1396 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1397 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
1398 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
1401 let Inst{4} = Rn{4};
1404 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
1405 let Inst{7-5} = lane{2-0};
1407 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
1408 let Inst{7-6} = lane{1-0};
1410 def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
1411 let Inst{7} = lane{0};
1414 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1415 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1416 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1418 // ...with double-spaced registers:
1419 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
1420 let Inst{7-6} = lane{1-0};
1421 let Inst{4} = Rn{4};
1423 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
1424 let Inst{7} = lane{0};
1425 let Inst{4} = Rn{4};
1428 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1429 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1431 // ...with address register writeback:
1432 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1433 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1434 (ins addrmode6:$addr, am6offset:$offset,
1435 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
1436 "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset",
1437 "$addr.addr = $wb", []> {
1438 let Inst{4} = Rn{4};
1441 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
1442 let Inst{7-5} = lane{2-0};
1444 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
1445 let Inst{7-6} = lane{1-0};
1447 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
1448 let Inst{7} = lane{0};
1451 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1452 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1453 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1455 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
1456 let Inst{7-6} = lane{1-0};
1458 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
1459 let Inst{7} = lane{0};
1462 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1463 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1465 // VST3LN : Vector Store (single 3-element structure from one lane)
1466 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1467 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1468 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
1469 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
1470 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
1474 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
1475 let Inst{7-5} = lane{2-0};
1477 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
1478 let Inst{7-6} = lane{1-0};
1480 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
1481 let Inst{7} = lane{0};
1484 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1485 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1486 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1488 // ...with double-spaced registers:
1489 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
1490 let Inst{7-6} = lane{1-0};
1492 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
1493 let Inst{7} = lane{0};
1496 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1497 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1499 // ...with address register writeback:
1500 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1501 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1502 (ins addrmode6:$Rn, am6offset:$Rm,
1503 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1504 IIC_VST3lnu, "vst3", Dt,
1505 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
1506 "$Rn.addr = $wb", []>;
1508 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
1509 let Inst{7-5} = lane{2-0};
1511 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
1512 let Inst{7-6} = lane{1-0};
1514 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
1515 let Inst{7} = lane{0};
1518 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1519 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1520 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1522 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
1523 let Inst{7-6} = lane{1-0};
1525 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
1526 let Inst{7} = lane{0};
1529 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1530 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1532 // VST4LN : Vector Store (single 4-element structure from one lane)
1533 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1534 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1535 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
1536 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
1537 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
1540 let Inst{4} = Rn{4};
1543 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
1544 let Inst{7-5} = lane{2-0};
1546 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
1547 let Inst{7-6} = lane{1-0};
1549 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
1550 let Inst{7} = lane{0};
1551 let Inst{5} = Rn{5};
1554 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1555 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1556 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1558 // ...with double-spaced registers:
1559 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
1560 let Inst{7-6} = lane{1-0};
1562 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
1563 let Inst{7} = lane{0};
1564 let Inst{5} = Rn{5};
1567 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1568 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1570 // ...with address register writeback:
1571 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1572 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1573 (ins addrmode6:$Rn, am6offset:$Rm,
1574 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1575 IIC_VST4lnu, "vst4", Dt,
1576 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
1577 "$Rn.addr = $wb", []> {
1578 let Inst{4} = Rn{4};
1581 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
1582 let Inst{7-5} = lane{2-0};
1584 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
1585 let Inst{7-6} = lane{1-0};
1587 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
1588 let Inst{7} = lane{0};
1589 let Inst{5} = Rn{5};
1592 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1593 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1594 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1596 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
1597 let Inst{7-6} = lane{1-0};
1599 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
1600 let Inst{7} = lane{0};
1601 let Inst{5} = Rn{5};
1604 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1605 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1607 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1610 //===----------------------------------------------------------------------===//
1611 // NEON pattern fragments
1612 //===----------------------------------------------------------------------===//
1614 // Extract D sub-registers of Q registers.
1615 def DSubReg_i8_reg : SDNodeXForm<imm, [{
1616 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1617 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
1619 def DSubReg_i16_reg : SDNodeXForm<imm, [{
1620 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1621 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
1623 def DSubReg_i32_reg : SDNodeXForm<imm, [{
1624 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1625 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
1627 def DSubReg_f64_reg : SDNodeXForm<imm, [{
1628 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1629 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
1632 // Extract S sub-registers of Q/D registers.
1633 def SSubReg_f32_reg : SDNodeXForm<imm, [{
1634 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
1635 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
1638 // Translate lane numbers from Q registers to D subregs.
1639 def SubReg_i8_lane : SDNodeXForm<imm, [{
1640 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
1642 def SubReg_i16_lane : SDNodeXForm<imm, [{
1643 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
1645 def SubReg_i32_lane : SDNodeXForm<imm, [{
1646 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
1649 //===----------------------------------------------------------------------===//
1650 // Instruction Classes
1651 //===----------------------------------------------------------------------===//
1653 // Basic 2-register operations: single-, double- and quad-register.
1654 class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1655 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1656 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1657 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
1658 (outs DPR_VFP2:$Vd), (ins DPR_VFP2:$Vm),
1659 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm", "", []>;
1660 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1661 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1662 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1663 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
1664 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
1665 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
1666 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1667 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1668 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1669 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
1670 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
1671 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
1673 // Basic 2-register intrinsics, both double- and quad-register.
1674 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1675 bits<2> op17_16, bits<5> op11_7, bit op4,
1676 InstrItinClass itin, string OpcodeStr, string Dt,
1677 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1678 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
1679 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1680 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
1681 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1682 bits<2> op17_16, bits<5> op11_7, bit op4,
1683 InstrItinClass itin, string OpcodeStr, string Dt,
1684 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1685 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
1686 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1687 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
1689 // Narrow 2-register operations.
1690 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1691 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1692 InstrItinClass itin, string OpcodeStr, string Dt,
1693 ValueType TyD, ValueType TyQ, SDNode OpNode>
1694 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
1695 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1696 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
1698 // Narrow 2-register intrinsics.
1699 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1700 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1701 InstrItinClass itin, string OpcodeStr, string Dt,
1702 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
1703 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
1704 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1705 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
1707 // Long 2-register operations (currently only used for VMOVL).
1708 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1709 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1710 InstrItinClass itin, string OpcodeStr, string Dt,
1711 ValueType TyQ, ValueType TyD, SDNode OpNode>
1712 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
1713 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1714 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
1716 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
1717 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
1718 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
1719 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
1720 OpcodeStr, Dt, "$Vd, $Vm",
1721 "$src1 = $Vd, $src2 = $Vm", []>;
1722 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
1723 InstrItinClass itin, string OpcodeStr, string Dt>
1724 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
1725 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
1726 "$src1 = $Vd, $src2 = $Vm", []>;
1728 // Basic 3-register operations: single-, double- and quad-register.
1729 class N3VS<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1730 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1731 SDNode OpNode, bit Commutable>
1732 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1733 (outs DPR_VFP2:$Vd), (ins DPR_VFP2:$Vn, DPR_VFP2:$Vm), N3RegFrm,
1734 IIC_VBIND, OpcodeStr, Dt, "$Vd, $Vn, $Vm", "", []> {
1735 let isCommutable = Commutable;
1738 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1739 InstrItinClass itin, string OpcodeStr, string Dt,
1740 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1741 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1742 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1743 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1744 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
1745 let isCommutable = Commutable;
1747 // Same as N3VD but no data type.
1748 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1749 InstrItinClass itin, string OpcodeStr,
1750 ValueType ResTy, ValueType OpTy,
1751 SDNode OpNode, bit Commutable>
1752 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
1753 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1754 OpcodeStr, "$Vd, $Vn, $Vm", "",
1755 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
1756 let isCommutable = Commutable;
1759 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
1760 InstrItinClass itin, string OpcodeStr, string Dt,
1761 ValueType Ty, SDNode ShOp>
1762 : N3V<0, 1, op21_20, op11_8, 1, 0,
1763 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1764 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1766 (Ty (ShOp (Ty DPR:$Vn),
1767 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
1768 let isCommutable = 0;
1770 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
1771 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1772 : N3V<0, 1, op21_20, op11_8, 1, 0,
1773 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1774 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm[$lane]","",
1776 (Ty (ShOp (Ty DPR:$Vn),
1777 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
1778 let isCommutable = 0;
1781 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1782 InstrItinClass itin, string OpcodeStr, string Dt,
1783 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1784 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1785 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1786 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1787 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
1788 let isCommutable = Commutable;
1790 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1791 InstrItinClass itin, string OpcodeStr,
1792 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1793 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
1794 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1795 OpcodeStr, "$Vd, $Vn, $Vm", "",
1796 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
1797 let isCommutable = Commutable;
1799 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
1800 InstrItinClass itin, string OpcodeStr, string Dt,
1801 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1802 : N3V<1, 1, op21_20, op11_8, 1, 0,
1803 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1804 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1805 [(set (ResTy QPR:$Vd),
1806 (ResTy (ShOp (ResTy QPR:$Vn),
1807 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
1809 let isCommutable = 0;
1811 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
1812 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1813 : N3V<1, 1, op21_20, op11_8, 1, 0,
1814 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1815 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm[$lane]","",
1816 [(set (ResTy QPR:$Vd),
1817 (ResTy (ShOp (ResTy QPR:$Vn),
1818 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
1820 let isCommutable = 0;
1823 // Basic 3-register intrinsics, both double- and quad-register.
1824 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1825 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1826 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1827 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1828 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
1829 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1830 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
1831 let isCommutable = Commutable;
1833 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1834 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1835 : N3V<0, 1, op21_20, op11_8, 1, 0,
1836 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1837 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1839 (Ty (IntOp (Ty DPR:$Vn),
1840 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
1842 let isCommutable = 0;
1844 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1845 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1846 : N3V<0, 1, op21_20, op11_8, 1, 0,
1847 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1848 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1850 (Ty (IntOp (Ty DPR:$Vn),
1851 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
1852 let isCommutable = 0;
1854 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1855 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1856 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1857 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1858 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
1859 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
1860 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
1861 let isCommutable = 0;
1864 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1865 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1866 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1867 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1868 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
1869 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1870 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
1871 let isCommutable = Commutable;
1873 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1874 string OpcodeStr, string Dt,
1875 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1876 : N3V<1, 1, op21_20, op11_8, 1, 0,
1877 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1878 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1879 [(set (ResTy QPR:$Vd),
1880 (ResTy (IntOp (ResTy QPR:$Vn),
1881 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
1883 let isCommutable = 0;
1885 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1886 string OpcodeStr, string Dt,
1887 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1888 : N3V<1, 1, op21_20, op11_8, 1, 0,
1889 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1890 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1891 [(set (ResTy QPR:$Vd),
1892 (ResTy (IntOp (ResTy QPR:$Vn),
1893 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
1895 let isCommutable = 0;
1897 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1898 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1899 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1900 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1901 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
1902 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
1903 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
1904 let isCommutable = 0;
1907 // Multiply-Add/Sub operations: single-, double- and quad-register.
1908 class N3VSMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1909 InstrItinClass itin, string OpcodeStr, string Dt,
1910 ValueType Ty, SDNode MulOp, SDNode OpNode>
1911 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1912 (outs DPR_VFP2:$Vd),
1913 (ins DPR_VFP2:$src1, DPR_VFP2:$Vn, DPR_VFP2:$Vm), N3RegFrm, itin,
1914 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd", []>;
1916 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1917 InstrItinClass itin, string OpcodeStr, string Dt,
1918 ValueType Ty, SDNode MulOp, SDNode OpNode>
1919 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1920 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1921 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1922 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
1923 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
1925 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1926 string OpcodeStr, string Dt,
1927 ValueType Ty, SDNode MulOp, SDNode ShOp>
1928 : N3V<0, 1, op21_20, op11_8, 1, 0,
1930 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1932 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
1934 (Ty (ShOp (Ty DPR:$src1),
1936 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
1938 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1939 string OpcodeStr, string Dt,
1940 ValueType Ty, SDNode MulOp, SDNode ShOp>
1941 : N3V<0, 1, op21_20, op11_8, 1, 0,
1943 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1945 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
1947 (Ty (ShOp (Ty DPR:$src1),
1949 (Ty (NEONvduplane (Ty DPR_8:$Vm),
1952 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1953 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
1954 SDNode MulOp, SDNode OpNode>
1955 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1956 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1957 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1958 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
1959 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
1960 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1961 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1962 SDNode MulOp, SDNode ShOp>
1963 : N3V<1, 1, op21_20, op11_8, 1, 0,
1965 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1967 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
1968 [(set (ResTy QPR:$Vd),
1969 (ResTy (ShOp (ResTy QPR:$src1),
1970 (ResTy (MulOp QPR:$Vn,
1971 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
1973 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1974 string OpcodeStr, string Dt,
1975 ValueType ResTy, ValueType OpTy,
1976 SDNode MulOp, SDNode ShOp>
1977 : N3V<1, 1, op21_20, op11_8, 1, 0,
1979 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1981 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
1982 [(set (ResTy QPR:$Vd),
1983 (ResTy (ShOp (ResTy QPR:$src1),
1984 (ResTy (MulOp QPR:$Vn,
1985 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
1988 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
1989 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1990 InstrItinClass itin, string OpcodeStr, string Dt,
1991 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
1992 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1993 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1994 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1995 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
1996 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
1997 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1998 InstrItinClass itin, string OpcodeStr, string Dt,
1999 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2000 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2001 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2002 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2003 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2004 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2006 // Neon 3-argument intrinsics, both double- and quad-register.
2007 // The destination register is also used as the first source operand register.
2008 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2009 InstrItinClass itin, string OpcodeStr, string Dt,
2010 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2011 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2012 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2013 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2014 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2015 (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2016 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2017 InstrItinClass itin, string OpcodeStr, string Dt,
2018 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2019 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2020 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2021 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2022 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2023 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2025 // Long Multiply-Add/Sub operations.
2026 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2027 InstrItinClass itin, string OpcodeStr, string Dt,
2028 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2029 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2030 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2031 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2032 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2033 (TyQ (MulOp (TyD DPR:$Vn),
2034 (TyD DPR:$Vm)))))]>;
2035 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2036 InstrItinClass itin, string OpcodeStr, string Dt,
2037 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2038 : N3V<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2039 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2041 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2043 (OpNode (TyQ QPR:$src1),
2044 (TyQ (MulOp (TyD DPR:$Vn),
2045 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),
2047 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2048 InstrItinClass itin, string OpcodeStr, string Dt,
2049 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2050 : N3V<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2051 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2053 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2055 (OpNode (TyQ QPR:$src1),
2056 (TyQ (MulOp (TyD DPR:$Vn),
2057 (TyD (NEONvduplane (TyD DPR_8:$Vm),
2060 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
2061 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2062 InstrItinClass itin, string OpcodeStr, string Dt,
2063 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2065 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2066 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2067 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2068 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2069 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2070 (TyD DPR:$Vm)))))))]>;
2072 // Neon Long 3-argument intrinsic. The destination register is
2073 // a quad-register and is also used as the first source operand register.
2074 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2075 InstrItinClass itin, string OpcodeStr, string Dt,
2076 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
2077 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2078 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2079 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2081 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2082 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2083 string OpcodeStr, string Dt,
2084 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2085 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2087 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2089 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2090 [(set (ResTy QPR:$Vd),
2091 (ResTy (IntOp (ResTy QPR:$src1),
2093 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2095 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2096 InstrItinClass itin, string OpcodeStr, string Dt,
2097 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2098 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2100 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2102 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2103 [(set (ResTy QPR:$Vd),
2104 (ResTy (IntOp (ResTy QPR:$src1),
2106 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2109 // Narrowing 3-register intrinsics.
2110 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2111 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
2112 Intrinsic IntOp, bit Commutable>
2113 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2114 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2115 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2116 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2117 let isCommutable = Commutable;
2120 // Long 3-register operations.
2121 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2122 InstrItinClass itin, string OpcodeStr, string Dt,
2123 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
2124 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2125 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2126 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2127 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2128 let isCommutable = Commutable;
2130 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2131 InstrItinClass itin, string OpcodeStr, string Dt,
2132 ValueType TyQ, ValueType TyD, SDNode OpNode>
2133 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2134 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2135 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2137 (TyQ (OpNode (TyD DPR:$Vn),
2138 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
2139 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2140 InstrItinClass itin, string OpcodeStr, string Dt,
2141 ValueType TyQ, ValueType TyD, SDNode OpNode>
2142 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2143 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2144 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2146 (TyQ (OpNode (TyD DPR:$Vn),
2147 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
2149 // Long 3-register operations with explicitly extended operands.
2150 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2151 InstrItinClass itin, string OpcodeStr, string Dt,
2152 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
2154 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2155 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2156 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2157 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
2158 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2159 let isCommutable = Commutable;
2162 // Long 3-register intrinsics with explicit extend (VABDL).
2163 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2164 InstrItinClass itin, string OpcodeStr, string Dt,
2165 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2167 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2168 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2169 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2170 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2171 (TyD DPR:$Vm))))))]> {
2172 let isCommutable = Commutable;
2175 // Long 3-register intrinsics.
2176 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2177 InstrItinClass itin, string OpcodeStr, string Dt,
2178 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
2179 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2180 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2181 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2182 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2183 let isCommutable = Commutable;
2185 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2186 string OpcodeStr, string Dt,
2187 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2188 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2189 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2190 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2191 [(set (ResTy QPR:$Vd),
2192 (ResTy (IntOp (OpTy DPR:$Vn),
2193 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2195 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2196 InstrItinClass itin, string OpcodeStr, string Dt,
2197 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2198 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2199 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2200 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2201 [(set (ResTy QPR:$Vd),
2202 (ResTy (IntOp (OpTy DPR:$Vn),
2203 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2206 // Wide 3-register operations.
2207 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2208 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
2209 SDNode OpNode, SDNode ExtOp, bit Commutable>
2210 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2211 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
2212 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2213 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
2214 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2215 let isCommutable = Commutable;
2218 // Pairwise long 2-register intrinsics, both double- and quad-register.
2219 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2220 bits<2> op17_16, bits<5> op11_7, bit op4,
2221 string OpcodeStr, string Dt,
2222 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2223 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2224 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2225 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2226 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2227 bits<2> op17_16, bits<5> op11_7, bit op4,
2228 string OpcodeStr, string Dt,
2229 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2230 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2231 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2232 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2234 // Pairwise long 2-register accumulate intrinsics,
2235 // both double- and quad-register.
2236 // The destination register is also used as the first source operand register.
2237 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2238 bits<2> op17_16, bits<5> op11_7, bit op4,
2239 string OpcodeStr, string Dt,
2240 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2241 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
2242 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
2243 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2244 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
2245 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2246 bits<2> op17_16, bits<5> op11_7, bit op4,
2247 string OpcodeStr, string Dt,
2248 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2249 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
2250 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
2251 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2252 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
2254 // Shift by immediate,
2255 // both double- and quad-register.
2256 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2257 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2258 ValueType Ty, SDNode OpNode>
2259 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2260 (outs DPR:$Vd), (ins DPR:$Vm, i32imm:$SIMM), f, itin,
2261 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2262 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
2263 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2264 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2265 ValueType Ty, SDNode OpNode>
2266 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2267 (outs QPR:$Vd), (ins QPR:$Vm, i32imm:$SIMM), f, itin,
2268 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2269 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
2271 // Long shift by immediate.
2272 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2273 string OpcodeStr, string Dt,
2274 ValueType ResTy, ValueType OpTy, SDNode OpNode>
2275 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2276 (outs QPR:$Vd), (ins DPR:$Vm, i32imm:$SIMM), N2RegVShLFrm,
2277 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2278 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm),
2279 (i32 imm:$SIMM))))]>;
2281 // Narrow shift by immediate.
2282 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2283 InstrItinClass itin, string OpcodeStr, string Dt,
2284 ValueType ResTy, ValueType OpTy, SDNode OpNode>
2285 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2286 (outs DPR:$Vd), (ins QPR:$Vm, i32imm:$SIMM), N2RegVShRFrm, itin,
2287 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2288 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
2289 (i32 imm:$SIMM))))]>;
2291 // Shift right by immediate and accumulate,
2292 // both double- and quad-register.
2293 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2294 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2295 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2296 (ins DPR:$src1, DPR:$Vm, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2297 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2298 [(set DPR:$Vd, (Ty (add DPR:$src1,
2299 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
2300 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2301 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2302 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2303 (ins QPR:$src1, QPR:$Vm, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2304 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2305 [(set QPR:$Vd, (Ty (add QPR:$src1,
2306 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
2308 // Shift by immediate and insert,
2309 // both double- and quad-register.
2310 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2311 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
2312 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2313 (ins DPR:$src1, DPR:$Vm, i32imm:$SIMM), f, IIC_VSHLiD,
2314 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2315 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
2316 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2317 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
2318 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2319 (ins QPR:$src1, QPR:$Vm, i32imm:$SIMM), f, IIC_VSHLiQ,
2320 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2321 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
2323 // Convert, with fractional bits immediate,
2324 // both double- and quad-register.
2325 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2326 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2328 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2329 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2330 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2331 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
2332 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2333 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2335 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2336 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2337 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2338 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
2340 //===----------------------------------------------------------------------===//
2342 //===----------------------------------------------------------------------===//
2344 // Abbreviations used in multiclass suffixes:
2345 // Q = quarter int (8 bit) elements
2346 // H = half int (16 bit) elements
2347 // S = single int (32 bit) elements
2348 // D = double int (64 bit) elements
2350 // Neon 2-register vector operations -- for disassembly only.
2352 // First with only element sizes of 8, 16 and 32 bits:
2353 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2354 bits<5> op11_7, bit op4, string opc, string Dt,
2355 string asm, SDNode OpNode> {
2356 // 64-bit vector types.
2357 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
2358 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2359 opc, !strconcat(Dt, "8"), asm, "",
2360 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
2361 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
2362 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2363 opc, !strconcat(Dt, "16"), asm, "",
2364 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>;
2365 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2366 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2367 opc, !strconcat(Dt, "32"), asm, "",
2368 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>;
2369 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2370 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2371 opc, "f32", asm, "",
2372 [(set DPR:$Vd, (v2f32 (OpNode (v2f32 DPR:$Vm))))]> {
2373 let Inst{10} = 1; // overwrite F = 1
2376 // 128-bit vector types.
2377 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
2378 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2379 opc, !strconcat(Dt, "8"), asm, "",
2380 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
2381 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
2382 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2383 opc, !strconcat(Dt, "16"), asm, "",
2384 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
2385 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2386 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2387 opc, !strconcat(Dt, "32"), asm, "",
2388 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
2389 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2390 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2391 opc, "f32", asm, "",
2392 [(set QPR:$Vd, (v4f32 (OpNode (v4f32 QPR:$Vm))))]> {
2393 let Inst{10} = 1; // overwrite F = 1
2397 // Neon 3-register vector operations.
2399 // First with only element sizes of 8, 16 and 32 bits:
2400 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2401 InstrItinClass itinD16, InstrItinClass itinD32,
2402 InstrItinClass itinQ16, InstrItinClass itinQ32,
2403 string OpcodeStr, string Dt,
2404 SDNode OpNode, bit Commutable = 0> {
2405 // 64-bit vector types.
2406 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
2407 OpcodeStr, !strconcat(Dt, "8"),
2408 v8i8, v8i8, OpNode, Commutable>;
2409 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
2410 OpcodeStr, !strconcat(Dt, "16"),
2411 v4i16, v4i16, OpNode, Commutable>;
2412 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
2413 OpcodeStr, !strconcat(Dt, "32"),
2414 v2i32, v2i32, OpNode, Commutable>;
2416 // 128-bit vector types.
2417 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
2418 OpcodeStr, !strconcat(Dt, "8"),
2419 v16i8, v16i8, OpNode, Commutable>;
2420 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
2421 OpcodeStr, !strconcat(Dt, "16"),
2422 v8i16, v8i16, OpNode, Commutable>;
2423 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
2424 OpcodeStr, !strconcat(Dt, "32"),
2425 v4i32, v4i32, OpNode, Commutable>;
2428 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
2429 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2431 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
2433 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2434 v8i16, v4i16, ShOp>;
2435 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
2436 v4i32, v2i32, ShOp>;
2439 // ....then also with element size 64 bits:
2440 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2441 InstrItinClass itinD, InstrItinClass itinQ,
2442 string OpcodeStr, string Dt,
2443 SDNode OpNode, bit Commutable = 0>
2444 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
2445 OpcodeStr, Dt, OpNode, Commutable> {
2446 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
2447 OpcodeStr, !strconcat(Dt, "64"),
2448 v1i64, v1i64, OpNode, Commutable>;
2449 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
2450 OpcodeStr, !strconcat(Dt, "64"),
2451 v2i64, v2i64, OpNode, Commutable>;
2455 // Neon Narrowing 2-register vector operations,
2456 // source operand element sizes of 16, 32 and 64 bits:
2457 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2458 bits<5> op11_7, bit op6, bit op4,
2459 InstrItinClass itin, string OpcodeStr, string Dt,
2461 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2462 itin, OpcodeStr, !strconcat(Dt, "16"),
2463 v8i8, v8i16, OpNode>;
2464 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2465 itin, OpcodeStr, !strconcat(Dt, "32"),
2466 v4i16, v4i32, OpNode>;
2467 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2468 itin, OpcodeStr, !strconcat(Dt, "64"),
2469 v2i32, v2i64, OpNode>;
2472 // Neon Narrowing 2-register vector intrinsics,
2473 // source operand element sizes of 16, 32 and 64 bits:
2474 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2475 bits<5> op11_7, bit op6, bit op4,
2476 InstrItinClass itin, string OpcodeStr, string Dt,
2478 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2479 itin, OpcodeStr, !strconcat(Dt, "16"),
2480 v8i8, v8i16, IntOp>;
2481 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2482 itin, OpcodeStr, !strconcat(Dt, "32"),
2483 v4i16, v4i32, IntOp>;
2484 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2485 itin, OpcodeStr, !strconcat(Dt, "64"),
2486 v2i32, v2i64, IntOp>;
2490 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
2491 // source operand element sizes of 16, 32 and 64 bits:
2492 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
2493 string OpcodeStr, string Dt, SDNode OpNode> {
2494 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2495 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
2496 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2497 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2498 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2499 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2503 // Neon 3-register vector intrinsics.
2505 // First with only element sizes of 16 and 32 bits:
2506 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2507 InstrItinClass itinD16, InstrItinClass itinD32,
2508 InstrItinClass itinQ16, InstrItinClass itinQ32,
2509 string OpcodeStr, string Dt,
2510 Intrinsic IntOp, bit Commutable = 0> {
2511 // 64-bit vector types.
2512 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
2513 OpcodeStr, !strconcat(Dt, "16"),
2514 v4i16, v4i16, IntOp, Commutable>;
2515 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
2516 OpcodeStr, !strconcat(Dt, "32"),
2517 v2i32, v2i32, IntOp, Commutable>;
2519 // 128-bit vector types.
2520 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2521 OpcodeStr, !strconcat(Dt, "16"),
2522 v8i16, v8i16, IntOp, Commutable>;
2523 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2524 OpcodeStr, !strconcat(Dt, "32"),
2525 v4i32, v4i32, IntOp, Commutable>;
2527 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2528 InstrItinClass itinD16, InstrItinClass itinD32,
2529 InstrItinClass itinQ16, InstrItinClass itinQ32,
2530 string OpcodeStr, string Dt,
2532 // 64-bit vector types.
2533 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
2534 OpcodeStr, !strconcat(Dt, "16"),
2535 v4i16, v4i16, IntOp>;
2536 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
2537 OpcodeStr, !strconcat(Dt, "32"),
2538 v2i32, v2i32, IntOp>;
2540 // 128-bit vector types.
2541 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2542 OpcodeStr, !strconcat(Dt, "16"),
2543 v8i16, v8i16, IntOp>;
2544 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2545 OpcodeStr, !strconcat(Dt, "32"),
2546 v4i32, v4i32, IntOp>;
2549 multiclass N3VIntSL_HS<bits<4> op11_8,
2550 InstrItinClass itinD16, InstrItinClass itinD32,
2551 InstrItinClass itinQ16, InstrItinClass itinQ32,
2552 string OpcodeStr, string Dt, Intrinsic IntOp> {
2553 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
2554 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
2555 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
2556 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
2557 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
2558 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
2559 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
2560 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
2563 // ....then also with element size of 8 bits:
2564 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2565 InstrItinClass itinD16, InstrItinClass itinD32,
2566 InstrItinClass itinQ16, InstrItinClass itinQ32,
2567 string OpcodeStr, string Dt,
2568 Intrinsic IntOp, bit Commutable = 0>
2569 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2570 OpcodeStr, Dt, IntOp, Commutable> {
2571 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
2572 OpcodeStr, !strconcat(Dt, "8"),
2573 v8i8, v8i8, IntOp, Commutable>;
2574 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2575 OpcodeStr, !strconcat(Dt, "8"),
2576 v16i8, v16i8, IntOp, Commutable>;
2578 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2579 InstrItinClass itinD16, InstrItinClass itinD32,
2580 InstrItinClass itinQ16, InstrItinClass itinQ32,
2581 string OpcodeStr, string Dt,
2583 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2584 OpcodeStr, Dt, IntOp> {
2585 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
2586 OpcodeStr, !strconcat(Dt, "8"),
2588 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2589 OpcodeStr, !strconcat(Dt, "8"),
2590 v16i8, v16i8, IntOp>;
2594 // ....then also with element size of 64 bits:
2595 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2596 InstrItinClass itinD16, InstrItinClass itinD32,
2597 InstrItinClass itinQ16, InstrItinClass itinQ32,
2598 string OpcodeStr, string Dt,
2599 Intrinsic IntOp, bit Commutable = 0>
2600 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2601 OpcodeStr, Dt, IntOp, Commutable> {
2602 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
2603 OpcodeStr, !strconcat(Dt, "64"),
2604 v1i64, v1i64, IntOp, Commutable>;
2605 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2606 OpcodeStr, !strconcat(Dt, "64"),
2607 v2i64, v2i64, IntOp, Commutable>;
2609 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2610 InstrItinClass itinD16, InstrItinClass itinD32,
2611 InstrItinClass itinQ16, InstrItinClass itinQ32,
2612 string OpcodeStr, string Dt,
2614 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2615 OpcodeStr, Dt, IntOp> {
2616 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
2617 OpcodeStr, !strconcat(Dt, "64"),
2618 v1i64, v1i64, IntOp>;
2619 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2620 OpcodeStr, !strconcat(Dt, "64"),
2621 v2i64, v2i64, IntOp>;
2624 // Neon Narrowing 3-register vector intrinsics,
2625 // source operand element sizes of 16, 32 and 64 bits:
2626 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2627 string OpcodeStr, string Dt,
2628 Intrinsic IntOp, bit Commutable = 0> {
2629 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
2630 OpcodeStr, !strconcat(Dt, "16"),
2631 v8i8, v8i16, IntOp, Commutable>;
2632 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
2633 OpcodeStr, !strconcat(Dt, "32"),
2634 v4i16, v4i32, IntOp, Commutable>;
2635 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
2636 OpcodeStr, !strconcat(Dt, "64"),
2637 v2i32, v2i64, IntOp, Commutable>;
2641 // Neon Long 3-register vector operations.
2643 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2644 InstrItinClass itin16, InstrItinClass itin32,
2645 string OpcodeStr, string Dt,
2646 SDNode OpNode, bit Commutable = 0> {
2647 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
2648 OpcodeStr, !strconcat(Dt, "8"),
2649 v8i16, v8i8, OpNode, Commutable>;
2650 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
2651 OpcodeStr, !strconcat(Dt, "16"),
2652 v4i32, v4i16, OpNode, Commutable>;
2653 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
2654 OpcodeStr, !strconcat(Dt, "32"),
2655 v2i64, v2i32, OpNode, Commutable>;
2658 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
2659 InstrItinClass itin, string OpcodeStr, string Dt,
2661 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
2662 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2663 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
2664 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2667 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2668 InstrItinClass itin16, InstrItinClass itin32,
2669 string OpcodeStr, string Dt,
2670 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2671 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
2672 OpcodeStr, !strconcat(Dt, "8"),
2673 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2674 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
2675 OpcodeStr, !strconcat(Dt, "16"),
2676 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2677 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
2678 OpcodeStr, !strconcat(Dt, "32"),
2679 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2682 // Neon Long 3-register vector intrinsics.
2684 // First with only element sizes of 16 and 32 bits:
2685 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2686 InstrItinClass itin16, InstrItinClass itin32,
2687 string OpcodeStr, string Dt,
2688 Intrinsic IntOp, bit Commutable = 0> {
2689 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
2690 OpcodeStr, !strconcat(Dt, "16"),
2691 v4i32, v4i16, IntOp, Commutable>;
2692 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
2693 OpcodeStr, !strconcat(Dt, "32"),
2694 v2i64, v2i32, IntOp, Commutable>;
2697 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
2698 InstrItinClass itin, string OpcodeStr, string Dt,
2700 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
2701 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2702 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
2703 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2706 // ....then also with element size of 8 bits:
2707 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2708 InstrItinClass itin16, InstrItinClass itin32,
2709 string OpcodeStr, string Dt,
2710 Intrinsic IntOp, bit Commutable = 0>
2711 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
2712 IntOp, Commutable> {
2713 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
2714 OpcodeStr, !strconcat(Dt, "8"),
2715 v8i16, v8i8, IntOp, Commutable>;
2718 // ....with explicit extend (VABDL).
2719 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2720 InstrItinClass itin, string OpcodeStr, string Dt,
2721 Intrinsic IntOp, SDNode ExtOp, bit Commutable = 0> {
2722 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
2723 OpcodeStr, !strconcat(Dt, "8"),
2724 v8i16, v8i8, IntOp, ExtOp, Commutable>;
2725 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
2726 OpcodeStr, !strconcat(Dt, "16"),
2727 v4i32, v4i16, IntOp, ExtOp, Commutable>;
2728 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
2729 OpcodeStr, !strconcat(Dt, "32"),
2730 v2i64, v2i32, IntOp, ExtOp, Commutable>;
2734 // Neon Wide 3-register vector intrinsics,
2735 // source operand element sizes of 8, 16 and 32 bits:
2736 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2737 string OpcodeStr, string Dt,
2738 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2739 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
2740 OpcodeStr, !strconcat(Dt, "8"),
2741 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2742 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
2743 OpcodeStr, !strconcat(Dt, "16"),
2744 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2745 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
2746 OpcodeStr, !strconcat(Dt, "32"),
2747 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2751 // Neon Multiply-Op vector operations,
2752 // element sizes of 8, 16 and 32 bits:
2753 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2754 InstrItinClass itinD16, InstrItinClass itinD32,
2755 InstrItinClass itinQ16, InstrItinClass itinQ32,
2756 string OpcodeStr, string Dt, SDNode OpNode> {
2757 // 64-bit vector types.
2758 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
2759 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
2760 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
2761 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
2762 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
2763 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
2765 // 128-bit vector types.
2766 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
2767 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
2768 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
2769 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
2770 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
2771 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
2774 multiclass N3VMulOpSL_HS<bits<4> op11_8,
2775 InstrItinClass itinD16, InstrItinClass itinD32,
2776 InstrItinClass itinQ16, InstrItinClass itinQ32,
2777 string OpcodeStr, string Dt, SDNode ShOp> {
2778 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
2779 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
2780 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
2781 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
2782 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
2783 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
2785 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
2786 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
2790 // Neon Intrinsic-Op vector operations,
2791 // element sizes of 8, 16 and 32 bits:
2792 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2793 InstrItinClass itinD, InstrItinClass itinQ,
2794 string OpcodeStr, string Dt, Intrinsic IntOp,
2796 // 64-bit vector types.
2797 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
2798 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
2799 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
2800 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
2801 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
2802 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
2804 // 128-bit vector types.
2805 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
2806 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
2807 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
2808 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
2809 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
2810 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
2813 // Neon 3-argument intrinsics,
2814 // element sizes of 8, 16 and 32 bits:
2815 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2816 InstrItinClass itinD, InstrItinClass itinQ,
2817 string OpcodeStr, string Dt, Intrinsic IntOp> {
2818 // 64-bit vector types.
2819 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
2820 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2821 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
2822 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
2823 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
2824 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
2826 // 128-bit vector types.
2827 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
2828 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
2829 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
2830 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
2831 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
2832 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
2836 // Neon Long Multiply-Op vector operations,
2837 // element sizes of 8, 16 and 32 bits:
2838 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2839 InstrItinClass itin16, InstrItinClass itin32,
2840 string OpcodeStr, string Dt, SDNode MulOp,
2842 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
2843 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
2844 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
2845 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
2846 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
2847 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
2850 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
2851 string Dt, SDNode MulOp, SDNode OpNode> {
2852 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
2853 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
2854 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
2855 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
2859 // Neon Long 3-argument intrinsics.
2861 // First with only element sizes of 16 and 32 bits:
2862 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2863 InstrItinClass itin16, InstrItinClass itin32,
2864 string OpcodeStr, string Dt, Intrinsic IntOp> {
2865 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
2866 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2867 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
2868 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2871 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
2872 string OpcodeStr, string Dt, Intrinsic IntOp> {
2873 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
2874 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
2875 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
2876 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2879 // ....then also with element size of 8 bits:
2880 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2881 InstrItinClass itin16, InstrItinClass itin32,
2882 string OpcodeStr, string Dt, Intrinsic IntOp>
2883 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
2884 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
2885 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
2888 // ....with explicit extend (VABAL).
2889 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2890 InstrItinClass itin, string OpcodeStr, string Dt,
2891 Intrinsic IntOp, SDNode ExtOp, SDNode OpNode> {
2892 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
2893 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
2894 IntOp, ExtOp, OpNode>;
2895 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
2896 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
2897 IntOp, ExtOp, OpNode>;
2898 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
2899 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
2900 IntOp, ExtOp, OpNode>;
2904 // Neon 2-register vector intrinsics,
2905 // element sizes of 8, 16 and 32 bits:
2906 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2907 bits<5> op11_7, bit op4,
2908 InstrItinClass itinD, InstrItinClass itinQ,
2909 string OpcodeStr, string Dt, Intrinsic IntOp> {
2910 // 64-bit vector types.
2911 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2912 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2913 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2914 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
2915 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2916 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
2918 // 128-bit vector types.
2919 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2920 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
2921 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2922 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
2923 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2924 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
2928 // Neon Pairwise long 2-register intrinsics,
2929 // element sizes of 8, 16 and 32 bits:
2930 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2931 bits<5> op11_7, bit op4,
2932 string OpcodeStr, string Dt, Intrinsic IntOp> {
2933 // 64-bit vector types.
2934 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2935 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
2936 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2937 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
2938 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2939 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
2941 // 128-bit vector types.
2942 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2943 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
2944 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2945 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
2946 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2947 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
2951 // Neon Pairwise long 2-register accumulate intrinsics,
2952 // element sizes of 8, 16 and 32 bits:
2953 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2954 bits<5> op11_7, bit op4,
2955 string OpcodeStr, string Dt, Intrinsic IntOp> {
2956 // 64-bit vector types.
2957 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2958 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
2959 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2960 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
2961 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2962 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
2964 // 128-bit vector types.
2965 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2966 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
2967 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2968 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
2969 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2970 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
2974 // Neon 2-register vector shift by immediate,
2975 // with f of either N2RegVShLFrm or N2RegVShRFrm
2976 // element sizes of 8, 16, 32 and 64 bits:
2977 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2978 InstrItinClass itin, string OpcodeStr, string Dt,
2979 SDNode OpNode, Format f> {
2980 // 64-bit vector types.
2981 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2982 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
2983 let Inst{21-19} = 0b001; // imm6 = 001xxx
2985 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2986 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
2987 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2989 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2990 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
2991 let Inst{21} = 0b1; // imm6 = 1xxxxx
2993 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, f, itin,
2994 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
2997 // 128-bit vector types.
2998 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
2999 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3000 let Inst{21-19} = 0b001; // imm6 = 001xxx
3002 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
3003 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3004 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3006 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
3007 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3008 let Inst{21} = 0b1; // imm6 = 1xxxxx
3010 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, f, itin,
3011 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3015 // Neon Shift-Accumulate vector operations,
3016 // element sizes of 8, 16, 32 and 64 bits:
3017 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3018 string OpcodeStr, string Dt, SDNode ShOp> {
3019 // 64-bit vector types.
3020 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4,
3021 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
3022 let Inst{21-19} = 0b001; // imm6 = 001xxx
3024 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4,
3025 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
3026 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3028 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4,
3029 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
3030 let Inst{21} = 0b1; // imm6 = 1xxxxx
3032 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4,
3033 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
3036 // 128-bit vector types.
3037 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4,
3038 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
3039 let Inst{21-19} = 0b001; // imm6 = 001xxx
3041 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4,
3042 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
3043 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3045 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4,
3046 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
3047 let Inst{21} = 0b1; // imm6 = 1xxxxx
3049 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4,
3050 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
3055 // Neon Shift-Insert vector operations,
3056 // with f of either N2RegVShLFrm or N2RegVShRFrm
3057 // element sizes of 8, 16, 32 and 64 bits:
3058 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3059 string OpcodeStr, SDNode ShOp,
3061 // 64-bit vector types.
3062 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4,
3063 f, OpcodeStr, "8", v8i8, ShOp> {
3064 let Inst{21-19} = 0b001; // imm6 = 001xxx
3066 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4,
3067 f, OpcodeStr, "16", v4i16, ShOp> {
3068 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3070 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4,
3071 f, OpcodeStr, "32", v2i32, ShOp> {
3072 let Inst{21} = 0b1; // imm6 = 1xxxxx
3074 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4,
3075 f, OpcodeStr, "64", v1i64, ShOp>;
3078 // 128-bit vector types.
3079 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4,
3080 f, OpcodeStr, "8", v16i8, ShOp> {
3081 let Inst{21-19} = 0b001; // imm6 = 001xxx
3083 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4,
3084 f, OpcodeStr, "16", v8i16, ShOp> {
3085 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3087 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4,
3088 f, OpcodeStr, "32", v4i32, ShOp> {
3089 let Inst{21} = 0b1; // imm6 = 1xxxxx
3091 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4,
3092 f, OpcodeStr, "64", v2i64, ShOp>;
3096 // Neon Shift Long operations,
3097 // element sizes of 8, 16, 32 bits:
3098 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3099 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
3100 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3101 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
3102 let Inst{21-19} = 0b001; // imm6 = 001xxx
3104 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3105 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
3106 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3108 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3109 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
3110 let Inst{21} = 0b1; // imm6 = 1xxxxx
3114 // Neon Shift Narrow operations,
3115 // element sizes of 16, 32, 64 bits:
3116 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3117 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
3119 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3120 OpcodeStr, !strconcat(Dt, "16"), v8i8, v8i16, OpNode> {
3121 let Inst{21-19} = 0b001; // imm6 = 001xxx
3123 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3124 OpcodeStr, !strconcat(Dt, "32"), v4i16, v4i32, OpNode> {
3125 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3127 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3128 OpcodeStr, !strconcat(Dt, "64"), v2i32, v2i64, OpNode> {
3129 let Inst{21} = 0b1; // imm6 = 1xxxxx
3133 //===----------------------------------------------------------------------===//
3134 // Instruction Definitions.
3135 //===----------------------------------------------------------------------===//
3137 // Vector Add Operations.
3139 // VADD : Vector Add (integer and floating-point)
3140 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
3142 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
3143 v2f32, v2f32, fadd, 1>;
3144 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
3145 v4f32, v4f32, fadd, 1>;
3146 // VADDL : Vector Add Long (Q = D + D)
3147 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3148 "vaddl", "s", add, sext, 1>;
3149 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3150 "vaddl", "u", add, zext, 1>;
3151 // VADDW : Vector Add Wide (Q = Q + D)
3152 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
3153 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
3154 // VHADD : Vector Halving Add
3155 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
3156 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3157 "vhadd", "s", int_arm_neon_vhadds, 1>;
3158 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
3159 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3160 "vhadd", "u", int_arm_neon_vhaddu, 1>;
3161 // VRHADD : Vector Rounding Halving Add
3162 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
3163 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3164 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
3165 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
3166 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3167 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
3168 // VQADD : Vector Saturating Add
3169 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
3170 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3171 "vqadd", "s", int_arm_neon_vqadds, 1>;
3172 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
3173 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3174 "vqadd", "u", int_arm_neon_vqaddu, 1>;
3175 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
3176 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
3177 int_arm_neon_vaddhn, 1>;
3178 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
3179 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
3180 int_arm_neon_vraddhn, 1>;
3182 // Vector Multiply Operations.
3184 // VMUL : Vector Multiply (integer, polynomial and floating-point)
3185 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
3186 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
3187 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
3188 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
3189 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
3190 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
3191 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
3192 v2f32, v2f32, fmul, 1>;
3193 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
3194 v4f32, v4f32, fmul, 1>;
3195 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
3196 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
3197 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
3200 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
3201 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
3202 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
3203 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3204 (DSubReg_i16_reg imm:$lane))),
3205 (SubReg_i16_lane imm:$lane)))>;
3206 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
3207 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
3208 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
3209 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3210 (DSubReg_i32_reg imm:$lane))),
3211 (SubReg_i32_lane imm:$lane)))>;
3212 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
3213 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
3214 (v4f32 (VMULslfq (v4f32 QPR:$src1),
3215 (v2f32 (EXTRACT_SUBREG QPR:$src2,
3216 (DSubReg_i32_reg imm:$lane))),
3217 (SubReg_i32_lane imm:$lane)))>;
3219 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
3220 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
3221 IIC_VMULi16Q, IIC_VMULi32Q,
3222 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
3223 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
3224 IIC_VMULi16Q, IIC_VMULi32Q,
3225 "vqdmulh", "s", int_arm_neon_vqdmulh>;
3226 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
3227 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3229 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
3230 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3231 (DSubReg_i16_reg imm:$lane))),
3232 (SubReg_i16_lane imm:$lane)))>;
3233 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
3234 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3236 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
3237 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3238 (DSubReg_i32_reg imm:$lane))),
3239 (SubReg_i32_lane imm:$lane)))>;
3241 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
3242 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
3243 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
3244 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
3245 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
3246 IIC_VMULi16Q, IIC_VMULi32Q,
3247 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
3248 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
3249 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3251 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
3252 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3253 (DSubReg_i16_reg imm:$lane))),
3254 (SubReg_i16_lane imm:$lane)))>;
3255 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
3256 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3258 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
3259 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3260 (DSubReg_i32_reg imm:$lane))),
3261 (SubReg_i32_lane imm:$lane)))>;
3263 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
3264 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3265 "vmull", "s", NEONvmulls, 1>;
3266 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3267 "vmull", "u", NEONvmullu, 1>;
3268 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
3269 v8i16, v8i8, int_arm_neon_vmullp, 1>;
3270 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
3271 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
3273 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
3274 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
3275 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
3276 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
3277 "vqdmull", "s", int_arm_neon_vqdmull>;
3279 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
3281 // VMLA : Vector Multiply Accumulate (integer and floating-point)
3282 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3283 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3284 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
3286 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
3288 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
3289 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3290 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
3292 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
3293 v4f32, v2f32, fmul, fadd>;
3295 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
3296 (mul (v8i16 QPR:$src2),
3297 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3298 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3299 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3300 (DSubReg_i16_reg imm:$lane))),
3301 (SubReg_i16_lane imm:$lane)))>;
3303 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
3304 (mul (v4i32 QPR:$src2),
3305 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3306 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3307 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3308 (DSubReg_i32_reg imm:$lane))),
3309 (SubReg_i32_lane imm:$lane)))>;
3311 def : Pat<(v4f32 (fadd (v4f32 QPR:$src1),
3312 (fmul (v4f32 QPR:$src2),
3313 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3314 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
3316 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3317 (DSubReg_i32_reg imm:$lane))),
3318 (SubReg_i32_lane imm:$lane)))>;
3320 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
3321 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3322 "vmlal", "s", NEONvmulls, add>;
3323 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3324 "vmlal", "u", NEONvmullu, add>;
3326 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
3327 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
3329 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
3330 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3331 "vqdmlal", "s", int_arm_neon_vqdmlal>;
3332 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
3334 // VMLS : Vector Multiply Subtract (integer and floating-point)
3335 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3336 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3337 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
3339 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
3341 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
3342 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3343 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
3345 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
3346 v4f32, v2f32, fmul, fsub>;
3348 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
3349 (mul (v8i16 QPR:$src2),
3350 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3351 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3352 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3353 (DSubReg_i16_reg imm:$lane))),
3354 (SubReg_i16_lane imm:$lane)))>;
3356 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
3357 (mul (v4i32 QPR:$src2),
3358 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3359 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3360 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3361 (DSubReg_i32_reg imm:$lane))),
3362 (SubReg_i32_lane imm:$lane)))>;
3364 def : Pat<(v4f32 (fsub (v4f32 QPR:$src1),
3365 (fmul (v4f32 QPR:$src2),
3366 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3367 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
3368 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3369 (DSubReg_i32_reg imm:$lane))),
3370 (SubReg_i32_lane imm:$lane)))>;
3372 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
3373 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3374 "vmlsl", "s", NEONvmulls, sub>;
3375 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3376 "vmlsl", "u", NEONvmullu, sub>;
3378 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
3379 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
3381 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
3382 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
3383 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3384 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3386 // Vector Subtract Operations.
3388 // VSUB : Vector Subtract (integer and floating-point)
3389 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
3390 "vsub", "i", sub, 0>;
3391 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
3392 v2f32, v2f32, fsub, 0>;
3393 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
3394 v4f32, v4f32, fsub, 0>;
3395 // VSUBL : Vector Subtract Long (Q = D - D)
3396 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3397 "vsubl", "s", sub, sext, 0>;
3398 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3399 "vsubl", "u", sub, zext, 0>;
3400 // VSUBW : Vector Subtract Wide (Q = Q - D)
3401 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
3402 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
3403 // VHSUB : Vector Halving Subtract
3404 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
3405 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3406 "vhsub", "s", int_arm_neon_vhsubs, 0>;
3407 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
3408 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3409 "vhsub", "u", int_arm_neon_vhsubu, 0>;
3410 // VQSUB : Vector Saturing Subtract
3411 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
3412 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3413 "vqsub", "s", int_arm_neon_vqsubs, 0>;
3414 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
3415 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3416 "vqsub", "u", int_arm_neon_vqsubu, 0>;
3417 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
3418 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
3419 int_arm_neon_vsubhn, 0>;
3420 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
3421 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
3422 int_arm_neon_vrsubhn, 0>;
3424 // Vector Comparisons.
3426 // VCEQ : Vector Compare Equal
3427 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3428 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
3429 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
3431 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
3434 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
3435 "$Vd, $Vm, #0", NEONvceqz>;
3437 // VCGE : Vector Compare Greater Than or Equal
3438 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3439 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
3440 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3441 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
3442 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
3444 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
3447 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
3448 "$Vd, $Vm, #0", NEONvcgez>;
3449 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
3450 "$Vd, $Vm, #0", NEONvclez>;
3452 // VCGT : Vector Compare Greater Than
3453 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3454 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
3455 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3456 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
3457 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
3459 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
3462 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
3463 "$Vd, $Vm, #0", NEONvcgtz>;
3464 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
3465 "$Vd, $Vm, #0", NEONvcltz>;
3467 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
3468 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
3469 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
3470 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
3471 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
3472 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
3473 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
3474 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
3475 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
3476 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
3477 // VTST : Vector Test Bits
3478 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
3479 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
3481 // Vector Bitwise Operations.
3483 def vnotd : PatFrag<(ops node:$in),
3484 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
3485 def vnotq : PatFrag<(ops node:$in),
3486 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
3489 // VAND : Vector Bitwise AND
3490 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
3491 v2i32, v2i32, and, 1>;
3492 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
3493 v4i32, v4i32, and, 1>;
3495 // VEOR : Vector Bitwise Exclusive OR
3496 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
3497 v2i32, v2i32, xor, 1>;
3498 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
3499 v4i32, v4i32, xor, 1>;
3501 // VORR : Vector Bitwise OR
3502 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
3503 v2i32, v2i32, or, 1>;
3504 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
3505 v4i32, v4i32, or, 1>;
3507 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
3508 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3510 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3512 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3513 let Inst{9} = SIMM{9};
3516 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
3517 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3519 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3521 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3522 let Inst{10-9} = SIMM{10-9};
3525 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
3526 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3528 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3530 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3531 let Inst{9} = SIMM{9};
3534 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
3535 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3537 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3539 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3540 let Inst{10-9} = SIMM{10-9};
3544 // VBIC : Vector Bitwise Bit Clear (AND NOT)
3545 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
3546 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
3547 "vbic", "$Vd, $Vn, $Vm", "",
3548 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
3549 (vnotd DPR:$Vm))))]>;
3550 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
3551 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
3552 "vbic", "$Vd, $Vn, $Vm", "",
3553 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
3554 (vnotq QPR:$Vm))))]>;
3556 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
3557 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3559 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3561 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3562 let Inst{9} = SIMM{9};
3565 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
3566 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3568 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3570 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3571 let Inst{10-9} = SIMM{10-9};
3574 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
3575 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3577 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3579 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3580 let Inst{9} = SIMM{9};
3583 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
3584 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3586 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3588 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3589 let Inst{10-9} = SIMM{10-9};
3592 // VORN : Vector Bitwise OR NOT
3593 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
3594 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
3595 "vorn", "$Vd, $Vn, $Vm", "",
3596 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
3597 (vnotd DPR:$Vm))))]>;
3598 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
3599 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
3600 "vorn", "$Vd, $Vn, $Vm", "",
3601 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
3602 (vnotq QPR:$Vm))))]>;
3604 // VMVN : Vector Bitwise NOT (Immediate)
3606 let isReMaterializable = 1 in {
3608 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
3609 (ins nModImm:$SIMM), IIC_VMOVImm,
3610 "vmvn", "i16", "$Vd, $SIMM", "",
3611 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
3612 let Inst{9} = SIMM{9};
3615 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
3616 (ins nModImm:$SIMM), IIC_VMOVImm,
3617 "vmvn", "i16", "$Vd, $SIMM", "",
3618 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
3619 let Inst{9} = SIMM{9};
3622 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
3623 (ins nModImm:$SIMM), IIC_VMOVImm,
3624 "vmvn", "i32", "$Vd, $SIMM", "",
3625 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
3626 let Inst{11-8} = SIMM{11-8};
3629 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
3630 (ins nModImm:$SIMM), IIC_VMOVImm,
3631 "vmvn", "i32", "$Vd, $SIMM", "",
3632 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
3633 let Inst{11-8} = SIMM{11-8};
3637 // VMVN : Vector Bitwise NOT
3638 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
3639 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
3640 "vmvn", "$Vd, $Vm", "",
3641 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
3642 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
3643 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
3644 "vmvn", "$Vd, $Vm", "",
3645 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
3646 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
3647 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
3649 // VBSL : Vector Bitwise Select
3650 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
3651 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3652 N3RegFrm, IIC_VCNTiD,
3653 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3655 (v2i32 (or (and DPR:$Vn, DPR:$src1),
3656 (and DPR:$Vm, (vnotd DPR:$src1)))))]>;
3657 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
3658 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3659 N3RegFrm, IIC_VCNTiQ,
3660 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3662 (v4i32 (or (and QPR:$Vn, QPR:$src1),
3663 (and QPR:$Vm, (vnotq QPR:$src1)))))]>;
3665 // VBIF : Vector Bitwise Insert if False
3666 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
3667 // FIXME: This instruction's encoding MAY NOT BE correct.
3668 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
3669 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3670 N3RegFrm, IIC_VBINiD,
3671 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3672 [/* For disassembly only; pattern left blank */]>;
3673 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
3674 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3675 N3RegFrm, IIC_VBINiQ,
3676 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3677 [/* For disassembly only; pattern left blank */]>;
3679 // VBIT : Vector Bitwise Insert if True
3680 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
3681 // FIXME: This instruction's encoding MAY NOT BE correct.
3682 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
3683 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3684 N3RegFrm, IIC_VBINiD,
3685 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3686 [/* For disassembly only; pattern left blank */]>;
3687 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
3688 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3689 N3RegFrm, IIC_VBINiQ,
3690 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3691 [/* For disassembly only; pattern left blank */]>;
3693 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
3694 // for equivalent operations with different register constraints; it just
3697 // Vector Absolute Differences.
3699 // VABD : Vector Absolute Difference
3700 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
3701 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3702 "vabd", "s", int_arm_neon_vabds, 1>;
3703 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
3704 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3705 "vabd", "u", int_arm_neon_vabdu, 1>;
3706 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
3707 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
3708 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
3709 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
3711 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
3712 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
3713 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
3714 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
3715 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
3717 // VABA : Vector Absolute Difference and Accumulate
3718 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3719 "vaba", "s", int_arm_neon_vabds, add>;
3720 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3721 "vaba", "u", int_arm_neon_vabdu, add>;
3723 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
3724 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
3725 "vabal", "s", int_arm_neon_vabds, zext, add>;
3726 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
3727 "vabal", "u", int_arm_neon_vabdu, zext, add>;
3729 // Vector Maximum and Minimum.
3731 // VMAX : Vector Maximum
3732 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
3733 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3734 "vmax", "s", int_arm_neon_vmaxs, 1>;
3735 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
3736 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3737 "vmax", "u", int_arm_neon_vmaxu, 1>;
3738 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
3740 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
3741 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
3743 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
3745 // VMIN : Vector Minimum
3746 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
3747 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3748 "vmin", "s", int_arm_neon_vmins, 1>;
3749 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
3750 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3751 "vmin", "u", int_arm_neon_vminu, 1>;
3752 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
3754 v2f32, v2f32, int_arm_neon_vmins, 1>;
3755 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
3757 v4f32, v4f32, int_arm_neon_vmins, 1>;
3759 // Vector Pairwise Operations.
3761 // VPADD : Vector Pairwise Add
3762 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3764 v8i8, v8i8, int_arm_neon_vpadd, 0>;
3765 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3767 v4i16, v4i16, int_arm_neon_vpadd, 0>;
3768 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3770 v2i32, v2i32, int_arm_neon_vpadd, 0>;
3771 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
3772 IIC_VPBIND, "vpadd", "f32",
3773 v2f32, v2f32, int_arm_neon_vpadd, 0>;
3775 // VPADDL : Vector Pairwise Add Long
3776 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
3777 int_arm_neon_vpaddls>;
3778 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
3779 int_arm_neon_vpaddlu>;
3781 // VPADAL : Vector Pairwise Add and Accumulate Long
3782 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
3783 int_arm_neon_vpadals>;
3784 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
3785 int_arm_neon_vpadalu>;
3787 // VPMAX : Vector Pairwise Maximum
3788 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3789 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
3790 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3791 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
3792 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3793 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
3794 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3795 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
3796 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3797 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
3798 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3799 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
3800 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
3801 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
3803 // VPMIN : Vector Pairwise Minimum
3804 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3805 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
3806 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3807 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
3808 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3809 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
3810 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3811 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
3812 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3813 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
3814 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3815 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
3816 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
3817 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
3819 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
3821 // VRECPE : Vector Reciprocal Estimate
3822 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
3823 IIC_VUNAD, "vrecpe", "u32",
3824 v2i32, v2i32, int_arm_neon_vrecpe>;
3825 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
3826 IIC_VUNAQ, "vrecpe", "u32",
3827 v4i32, v4i32, int_arm_neon_vrecpe>;
3828 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
3829 IIC_VUNAD, "vrecpe", "f32",
3830 v2f32, v2f32, int_arm_neon_vrecpe>;
3831 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
3832 IIC_VUNAQ, "vrecpe", "f32",
3833 v4f32, v4f32, int_arm_neon_vrecpe>;
3835 // VRECPS : Vector Reciprocal Step
3836 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
3837 IIC_VRECSD, "vrecps", "f32",
3838 v2f32, v2f32, int_arm_neon_vrecps, 1>;
3839 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
3840 IIC_VRECSQ, "vrecps", "f32",
3841 v4f32, v4f32, int_arm_neon_vrecps, 1>;
3843 // VRSQRTE : Vector Reciprocal Square Root Estimate
3844 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
3845 IIC_VUNAD, "vrsqrte", "u32",
3846 v2i32, v2i32, int_arm_neon_vrsqrte>;
3847 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
3848 IIC_VUNAQ, "vrsqrte", "u32",
3849 v4i32, v4i32, int_arm_neon_vrsqrte>;
3850 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
3851 IIC_VUNAD, "vrsqrte", "f32",
3852 v2f32, v2f32, int_arm_neon_vrsqrte>;
3853 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
3854 IIC_VUNAQ, "vrsqrte", "f32",
3855 v4f32, v4f32, int_arm_neon_vrsqrte>;
3857 // VRSQRTS : Vector Reciprocal Square Root Step
3858 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
3859 IIC_VRECSD, "vrsqrts", "f32",
3860 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
3861 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
3862 IIC_VRECSQ, "vrsqrts", "f32",
3863 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
3867 // VSHL : Vector Shift
3868 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
3869 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
3870 "vshl", "s", int_arm_neon_vshifts>;
3871 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
3872 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
3873 "vshl", "u", int_arm_neon_vshiftu>;
3874 // VSHL : Vector Shift Left (Immediate)
3875 defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl,
3877 // VSHR : Vector Shift Right (Immediate)
3878 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", NEONvshrs,
3880 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", NEONvshru,
3883 // VSHLL : Vector Shift Left Long
3884 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
3885 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
3887 // VSHLL : Vector Shift Left Long (with maximum shift count)
3888 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
3889 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
3890 ValueType OpTy, SDNode OpNode>
3891 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
3892 ResTy, OpTy, OpNode> {
3893 let Inst{21-16} = op21_16;
3895 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
3896 v8i16, v8i8, NEONvshlli>;
3897 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
3898 v4i32, v4i16, NEONvshlli>;
3899 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
3900 v2i64, v2i32, NEONvshlli>;
3902 // VSHRN : Vector Shift Right and Narrow
3903 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
3906 // VRSHL : Vector Rounding Shift
3907 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
3908 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3909 "vrshl", "s", int_arm_neon_vrshifts>;
3910 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
3911 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3912 "vrshl", "u", int_arm_neon_vrshiftu>;
3913 // VRSHR : Vector Rounding Shift Right
3914 defm VRSHRs : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs,
3916 defm VRSHRu : N2VSh_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", NEONvrshru,
3919 // VRSHRN : Vector Rounding Shift Right and Narrow
3920 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
3923 // VQSHL : Vector Saturating Shift
3924 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
3925 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3926 "vqshl", "s", int_arm_neon_vqshifts>;
3927 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
3928 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3929 "vqshl", "u", int_arm_neon_vqshiftu>;
3930 // VQSHL : Vector Saturating Shift Left (Immediate)
3931 defm VQSHLsi : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls,
3933 defm VQSHLui : N2VSh_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu,
3935 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
3936 defm VQSHLsu : N2VSh_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu,
3939 // VQSHRN : Vector Saturating Shift Right and Narrow
3940 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
3942 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
3945 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
3946 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
3949 // VQRSHL : Vector Saturating Rounding Shift
3950 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
3951 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3952 "vqrshl", "s", int_arm_neon_vqrshifts>;
3953 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
3954 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3955 "vqrshl", "u", int_arm_neon_vqrshiftu>;
3957 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
3958 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
3960 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
3963 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
3964 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
3967 // VSRA : Vector Shift Right and Accumulate
3968 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
3969 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
3970 // VRSRA : Vector Rounding Shift Right and Accumulate
3971 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
3972 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
3974 // VSLI : Vector Shift Left and Insert
3975 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli", NEONvsli, N2RegVShLFrm>;
3976 // VSRI : Vector Shift Right and Insert
3977 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri", NEONvsri, N2RegVShRFrm>;
3979 // Vector Absolute and Saturating Absolute.
3981 // VABS : Vector Absolute Value
3982 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
3983 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
3985 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
3986 IIC_VUNAD, "vabs", "f32",
3987 v2f32, v2f32, int_arm_neon_vabs>;
3988 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
3989 IIC_VUNAQ, "vabs", "f32",
3990 v4f32, v4f32, int_arm_neon_vabs>;
3992 // VQABS : Vector Saturating Absolute Value
3993 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
3994 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
3995 int_arm_neon_vqabs>;
3999 def vnegd : PatFrag<(ops node:$in),
4000 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
4001 def vnegq : PatFrag<(ops node:$in),
4002 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
4004 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4005 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
4006 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
4007 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
4008 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4009 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
4010 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
4011 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
4013 // VNEG : Vector Negate (integer)
4014 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
4015 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
4016 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
4017 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
4018 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
4019 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
4021 // VNEG : Vector Negate (floating-point)
4022 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
4023 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
4024 "vneg", "f32", "$Vd, $Vm", "",
4025 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
4026 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
4027 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
4028 "vneg", "f32", "$Vd, $Vm", "",
4029 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
4031 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
4032 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
4033 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
4034 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
4035 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
4036 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
4038 // VQNEG : Vector Saturating Negate
4039 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
4040 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
4041 int_arm_neon_vqneg>;
4043 // Vector Bit Counting Operations.
4045 // VCLS : Vector Count Leading Sign Bits
4046 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
4047 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
4049 // VCLZ : Vector Count Leading Zeros
4050 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
4051 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
4053 // VCNT : Vector Count One Bits
4054 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4055 IIC_VCNTiD, "vcnt", "8",
4056 v8i8, v8i8, int_arm_neon_vcnt>;
4057 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4058 IIC_VCNTiQ, "vcnt", "8",
4059 v16i8, v16i8, int_arm_neon_vcnt>;
4061 // Vector Swap -- for disassembly only.
4062 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
4063 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
4064 "vswp", "$Vd, $Vm", "", []>;
4065 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
4066 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
4067 "vswp", "$Vd, $Vm", "", []>;
4069 // Vector Move Operations.
4071 // VMOV : Vector Move (Register)
4073 let neverHasSideEffects = 1 in {
4074 def VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$Vd), (ins DPR:$Vm),
4075 N3RegFrm, IIC_VMOV, "vmov", "$Vd, $Vm", "", []> {
4076 let Vn{4-0} = Vm{4-0};
4078 def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$Vd), (ins QPR:$Vm),
4079 N3RegFrm, IIC_VMOV, "vmov", "$Vd, $Vm", "", []> {
4080 let Vn{4-0} = Vm{4-0};
4083 // Pseudo vector move instructions for QQ and QQQQ registers. This should
4084 // be expanded after register allocation is completed.
4085 def VMOVQQ : PseudoInst<(outs QQPR:$dst), (ins QQPR:$src),
4088 def VMOVQQQQ : PseudoInst<(outs QQQQPR:$dst), (ins QQQQPR:$src),
4090 } // neverHasSideEffects
4092 // VMOV : Vector Move (Immediate)
4094 let isReMaterializable = 1 in {
4095 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
4096 (ins nModImm:$SIMM), IIC_VMOVImm,
4097 "vmov", "i8", "$Vd, $SIMM", "",
4098 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
4099 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
4100 (ins nModImm:$SIMM), IIC_VMOVImm,
4101 "vmov", "i8", "$Vd, $SIMM", "",
4102 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
4104 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
4105 (ins nModImm:$SIMM), IIC_VMOVImm,
4106 "vmov", "i16", "$Vd, $SIMM", "",
4107 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
4108 let Inst{9} = SIMM{9};
4111 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
4112 (ins nModImm:$SIMM), IIC_VMOVImm,
4113 "vmov", "i16", "$Vd, $SIMM", "",
4114 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
4115 let Inst{9} = SIMM{9};
4118 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
4119 (ins nModImm:$SIMM), IIC_VMOVImm,
4120 "vmov", "i32", "$Vd, $SIMM", "",
4121 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
4122 let Inst{11-8} = SIMM{11-8};
4125 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
4126 (ins nModImm:$SIMM), IIC_VMOVImm,
4127 "vmov", "i32", "$Vd, $SIMM", "",
4128 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
4129 let Inst{11-8} = SIMM{11-8};
4132 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
4133 (ins nModImm:$SIMM), IIC_VMOVImm,
4134 "vmov", "i64", "$Vd, $SIMM", "",
4135 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
4136 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
4137 (ins nModImm:$SIMM), IIC_VMOVImm,
4138 "vmov", "i64", "$Vd, $SIMM", "",
4139 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
4140 } // isReMaterializable
4142 // VMOV : Vector Get Lane (move scalar to ARM core register)
4144 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
4145 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4146 IIC_VMOVSI, "vmov", "s8", "$R, $V[$lane]",
4147 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
4149 let Inst{21} = lane{2};
4150 let Inst{6-5} = lane{1-0};
4152 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
4153 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4154 IIC_VMOVSI, "vmov", "s16", "$R, $V[$lane]",
4155 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
4157 let Inst{21} = lane{1};
4158 let Inst{6} = lane{0};
4160 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
4161 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4162 IIC_VMOVSI, "vmov", "u8", "$R, $V[$lane]",
4163 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
4165 let Inst{21} = lane{2};
4166 let Inst{6-5} = lane{1-0};
4168 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
4169 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4170 IIC_VMOVSI, "vmov", "u16", "$R, $V[$lane]",
4171 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
4173 let Inst{21} = lane{1};
4174 let Inst{6} = lane{0};
4176 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
4177 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4178 IIC_VMOVSI, "vmov", "32", "$R, $V[$lane]",
4179 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
4181 let Inst{21} = lane{0};
4183 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
4184 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
4185 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4186 (DSubReg_i8_reg imm:$lane))),
4187 (SubReg_i8_lane imm:$lane))>;
4188 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
4189 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4190 (DSubReg_i16_reg imm:$lane))),
4191 (SubReg_i16_lane imm:$lane))>;
4192 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
4193 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4194 (DSubReg_i8_reg imm:$lane))),
4195 (SubReg_i8_lane imm:$lane))>;
4196 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
4197 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4198 (DSubReg_i16_reg imm:$lane))),
4199 (SubReg_i16_lane imm:$lane))>;
4200 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
4201 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
4202 (DSubReg_i32_reg imm:$lane))),
4203 (SubReg_i32_lane imm:$lane))>;
4204 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
4205 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
4206 (SSubReg_f32_reg imm:$src2))>;
4207 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
4208 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
4209 (SSubReg_f32_reg imm:$src2))>;
4210 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
4211 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4212 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
4213 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4216 // VMOV : Vector Set Lane (move ARM core register to scalar)
4218 let Constraints = "$src1 = $V" in {
4219 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
4220 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4221 IIC_VMOVISL, "vmov", "8", "$V[$lane], $R",
4222 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
4223 GPR:$R, imm:$lane))]> {
4224 let Inst{21} = lane{2};
4225 let Inst{6-5} = lane{1-0};
4227 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
4228 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4229 IIC_VMOVISL, "vmov", "16", "$V[$lane], $R",
4230 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
4231 GPR:$R, imm:$lane))]> {
4232 let Inst{21} = lane{1};
4233 let Inst{6} = lane{0};
4235 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
4236 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4237 IIC_VMOVISL, "vmov", "32", "$V[$lane], $R",
4238 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
4239 GPR:$R, imm:$lane))]> {
4240 let Inst{21} = lane{0};
4243 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
4244 (v16i8 (INSERT_SUBREG QPR:$src1,
4245 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
4246 (DSubReg_i8_reg imm:$lane))),
4247 GPR:$src2, (SubReg_i8_lane imm:$lane))),
4248 (DSubReg_i8_reg imm:$lane)))>;
4249 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
4250 (v8i16 (INSERT_SUBREG QPR:$src1,
4251 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
4252 (DSubReg_i16_reg imm:$lane))),
4253 GPR:$src2, (SubReg_i16_lane imm:$lane))),
4254 (DSubReg_i16_reg imm:$lane)))>;
4255 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
4256 (v4i32 (INSERT_SUBREG QPR:$src1,
4257 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
4258 (DSubReg_i32_reg imm:$lane))),
4259 GPR:$src2, (SubReg_i32_lane imm:$lane))),
4260 (DSubReg_i32_reg imm:$lane)))>;
4262 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
4263 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
4264 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4265 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
4266 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
4267 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4269 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4270 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4271 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4272 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4274 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
4275 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4276 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
4277 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
4278 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
4279 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4281 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
4282 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4283 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
4284 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4285 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
4286 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4288 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
4289 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4290 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4292 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
4293 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
4294 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4296 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
4297 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4298 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4301 // VDUP : Vector Duplicate (from ARM core register to all elements)
4303 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4304 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
4305 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4306 [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4307 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4308 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
4309 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4310 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4312 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
4313 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
4314 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
4315 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
4316 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
4317 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
4319 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$V), (ins GPR:$R),
4320 IIC_VMOVIS, "vdup", "32", "$V, $R",
4321 [(set DPR:$V, (v2f32 (NEONvdup
4322 (f32 (bitconvert GPR:$R)))))]>;
4323 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$V), (ins GPR:$R),
4324 IIC_VMOVIS, "vdup", "32", "$V, $R",
4325 [(set QPR:$V, (v4f32 (NEONvdup
4326 (f32 (bitconvert GPR:$R)))))]>;
4328 // VDUP : Vector Duplicate Lane (from scalar to all elements)
4330 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
4332 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, nohash_imm:$lane),
4333 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm[$lane]",
4334 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
4336 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
4337 ValueType ResTy, ValueType OpTy>
4338 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, nohash_imm:$lane),
4339 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm[$lane]",
4340 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
4343 // Inst{19-16} is partially specified depending on the element size.
4345 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8> {
4346 let Inst{19-17} = lane{2-0};
4348 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16> {
4349 let Inst{19-18} = lane{1-0};
4351 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32> {
4352 let Inst{19} = lane{0};
4354 def VDUPLNfd : VDUPLND<{?,1,0,0}, "vdup", "32", v2f32> {
4355 let Inst{19} = lane{0};
4357 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8> {
4358 let Inst{19-17} = lane{2-0};
4360 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16> {
4361 let Inst{19-18} = lane{1-0};
4363 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32> {
4364 let Inst{19} = lane{0};
4366 def VDUPLNfq : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4f32, v2f32> {
4367 let Inst{19} = lane{0};
4370 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
4371 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
4372 (DSubReg_i8_reg imm:$lane))),
4373 (SubReg_i8_lane imm:$lane)))>;
4374 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
4375 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
4376 (DSubReg_i16_reg imm:$lane))),
4377 (SubReg_i16_lane imm:$lane)))>;
4378 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
4379 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
4380 (DSubReg_i32_reg imm:$lane))),
4381 (SubReg_i32_lane imm:$lane)))>;
4382 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
4383 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
4384 (DSubReg_i32_reg imm:$lane))),
4385 (SubReg_i32_lane imm:$lane)))>;
4387 def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4388 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
4389 def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4390 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
4392 // VMOVN : Vector Narrowing Move
4393 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
4394 "vmovn", "i", trunc>;
4395 // VQMOVN : Vector Saturating Narrowing Move
4396 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
4397 "vqmovn", "s", int_arm_neon_vqmovns>;
4398 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
4399 "vqmovn", "u", int_arm_neon_vqmovnu>;
4400 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
4401 "vqmovun", "s", int_arm_neon_vqmovnsu>;
4402 // VMOVL : Vector Lengthening Move
4403 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
4404 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
4406 // Vector Conversions.
4408 // VCVT : Vector Convert Between Floating-Point and Integers
4409 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4410 v2i32, v2f32, fp_to_sint>;
4411 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4412 v2i32, v2f32, fp_to_uint>;
4413 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4414 v2f32, v2i32, sint_to_fp>;
4415 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4416 v2f32, v2i32, uint_to_fp>;
4418 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4419 v4i32, v4f32, fp_to_sint>;
4420 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4421 v4i32, v4f32, fp_to_uint>;
4422 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4423 v4f32, v4i32, sint_to_fp>;
4424 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4425 v4f32, v4i32, uint_to_fp>;
4427 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
4428 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4429 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
4430 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4431 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
4432 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4433 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
4434 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4435 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
4437 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4438 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
4439 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4440 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
4441 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4442 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
4443 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4444 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
4448 // VREV64 : Vector Reverse elements within 64-bit doublewords
4450 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4451 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
4452 (ins DPR:$Vm), IIC_VMOVD,
4453 OpcodeStr, Dt, "$Vd, $Vm", "",
4454 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
4455 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4456 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
4457 (ins QPR:$Vm), IIC_VMOVQ,
4458 OpcodeStr, Dt, "$Vd, $Vm", "",
4459 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
4461 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
4462 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
4463 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
4464 def VREV64df : VREV64D<0b10, "vrev64", "32", v2f32>;
4466 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
4467 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
4468 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
4469 def VREV64qf : VREV64Q<0b10, "vrev64", "32", v4f32>;
4471 // VREV32 : Vector Reverse elements within 32-bit words
4473 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4474 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
4475 (ins DPR:$Vm), IIC_VMOVD,
4476 OpcodeStr, Dt, "$Vd, $Vm", "",
4477 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
4478 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4479 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
4480 (ins QPR:$Vm), IIC_VMOVQ,
4481 OpcodeStr, Dt, "$Vd, $Vm", "",
4482 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
4484 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
4485 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
4487 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
4488 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
4490 // VREV16 : Vector Reverse elements within 16-bit halfwords
4492 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4493 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
4494 (ins DPR:$Vm), IIC_VMOVD,
4495 OpcodeStr, Dt, "$Vd, $Vm", "",
4496 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
4497 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4498 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
4499 (ins QPR:$Vm), IIC_VMOVQ,
4500 OpcodeStr, Dt, "$Vd, $Vm", "",
4501 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
4503 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
4504 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
4506 // Other Vector Shuffles.
4508 // VEXT : Vector Extract
4510 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
4511 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
4512 (ins DPR:$Vn, DPR:$Vm, i32imm:$index), NVExtFrm,
4513 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4514 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
4515 (Ty DPR:$Vm), imm:$index)))]> {
4517 let Inst{11-8} = index{3-0};
4520 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
4521 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
4522 (ins QPR:$Vn, QPR:$Vm, i32imm:$index), NVExtFrm,
4523 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4524 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
4525 (Ty QPR:$Vm), imm:$index)))]> {
4527 let Inst{11-8} = index{3-0};
4530 def VEXTd8 : VEXTd<"vext", "8", v8i8> {
4531 let Inst{11-8} = index{3-0};
4533 def VEXTd16 : VEXTd<"vext", "16", v4i16> {
4534 let Inst{11-9} = index{2-0};
4537 def VEXTd32 : VEXTd<"vext", "32", v2i32> {
4538 let Inst{11-10} = index{1-0};
4539 let Inst{9-8} = 0b00;
4541 def VEXTdf : VEXTd<"vext", "32", v2f32> {
4542 let Inst{11} = index{0};
4543 let Inst{10-8} = 0b000;
4546 def VEXTq8 : VEXTq<"vext", "8", v16i8> {
4547 let Inst{11-8} = index{3-0};
4549 def VEXTq16 : VEXTq<"vext", "16", v8i16> {
4550 let Inst{11-9} = index{2-0};
4553 def VEXTq32 : VEXTq<"vext", "32", v4i32> {
4554 let Inst{11-10} = index{1-0};
4555 let Inst{9-8} = 0b00;
4557 def VEXTqf : VEXTq<"vext", "32", v4f32> {
4558 let Inst{11} = index{0};
4559 let Inst{10-8} = 0b000;
4562 // VTRN : Vector Transpose
4564 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
4565 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
4566 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
4568 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
4569 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
4570 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
4572 // VUZP : Vector Unzip (Deinterleave)
4574 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
4575 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
4576 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
4578 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
4579 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
4580 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
4582 // VZIP : Vector Zip (Interleave)
4584 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
4585 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
4586 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
4588 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
4589 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
4590 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
4592 // Vector Table Lookup and Table Extension.
4594 // VTBL : Vector Table Lookup
4596 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
4597 (ins DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
4598 "vtbl", "8", "$Vd, \\{$Vn\\}, $Vm", "",
4599 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 DPR:$Vn, DPR:$Vm)))]>;
4600 let hasExtraSrcRegAllocReq = 1 in {
4602 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
4603 (ins DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTB2,
4604 "vtbl", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "", []>;
4606 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
4607 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm), NVTBLFrm, IIC_VTB3,
4608 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm", "", []>;
4610 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
4611 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm),
4613 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm", "", []>;
4614 } // hasExtraSrcRegAllocReq = 1
4617 : PseudoNeonI<(outs DPR:$dst), (ins QPR:$tbl, DPR:$src), IIC_VTB2, "", []>;
4619 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
4621 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
4623 // VTBX : Vector Table Extension
4625 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
4626 (ins DPR:$orig, DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
4627 "vtbx", "8", "$Vd, \\{$Vn\\}, $Vm", "$orig = $Vd",
4628 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
4629 DPR:$orig, DPR:$Vn, DPR:$Vm)))]>;
4630 let hasExtraSrcRegAllocReq = 1 in {
4632 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
4633 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
4634 "vtbx", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "$orig = $Vd", []>;
4636 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
4637 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm),
4638 NVTBLFrm, IIC_VTBX3,
4639 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm",
4642 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd), (ins DPR:$orig, DPR:$Vn,
4643 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
4644 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm",
4646 } // hasExtraSrcRegAllocReq = 1
4649 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QPR:$tbl, DPR:$src),
4650 IIC_VTBX2, "$orig = $dst", []>;
4652 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4653 IIC_VTBX3, "$orig = $dst", []>;
4655 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4656 IIC_VTBX4, "$orig = $dst", []>;
4658 //===----------------------------------------------------------------------===//
4659 // NEON instructions for single-precision FP math
4660 //===----------------------------------------------------------------------===//
4662 class N2VSPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
4663 : NEONFPPat<(ResTy (OpNode SPR:$a)),
4664 (EXTRACT_SUBREG (OpTy (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)),
4668 class N3VSPat<SDNode OpNode, NeonI Inst>
4669 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
4670 (EXTRACT_SUBREG (v2f32
4671 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
4673 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
4677 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
4678 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
4679 (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
4681 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
4683 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
4687 // These need separate instructions because they must use DPR_VFP2 register
4688 // class which have SPR sub-registers.
4690 // Vector Add Operations used for single-precision FP
4691 let neverHasSideEffects = 1 in
4692 def VADDfd_sfp : N3VS<0,0,0b00,0b1101,0, "vadd", "f32", v2f32, v2f32, fadd, 1>;
4693 def : N3VSPat<fadd, VADDfd_sfp>;
4695 // Vector Sub Operations used for single-precision FP
4696 let neverHasSideEffects = 1 in
4697 def VSUBfd_sfp : N3VS<0,0,0b10,0b1101,0, "vsub", "f32", v2f32, v2f32, fsub, 0>;
4698 def : N3VSPat<fsub, VSUBfd_sfp>;
4700 // Vector Multiply Operations used for single-precision FP
4701 let neverHasSideEffects = 1 in
4702 def VMULfd_sfp : N3VS<1,0,0b00,0b1101,1, "vmul", "f32", v2f32, v2f32, fmul, 1>;
4703 def : N3VSPat<fmul, VMULfd_sfp>;
4705 // Vector Multiply-Accumulate/Subtract used for single-precision FP
4706 // vml[as].f32 can cause 4-8 cycle stalls in following ASIMD instructions, so
4707 // we want to avoid them for now. e.g., alternating vmla/vadd instructions.
4709 //let neverHasSideEffects = 1 in
4710 //def VMLAfd_sfp : N3VSMulOp<0,0,0b00,0b1101,1, IIC_VMACD, "vmla", "f32",
4711 // v2f32, fmul, fadd>;
4712 //def : N3VSMulOpPat<fmul, fadd, VMLAfd_sfp>;
4714 //let neverHasSideEffects = 1 in
4715 //def VMLSfd_sfp : N3VSMulOp<0,0,0b10,0b1101,1, IIC_VMACD, "vmls", "f32",
4716 // v2f32, fmul, fsub>;
4717 //def : N3VSMulOpPat<fmul, fsub, VMLSfd_sfp>;
4719 // Vector Absolute used for single-precision FP
4720 let neverHasSideEffects = 1 in
4721 def VABSfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01110, 0, 0,
4722 (outs DPR_VFP2:$Vd), (ins DPR_VFP2:$Vm), IIC_VUNAD,
4723 "vabs", "f32", "$Vd, $Vm", "", []>;
4724 def : N2VSPat<fabs, f32, v2f32, VABSfd_sfp>;
4726 // Vector Negate used for single-precision FP
4727 let neverHasSideEffects = 1 in
4728 def VNEGfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
4729 (outs DPR_VFP2:$Vd), (ins DPR_VFP2:$Vm), IIC_VUNAD,
4730 "vneg", "f32", "$Vd, $Vm", "", []>;
4731 def : N2VSPat<fneg, f32, v2f32, VNEGfd_sfp>;
4733 // Vector Maximum used for single-precision FP
4734 let neverHasSideEffects = 1 in
4735 def VMAXfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$Vd),
4736 (ins DPR_VFP2:$Vn, DPR_VFP2:$Vm), N3RegFrm, IIC_VBIND,
4737 "vmax", "f32", "$Vd, $Vn, $Vm", "", []>;
4738 def : N3VSPat<NEONfmax, VMAXfd_sfp>;
4740 // Vector Minimum used for single-precision FP
4741 let neverHasSideEffects = 1 in
4742 def VMINfd_sfp : N3V<0, 0, 0b10, 0b1111, 0, 0, (outs DPR_VFP2:$Vd),
4743 (ins DPR_VFP2:$Vn, DPR_VFP2:$Vm), N3RegFrm, IIC_VBIND,
4744 "vmin", "f32", "$Vd, $Vn, $Vm", "", []>;
4745 def : N3VSPat<NEONfmin, VMINfd_sfp>;
4747 // Vector Convert between single-precision FP and integer
4748 let neverHasSideEffects = 1 in
4749 def VCVTf2sd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4750 v2i32, v2f32, fp_to_sint>;
4751 def : N2VSPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
4753 let neverHasSideEffects = 1 in
4754 def VCVTf2ud_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4755 v2i32, v2f32, fp_to_uint>;
4756 def : N2VSPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
4758 let neverHasSideEffects = 1 in
4759 def VCVTs2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4760 v2f32, v2i32, sint_to_fp>;
4761 def : N2VSPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
4763 let neverHasSideEffects = 1 in
4764 def VCVTu2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4765 v2f32, v2i32, uint_to_fp>;
4766 def : N2VSPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
4768 //===----------------------------------------------------------------------===//
4769 // Non-Instruction Patterns
4770 //===----------------------------------------------------------------------===//
4773 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
4774 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
4775 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
4776 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
4777 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
4778 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
4779 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
4780 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
4781 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
4782 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
4783 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
4784 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
4785 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
4786 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
4787 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
4788 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
4789 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
4790 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
4791 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
4792 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
4793 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
4794 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
4795 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
4796 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
4797 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
4798 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
4799 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
4800 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
4801 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
4802 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
4804 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
4805 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
4806 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
4807 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
4808 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
4809 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
4810 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
4811 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
4812 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
4813 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
4814 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
4815 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
4816 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
4817 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
4818 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
4819 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
4820 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
4821 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
4822 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
4823 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
4824 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
4825 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
4826 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
4827 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
4828 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
4829 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
4830 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
4831 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
4832 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
4833 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;