1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
70 // VDUPLANE can produce a quad-register result from a double-register source,
71 // so the result is not constrained to match the source.
72 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
73 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
76 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
77 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
78 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
80 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
81 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
82 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
83 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
85 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
88 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
89 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
90 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
92 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
94 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
95 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
97 //===----------------------------------------------------------------------===//
98 // NEON operand definitions
99 //===----------------------------------------------------------------------===//
101 def nModImm : Operand<i32> {
102 let PrintMethod = "printNEONModImmOperand";
105 //===----------------------------------------------------------------------===//
106 // NEON load / store instructions
107 //===----------------------------------------------------------------------===//
109 let mayLoad = 1, neverHasSideEffects = 1 in {
110 // Use vldmia to load a Q register as a D register pair.
111 // This is equivalent to VLDMD except that it has a Q register operand
112 // instead of a pair of D registers.
114 : AXDI5<(outs QPR:$dst), (ins addrmode5:$addr, pred:$p),
115 IndexModeNone, IIC_fpLoadm,
116 "vldm${addr:submode}${p}\t${addr:base}, ${dst:dregpair}", "", []>;
118 // Use vld1 to load a Q register as a D register pair.
119 // This alternative to VLDMQ allows an alignment to be specified.
120 // This is equivalent to VLD1q64 except that it has a Q register operand.
122 : NLdSt<0,0b10,0b1010,0b1100, (outs QPR:$dst), (ins addrmode6:$addr),
123 IIC_VLD1, "vld1", "64", "${dst:dregpair}, $addr", "", []>;
124 } // mayLoad = 1, neverHasSideEffects = 1
126 let mayStore = 1, neverHasSideEffects = 1 in {
127 // Use vstmia to store a Q register as a D register pair.
128 // This is equivalent to VSTMD except that it has a Q register operand
129 // instead of a pair of D registers.
131 : AXDI5<(outs), (ins QPR:$src, addrmode5:$addr, pred:$p),
132 IndexModeNone, IIC_fpStorem,
133 "vstm${addr:submode}${p}\t${addr:base}, ${src:dregpair}", "", []>;
135 // Use vst1 to store a Q register as a D register pair.
136 // This alternative to VSTMQ allows an alignment to be specified.
137 // This is equivalent to VST1q64 except that it has a Q register operand.
139 : NLdSt<0,0b00,0b1010,0b1100, (outs), (ins addrmode6:$addr, QPR:$src),
140 IIC_VST, "vst1", "64", "${src:dregpair}, $addr", "", []>;
141 } // mayStore = 1, neverHasSideEffects = 1
143 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
145 // VLD1 : Vector Load (multiple single elements)
146 class VLD1D<bits<4> op7_4, string Dt>
147 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst),
148 (ins addrmode6:$addr), IIC_VLD1,
149 "vld1", Dt, "\\{$dst\\}, $addr", "", []>;
150 class VLD1Q<bits<4> op7_4, string Dt>
151 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$dst1, DPR:$dst2),
152 (ins addrmode6:$addr), IIC_VLD1,
153 "vld1", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>;
155 def VLD1d8 : VLD1D<0b0000, "8">;
156 def VLD1d16 : VLD1D<0b0100, "16">;
157 def VLD1d32 : VLD1D<0b1000, "32">;
158 def VLD1d64 : VLD1D<0b1100, "64">;
160 def VLD1q8 : VLD1Q<0b0000, "8">;
161 def VLD1q16 : VLD1Q<0b0100, "16">;
162 def VLD1q32 : VLD1Q<0b1000, "32">;
163 def VLD1q64 : VLD1Q<0b1100, "64">;
165 // ...with address register writeback:
166 class VLD1DWB<bits<4> op7_4, string Dt>
167 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst, GPR:$wb),
168 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1,
169 "vld1", Dt, "\\{$dst\\}, $addr$offset",
170 "$addr.addr = $wb", []>;
171 class VLD1QWB<bits<4> op7_4, string Dt>
172 : NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst, GPR:$wb),
173 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1,
174 "vld1", Dt, "${dst:dregpair}, $addr$offset",
175 "$addr.addr = $wb", []>;
177 def VLD1d8_UPD : VLD1DWB<0b0000, "8">;
178 def VLD1d16_UPD : VLD1DWB<0b0100, "16">;
179 def VLD1d32_UPD : VLD1DWB<0b1000, "32">;
180 def VLD1d64_UPD : VLD1DWB<0b1100, "64">;
182 def VLD1q8_UPD : VLD1QWB<0b0000, "8">;
183 def VLD1q16_UPD : VLD1QWB<0b0100, "16">;
184 def VLD1q32_UPD : VLD1QWB<0b1000, "32">;
185 def VLD1q64_UPD : VLD1QWB<0b1100, "64">;
187 // ...with 3 registers (some of these are only for the disassembler):
188 class VLD1D3<bits<4> op7_4, string Dt>
189 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
190 (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
191 "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
192 class VLD1D3WB<bits<4> op7_4, string Dt>
193 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
194 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1, "vld1", Dt,
195 "\\{$dst1, $dst2, $dst3\\}, $addr$offset", "$addr.addr = $wb", []>;
197 def VLD1d8T : VLD1D3<0b0000, "8">;
198 def VLD1d16T : VLD1D3<0b0100, "16">;
199 def VLD1d32T : VLD1D3<0b1000, "32">;
200 def VLD1d64T : VLD1D3<0b1100, "64">;
202 def VLD1d8T_UPD : VLD1D3WB<0b0000, "8">;
203 def VLD1d16T_UPD : VLD1D3WB<0b0100, "16">;
204 def VLD1d32T_UPD : VLD1D3WB<0b1000, "32">;
205 def VLD1d64T_UPD : VLD1D3WB<0b1100, "64">;
207 // ...with 4 registers (some of these are only for the disassembler):
208 class VLD1D4<bits<4> op7_4, string Dt>
209 : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
210 (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
211 "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
212 class VLD1D4WB<bits<4> op7_4, string Dt>
213 : NLdSt<0,0b10,0b0010,op7_4,
214 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
215 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1, "vld1", Dt,
216 "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset", "$addr.addr = $wb",
219 def VLD1d8Q : VLD1D4<0b0000, "8">;
220 def VLD1d16Q : VLD1D4<0b0100, "16">;
221 def VLD1d32Q : VLD1D4<0b1000, "32">;
222 def VLD1d64Q : VLD1D4<0b1100, "64">;
224 def VLD1d8Q_UPD : VLD1D4WB<0b0000, "8">;
225 def VLD1d16Q_UPD : VLD1D4WB<0b0100, "16">;
226 def VLD1d32Q_UPD : VLD1D4WB<0b1000, "32">;
227 def VLD1d64Q_UPD : VLD1D4WB<0b1100, "64">;
229 // VLD2 : Vector Load (multiple 2-element structures)
230 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
231 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2),
232 (ins addrmode6:$addr), IIC_VLD2,
233 "vld2", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>;
234 class VLD2Q<bits<4> op7_4, string Dt>
235 : NLdSt<0, 0b10, 0b0011, op7_4,
236 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
237 (ins addrmode6:$addr), IIC_VLD2,
238 "vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
240 def VLD2d8 : VLD2D<0b1000, 0b0000, "8">;
241 def VLD2d16 : VLD2D<0b1000, 0b0100, "16">;
242 def VLD2d32 : VLD2D<0b1000, 0b1000, "32">;
244 def VLD2q8 : VLD2Q<0b0000, "8">;
245 def VLD2q16 : VLD2Q<0b0100, "16">;
246 def VLD2q32 : VLD2Q<0b1000, "32">;
248 // ...with address register writeback:
249 class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
250 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
251 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2,
252 "vld2", Dt, "\\{$dst1, $dst2\\}, $addr$offset",
253 "$addr.addr = $wb", []>;
254 class VLD2QWB<bits<4> op7_4, string Dt>
255 : NLdSt<0, 0b10, 0b0011, op7_4,
256 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
257 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2,
258 "vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset",
259 "$addr.addr = $wb", []>;
261 def VLD2d8_UPD : VLD2DWB<0b1000, 0b0000, "8">;
262 def VLD2d16_UPD : VLD2DWB<0b1000, 0b0100, "16">;
263 def VLD2d32_UPD : VLD2DWB<0b1000, 0b1000, "32">;
265 def VLD2q8_UPD : VLD2QWB<0b0000, "8">;
266 def VLD2q16_UPD : VLD2QWB<0b0100, "16">;
267 def VLD2q32_UPD : VLD2QWB<0b1000, "32">;
269 // ...with double-spaced registers (for disassembly only):
270 def VLD2b8 : VLD2D<0b1001, 0b0000, "8">;
271 def VLD2b16 : VLD2D<0b1001, 0b0100, "16">;
272 def VLD2b32 : VLD2D<0b1001, 0b1000, "32">;
273 def VLD2b8_UPD : VLD2DWB<0b1001, 0b0000, "8">;
274 def VLD2b16_UPD : VLD2DWB<0b1001, 0b0100, "16">;
275 def VLD2b32_UPD : VLD2DWB<0b1001, 0b1000, "32">;
277 // VLD3 : Vector Load (multiple 3-element structures)
278 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
279 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
280 (ins addrmode6:$addr), IIC_VLD3,
281 "vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
283 def VLD3d8 : VLD3D<0b0100, 0b0000, "8">;
284 def VLD3d16 : VLD3D<0b0100, 0b0100, "16">;
285 def VLD3d32 : VLD3D<0b0100, 0b1000, "32">;
287 // ...with address register writeback:
288 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
289 : NLdSt<0, 0b10, op11_8, op7_4,
290 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
291 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD3,
292 "vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr$offset",
293 "$addr.addr = $wb", []>;
295 def VLD3d8_UPD : VLD3DWB<0b0100, 0b0000, "8">;
296 def VLD3d16_UPD : VLD3DWB<0b0100, 0b0100, "16">;
297 def VLD3d32_UPD : VLD3DWB<0b0100, 0b1000, "32">;
299 // ...with double-spaced registers (non-updating versions for disassembly only):
300 def VLD3q8 : VLD3D<0b0101, 0b0000, "8">;
301 def VLD3q16 : VLD3D<0b0101, 0b0100, "16">;
302 def VLD3q32 : VLD3D<0b0101, 0b1000, "32">;
303 def VLD3q8_UPD : VLD3DWB<0b0101, 0b0000, "8">;
304 def VLD3q16_UPD : VLD3DWB<0b0101, 0b0100, "16">;
305 def VLD3q32_UPD : VLD3DWB<0b0101, 0b1000, "32">;
307 // ...alternate versions to be allocated odd register numbers:
308 def VLD3q8odd_UPD : VLD3DWB<0b0101, 0b0000, "8">;
309 def VLD3q16odd_UPD : VLD3DWB<0b0101, 0b0100, "16">;
310 def VLD3q32odd_UPD : VLD3DWB<0b0101, 0b1000, "32">;
312 // VLD4 : Vector Load (multiple 4-element structures)
313 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
314 : NLdSt<0, 0b10, op11_8, op7_4,
315 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
316 (ins addrmode6:$addr), IIC_VLD4,
317 "vld4", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
319 def VLD4d8 : VLD4D<0b0000, 0b0000, "8">;
320 def VLD4d16 : VLD4D<0b0000, 0b0100, "16">;
321 def VLD4d32 : VLD4D<0b0000, 0b1000, "32">;
323 // ...with address register writeback:
324 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
325 : NLdSt<0, 0b10, op11_8, op7_4,
326 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
327 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD4,
328 "vld4", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset",
329 "$addr.addr = $wb", []>;
331 def VLD4d8_UPD : VLD4DWB<0b0000, 0b0000, "8">;
332 def VLD4d16_UPD : VLD4DWB<0b0000, 0b0100, "16">;
333 def VLD4d32_UPD : VLD4DWB<0b0000, 0b1000, "32">;
335 // ...with double-spaced registers (non-updating versions for disassembly only):
336 def VLD4q8 : VLD4D<0b0001, 0b0000, "8">;
337 def VLD4q16 : VLD4D<0b0001, 0b0100, "16">;
338 def VLD4q32 : VLD4D<0b0001, 0b1000, "32">;
339 def VLD4q8_UPD : VLD4DWB<0b0001, 0b0000, "8">;
340 def VLD4q16_UPD : VLD4DWB<0b0001, 0b0100, "16">;
341 def VLD4q32_UPD : VLD4DWB<0b0001, 0b1000, "32">;
343 // ...alternate versions to be allocated odd register numbers:
344 def VLD4q8odd_UPD : VLD4DWB<0b0001, 0b0000, "8">;
345 def VLD4q16odd_UPD : VLD4DWB<0b0001, 0b0100, "16">;
346 def VLD4q32odd_UPD : VLD4DWB<0b0001, 0b1000, "32">;
348 // VLD1LN : Vector Load (single element to one lane)
349 // FIXME: Not yet implemented.
351 // VLD2LN : Vector Load (single 2-element structure to one lane)
352 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
353 : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2),
354 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
355 IIC_VLD2, "vld2", Dt, "\\{$dst1[$lane], $dst2[$lane]\\}, $addr",
356 "$src1 = $dst1, $src2 = $dst2", []>;
358 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8">;
359 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16">;
360 def VLD2LNd32 : VLD2LN<0b1001, {?,0,?,?}, "32">;
362 // ...with double-spaced registers:
363 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16">;
364 def VLD2LNq32 : VLD2LN<0b1001, {?,1,?,?}, "32">;
366 // ...alternate versions to be allocated odd register numbers:
367 def VLD2LNq16odd : VLD2LN<0b0101, {?,?,1,?}, "16">;
368 def VLD2LNq32odd : VLD2LN<0b1001, {?,1,?,?}, "32">;
370 // ...with address register writeback:
371 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
372 : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
373 (ins addrmode6:$addr, am6offset:$offset,
374 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2, "vld2", Dt,
375 "\\{$dst1[$lane], $dst2[$lane]\\}, $addr$offset",
376 "$src1 = $dst1, $src2 = $dst2, $addr.addr = $wb", []>;
378 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8">;
379 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16">;
380 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,?,?}, "32">;
382 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16">;
383 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,?,?}, "32">;
385 // VLD3LN : Vector Load (single 3-element structure to one lane)
386 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
387 : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
388 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
389 nohash_imm:$lane), IIC_VLD3, "vld3", Dt,
390 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr",
391 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
393 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8">;
394 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16">;
395 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32">;
397 // ...with double-spaced registers:
398 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16">;
399 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32">;
401 // ...alternate versions to be allocated odd register numbers:
402 def VLD3LNq16odd : VLD3LN<0b0110, {?,?,1,0}, "16">;
403 def VLD3LNq32odd : VLD3LN<0b1010, {?,1,0,0}, "32">;
405 // ...with address register writeback:
406 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
407 : NLdSt<1, 0b10, op11_8, op7_4,
408 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
409 (ins addrmode6:$addr, am6offset:$offset,
410 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
411 IIC_VLD3, "vld3", Dt,
412 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr$offset",
413 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $addr.addr = $wb",
416 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8">;
417 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16">;
418 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32">;
420 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16">;
421 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32">;
423 // VLD4LN : Vector Load (single 4-element structure to one lane)
424 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
425 : NLdSt<1, 0b10, op11_8, op7_4,
426 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
427 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
428 nohash_imm:$lane), IIC_VLD4, "vld4", Dt,
429 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr",
430 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
432 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8">;
433 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16">;
434 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32">;
436 // ...with double-spaced registers:
437 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16">;
438 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32">;
440 // ...alternate versions to be allocated odd register numbers:
441 def VLD4LNq16odd : VLD4LN<0b0111, {?,?,1,?}, "16">;
442 def VLD4LNq32odd : VLD4LN<0b1011, {?,1,?,?}, "32">;
444 // ...with address register writeback:
445 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
446 : NLdSt<1, 0b10, op11_8, op7_4,
447 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
448 (ins addrmode6:$addr, am6offset:$offset,
449 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
450 IIC_VLD4, "vld4", Dt,
451 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr$offset",
452 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $addr.addr = $wb",
455 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8">;
456 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16">;
457 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32">;
459 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16">;
460 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32">;
462 // VLD1DUP : Vector Load (single element to all lanes)
463 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
464 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
465 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
466 // FIXME: Not yet implemented.
467 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
469 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
471 // VST1 : Vector Store (multiple single elements)
472 class VST1D<bits<4> op7_4, string Dt>
473 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src), IIC_VST,
474 "vst1", Dt, "\\{$src\\}, $addr", "", []>;
475 class VST1Q<bits<4> op7_4, string Dt>
476 : NLdSt<0,0b00,0b1010,op7_4, (outs),
477 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
478 "vst1", Dt, "\\{$src1, $src2\\}, $addr", "", []>;
480 def VST1d8 : VST1D<0b0000, "8">;
481 def VST1d16 : VST1D<0b0100, "16">;
482 def VST1d32 : VST1D<0b1000, "32">;
483 def VST1d64 : VST1D<0b1100, "64">;
485 def VST1q8 : VST1Q<0b0000, "8">;
486 def VST1q16 : VST1Q<0b0100, "16">;
487 def VST1q32 : VST1Q<0b1000, "32">;
488 def VST1q64 : VST1Q<0b1100, "64">;
490 // ...with address register writeback:
491 class VST1DWB<bits<4> op7_4, string Dt>
492 : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
493 (ins addrmode6:$addr, am6offset:$offset, DPR:$src), IIC_VST,
494 "vst1", Dt, "\\{$src\\}, $addr$offset", "$addr.addr = $wb", []>;
495 class VST1QWB<bits<4> op7_4, string Dt>
496 : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),
497 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), IIC_VST,
498 "vst1", Dt, "${src:dregpair}, $addr$offset", "$addr.addr = $wb", []>;
500 def VST1d8_UPD : VST1DWB<0b0000, "8">;
501 def VST1d16_UPD : VST1DWB<0b0100, "16">;
502 def VST1d32_UPD : VST1DWB<0b1000, "32">;
503 def VST1d64_UPD : VST1DWB<0b1100, "64">;
505 def VST1q8_UPD : VST1QWB<0b0000, "8">;
506 def VST1q16_UPD : VST1QWB<0b0100, "16">;
507 def VST1q32_UPD : VST1QWB<0b1000, "32">;
508 def VST1q64_UPD : VST1QWB<0b1100, "64">;
510 // ...with 3 registers (some of these are only for the disassembler):
511 class VST1D3<bits<4> op7_4, string Dt>
512 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
513 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
514 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>;
515 class VST1D3WB<bits<4> op7_4, string Dt>
516 : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
517 (ins addrmode6:$addr, am6offset:$offset,
518 DPR:$src1, DPR:$src2, DPR:$src3),
519 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr$offset",
520 "$addr.addr = $wb", []>;
522 def VST1d8T : VST1D3<0b0000, "8">;
523 def VST1d16T : VST1D3<0b0100, "16">;
524 def VST1d32T : VST1D3<0b1000, "32">;
525 def VST1d64T : VST1D3<0b1100, "64">;
527 def VST1d8T_UPD : VST1D3WB<0b0000, "8">;
528 def VST1d16T_UPD : VST1D3WB<0b0100, "16">;
529 def VST1d32T_UPD : VST1D3WB<0b1000, "32">;
530 def VST1d64T_UPD : VST1D3WB<0b1100, "64">;
532 // ...with 4 registers (some of these are only for the disassembler):
533 class VST1D4<bits<4> op7_4, string Dt>
534 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
535 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
536 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr", "",
538 class VST1D4WB<bits<4> op7_4, string Dt>
539 : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
540 (ins addrmode6:$addr, am6offset:$offset,
541 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
542 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
543 "$addr.addr = $wb", []>;
545 def VST1d8Q : VST1D4<0b0000, "8">;
546 def VST1d16Q : VST1D4<0b0100, "16">;
547 def VST1d32Q : VST1D4<0b1000, "32">;
548 def VST1d64Q : VST1D4<0b1100, "64">;
550 def VST1d8Q_UPD : VST1D4WB<0b0000, "8">;
551 def VST1d16Q_UPD : VST1D4WB<0b0100, "16">;
552 def VST1d32Q_UPD : VST1D4WB<0b1000, "32">;
553 def VST1d64Q_UPD : VST1D4WB<0b1100, "64">;
555 // VST2 : Vector Store (multiple 2-element structures)
556 class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
557 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
558 (ins addrmode6:$addr, DPR:$src1, DPR:$src2),
559 IIC_VST, "vst2", Dt, "\\{$src1, $src2\\}, $addr", "", []>;
560 class VST2Q<bits<4> op7_4, string Dt>
561 : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
562 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
563 IIC_VST, "vst2", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
566 def VST2d8 : VST2D<0b1000, 0b0000, "8">;
567 def VST2d16 : VST2D<0b1000, 0b0100, "16">;
568 def VST2d32 : VST2D<0b1000, 0b1000, "32">;
570 def VST2q8 : VST2Q<0b0000, "8">;
571 def VST2q16 : VST2Q<0b0100, "16">;
572 def VST2q32 : VST2Q<0b1000, "32">;
574 // ...with address register writeback:
575 class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
576 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
577 (ins addrmode6:$addr, am6offset:$offset, DPR:$src1, DPR:$src2),
578 IIC_VST, "vst2", Dt, "\\{$src1, $src2\\}, $addr$offset",
579 "$addr.addr = $wb", []>;
580 class VST2QWB<bits<4> op7_4, string Dt>
581 : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
582 (ins addrmode6:$addr, am6offset:$offset,
583 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
584 IIC_VST, "vst2", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
585 "$addr.addr = $wb", []>;
587 def VST2d8_UPD : VST2DWB<0b1000, 0b0000, "8">;
588 def VST2d16_UPD : VST2DWB<0b1000, 0b0100, "16">;
589 def VST2d32_UPD : VST2DWB<0b1000, 0b1000, "32">;
591 def VST2q8_UPD : VST2QWB<0b0000, "8">;
592 def VST2q16_UPD : VST2QWB<0b0100, "16">;
593 def VST2q32_UPD : VST2QWB<0b1000, "32">;
595 // ...with double-spaced registers (for disassembly only):
596 def VST2b8 : VST2D<0b1001, 0b0000, "8">;
597 def VST2b16 : VST2D<0b1001, 0b0100, "16">;
598 def VST2b32 : VST2D<0b1001, 0b1000, "32">;
599 def VST2b8_UPD : VST2DWB<0b1001, 0b0000, "8">;
600 def VST2b16_UPD : VST2DWB<0b1001, 0b0100, "16">;
601 def VST2b32_UPD : VST2DWB<0b1001, 0b1000, "32">;
603 // VST3 : Vector Store (multiple 3-element structures)
604 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
605 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
606 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
607 "vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>;
609 def VST3d8 : VST3D<0b0100, 0b0000, "8">;
610 def VST3d16 : VST3D<0b0100, 0b0100, "16">;
611 def VST3d32 : VST3D<0b0100, 0b1000, "32">;
613 // ...with address register writeback:
614 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
615 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
616 (ins addrmode6:$addr, am6offset:$offset,
617 DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
618 "vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr$offset",
619 "$addr.addr = $wb", []>;
621 def VST3d8_UPD : VST3DWB<0b0100, 0b0000, "8">;
622 def VST3d16_UPD : VST3DWB<0b0100, 0b0100, "16">;
623 def VST3d32_UPD : VST3DWB<0b0100, 0b1000, "32">;
625 // ...with double-spaced registers (non-updating versions for disassembly only):
626 def VST3q8 : VST3D<0b0101, 0b0000, "8">;
627 def VST3q16 : VST3D<0b0101, 0b0100, "16">;
628 def VST3q32 : VST3D<0b0101, 0b1000, "32">;
629 def VST3q8_UPD : VST3DWB<0b0101, 0b0000, "8">;
630 def VST3q16_UPD : VST3DWB<0b0101, 0b0100, "16">;
631 def VST3q32_UPD : VST3DWB<0b0101, 0b1000, "32">;
633 // ...alternate versions to be allocated odd register numbers:
634 def VST3q8odd_UPD : VST3DWB<0b0101, 0b0000, "8">;
635 def VST3q16odd_UPD : VST3DWB<0b0101, 0b0100, "16">;
636 def VST3q32odd_UPD : VST3DWB<0b0101, 0b1000, "32">;
638 // VST4 : Vector Store (multiple 4-element structures)
639 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
640 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
641 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
642 IIC_VST, "vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
645 def VST4d8 : VST4D<0b0000, 0b0000, "8">;
646 def VST4d16 : VST4D<0b0000, 0b0100, "16">;
647 def VST4d32 : VST4D<0b0000, 0b1000, "32">;
649 // ...with address register writeback:
650 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
651 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
652 (ins addrmode6:$addr, am6offset:$offset,
653 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST,
654 "vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
655 "$addr.addr = $wb", []>;
657 def VST4d8_UPD : VST4DWB<0b0000, 0b0000, "8">;
658 def VST4d16_UPD : VST4DWB<0b0000, 0b0100, "16">;
659 def VST4d32_UPD : VST4DWB<0b0000, 0b1000, "32">;
661 // ...with double-spaced registers (non-updating versions for disassembly only):
662 def VST4q8 : VST4D<0b0001, 0b0000, "8">;
663 def VST4q16 : VST4D<0b0001, 0b0100, "16">;
664 def VST4q32 : VST4D<0b0001, 0b1000, "32">;
665 def VST4q8_UPD : VST4DWB<0b0001, 0b0000, "8">;
666 def VST4q16_UPD : VST4DWB<0b0001, 0b0100, "16">;
667 def VST4q32_UPD : VST4DWB<0b0001, 0b1000, "32">;
669 // ...alternate versions to be allocated odd register numbers:
670 def VST4q8odd_UPD : VST4DWB<0b0001, 0b0000, "8">;
671 def VST4q16odd_UPD : VST4DWB<0b0001, 0b0100, "16">;
672 def VST4q32odd_UPD : VST4DWB<0b0001, 0b1000, "32">;
674 // VST1LN : Vector Store (single element from one lane)
675 // FIXME: Not yet implemented.
677 // VST2LN : Vector Store (single 2-element structure from one lane)
678 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
679 : NLdSt<1, 0b00, op11_8, op7_4, (outs),
680 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
681 IIC_VST, "vst2", Dt, "\\{$src1[$lane], $src2[$lane]\\}, $addr",
684 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8">;
685 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16">;
686 def VST2LNd32 : VST2LN<0b1001, {?,0,?,?}, "32">;
688 // ...with double-spaced registers:
689 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16">;
690 def VST2LNq32 : VST2LN<0b1001, {?,1,?,?}, "32">;
692 // ...alternate versions to be allocated odd register numbers:
693 def VST2LNq16odd : VST2LN<0b0101, {?,?,1,?}, "16">;
694 def VST2LNq32odd : VST2LN<0b1001, {?,1,?,?}, "32">;
696 // ...with address register writeback:
697 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
698 : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
699 (ins addrmode6:$addr, am6offset:$offset,
700 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST, "vst2", Dt,
701 "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset",
702 "$addr.addr = $wb", []>;
704 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8">;
705 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16">;
706 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,?,?}, "32">;
708 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16">;
709 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,?,?}, "32">;
711 // VST3LN : Vector Store (single 3-element structure from one lane)
712 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
713 : NLdSt<1, 0b00, op11_8, op7_4, (outs),
714 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
715 nohash_imm:$lane), IIC_VST, "vst3", Dt,
716 "\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr", "", []>;
718 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8">;
719 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16">;
720 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32">;
722 // ...with double-spaced registers:
723 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16">;
724 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32">;
726 // ...alternate versions to be allocated odd register numbers:
727 def VST3LNq16odd : VST3LN<0b0110, {?,?,1,0}, "16">;
728 def VST3LNq32odd : VST3LN<0b1010, {?,1,0,0}, "32">;
730 // ...with address register writeback:
731 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
732 : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
733 (ins addrmode6:$addr, am6offset:$offset,
734 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
736 "\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr$offset",
737 "$addr.addr = $wb", []>;
739 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8">;
740 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16">;
741 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32">;
743 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16">;
744 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32">;
746 // VST4LN : Vector Store (single 4-element structure from one lane)
747 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
748 : NLdSt<1, 0b00, op11_8, op7_4, (outs),
749 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
750 nohash_imm:$lane), IIC_VST, "vst4", Dt,
751 "\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr",
754 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8">;
755 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16">;
756 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32">;
758 // ...with double-spaced registers:
759 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16">;
760 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32">;
762 // ...alternate versions to be allocated odd register numbers:
763 def VST4LNq16odd : VST4LN<0b0111, {?,?,1,?}, "16">;
764 def VST4LNq32odd : VST4LN<0b1011, {?,1,?,?}, "32">;
766 // ...with address register writeback:
767 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
768 : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
769 (ins addrmode6:$addr, am6offset:$offset,
770 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
772 "\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr$offset",
773 "$addr.addr = $wb", []>;
775 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8">;
776 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16">;
777 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32">;
779 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16">;
780 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32">;
782 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
785 //===----------------------------------------------------------------------===//
786 // NEON pattern fragments
787 //===----------------------------------------------------------------------===//
789 // Extract D sub-registers of Q registers.
790 def DSubReg_i8_reg : SDNodeXForm<imm, [{
791 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
792 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
794 def DSubReg_i16_reg : SDNodeXForm<imm, [{
795 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
796 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
798 def DSubReg_i32_reg : SDNodeXForm<imm, [{
799 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
800 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
802 def DSubReg_f64_reg : SDNodeXForm<imm, [{
803 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
804 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
807 // Extract S sub-registers of Q/D registers.
808 def SSubReg_f32_reg : SDNodeXForm<imm, [{
809 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
810 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
813 // Translate lane numbers from Q registers to D subregs.
814 def SubReg_i8_lane : SDNodeXForm<imm, [{
815 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
817 def SubReg_i16_lane : SDNodeXForm<imm, [{
818 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
820 def SubReg_i32_lane : SDNodeXForm<imm, [{
821 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
824 //===----------------------------------------------------------------------===//
825 // Instruction Classes
826 //===----------------------------------------------------------------------===//
828 // Basic 2-register operations: single-, double- and quad-register.
829 class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
830 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
831 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
832 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
833 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
834 IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
835 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
836 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
837 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
838 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
839 (ins DPR:$src), IIC_VUNAD, OpcodeStr, Dt,"$dst, $src", "",
840 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
841 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
842 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
843 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
844 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
845 (ins QPR:$src), IIC_VUNAQ, OpcodeStr, Dt,"$dst, $src", "",
846 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
848 // Basic 2-register intrinsics, both double- and quad-register.
849 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
850 bits<2> op17_16, bits<5> op11_7, bit op4,
851 InstrItinClass itin, string OpcodeStr, string Dt,
852 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
853 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
854 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
855 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
856 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
857 bits<2> op17_16, bits<5> op11_7, bit op4,
858 InstrItinClass itin, string OpcodeStr, string Dt,
859 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
860 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
861 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
862 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
864 // Narrow 2-register intrinsics.
865 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
866 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
867 InstrItinClass itin, string OpcodeStr, string Dt,
868 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
869 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
870 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
871 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
873 // Long 2-register intrinsics (currently only used for VMOVL).
874 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
875 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
876 InstrItinClass itin, string OpcodeStr, string Dt,
877 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
878 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$dst),
879 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
880 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
882 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
883 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
884 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
885 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
886 OpcodeStr, Dt, "$dst1, $dst2",
887 "$src1 = $dst1, $src2 = $dst2", []>;
888 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
889 InstrItinClass itin, string OpcodeStr, string Dt>
890 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
891 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$dst1, $dst2",
892 "$src1 = $dst1, $src2 = $dst2", []>;
894 // Basic 3-register operations: single-, double- and quad-register.
895 class N3VS<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
896 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
897 SDNode OpNode, bit Commutable>
898 : N3V<op24, op23, op21_20, op11_8, 0, op4,
899 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm,
900 IIC_VBIND, OpcodeStr, Dt, "$dst, $src1, $src2", "", []> {
901 let isCommutable = Commutable;
904 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
905 InstrItinClass itin, string OpcodeStr, string Dt,
906 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
907 : N3V<op24, op23, op21_20, op11_8, 0, op4,
908 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
909 OpcodeStr, Dt, "$dst, $src1, $src2", "",
910 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
911 let isCommutable = Commutable;
913 // Same as N3VD but no data type.
914 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
915 InstrItinClass itin, string OpcodeStr,
916 ValueType ResTy, ValueType OpTy,
917 SDNode OpNode, bit Commutable>
918 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
919 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
920 OpcodeStr, "$dst, $src1, $src2", "",
921 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]>{
922 let isCommutable = Commutable;
925 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
926 InstrItinClass itin, string OpcodeStr, string Dt,
927 ValueType Ty, SDNode ShOp>
928 : N3V<0, 1, op21_20, op11_8, 1, 0,
929 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
930 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
932 (Ty (ShOp (Ty DPR:$src1),
933 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),imm:$lane)))))]> {
934 let isCommutable = 0;
936 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
937 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
938 : N3V<0, 1, op21_20, op11_8, 1, 0,
939 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
940 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$dst, $src1, $src2[$lane]","",
942 (Ty (ShOp (Ty DPR:$src1),
943 (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
944 let isCommutable = 0;
947 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
948 InstrItinClass itin, string OpcodeStr, string Dt,
949 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
950 : N3V<op24, op23, op21_20, op11_8, 1, op4,
951 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, itin,
952 OpcodeStr, Dt, "$dst, $src1, $src2", "",
953 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
954 let isCommutable = Commutable;
956 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
957 InstrItinClass itin, string OpcodeStr,
958 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
959 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
960 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, itin,
961 OpcodeStr, "$dst, $src1, $src2", "",
962 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]>{
963 let isCommutable = Commutable;
965 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
966 InstrItinClass itin, string OpcodeStr, string Dt,
967 ValueType ResTy, ValueType OpTy, SDNode ShOp>
968 : N3V<1, 1, op21_20, op11_8, 1, 0,
969 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
970 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
971 [(set (ResTy QPR:$dst),
972 (ResTy (ShOp (ResTy QPR:$src1),
973 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
975 let isCommutable = 0;
977 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
978 ValueType ResTy, ValueType OpTy, SDNode ShOp>
979 : N3V<1, 1, op21_20, op11_8, 1, 0,
980 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
981 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$dst, $src1, $src2[$lane]","",
982 [(set (ResTy QPR:$dst),
983 (ResTy (ShOp (ResTy QPR:$src1),
984 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
986 let isCommutable = 0;
989 // Basic 3-register intrinsics, both double- and quad-register.
990 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
991 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
992 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
993 : N3V<op24, op23, op21_20, op11_8, 0, op4,
994 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), f, itin,
995 OpcodeStr, Dt, "$dst, $src1, $src2", "",
996 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
997 let isCommutable = Commutable;
999 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1000 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1001 : N3V<0, 1, op21_20, op11_8, 1, 0,
1002 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1003 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1004 [(set (Ty DPR:$dst),
1005 (Ty (IntOp (Ty DPR:$src1),
1006 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
1008 let isCommutable = 0;
1010 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1011 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1012 : N3V<0, 1, op21_20, op11_8, 1, 0,
1013 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1014 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1015 [(set (Ty DPR:$dst),
1016 (Ty (IntOp (Ty DPR:$src1),
1017 (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
1018 let isCommutable = 0;
1021 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1022 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1023 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1024 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1025 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), f, itin,
1026 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1027 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
1028 let isCommutable = Commutable;
1030 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1031 string OpcodeStr, string Dt,
1032 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1033 : N3V<1, 1, op21_20, op11_8, 1, 0,
1034 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1035 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1036 [(set (ResTy QPR:$dst),
1037 (ResTy (IntOp (ResTy QPR:$src1),
1038 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1040 let isCommutable = 0;
1042 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1043 string OpcodeStr, string Dt,
1044 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1045 : N3V<1, 1, op21_20, op11_8, 1, 0,
1046 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1047 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1048 [(set (ResTy QPR:$dst),
1049 (ResTy (IntOp (ResTy QPR:$src1),
1050 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
1052 let isCommutable = 0;
1055 // Multiply-Add/Sub operations: single-, double- and quad-register.
1056 class N3VSMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1057 InstrItinClass itin, string OpcodeStr, string Dt,
1058 ValueType Ty, SDNode MulOp, SDNode OpNode>
1059 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1060 (outs DPR_VFP2:$dst),
1061 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), N3RegFrm, itin,
1062 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst", []>;
1064 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1065 InstrItinClass itin, string OpcodeStr, string Dt,
1066 ValueType Ty, SDNode MulOp, SDNode OpNode>
1067 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1068 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1069 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1070 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
1071 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
1072 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1073 string OpcodeStr, string Dt,
1074 ValueType Ty, SDNode MulOp, SDNode ShOp>
1075 : N3V<0, 1, op21_20, op11_8, 1, 0,
1077 (ins DPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1079 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1080 [(set (Ty DPR:$dst),
1081 (Ty (ShOp (Ty DPR:$src1),
1082 (Ty (MulOp DPR:$src2,
1083 (Ty (NEONvduplane (Ty DPR_VFP2:$src3),
1085 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1086 string OpcodeStr, string Dt,
1087 ValueType Ty, SDNode MulOp, SDNode ShOp>
1088 : N3V<0, 1, op21_20, op11_8, 1, 0,
1090 (ins DPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1092 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1093 [(set (Ty DPR:$dst),
1094 (Ty (ShOp (Ty DPR:$src1),
1095 (Ty (MulOp DPR:$src2,
1096 (Ty (NEONvduplane (Ty DPR_8:$src3),
1099 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1100 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
1101 SDNode MulOp, SDNode OpNode>
1102 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1103 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), N3RegFrm, itin,
1104 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1105 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
1106 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
1107 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1108 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1109 SDNode MulOp, SDNode ShOp>
1110 : N3V<1, 1, op21_20, op11_8, 1, 0,
1112 (ins QPR:$src1, QPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1114 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1115 [(set (ResTy QPR:$dst),
1116 (ResTy (ShOp (ResTy QPR:$src1),
1117 (ResTy (MulOp QPR:$src2,
1118 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src3),
1120 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1121 string OpcodeStr, string Dt,
1122 ValueType ResTy, ValueType OpTy,
1123 SDNode MulOp, SDNode ShOp>
1124 : N3V<1, 1, op21_20, op11_8, 1, 0,
1126 (ins QPR:$src1, QPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1128 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1129 [(set (ResTy QPR:$dst),
1130 (ResTy (ShOp (ResTy QPR:$src1),
1131 (ResTy (MulOp QPR:$src2,
1132 (ResTy (NEONvduplane (OpTy DPR_8:$src3),
1135 // Neon 3-argument intrinsics, both double- and quad-register.
1136 // The destination register is also used as the first source operand register.
1137 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1138 InstrItinClass itin, string OpcodeStr, string Dt,
1139 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1140 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1141 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1142 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1143 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
1144 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
1145 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1146 InstrItinClass itin, string OpcodeStr, string Dt,
1147 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1148 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1149 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), N3RegFrm, itin,
1150 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1151 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
1152 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
1154 // Neon Long 3-argument intrinsic. The destination register is
1155 // a quad-register and is also used as the first source operand register.
1156 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1157 InstrItinClass itin, string OpcodeStr, string Dt,
1158 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
1159 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1160 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1161 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1163 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
1164 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1165 string OpcodeStr, string Dt,
1166 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1167 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1169 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1171 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1172 [(set (ResTy QPR:$dst),
1173 (ResTy (IntOp (ResTy QPR:$src1),
1175 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src3),
1177 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1178 InstrItinClass itin, string OpcodeStr, string Dt,
1179 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1180 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1182 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1184 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1185 [(set (ResTy QPR:$dst),
1186 (ResTy (IntOp (ResTy QPR:$src1),
1188 (OpTy (NEONvduplane (OpTy DPR_8:$src3),
1191 // Narrowing 3-register intrinsics.
1192 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1193 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
1194 Intrinsic IntOp, bit Commutable>
1195 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1196 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINi4D,
1197 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1198 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
1199 let isCommutable = Commutable;
1202 // Long 3-register intrinsics.
1203 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1204 InstrItinClass itin, string OpcodeStr, string Dt,
1205 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
1206 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1207 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1208 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1209 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
1210 let isCommutable = Commutable;
1212 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1213 string OpcodeStr, string Dt,
1214 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1215 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1216 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1217 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1218 [(set (ResTy QPR:$dst),
1219 (ResTy (IntOp (OpTy DPR:$src1),
1220 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1222 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1223 InstrItinClass itin, string OpcodeStr, string Dt,
1224 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1225 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1226 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1227 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1228 [(set (ResTy QPR:$dst),
1229 (ResTy (IntOp (OpTy DPR:$src1),
1230 (OpTy (NEONvduplane (OpTy DPR_8:$src2),
1233 // Wide 3-register intrinsics.
1234 class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1235 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
1236 Intrinsic IntOp, bit Commutable>
1237 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1238 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), N3RegFrm, IIC_VSUBiD,
1239 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1240 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
1241 let isCommutable = Commutable;
1244 // Pairwise long 2-register intrinsics, both double- and quad-register.
1245 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1246 bits<2> op17_16, bits<5> op11_7, bit op4,
1247 string OpcodeStr, string Dt,
1248 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1249 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1250 (ins DPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
1251 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
1252 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1253 bits<2> op17_16, bits<5> op11_7, bit op4,
1254 string OpcodeStr, string Dt,
1255 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1256 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1257 (ins QPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
1258 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
1260 // Pairwise long 2-register accumulate intrinsics,
1261 // both double- and quad-register.
1262 // The destination register is also used as the first source operand register.
1263 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1264 bits<2> op17_16, bits<5> op11_7, bit op4,
1265 string OpcodeStr, string Dt,
1266 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1267 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
1268 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), IIC_VPALiD,
1269 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
1270 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
1271 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1272 bits<2> op17_16, bits<5> op11_7, bit op4,
1273 string OpcodeStr, string Dt,
1274 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1275 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
1276 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VPALiQ,
1277 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
1278 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
1280 // Shift by immediate,
1281 // both double- and quad-register.
1282 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1283 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1284 ValueType Ty, SDNode OpNode>
1285 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1286 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), f, itin,
1287 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1288 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
1289 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1290 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1291 ValueType Ty, SDNode OpNode>
1292 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1293 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), f, itin,
1294 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1295 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
1297 // Long shift by immediate.
1298 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1299 string OpcodeStr, string Dt,
1300 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1301 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1302 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), N2RegVShLFrm,
1303 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1304 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
1305 (i32 imm:$SIMM))))]>;
1307 // Narrow shift by immediate.
1308 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1309 InstrItinClass itin, string OpcodeStr, string Dt,
1310 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1311 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1312 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), N2RegVShRFrm, itin,
1313 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1314 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
1315 (i32 imm:$SIMM))))]>;
1317 // Shift right by immediate and accumulate,
1318 // both double- and quad-register.
1319 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1320 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1321 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1322 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
1323 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1324 [(set DPR:$dst, (Ty (add DPR:$src1,
1325 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
1326 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1327 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1328 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1329 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
1330 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1331 [(set QPR:$dst, (Ty (add QPR:$src1,
1332 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
1334 // Shift by immediate and insert,
1335 // both double- and quad-register.
1336 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1337 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
1338 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1339 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), f, IIC_VSHLiD,
1340 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1341 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
1342 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1343 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
1344 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1345 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), f, IIC_VSHLiQ,
1346 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1347 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
1349 // Convert, with fractional bits immediate,
1350 // both double- and quad-register.
1351 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1352 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1354 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1355 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NVCVTFrm,
1356 IIC_VUNAD, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1357 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
1358 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1359 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1361 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1362 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NVCVTFrm,
1363 IIC_VUNAQ, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1364 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
1366 //===----------------------------------------------------------------------===//
1368 //===----------------------------------------------------------------------===//
1370 // Abbreviations used in multiclass suffixes:
1371 // Q = quarter int (8 bit) elements
1372 // H = half int (16 bit) elements
1373 // S = single int (32 bit) elements
1374 // D = double int (64 bit) elements
1376 // Neon 2-register vector operations -- for disassembly only.
1378 // First with only element sizes of 8, 16 and 32 bits:
1379 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1380 bits<5> op11_7, bit op4, string opc, string Dt,
1382 // 64-bit vector types.
1383 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
1384 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1385 opc, !strconcat(Dt, "8"), asm, "", []>;
1386 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
1387 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1388 opc, !strconcat(Dt, "16"), asm, "", []>;
1389 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
1390 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1391 opc, !strconcat(Dt, "32"), asm, "", []>;
1392 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
1393 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1394 opc, "f32", asm, "", []> {
1395 let Inst{10} = 1; // overwrite F = 1
1398 // 128-bit vector types.
1399 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
1400 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1401 opc, !strconcat(Dt, "8"), asm, "", []>;
1402 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
1403 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1404 opc, !strconcat(Dt, "16"), asm, "", []>;
1405 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
1406 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1407 opc, !strconcat(Dt, "32"), asm, "", []>;
1408 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
1409 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1410 opc, "f32", asm, "", []> {
1411 let Inst{10} = 1; // overwrite F = 1
1415 // Neon 3-register vector operations.
1417 // First with only element sizes of 8, 16 and 32 bits:
1418 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1419 InstrItinClass itinD16, InstrItinClass itinD32,
1420 InstrItinClass itinQ16, InstrItinClass itinQ32,
1421 string OpcodeStr, string Dt,
1422 SDNode OpNode, bit Commutable = 0> {
1423 // 64-bit vector types.
1424 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
1425 OpcodeStr, !strconcat(Dt, "8"),
1426 v8i8, v8i8, OpNode, Commutable>;
1427 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
1428 OpcodeStr, !strconcat(Dt, "16"),
1429 v4i16, v4i16, OpNode, Commutable>;
1430 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
1431 OpcodeStr, !strconcat(Dt, "32"),
1432 v2i32, v2i32, OpNode, Commutable>;
1434 // 128-bit vector types.
1435 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
1436 OpcodeStr, !strconcat(Dt, "8"),
1437 v16i8, v16i8, OpNode, Commutable>;
1438 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
1439 OpcodeStr, !strconcat(Dt, "16"),
1440 v8i16, v8i16, OpNode, Commutable>;
1441 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
1442 OpcodeStr, !strconcat(Dt, "32"),
1443 v4i32, v4i32, OpNode, Commutable>;
1446 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
1447 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1449 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
1451 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1452 v8i16, v4i16, ShOp>;
1453 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
1454 v4i32, v2i32, ShOp>;
1457 // ....then also with element size 64 bits:
1458 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1459 InstrItinClass itinD, InstrItinClass itinQ,
1460 string OpcodeStr, string Dt,
1461 SDNode OpNode, bit Commutable = 0>
1462 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
1463 OpcodeStr, Dt, OpNode, Commutable> {
1464 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
1465 OpcodeStr, !strconcat(Dt, "64"),
1466 v1i64, v1i64, OpNode, Commutable>;
1467 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
1468 OpcodeStr, !strconcat(Dt, "64"),
1469 v2i64, v2i64, OpNode, Commutable>;
1473 // Neon Narrowing 2-register vector intrinsics,
1474 // source operand element sizes of 16, 32 and 64 bits:
1475 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1476 bits<5> op11_7, bit op6, bit op4,
1477 InstrItinClass itin, string OpcodeStr, string Dt,
1479 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
1480 itin, OpcodeStr, !strconcat(Dt, "16"),
1481 v8i8, v8i16, IntOp>;
1482 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
1483 itin, OpcodeStr, !strconcat(Dt, "32"),
1484 v4i16, v4i32, IntOp>;
1485 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
1486 itin, OpcodeStr, !strconcat(Dt, "64"),
1487 v2i32, v2i64, IntOp>;
1491 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
1492 // source operand element sizes of 16, 32 and 64 bits:
1493 multiclass N2VLInt_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
1494 string OpcodeStr, string Dt, Intrinsic IntOp> {
1495 def v8i16 : N2VLInt<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1496 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
1497 def v4i32 : N2VLInt<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1498 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1499 def v2i64 : N2VLInt<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1500 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1504 // Neon 3-register vector intrinsics.
1506 // First with only element sizes of 16 and 32 bits:
1507 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
1508 InstrItinClass itinD16, InstrItinClass itinD32,
1509 InstrItinClass itinQ16, InstrItinClass itinQ32,
1510 string OpcodeStr, string Dt,
1511 Intrinsic IntOp, bit Commutable = 0> {
1512 // 64-bit vector types.
1513 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
1514 OpcodeStr, !strconcat(Dt, "16"),
1515 v4i16, v4i16, IntOp, Commutable>;
1516 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
1517 OpcodeStr, !strconcat(Dt, "32"),
1518 v2i32, v2i32, IntOp, Commutable>;
1520 // 128-bit vector types.
1521 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
1522 OpcodeStr, !strconcat(Dt, "16"),
1523 v8i16, v8i16, IntOp, Commutable>;
1524 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
1525 OpcodeStr, !strconcat(Dt, "32"),
1526 v4i32, v4i32, IntOp, Commutable>;
1529 multiclass N3VIntSL_HS<bits<4> op11_8,
1530 InstrItinClass itinD16, InstrItinClass itinD32,
1531 InstrItinClass itinQ16, InstrItinClass itinQ32,
1532 string OpcodeStr, string Dt, Intrinsic IntOp> {
1533 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
1534 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
1535 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
1536 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
1537 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
1538 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
1539 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
1540 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
1543 // ....then also with element size of 8 bits:
1544 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
1545 InstrItinClass itinD16, InstrItinClass itinD32,
1546 InstrItinClass itinQ16, InstrItinClass itinQ32,
1547 string OpcodeStr, string Dt,
1548 Intrinsic IntOp, bit Commutable = 0>
1549 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
1550 OpcodeStr, Dt, IntOp, Commutable> {
1551 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
1552 OpcodeStr, !strconcat(Dt, "8"),
1553 v8i8, v8i8, IntOp, Commutable>;
1554 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
1555 OpcodeStr, !strconcat(Dt, "8"),
1556 v16i8, v16i8, IntOp, Commutable>;
1559 // ....then also with element size of 64 bits:
1560 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
1561 InstrItinClass itinD16, InstrItinClass itinD32,
1562 InstrItinClass itinQ16, InstrItinClass itinQ32,
1563 string OpcodeStr, string Dt,
1564 Intrinsic IntOp, bit Commutable = 0>
1565 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
1566 OpcodeStr, Dt, IntOp, Commutable> {
1567 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
1568 OpcodeStr, !strconcat(Dt, "64"),
1569 v1i64, v1i64, IntOp, Commutable>;
1570 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
1571 OpcodeStr, !strconcat(Dt, "64"),
1572 v2i64, v2i64, IntOp, Commutable>;
1575 // Neon Narrowing 3-register vector intrinsics,
1576 // source operand element sizes of 16, 32 and 64 bits:
1577 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1578 string OpcodeStr, string Dt,
1579 Intrinsic IntOp, bit Commutable = 0> {
1580 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
1581 OpcodeStr, !strconcat(Dt, "16"),
1582 v8i8, v8i16, IntOp, Commutable>;
1583 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
1584 OpcodeStr, !strconcat(Dt, "32"),
1585 v4i16, v4i32, IntOp, Commutable>;
1586 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
1587 OpcodeStr, !strconcat(Dt, "64"),
1588 v2i32, v2i64, IntOp, Commutable>;
1592 // Neon Long 3-register vector intrinsics.
1594 // First with only element sizes of 16 and 32 bits:
1595 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1596 InstrItinClass itin16, InstrItinClass itin32,
1597 string OpcodeStr, string Dt,
1598 Intrinsic IntOp, bit Commutable = 0> {
1599 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
1600 OpcodeStr, !strconcat(Dt, "16"),
1601 v4i32, v4i16, IntOp, Commutable>;
1602 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
1603 OpcodeStr, !strconcat(Dt, "32"),
1604 v2i64, v2i32, IntOp, Commutable>;
1607 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
1608 InstrItinClass itin, string OpcodeStr, string Dt,
1610 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
1611 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1612 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
1613 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1616 // ....then also with element size of 8 bits:
1617 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1618 InstrItinClass itin16, InstrItinClass itin32,
1619 string OpcodeStr, string Dt,
1620 Intrinsic IntOp, bit Commutable = 0>
1621 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
1622 IntOp, Commutable> {
1623 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
1624 OpcodeStr, !strconcat(Dt, "8"),
1625 v8i16, v8i8, IntOp, Commutable>;
1629 // Neon Wide 3-register vector intrinsics,
1630 // source operand element sizes of 8, 16 and 32 bits:
1631 multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1632 string OpcodeStr, string Dt,
1633 Intrinsic IntOp, bit Commutable = 0> {
1634 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4,
1635 OpcodeStr, !strconcat(Dt, "8"),
1636 v8i16, v8i8, IntOp, Commutable>;
1637 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4,
1638 OpcodeStr, !strconcat(Dt, "16"),
1639 v4i32, v4i16, IntOp, Commutable>;
1640 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4,
1641 OpcodeStr, !strconcat(Dt, "32"),
1642 v2i64, v2i32, IntOp, Commutable>;
1646 // Neon Multiply-Op vector operations,
1647 // element sizes of 8, 16 and 32 bits:
1648 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1649 InstrItinClass itinD16, InstrItinClass itinD32,
1650 InstrItinClass itinQ16, InstrItinClass itinQ32,
1651 string OpcodeStr, string Dt, SDNode OpNode> {
1652 // 64-bit vector types.
1653 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
1654 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
1655 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
1656 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
1657 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
1658 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
1660 // 128-bit vector types.
1661 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
1662 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
1663 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
1664 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
1665 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
1666 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
1669 multiclass N3VMulOpSL_HS<bits<4> op11_8,
1670 InstrItinClass itinD16, InstrItinClass itinD32,
1671 InstrItinClass itinQ16, InstrItinClass itinQ32,
1672 string OpcodeStr, string Dt, SDNode ShOp> {
1673 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
1674 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
1675 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
1676 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
1677 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
1678 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
1680 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
1681 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
1685 // Neon 3-argument intrinsics,
1686 // element sizes of 8, 16 and 32 bits:
1687 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1688 InstrItinClass itinD, InstrItinClass itinQ,
1689 string OpcodeStr, string Dt, Intrinsic IntOp> {
1690 // 64-bit vector types.
1691 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
1692 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
1693 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
1694 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
1695 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
1696 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
1698 // 128-bit vector types.
1699 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
1700 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
1701 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
1702 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
1703 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
1704 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
1708 // Neon Long 3-argument intrinsics.
1710 // First with only element sizes of 16 and 32 bits:
1711 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1712 InstrItinClass itin16, InstrItinClass itin32,
1713 string OpcodeStr, string Dt, Intrinsic IntOp> {
1714 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
1715 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1716 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
1717 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1720 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
1721 string OpcodeStr, string Dt, Intrinsic IntOp> {
1722 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
1723 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
1724 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
1725 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1728 // ....then also with element size of 8 bits:
1729 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1730 InstrItinClass itin16, InstrItinClass itin32,
1731 string OpcodeStr, string Dt, Intrinsic IntOp>
1732 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
1733 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
1734 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
1738 // Neon 2-register vector intrinsics,
1739 // element sizes of 8, 16 and 32 bits:
1740 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1741 bits<5> op11_7, bit op4,
1742 InstrItinClass itinD, InstrItinClass itinQ,
1743 string OpcodeStr, string Dt, Intrinsic IntOp> {
1744 // 64-bit vector types.
1745 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1746 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
1747 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1748 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
1749 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1750 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
1752 // 128-bit vector types.
1753 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1754 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
1755 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1756 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
1757 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1758 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
1762 // Neon Pairwise long 2-register intrinsics,
1763 // element sizes of 8, 16 and 32 bits:
1764 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1765 bits<5> op11_7, bit op4,
1766 string OpcodeStr, string Dt, Intrinsic IntOp> {
1767 // 64-bit vector types.
1768 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1769 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
1770 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1771 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
1772 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1773 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
1775 // 128-bit vector types.
1776 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1777 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
1778 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1779 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
1780 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1781 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
1785 // Neon Pairwise long 2-register accumulate intrinsics,
1786 // element sizes of 8, 16 and 32 bits:
1787 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1788 bits<5> op11_7, bit op4,
1789 string OpcodeStr, string Dt, Intrinsic IntOp> {
1790 // 64-bit vector types.
1791 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1792 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
1793 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1794 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
1795 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1796 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
1798 // 128-bit vector types.
1799 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1800 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
1801 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1802 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
1803 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1804 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
1808 // Neon 2-register vector shift by immediate,
1809 // with f of either N2RegVShLFrm or N2RegVShRFrm
1810 // element sizes of 8, 16, 32 and 64 bits:
1811 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1812 InstrItinClass itin, string OpcodeStr, string Dt,
1813 SDNode OpNode, Format f> {
1814 // 64-bit vector types.
1815 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
1816 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
1817 let Inst{21-19} = 0b001; // imm6 = 001xxx
1819 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
1820 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
1821 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1823 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
1824 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
1825 let Inst{21} = 0b1; // imm6 = 1xxxxx
1827 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, f, itin,
1828 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
1831 // 128-bit vector types.
1832 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
1833 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
1834 let Inst{21-19} = 0b001; // imm6 = 001xxx
1836 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
1837 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
1838 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1840 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
1841 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
1842 let Inst{21} = 0b1; // imm6 = 1xxxxx
1844 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, f, itin,
1845 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
1849 // Neon Shift-Accumulate vector operations,
1850 // element sizes of 8, 16, 32 and 64 bits:
1851 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1852 string OpcodeStr, string Dt, SDNode ShOp> {
1853 // 64-bit vector types.
1854 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1855 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
1856 let Inst{21-19} = 0b001; // imm6 = 001xxx
1858 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1859 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
1860 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1862 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1863 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
1864 let Inst{21} = 0b1; // imm6 = 1xxxxx
1866 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4,
1867 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
1870 // 128-bit vector types.
1871 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1872 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
1873 let Inst{21-19} = 0b001; // imm6 = 001xxx
1875 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1876 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
1877 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1879 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1880 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
1881 let Inst{21} = 0b1; // imm6 = 1xxxxx
1883 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4,
1884 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
1889 // Neon Shift-Insert vector operations,
1890 // with f of either N2RegVShLFrm or N2RegVShRFrm
1891 // element sizes of 8, 16, 32 and 64 bits:
1892 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1893 string OpcodeStr, SDNode ShOp,
1895 // 64-bit vector types.
1896 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4,
1897 f, OpcodeStr, "8", v8i8, ShOp> {
1898 let Inst{21-19} = 0b001; // imm6 = 001xxx
1900 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4,
1901 f, OpcodeStr, "16", v4i16, ShOp> {
1902 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1904 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4,
1905 f, OpcodeStr, "32", v2i32, ShOp> {
1906 let Inst{21} = 0b1; // imm6 = 1xxxxx
1908 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4,
1909 f, OpcodeStr, "64", v1i64, ShOp>;
1912 // 128-bit vector types.
1913 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4,
1914 f, OpcodeStr, "8", v16i8, ShOp> {
1915 let Inst{21-19} = 0b001; // imm6 = 001xxx
1917 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4,
1918 f, OpcodeStr, "16", v8i16, ShOp> {
1919 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1921 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4,
1922 f, OpcodeStr, "32", v4i32, ShOp> {
1923 let Inst{21} = 0b1; // imm6 = 1xxxxx
1925 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4,
1926 f, OpcodeStr, "64", v2i64, ShOp>;
1930 // Neon Shift Long operations,
1931 // element sizes of 8, 16, 32 bits:
1932 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
1933 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
1934 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1935 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
1936 let Inst{21-19} = 0b001; // imm6 = 001xxx
1938 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1939 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
1940 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1942 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1943 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
1944 let Inst{21} = 0b1; // imm6 = 1xxxxx
1948 // Neon Shift Narrow operations,
1949 // element sizes of 16, 32, 64 bits:
1950 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
1951 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
1953 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1954 OpcodeStr, !strconcat(Dt, "16"), v8i8, v8i16, OpNode> {
1955 let Inst{21-19} = 0b001; // imm6 = 001xxx
1957 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1958 OpcodeStr, !strconcat(Dt, "32"), v4i16, v4i32, OpNode> {
1959 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1961 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1962 OpcodeStr, !strconcat(Dt, "64"), v2i32, v2i64, OpNode> {
1963 let Inst{21} = 0b1; // imm6 = 1xxxxx
1967 //===----------------------------------------------------------------------===//
1968 // Instruction Definitions.
1969 //===----------------------------------------------------------------------===//
1971 // Vector Add Operations.
1973 // VADD : Vector Add (integer and floating-point)
1974 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
1976 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
1977 v2f32, v2f32, fadd, 1>;
1978 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
1979 v4f32, v4f32, fadd, 1>;
1980 // VADDL : Vector Add Long (Q = D + D)
1981 defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
1982 "vaddl", "s", int_arm_neon_vaddls, 1>;
1983 defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
1984 "vaddl", "u", int_arm_neon_vaddlu, 1>;
1985 // VADDW : Vector Add Wide (Q = Q + D)
1986 defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw", "s", int_arm_neon_vaddws, 0>;
1987 defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw", "u", int_arm_neon_vaddwu, 0>;
1988 // VHADD : Vector Halving Add
1989 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
1990 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
1991 "vhadd", "s", int_arm_neon_vhadds, 1>;
1992 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
1993 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
1994 "vhadd", "u", int_arm_neon_vhaddu, 1>;
1995 // VRHADD : Vector Rounding Halving Add
1996 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
1997 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
1998 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
1999 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
2000 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2001 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
2002 // VQADD : Vector Saturating Add
2003 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
2004 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2005 "vqadd", "s", int_arm_neon_vqadds, 1>;
2006 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
2007 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2008 "vqadd", "u", int_arm_neon_vqaddu, 1>;
2009 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
2010 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
2011 int_arm_neon_vaddhn, 1>;
2012 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
2013 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
2014 int_arm_neon_vraddhn, 1>;
2016 // Vector Multiply Operations.
2018 // VMUL : Vector Multiply (integer, polynomial and floating-point)
2019 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
2020 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
2021 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
2022 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
2023 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
2024 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
2025 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VBIND, "vmul", "f32",
2026 v2f32, v2f32, fmul, 1>;
2027 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VBINQ, "vmul", "f32",
2028 v4f32, v4f32, fmul, 1>;
2029 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
2030 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
2031 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
2034 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
2035 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
2036 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
2037 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2038 (DSubReg_i16_reg imm:$lane))),
2039 (SubReg_i16_lane imm:$lane)))>;
2040 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
2041 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
2042 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
2043 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2044 (DSubReg_i32_reg imm:$lane))),
2045 (SubReg_i32_lane imm:$lane)))>;
2046 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
2047 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
2048 (v4f32 (VMULslfq (v4f32 QPR:$src1),
2049 (v2f32 (EXTRACT_SUBREG QPR:$src2,
2050 (DSubReg_i32_reg imm:$lane))),
2051 (SubReg_i32_lane imm:$lane)))>;
2053 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
2054 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
2055 IIC_VMULi16Q, IIC_VMULi32Q,
2056 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
2057 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
2058 IIC_VMULi16Q, IIC_VMULi32Q,
2059 "vqdmulh", "s", int_arm_neon_vqdmulh>;
2060 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
2061 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
2063 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
2064 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2065 (DSubReg_i16_reg imm:$lane))),
2066 (SubReg_i16_lane imm:$lane)))>;
2067 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
2068 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
2070 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
2071 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2072 (DSubReg_i32_reg imm:$lane))),
2073 (SubReg_i32_lane imm:$lane)))>;
2075 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
2076 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
2077 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
2078 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
2079 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
2080 IIC_VMULi16Q, IIC_VMULi32Q,
2081 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
2082 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
2083 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
2085 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
2086 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2087 (DSubReg_i16_reg imm:$lane))),
2088 (SubReg_i16_lane imm:$lane)))>;
2089 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
2090 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
2092 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
2093 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2094 (DSubReg_i32_reg imm:$lane))),
2095 (SubReg_i32_lane imm:$lane)))>;
2097 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
2098 defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
2099 "vmull", "s", int_arm_neon_vmulls, 1>;
2100 defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
2101 "vmull", "u", int_arm_neon_vmullu, 1>;
2102 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
2103 v8i16, v8i8, int_arm_neon_vmullp, 1>;
2104 defm VMULLsls : N3VLIntSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s",
2105 int_arm_neon_vmulls>;
2106 defm VMULLslu : N3VLIntSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u",
2107 int_arm_neon_vmullu>;
2109 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
2110 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
2111 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
2112 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
2113 "vqdmull", "s", int_arm_neon_vqdmull>;
2115 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
2117 // VMLA : Vector Multiply Accumulate (integer and floating-point)
2118 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
2119 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
2120 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
2122 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
2124 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
2125 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
2126 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
2128 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
2129 v4f32, v2f32, fmul, fadd>;
2131 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
2132 (mul (v8i16 QPR:$src2),
2133 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
2134 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
2135 (v4i16 (EXTRACT_SUBREG QPR:$src3,
2136 (DSubReg_i16_reg imm:$lane))),
2137 (SubReg_i16_lane imm:$lane)))>;
2139 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
2140 (mul (v4i32 QPR:$src2),
2141 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
2142 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
2143 (v2i32 (EXTRACT_SUBREG QPR:$src3,
2144 (DSubReg_i32_reg imm:$lane))),
2145 (SubReg_i32_lane imm:$lane)))>;
2147 def : Pat<(v4f32 (fadd (v4f32 QPR:$src1),
2148 (fmul (v4f32 QPR:$src2),
2149 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
2150 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
2152 (v2f32 (EXTRACT_SUBREG QPR:$src3,
2153 (DSubReg_i32_reg imm:$lane))),
2154 (SubReg_i32_lane imm:$lane)))>;
2156 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
2157 defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
2158 "vmlal", "s", int_arm_neon_vmlals>;
2159 defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
2160 "vmlal", "u", int_arm_neon_vmlalu>;
2162 defm VMLALsls : N3VLInt3SL_HS<0, 0b0010, "vmlal", "s", int_arm_neon_vmlals>;
2163 defm VMLALslu : N3VLInt3SL_HS<1, 0b0010, "vmlal", "u", int_arm_neon_vmlalu>;
2165 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
2166 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
2167 "vqdmlal", "s", int_arm_neon_vqdmlal>;
2168 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
2170 // VMLS : Vector Multiply Subtract (integer and floating-point)
2171 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
2172 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
2173 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
2175 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
2177 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
2178 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
2179 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
2181 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
2182 v4f32, v2f32, fmul, fsub>;
2184 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
2185 (mul (v8i16 QPR:$src2),
2186 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
2187 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
2188 (v4i16 (EXTRACT_SUBREG QPR:$src3,
2189 (DSubReg_i16_reg imm:$lane))),
2190 (SubReg_i16_lane imm:$lane)))>;
2192 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
2193 (mul (v4i32 QPR:$src2),
2194 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
2195 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
2196 (v2i32 (EXTRACT_SUBREG QPR:$src3,
2197 (DSubReg_i32_reg imm:$lane))),
2198 (SubReg_i32_lane imm:$lane)))>;
2200 def : Pat<(v4f32 (fsub (v4f32 QPR:$src1),
2201 (fmul (v4f32 QPR:$src2),
2202 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
2203 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
2204 (v2f32 (EXTRACT_SUBREG QPR:$src3,
2205 (DSubReg_i32_reg imm:$lane))),
2206 (SubReg_i32_lane imm:$lane)))>;
2208 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
2209 defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
2210 "vmlsl", "s", int_arm_neon_vmlsls>;
2211 defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
2212 "vmlsl", "u", int_arm_neon_vmlslu>;
2214 defm VMLSLsls : N3VLInt3SL_HS<0, 0b0110, "vmlsl", "s", int_arm_neon_vmlsls>;
2215 defm VMLSLslu : N3VLInt3SL_HS<1, 0b0110, "vmlsl", "u", int_arm_neon_vmlslu>;
2217 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
2218 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
2219 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
2220 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
2222 // Vector Subtract Operations.
2224 // VSUB : Vector Subtract (integer and floating-point)
2225 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
2226 "vsub", "i", sub, 0>;
2227 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
2228 v2f32, v2f32, fsub, 0>;
2229 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
2230 v4f32, v4f32, fsub, 0>;
2231 // VSUBL : Vector Subtract Long (Q = D - D)
2232 defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
2233 "vsubl", "s", int_arm_neon_vsubls, 1>;
2234 defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
2235 "vsubl", "u", int_arm_neon_vsublu, 1>;
2236 // VSUBW : Vector Subtract Wide (Q = Q - D)
2237 defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw", "s", int_arm_neon_vsubws, 0>;
2238 defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw", "u", int_arm_neon_vsubwu, 0>;
2239 // VHSUB : Vector Halving Subtract
2240 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
2241 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2242 "vhsub", "s", int_arm_neon_vhsubs, 0>;
2243 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
2244 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2245 "vhsub", "u", int_arm_neon_vhsubu, 0>;
2246 // VQSUB : Vector Saturing Subtract
2247 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
2248 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2249 "vqsub", "s", int_arm_neon_vqsubs, 0>;
2250 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
2251 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2252 "vqsub", "u", int_arm_neon_vqsubu, 0>;
2253 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
2254 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
2255 int_arm_neon_vsubhn, 0>;
2256 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
2257 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
2258 int_arm_neon_vrsubhn, 0>;
2260 // Vector Comparisons.
2262 // VCEQ : Vector Compare Equal
2263 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2264 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
2265 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
2267 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
2269 // For disassembly only.
2270 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
2273 // VCGE : Vector Compare Greater Than or Equal
2274 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2275 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
2276 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2277 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
2278 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
2280 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
2282 // For disassembly only.
2283 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
2285 // For disassembly only.
2286 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
2289 // VCGT : Vector Compare Greater Than
2290 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2291 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
2292 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2293 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
2294 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
2296 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
2298 // For disassembly only.
2299 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
2301 // For disassembly only.
2302 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
2305 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
2306 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
2307 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
2308 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
2309 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
2310 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
2311 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
2312 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
2313 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
2314 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
2315 // VTST : Vector Test Bits
2316 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2317 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
2319 // Vector Bitwise Operations.
2321 def vnot8 : PatFrag<(ops node:$in),
2322 (xor node:$in, (bitconvert (v8i8 immAllOnesV)))>;
2323 def vnot16 : PatFrag<(ops node:$in),
2324 (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>;
2327 // VAND : Vector Bitwise AND
2328 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
2329 v2i32, v2i32, and, 1>;
2330 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
2331 v4i32, v4i32, and, 1>;
2333 // VEOR : Vector Bitwise Exclusive OR
2334 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
2335 v2i32, v2i32, xor, 1>;
2336 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
2337 v4i32, v4i32, xor, 1>;
2339 // VORR : Vector Bitwise OR
2340 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
2341 v2i32, v2i32, or, 1>;
2342 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
2343 v4i32, v4i32, or, 1>;
2345 // VBIC : Vector Bitwise Bit Clear (AND NOT)
2346 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2347 (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD,
2348 "vbic", "$dst, $src1, $src2", "",
2349 [(set DPR:$dst, (v2i32 (and DPR:$src1,
2350 (vnot8 DPR:$src2))))]>;
2351 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2352 (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINiQ,
2353 "vbic", "$dst, $src1, $src2", "",
2354 [(set QPR:$dst, (v4i32 (and QPR:$src1,
2355 (vnot16 QPR:$src2))))]>;
2357 // VORN : Vector Bitwise OR NOT
2358 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
2359 (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD,
2360 "vorn", "$dst, $src1, $src2", "",
2361 [(set DPR:$dst, (v2i32 (or DPR:$src1,
2362 (vnot8 DPR:$src2))))]>;
2363 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
2364 (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINiQ,
2365 "vorn", "$dst, $src1, $src2", "",
2366 [(set QPR:$dst, (v4i32 (or QPR:$src1,
2367 (vnot16 QPR:$src2))))]>;
2369 // VMVN : Vector Bitwise NOT
2370 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
2371 (outs DPR:$dst), (ins DPR:$src), IIC_VSUBiD,
2372 "vmvn", "$dst, $src", "",
2373 [(set DPR:$dst, (v2i32 (vnot8 DPR:$src)))]>;
2374 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
2375 (outs QPR:$dst), (ins QPR:$src), IIC_VSUBiD,
2376 "vmvn", "$dst, $src", "",
2377 [(set QPR:$dst, (v4i32 (vnot16 QPR:$src)))]>;
2378 def : Pat<(v2i32 (vnot8 DPR:$src)), (VMVNd DPR:$src)>;
2379 def : Pat<(v4i32 (vnot16 QPR:$src)), (VMVNq QPR:$src)>;
2381 // VBSL : Vector Bitwise Select
2382 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2383 (ins DPR:$src1, DPR:$src2, DPR:$src3),
2384 N3RegFrm, IIC_VCNTiD,
2385 "vbsl", "$dst, $src2, $src3", "$src1 = $dst",
2387 (v2i32 (or (and DPR:$src2, DPR:$src1),
2388 (and DPR:$src3, (vnot8 DPR:$src1)))))]>;
2389 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2390 (ins QPR:$src1, QPR:$src2, QPR:$src3),
2391 N3RegFrm, IIC_VCNTiQ,
2392 "vbsl", "$dst, $src2, $src3", "$src1 = $dst",
2394 (v4i32 (or (and QPR:$src2, QPR:$src1),
2395 (and QPR:$src3, (vnot16 QPR:$src1)))))]>;
2397 // VBIF : Vector Bitwise Insert if False
2398 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
2399 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
2400 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
2401 N3RegFrm, IIC_VBINiD,
2402 "vbif", "$dst, $src2, $src3", "$src1 = $dst",
2403 [/* For disassembly only; pattern left blank */]>;
2404 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
2405 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
2406 N3RegFrm, IIC_VBINiQ,
2407 "vbif", "$dst, $src2, $src3", "$src1 = $dst",
2408 [/* For disassembly only; pattern left blank */]>;
2410 // VBIT : Vector Bitwise Insert if True
2411 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
2412 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
2413 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
2414 N3RegFrm, IIC_VBINiD,
2415 "vbit", "$dst, $src2, $src3", "$src1 = $dst",
2416 [/* For disassembly only; pattern left blank */]>;
2417 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
2418 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
2419 N3RegFrm, IIC_VBINiQ,
2420 "vbit", "$dst, $src2, $src3", "$src1 = $dst",
2421 [/* For disassembly only; pattern left blank */]>;
2423 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
2424 // for equivalent operations with different register constraints; it just
2427 // Vector Absolute Differences.
2429 // VABD : Vector Absolute Difference
2430 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
2431 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2432 "vabd", "s", int_arm_neon_vabds, 0>;
2433 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
2434 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2435 "vabd", "u", int_arm_neon_vabdu, 0>;
2436 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
2437 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 0>;
2438 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
2439 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 0>;
2441 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
2442 defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, IIC_VSUBi4Q, IIC_VSUBi4Q,
2443 "vabdl", "s", int_arm_neon_vabdls, 0>;
2444 defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, IIC_VSUBi4Q, IIC_VSUBi4Q,
2445 "vabdl", "u", int_arm_neon_vabdlu, 0>;
2447 // VABA : Vector Absolute Difference and Accumulate
2448 defm VABAs : N3VInt3_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
2449 "vaba", "s", int_arm_neon_vabas>;
2450 defm VABAu : N3VInt3_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
2451 "vaba", "u", int_arm_neon_vabau>;
2453 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
2454 defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, IIC_VABAD, IIC_VABAD,
2455 "vabal", "s", int_arm_neon_vabals>;
2456 defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, IIC_VABAD, IIC_VABAD,
2457 "vabal", "u", int_arm_neon_vabalu>;
2459 // Vector Maximum and Minimum.
2461 // VMAX : Vector Maximum
2462 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
2463 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2464 "vmax", "s", int_arm_neon_vmaxs, 1>;
2465 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
2466 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2467 "vmax", "u", int_arm_neon_vmaxu, 1>;
2468 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
2470 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
2471 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
2473 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
2475 // VMIN : Vector Minimum
2476 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
2477 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2478 "vmin", "s", int_arm_neon_vmins, 1>;
2479 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
2480 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2481 "vmin", "u", int_arm_neon_vminu, 1>;
2482 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
2484 v2f32, v2f32, int_arm_neon_vmins, 1>;
2485 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
2487 v4f32, v4f32, int_arm_neon_vmins, 1>;
2489 // Vector Pairwise Operations.
2491 // VPADD : Vector Pairwise Add
2492 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
2494 v8i8, v8i8, int_arm_neon_vpadd, 0>;
2495 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
2497 v4i16, v4i16, int_arm_neon_vpadd, 0>;
2498 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
2500 v2i32, v2i32, int_arm_neon_vpadd, 0>;
2501 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
2502 IIC_VBIND, "vpadd", "f32",
2503 v2f32, v2f32, int_arm_neon_vpadd, 0>;
2505 // VPADDL : Vector Pairwise Add Long
2506 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
2507 int_arm_neon_vpaddls>;
2508 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
2509 int_arm_neon_vpaddlu>;
2511 // VPADAL : Vector Pairwise Add and Accumulate Long
2512 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
2513 int_arm_neon_vpadals>;
2514 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
2515 int_arm_neon_vpadalu>;
2517 // VPMAX : Vector Pairwise Maximum
2518 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2519 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
2520 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2521 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
2522 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2523 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
2524 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2525 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
2526 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2527 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
2528 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2529 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
2530 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2531 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
2533 // VPMIN : Vector Pairwise Minimum
2534 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2535 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
2536 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2537 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
2538 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2539 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
2540 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2541 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
2542 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2543 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
2544 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2545 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
2546 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VSUBi4D, "vpmin",
2547 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
2549 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
2551 // VRECPE : Vector Reciprocal Estimate
2552 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
2553 IIC_VUNAD, "vrecpe", "u32",
2554 v2i32, v2i32, int_arm_neon_vrecpe>;
2555 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
2556 IIC_VUNAQ, "vrecpe", "u32",
2557 v4i32, v4i32, int_arm_neon_vrecpe>;
2558 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
2559 IIC_VUNAD, "vrecpe", "f32",
2560 v2f32, v2f32, int_arm_neon_vrecpe>;
2561 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
2562 IIC_VUNAQ, "vrecpe", "f32",
2563 v4f32, v4f32, int_arm_neon_vrecpe>;
2565 // VRECPS : Vector Reciprocal Step
2566 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
2567 IIC_VRECSD, "vrecps", "f32",
2568 v2f32, v2f32, int_arm_neon_vrecps, 1>;
2569 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
2570 IIC_VRECSQ, "vrecps", "f32",
2571 v4f32, v4f32, int_arm_neon_vrecps, 1>;
2573 // VRSQRTE : Vector Reciprocal Square Root Estimate
2574 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
2575 IIC_VUNAD, "vrsqrte", "u32",
2576 v2i32, v2i32, int_arm_neon_vrsqrte>;
2577 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
2578 IIC_VUNAQ, "vrsqrte", "u32",
2579 v4i32, v4i32, int_arm_neon_vrsqrte>;
2580 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
2581 IIC_VUNAD, "vrsqrte", "f32",
2582 v2f32, v2f32, int_arm_neon_vrsqrte>;
2583 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
2584 IIC_VUNAQ, "vrsqrte", "f32",
2585 v4f32, v4f32, int_arm_neon_vrsqrte>;
2587 // VRSQRTS : Vector Reciprocal Square Root Step
2588 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
2589 IIC_VRECSD, "vrsqrts", "f32",
2590 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
2591 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
2592 IIC_VRECSQ, "vrsqrts", "f32",
2593 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
2597 // VSHL : Vector Shift
2598 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, N3RegVShFrm,
2599 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
2600 "vshl", "s", int_arm_neon_vshifts, 0>;
2601 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, N3RegVShFrm,
2602 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
2603 "vshl", "u", int_arm_neon_vshiftu, 0>;
2604 // VSHL : Vector Shift Left (Immediate)
2605 defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl,
2607 // VSHR : Vector Shift Right (Immediate)
2608 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", NEONvshrs,
2610 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", NEONvshru,
2613 // VSHLL : Vector Shift Left Long
2614 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
2615 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
2617 // VSHLL : Vector Shift Left Long (with maximum shift count)
2618 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
2619 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
2620 ValueType OpTy, SDNode OpNode>
2621 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
2622 ResTy, OpTy, OpNode> {
2623 let Inst{21-16} = op21_16;
2625 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
2626 v8i16, v8i8, NEONvshlli>;
2627 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
2628 v4i32, v4i16, NEONvshlli>;
2629 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
2630 v2i64, v2i32, NEONvshlli>;
2632 // VSHRN : Vector Shift Right and Narrow
2633 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
2636 // VRSHL : Vector Rounding Shift
2637 defm VRSHLs : N3VInt_QHSD<0, 0, 0b0101, 0, N3RegVShFrm,
2638 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
2639 "vrshl", "s", int_arm_neon_vrshifts, 0>;
2640 defm VRSHLu : N3VInt_QHSD<1, 0, 0b0101, 0, N3RegVShFrm,
2641 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
2642 "vrshl", "u", int_arm_neon_vrshiftu, 0>;
2643 // VRSHR : Vector Rounding Shift Right
2644 defm VRSHRs : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs,
2646 defm VRSHRu : N2VSh_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", NEONvrshru,
2649 // VRSHRN : Vector Rounding Shift Right and Narrow
2650 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
2653 // VQSHL : Vector Saturating Shift
2654 defm VQSHLs : N3VInt_QHSD<0, 0, 0b0100, 1, N3RegVShFrm,
2655 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
2656 "vqshl", "s", int_arm_neon_vqshifts, 0>;
2657 defm VQSHLu : N3VInt_QHSD<1, 0, 0b0100, 1, N3RegVShFrm,
2658 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
2659 "vqshl", "u", int_arm_neon_vqshiftu, 0>;
2660 // VQSHL : Vector Saturating Shift Left (Immediate)
2661 defm VQSHLsi : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls,
2663 defm VQSHLui : N2VSh_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu,
2665 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
2666 defm VQSHLsu : N2VSh_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu,
2669 // VQSHRN : Vector Saturating Shift Right and Narrow
2670 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
2672 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
2675 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
2676 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
2679 // VQRSHL : Vector Saturating Rounding Shift
2680 defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, N3RegVShFrm,
2681 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
2682 "vqrshl", "s", int_arm_neon_vqrshifts, 0>;
2683 defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, N3RegVShFrm,
2684 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
2685 "vqrshl", "u", int_arm_neon_vqrshiftu, 0>;
2687 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
2688 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
2690 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
2693 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
2694 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
2697 // VSRA : Vector Shift Right and Accumulate
2698 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
2699 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
2700 // VRSRA : Vector Rounding Shift Right and Accumulate
2701 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
2702 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
2704 // VSLI : Vector Shift Left and Insert
2705 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli", NEONvsli, N2RegVShLFrm>;
2706 // VSRI : Vector Shift Right and Insert
2707 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri", NEONvsri, N2RegVShRFrm>;
2709 // Vector Absolute and Saturating Absolute.
2711 // VABS : Vector Absolute Value
2712 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
2713 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
2715 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2716 IIC_VUNAD, "vabs", "f32",
2717 v2f32, v2f32, int_arm_neon_vabs>;
2718 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2719 IIC_VUNAQ, "vabs", "f32",
2720 v4f32, v4f32, int_arm_neon_vabs>;
2722 // VQABS : Vector Saturating Absolute Value
2723 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
2724 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
2725 int_arm_neon_vqabs>;
2729 def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
2730 def vneg8 : PatFrag<(ops node:$in),
2731 (sub (bitconvert (v8i8 immAllZerosV)), node:$in)>;
2732 def vneg16 : PatFrag<(ops node:$in),
2733 (sub (bitconvert (v16i8 immAllZerosV)), node:$in)>;
2735 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
2736 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
2737 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
2738 [(set DPR:$dst, (Ty (vneg8 DPR:$src)))]>;
2739 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
2740 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
2741 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
2742 [(set QPR:$dst, (Ty (vneg16 QPR:$src)))]>;
2744 // VNEG : Vector Negate (integer)
2745 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
2746 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
2747 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
2748 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
2749 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
2750 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
2752 // VNEG : Vector Negate (floating-point)
2753 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
2754 (outs DPR:$dst), (ins DPR:$src), IIC_VUNAD,
2755 "vneg", "f32", "$dst, $src", "",
2756 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
2757 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
2758 (outs QPR:$dst), (ins QPR:$src), IIC_VUNAQ,
2759 "vneg", "f32", "$dst, $src", "",
2760 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
2762 def : Pat<(v8i8 (vneg8 DPR:$src)), (VNEGs8d DPR:$src)>;
2763 def : Pat<(v4i16 (vneg8 DPR:$src)), (VNEGs16d DPR:$src)>;
2764 def : Pat<(v2i32 (vneg8 DPR:$src)), (VNEGs32d DPR:$src)>;
2765 def : Pat<(v16i8 (vneg16 QPR:$src)), (VNEGs8q QPR:$src)>;
2766 def : Pat<(v8i16 (vneg16 QPR:$src)), (VNEGs16q QPR:$src)>;
2767 def : Pat<(v4i32 (vneg16 QPR:$src)), (VNEGs32q QPR:$src)>;
2769 // VQNEG : Vector Saturating Negate
2770 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
2771 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
2772 int_arm_neon_vqneg>;
2774 // Vector Bit Counting Operations.
2776 // VCLS : Vector Count Leading Sign Bits
2777 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
2778 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
2780 // VCLZ : Vector Count Leading Zeros
2781 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
2782 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
2784 // VCNT : Vector Count One Bits
2785 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2786 IIC_VCNTiD, "vcnt", "8",
2787 v8i8, v8i8, int_arm_neon_vcnt>;
2788 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2789 IIC_VCNTiQ, "vcnt", "8",
2790 v16i8, v16i8, int_arm_neon_vcnt>;
2792 // Vector Swap -- for disassembly only.
2793 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
2794 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
2795 "vswp", "$dst, $src", "", []>;
2796 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
2797 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
2798 "vswp", "$dst, $src", "", []>;
2800 // Vector Move Operations.
2802 // VMOV : Vector Move (Register)
2804 let neverHasSideEffects = 1 in {
2805 def VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
2806 N3RegFrm, IIC_VMOVD, "vmov", "$dst, $src", "", []>;
2807 def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
2808 N3RegFrm, IIC_VMOVD, "vmov", "$dst, $src", "", []>;
2810 // Pseudo vector move instructions for QQ and QQQQ registers. This should
2811 // be expanded after register allocation is completed.
2812 def VMOVQQ : PseudoInst<(outs QQPR:$dst), (ins QQPR:$src),
2813 NoItinerary, "${:comment} vmov\t$dst, $src", []>;
2815 def VMOVQQQQ : PseudoInst<(outs QQQQPR:$dst), (ins QQQQPR:$src),
2816 NoItinerary, "${:comment} vmov\t$dst, $src", []>;
2817 } // neverHasSideEffects
2819 // VMOV : Vector Move (Immediate)
2821 // VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
2822 def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
2823 return ARM::getVMOVImm(N, 1, *CurDAG);
2825 def vmovImm8 : PatLeaf<(build_vector), [{
2826 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
2829 // VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
2830 def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
2831 return ARM::getVMOVImm(N, 2, *CurDAG);
2833 def vmovImm16 : PatLeaf<(build_vector), [{
2834 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
2835 }], VMOV_get_imm16>;
2837 // VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
2838 def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
2839 return ARM::getVMOVImm(N, 4, *CurDAG);
2841 def vmovImm32 : PatLeaf<(build_vector), [{
2842 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
2843 }], VMOV_get_imm32>;
2845 // VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
2846 def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
2847 return ARM::getVMOVImm(N, 8, *CurDAG);
2849 def vmovImm64 : PatLeaf<(build_vector), [{
2850 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
2851 }], VMOV_get_imm64>;
2853 // Note: Some of the cmode bits in the following VMOV instructions need to
2854 // be encoded based on the immed values.
2856 let isReMaterializable = 1 in {
2857 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
2858 (ins nModImm:$SIMM), IIC_VMOVImm,
2859 "vmov", "i8", "$dst, $SIMM", "",
2860 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
2861 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
2862 (ins nModImm:$SIMM), IIC_VMOVImm,
2863 "vmov", "i8", "$dst, $SIMM", "",
2864 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
2866 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$dst),
2867 (ins nModImm:$SIMM), IIC_VMOVImm,
2868 "vmov", "i16", "$dst, $SIMM", "",
2869 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
2870 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$dst),
2871 (ins nModImm:$SIMM), IIC_VMOVImm,
2872 "vmov", "i16", "$dst, $SIMM", "",
2873 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
2875 def VMOVv2i32 : N1ModImm<1, 0b000, {0,?,?,0}, 0, 0, 0, 1, (outs DPR:$dst),
2876 (ins nModImm:$SIMM), IIC_VMOVImm,
2877 "vmov", "i32", "$dst, $SIMM", "",
2878 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
2879 def VMOVv4i32 : N1ModImm<1, 0b000, {0,?,?,0}, 0, 1, 0, 1, (outs QPR:$dst),
2880 (ins nModImm:$SIMM), IIC_VMOVImm,
2881 "vmov", "i32", "$dst, $SIMM", "",
2882 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
2884 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
2885 (ins nModImm:$SIMM), IIC_VMOVImm,
2886 "vmov", "i64", "$dst, $SIMM", "",
2887 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
2888 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
2889 (ins nModImm:$SIMM), IIC_VMOVImm,
2890 "vmov", "i64", "$dst, $SIMM", "",
2891 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
2892 } // isReMaterializable
2894 // VMOV : Vector Get Lane (move scalar to ARM core register)
2896 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
2897 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2898 IIC_VMOVSI, "vmov", "s8", "$dst, $src[$lane]",
2899 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
2901 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
2902 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2903 IIC_VMOVSI, "vmov", "s16", "$dst, $src[$lane]",
2904 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
2906 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
2907 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2908 IIC_VMOVSI, "vmov", "u8", "$dst, $src[$lane]",
2909 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
2911 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
2912 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2913 IIC_VMOVSI, "vmov", "u16", "$dst, $src[$lane]",
2914 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
2916 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
2917 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2918 IIC_VMOVSI, "vmov", "32", "$dst, $src[$lane]",
2919 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
2921 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
2922 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
2923 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2924 (DSubReg_i8_reg imm:$lane))),
2925 (SubReg_i8_lane imm:$lane))>;
2926 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
2927 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2928 (DSubReg_i16_reg imm:$lane))),
2929 (SubReg_i16_lane imm:$lane))>;
2930 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
2931 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2932 (DSubReg_i8_reg imm:$lane))),
2933 (SubReg_i8_lane imm:$lane))>;
2934 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
2935 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2936 (DSubReg_i16_reg imm:$lane))),
2937 (SubReg_i16_lane imm:$lane))>;
2938 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
2939 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
2940 (DSubReg_i32_reg imm:$lane))),
2941 (SubReg_i32_lane imm:$lane))>;
2942 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
2943 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
2944 (SSubReg_f32_reg imm:$src2))>;
2945 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
2946 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
2947 (SSubReg_f32_reg imm:$src2))>;
2948 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
2949 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2950 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
2951 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2954 // VMOV : Vector Set Lane (move ARM core register to scalar)
2956 let Constraints = "$src1 = $dst" in {
2957 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$dst),
2958 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2959 IIC_VMOVISL, "vmov", "8", "$dst[$lane], $src2",
2960 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
2961 GPR:$src2, imm:$lane))]>;
2962 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$dst),
2963 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2964 IIC_VMOVISL, "vmov", "16", "$dst[$lane], $src2",
2965 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
2966 GPR:$src2, imm:$lane))]>;
2967 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$dst),
2968 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2969 IIC_VMOVISL, "vmov", "32", "$dst[$lane], $src2",
2970 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
2971 GPR:$src2, imm:$lane))]>;
2973 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
2974 (v16i8 (INSERT_SUBREG QPR:$src1,
2975 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
2976 (DSubReg_i8_reg imm:$lane))),
2977 GPR:$src2, (SubReg_i8_lane imm:$lane))),
2978 (DSubReg_i8_reg imm:$lane)))>;
2979 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
2980 (v8i16 (INSERT_SUBREG QPR:$src1,
2981 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
2982 (DSubReg_i16_reg imm:$lane))),
2983 GPR:$src2, (SubReg_i16_lane imm:$lane))),
2984 (DSubReg_i16_reg imm:$lane)))>;
2985 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
2986 (v4i32 (INSERT_SUBREG QPR:$src1,
2987 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
2988 (DSubReg_i32_reg imm:$lane))),
2989 GPR:$src2, (SubReg_i32_lane imm:$lane))),
2990 (DSubReg_i32_reg imm:$lane)))>;
2992 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
2993 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
2994 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
2995 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
2996 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
2997 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
2999 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
3000 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
3001 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
3002 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
3004 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
3005 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
3006 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
3007 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
3008 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
3009 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
3011 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
3012 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
3013 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
3014 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
3015 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
3016 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
3018 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
3019 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3020 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
3022 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
3023 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
3024 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
3026 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
3027 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3028 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
3031 // VDUP : Vector Duplicate (from ARM core register to all elements)
3033 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
3034 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
3035 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
3036 [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
3037 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
3038 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
3039 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
3040 [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
3042 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
3043 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
3044 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
3045 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
3046 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
3047 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
3049 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
3050 IIC_VMOVIS, "vdup", "32", "$dst, $src",
3051 [(set DPR:$dst, (v2f32 (NEONvdup
3052 (f32 (bitconvert GPR:$src)))))]>;
3053 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
3054 IIC_VMOVIS, "vdup", "32", "$dst, $src",
3055 [(set QPR:$dst, (v4f32 (NEONvdup
3056 (f32 (bitconvert GPR:$src)))))]>;
3058 // VDUP : Vector Duplicate Lane (from scalar to all elements)
3060 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
3062 : NVDupLane<op19_16, 0, (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3063 IIC_VMOVD, OpcodeStr, Dt, "$dst, $src[$lane]",
3064 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
3066 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
3067 ValueType ResTy, ValueType OpTy>
3068 : NVDupLane<op19_16, 1, (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3069 IIC_VMOVD, OpcodeStr, Dt, "$dst, $src[$lane]",
3070 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src),
3073 // Inst{19-16} is partially specified depending on the element size.
3075 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8>;
3076 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16>;
3077 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32>;
3078 def VDUPLNfd : VDUPLND<{?,1,0,0}, "vdup", "32", v2f32>;
3079 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8>;
3080 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16>;
3081 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32>;
3082 def VDUPLNfq : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4f32, v2f32>;
3084 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
3085 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
3086 (DSubReg_i8_reg imm:$lane))),
3087 (SubReg_i8_lane imm:$lane)))>;
3088 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
3089 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
3090 (DSubReg_i16_reg imm:$lane))),
3091 (SubReg_i16_lane imm:$lane)))>;
3092 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
3093 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
3094 (DSubReg_i32_reg imm:$lane))),
3095 (SubReg_i32_lane imm:$lane)))>;
3096 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
3097 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
3098 (DSubReg_i32_reg imm:$lane))),
3099 (SubReg_i32_lane imm:$lane)))>;
3101 def VDUPfdf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 0, 0,
3102 (outs DPR:$dst), (ins SPR:$src),
3103 IIC_VMOVD, "vdup", "32", "$dst, ${src:lane}", "",
3104 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
3106 def VDUPfqf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 1, 0,
3107 (outs QPR:$dst), (ins SPR:$src),
3108 IIC_VMOVD, "vdup", "32", "$dst, ${src:lane}", "",
3109 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
3111 // VMOVN : Vector Narrowing Move
3112 defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVD,
3113 "vmovn", "i", int_arm_neon_vmovn>;
3114 // VQMOVN : Vector Saturating Narrowing Move
3115 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
3116 "vqmovn", "s", int_arm_neon_vqmovns>;
3117 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
3118 "vqmovn", "u", int_arm_neon_vqmovnu>;
3119 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
3120 "vqmovun", "s", int_arm_neon_vqmovnsu>;
3121 // VMOVL : Vector Lengthening Move
3122 defm VMOVLs : N2VLInt_QHS<0b01,0b10100,0,1, "vmovl", "s",
3123 int_arm_neon_vmovls>;
3124 defm VMOVLu : N2VLInt_QHS<0b11,0b10100,0,1, "vmovl", "u",
3125 int_arm_neon_vmovlu>;
3127 // Vector Conversions.
3129 // VCVT : Vector Convert Between Floating-Point and Integers
3130 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3131 v2i32, v2f32, fp_to_sint>;
3132 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3133 v2i32, v2f32, fp_to_uint>;
3134 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3135 v2f32, v2i32, sint_to_fp>;
3136 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3137 v2f32, v2i32, uint_to_fp>;
3139 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3140 v4i32, v4f32, fp_to_sint>;
3141 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3142 v4i32, v4f32, fp_to_uint>;
3143 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3144 v4f32, v4i32, sint_to_fp>;
3145 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3146 v4f32, v4i32, uint_to_fp>;
3148 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
3149 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
3150 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
3151 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
3152 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
3153 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
3154 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
3155 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
3156 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
3158 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
3159 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
3160 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
3161 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
3162 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
3163 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
3164 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
3165 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
3169 // VREV64 : Vector Reverse elements within 64-bit doublewords
3171 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3172 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
3173 (ins DPR:$src), IIC_VMOVD,
3174 OpcodeStr, Dt, "$dst, $src", "",
3175 [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
3176 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3177 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
3178 (ins QPR:$src), IIC_VMOVD,
3179 OpcodeStr, Dt, "$dst, $src", "",
3180 [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
3182 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
3183 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
3184 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
3185 def VREV64df : VREV64D<0b10, "vrev64", "32", v2f32>;
3187 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
3188 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
3189 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
3190 def VREV64qf : VREV64Q<0b10, "vrev64", "32", v4f32>;
3192 // VREV32 : Vector Reverse elements within 32-bit words
3194 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3195 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
3196 (ins DPR:$src), IIC_VMOVD,
3197 OpcodeStr, Dt, "$dst, $src", "",
3198 [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
3199 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3200 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
3201 (ins QPR:$src), IIC_VMOVD,
3202 OpcodeStr, Dt, "$dst, $src", "",
3203 [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
3205 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
3206 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
3208 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
3209 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
3211 // VREV16 : Vector Reverse elements within 16-bit halfwords
3213 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3214 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
3215 (ins DPR:$src), IIC_VMOVD,
3216 OpcodeStr, Dt, "$dst, $src", "",
3217 [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
3218 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3219 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
3220 (ins QPR:$src), IIC_VMOVD,
3221 OpcodeStr, Dt, "$dst, $src", "",
3222 [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
3224 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
3225 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
3227 // Other Vector Shuffles.
3229 // VEXT : Vector Extract
3231 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
3232 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$dst),
3233 (ins DPR:$lhs, DPR:$rhs, i32imm:$index), NVExtFrm,
3234 IIC_VEXTD, OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
3235 [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
3236 (Ty DPR:$rhs), imm:$index)))]>;
3238 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
3239 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$dst),
3240 (ins QPR:$lhs, QPR:$rhs, i32imm:$index), NVExtFrm,
3241 IIC_VEXTQ, OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
3242 [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
3243 (Ty QPR:$rhs), imm:$index)))]>;
3245 def VEXTd8 : VEXTd<"vext", "8", v8i8>;
3246 def VEXTd16 : VEXTd<"vext", "16", v4i16>;
3247 def VEXTd32 : VEXTd<"vext", "32", v2i32>;
3248 def VEXTdf : VEXTd<"vext", "32", v2f32>;
3250 def VEXTq8 : VEXTq<"vext", "8", v16i8>;
3251 def VEXTq16 : VEXTq<"vext", "16", v8i16>;
3252 def VEXTq32 : VEXTq<"vext", "32", v4i32>;
3253 def VEXTqf : VEXTq<"vext", "32", v4f32>;
3255 // VTRN : Vector Transpose
3257 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
3258 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
3259 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
3261 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
3262 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
3263 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
3265 // VUZP : Vector Unzip (Deinterleave)
3267 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
3268 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
3269 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
3271 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
3272 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
3273 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
3275 // VZIP : Vector Zip (Interleave)
3277 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
3278 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
3279 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
3281 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
3282 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
3283 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
3285 // Vector Table Lookup and Table Extension.
3287 // VTBL : Vector Table Lookup
3289 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
3290 (ins DPR:$tbl1, DPR:$src), NVTBLFrm, IIC_VTB1,
3291 "vtbl", "8", "$dst, \\{$tbl1\\}, $src", "",
3292 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
3293 let hasExtraSrcRegAllocReq = 1 in {
3295 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
3296 (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), NVTBLFrm, IIC_VTB2,
3297 "vtbl", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "",
3298 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl2
3299 DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
3301 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
3302 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), NVTBLFrm, IIC_VTB3,
3303 "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src", "",
3304 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl3
3305 DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
3307 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
3308 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src),
3310 "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src", "",
3311 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl4 DPR:$tbl1, DPR:$tbl2,
3312 DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
3313 } // hasExtraSrcRegAllocReq = 1
3315 // VTBX : Vector Table Extension
3317 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
3318 (ins DPR:$orig, DPR:$tbl1, DPR:$src), NVTBLFrm, IIC_VTBX1,
3319 "vtbx", "8", "$dst, \\{$tbl1\\}, $src", "$orig = $dst",
3320 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
3321 DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
3322 let hasExtraSrcRegAllocReq = 1 in {
3324 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
3325 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), NVTBLFrm, IIC_VTBX2,
3326 "vtbx", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "$orig = $dst",
3327 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx2
3328 DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
3330 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
3331 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src),
3332 NVTBLFrm, IIC_VTBX3,
3333 "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src", "$orig = $dst",
3334 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx3 DPR:$orig, DPR:$tbl1,
3335 DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
3337 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
3338 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), NVTBLFrm, IIC_VTBX4,
3339 "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src",
3341 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx4 DPR:$orig, DPR:$tbl1,
3342 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
3343 } // hasExtraSrcRegAllocReq = 1
3345 //===----------------------------------------------------------------------===//
3346 // NEON instructions for single-precision FP math
3347 //===----------------------------------------------------------------------===//
3349 class N2VSPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
3350 : NEONFPPat<(ResTy (OpNode SPR:$a)),
3351 (EXTRACT_SUBREG (OpTy (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)),
3355 class N3VSPat<SDNode OpNode, NeonI Inst>
3356 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
3357 (EXTRACT_SUBREG (v2f32
3358 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3360 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3364 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
3365 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
3366 (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3368 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3370 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3374 // These need separate instructions because they must use DPR_VFP2 register
3375 // class which have SPR sub-registers.
3377 // Vector Add Operations used for single-precision FP
3378 let neverHasSideEffects = 1 in
3379 def VADDfd_sfp : N3VS<0,0,0b00,0b1101,0, "vadd", "f32", v2f32, v2f32, fadd, 1>;
3380 def : N3VSPat<fadd, VADDfd_sfp>;
3382 // Vector Sub Operations used for single-precision FP
3383 let neverHasSideEffects = 1 in
3384 def VSUBfd_sfp : N3VS<0,0,0b10,0b1101,0, "vsub", "f32", v2f32, v2f32, fsub, 0>;
3385 def : N3VSPat<fsub, VSUBfd_sfp>;
3387 // Vector Multiply Operations used for single-precision FP
3388 let neverHasSideEffects = 1 in
3389 def VMULfd_sfp : N3VS<1,0,0b00,0b1101,1, "vmul", "f32", v2f32, v2f32, fmul, 1>;
3390 def : N3VSPat<fmul, VMULfd_sfp>;
3392 // Vector Multiply-Accumulate/Subtract used for single-precision FP
3393 // vml[as].f32 can cause 4-8 cycle stalls in following ASIMD instructions, so
3394 // we want to avoid them for now. e.g., alternating vmla/vadd instructions.
3396 //let neverHasSideEffects = 1 in
3397 //def VMLAfd_sfp : N3VSMulOp<0,0,0b00,0b1101,1, IIC_VMACD, "vmla", "f32",
3398 // v2f32, fmul, fadd>;
3399 //def : N3VSMulOpPat<fmul, fadd, VMLAfd_sfp>;
3401 //let neverHasSideEffects = 1 in
3402 //def VMLSfd_sfp : N3VSMulOp<0,0,0b10,0b1101,1, IIC_VMACD, "vmls", "f32",
3403 // v2f32, fmul, fsub>;
3404 //def : N3VSMulOpPat<fmul, fsub, VMLSfd_sfp>;
3406 // Vector Absolute used for single-precision FP
3407 let neverHasSideEffects = 1 in
3408 def VABSfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01110, 0, 0,
3409 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
3410 "vabs", "f32", "$dst, $src", "", []>;
3411 def : N2VSPat<fabs, f32, v2f32, VABSfd_sfp>;
3413 // Vector Negate used for single-precision FP
3414 let neverHasSideEffects = 1 in
3415 def VNEGfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
3416 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
3417 "vneg", "f32", "$dst, $src", "", []>;
3418 def : N2VSPat<fneg, f32, v2f32, VNEGfd_sfp>;
3420 // Vector Maximum used for single-precision FP
3421 let neverHasSideEffects = 1 in
3422 def VMAXfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
3423 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm, IIC_VBIND,
3424 "vmax", "f32", "$dst, $src1, $src2", "", []>;
3425 def : N3VSPat<NEONfmax, VMAXfd_sfp>;
3427 // Vector Minimum used for single-precision FP
3428 let neverHasSideEffects = 1 in
3429 def VMINfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
3430 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm, IIC_VBIND,
3431 "vmin", "f32", "$dst, $src1, $src2", "", []>;
3432 def : N3VSPat<NEONfmin, VMINfd_sfp>;
3434 // Vector Convert between single-precision FP and integer
3435 let neverHasSideEffects = 1 in
3436 def VCVTf2sd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3437 v2i32, v2f32, fp_to_sint>;
3438 def : N2VSPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
3440 let neverHasSideEffects = 1 in
3441 def VCVTf2ud_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3442 v2i32, v2f32, fp_to_uint>;
3443 def : N2VSPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
3445 let neverHasSideEffects = 1 in
3446 def VCVTs2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3447 v2f32, v2i32, sint_to_fp>;
3448 def : N2VSPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
3450 let neverHasSideEffects = 1 in
3451 def VCVTu2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3452 v2f32, v2i32, uint_to_fp>;
3453 def : N2VSPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
3455 //===----------------------------------------------------------------------===//
3456 // Non-Instruction Patterns
3457 //===----------------------------------------------------------------------===//
3460 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
3461 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
3462 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
3463 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
3464 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
3465 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
3466 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
3467 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
3468 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
3469 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
3470 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
3471 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
3472 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
3473 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
3474 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
3475 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
3476 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
3477 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
3478 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
3479 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
3480 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
3481 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
3482 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
3483 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
3484 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
3485 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
3486 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
3487 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
3488 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
3489 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
3491 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
3492 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
3493 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
3494 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
3495 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
3496 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
3497 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
3498 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
3499 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
3500 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
3501 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
3502 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
3503 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
3504 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
3505 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
3506 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
3507 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
3508 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
3509 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
3510 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
3511 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
3512 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
3513 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
3514 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
3515 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
3516 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
3517 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
3518 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
3519 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
3520 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;