1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
70 // VDUPLANE can produce a quad-register result from a double-register source,
71 // so the result is not constrained to match the source.
72 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
73 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
76 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
77 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
78 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
80 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
81 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
82 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
83 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
85 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
88 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
89 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
90 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
92 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
94 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
95 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
97 //===----------------------------------------------------------------------===//
98 // NEON operand definitions
99 //===----------------------------------------------------------------------===//
101 def h8imm : Operand<i8> {
102 let PrintMethod = "printHex8ImmOperand";
104 def h16imm : Operand<i16> {
105 let PrintMethod = "printHex16ImmOperand";
107 def h32imm : Operand<i32> {
108 let PrintMethod = "printHex32ImmOperand";
110 def h64imm : Operand<i64> {
111 let PrintMethod = "printHex64ImmOperand";
114 //===----------------------------------------------------------------------===//
115 // NEON load / store instructions
116 //===----------------------------------------------------------------------===//
118 // Use vldmia to load a Q register as a D register pair.
119 def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr), IIC_fpLoadm,
120 "vldmia", "$addr, ${dst:dregpair}",
121 [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]> {
122 let Inst{27-25} = 0b110;
123 let Inst{24} = 0; // P bit
124 let Inst{23} = 1; // U bit
126 let Inst{11-8} = 0b1011;
129 // Use vstmia to store a Q register as a D register pair.
130 def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr), IIC_fpStorem,
131 "vstmia", "$addr, ${src:dregpair}",
132 [(store (v2f64 QPR:$src), addrmode4:$addr)]> {
133 let Inst{27-25} = 0b110;
134 let Inst{24} = 0; // P bit
135 let Inst{23} = 1; // U bit
137 let Inst{11-8} = 0b1011;
140 // VLD1 : Vector Load (multiple single elements)
141 class VLD1D<bits<4> op7_4, string Dt, ValueType Ty>
142 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst), (ins addrmode6:$addr), IIC_VLD1,
143 "vld1", Dt, "\\{$dst\\}, $addr", "",
144 [(set DPR:$dst, (Ty (int_arm_neon_vld1 addrmode6:$addr)))]>;
145 class VLD1Q<bits<4> op7_4, string Dt, ValueType Ty>
146 : NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst), (ins addrmode6:$addr), IIC_VLD1,
147 "vld1", Dt, "${dst:dregpair}, $addr", "",
148 [(set QPR:$dst, (Ty (int_arm_neon_vld1 addrmode6:$addr)))]>;
150 def VLD1d8 : VLD1D<0b0000, "8", v8i8>;
151 def VLD1d16 : VLD1D<0b0100, "16", v4i16>;
152 def VLD1d32 : VLD1D<0b1000, "32", v2i32>;
153 def VLD1df : VLD1D<0b1000, "32", v2f32>;
154 def VLD1d64 : VLD1D<0b1100, "64", v1i64>;
156 def VLD1q8 : VLD1Q<0b0000, "8", v16i8>;
157 def VLD1q16 : VLD1Q<0b0100, "16", v8i16>;
158 def VLD1q32 : VLD1Q<0b1000, "32", v4i32>;
159 def VLD1qf : VLD1Q<0b1000, "32", v4f32>;
160 def VLD1q64 : VLD1Q<0b1100, "64", v2i64>;
162 // These (dreg triple/quadruple) are for disassembly only.
163 class VLD1D3<bits<4> op7_4, string Dt>
164 : NLdSt<0, 0b10, 0b0110, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
165 (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
166 "\\{$dst1, $dst2, $dst3\\}, $addr", "",
167 [/* For disassembly only; pattern left blank */]>;
168 class VLD1D4<bits<4> op7_4, string Dt>
169 : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
170 (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
171 "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "",
172 [/* For disassembly only; pattern left blank */]>;
174 def VLD1d8T : VLD1D3<0b0000, "8">;
175 def VLD1d16T : VLD1D3<0b0100, "16">;
176 def VLD1d32T : VLD1D3<0b1000, "32">;
177 //def VLD1d64T : VLD1D3<0b1100, "64">;
179 def VLD1d8Q : VLD1D4<0b0000, "8">;
180 def VLD1d16Q : VLD1D4<0b0100, "16">;
181 def VLD1d32Q : VLD1D4<0b1000, "32">;
182 //def VLD1d64Q : VLD1D4<0b1100, "64">;
185 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
187 // VLD2 : Vector Load (multiple 2-element structures)
188 class VLD2D<bits<4> op7_4, string Dt>
189 : NLdSt<0,0b10,0b1000,op7_4, (outs DPR:$dst1, DPR:$dst2),
190 (ins addrmode6:$addr), IIC_VLD2,
191 "vld2", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>;
192 class VLD2Q<bits<4> op7_4, string Dt>
193 : NLdSt<0,0b10,0b0011,op7_4,
194 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
195 (ins addrmode6:$addr), IIC_VLD2,
196 "vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
198 def VLD2d8 : VLD2D<0b0000, "8">;
199 def VLD2d16 : VLD2D<0b0100, "16">;
200 def VLD2d32 : VLD2D<0b1000, "32">;
201 def VLD2d64 : NLdSt<0,0b10,0b1010,0b1100, (outs DPR:$dst1, DPR:$dst2),
202 (ins addrmode6:$addr), IIC_VLD1,
203 "vld1", "64", "\\{$dst1, $dst2\\}, $addr", "", []>;
205 def VLD2q8 : VLD2Q<0b0000, "8">;
206 def VLD2q16 : VLD2Q<0b0100, "16">;
207 def VLD2q32 : VLD2Q<0b1000, "32">;
209 // These (double-spaced dreg pair) are for disassembly only.
210 class VLD2Ddbl<bits<4> op7_4, string Dt>
211 : NLdSt<0,0b10,0b1001,op7_4, (outs DPR:$dst1, DPR:$dst2),
212 (ins addrmode6:$addr), IIC_VLD2,
213 "vld2", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>;
215 def VLD2d8D : VLD2Ddbl<0b0000, "8">;
216 def VLD2d16D : VLD2Ddbl<0b0100, "16">;
217 def VLD2d32D : VLD2Ddbl<0b1000, "32">;
219 // VLD3 : Vector Load (multiple 3-element structures)
220 class VLD3D<bits<4> op7_4, string Dt>
221 : NLdSt<0,0b10,0b0100,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
222 (ins addrmode6:$addr), IIC_VLD3,
223 "vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
224 class VLD3WB<bits<4> op7_4, string Dt>
225 : NLdSt<0,0b10,0b0101,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
226 (ins addrmode6:$addr), IIC_VLD3,
227 "vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr",
228 "$addr.addr = $wb", []>;
230 def VLD3d8 : VLD3D<0b0000, "8">;
231 def VLD3d16 : VLD3D<0b0100, "16">;
232 def VLD3d32 : VLD3D<0b1000, "32">;
233 def VLD3d64 : NLdSt<0,0b10,0b0110,0b1100,
234 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
235 (ins addrmode6:$addr), IIC_VLD1,
236 "vld1", "64", "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
238 // vld3 to double-spaced even registers.
239 def VLD3q8a : VLD3WB<0b0000, "8">;
240 def VLD3q16a : VLD3WB<0b0100, "16">;
241 def VLD3q32a : VLD3WB<0b1000, "32">;
243 // vld3 to double-spaced odd registers.
244 def VLD3q8b : VLD3WB<0b0000, "8">;
245 def VLD3q16b : VLD3WB<0b0100, "16">;
246 def VLD3q32b : VLD3WB<0b1000, "32">;
248 // VLD4 : Vector Load (multiple 4-element structures)
249 class VLD4D<bits<4> op7_4, string Dt>
250 : NLdSt<0,0b10,0b0000,op7_4,
251 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
252 (ins addrmode6:$addr), IIC_VLD4,
253 "vld4", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
254 class VLD4WB<bits<4> op7_4, string Dt>
255 : NLdSt<0,0b10,0b0001,op7_4,
256 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
257 (ins addrmode6:$addr), IIC_VLD4,
258 "vld4", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr",
259 "$addr.addr = $wb", []>;
261 def VLD4d8 : VLD4D<0b0000, "8">;
262 def VLD4d16 : VLD4D<0b0100, "16">;
263 def VLD4d32 : VLD4D<0b1000, "32">;
264 def VLD4d64 : NLdSt<0,0b10,0b0010,0b1100,
265 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
266 (ins addrmode6:$addr), IIC_VLD1,
267 "vld1", "64", "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr",
270 // vld4 to double-spaced even registers.
271 def VLD4q8a : VLD4WB<0b0000, "8">;
272 def VLD4q16a : VLD4WB<0b0100, "16">;
273 def VLD4q32a : VLD4WB<0b1000, "32">;
275 // vld4 to double-spaced odd registers.
276 def VLD4q8b : VLD4WB<0b0000, "8">;
277 def VLD4q16b : VLD4WB<0b0100, "16">;
278 def VLD4q32b : VLD4WB<0b1000, "32">;
280 // VLD1LN : Vector Load (single element to one lane)
281 // FIXME: Not yet implemented.
283 // VLD2LN : Vector Load (single 2-element structure to one lane)
284 class VLD2LN<bits<4> op11_8, string Dt>
285 : NLdSt<1,0b10,op11_8,{?,?,?,?}, (outs DPR:$dst1, DPR:$dst2),
286 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
287 IIC_VLD2, "vld2", Dt, "\\{$dst1[$lane], $dst2[$lane]\\}, $addr",
288 "$src1 = $dst1, $src2 = $dst2", []>;
290 // vld2 to single-spaced registers.
291 def VLD2LNd8 : VLD2LN<0b0001, "8">;
292 def VLD2LNd16 : VLD2LN<0b0101, "16"> { let Inst{5} = 0; }
293 def VLD2LNd32 : VLD2LN<0b1001, "32"> { let Inst{6} = 0; }
295 // vld2 to double-spaced even registers.
296 def VLD2LNq16a: VLD2LN<0b0101, "16"> { let Inst{5} = 1; }
297 def VLD2LNq32a: VLD2LN<0b1001, "32"> { let Inst{6} = 1; }
299 // vld2 to double-spaced odd registers.
300 def VLD2LNq16b: VLD2LN<0b0101, "16"> { let Inst{5} = 1; }
301 def VLD2LNq32b: VLD2LN<0b1001, "32"> { let Inst{6} = 1; }
303 // VLD3LN : Vector Load (single 3-element structure to one lane)
304 class VLD3LN<bits<4> op11_8, string Dt>
305 : NLdSt<1,0b10,op11_8,{?,?,?,?}, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
306 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
307 nohash_imm:$lane), IIC_VLD3, "vld3", Dt,
308 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr",
309 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
311 // vld3 to single-spaced registers.
312 def VLD3LNd8 : VLD3LN<0b0010, "8"> { let Inst{4} = 0; }
313 def VLD3LNd16 : VLD3LN<0b0110, "16"> { let Inst{5-4} = 0b00; }
314 def VLD3LNd32 : VLD3LN<0b1010, "32"> { let Inst{6-4} = 0b000; }
316 // vld3 to double-spaced even registers.
317 def VLD3LNq16a: VLD3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
318 def VLD3LNq32a: VLD3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
320 // vld3 to double-spaced odd registers.
321 def VLD3LNq16b: VLD3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
322 def VLD3LNq32b: VLD3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
324 // VLD4LN : Vector Load (single 4-element structure to one lane)
325 class VLD4LN<bits<4> op11_8, string Dt>
326 : NLdSt<1,0b10,op11_8,{?,?,?,?},
327 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
328 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
329 nohash_imm:$lane), IIC_VLD4, "vld4", Dt,
330 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr",
331 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
333 // vld4 to single-spaced registers.
334 def VLD4LNd8 : VLD4LN<0b0011, "8">;
335 def VLD4LNd16 : VLD4LN<0b0111, "16"> { let Inst{5} = 0; }
336 def VLD4LNd32 : VLD4LN<0b1011, "32"> { let Inst{6} = 0; }
338 // vld4 to double-spaced even registers.
339 def VLD4LNq16a: VLD4LN<0b0111, "16"> { let Inst{5} = 1; }
340 def VLD4LNq32a: VLD4LN<0b1011, "32"> { let Inst{6} = 1; }
342 // vld4 to double-spaced odd registers.
343 def VLD4LNq16b: VLD4LN<0b0111, "16"> { let Inst{5} = 1; }
344 def VLD4LNq32b: VLD4LN<0b1011, "32"> { let Inst{6} = 1; }
346 // VLD1DUP : Vector Load (single element to all lanes)
347 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
348 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
349 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
350 // FIXME: Not yet implemented.
351 } // mayLoad = 1, hasExtraDefRegAllocReq = 1
353 // VST1 : Vector Store (multiple single elements)
354 class VST1D<bits<4> op7_4, string Dt, ValueType Ty>
355 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src), IIC_VST,
356 "vst1", Dt, "\\{$src\\}, $addr", "",
357 [(int_arm_neon_vst1 addrmode6:$addr, (Ty DPR:$src))]>;
358 class VST1Q<bits<4> op7_4, string Dt, ValueType Ty>
359 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$addr, QPR:$src), IIC_VST,
360 "vst1", Dt, "${src:dregpair}, $addr", "",
361 [(int_arm_neon_vst1 addrmode6:$addr, (Ty QPR:$src))]>;
363 let hasExtraSrcRegAllocReq = 1 in {
364 def VST1d8 : VST1D<0b0000, "8", v8i8>;
365 def VST1d16 : VST1D<0b0100, "16", v4i16>;
366 def VST1d32 : VST1D<0b1000, "32", v2i32>;
367 def VST1df : VST1D<0b1000, "32", v2f32>;
368 def VST1d64 : VST1D<0b1100, "64", v1i64>;
370 def VST1q8 : VST1Q<0b0000, "8", v16i8>;
371 def VST1q16 : VST1Q<0b0100, "16", v8i16>;
372 def VST1q32 : VST1Q<0b1000, "32", v4i32>;
373 def VST1qf : VST1Q<0b1000, "32", v4f32>;
374 def VST1q64 : VST1Q<0b1100, "64", v2i64>;
375 } // hasExtraSrcRegAllocReq
377 // These (dreg triple/quadruple) are for disassembly only.
378 class VST1D3<bits<4> op7_4, string Dt>
379 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
380 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
381 "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr", "",
382 [/* For disassembly only; pattern left blank */]>;
383 class VST1D4<bits<4> op7_4, string Dt>
384 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
385 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
386 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr", "",
387 [/* For disassembly only; pattern left blank */]>;
389 def VST1d8T : VST1D3<0b0000, "8">;
390 def VST1d16T : VST1D3<0b0100, "16">;
391 def VST1d32T : VST1D3<0b1000, "32">;
392 //def VST1d64T : VST1D3<0b1100, "64">;
394 def VST1d8Q : VST1D4<0b0000, "8">;
395 def VST1d16Q : VST1D4<0b0100, "16">;
396 def VST1d32Q : VST1D4<0b1000, "32">;
397 //def VST1d64Q : VST1D4<0b1100, "64">;
400 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
402 // VST2 : Vector Store (multiple 2-element structures)
403 class VST2D<bits<4> op7_4, string Dt>
404 : NLdSt<0,0b00,0b1000,op7_4, (outs),
405 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
406 "vst2", Dt, "\\{$src1, $src2\\}, $addr", "", []>;
407 class VST2Q<bits<4> op7_4, string Dt>
408 : NLdSt<0,0b00,0b0011,op7_4, (outs),
409 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
410 IIC_VST, "vst2", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
413 def VST2d8 : VST2D<0b0000, "8">;
414 def VST2d16 : VST2D<0b0100, "16">;
415 def VST2d32 : VST2D<0b1000, "32">;
416 def VST2d64 : NLdSt<0,0b00,0b1010,0b1100, (outs),
417 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
418 "vst1", "64", "\\{$src1, $src2\\}, $addr", "", []>;
420 def VST2q8 : VST2Q<0b0000, "8">;
421 def VST2q16 : VST2Q<0b0100, "16">;
422 def VST2q32 : VST2Q<0b1000, "32">;
424 // These (double-spaced dreg pair) are for disassembly only.
425 class VST2Ddbl<bits<4> op7_4, string Dt>
426 : NLdSt<0, 0b00, 0b1001, op7_4, (outs),
427 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
428 "vst2", Dt, "\\{$src1, $src2\\}, $addr", "", []>;
430 def VST2d8D : VST2Ddbl<0b0000, "8">;
431 def VST2d16D : VST2Ddbl<0b0100, "16">;
432 def VST2d32D : VST2Ddbl<0b1000, "32">;
434 // VST3 : Vector Store (multiple 3-element structures)
435 class VST3D<bits<4> op7_4, string Dt>
436 : NLdSt<0,0b00,0b0100,op7_4, (outs),
437 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
438 "vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>;
439 class VST3WB<bits<4> op7_4, string Dt>
440 : NLdSt<0,0b00,0b0101,op7_4, (outs GPR:$wb),
441 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
442 "vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr",
443 "$addr.addr = $wb", []>;
445 def VST3d8 : VST3D<0b0000, "8">;
446 def VST3d16 : VST3D<0b0100, "16">;
447 def VST3d32 : VST3D<0b1000, "32">;
448 def VST3d64 : NLdSt<0,0b00,0b0110,0b1100, (outs),
449 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
451 "vst1", "64", "\\{$src1, $src2, $src3\\}, $addr", "", []>;
453 // vst3 to double-spaced even registers.
454 def VST3q8a : VST3WB<0b0000, "8">;
455 def VST3q16a : VST3WB<0b0100, "16">;
456 def VST3q32a : VST3WB<0b1000, "32">;
458 // vst3 to double-spaced odd registers.
459 def VST3q8b : VST3WB<0b0000, "8">;
460 def VST3q16b : VST3WB<0b0100, "16">;
461 def VST3q32b : VST3WB<0b1000, "32">;
463 // VST4 : Vector Store (multiple 4-element structures)
464 class VST4D<bits<4> op7_4, string Dt>
465 : NLdSt<0,0b00,0b0000,op7_4, (outs),
466 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
467 IIC_VST, "vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
469 class VST4WB<bits<4> op7_4, string Dt>
470 : NLdSt<0,0b00,0b0001,op7_4, (outs GPR:$wb),
471 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
472 IIC_VST, "vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
473 "$addr.addr = $wb", []>;
475 def VST4d8 : VST4D<0b0000, "8">;
476 def VST4d16 : VST4D<0b0100, "16">;
477 def VST4d32 : VST4D<0b1000, "32">;
478 def VST4d64 : NLdSt<0,0b00,0b0010,0b1100, (outs),
479 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
481 "vst1", "64", "\\{$src1, $src2, $src3, $src4\\}, $addr",
484 // vst4 to double-spaced even registers.
485 def VST4q8a : VST4WB<0b0000, "8">;
486 def VST4q16a : VST4WB<0b0100, "16">;
487 def VST4q32a : VST4WB<0b1000, "32">;
489 // vst4 to double-spaced odd registers.
490 def VST4q8b : VST4WB<0b0000, "8">;
491 def VST4q16b : VST4WB<0b0100, "16">;
492 def VST4q32b : VST4WB<0b1000, "32">;
494 // VST1LN : Vector Store (single element from one lane)
495 // FIXME: Not yet implemented.
497 // VST2LN : Vector Store (single 2-element structure from one lane)
498 class VST2LN<bits<4> op11_8, string Dt>
499 : NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs),
500 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
501 IIC_VST, "vst2", Dt, "\\{$src1[$lane], $src2[$lane]\\}, $addr",
504 // vst2 to single-spaced registers.
505 def VST2LNd8 : VST2LN<0b0001, "8">;
506 def VST2LNd16 : VST2LN<0b0101, "16"> { let Inst{5} = 0; }
507 def VST2LNd32 : VST2LN<0b1001, "32"> { let Inst{6} = 0; }
509 // vst2 to double-spaced even registers.
510 def VST2LNq16a: VST2LN<0b0101, "16"> { let Inst{5} = 1; }
511 def VST2LNq32a: VST2LN<0b1001, "32"> { let Inst{6} = 1; }
513 // vst2 to double-spaced odd registers.
514 def VST2LNq16b: VST2LN<0b0101, "16"> { let Inst{5} = 1; }
515 def VST2LNq32b: VST2LN<0b1001, "32"> { let Inst{6} = 1; }
517 // VST3LN : Vector Store (single 3-element structure from one lane)
518 class VST3LN<bits<4> op11_8, string Dt>
519 : NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs),
520 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
521 nohash_imm:$lane), IIC_VST, "vst3", Dt,
522 "\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr", "", []>;
524 // vst3 to single-spaced registers.
525 def VST3LNd8 : VST3LN<0b0010, "8"> { let Inst{4} = 0; }
526 def VST3LNd16 : VST3LN<0b0110, "16"> { let Inst{5-4} = 0b00; }
527 def VST3LNd32 : VST3LN<0b1010, "32"> { let Inst{6-4} = 0b000; }
529 // vst3 to double-spaced even registers.
530 def VST3LNq16a: VST3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
531 def VST3LNq32a: VST3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
533 // vst3 to double-spaced odd registers.
534 def VST3LNq16b: VST3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
535 def VST3LNq32b: VST3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
537 // VST4LN : Vector Store (single 4-element structure from one lane)
538 class VST4LN<bits<4> op11_8, string Dt>
539 : NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs),
540 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
541 nohash_imm:$lane), IIC_VST, "vst4", Dt,
542 "\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr",
545 // vst4 to single-spaced registers.
546 def VST4LNd8 : VST4LN<0b0011, "8">;
547 def VST4LNd16 : VST4LN<0b0111, "16"> { let Inst{5} = 0; }
548 def VST4LNd32 : VST4LN<0b1011, "32"> { let Inst{6} = 0; }
550 // vst4 to double-spaced even registers.
551 def VST4LNq16a: VST4LN<0b0111, "16"> { let Inst{5} = 1; }
552 def VST4LNq32a: VST4LN<0b1011, "32"> { let Inst{6} = 1; }
554 // vst4 to double-spaced odd registers.
555 def VST4LNq16b: VST4LN<0b0111, "16"> { let Inst{5} = 1; }
556 def VST4LNq32b: VST4LN<0b1011, "32"> { let Inst{6} = 1; }
558 } // mayStore = 1, hasExtraSrcRegAllocReq = 1
561 //===----------------------------------------------------------------------===//
562 // NEON pattern fragments
563 //===----------------------------------------------------------------------===//
565 // Extract D sub-registers of Q registers.
566 // (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
567 def DSubReg_i8_reg : SDNodeXForm<imm, [{
568 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
570 def DSubReg_i16_reg : SDNodeXForm<imm, [{
571 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
573 def DSubReg_i32_reg : SDNodeXForm<imm, [{
574 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
576 def DSubReg_f64_reg : SDNodeXForm<imm, [{
577 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
579 def DSubReg_f64_other_reg : SDNodeXForm<imm, [{
580 return CurDAG->getTargetConstant(5 + (1 - N->getZExtValue()), MVT::i32);
583 // Extract S sub-registers of Q/D registers.
584 // (arm_ssubreg_0 is 1; arm_ssubreg_1 is 2; etc.)
585 def SSubReg_f32_reg : SDNodeXForm<imm, [{
586 return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32);
589 // Translate lane numbers from Q registers to D subregs.
590 def SubReg_i8_lane : SDNodeXForm<imm, [{
591 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
593 def SubReg_i16_lane : SDNodeXForm<imm, [{
594 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
596 def SubReg_i32_lane : SDNodeXForm<imm, [{
597 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
600 //===----------------------------------------------------------------------===//
601 // Instruction Classes
602 //===----------------------------------------------------------------------===//
604 // Basic 2-register operations: single-, double- and quad-register.
605 class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
606 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
607 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
608 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
609 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
610 IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
611 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
612 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
613 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
614 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
615 (ins DPR:$src), IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "",
616 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
617 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
618 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
619 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
620 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
621 (ins QPR:$src), IIC_VUNAQ, OpcodeStr, Dt, "$dst, $src", "",
622 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
624 // Basic 2-register intrinsics, both double- and quad-register.
625 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
626 bits<2> op17_16, bits<5> op11_7, bit op4,
627 InstrItinClass itin, string OpcodeStr, string Dt,
628 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
629 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
630 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
631 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
632 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
633 bits<2> op17_16, bits<5> op11_7, bit op4,
634 InstrItinClass itin, string OpcodeStr, string Dt,
635 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
636 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
637 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
638 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
640 // Narrow 2-register intrinsics.
641 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
642 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
643 InstrItinClass itin, string OpcodeStr, string Dt,
644 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
645 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
646 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
647 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
649 // Long 2-register intrinsics (currently only used for VMOVL).
650 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
651 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
652 InstrItinClass itin, string OpcodeStr, string Dt,
653 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
654 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$dst),
655 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
656 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
658 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
659 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
660 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
661 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
662 OpcodeStr, Dt, "$dst1, $dst2",
663 "$src1 = $dst1, $src2 = $dst2", []>;
664 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
665 InstrItinClass itin, string OpcodeStr, string Dt>
666 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
667 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$dst1, $dst2",
668 "$src1 = $dst1, $src2 = $dst2", []>;
670 // Basic 3-register operations: single-, double- and quad-register.
671 class N3VS<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
672 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
673 SDNode OpNode, bit Commutable>
674 : N3V<op24, op23, op21_20, op11_8, 0, op4,
675 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), IIC_VBIND,
676 OpcodeStr, Dt, "$dst, $src1, $src2", "", []> {
677 let isCommutable = Commutable;
680 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
681 InstrItinClass itin, string OpcodeStr, string Dt,
682 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
683 : N3V<op24, op23, op21_20, op11_8, 0, op4,
684 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
685 OpcodeStr, Dt, "$dst, $src1, $src2", "",
686 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
687 let isCommutable = Commutable;
689 // Same as N3VD but no data type.
690 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
691 InstrItinClass itin, string OpcodeStr,
692 ValueType ResTy, ValueType OpTy,
693 SDNode OpNode, bit Commutable>
694 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
695 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
696 OpcodeStr, "$dst, $src1, $src2", "",
697 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]>{
698 let isCommutable = Commutable;
700 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
701 InstrItinClass itin, string OpcodeStr, string Dt,
702 ValueType Ty, SDNode ShOp>
703 : N3V<0, 1, op21_20, op11_8, 1, 0,
704 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
705 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
707 (Ty (ShOp (Ty DPR:$src1),
708 (Ty (NEONvduplane (Ty DPR_VFP2:$src2), imm:$lane)))))]>{
709 let isCommutable = 0;
711 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
712 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
713 : N3V<0, 1, op21_20, op11_8, 1, 0,
714 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
715 IIC_VMULi16D, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
717 (Ty (ShOp (Ty DPR:$src1),
718 (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
719 let isCommutable = 0;
722 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
723 InstrItinClass itin, string OpcodeStr, string Dt,
724 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
725 : N3V<op24, op23, op21_20, op11_8, 1, op4,
726 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
727 OpcodeStr, Dt, "$dst, $src1, $src2", "",
728 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
729 let isCommutable = Commutable;
731 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
732 InstrItinClass itin, string OpcodeStr,
733 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
734 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
735 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
736 OpcodeStr, "$dst, $src1, $src2", "",
737 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]>{
738 let isCommutable = Commutable;
740 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
741 InstrItinClass itin, string OpcodeStr, string Dt,
742 ValueType ResTy, ValueType OpTy, SDNode ShOp>
743 : N3V<1, 1, op21_20, op11_8, 1, 0,
744 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
745 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
746 [(set (ResTy QPR:$dst),
747 (ResTy (ShOp (ResTy QPR:$src1),
748 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
750 let isCommutable = 0;
752 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
753 ValueType ResTy, ValueType OpTy, SDNode ShOp>
754 : N3V<1, 1, op21_20, op11_8, 1, 0,
755 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
756 IIC_VMULi16Q, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
757 [(set (ResTy QPR:$dst),
758 (ResTy (ShOp (ResTy QPR:$src1),
759 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
761 let isCommutable = 0;
764 // Basic 3-register intrinsics, both double- and quad-register.
765 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
766 InstrItinClass itin, string OpcodeStr, string Dt,
767 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
768 : N3V<op24, op23, op21_20, op11_8, 0, op4,
769 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
770 OpcodeStr, Dt, "$dst, $src1, $src2", "",
771 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
772 let isCommutable = Commutable;
774 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
775 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
776 : N3V<0, 1, op21_20, op11_8, 1, 0,
777 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
778 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
780 (Ty (IntOp (Ty DPR:$src1),
781 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
783 let isCommutable = 0;
785 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
786 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
787 : N3V<0, 1, op21_20, op11_8, 1, 0,
788 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
789 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
791 (Ty (IntOp (Ty DPR:$src1),
792 (Ty (NEONvduplane (Ty DPR_8:$src2),
794 let isCommutable = 0;
797 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
798 InstrItinClass itin, string OpcodeStr, string Dt,
799 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
800 : N3V<op24, op23, op21_20, op11_8, 1, op4,
801 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
802 OpcodeStr, Dt, "$dst, $src1, $src2", "",
803 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
804 let isCommutable = Commutable;
806 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
807 string OpcodeStr, string Dt,
808 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
809 : N3V<1, 1, op21_20, op11_8, 1, 0,
810 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
811 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
812 [(set (ResTy QPR:$dst),
813 (ResTy (IntOp (ResTy QPR:$src1),
814 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
816 let isCommutable = 0;
818 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
819 string OpcodeStr, string Dt,
820 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
821 : N3V<1, 1, op21_20, op11_8, 1, 0,
822 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
823 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
824 [(set (ResTy QPR:$dst),
825 (ResTy (IntOp (ResTy QPR:$src1),
826 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
828 let isCommutable = 0;
831 // Multiply-Add/Sub operations: single-, double- and quad-register.
832 class N3VSMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
833 InstrItinClass itin, string OpcodeStr, string Dt,
834 ValueType Ty, SDNode MulOp, SDNode OpNode>
835 : N3V<op24, op23, op21_20, op11_8, 0, op4,
836 (outs DPR_VFP2:$dst),
837 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), itin,
838 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst", []>;
840 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
841 InstrItinClass itin, string OpcodeStr, string Dt,
842 ValueType Ty, SDNode MulOp, SDNode OpNode>
843 : N3V<op24, op23, op21_20, op11_8, 0, op4,
844 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin,
845 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
846 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
847 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
848 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
849 string OpcodeStr, string Dt,
850 ValueType Ty, SDNode MulOp, SDNode ShOp>
851 : N3V<0, 1, op21_20, op11_8, 1, 0,
853 (ins DPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
854 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
856 (Ty (ShOp (Ty DPR:$src1),
857 (Ty (MulOp DPR:$src2,
858 (Ty (NEONvduplane (Ty DPR_VFP2:$src3),
860 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
861 string OpcodeStr, string Dt,
862 ValueType Ty, SDNode MulOp, SDNode ShOp>
863 : N3V<0, 1, op21_20, op11_8, 1, 0,
865 (ins DPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
866 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
868 (Ty (ShOp (Ty DPR:$src1),
869 (Ty (MulOp DPR:$src2,
870 (Ty (NEONvduplane (Ty DPR_8:$src3),
873 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
874 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
875 SDNode MulOp, SDNode OpNode>
876 : N3V<op24, op23, op21_20, op11_8, 1, op4,
877 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin,
878 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
879 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
880 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
881 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
882 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
883 SDNode MulOp, SDNode ShOp>
884 : N3V<1, 1, op21_20, op11_8, 1, 0,
886 (ins QPR:$src1, QPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
887 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
888 [(set (ResTy QPR:$dst),
889 (ResTy (ShOp (ResTy QPR:$src1),
890 (ResTy (MulOp QPR:$src2,
891 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src3),
893 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
894 string OpcodeStr, string Dt,
895 ValueType ResTy, ValueType OpTy,
896 SDNode MulOp, SDNode ShOp>
897 : N3V<1, 1, op21_20, op11_8, 1, 0,
899 (ins QPR:$src1, QPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
900 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
901 [(set (ResTy QPR:$dst),
902 (ResTy (ShOp (ResTy QPR:$src1),
903 (ResTy (MulOp QPR:$src2,
904 (ResTy (NEONvduplane (OpTy DPR_8:$src3),
907 // Neon 3-argument intrinsics, both double- and quad-register.
908 // The destination register is also used as the first source operand register.
909 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
910 InstrItinClass itin, string OpcodeStr, string Dt,
911 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
912 : N3V<op24, op23, op21_20, op11_8, 0, op4,
913 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin,
914 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
915 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
916 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
917 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
918 InstrItinClass itin, string OpcodeStr, string Dt,
919 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
920 : N3V<op24, op23, op21_20, op11_8, 1, op4,
921 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin,
922 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
923 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
924 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
926 // Neon Long 3-argument intrinsic. The destination register is
927 // a quad-register and is also used as the first source operand register.
928 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
929 InstrItinClass itin, string OpcodeStr, string Dt,
930 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
931 : N3V<op24, op23, op21_20, op11_8, 0, op4,
932 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), itin,
933 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
935 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
936 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
937 string OpcodeStr, string Dt,
938 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
939 : N3V<op24, 1, op21_20, op11_8, 1, 0,
941 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
942 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
943 [(set (ResTy QPR:$dst),
944 (ResTy (IntOp (ResTy QPR:$src1),
946 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src3),
948 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
949 InstrItinClass itin, string OpcodeStr, string Dt,
950 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
951 : N3V<op24, 1, op21_20, op11_8, 1, 0,
953 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
954 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
955 [(set (ResTy QPR:$dst),
956 (ResTy (IntOp (ResTy QPR:$src1),
958 (OpTy (NEONvduplane (OpTy DPR_8:$src3),
961 // Narrowing 3-register intrinsics.
962 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
963 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
964 Intrinsic IntOp, bit Commutable>
965 : N3V<op24, op23, op21_20, op11_8, 0, op4,
966 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VBINi4D,
967 OpcodeStr, Dt, "$dst, $src1, $src2", "",
968 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
969 let isCommutable = Commutable;
972 // Long 3-register intrinsics.
973 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
974 InstrItinClass itin, string OpcodeStr, string Dt,
975 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
976 : N3V<op24, op23, op21_20, op11_8, 0, op4,
977 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
978 OpcodeStr, Dt, "$dst, $src1, $src2", "",
979 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
980 let isCommutable = Commutable;
982 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
983 string OpcodeStr, string Dt,
984 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
985 : N3V<op24, 1, op21_20, op11_8, 1, 0,
986 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
987 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
988 [(set (ResTy QPR:$dst),
989 (ResTy (IntOp (OpTy DPR:$src1),
990 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src2),
992 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
993 InstrItinClass itin, string OpcodeStr, string Dt,
994 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
995 : N3V<op24, 1, op21_20, op11_8, 1, 0,
996 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
997 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
998 [(set (ResTy QPR:$dst),
999 (ResTy (IntOp (OpTy DPR:$src1),
1000 (OpTy (NEONvduplane (OpTy DPR_8:$src2),
1003 // Wide 3-register intrinsics.
1004 class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1005 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
1006 Intrinsic IntOp, bit Commutable>
1007 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1008 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), IIC_VSUBiD,
1009 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1010 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
1011 let isCommutable = Commutable;
1014 // Pairwise long 2-register intrinsics, both double- and quad-register.
1015 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1016 bits<2> op17_16, bits<5> op11_7, bit op4,
1017 string OpcodeStr, string Dt,
1018 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1019 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1020 (ins DPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
1021 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
1022 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1023 bits<2> op17_16, bits<5> op11_7, bit op4,
1024 string OpcodeStr, string Dt,
1025 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1026 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1027 (ins QPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
1028 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
1030 // Pairwise long 2-register accumulate intrinsics,
1031 // both double- and quad-register.
1032 // The destination register is also used as the first source operand register.
1033 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1034 bits<2> op17_16, bits<5> op11_7, bit op4,
1035 string OpcodeStr, string Dt,
1036 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1037 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
1038 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), IIC_VPALiD,
1039 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
1040 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
1041 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1042 bits<2> op17_16, bits<5> op11_7, bit op4,
1043 string OpcodeStr, string Dt,
1044 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1045 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
1046 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VPALiQ,
1047 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
1048 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
1050 // Shift by immediate,
1051 // both double- and quad-register.
1052 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1053 InstrItinClass itin, string OpcodeStr, string Dt,
1054 ValueType Ty, SDNode OpNode>
1055 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1056 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), itin,
1057 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1058 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
1059 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1060 InstrItinClass itin, string OpcodeStr, string Dt,
1061 ValueType Ty, SDNode OpNode>
1062 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1063 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin,
1064 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1065 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
1067 // Long shift by immediate.
1068 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1069 string OpcodeStr, string Dt,
1070 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1071 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1072 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VSHLiD,
1073 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1074 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
1075 (i32 imm:$SIMM))))]>;
1077 // Narrow shift by immediate.
1078 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1079 InstrItinClass itin, string OpcodeStr, string Dt,
1080 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1081 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1082 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin,
1083 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1084 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
1085 (i32 imm:$SIMM))))]>;
1087 // Shift right by immediate and accumulate,
1088 // both double- and quad-register.
1089 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1090 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1091 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1092 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), IIC_VPALiD,
1093 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1094 [(set DPR:$dst, (Ty (add DPR:$src1,
1095 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
1096 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1097 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1098 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1099 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), IIC_VPALiD,
1100 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1101 [(set QPR:$dst, (Ty (add QPR:$src1,
1102 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
1104 // Shift by immediate and insert,
1105 // both double- and quad-register.
1106 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1107 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1108 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1109 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), IIC_VSHLiD,
1110 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1111 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
1112 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1113 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1114 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1115 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), IIC_VSHLiQ,
1116 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1117 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
1119 // Convert, with fractional bits immediate,
1120 // both double- and quad-register.
1121 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1122 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1124 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1125 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VUNAD,
1126 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1127 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
1128 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1129 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1131 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1132 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), IIC_VUNAQ,
1133 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1134 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
1136 //===----------------------------------------------------------------------===//
1138 //===----------------------------------------------------------------------===//
1140 // Abbreviations used in multiclass suffixes:
1141 // Q = quarter int (8 bit) elements
1142 // H = half int (16 bit) elements
1143 // S = single int (32 bit) elements
1144 // D = double int (64 bit) elements
1146 // Neon 2-register vector operations -- for disassembly only.
1148 // First with only element sizes of 8, 16 and 32 bits:
1149 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1150 bits<5> op11_7, bit op4, string opc, string Dt,
1152 // 64-bit vector types.
1153 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
1154 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1155 opc, !strconcat(Dt, "8"), asm, "", []>;
1156 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
1157 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1158 opc, !strconcat(Dt, "16"), asm, "", []>;
1159 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
1160 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1161 opc, !strconcat(Dt, "32"), asm, "", []>;
1162 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
1163 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1164 opc, "f32", asm, "", []> {
1165 let Inst{10} = 1; // overwrite F = 1
1168 // 128-bit vector types.
1169 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
1170 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1171 opc, !strconcat(Dt, "8"), asm, "", []>;
1172 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
1173 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1174 opc, !strconcat(Dt, "16"), asm, "", []>;
1175 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
1176 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1177 opc, !strconcat(Dt, "32"), asm, "", []>;
1178 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
1179 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1180 opc, "f32", asm, "", []> {
1181 let Inst{10} = 1; // overwrite F = 1
1185 // Neon 3-register vector operations.
1187 // First with only element sizes of 8, 16 and 32 bits:
1188 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1189 InstrItinClass itinD16, InstrItinClass itinD32,
1190 InstrItinClass itinQ16, InstrItinClass itinQ32,
1191 string OpcodeStr, string Dt,
1192 SDNode OpNode, bit Commutable = 0> {
1193 // 64-bit vector types.
1194 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
1195 OpcodeStr, !strconcat(Dt, "8"),
1196 v8i8, v8i8, OpNode, Commutable>;
1197 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
1198 OpcodeStr, !strconcat(Dt, "16"),
1199 v4i16, v4i16, OpNode, Commutable>;
1200 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
1201 OpcodeStr, !strconcat(Dt, "32"),
1202 v2i32, v2i32, OpNode, Commutable>;
1204 // 128-bit vector types.
1205 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
1206 OpcodeStr, !strconcat(Dt, "8"),
1207 v16i8, v16i8, OpNode, Commutable>;
1208 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
1209 OpcodeStr, !strconcat(Dt, "16"),
1210 v8i16, v8i16, OpNode, Commutable>;
1211 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
1212 OpcodeStr, !strconcat(Dt, "32"),
1213 v4i32, v4i32, OpNode, Commutable>;
1216 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
1217 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1219 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
1221 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1222 v8i16, v4i16, ShOp>;
1223 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
1224 v4i32, v2i32, ShOp>;
1227 // ....then also with element size 64 bits:
1228 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1229 InstrItinClass itinD, InstrItinClass itinQ,
1230 string OpcodeStr, string Dt,
1231 SDNode OpNode, bit Commutable = 0>
1232 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
1233 OpcodeStr, Dt, OpNode, Commutable> {
1234 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
1235 OpcodeStr, !strconcat(Dt, "64"),
1236 v1i64, v1i64, OpNode, Commutable>;
1237 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
1238 OpcodeStr, !strconcat(Dt, "64"),
1239 v2i64, v2i64, OpNode, Commutable>;
1243 // Neon Narrowing 2-register vector intrinsics,
1244 // source operand element sizes of 16, 32 and 64 bits:
1245 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1246 bits<5> op11_7, bit op6, bit op4,
1247 InstrItinClass itin, string OpcodeStr, string Dt,
1249 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
1250 itin, OpcodeStr, !strconcat(Dt, "16"),
1251 v8i8, v8i16, IntOp>;
1252 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
1253 itin, OpcodeStr, !strconcat(Dt, "32"),
1254 v4i16, v4i32, IntOp>;
1255 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
1256 itin, OpcodeStr, !strconcat(Dt, "64"),
1257 v2i32, v2i64, IntOp>;
1261 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
1262 // source operand element sizes of 16, 32 and 64 bits:
1263 multiclass N2VLInt_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
1264 string OpcodeStr, string Dt, Intrinsic IntOp> {
1265 def v8i16 : N2VLInt<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1266 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
1267 def v4i32 : N2VLInt<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1268 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1269 def v2i64 : N2VLInt<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1270 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1274 // Neon 3-register vector intrinsics.
1276 // First with only element sizes of 16 and 32 bits:
1277 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1278 InstrItinClass itinD16, InstrItinClass itinD32,
1279 InstrItinClass itinQ16, InstrItinClass itinQ32,
1280 string OpcodeStr, string Dt,
1281 Intrinsic IntOp, bit Commutable = 0> {
1282 // 64-bit vector types.
1283 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, itinD16,
1284 OpcodeStr, !strconcat(Dt, "16"),
1285 v4i16, v4i16, IntOp, Commutable>;
1286 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, itinD32,
1287 OpcodeStr, !strconcat(Dt, "32"),
1288 v2i32, v2i32, IntOp, Commutable>;
1290 // 128-bit vector types.
1291 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, itinQ16,
1292 OpcodeStr, !strconcat(Dt, "16"),
1293 v8i16, v8i16, IntOp, Commutable>;
1294 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, itinQ32,
1295 OpcodeStr, !strconcat(Dt, "32"),
1296 v4i32, v4i32, IntOp, Commutable>;
1299 multiclass N3VIntSL_HS<bits<4> op11_8,
1300 InstrItinClass itinD16, InstrItinClass itinD32,
1301 InstrItinClass itinQ16, InstrItinClass itinQ32,
1302 string OpcodeStr, string Dt, Intrinsic IntOp> {
1303 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
1304 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
1305 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
1306 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
1307 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
1308 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
1309 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
1310 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
1313 // ....then also with element size of 8 bits:
1314 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1315 InstrItinClass itinD16, InstrItinClass itinD32,
1316 InstrItinClass itinQ16, InstrItinClass itinQ32,
1317 string OpcodeStr, string Dt,
1318 Intrinsic IntOp, bit Commutable = 0>
1319 : N3VInt_HS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
1320 OpcodeStr, Dt, IntOp, Commutable> {
1321 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, itinD16,
1322 OpcodeStr, !strconcat(Dt, "8"),
1323 v8i8, v8i8, IntOp, Commutable>;
1324 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, itinQ16,
1325 OpcodeStr, !strconcat(Dt, "8"),
1326 v16i8, v16i8, IntOp, Commutable>;
1329 // ....then also with element size of 64 bits:
1330 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1331 InstrItinClass itinD16, InstrItinClass itinD32,
1332 InstrItinClass itinQ16, InstrItinClass itinQ32,
1333 string OpcodeStr, string Dt,
1334 Intrinsic IntOp, bit Commutable = 0>
1335 : N3VInt_QHS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
1336 OpcodeStr, Dt, IntOp, Commutable> {
1337 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, itinD32,
1338 OpcodeStr, !strconcat(Dt, "64"),
1339 v1i64, v1i64, IntOp, Commutable>;
1340 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, itinQ32,
1341 OpcodeStr, !strconcat(Dt, "64"),
1342 v2i64, v2i64, IntOp, Commutable>;
1346 // Neon Narrowing 3-register vector intrinsics,
1347 // source operand element sizes of 16, 32 and 64 bits:
1348 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1349 string OpcodeStr, string Dt,
1350 Intrinsic IntOp, bit Commutable = 0> {
1351 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
1352 OpcodeStr, !strconcat(Dt, "16"),
1353 v8i8, v8i16, IntOp, Commutable>;
1354 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
1355 OpcodeStr, !strconcat(Dt, "32"),
1356 v4i16, v4i32, IntOp, Commutable>;
1357 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
1358 OpcodeStr, !strconcat(Dt, "64"),
1359 v2i32, v2i64, IntOp, Commutable>;
1363 // Neon Long 3-register vector intrinsics.
1365 // First with only element sizes of 16 and 32 bits:
1366 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1367 InstrItinClass itin, string OpcodeStr, string Dt,
1368 Intrinsic IntOp, bit Commutable = 0> {
1369 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin,
1370 OpcodeStr, !strconcat(Dt, "16"),
1371 v4i32, v4i16, IntOp, Commutable>;
1372 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin,
1373 OpcodeStr, !strconcat(Dt, "32"),
1374 v2i64, v2i32, IntOp, Commutable>;
1377 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
1378 InstrItinClass itin, string OpcodeStr, string Dt,
1380 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
1381 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1382 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
1383 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1386 // ....then also with element size of 8 bits:
1387 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1388 InstrItinClass itin, string OpcodeStr, string Dt,
1389 Intrinsic IntOp, bit Commutable = 0>
1390 : N3VLInt_HS<op24, op23, op11_8, op4, itin, OpcodeStr, Dt,
1391 IntOp, Commutable> {
1392 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin,
1393 OpcodeStr, !strconcat(Dt, "8"),
1394 v8i16, v8i8, IntOp, Commutable>;
1398 // Neon Wide 3-register vector intrinsics,
1399 // source operand element sizes of 8, 16 and 32 bits:
1400 multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1401 string OpcodeStr, string Dt,
1402 Intrinsic IntOp, bit Commutable = 0> {
1403 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4,
1404 OpcodeStr, !strconcat(Dt, "8"),
1405 v8i16, v8i8, IntOp, Commutable>;
1406 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4,
1407 OpcodeStr, !strconcat(Dt, "16"),
1408 v4i32, v4i16, IntOp, Commutable>;
1409 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4,
1410 OpcodeStr, !strconcat(Dt, "32"),
1411 v2i64, v2i32, IntOp, Commutable>;
1415 // Neon Multiply-Op vector operations,
1416 // element sizes of 8, 16 and 32 bits:
1417 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1418 InstrItinClass itinD16, InstrItinClass itinD32,
1419 InstrItinClass itinQ16, InstrItinClass itinQ32,
1420 string OpcodeStr, string Dt, SDNode OpNode> {
1421 // 64-bit vector types.
1422 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
1423 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
1424 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
1425 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
1426 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
1427 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
1429 // 128-bit vector types.
1430 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
1431 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
1432 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
1433 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
1434 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
1435 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
1438 multiclass N3VMulOpSL_HS<bits<4> op11_8,
1439 InstrItinClass itinD16, InstrItinClass itinD32,
1440 InstrItinClass itinQ16, InstrItinClass itinQ32,
1441 string OpcodeStr, string Dt, SDNode ShOp> {
1442 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
1443 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
1444 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
1445 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
1446 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
1447 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
1449 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
1450 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
1454 // Neon 3-argument intrinsics,
1455 // element sizes of 8, 16 and 32 bits:
1456 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1457 string OpcodeStr, string Dt, Intrinsic IntOp> {
1458 // 64-bit vector types.
1459 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16D,
1460 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
1461 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
1462 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
1463 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32D,
1464 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
1466 // 128-bit vector types.
1467 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16Q,
1468 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
1469 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16Q,
1470 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
1471 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32Q,
1472 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
1476 // Neon Long 3-argument intrinsics.
1478 // First with only element sizes of 16 and 32 bits:
1479 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1480 string OpcodeStr, string Dt, Intrinsic IntOp> {
1481 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
1482 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1483 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi16D,
1484 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1487 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
1488 string OpcodeStr, string Dt, Intrinsic IntOp> {
1489 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
1490 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
1491 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
1492 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1495 // ....then also with element size of 8 bits:
1496 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1497 string OpcodeStr, string Dt, Intrinsic IntOp>
1498 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, Dt, IntOp> {
1499 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16D,
1500 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
1504 // Neon 2-register vector intrinsics,
1505 // element sizes of 8, 16 and 32 bits:
1506 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1507 bits<5> op11_7, bit op4,
1508 InstrItinClass itinD, InstrItinClass itinQ,
1509 string OpcodeStr, string Dt, Intrinsic IntOp> {
1510 // 64-bit vector types.
1511 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1512 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
1513 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1514 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
1515 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1516 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
1518 // 128-bit vector types.
1519 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1520 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
1521 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1522 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
1523 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1524 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
1528 // Neon Pairwise long 2-register intrinsics,
1529 // element sizes of 8, 16 and 32 bits:
1530 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1531 bits<5> op11_7, bit op4,
1532 string OpcodeStr, string Dt, Intrinsic IntOp> {
1533 // 64-bit vector types.
1534 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1535 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
1536 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1537 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
1538 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1539 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
1541 // 128-bit vector types.
1542 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1543 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
1544 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1545 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
1546 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1547 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
1551 // Neon Pairwise long 2-register accumulate intrinsics,
1552 // element sizes of 8, 16 and 32 bits:
1553 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1554 bits<5> op11_7, bit op4,
1555 string OpcodeStr, string Dt, Intrinsic IntOp> {
1556 // 64-bit vector types.
1557 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1558 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
1559 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1560 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
1561 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1562 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
1564 // 128-bit vector types.
1565 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1566 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
1567 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1568 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
1569 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1570 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
1574 // Neon 2-register vector shift by immediate,
1575 // element sizes of 8, 16, 32 and 64 bits:
1576 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1577 InstrItinClass itin, string OpcodeStr, string Dt,
1579 // 64-bit vector types.
1580 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
1581 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
1582 let Inst{21-19} = 0b001; // imm6 = 001xxx
1584 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
1585 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
1586 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1588 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
1589 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
1590 let Inst{21} = 0b1; // imm6 = 1xxxxx
1592 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, itin,
1593 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
1596 // 128-bit vector types.
1597 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
1598 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
1599 let Inst{21-19} = 0b001; // imm6 = 001xxx
1601 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
1602 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
1603 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1605 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
1606 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
1607 let Inst{21} = 0b1; // imm6 = 1xxxxx
1609 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, itin,
1610 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
1615 // Neon Shift-Accumulate vector operations,
1616 // element sizes of 8, 16, 32 and 64 bits:
1617 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1618 string OpcodeStr, string Dt, SDNode ShOp> {
1619 // 64-bit vector types.
1620 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1621 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
1622 let Inst{21-19} = 0b001; // imm6 = 001xxx
1624 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1625 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
1626 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1628 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1629 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
1630 let Inst{21} = 0b1; // imm6 = 1xxxxx
1632 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4,
1633 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
1636 // 128-bit vector types.
1637 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1638 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
1639 let Inst{21-19} = 0b001; // imm6 = 001xxx
1641 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1642 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
1643 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1645 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1646 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
1647 let Inst{21} = 0b1; // imm6 = 1xxxxx
1649 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4,
1650 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
1655 // Neon Shift-Insert vector operations,
1656 // element sizes of 8, 16, 32 and 64 bits:
1657 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1658 string OpcodeStr, SDNode ShOp> {
1659 // 64-bit vector types.
1660 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4,
1661 OpcodeStr, "8", v8i8, ShOp> {
1662 let Inst{21-19} = 0b001; // imm6 = 001xxx
1664 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4,
1665 OpcodeStr, "16", v4i16, ShOp> {
1666 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1668 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4,
1669 OpcodeStr, "32", v2i32, ShOp> {
1670 let Inst{21} = 0b1; // imm6 = 1xxxxx
1672 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4,
1673 OpcodeStr, "64", v1i64, ShOp>;
1676 // 128-bit vector types.
1677 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4,
1678 OpcodeStr, "8", v16i8, ShOp> {
1679 let Inst{21-19} = 0b001; // imm6 = 001xxx
1681 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4,
1682 OpcodeStr, "16", v8i16, ShOp> {
1683 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1685 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4,
1686 OpcodeStr, "32", v4i32, ShOp> {
1687 let Inst{21} = 0b1; // imm6 = 1xxxxx
1689 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4,
1690 OpcodeStr, "64", v2i64, ShOp>;
1694 // Neon Shift Long operations,
1695 // element sizes of 8, 16, 32 bits:
1696 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
1697 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
1698 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1699 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
1700 let Inst{21-19} = 0b001; // imm6 = 001xxx
1702 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1703 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
1704 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1706 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1707 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
1708 let Inst{21} = 0b1; // imm6 = 1xxxxx
1712 // Neon Shift Narrow operations,
1713 // element sizes of 16, 32, 64 bits:
1714 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
1715 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
1717 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1718 OpcodeStr, !strconcat(Dt, "16"), v8i8, v8i16, OpNode> {
1719 let Inst{21-19} = 0b001; // imm6 = 001xxx
1721 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1722 OpcodeStr, !strconcat(Dt, "32"), v4i16, v4i32, OpNode> {
1723 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1725 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1726 OpcodeStr, !strconcat(Dt, "64"), v2i32, v2i64, OpNode> {
1727 let Inst{21} = 0b1; // imm6 = 1xxxxx
1731 //===----------------------------------------------------------------------===//
1732 // Instruction Definitions.
1733 //===----------------------------------------------------------------------===//
1735 // Vector Add Operations.
1737 // VADD : Vector Add (integer and floating-point)
1738 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
1740 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
1741 v2f32, v2f32, fadd, 1>;
1742 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
1743 v4f32, v4f32, fadd, 1>;
1744 // VADDL : Vector Add Long (Q = D + D)
1745 defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, IIC_VSHLiD, "vaddl", "s",
1746 int_arm_neon_vaddls, 1>;
1747 defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, IIC_VSHLiD, "vaddl", "u",
1748 int_arm_neon_vaddlu, 1>;
1749 // VADDW : Vector Add Wide (Q = Q + D)
1750 defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw", "s", int_arm_neon_vaddws, 0>;
1751 defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw", "u", int_arm_neon_vaddwu, 0>;
1752 // VHADD : Vector Halving Add
1753 defm VHADDs : N3VInt_QHS<0,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1754 IIC_VBINi4Q, "vhadd", "s", int_arm_neon_vhadds, 1>;
1755 defm VHADDu : N3VInt_QHS<1,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1756 IIC_VBINi4Q, "vhadd", "u", int_arm_neon_vhaddu, 1>;
1757 // VRHADD : Vector Rounding Halving Add
1758 defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1759 IIC_VBINi4Q, "vrhadd", "s", int_arm_neon_vrhadds, 1>;
1760 defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1761 IIC_VBINi4Q, "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
1762 // VQADD : Vector Saturating Add
1763 defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1764 IIC_VBINi4Q, "vqadd", "s", int_arm_neon_vqadds, 1>;
1765 defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1766 IIC_VBINi4Q, "vqadd", "u", int_arm_neon_vqaddu, 1>;
1767 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
1768 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
1769 int_arm_neon_vaddhn, 1>;
1770 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
1771 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
1772 int_arm_neon_vraddhn, 1>;
1774 // Vector Multiply Operations.
1776 // VMUL : Vector Multiply (integer, polynomial and floating-point)
1777 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
1778 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
1779 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16D, "vmul", "p8",
1780 v8i8, v8i8, int_arm_neon_vmulp, 1>;
1781 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16Q, "vmul", "p8",
1782 v16i8, v16i8, int_arm_neon_vmulp, 1>;
1783 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VBIND, "vmul", "f32",
1784 v2f32, v2f32, fmul, 1>;
1785 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VBINQ, "vmul", "f32",
1786 v4f32, v4f32, fmul, 1>;
1787 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
1788 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
1789 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
1792 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
1793 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
1794 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
1795 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1796 (DSubReg_i16_reg imm:$lane))),
1797 (SubReg_i16_lane imm:$lane)))>;
1798 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
1799 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
1800 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
1801 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1802 (DSubReg_i32_reg imm:$lane))),
1803 (SubReg_i32_lane imm:$lane)))>;
1804 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
1805 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
1806 (v4f32 (VMULslfq (v4f32 QPR:$src1),
1807 (v2f32 (EXTRACT_SUBREG QPR:$src2,
1808 (DSubReg_i32_reg imm:$lane))),
1809 (SubReg_i32_lane imm:$lane)))>;
1811 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
1812 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
1813 IIC_VMULi16Q, IIC_VMULi32Q,
1814 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
1815 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
1816 IIC_VMULi16Q, IIC_VMULi32Q,
1817 "vqdmulh", "s", int_arm_neon_vqdmulh>;
1818 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
1819 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
1821 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
1822 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1823 (DSubReg_i16_reg imm:$lane))),
1824 (SubReg_i16_lane imm:$lane)))>;
1825 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
1826 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
1828 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
1829 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1830 (DSubReg_i32_reg imm:$lane))),
1831 (SubReg_i32_lane imm:$lane)))>;
1833 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
1834 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
1835 IIC_VMULi16Q, IIC_VMULi32Q,
1836 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
1837 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
1838 IIC_VMULi16Q, IIC_VMULi32Q,
1839 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
1840 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
1841 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
1843 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
1844 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1845 (DSubReg_i16_reg imm:$lane))),
1846 (SubReg_i16_lane imm:$lane)))>;
1847 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
1848 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
1850 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
1851 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1852 (DSubReg_i32_reg imm:$lane))),
1853 (SubReg_i32_lane imm:$lane)))>;
1855 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
1856 defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, IIC_VMULi16D, "vmull", "s",
1857 int_arm_neon_vmulls, 1>;
1858 defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, IIC_VMULi16D, "vmull", "u",
1859 int_arm_neon_vmullu, 1>;
1860 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
1861 v8i16, v8i8, int_arm_neon_vmullp, 1>;
1862 defm VMULLsls : N3VLIntSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s",
1863 int_arm_neon_vmulls>;
1864 defm VMULLslu : N3VLIntSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u",
1865 int_arm_neon_vmullu>;
1867 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
1868 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, "vqdmull", "s",
1869 int_arm_neon_vqdmull, 1>;
1870 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D, "vqdmull", "s",
1871 int_arm_neon_vqdmull>;
1873 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
1875 // VMLA : Vector Multiply Accumulate (integer and floating-point)
1876 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
1877 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
1878 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
1880 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
1882 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
1883 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
1884 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
1886 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
1887 v4f32, v2f32, fmul, fadd>;
1889 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
1890 (mul (v8i16 QPR:$src2),
1891 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
1892 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
1893 (v4i16 (EXTRACT_SUBREG QPR:$src3,
1894 (DSubReg_i16_reg imm:$lane))),
1895 (SubReg_i16_lane imm:$lane)))>;
1897 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
1898 (mul (v4i32 QPR:$src2),
1899 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
1900 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
1901 (v2i32 (EXTRACT_SUBREG QPR:$src3,
1902 (DSubReg_i32_reg imm:$lane))),
1903 (SubReg_i32_lane imm:$lane)))>;
1905 def : Pat<(v4f32 (fadd (v4f32 QPR:$src1),
1906 (fmul (v4f32 QPR:$src2),
1907 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
1908 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
1910 (v2f32 (EXTRACT_SUBREG QPR:$src3,
1911 (DSubReg_i32_reg imm:$lane))),
1912 (SubReg_i32_lane imm:$lane)))>;
1914 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
1915 defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal", "s", int_arm_neon_vmlals>;
1916 defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal", "u", int_arm_neon_vmlalu>;
1918 defm VMLALsls : N3VLInt3SL_HS<0, 0b0010, "vmlal", "s", int_arm_neon_vmlals>;
1919 defm VMLALslu : N3VLInt3SL_HS<1, 0b0010, "vmlal", "u", int_arm_neon_vmlalu>;
1921 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
1922 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal", "s",
1923 int_arm_neon_vqdmlal>;
1924 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
1926 // VMLS : Vector Multiply Subtract (integer and floating-point)
1927 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
1928 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
1929 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
1931 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
1933 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
1934 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
1935 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
1937 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
1938 v4f32, v2f32, fmul, fsub>;
1940 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
1941 (mul (v8i16 QPR:$src2),
1942 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
1943 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
1944 (v4i16 (EXTRACT_SUBREG QPR:$src3,
1945 (DSubReg_i16_reg imm:$lane))),
1946 (SubReg_i16_lane imm:$lane)))>;
1948 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
1949 (mul (v4i32 QPR:$src2),
1950 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
1951 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
1952 (v2i32 (EXTRACT_SUBREG QPR:$src3,
1953 (DSubReg_i32_reg imm:$lane))),
1954 (SubReg_i32_lane imm:$lane)))>;
1956 def : Pat<(v4f32 (fsub (v4f32 QPR:$src1),
1957 (fmul (v4f32 QPR:$src2),
1958 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
1959 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
1960 (v2f32 (EXTRACT_SUBREG QPR:$src3,
1961 (DSubReg_i32_reg imm:$lane))),
1962 (SubReg_i32_lane imm:$lane)))>;
1964 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
1965 defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl", "s", int_arm_neon_vmlsls>;
1966 defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl", "u", int_arm_neon_vmlslu>;
1968 defm VMLSLsls : N3VLInt3SL_HS<0, 0b0110, "vmlsl", "s", int_arm_neon_vmlsls>;
1969 defm VMLSLslu : N3VLInt3SL_HS<1, 0b0110, "vmlsl", "u", int_arm_neon_vmlslu>;
1971 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
1972 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl", "s",
1973 int_arm_neon_vqdmlsl>;
1974 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
1976 // Vector Subtract Operations.
1978 // VSUB : Vector Subtract (integer and floating-point)
1979 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
1980 "vsub", "i", sub, 0>;
1981 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
1982 v2f32, v2f32, fsub, 0>;
1983 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
1984 v4f32, v4f32, fsub, 0>;
1985 // VSUBL : Vector Subtract Long (Q = D - D)
1986 defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, IIC_VSHLiD, "vsubl", "s",
1987 int_arm_neon_vsubls, 1>;
1988 defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, IIC_VSHLiD, "vsubl", "u",
1989 int_arm_neon_vsublu, 1>;
1990 // VSUBW : Vector Subtract Wide (Q = Q - D)
1991 defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw", "s", int_arm_neon_vsubws, 0>;
1992 defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw", "u", int_arm_neon_vsubwu, 0>;
1993 // VHSUB : Vector Halving Subtract
1994 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D,
1995 IIC_VBINi4Q, IIC_VBINi4Q,
1996 "vhsub", "s", int_arm_neon_vhsubs, 0>;
1997 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D,
1998 IIC_VBINi4Q, IIC_VBINi4Q,
1999 "vhsub", "u", int_arm_neon_vhsubu, 0>;
2000 // VQSUB : Vector Saturing Subtract
2001 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D,
2002 IIC_VBINi4Q, IIC_VBINi4Q,
2003 "vqsub", "s", int_arm_neon_vqsubs, 0>;
2004 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D,
2005 IIC_VBINi4Q, IIC_VBINi4Q,
2006 "vqsub", "u", int_arm_neon_vqsubu, 0>;
2007 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
2008 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
2009 int_arm_neon_vsubhn, 0>;
2010 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
2011 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
2012 int_arm_neon_vrsubhn, 0>;
2014 // Vector Comparisons.
2016 // VCEQ : Vector Compare Equal
2017 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2018 IIC_VBINi4Q, "vceq", "i", NEONvceq, 1>;
2019 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
2021 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
2023 // For disassembly only.
2024 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
2027 // VCGE : Vector Compare Greater Than or Equal
2028 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2029 IIC_VBINi4Q, "vcge", "s", NEONvcge, 0>;
2030 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2031 IIC_VBINi4Q, "vcge", "u", NEONvcgeu, 0>;
2032 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32",
2033 v2i32, v2f32, NEONvcge, 0>;
2034 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
2036 // For disassembly only.
2037 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
2039 // For disassembly only.
2040 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
2043 // VCGT : Vector Compare Greater Than
2044 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2045 IIC_VBINi4Q, "vcgt", "s", NEONvcgt, 0>;
2046 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2047 IIC_VBINi4Q, "vcgt", "u", NEONvcgtu, 0>;
2048 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
2050 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
2052 // For disassembly only.
2053 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
2055 // For disassembly only.
2056 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
2059 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
2060 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, IIC_VBIND, "vacge", "f32",
2061 v2i32, v2f32, int_arm_neon_vacged, 0>;
2062 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, IIC_VBINQ, "vacge", "f32",
2063 v4i32, v4f32, int_arm_neon_vacgeq, 0>;
2064 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
2065 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, IIC_VBIND, "vacgt", "f32",
2066 v2i32, v2f32, int_arm_neon_vacgtd, 0>;
2067 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, IIC_VBINQ, "vacgt", "f32",
2068 v4i32, v4f32, int_arm_neon_vacgtq, 0>;
2069 // VTST : Vector Test Bits
2070 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2071 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
2073 // Vector Bitwise Operations.
2075 // VAND : Vector Bitwise AND
2076 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
2077 v2i32, v2i32, and, 1>;
2078 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
2079 v4i32, v4i32, and, 1>;
2081 // VEOR : Vector Bitwise Exclusive OR
2082 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
2083 v2i32, v2i32, xor, 1>;
2084 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
2085 v4i32, v4i32, xor, 1>;
2087 // VORR : Vector Bitwise OR
2088 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
2089 v2i32, v2i32, or, 1>;
2090 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
2091 v4i32, v4i32, or, 1>;
2093 // VBIC : Vector Bitwise Bit Clear (AND NOT)
2094 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2095 (ins DPR:$src1, DPR:$src2), IIC_VBINiD,
2096 "vbic", "$dst, $src1, $src2", "",
2097 [(set DPR:$dst, (v2i32 (and DPR:$src1,
2098 (vnot_conv DPR:$src2))))]>;
2099 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2100 (ins QPR:$src1, QPR:$src2), IIC_VBINiQ,
2101 "vbic", "$dst, $src1, $src2", "",
2102 [(set QPR:$dst, (v4i32 (and QPR:$src1,
2103 (vnot_conv QPR:$src2))))]>;
2105 // VORN : Vector Bitwise OR NOT
2106 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
2107 (ins DPR:$src1, DPR:$src2), IIC_VBINiD,
2108 "vorn", "$dst, $src1, $src2", "",
2109 [(set DPR:$dst, (v2i32 (or DPR:$src1,
2110 (vnot_conv DPR:$src2))))]>;
2111 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
2112 (ins QPR:$src1, QPR:$src2), IIC_VBINiQ,
2113 "vorn", "$dst, $src1, $src2", "",
2114 [(set QPR:$dst, (v4i32 (or QPR:$src1,
2115 (vnot_conv QPR:$src2))))]>;
2117 // VMVN : Vector Bitwise NOT
2118 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
2119 (outs DPR:$dst), (ins DPR:$src), IIC_VSHLiD,
2120 "vmvn", "$dst, $src", "",
2121 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>;
2122 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
2123 (outs QPR:$dst), (ins QPR:$src), IIC_VSHLiD,
2124 "vmvn", "$dst, $src", "",
2125 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>;
2126 def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>;
2127 def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>;
2129 // VBSL : Vector Bitwise Select
2130 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2131 (ins DPR:$src1, DPR:$src2, DPR:$src3), IIC_VCNTiD,
2132 "vbsl", "$dst, $src2, $src3", "$src1 = $dst",
2134 (v2i32 (or (and DPR:$src2, DPR:$src1),
2135 (and DPR:$src3, (vnot_conv DPR:$src1)))))]>;
2136 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2137 (ins QPR:$src1, QPR:$src2, QPR:$src3), IIC_VCNTiQ,
2138 "vbsl", "$dst, $src2, $src3", "$src1 = $dst",
2140 (v4i32 (or (and QPR:$src2, QPR:$src1),
2141 (and QPR:$src3, (vnot_conv QPR:$src1)))))]>;
2143 // VBIF : Vector Bitwise Insert if False
2144 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
2145 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
2146 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
2147 IIC_VBINiD, "vbif", "$dst, $src2, $src3", "$src1 = $dst",
2148 [/* For disassembly only; pattern left blank */]>;
2149 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
2150 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
2151 IIC_VBINiQ, "vbif", "$dst, $src2, $src3", "$src1 = $dst",
2152 [/* For disassembly only; pattern left blank */]>;
2154 // VBIT : Vector Bitwise Insert if True
2155 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
2156 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
2157 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
2158 IIC_VBINiD, "vbit", "$dst, $src2, $src3", "$src1 = $dst",
2159 [/* For disassembly only; pattern left blank */]>;
2160 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
2161 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
2162 IIC_VBINiQ, "vbit", "$dst, $src2, $src3", "$src1 = $dst",
2163 [/* For disassembly only; pattern left blank */]>;
2165 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
2166 // for equivalent operations with different register constraints; it just
2169 // Vector Absolute Differences.
2171 // VABD : Vector Absolute Difference
2172 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D,
2173 IIC_VBINi4Q, IIC_VBINi4Q,
2174 "vabd", "s", int_arm_neon_vabds, 0>;
2175 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D,
2176 IIC_VBINi4Q, IIC_VBINi4Q,
2177 "vabd", "u", int_arm_neon_vabdu, 0>;
2178 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, IIC_VBIND,
2179 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 0>;
2180 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, IIC_VBINQ,
2181 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 0>;
2183 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
2184 defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, IIC_VBINi4Q,
2185 "vabdl", "s", int_arm_neon_vabdls, 0>;
2186 defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, IIC_VBINi4Q,
2187 "vabdl", "u", int_arm_neon_vabdlu, 0>;
2189 // VABA : Vector Absolute Difference and Accumulate
2190 defm VABAs : N3VInt3_QHS<0,0,0b0111,1, "vaba", "s", int_arm_neon_vabas>;
2191 defm VABAu : N3VInt3_QHS<1,0,0b0111,1, "vaba", "u", int_arm_neon_vabau>;
2193 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
2194 defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal", "s", int_arm_neon_vabals>;
2195 defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal", "u", int_arm_neon_vabalu>;
2197 // Vector Maximum and Minimum.
2199 // VMAX : Vector Maximum
2200 defm VMAXs : N3VInt_QHS<0,0,0b0110,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2201 IIC_VBINi4Q, "vmax", "s", int_arm_neon_vmaxs, 1>;
2202 defm VMAXu : N3VInt_QHS<1,0,0b0110,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2203 IIC_VBINi4Q, "vmax", "u", int_arm_neon_vmaxu, 1>;
2204 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, IIC_VBIND, "vmax", "f32",
2205 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
2206 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, IIC_VBINQ, "vmax", "f32",
2207 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
2209 // VMIN : Vector Minimum
2210 defm VMINs : N3VInt_QHS<0,0,0b0110,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2211 IIC_VBINi4Q, "vmin", "s", int_arm_neon_vmins, 1>;
2212 defm VMINu : N3VInt_QHS<1,0,0b0110,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2213 IIC_VBINi4Q, "vmin", "u", int_arm_neon_vminu, 1>;
2214 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, IIC_VBIND, "vmin", "f32",
2215 v2f32, v2f32, int_arm_neon_vmins, 1>;
2216 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, IIC_VBINQ, "vmin", "f32",
2217 v4f32, v4f32, int_arm_neon_vmins, 1>;
2219 // Vector Pairwise Operations.
2221 // VPADD : Vector Pairwise Add
2222 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, IIC_VBINiD, "vpadd", "i8",
2223 v8i8, v8i8, int_arm_neon_vpadd, 0>;
2224 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, IIC_VBINiD, "vpadd", "i16",
2225 v4i16, v4i16, int_arm_neon_vpadd, 0>;
2226 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, IIC_VBINiD, "vpadd", "i32",
2227 v2i32, v2i32, int_arm_neon_vpadd, 0>;
2228 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, IIC_VBIND, "vpadd", "f32",
2229 v2f32, v2f32, int_arm_neon_vpadd, 0>;
2231 // VPADDL : Vector Pairwise Add Long
2232 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
2233 int_arm_neon_vpaddls>;
2234 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
2235 int_arm_neon_vpaddlu>;
2237 // VPADAL : Vector Pairwise Add and Accumulate Long
2238 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
2239 int_arm_neon_vpadals>;
2240 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
2241 int_arm_neon_vpadalu>;
2243 // VPMAX : Vector Pairwise Maximum
2244 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax", "s8",
2245 v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
2246 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax", "s16",
2247 v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
2248 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax", "s32",
2249 v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
2250 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax", "u8",
2251 v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
2252 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax", "u16",
2253 v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
2254 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax", "u32",
2255 v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
2256 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, IIC_VBINi4D, "vpmax", "f32",
2257 v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
2259 // VPMIN : Vector Pairwise Minimum
2260 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin", "s8",
2261 v8i8, v8i8, int_arm_neon_vpmins, 0>;
2262 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin", "s16",
2263 v4i16, v4i16, int_arm_neon_vpmins, 0>;
2264 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin", "s32",
2265 v2i32, v2i32, int_arm_neon_vpmins, 0>;
2266 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin", "u8",
2267 v8i8, v8i8, int_arm_neon_vpminu, 0>;
2268 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin", "u16",
2269 v4i16, v4i16, int_arm_neon_vpminu, 0>;
2270 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin", "u32",
2271 v2i32, v2i32, int_arm_neon_vpminu, 0>;
2272 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, IIC_VBINi4D, "vpmin", "f32",
2273 v2f32, v2f32, int_arm_neon_vpmins, 0>;
2275 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
2277 // VRECPE : Vector Reciprocal Estimate
2278 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
2279 IIC_VUNAD, "vrecpe", "u32",
2280 v2i32, v2i32, int_arm_neon_vrecpe>;
2281 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
2282 IIC_VUNAQ, "vrecpe", "u32",
2283 v4i32, v4i32, int_arm_neon_vrecpe>;
2284 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
2285 IIC_VUNAD, "vrecpe", "f32",
2286 v2f32, v2f32, int_arm_neon_vrecpe>;
2287 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
2288 IIC_VUNAQ, "vrecpe", "f32",
2289 v4f32, v4f32, int_arm_neon_vrecpe>;
2291 // VRECPS : Vector Reciprocal Step
2292 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1,
2293 IIC_VRECSD, "vrecps", "f32",
2294 v2f32, v2f32, int_arm_neon_vrecps, 1>;
2295 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1,
2296 IIC_VRECSQ, "vrecps", "f32",
2297 v4f32, v4f32, int_arm_neon_vrecps, 1>;
2299 // VRSQRTE : Vector Reciprocal Square Root Estimate
2300 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
2301 IIC_VUNAD, "vrsqrte", "u32",
2302 v2i32, v2i32, int_arm_neon_vrsqrte>;
2303 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
2304 IIC_VUNAQ, "vrsqrte", "u32",
2305 v4i32, v4i32, int_arm_neon_vrsqrte>;
2306 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
2307 IIC_VUNAD, "vrsqrte", "f32",
2308 v2f32, v2f32, int_arm_neon_vrsqrte>;
2309 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
2310 IIC_VUNAQ, "vrsqrte", "f32",
2311 v4f32, v4f32, int_arm_neon_vrsqrte>;
2313 // VRSQRTS : Vector Reciprocal Square Root Step
2314 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1,
2315 IIC_VRECSD, "vrsqrts", "f32",
2316 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
2317 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1,
2318 IIC_VRECSQ, "vrsqrts", "f32",
2319 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
2323 // VSHL : Vector Shift
2324 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
2325 IIC_VSHLiQ, "vshl", "s", int_arm_neon_vshifts, 0>;
2326 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
2327 IIC_VSHLiQ, "vshl", "u", int_arm_neon_vshiftu, 0>;
2328 // VSHL : Vector Shift Left (Immediate)
2329 defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
2330 // VSHR : Vector Shift Right (Immediate)
2331 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", NEONvshrs>;
2332 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", NEONvshru>;
2334 // VSHLL : Vector Shift Left Long
2335 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
2336 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
2338 // VSHLL : Vector Shift Left Long (with maximum shift count)
2339 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
2340 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
2341 ValueType OpTy, SDNode OpNode>
2342 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
2343 ResTy, OpTy, OpNode> {
2344 let Inst{21-16} = op21_16;
2346 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
2347 v8i16, v8i8, NEONvshlli>;
2348 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
2349 v4i32, v4i16, NEONvshlli>;
2350 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
2351 v2i64, v2i32, NEONvshlli>;
2353 // VSHRN : Vector Shift Right and Narrow
2354 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
2357 // VRSHL : Vector Rounding Shift
2358 defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2359 IIC_VSHLi4Q, "vrshl", "s", int_arm_neon_vrshifts,0>;
2360 defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2361 IIC_VSHLi4Q, "vrshl", "u", int_arm_neon_vrshiftu,0>;
2362 // VRSHR : Vector Rounding Shift Right
2363 defm VRSHRs : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs>;
2364 defm VRSHRu : N2VSh_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", NEONvrshru>;
2366 // VRSHRN : Vector Rounding Shift Right and Narrow
2367 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
2370 // VQSHL : Vector Saturating Shift
2371 defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2372 IIC_VSHLi4Q, "vqshl", "s", int_arm_neon_vqshifts,0>;
2373 defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2374 IIC_VSHLi4Q, "vqshl", "u", int_arm_neon_vqshiftu,0>;
2375 // VQSHL : Vector Saturating Shift Left (Immediate)
2376 defm VQSHLsi : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s", NEONvqshls>;
2377 defm VQSHLui : N2VSh_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u", NEONvqshlu>;
2378 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
2379 defm VQSHLsu : N2VSh_QHSD<1,1,0b0110,1, IIC_VSHLi4D, "vqshlu","s",NEONvqshlsu>;
2381 // VQSHRN : Vector Saturating Shift Right and Narrow
2382 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
2384 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
2387 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
2388 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
2391 // VQRSHL : Vector Saturating Rounding Shift
2392 defm VQRSHLs : N3VInt_QHSD<0,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2393 IIC_VSHLi4Q, "vqrshl", "s",
2394 int_arm_neon_vqrshifts, 0>;
2395 defm VQRSHLu : N3VInt_QHSD<1,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2396 IIC_VSHLi4Q, "vqrshl", "u",
2397 int_arm_neon_vqrshiftu, 0>;
2399 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
2400 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
2402 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
2405 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
2406 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
2409 // VSRA : Vector Shift Right and Accumulate
2410 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
2411 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
2412 // VRSRA : Vector Rounding Shift Right and Accumulate
2413 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
2414 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
2416 // VSLI : Vector Shift Left and Insert
2417 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli", NEONvsli>;
2418 // VSRI : Vector Shift Right and Insert
2419 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri", NEONvsri>;
2421 // Vector Absolute and Saturating Absolute.
2423 // VABS : Vector Absolute Value
2424 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
2425 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
2427 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2428 IIC_VUNAD, "vabs", "f32",
2429 v2f32, v2f32, int_arm_neon_vabs>;
2430 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2431 IIC_VUNAQ, "vabs", "f32",
2432 v4f32, v4f32, int_arm_neon_vabs>;
2434 // VQABS : Vector Saturating Absolute Value
2435 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
2436 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
2437 int_arm_neon_vqabs>;
2441 def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
2442 def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>;
2444 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
2445 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
2446 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
2447 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>;
2448 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
2449 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
2450 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
2451 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>;
2453 // VNEG : Vector Negate
2454 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
2455 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
2456 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
2457 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
2458 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
2459 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
2461 // VNEG : Vector Negate (floating-point)
2462 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
2463 (outs DPR:$dst), (ins DPR:$src), IIC_VUNAD,
2464 "vneg", "f32", "$dst, $src", "",
2465 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
2466 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
2467 (outs QPR:$dst), (ins QPR:$src), IIC_VUNAQ,
2468 "vneg", "f32", "$dst, $src", "",
2469 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
2471 def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
2472 def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
2473 def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>;
2474 def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>;
2475 def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>;
2476 def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>;
2478 // VQNEG : Vector Saturating Negate
2479 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
2480 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
2481 int_arm_neon_vqneg>;
2483 // Vector Bit Counting Operations.
2485 // VCLS : Vector Count Leading Sign Bits
2486 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
2487 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
2489 // VCLZ : Vector Count Leading Zeros
2490 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
2491 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
2493 // VCNT : Vector Count One Bits
2494 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2495 IIC_VCNTiD, "vcnt", "8",
2496 v8i8, v8i8, int_arm_neon_vcnt>;
2497 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2498 IIC_VCNTiQ, "vcnt", "8",
2499 v16i8, v16i8, int_arm_neon_vcnt>;
2501 // Vector Swap -- for disassembly only.
2502 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
2503 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
2504 "vswp", "$dst, $src", "", []>;
2505 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
2506 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
2507 "vswp", "$dst, $src", "", []>;
2509 // Vector Move Operations.
2511 // VMOV : Vector Move (Register)
2513 def VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
2514 IIC_VMOVD, "vmov", "$dst, $src", "", []>;
2515 def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
2516 IIC_VMOVD, "vmov", "$dst, $src", "", []>;
2518 // VMOV : Vector Move (Immediate)
2520 // VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
2521 def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
2522 return ARM::getVMOVImm(N, 1, *CurDAG);
2524 def vmovImm8 : PatLeaf<(build_vector), [{
2525 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
2528 // VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
2529 def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
2530 return ARM::getVMOVImm(N, 2, *CurDAG);
2532 def vmovImm16 : PatLeaf<(build_vector), [{
2533 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
2534 }], VMOV_get_imm16>;
2536 // VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
2537 def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
2538 return ARM::getVMOVImm(N, 4, *CurDAG);
2540 def vmovImm32 : PatLeaf<(build_vector), [{
2541 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
2542 }], VMOV_get_imm32>;
2544 // VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
2545 def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
2546 return ARM::getVMOVImm(N, 8, *CurDAG);
2548 def vmovImm64 : PatLeaf<(build_vector), [{
2549 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
2550 }], VMOV_get_imm64>;
2552 // Note: Some of the cmode bits in the following VMOV instructions need to
2553 // be encoded based on the immed values.
2555 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
2556 (ins h8imm:$SIMM), IIC_VMOVImm,
2557 "vmov", "i8", "$dst, $SIMM", "",
2558 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
2559 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
2560 (ins h8imm:$SIMM), IIC_VMOVImm,
2561 "vmov", "i8", "$dst, $SIMM", "",
2562 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
2564 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,?}, 0, 0, {?}, 1, (outs DPR:$dst),
2565 (ins h16imm:$SIMM), IIC_VMOVImm,
2566 "vmov", "i16", "$dst, $SIMM", "",
2567 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
2568 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,?}, 0, 1, {?}, 1, (outs QPR:$dst),
2569 (ins h16imm:$SIMM), IIC_VMOVImm,
2570 "vmov", "i16", "$dst, $SIMM", "",
2571 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
2573 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, {?}, 1, (outs DPR:$dst),
2574 (ins h32imm:$SIMM), IIC_VMOVImm,
2575 "vmov", "i32", "$dst, $SIMM", "",
2576 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
2577 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, {?}, 1, (outs QPR:$dst),
2578 (ins h32imm:$SIMM), IIC_VMOVImm,
2579 "vmov", "i32", "$dst, $SIMM", "",
2580 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
2582 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
2583 (ins h64imm:$SIMM), IIC_VMOVImm,
2584 "vmov", "i64", "$dst, $SIMM", "",
2585 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
2586 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
2587 (ins h64imm:$SIMM), IIC_VMOVImm,
2588 "vmov", "i64", "$dst, $SIMM", "",
2589 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
2591 // VMOV : Vector Get Lane (move scalar to ARM core register)
2593 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
2594 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2595 IIC_VMOVSI, "vmov", "s8", "$dst, $src[$lane]",
2596 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
2598 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
2599 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2600 IIC_VMOVSI, "vmov", "s16", "$dst, $src[$lane]",
2601 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
2603 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
2604 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2605 IIC_VMOVSI, "vmov", "u8", "$dst, $src[$lane]",
2606 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
2608 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
2609 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2610 IIC_VMOVSI, "vmov", "u16", "$dst, $src[$lane]",
2611 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
2613 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
2614 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2615 IIC_VMOVSI, "vmov", "32", "$dst, $src[$lane]",
2616 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
2618 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
2619 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
2620 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2621 (DSubReg_i8_reg imm:$lane))),
2622 (SubReg_i8_lane imm:$lane))>;
2623 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
2624 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2625 (DSubReg_i16_reg imm:$lane))),
2626 (SubReg_i16_lane imm:$lane))>;
2627 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
2628 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2629 (DSubReg_i8_reg imm:$lane))),
2630 (SubReg_i8_lane imm:$lane))>;
2631 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
2632 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2633 (DSubReg_i16_reg imm:$lane))),
2634 (SubReg_i16_lane imm:$lane))>;
2635 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
2636 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
2637 (DSubReg_i32_reg imm:$lane))),
2638 (SubReg_i32_lane imm:$lane))>;
2639 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
2640 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
2641 (SSubReg_f32_reg imm:$src2))>;
2642 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
2643 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
2644 (SSubReg_f32_reg imm:$src2))>;
2645 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
2646 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2647 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
2648 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2651 // VMOV : Vector Set Lane (move ARM core register to scalar)
2653 let Constraints = "$src1 = $dst" in {
2654 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$dst),
2655 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2656 IIC_VMOVISL, "vmov", "8", "$dst[$lane], $src2",
2657 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
2658 GPR:$src2, imm:$lane))]>;
2659 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$dst),
2660 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2661 IIC_VMOVISL, "vmov", "16", "$dst[$lane], $src2",
2662 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
2663 GPR:$src2, imm:$lane))]>;
2664 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$dst),
2665 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2666 IIC_VMOVISL, "vmov", "32", "$dst[$lane], $src2",
2667 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
2668 GPR:$src2, imm:$lane))]>;
2670 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
2671 (v16i8 (INSERT_SUBREG QPR:$src1,
2672 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
2673 (DSubReg_i8_reg imm:$lane))),
2674 GPR:$src2, (SubReg_i8_lane imm:$lane))),
2675 (DSubReg_i8_reg imm:$lane)))>;
2676 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
2677 (v8i16 (INSERT_SUBREG QPR:$src1,
2678 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
2679 (DSubReg_i16_reg imm:$lane))),
2680 GPR:$src2, (SubReg_i16_lane imm:$lane))),
2681 (DSubReg_i16_reg imm:$lane)))>;
2682 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
2683 (v4i32 (INSERT_SUBREG QPR:$src1,
2684 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
2685 (DSubReg_i32_reg imm:$lane))),
2686 GPR:$src2, (SubReg_i32_lane imm:$lane))),
2687 (DSubReg_i32_reg imm:$lane)))>;
2689 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
2690 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
2691 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
2692 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
2693 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
2694 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
2696 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
2697 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
2698 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
2699 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
2701 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
2702 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
2703 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
2704 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, arm_dsubreg_0)>;
2705 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
2706 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
2708 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
2709 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2710 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
2711 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2712 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
2713 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2715 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
2716 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
2717 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2719 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
2720 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
2721 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2723 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
2724 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
2725 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2728 // VDUP : Vector Duplicate (from ARM core register to all elements)
2730 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
2731 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
2732 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
2733 [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
2734 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
2735 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
2736 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
2737 [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
2739 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
2740 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
2741 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
2742 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
2743 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
2744 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
2746 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
2747 IIC_VMOVIS, "vdup", "32", "$dst, $src",
2748 [(set DPR:$dst, (v2f32 (NEONvdup
2749 (f32 (bitconvert GPR:$src)))))]>;
2750 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
2751 IIC_VMOVIS, "vdup", "32", "$dst, $src",
2752 [(set QPR:$dst, (v4f32 (NEONvdup
2753 (f32 (bitconvert GPR:$src)))))]>;
2755 // VDUP : Vector Duplicate Lane (from scalar to all elements)
2757 class VDUPLND<bits<2> op19_18, bits<2> op17_16,
2758 string OpcodeStr, string Dt, ValueType Ty>
2759 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
2760 (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
2761 OpcodeStr, Dt, "$dst, $src[$lane]", "",
2762 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
2764 class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, string Dt,
2765 ValueType ResTy, ValueType OpTy>
2766 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
2767 (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
2768 OpcodeStr, Dt, "$dst, $src[$lane]", "",
2769 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src), imm:$lane)))]>;
2771 // Inst{19-16} is partially specified depending on the element size.
2773 def VDUPLN8d : VDUPLND<{?,?}, {?,1}, "vdup", "8", v8i8>;
2774 def VDUPLN16d : VDUPLND<{?,?}, {1,0}, "vdup", "16", v4i16>;
2775 def VDUPLN32d : VDUPLND<{?,1}, {0,0}, "vdup", "32", v2i32>;
2776 def VDUPLNfd : VDUPLND<{?,1}, {0,0}, "vdup", "32", v2f32>;
2777 def VDUPLN8q : VDUPLNQ<{?,?}, {?,1}, "vdup", "8", v16i8, v8i8>;
2778 def VDUPLN16q : VDUPLNQ<{?,?}, {1,0}, "vdup", "16", v8i16, v4i16>;
2779 def VDUPLN32q : VDUPLNQ<{?,1}, {0,0}, "vdup", "32", v4i32, v2i32>;
2780 def VDUPLNfq : VDUPLNQ<{?,1}, {0,0}, "vdup", "32", v4f32, v2f32>;
2782 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
2783 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
2784 (DSubReg_i8_reg imm:$lane))),
2785 (SubReg_i8_lane imm:$lane)))>;
2786 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
2787 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
2788 (DSubReg_i16_reg imm:$lane))),
2789 (SubReg_i16_lane imm:$lane)))>;
2790 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
2791 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
2792 (DSubReg_i32_reg imm:$lane))),
2793 (SubReg_i32_lane imm:$lane)))>;
2794 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
2795 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
2796 (DSubReg_i32_reg imm:$lane))),
2797 (SubReg_i32_lane imm:$lane)))>;
2799 def VDUPfdf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 0, 0,
2800 (outs DPR:$dst), (ins SPR:$src),
2801 IIC_VMOVD, "vdup", "32", "$dst, ${src:lane}", "",
2802 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
2804 def VDUPfqf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 1, 0,
2805 (outs QPR:$dst), (ins SPR:$src),
2806 IIC_VMOVD, "vdup", "32", "$dst, ${src:lane}", "",
2807 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
2809 def : Pat<(v2i64 (NEONvduplane (v2i64 QPR:$src), imm:$lane)),
2810 (INSERT_SUBREG QPR:$src,
2811 (i64 (EXTRACT_SUBREG QPR:$src,
2812 (DSubReg_f64_reg imm:$lane))),
2813 (DSubReg_f64_other_reg imm:$lane))>;
2814 def : Pat<(v2f64 (NEONvduplane (v2f64 QPR:$src), imm:$lane)),
2815 (INSERT_SUBREG QPR:$src,
2816 (f64 (EXTRACT_SUBREG QPR:$src,
2817 (DSubReg_f64_reg imm:$lane))),
2818 (DSubReg_f64_other_reg imm:$lane))>;
2820 // VMOVN : Vector Narrowing Move
2821 defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVD,
2822 "vmovn", "i", int_arm_neon_vmovn>;
2823 // VQMOVN : Vector Saturating Narrowing Move
2824 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
2825 "vqmovn", "s", int_arm_neon_vqmovns>;
2826 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
2827 "vqmovn", "u", int_arm_neon_vqmovnu>;
2828 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
2829 "vqmovun", "s", int_arm_neon_vqmovnsu>;
2830 // VMOVL : Vector Lengthening Move
2831 defm VMOVLs : N2VLInt_QHS<0b01,0b10100,0,1, "vmovl", "s",
2832 int_arm_neon_vmovls>;
2833 defm VMOVLu : N2VLInt_QHS<0b11,0b10100,0,1, "vmovl", "u",
2834 int_arm_neon_vmovlu>;
2836 // Vector Conversions.
2838 // VCVT : Vector Convert Between Floating-Point and Integers
2839 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
2840 v2i32, v2f32, fp_to_sint>;
2841 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
2842 v2i32, v2f32, fp_to_uint>;
2843 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
2844 v2f32, v2i32, sint_to_fp>;
2845 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
2846 v2f32, v2i32, uint_to_fp>;
2848 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
2849 v4i32, v4f32, fp_to_sint>;
2850 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
2851 v4i32, v4f32, fp_to_uint>;
2852 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
2853 v4f32, v4i32, sint_to_fp>;
2854 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
2855 v4f32, v4i32, uint_to_fp>;
2857 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
2858 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
2859 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
2860 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
2861 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
2862 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
2863 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
2864 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
2865 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
2867 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
2868 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
2869 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
2870 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
2871 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
2872 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
2873 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
2874 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
2878 // VREV64 : Vector Reverse elements within 64-bit doublewords
2880 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
2881 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
2882 (ins DPR:$src), IIC_VMOVD,
2883 OpcodeStr, Dt, "$dst, $src", "",
2884 [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
2885 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
2886 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
2887 (ins QPR:$src), IIC_VMOVD,
2888 OpcodeStr, Dt, "$dst, $src", "",
2889 [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
2891 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
2892 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
2893 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
2894 def VREV64df : VREV64D<0b10, "vrev64", "32", v2f32>;
2896 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
2897 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
2898 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
2899 def VREV64qf : VREV64Q<0b10, "vrev64", "32", v4f32>;
2901 // VREV32 : Vector Reverse elements within 32-bit words
2903 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
2904 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
2905 (ins DPR:$src), IIC_VMOVD,
2906 OpcodeStr, Dt, "$dst, $src", "",
2907 [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
2908 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
2909 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
2910 (ins QPR:$src), IIC_VMOVD,
2911 OpcodeStr, Dt, "$dst, $src", "",
2912 [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
2914 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
2915 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
2917 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
2918 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
2920 // VREV16 : Vector Reverse elements within 16-bit halfwords
2922 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
2923 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
2924 (ins DPR:$src), IIC_VMOVD,
2925 OpcodeStr, Dt, "$dst, $src", "",
2926 [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
2927 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
2928 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
2929 (ins QPR:$src), IIC_VMOVD,
2930 OpcodeStr, Dt, "$dst, $src", "",
2931 [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
2933 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
2934 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
2936 // Other Vector Shuffles.
2938 // VEXT : Vector Extract
2940 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
2941 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$dst),
2942 (ins DPR:$lhs, DPR:$rhs, i32imm:$index), IIC_VEXTD,
2943 OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
2944 [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
2945 (Ty DPR:$rhs), imm:$index)))]>;
2947 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
2948 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$dst),
2949 (ins QPR:$lhs, QPR:$rhs, i32imm:$index), IIC_VEXTQ,
2950 OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
2951 [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
2952 (Ty QPR:$rhs), imm:$index)))]>;
2954 def VEXTd8 : VEXTd<"vext", "8", v8i8>;
2955 def VEXTd16 : VEXTd<"vext", "16", v4i16>;
2956 def VEXTd32 : VEXTd<"vext", "32", v2i32>;
2957 def VEXTdf : VEXTd<"vext", "32", v2f32>;
2959 def VEXTq8 : VEXTq<"vext", "8", v16i8>;
2960 def VEXTq16 : VEXTq<"vext", "16", v8i16>;
2961 def VEXTq32 : VEXTq<"vext", "32", v4i32>;
2962 def VEXTqf : VEXTq<"vext", "32", v4f32>;
2964 // VTRN : Vector Transpose
2966 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
2967 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
2968 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
2970 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
2971 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
2972 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
2974 // VUZP : Vector Unzip (Deinterleave)
2976 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
2977 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
2978 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
2980 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
2981 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
2982 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
2984 // VZIP : Vector Zip (Interleave)
2986 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
2987 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
2988 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
2990 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
2991 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
2992 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
2994 // Vector Table Lookup and Table Extension.
2996 // VTBL : Vector Table Lookup
2998 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
2999 (ins DPR:$tbl1, DPR:$src), IIC_VTB1,
3000 "vtbl", "8", "$dst, \\{$tbl1\\}, $src", "",
3001 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
3002 let hasExtraSrcRegAllocReq = 1 in {
3004 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
3005 (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTB2,
3006 "vtbl", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "",
3007 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl2
3008 DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
3010 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
3011 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTB3,
3012 "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src", "",
3013 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl3
3014 DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
3016 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
3017 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTB4,
3018 "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src", "",
3019 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl4 DPR:$tbl1, DPR:$tbl2,
3020 DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
3021 } // hasExtraSrcRegAllocReq = 1
3023 // VTBX : Vector Table Extension
3025 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
3026 (ins DPR:$orig, DPR:$tbl1, DPR:$src), IIC_VTBX1,
3027 "vtbx", "8", "$dst, \\{$tbl1\\}, $src", "$orig = $dst",
3028 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
3029 DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
3030 let hasExtraSrcRegAllocReq = 1 in {
3032 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
3033 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTBX2,
3034 "vtbx", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "$orig = $dst",
3035 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx2
3036 DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
3038 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
3039 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTBX3,
3040 "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src", "$orig = $dst",
3041 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx3 DPR:$orig, DPR:$tbl1,
3042 DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
3044 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
3045 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTBX4,
3046 "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src",
3048 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx4 DPR:$orig, DPR:$tbl1,
3049 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
3050 } // hasExtraSrcRegAllocReq = 1
3052 //===----------------------------------------------------------------------===//
3053 // NEON instructions for single-precision FP math
3054 //===----------------------------------------------------------------------===//
3056 class N2VSPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
3057 : NEONFPPat<(ResTy (OpNode SPR:$a)),
3058 (EXTRACT_SUBREG (OpTy (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)),
3059 SPR:$a, arm_ssubreg_0))),
3062 class N3VSPat<SDNode OpNode, NeonI Inst>
3063 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
3064 (EXTRACT_SUBREG (v2f32
3065 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3066 SPR:$a, arm_ssubreg_0),
3067 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3068 SPR:$b, arm_ssubreg_0))),
3071 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
3072 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
3073 (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3074 SPR:$acc, arm_ssubreg_0),
3075 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3076 SPR:$a, arm_ssubreg_0),
3077 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3078 SPR:$b, arm_ssubreg_0)),
3081 // These need separate instructions because they must use DPR_VFP2 register
3082 // class which have SPR sub-registers.
3084 // Vector Add Operations used for single-precision FP
3085 let neverHasSideEffects = 1 in
3086 def VADDfd_sfp : N3VS<0,0,0b00,0b1101,0, "vadd", "f32", v2f32, v2f32, fadd, 1>;
3087 def : N3VSPat<fadd, VADDfd_sfp>;
3089 // Vector Sub Operations used for single-precision FP
3090 let neverHasSideEffects = 1 in
3091 def VSUBfd_sfp : N3VS<0,0,0b10,0b1101,0, "vsub", "f32", v2f32, v2f32, fsub, 0>;
3092 def : N3VSPat<fsub, VSUBfd_sfp>;
3094 // Vector Multiply Operations used for single-precision FP
3095 let neverHasSideEffects = 1 in
3096 def VMULfd_sfp : N3VS<1,0,0b00,0b1101,1, "vmul", "f32", v2f32, v2f32, fmul, 1>;
3097 def : N3VSPat<fmul, VMULfd_sfp>;
3099 // Vector Multiply-Accumulate/Subtract used for single-precision FP
3100 // vml[as].f32 can cause 4-8 cycle stalls in following ASIMD instructions, so
3101 // we want to avoid them for now. e.g., alternating vmla/vadd instructions.
3103 //let neverHasSideEffects = 1 in
3104 //def VMLAfd_sfp : N3VSMulOp<0,0,0b00,0b1101,1, IIC_VMACD, "vmla", "f32",
3105 // v2f32, fmul, fadd>;
3106 //def : N3VSMulOpPat<fmul, fadd, VMLAfd_sfp>;
3108 //let neverHasSideEffects = 1 in
3109 //def VMLSfd_sfp : N3VSMulOp<0,0,0b10,0b1101,1, IIC_VMACD, "vmls", "f32",
3110 // v2f32, fmul, fsub>;
3111 //def : N3VSMulOpPat<fmul, fsub, VMLSfd_sfp>;
3113 // Vector Absolute used for single-precision FP
3114 let neverHasSideEffects = 1 in
3115 def VABSfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01110, 0, 0,
3116 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
3117 "vabs", "f32", "$dst, $src", "", []>;
3118 def : N2VSPat<fabs, f32, v2f32, VABSfd_sfp>;
3120 // Vector Negate used for single-precision FP
3121 let neverHasSideEffects = 1 in
3122 def VNEGfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
3123 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
3124 "vneg", "f32", "$dst, $src", "", []>;
3125 def : N2VSPat<fneg, f32, v2f32, VNEGfd_sfp>;
3127 // Vector Maximum used for single-precision FP
3128 let neverHasSideEffects = 1 in
3129 def VMAXfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
3130 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), IIC_VBIND,
3131 "vmax", "f32", "$dst, $src1, $src2", "", []>;
3132 def : N3VSPat<NEONfmax, VMAXfd_sfp>;
3134 // Vector Minimum used for single-precision FP
3135 let neverHasSideEffects = 1 in
3136 def VMINfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
3137 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), IIC_VBIND,
3138 "vmin", "f32", "$dst, $src1, $src2", "", []>;
3139 def : N3VSPat<NEONfmin, VMINfd_sfp>;
3141 // Vector Convert between single-precision FP and integer
3143 class NVCVTFIPat<SDNode OpNode, NeonI Inst>
3144 : NEONFPPat<(i32 (OpNode SPR:$a)),
3145 (i32 (EXTRACT_SUBREG
3147 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3152 class NVCVTIFPat<SDNode OpNode, NeonI Inst>
3153 : NEONFPPat<(f32 (OpNode GPR:$a)),
3154 (f32 (EXTRACT_SUBREG
3156 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
3157 (i32 (COPY_TO_REGCLASS GPR:$a, SPR)),
3161 let neverHasSideEffects = 1 in
3162 def VCVTf2sd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3163 v2i32, v2f32, fp_to_sint>;
3164 def : NVCVTFIPat<fp_to_sint, VCVTf2sd_sfp>;
3166 let neverHasSideEffects = 1 in
3167 def VCVTf2ud_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3168 v2i32, v2f32, fp_to_uint>;
3169 def : NVCVTFIPat<fp_to_uint, VCVTf2ud_sfp>;
3171 let neverHasSideEffects = 1 in
3172 def VCVTs2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3173 v2f32, v2i32, sint_to_fp>;
3174 def : NVCVTIFPat<sint_to_fp, VCVTs2fd_sfp>;
3176 let neverHasSideEffects = 1 in
3177 def VCVTu2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3178 v2f32, v2i32, uint_to_fp>;
3179 def : NVCVTIFPat<uint_to_fp, VCVTu2fd_sfp>;
3181 //===----------------------------------------------------------------------===//
3182 // Non-Instruction Patterns
3183 //===----------------------------------------------------------------------===//
3186 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
3187 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
3188 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
3189 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
3190 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
3191 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
3192 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
3193 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
3194 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
3195 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
3196 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
3197 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
3198 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
3199 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
3200 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
3201 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
3202 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
3203 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
3204 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
3205 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
3206 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
3207 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
3208 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
3209 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
3210 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
3211 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
3212 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
3213 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
3214 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
3215 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
3217 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
3218 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
3219 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
3220 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
3221 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
3222 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
3223 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
3224 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
3225 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
3226 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
3227 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
3228 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
3229 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
3230 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
3231 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
3232 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
3233 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
3234 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
3235 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
3236 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
3237 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
3238 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
3239 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
3240 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
3241 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
3242 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
3243 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
3244 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
3245 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
3246 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;