1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
69 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
70 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
72 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
74 // VDUPLANE can produce a quad-register result from a double-register source,
75 // so the result is not constrained to match the source.
76 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
77 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
80 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
81 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
82 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
84 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
85 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
86 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
87 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
89 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
92 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
93 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
94 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
96 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
98 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
99 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
101 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
102 SDTCisSameAs<0, 2>]>;
103 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
104 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
106 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
107 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
108 unsigned EltBits = 0;
109 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
110 return (EltBits == 32 && EltVal == 0);
113 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
114 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
115 unsigned EltBits = 0;
116 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
117 return (EltBits == 8 && EltVal == 0xff);
120 //===----------------------------------------------------------------------===//
121 // NEON operand definitions
122 //===----------------------------------------------------------------------===//
124 def nModImm : Operand<i32> {
125 let PrintMethod = "printNEONModImmOperand";
128 //===----------------------------------------------------------------------===//
129 // NEON load / store instructions
130 //===----------------------------------------------------------------------===//
132 // Use VLDM to load a Q register as a D register pair.
133 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
135 : PseudoVFPLdStM<(outs QPR:$dst), (ins addrmode4:$addr), IIC_fpLoad_m, "",
136 [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]>;
138 // Use VSTM to store a Q register as a D register pair.
139 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
141 : PseudoVFPLdStM<(outs), (ins QPR:$src, addrmode4:$addr), IIC_fpStore_m, "",
142 [(store (v2f64 QPR:$src), addrmode4:$addr)]>;
144 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
146 // Classes for VLD* pseudo-instructions with multi-register operands.
147 // These are expanded to real instructions after register allocation.
148 class VLDQPseudo<InstrItinClass itin>
149 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
150 class VLDQWBPseudo<InstrItinClass itin>
151 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
152 (ins addrmode6:$addr, am6offset:$offset), itin,
154 class VLDQQPseudo<InstrItinClass itin>
155 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
156 class VLDQQWBPseudo<InstrItinClass itin>
157 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
158 (ins addrmode6:$addr, am6offset:$offset), itin,
160 class VLDQQQQWBPseudo<InstrItinClass itin>
161 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
162 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
163 "$addr.addr = $wb, $src = $dst">;
165 // VLD1 : Vector Load (multiple single elements)
166 class VLD1D<bits<4> op7_4, string Dt>
167 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst),
168 (ins addrmode6:$addr), IIC_VLD1,
169 "vld1", Dt, "\\{$dst\\}, $addr", "", []>;
170 class VLD1Q<bits<4> op7_4, string Dt>
171 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$dst1, DPR:$dst2),
172 (ins addrmode6:$addr), IIC_VLD1x2,
173 "vld1", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>;
175 def VLD1d8 : VLD1D<0b0000, "8">;
176 def VLD1d16 : VLD1D<0b0100, "16">;
177 def VLD1d32 : VLD1D<0b1000, "32">;
178 def VLD1d64 : VLD1D<0b1100, "64">;
180 def VLD1q8 : VLD1Q<0b0000, "8">;
181 def VLD1q16 : VLD1Q<0b0100, "16">;
182 def VLD1q32 : VLD1Q<0b1000, "32">;
183 def VLD1q64 : VLD1Q<0b1100, "64">;
185 def VLD1q8Pseudo : VLDQPseudo<IIC_VLD1x2>;
186 def VLD1q16Pseudo : VLDQPseudo<IIC_VLD1x2>;
187 def VLD1q32Pseudo : VLDQPseudo<IIC_VLD1x2>;
188 def VLD1q64Pseudo : VLDQPseudo<IIC_VLD1x2>;
190 // ...with address register writeback:
191 class VLD1DWB<bits<4> op7_4, string Dt>
192 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst, GPR:$wb),
193 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1u,
194 "vld1", Dt, "\\{$dst\\}, $addr$offset",
195 "$addr.addr = $wb", []>;
196 class VLD1QWB<bits<4> op7_4, string Dt>
197 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
198 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1x2u,
199 "vld1", Dt, "\\{$dst1, $dst2\\}, $addr$offset",
200 "$addr.addr = $wb", []>;
202 def VLD1d8_UPD : VLD1DWB<0b0000, "8">;
203 def VLD1d16_UPD : VLD1DWB<0b0100, "16">;
204 def VLD1d32_UPD : VLD1DWB<0b1000, "32">;
205 def VLD1d64_UPD : VLD1DWB<0b1100, "64">;
207 def VLD1q8_UPD : VLD1QWB<0b0000, "8">;
208 def VLD1q16_UPD : VLD1QWB<0b0100, "16">;
209 def VLD1q32_UPD : VLD1QWB<0b1000, "32">;
210 def VLD1q64_UPD : VLD1QWB<0b1100, "64">;
212 def VLD1q8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
213 def VLD1q16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
214 def VLD1q32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
215 def VLD1q64Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
217 // ...with 3 registers (some of these are only for the disassembler):
218 class VLD1D3<bits<4> op7_4, string Dt>
219 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
220 (ins addrmode6:$addr), IIC_VLD1x3, "vld1", Dt,
221 "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
222 class VLD1D3WB<bits<4> op7_4, string Dt>
223 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
224 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1x3u, "vld1", Dt,
225 "\\{$dst1, $dst2, $dst3\\}, $addr$offset", "$addr.addr = $wb", []>;
227 def VLD1d8T : VLD1D3<0b0000, "8">;
228 def VLD1d16T : VLD1D3<0b0100, "16">;
229 def VLD1d32T : VLD1D3<0b1000, "32">;
230 def VLD1d64T : VLD1D3<0b1100, "64">;
232 def VLD1d8T_UPD : VLD1D3WB<0b0000, "8">;
233 def VLD1d16T_UPD : VLD1D3WB<0b0100, "16">;
234 def VLD1d32T_UPD : VLD1D3WB<0b1000, "32">;
235 def VLD1d64T_UPD : VLD1D3WB<0b1100, "64">;
237 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
238 def VLD1d64TPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x3u>;
240 // ...with 4 registers (some of these are only for the disassembler):
241 class VLD1D4<bits<4> op7_4, string Dt>
242 : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
243 (ins addrmode6:$addr), IIC_VLD1x4, "vld1", Dt,
244 "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
245 class VLD1D4WB<bits<4> op7_4, string Dt>
246 : NLdSt<0,0b10,0b0010,op7_4,
247 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
248 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD4, "vld1", Dt,
249 "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset", "$addr.addr = $wb",
252 def VLD1d8Q : VLD1D4<0b0000, "8">;
253 def VLD1d16Q : VLD1D4<0b0100, "16">;
254 def VLD1d32Q : VLD1D4<0b1000, "32">;
255 def VLD1d64Q : VLD1D4<0b1100, "64">;
257 def VLD1d8Q_UPD : VLD1D4WB<0b0000, "8">;
258 def VLD1d16Q_UPD : VLD1D4WB<0b0100, "16">;
259 def VLD1d32Q_UPD : VLD1D4WB<0b1000, "32">;
260 def VLD1d64Q_UPD : VLD1D4WB<0b1100, "64">;
262 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
263 def VLD1d64QPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x4u>;
265 // VLD2 : Vector Load (multiple 2-element structures)
266 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
267 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2),
268 (ins addrmode6:$addr), IIC_VLD2,
269 "vld2", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>;
270 class VLD2Q<bits<4> op7_4, string Dt>
271 : NLdSt<0, 0b10, 0b0011, op7_4,
272 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
273 (ins addrmode6:$addr), IIC_VLD2x2,
274 "vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
276 def VLD2d8 : VLD2D<0b1000, 0b0000, "8">;
277 def VLD2d16 : VLD2D<0b1000, 0b0100, "16">;
278 def VLD2d32 : VLD2D<0b1000, 0b1000, "32">;
280 def VLD2q8 : VLD2Q<0b0000, "8">;
281 def VLD2q16 : VLD2Q<0b0100, "16">;
282 def VLD2q32 : VLD2Q<0b1000, "32">;
284 def VLD2d8Pseudo : VLDQPseudo<IIC_VLD2>;
285 def VLD2d16Pseudo : VLDQPseudo<IIC_VLD2>;
286 def VLD2d32Pseudo : VLDQPseudo<IIC_VLD2>;
288 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
289 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
290 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
292 // ...with address register writeback:
293 class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
294 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
295 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2u,
296 "vld2", Dt, "\\{$dst1, $dst2\\}, $addr$offset",
297 "$addr.addr = $wb", []>;
298 class VLD2QWB<bits<4> op7_4, string Dt>
299 : NLdSt<0, 0b10, 0b0011, op7_4,
300 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
301 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2x2u,
302 "vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset",
303 "$addr.addr = $wb", []>;
305 def VLD2d8_UPD : VLD2DWB<0b1000, 0b0000, "8">;
306 def VLD2d16_UPD : VLD2DWB<0b1000, 0b0100, "16">;
307 def VLD2d32_UPD : VLD2DWB<0b1000, 0b1000, "32">;
309 def VLD2q8_UPD : VLD2QWB<0b0000, "8">;
310 def VLD2q16_UPD : VLD2QWB<0b0100, "16">;
311 def VLD2q32_UPD : VLD2QWB<0b1000, "32">;
313 def VLD2d8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
314 def VLD2d16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
315 def VLD2d32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
317 def VLD2q8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
318 def VLD2q16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
319 def VLD2q32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
321 // ...with double-spaced registers (for disassembly only):
322 def VLD2b8 : VLD2D<0b1001, 0b0000, "8">;
323 def VLD2b16 : VLD2D<0b1001, 0b0100, "16">;
324 def VLD2b32 : VLD2D<0b1001, 0b1000, "32">;
325 def VLD2b8_UPD : VLD2DWB<0b1001, 0b0000, "8">;
326 def VLD2b16_UPD : VLD2DWB<0b1001, 0b0100, "16">;
327 def VLD2b32_UPD : VLD2DWB<0b1001, 0b1000, "32">;
329 // VLD3 : Vector Load (multiple 3-element structures)
330 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
331 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
332 (ins addrmode6:$addr), IIC_VLD3,
333 "vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
335 def VLD3d8 : VLD3D<0b0100, 0b0000, "8">;
336 def VLD3d16 : VLD3D<0b0100, 0b0100, "16">;
337 def VLD3d32 : VLD3D<0b0100, 0b1000, "32">;
339 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
340 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
341 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
343 // ...with address register writeback:
344 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
345 : NLdSt<0, 0b10, op11_8, op7_4,
346 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
347 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD3u,
348 "vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr$offset",
349 "$addr.addr = $wb", []>;
351 def VLD3d8_UPD : VLD3DWB<0b0100, 0b0000, "8">;
352 def VLD3d16_UPD : VLD3DWB<0b0100, 0b0100, "16">;
353 def VLD3d32_UPD : VLD3DWB<0b0100, 0b1000, "32">;
355 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
356 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
357 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
359 // ...with double-spaced registers (non-updating versions for disassembly only):
360 def VLD3q8 : VLD3D<0b0101, 0b0000, "8">;
361 def VLD3q16 : VLD3D<0b0101, 0b0100, "16">;
362 def VLD3q32 : VLD3D<0b0101, 0b1000, "32">;
363 def VLD3q8_UPD : VLD3DWB<0b0101, 0b0000, "8">;
364 def VLD3q16_UPD : VLD3DWB<0b0101, 0b0100, "16">;
365 def VLD3q32_UPD : VLD3DWB<0b0101, 0b1000, "32">;
367 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
368 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
369 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
371 // ...alternate versions to be allocated odd register numbers:
372 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
373 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
374 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
376 // VLD4 : Vector Load (multiple 4-element structures)
377 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
378 : NLdSt<0, 0b10, op11_8, op7_4,
379 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
380 (ins addrmode6:$addr), IIC_VLD4,
381 "vld4", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
383 def VLD4d8 : VLD4D<0b0000, 0b0000, "8">;
384 def VLD4d16 : VLD4D<0b0000, 0b0100, "16">;
385 def VLD4d32 : VLD4D<0b0000, 0b1000, "32">;
387 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
388 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
389 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
391 // ...with address register writeback:
392 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
393 : NLdSt<0, 0b10, op11_8, op7_4,
394 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
395 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD4,
396 "vld4", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset",
397 "$addr.addr = $wb", []>;
399 def VLD4d8_UPD : VLD4DWB<0b0000, 0b0000, "8">;
400 def VLD4d16_UPD : VLD4DWB<0b0000, 0b0100, "16">;
401 def VLD4d32_UPD : VLD4DWB<0b0000, 0b1000, "32">;
403 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
404 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
405 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
407 // ...with double-spaced registers (non-updating versions for disassembly only):
408 def VLD4q8 : VLD4D<0b0001, 0b0000, "8">;
409 def VLD4q16 : VLD4D<0b0001, 0b0100, "16">;
410 def VLD4q32 : VLD4D<0b0001, 0b1000, "32">;
411 def VLD4q8_UPD : VLD4DWB<0b0001, 0b0000, "8">;
412 def VLD4q16_UPD : VLD4DWB<0b0001, 0b0100, "16">;
413 def VLD4q32_UPD : VLD4DWB<0b0001, 0b1000, "32">;
415 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
416 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
417 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
419 // ...alternate versions to be allocated odd register numbers:
420 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
421 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
422 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
424 // Classes for VLD*LN pseudo-instructions with multi-register operands.
425 // These are expanded to real instructions after register allocation.
426 class VLDQLNPseudo<InstrItinClass itin>
427 : PseudoNLdSt<(outs QPR:$dst),
428 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
429 itin, "$src = $dst">;
430 class VLDQLNWBPseudo<InstrItinClass itin>
431 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
432 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
433 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
434 class VLDQQLNPseudo<InstrItinClass itin>
435 : PseudoNLdSt<(outs QQPR:$dst),
436 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
437 itin, "$src = $dst">;
438 class VLDQQLNWBPseudo<InstrItinClass itin>
439 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
440 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
441 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
442 class VLDQQQQLNPseudo<InstrItinClass itin>
443 : PseudoNLdSt<(outs QQQQPR:$dst),
444 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
445 itin, "$src = $dst">;
446 class VLDQQQQLNWBPseudo<InstrItinClass itin>
447 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
448 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
449 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
451 // VLD1LN : Vector Load (single element to one lane)
452 // FIXME: Not yet implemented.
454 // VLD2LN : Vector Load (single 2-element structure to one lane)
455 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
456 : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2),
457 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
458 IIC_VLD2ln, "vld2", Dt, "\\{$dst1[$lane], $dst2[$lane]\\}, $addr",
459 "$src1 = $dst1, $src2 = $dst2", []>;
461 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8">;
462 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16">;
463 def VLD2LNd32 : VLD2LN<0b1001, {?,0,?,?}, "32">;
465 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
466 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
467 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
469 // ...with double-spaced registers:
470 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16">;
471 def VLD2LNq32 : VLD2LN<0b1001, {?,1,?,?}, "32">;
473 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
474 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
476 // ...with address register writeback:
477 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
478 : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
479 (ins addrmode6:$addr, am6offset:$offset,
480 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
481 "\\{$dst1[$lane], $dst2[$lane]\\}, $addr$offset",
482 "$src1 = $dst1, $src2 = $dst2, $addr.addr = $wb", []>;
484 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8">;
485 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16">;
486 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,?,?}, "32">;
488 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
489 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
490 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
492 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16">;
493 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,?,?}, "32">;
495 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
496 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
498 // VLD3LN : Vector Load (single 3-element structure to one lane)
499 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
500 : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
501 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
502 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
503 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr",
504 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
506 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8">;
507 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16">;
508 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32">;
510 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
511 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
512 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
514 // ...with double-spaced registers:
515 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16">;
516 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32">;
518 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
519 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
521 // ...with address register writeback:
522 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
523 : NLdSt<1, 0b10, op11_8, op7_4,
524 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
525 (ins addrmode6:$addr, am6offset:$offset,
526 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
527 IIC_VLD3lnu, "vld3", Dt,
528 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr$offset",
529 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $addr.addr = $wb",
532 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8">;
533 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16">;
534 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32">;
536 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
537 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
538 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
540 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16">;
541 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32">;
543 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
544 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
546 // VLD4LN : Vector Load (single 4-element structure to one lane)
547 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
548 : NLdSt<1, 0b10, op11_8, op7_4,
549 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
550 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
551 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
552 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr",
553 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
555 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8">;
556 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16">;
557 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32">;
559 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
560 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
561 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
563 // ...with double-spaced registers:
564 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16">;
565 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32">;
567 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
568 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
570 // ...with address register writeback:
571 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
572 : NLdSt<1, 0b10, op11_8, op7_4,
573 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
574 (ins addrmode6:$addr, am6offset:$offset,
575 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
576 IIC_VLD4ln, "vld4", Dt,
577 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr$offset",
578 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $addr.addr = $wb",
581 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8">;
582 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16">;
583 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32">;
585 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
586 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
587 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
589 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16">;
590 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32">;
592 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
593 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
595 // VLD1DUP : Vector Load (single element to all lanes)
596 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
597 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
598 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
599 // FIXME: Not yet implemented.
600 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
602 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
604 // Classes for VST* pseudo-instructions with multi-register operands.
605 // These are expanded to real instructions after register allocation.
606 class VSTQPseudo<InstrItinClass itin>
607 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
608 class VSTQWBPseudo<InstrItinClass itin>
609 : PseudoNLdSt<(outs GPR:$wb),
610 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
612 class VSTQQPseudo<InstrItinClass itin>
613 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
614 class VSTQQWBPseudo<InstrItinClass itin>
615 : PseudoNLdSt<(outs GPR:$wb),
616 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
618 class VSTQQQQWBPseudo<InstrItinClass itin>
619 : PseudoNLdSt<(outs GPR:$wb),
620 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
623 // VST1 : Vector Store (multiple single elements)
624 class VST1D<bits<4> op7_4, string Dt>
625 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src),
626 IIC_VST1, "vst1", Dt, "\\{$src\\}, $addr", "", []>;
627 class VST1Q<bits<4> op7_4, string Dt>
628 : NLdSt<0,0b00,0b1010,op7_4, (outs),
629 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST1x2,
630 "vst1", Dt, "\\{$src1, $src2\\}, $addr", "", []>;
632 def VST1d8 : VST1D<0b0000, "8">;
633 def VST1d16 : VST1D<0b0100, "16">;
634 def VST1d32 : VST1D<0b1000, "32">;
635 def VST1d64 : VST1D<0b1100, "64">;
637 def VST1q8 : VST1Q<0b0000, "8">;
638 def VST1q16 : VST1Q<0b0100, "16">;
639 def VST1q32 : VST1Q<0b1000, "32">;
640 def VST1q64 : VST1Q<0b1100, "64">;
642 def VST1q8Pseudo : VSTQPseudo<IIC_VST1x2>;
643 def VST1q16Pseudo : VSTQPseudo<IIC_VST1x2>;
644 def VST1q32Pseudo : VSTQPseudo<IIC_VST1x2>;
645 def VST1q64Pseudo : VSTQPseudo<IIC_VST1x2>;
647 // ...with address register writeback:
648 class VST1DWB<bits<4> op7_4, string Dt>
649 : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
650 (ins addrmode6:$addr, am6offset:$offset, DPR:$src), IIC_VST1u,
651 "vst1", Dt, "\\{$src\\}, $addr$offset", "$addr.addr = $wb", []>;
652 class VST1QWB<bits<4> op7_4, string Dt>
653 : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),
654 (ins addrmode6:$addr, am6offset:$offset, DPR:$src1, DPR:$src2),
655 IIC_VST1x2u, "vst1", Dt, "\\{$src1, $src2\\}, $addr$offset",
656 "$addr.addr = $wb", []>;
658 def VST1d8_UPD : VST1DWB<0b0000, "8">;
659 def VST1d16_UPD : VST1DWB<0b0100, "16">;
660 def VST1d32_UPD : VST1DWB<0b1000, "32">;
661 def VST1d64_UPD : VST1DWB<0b1100, "64">;
663 def VST1q8_UPD : VST1QWB<0b0000, "8">;
664 def VST1q16_UPD : VST1QWB<0b0100, "16">;
665 def VST1q32_UPD : VST1QWB<0b1000, "32">;
666 def VST1q64_UPD : VST1QWB<0b1100, "64">;
668 def VST1q8Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
669 def VST1q16Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
670 def VST1q32Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
671 def VST1q64Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
673 // ...with 3 registers (some of these are only for the disassembler):
674 class VST1D3<bits<4> op7_4, string Dt>
675 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
676 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
677 IIC_VST1x3, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>;
678 class VST1D3WB<bits<4> op7_4, string Dt>
679 : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
680 (ins addrmode6:$addr, am6offset:$offset,
681 DPR:$src1, DPR:$src2, DPR:$src3),
682 IIC_VST1x3u, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr$offset",
683 "$addr.addr = $wb", []>;
685 def VST1d8T : VST1D3<0b0000, "8">;
686 def VST1d16T : VST1D3<0b0100, "16">;
687 def VST1d32T : VST1D3<0b1000, "32">;
688 def VST1d64T : VST1D3<0b1100, "64">;
690 def VST1d8T_UPD : VST1D3WB<0b0000, "8">;
691 def VST1d16T_UPD : VST1D3WB<0b0100, "16">;
692 def VST1d32T_UPD : VST1D3WB<0b1000, "32">;
693 def VST1d64T_UPD : VST1D3WB<0b1100, "64">;
695 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
696 def VST1d64TPseudo_UPD : VSTQQWBPseudo<IIC_VST1x3u>;
698 // ...with 4 registers (some of these are only for the disassembler):
699 class VST1D4<bits<4> op7_4, string Dt>
700 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
701 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
702 IIC_VST1x4, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr", "",
704 class VST1D4WB<bits<4> op7_4, string Dt>
705 : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
706 (ins addrmode6:$addr, am6offset:$offset,
707 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST1x4u,
708 "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
709 "$addr.addr = $wb", []>;
711 def VST1d8Q : VST1D4<0b0000, "8">;
712 def VST1d16Q : VST1D4<0b0100, "16">;
713 def VST1d32Q : VST1D4<0b1000, "32">;
714 def VST1d64Q : VST1D4<0b1100, "64">;
716 def VST1d8Q_UPD : VST1D4WB<0b0000, "8">;
717 def VST1d16Q_UPD : VST1D4WB<0b0100, "16">;
718 def VST1d32Q_UPD : VST1D4WB<0b1000, "32">;
719 def VST1d64Q_UPD : VST1D4WB<0b1100, "64">;
721 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
722 def VST1d64QPseudo_UPD : VSTQQWBPseudo<IIC_VST1x4u>;
724 // VST2 : Vector Store (multiple 2-element structures)
725 class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
726 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
727 (ins addrmode6:$addr, DPR:$src1, DPR:$src2),
728 IIC_VST2, "vst2", Dt, "\\{$src1, $src2\\}, $addr", "", []>;
729 class VST2Q<bits<4> op7_4, string Dt>
730 : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
731 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
732 IIC_VST2x2, "vst2", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
735 def VST2d8 : VST2D<0b1000, 0b0000, "8">;
736 def VST2d16 : VST2D<0b1000, 0b0100, "16">;
737 def VST2d32 : VST2D<0b1000, 0b1000, "32">;
739 def VST2q8 : VST2Q<0b0000, "8">;
740 def VST2q16 : VST2Q<0b0100, "16">;
741 def VST2q32 : VST2Q<0b1000, "32">;
743 def VST2d8Pseudo : VSTQPseudo<IIC_VST2>;
744 def VST2d16Pseudo : VSTQPseudo<IIC_VST2>;
745 def VST2d32Pseudo : VSTQPseudo<IIC_VST2>;
747 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
748 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
749 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
751 // ...with address register writeback:
752 class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
753 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
754 (ins addrmode6:$addr, am6offset:$offset, DPR:$src1, DPR:$src2),
755 IIC_VST2u, "vst2", Dt, "\\{$src1, $src2\\}, $addr$offset",
756 "$addr.addr = $wb", []>;
757 class VST2QWB<bits<4> op7_4, string Dt>
758 : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
759 (ins addrmode6:$addr, am6offset:$offset,
760 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST2x2u,
761 "vst2", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
762 "$addr.addr = $wb", []>;
764 def VST2d8_UPD : VST2DWB<0b1000, 0b0000, "8">;
765 def VST2d16_UPD : VST2DWB<0b1000, 0b0100, "16">;
766 def VST2d32_UPD : VST2DWB<0b1000, 0b1000, "32">;
768 def VST2q8_UPD : VST2QWB<0b0000, "8">;
769 def VST2q16_UPD : VST2QWB<0b0100, "16">;
770 def VST2q32_UPD : VST2QWB<0b1000, "32">;
772 def VST2d8Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
773 def VST2d16Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
774 def VST2d32Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
776 def VST2q8Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
777 def VST2q16Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
778 def VST2q32Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
780 // ...with double-spaced registers (for disassembly only):
781 def VST2b8 : VST2D<0b1001, 0b0000, "8">;
782 def VST2b16 : VST2D<0b1001, 0b0100, "16">;
783 def VST2b32 : VST2D<0b1001, 0b1000, "32">;
784 def VST2b8_UPD : VST2DWB<0b1001, 0b0000, "8">;
785 def VST2b16_UPD : VST2DWB<0b1001, 0b0100, "16">;
786 def VST2b32_UPD : VST2DWB<0b1001, 0b1000, "32">;
788 // VST3 : Vector Store (multiple 3-element structures)
789 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
790 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
791 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST3,
792 "vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>;
794 def VST3d8 : VST3D<0b0100, 0b0000, "8">;
795 def VST3d16 : VST3D<0b0100, 0b0100, "16">;
796 def VST3d32 : VST3D<0b0100, 0b1000, "32">;
798 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
799 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
800 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
802 // ...with address register writeback:
803 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
804 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
805 (ins addrmode6:$addr, am6offset:$offset,
806 DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST3u,
807 "vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr$offset",
808 "$addr.addr = $wb", []>;
810 def VST3d8_UPD : VST3DWB<0b0100, 0b0000, "8">;
811 def VST3d16_UPD : VST3DWB<0b0100, 0b0100, "16">;
812 def VST3d32_UPD : VST3DWB<0b0100, 0b1000, "32">;
814 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
815 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
816 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
818 // ...with double-spaced registers (non-updating versions for disassembly only):
819 def VST3q8 : VST3D<0b0101, 0b0000, "8">;
820 def VST3q16 : VST3D<0b0101, 0b0100, "16">;
821 def VST3q32 : VST3D<0b0101, 0b1000, "32">;
822 def VST3q8_UPD : VST3DWB<0b0101, 0b0000, "8">;
823 def VST3q16_UPD : VST3DWB<0b0101, 0b0100, "16">;
824 def VST3q32_UPD : VST3DWB<0b0101, 0b1000, "32">;
826 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
827 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
828 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
830 // ...alternate versions to be allocated odd register numbers:
831 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
832 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
833 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
835 // VST4 : Vector Store (multiple 4-element structures)
836 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
837 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
838 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
839 IIC_VST4, "vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
842 def VST4d8 : VST4D<0b0000, 0b0000, "8">;
843 def VST4d16 : VST4D<0b0000, 0b0100, "16">;
844 def VST4d32 : VST4D<0b0000, 0b1000, "32">;
846 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
847 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
848 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
850 // ...with address register writeback:
851 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
852 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
853 (ins addrmode6:$addr, am6offset:$offset,
854 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
855 "vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
856 "$addr.addr = $wb", []>;
858 def VST4d8_UPD : VST4DWB<0b0000, 0b0000, "8">;
859 def VST4d16_UPD : VST4DWB<0b0000, 0b0100, "16">;
860 def VST4d32_UPD : VST4DWB<0b0000, 0b1000, "32">;
862 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
863 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
864 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
866 // ...with double-spaced registers (non-updating versions for disassembly only):
867 def VST4q8 : VST4D<0b0001, 0b0000, "8">;
868 def VST4q16 : VST4D<0b0001, 0b0100, "16">;
869 def VST4q32 : VST4D<0b0001, 0b1000, "32">;
870 def VST4q8_UPD : VST4DWB<0b0001, 0b0000, "8">;
871 def VST4q16_UPD : VST4DWB<0b0001, 0b0100, "16">;
872 def VST4q32_UPD : VST4DWB<0b0001, 0b1000, "32">;
874 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
875 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
876 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
878 // ...alternate versions to be allocated odd register numbers:
879 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
880 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
881 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
883 // Classes for VST*LN pseudo-instructions with multi-register operands.
884 // These are expanded to real instructions after register allocation.
885 class VSTQLNPseudo<InstrItinClass itin>
886 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
888 class VSTQLNWBPseudo<InstrItinClass itin>
889 : PseudoNLdSt<(outs GPR:$wb),
890 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
891 nohash_imm:$lane), itin, "$addr.addr = $wb">;
892 class VSTQQLNPseudo<InstrItinClass itin>
893 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
895 class VSTQQLNWBPseudo<InstrItinClass itin>
896 : PseudoNLdSt<(outs GPR:$wb),
897 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
898 nohash_imm:$lane), itin, "$addr.addr = $wb">;
899 class VSTQQQQLNPseudo<InstrItinClass itin>
900 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
902 class VSTQQQQLNWBPseudo<InstrItinClass itin>
903 : PseudoNLdSt<(outs GPR:$wb),
904 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
905 nohash_imm:$lane), itin, "$addr.addr = $wb">;
907 // VST1LN : Vector Store (single element from one lane)
908 // FIXME: Not yet implemented.
910 // VST2LN : Vector Store (single 2-element structure from one lane)
911 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
912 : NLdSt<1, 0b00, op11_8, op7_4, (outs),
913 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
914 IIC_VST2ln, "vst2", Dt, "\\{$src1[$lane], $src2[$lane]\\}, $addr",
917 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8">;
918 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16">;
919 def VST2LNd32 : VST2LN<0b1001, {?,0,?,?}, "32">;
921 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
922 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
923 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
925 // ...with double-spaced registers:
926 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16">;
927 def VST2LNq32 : VST2LN<0b1001, {?,1,?,?}, "32">;
929 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
930 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
932 // ...with address register writeback:
933 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
934 : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
935 (ins addrmode6:$addr, am6offset:$offset,
936 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
937 "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset",
938 "$addr.addr = $wb", []>;
940 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8">;
941 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16">;
942 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,?,?}, "32">;
944 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
945 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
946 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
948 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16">;
949 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,?,?}, "32">;
951 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
952 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
954 // VST3LN : Vector Store (single 3-element structure from one lane)
955 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
956 : NLdSt<1, 0b00, op11_8, op7_4, (outs),
957 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
958 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
959 "\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr", "", []>;
961 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8">;
962 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16">;
963 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32">;
965 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
966 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
967 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
969 // ...with double-spaced registers:
970 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16">;
971 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32">;
973 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
974 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
976 // ...with address register writeback:
977 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
978 : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
979 (ins addrmode6:$addr, am6offset:$offset,
980 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
981 IIC_VST3lnu, "vst3", Dt,
982 "\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr$offset",
983 "$addr.addr = $wb", []>;
985 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8">;
986 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16">;
987 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32">;
989 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
990 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
991 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
993 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16">;
994 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32">;
996 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
997 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
999 // VST4LN : Vector Store (single 4-element structure from one lane)
1000 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1001 : NLdSt<1, 0b00, op11_8, op7_4, (outs),
1002 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
1003 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
1004 "\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr",
1007 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8">;
1008 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16">;
1009 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32">;
1011 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1012 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1013 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1015 // ...with double-spaced registers:
1016 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16">;
1017 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32">;
1019 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1020 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1022 // ...with address register writeback:
1023 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1024 : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1025 (ins addrmode6:$addr, am6offset:$offset,
1026 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1027 IIC_VST4lnu, "vst4", Dt,
1028 "\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr$offset",
1029 "$addr.addr = $wb", []>;
1031 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8">;
1032 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16">;
1033 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32">;
1035 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1036 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1037 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1039 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16">;
1040 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32">;
1042 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1043 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1045 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1048 //===----------------------------------------------------------------------===//
1049 // NEON pattern fragments
1050 //===----------------------------------------------------------------------===//
1052 // Extract D sub-registers of Q registers.
1053 def DSubReg_i8_reg : SDNodeXForm<imm, [{
1054 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1055 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
1057 def DSubReg_i16_reg : SDNodeXForm<imm, [{
1058 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1059 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
1061 def DSubReg_i32_reg : SDNodeXForm<imm, [{
1062 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1063 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
1065 def DSubReg_f64_reg : SDNodeXForm<imm, [{
1066 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1067 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
1070 // Extract S sub-registers of Q/D registers.
1071 def SSubReg_f32_reg : SDNodeXForm<imm, [{
1072 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
1073 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
1076 // Translate lane numbers from Q registers to D subregs.
1077 def SubReg_i8_lane : SDNodeXForm<imm, [{
1078 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
1080 def SubReg_i16_lane : SDNodeXForm<imm, [{
1081 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
1083 def SubReg_i32_lane : SDNodeXForm<imm, [{
1084 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
1087 //===----------------------------------------------------------------------===//
1088 // Instruction Classes
1089 //===----------------------------------------------------------------------===//
1091 // Basic 2-register operations: single-, double- and quad-register.
1092 class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1093 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1094 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1095 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
1096 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
1097 IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
1098 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1099 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1100 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1101 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1102 (ins DPR:$src), IIC_VUNAD, OpcodeStr, Dt,"$dst, $src", "",
1103 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
1104 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1105 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1106 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1107 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1108 (ins QPR:$src), IIC_VUNAQ, OpcodeStr, Dt,"$dst, $src", "",
1109 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
1111 // Basic 2-register intrinsics, both double- and quad-register.
1112 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1113 bits<2> op17_16, bits<5> op11_7, bit op4,
1114 InstrItinClass itin, string OpcodeStr, string Dt,
1115 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1116 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1117 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1118 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
1119 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1120 bits<2> op17_16, bits<5> op11_7, bit op4,
1121 InstrItinClass itin, string OpcodeStr, string Dt,
1122 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1123 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1124 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1125 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
1127 // Narrow 2-register operations.
1128 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1129 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1130 InstrItinClass itin, string OpcodeStr, string Dt,
1131 ValueType TyD, ValueType TyQ, SDNode OpNode>
1132 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
1133 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1134 [(set DPR:$dst, (TyD (OpNode (TyQ QPR:$src))))]>;
1136 // Narrow 2-register intrinsics.
1137 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1138 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1139 InstrItinClass itin, string OpcodeStr, string Dt,
1140 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
1141 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
1142 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1143 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
1145 // Long 2-register operations (currently only used for VMOVL).
1146 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1147 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1148 InstrItinClass itin, string OpcodeStr, string Dt,
1149 ValueType TyQ, ValueType TyD, SDNode OpNode>
1150 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$dst),
1151 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1152 [(set QPR:$dst, (TyQ (OpNode (TyD DPR:$src))))]>;
1154 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
1155 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
1156 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
1157 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
1158 OpcodeStr, Dt, "$dst1, $dst2",
1159 "$src1 = $dst1, $src2 = $dst2", []>;
1160 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
1161 InstrItinClass itin, string OpcodeStr, string Dt>
1162 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
1163 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$dst1, $dst2",
1164 "$src1 = $dst1, $src2 = $dst2", []>;
1166 // Basic 3-register operations: single-, double- and quad-register.
1167 class N3VS<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1168 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1169 SDNode OpNode, bit Commutable>
1170 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1171 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm,
1172 IIC_VBIND, OpcodeStr, Dt, "$dst, $src1, $src2", "", []> {
1173 let isCommutable = Commutable;
1176 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1177 InstrItinClass itin, string OpcodeStr, string Dt,
1178 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1179 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1180 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1181 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1182 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
1183 let isCommutable = Commutable;
1185 // Same as N3VD but no data type.
1186 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1187 InstrItinClass itin, string OpcodeStr,
1188 ValueType ResTy, ValueType OpTy,
1189 SDNode OpNode, bit Commutable>
1190 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
1191 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1192 OpcodeStr, "$dst, $src1, $src2", "",
1193 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]>{
1194 let isCommutable = Commutable;
1197 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
1198 InstrItinClass itin, string OpcodeStr, string Dt,
1199 ValueType Ty, SDNode ShOp>
1200 : N3V<0, 1, op21_20, op11_8, 1, 0,
1201 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1202 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1203 [(set (Ty DPR:$dst),
1204 (Ty (ShOp (Ty DPR:$src1),
1205 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),imm:$lane)))))]> {
1206 let isCommutable = 0;
1208 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
1209 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1210 : N3V<0, 1, op21_20, op11_8, 1, 0,
1211 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1212 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$dst, $src1, $src2[$lane]","",
1213 [(set (Ty DPR:$dst),
1214 (Ty (ShOp (Ty DPR:$src1),
1215 (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
1216 let isCommutable = 0;
1219 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1220 InstrItinClass itin, string OpcodeStr, string Dt,
1221 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1222 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1223 (outs QPR:$Qd), (ins QPR:$Qn, QPR:$Qm), N3RegFrm, itin,
1224 OpcodeStr, Dt, "$Qd, $Qn, $Qm", "",
1225 [(set QPR:$Qd, (ResTy (OpNode (OpTy QPR:$Qn), (OpTy QPR:$Qm))))]> {
1226 let isCommutable = Commutable;
1228 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1229 InstrItinClass itin, string OpcodeStr,
1230 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1231 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
1232 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, itin,
1233 OpcodeStr, "$dst, $src1, $src2", "",
1234 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]>{
1235 let isCommutable = Commutable;
1237 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
1238 InstrItinClass itin, string OpcodeStr, string Dt,
1239 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1240 : N3V<1, 1, op21_20, op11_8, 1, 0,
1241 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1242 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1243 [(set (ResTy QPR:$dst),
1244 (ResTy (ShOp (ResTy QPR:$src1),
1245 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1247 let isCommutable = 0;
1249 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
1250 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1251 : N3V<1, 1, op21_20, op11_8, 1, 0,
1252 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1253 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$dst, $src1, $src2[$lane]","",
1254 [(set (ResTy QPR:$dst),
1255 (ResTy (ShOp (ResTy QPR:$src1),
1256 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
1258 let isCommutable = 0;
1261 // Basic 3-register intrinsics, both double- and quad-register.
1262 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1263 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1264 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1265 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1266 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
1267 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1268 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
1269 let isCommutable = Commutable;
1271 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1272 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1273 : N3V<0, 1, op21_20, op11_8, 1, 0,
1274 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1275 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1276 [(set (Ty DPR:$dst),
1277 (Ty (IntOp (Ty DPR:$src1),
1278 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
1280 let isCommutable = 0;
1282 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1283 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1284 : N3V<0, 1, op21_20, op11_8, 1, 0,
1285 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1286 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1287 [(set (Ty DPR:$dst),
1288 (Ty (IntOp (Ty DPR:$src1),
1289 (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
1290 let isCommutable = 0;
1293 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1294 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1295 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1296 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1297 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
1298 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1299 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
1300 let isCommutable = Commutable;
1302 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1303 string OpcodeStr, string Dt,
1304 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1305 : N3V<1, 1, op21_20, op11_8, 1, 0,
1306 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1307 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1308 [(set (ResTy QPR:$dst),
1309 (ResTy (IntOp (ResTy QPR:$src1),
1310 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1312 let isCommutable = 0;
1314 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1315 string OpcodeStr, string Dt,
1316 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1317 : N3V<1, 1, op21_20, op11_8, 1, 0,
1318 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1319 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1320 [(set (ResTy QPR:$dst),
1321 (ResTy (IntOp (ResTy QPR:$src1),
1322 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
1324 let isCommutable = 0;
1327 // Multiply-Add/Sub operations: single-, double- and quad-register.
1328 class N3VSMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1329 InstrItinClass itin, string OpcodeStr, string Dt,
1330 ValueType Ty, SDNode MulOp, SDNode OpNode>
1331 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1332 (outs DPR_VFP2:$dst),
1333 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), N3RegFrm, itin,
1334 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst", []>;
1336 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1337 InstrItinClass itin, string OpcodeStr, string Dt,
1338 ValueType Ty, SDNode MulOp, SDNode OpNode>
1339 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1340 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1341 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1342 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
1343 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
1345 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1346 string OpcodeStr, string Dt,
1347 ValueType Ty, SDNode MulOp, SDNode ShOp>
1348 : N3V<0, 1, op21_20, op11_8, 1, 0,
1350 (ins DPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1352 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1353 [(set (Ty DPR:$dst),
1354 (Ty (ShOp (Ty DPR:$src1),
1355 (Ty (MulOp DPR:$src2,
1356 (Ty (NEONvduplane (Ty DPR_VFP2:$src3),
1358 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1359 string OpcodeStr, string Dt,
1360 ValueType Ty, SDNode MulOp, SDNode ShOp>
1361 : N3V<0, 1, op21_20, op11_8, 1, 0,
1363 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1365 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
1367 (Ty (ShOp (Ty DPR:$src1),
1369 (Ty (NEONvduplane (Ty DPR_8:$Vm),
1372 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1373 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
1374 SDNode MulOp, SDNode OpNode>
1375 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1376 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1377 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1378 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
1379 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
1380 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1381 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1382 SDNode MulOp, SDNode ShOp>
1383 : N3V<1, 1, op21_20, op11_8, 1, 0,
1385 (ins QPR:$src1, QPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1387 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1388 [(set (ResTy QPR:$dst),
1389 (ResTy (ShOp (ResTy QPR:$src1),
1390 (ResTy (MulOp QPR:$src2,
1391 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src3),
1393 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1394 string OpcodeStr, string Dt,
1395 ValueType ResTy, ValueType OpTy,
1396 SDNode MulOp, SDNode ShOp>
1397 : N3V<1, 1, op21_20, op11_8, 1, 0,
1399 (ins QPR:$src1, QPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1401 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1402 [(set (ResTy QPR:$dst),
1403 (ResTy (ShOp (ResTy QPR:$src1),
1404 (ResTy (MulOp QPR:$src2,
1405 (ResTy (NEONvduplane (OpTy DPR_8:$src3),
1408 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
1409 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1410 InstrItinClass itin, string OpcodeStr, string Dt,
1411 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
1412 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1413 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1414 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1415 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
1416 (Ty (IntOp (Ty DPR:$src2), (Ty DPR:$src3))))))]>;
1417 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1418 InstrItinClass itin, string OpcodeStr, string Dt,
1419 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
1420 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1421 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), N3RegFrm, itin,
1422 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1423 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
1424 (Ty (IntOp (Ty QPR:$src2), (Ty QPR:$src3))))))]>;
1426 // Neon 3-argument intrinsics, both double- and quad-register.
1427 // The destination register is also used as the first source operand register.
1428 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1429 InstrItinClass itin, string OpcodeStr, string Dt,
1430 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1431 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1432 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1433 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1434 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
1435 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
1436 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1437 InstrItinClass itin, string OpcodeStr, string Dt,
1438 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1439 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1440 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), N3RegFrm, itin,
1441 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1442 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
1443 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
1445 // Long Multiply-Add/Sub operations.
1446 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1447 InstrItinClass itin, string OpcodeStr, string Dt,
1448 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
1449 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1450 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1451 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1452 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
1453 (TyQ (MulOp (TyD DPR:$Vn),
1454 (TyD DPR:$Vm)))))]>;
1455 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
1456 InstrItinClass itin, string OpcodeStr, string Dt,
1457 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
1458 : N3V<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$dst),
1459 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1461 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1463 (OpNode (TyQ QPR:$src1),
1464 (TyQ (MulOp (TyD DPR:$src2),
1465 (TyD (NEONvduplane (TyD DPR_VFP2:$src3),
1467 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1468 InstrItinClass itin, string OpcodeStr, string Dt,
1469 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
1470 : N3V<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$dst),
1471 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1473 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1475 (OpNode (TyQ QPR:$src1),
1476 (TyQ (MulOp (TyD DPR:$src2),
1477 (TyD (NEONvduplane (TyD DPR_8:$src3),
1480 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
1481 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1482 InstrItinClass itin, string OpcodeStr, string Dt,
1483 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
1485 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1486 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1487 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1488 [(set QPR:$dst, (OpNode (TyQ QPR:$src1),
1489 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$src2),
1490 (TyD DPR:$src3)))))))]>;
1492 // Neon Long 3-argument intrinsic. The destination register is
1493 // a quad-register and is also used as the first source operand register.
1494 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1495 InstrItinClass itin, string OpcodeStr, string Dt,
1496 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
1497 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1498 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1499 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1501 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
1502 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1503 string OpcodeStr, string Dt,
1504 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1505 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1507 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1509 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1510 [(set (ResTy QPR:$dst),
1511 (ResTy (IntOp (ResTy QPR:$src1),
1513 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src3),
1515 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1516 InstrItinClass itin, string OpcodeStr, string Dt,
1517 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1518 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1520 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1522 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1523 [(set (ResTy QPR:$dst),
1524 (ResTy (IntOp (ResTy QPR:$src1),
1526 (OpTy (NEONvduplane (OpTy DPR_8:$src3),
1529 // Narrowing 3-register intrinsics.
1530 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1531 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
1532 Intrinsic IntOp, bit Commutable>
1533 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1534 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINi4D,
1535 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1536 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
1537 let isCommutable = Commutable;
1540 // Long 3-register operations.
1541 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1542 InstrItinClass itin, string OpcodeStr, string Dt,
1543 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
1544 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1545 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1546 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1547 [(set QPR:$dst, (TyQ (OpNode (TyD DPR:$src1), (TyD DPR:$src2))))]> {
1548 let isCommutable = Commutable;
1550 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
1551 InstrItinClass itin, string OpcodeStr, string Dt,
1552 ValueType TyQ, ValueType TyD, SDNode OpNode>
1553 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1554 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1555 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1557 (TyQ (OpNode (TyD DPR:$src1),
1558 (TyD (NEONvduplane (TyD DPR_VFP2:$src2),imm:$lane)))))]>;
1559 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1560 InstrItinClass itin, string OpcodeStr, string Dt,
1561 ValueType TyQ, ValueType TyD, SDNode OpNode>
1562 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1563 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1564 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1566 (TyQ (OpNode (TyD DPR:$src1),
1567 (TyD (NEONvduplane (TyD DPR_8:$src2), imm:$lane)))))]>;
1569 // Long 3-register operations with explicitly extended operands.
1570 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1571 InstrItinClass itin, string OpcodeStr, string Dt,
1572 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
1574 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1575 (outs QPR:$Qd), (ins DPR:$Dn, DPR:$Dm), N3RegFrm, itin,
1576 OpcodeStr, Dt, "$Qd, $Dn, $Dm", "",
1577 [(set QPR:$Qd, (OpNode (TyQ (ExtOp (TyD DPR:$Dn))),
1578 (TyQ (ExtOp (TyD DPR:$Dm)))))]> {
1579 let isCommutable = Commutable;
1582 // Long 3-register intrinsics with explicit extend (VABDL).
1583 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1584 InstrItinClass itin, string OpcodeStr, string Dt,
1585 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
1587 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1588 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1589 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1590 [(set QPR:$dst, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$src1),
1591 (TyD DPR:$src2))))))]> {
1592 let isCommutable = Commutable;
1595 // Long 3-register intrinsics.
1596 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1597 InstrItinClass itin, string OpcodeStr, string Dt,
1598 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
1599 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1600 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1601 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1602 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
1603 let isCommutable = Commutable;
1605 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1606 string OpcodeStr, string Dt,
1607 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1608 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1609 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1610 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1611 [(set (ResTy QPR:$dst),
1612 (ResTy (IntOp (OpTy DPR:$src1),
1613 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1615 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1616 InstrItinClass itin, string OpcodeStr, string Dt,
1617 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1618 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1619 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1620 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1621 [(set (ResTy QPR:$dst),
1622 (ResTy (IntOp (OpTy DPR:$src1),
1623 (OpTy (NEONvduplane (OpTy DPR_8:$src2),
1626 // Wide 3-register operations.
1627 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1628 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
1629 SDNode OpNode, SDNode ExtOp, bit Commutable>
1630 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1631 (outs QPR:$Qd), (ins QPR:$Qn, DPR:$Dm), N3RegFrm, IIC_VSUBiD,
1632 OpcodeStr, Dt, "$Qd, $Qn, $Dm", "",
1633 [(set QPR:$Qd, (OpNode (TyQ QPR:$Qn),
1634 (TyQ (ExtOp (TyD DPR:$Dm)))))]> {
1635 let isCommutable = Commutable;
1638 // Pairwise long 2-register intrinsics, both double- and quad-register.
1639 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1640 bits<2> op17_16, bits<5> op11_7, bit op4,
1641 string OpcodeStr, string Dt,
1642 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1643 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1644 (ins DPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
1645 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
1646 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1647 bits<2> op17_16, bits<5> op11_7, bit op4,
1648 string OpcodeStr, string Dt,
1649 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1650 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1651 (ins QPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
1652 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
1654 // Pairwise long 2-register accumulate intrinsics,
1655 // both double- and quad-register.
1656 // The destination register is also used as the first source operand register.
1657 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1658 bits<2> op17_16, bits<5> op11_7, bit op4,
1659 string OpcodeStr, string Dt,
1660 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1661 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
1662 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), IIC_VPALiD,
1663 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
1664 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
1665 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1666 bits<2> op17_16, bits<5> op11_7, bit op4,
1667 string OpcodeStr, string Dt,
1668 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1669 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
1670 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VPALiQ,
1671 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
1672 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
1674 // Shift by immediate,
1675 // both double- and quad-register.
1676 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1677 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1678 ValueType Ty, SDNode OpNode>
1679 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1680 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), f, itin,
1681 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1682 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
1683 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1684 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1685 ValueType Ty, SDNode OpNode>
1686 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1687 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), f, itin,
1688 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1689 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
1691 // Long shift by immediate.
1692 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1693 string OpcodeStr, string Dt,
1694 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1695 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1696 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), N2RegVShLFrm,
1697 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1698 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
1699 (i32 imm:$SIMM))))]>;
1701 // Narrow shift by immediate.
1702 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1703 InstrItinClass itin, string OpcodeStr, string Dt,
1704 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1705 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1706 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), N2RegVShRFrm, itin,
1707 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1708 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
1709 (i32 imm:$SIMM))))]>;
1711 // Shift right by immediate and accumulate,
1712 // both double- and quad-register.
1713 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1714 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1715 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1716 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
1717 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1718 [(set DPR:$dst, (Ty (add DPR:$src1,
1719 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
1720 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1721 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1722 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1723 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
1724 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1725 [(set QPR:$dst, (Ty (add QPR:$src1,
1726 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
1728 // Shift by immediate and insert,
1729 // both double- and quad-register.
1730 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1731 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
1732 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1733 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), f, IIC_VSHLiD,
1734 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1735 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
1736 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1737 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
1738 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1739 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), f, IIC_VSHLiQ,
1740 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1741 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
1743 // Convert, with fractional bits immediate,
1744 // both double- and quad-register.
1745 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1746 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1748 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1749 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NVCVTFrm,
1750 IIC_VUNAD, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1751 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
1752 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1753 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1755 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1756 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NVCVTFrm,
1757 IIC_VUNAQ, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1758 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
1760 //===----------------------------------------------------------------------===//
1762 //===----------------------------------------------------------------------===//
1764 // Abbreviations used in multiclass suffixes:
1765 // Q = quarter int (8 bit) elements
1766 // H = half int (16 bit) elements
1767 // S = single int (32 bit) elements
1768 // D = double int (64 bit) elements
1770 // Neon 2-register vector operations -- for disassembly only.
1772 // First with only element sizes of 8, 16 and 32 bits:
1773 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1774 bits<5> op11_7, bit op4, string opc, string Dt,
1776 // 64-bit vector types.
1777 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
1778 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1779 opc, !strconcat(Dt, "8"), asm, "", []>;
1780 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
1781 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1782 opc, !strconcat(Dt, "16"), asm, "", []>;
1783 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
1784 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1785 opc, !strconcat(Dt, "32"), asm, "", []>;
1786 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
1787 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1788 opc, "f32", asm, "", []> {
1789 let Inst{10} = 1; // overwrite F = 1
1792 // 128-bit vector types.
1793 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
1794 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1795 opc, !strconcat(Dt, "8"), asm, "", []>;
1796 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
1797 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1798 opc, !strconcat(Dt, "16"), asm, "", []>;
1799 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
1800 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1801 opc, !strconcat(Dt, "32"), asm, "", []>;
1802 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
1803 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1804 opc, "f32", asm, "", []> {
1805 let Inst{10} = 1; // overwrite F = 1
1809 // Neon 3-register vector operations.
1811 // First with only element sizes of 8, 16 and 32 bits:
1812 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1813 InstrItinClass itinD16, InstrItinClass itinD32,
1814 InstrItinClass itinQ16, InstrItinClass itinQ32,
1815 string OpcodeStr, string Dt,
1816 SDNode OpNode, bit Commutable = 0> {
1817 // 64-bit vector types.
1818 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
1819 OpcodeStr, !strconcat(Dt, "8"),
1820 v8i8, v8i8, OpNode, Commutable>;
1821 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
1822 OpcodeStr, !strconcat(Dt, "16"),
1823 v4i16, v4i16, OpNode, Commutable>;
1824 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
1825 OpcodeStr, !strconcat(Dt, "32"),
1826 v2i32, v2i32, OpNode, Commutable>;
1828 // 128-bit vector types.
1829 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
1830 OpcodeStr, !strconcat(Dt, "8"),
1831 v16i8, v16i8, OpNode, Commutable>;
1832 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
1833 OpcodeStr, !strconcat(Dt, "16"),
1834 v8i16, v8i16, OpNode, Commutable>;
1835 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
1836 OpcodeStr, !strconcat(Dt, "32"),
1837 v4i32, v4i32, OpNode, Commutable>;
1840 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
1841 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1843 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
1845 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1846 v8i16, v4i16, ShOp>;
1847 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
1848 v4i32, v2i32, ShOp>;
1851 // ....then also with element size 64 bits:
1852 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1853 InstrItinClass itinD, InstrItinClass itinQ,
1854 string OpcodeStr, string Dt,
1855 SDNode OpNode, bit Commutable = 0>
1856 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
1857 OpcodeStr, Dt, OpNode, Commutable> {
1858 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
1859 OpcodeStr, !strconcat(Dt, "64"),
1860 v1i64, v1i64, OpNode, Commutable>;
1861 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
1862 OpcodeStr, !strconcat(Dt, "64"),
1863 v2i64, v2i64, OpNode, Commutable>;
1867 // Neon Narrowing 2-register vector operations,
1868 // source operand element sizes of 16, 32 and 64 bits:
1869 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1870 bits<5> op11_7, bit op6, bit op4,
1871 InstrItinClass itin, string OpcodeStr, string Dt,
1873 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
1874 itin, OpcodeStr, !strconcat(Dt, "16"),
1875 v8i8, v8i16, OpNode>;
1876 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
1877 itin, OpcodeStr, !strconcat(Dt, "32"),
1878 v4i16, v4i32, OpNode>;
1879 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
1880 itin, OpcodeStr, !strconcat(Dt, "64"),
1881 v2i32, v2i64, OpNode>;
1884 // Neon Narrowing 2-register vector intrinsics,
1885 // source operand element sizes of 16, 32 and 64 bits:
1886 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1887 bits<5> op11_7, bit op6, bit op4,
1888 InstrItinClass itin, string OpcodeStr, string Dt,
1890 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
1891 itin, OpcodeStr, !strconcat(Dt, "16"),
1892 v8i8, v8i16, IntOp>;
1893 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
1894 itin, OpcodeStr, !strconcat(Dt, "32"),
1895 v4i16, v4i32, IntOp>;
1896 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
1897 itin, OpcodeStr, !strconcat(Dt, "64"),
1898 v2i32, v2i64, IntOp>;
1902 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
1903 // source operand element sizes of 16, 32 and 64 bits:
1904 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
1905 string OpcodeStr, string Dt, SDNode OpNode> {
1906 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1907 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
1908 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1909 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
1910 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1911 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
1915 // Neon 3-register vector intrinsics.
1917 // First with only element sizes of 16 and 32 bits:
1918 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
1919 InstrItinClass itinD16, InstrItinClass itinD32,
1920 InstrItinClass itinQ16, InstrItinClass itinQ32,
1921 string OpcodeStr, string Dt,
1922 Intrinsic IntOp, bit Commutable = 0> {
1923 // 64-bit vector types.
1924 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
1925 OpcodeStr, !strconcat(Dt, "16"),
1926 v4i16, v4i16, IntOp, Commutable>;
1927 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
1928 OpcodeStr, !strconcat(Dt, "32"),
1929 v2i32, v2i32, IntOp, Commutable>;
1931 // 128-bit vector types.
1932 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
1933 OpcodeStr, !strconcat(Dt, "16"),
1934 v8i16, v8i16, IntOp, Commutable>;
1935 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
1936 OpcodeStr, !strconcat(Dt, "32"),
1937 v4i32, v4i32, IntOp, Commutable>;
1940 multiclass N3VIntSL_HS<bits<4> op11_8,
1941 InstrItinClass itinD16, InstrItinClass itinD32,
1942 InstrItinClass itinQ16, InstrItinClass itinQ32,
1943 string OpcodeStr, string Dt, Intrinsic IntOp> {
1944 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
1945 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
1946 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
1947 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
1948 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
1949 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
1950 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
1951 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
1954 // ....then also with element size of 8 bits:
1955 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
1956 InstrItinClass itinD16, InstrItinClass itinD32,
1957 InstrItinClass itinQ16, InstrItinClass itinQ32,
1958 string OpcodeStr, string Dt,
1959 Intrinsic IntOp, bit Commutable = 0>
1960 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
1961 OpcodeStr, Dt, IntOp, Commutable> {
1962 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
1963 OpcodeStr, !strconcat(Dt, "8"),
1964 v8i8, v8i8, IntOp, Commutable>;
1965 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
1966 OpcodeStr, !strconcat(Dt, "8"),
1967 v16i8, v16i8, IntOp, Commutable>;
1970 // ....then also with element size of 64 bits:
1971 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
1972 InstrItinClass itinD16, InstrItinClass itinD32,
1973 InstrItinClass itinQ16, InstrItinClass itinQ32,
1974 string OpcodeStr, string Dt,
1975 Intrinsic IntOp, bit Commutable = 0>
1976 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
1977 OpcodeStr, Dt, IntOp, Commutable> {
1978 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
1979 OpcodeStr, !strconcat(Dt, "64"),
1980 v1i64, v1i64, IntOp, Commutable>;
1981 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
1982 OpcodeStr, !strconcat(Dt, "64"),
1983 v2i64, v2i64, IntOp, Commutable>;
1986 // Neon Narrowing 3-register vector intrinsics,
1987 // source operand element sizes of 16, 32 and 64 bits:
1988 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1989 string OpcodeStr, string Dt,
1990 Intrinsic IntOp, bit Commutable = 0> {
1991 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
1992 OpcodeStr, !strconcat(Dt, "16"),
1993 v8i8, v8i16, IntOp, Commutable>;
1994 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
1995 OpcodeStr, !strconcat(Dt, "32"),
1996 v4i16, v4i32, IntOp, Commutable>;
1997 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
1998 OpcodeStr, !strconcat(Dt, "64"),
1999 v2i32, v2i64, IntOp, Commutable>;
2003 // Neon Long 3-register vector operations.
2005 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2006 InstrItinClass itin16, InstrItinClass itin32,
2007 string OpcodeStr, string Dt,
2008 SDNode OpNode, bit Commutable = 0> {
2009 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
2010 OpcodeStr, !strconcat(Dt, "8"),
2011 v8i16, v8i8, OpNode, Commutable>;
2012 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
2013 OpcodeStr, !strconcat(Dt, "16"),
2014 v4i32, v4i16, OpNode, Commutable>;
2015 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
2016 OpcodeStr, !strconcat(Dt, "32"),
2017 v2i64, v2i32, OpNode, Commutable>;
2020 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
2021 InstrItinClass itin, string OpcodeStr, string Dt,
2023 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
2024 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2025 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
2026 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2029 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2030 InstrItinClass itin16, InstrItinClass itin32,
2031 string OpcodeStr, string Dt,
2032 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2033 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
2034 OpcodeStr, !strconcat(Dt, "8"),
2035 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2036 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
2037 OpcodeStr, !strconcat(Dt, "16"),
2038 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2039 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
2040 OpcodeStr, !strconcat(Dt, "32"),
2041 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2044 // Neon Long 3-register vector intrinsics.
2046 // First with only element sizes of 16 and 32 bits:
2047 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2048 InstrItinClass itin16, InstrItinClass itin32,
2049 string OpcodeStr, string Dt,
2050 Intrinsic IntOp, bit Commutable = 0> {
2051 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
2052 OpcodeStr, !strconcat(Dt, "16"),
2053 v4i32, v4i16, IntOp, Commutable>;
2054 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
2055 OpcodeStr, !strconcat(Dt, "32"),
2056 v2i64, v2i32, IntOp, Commutable>;
2059 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
2060 InstrItinClass itin, string OpcodeStr, string Dt,
2062 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
2063 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2064 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
2065 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2068 // ....then also with element size of 8 bits:
2069 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2070 InstrItinClass itin16, InstrItinClass itin32,
2071 string OpcodeStr, string Dt,
2072 Intrinsic IntOp, bit Commutable = 0>
2073 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
2074 IntOp, Commutable> {
2075 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
2076 OpcodeStr, !strconcat(Dt, "8"),
2077 v8i16, v8i8, IntOp, Commutable>;
2080 // ....with explicit extend (VABDL).
2081 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2082 InstrItinClass itin, string OpcodeStr, string Dt,
2083 Intrinsic IntOp, SDNode ExtOp, bit Commutable = 0> {
2084 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
2085 OpcodeStr, !strconcat(Dt, "8"),
2086 v8i16, v8i8, IntOp, ExtOp, Commutable>;
2087 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
2088 OpcodeStr, !strconcat(Dt, "16"),
2089 v4i32, v4i16, IntOp, ExtOp, Commutable>;
2090 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
2091 OpcodeStr, !strconcat(Dt, "32"),
2092 v2i64, v2i32, IntOp, ExtOp, Commutable>;
2096 // Neon Wide 3-register vector intrinsics,
2097 // source operand element sizes of 8, 16 and 32 bits:
2098 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2099 string OpcodeStr, string Dt,
2100 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2101 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
2102 OpcodeStr, !strconcat(Dt, "8"),
2103 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2104 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
2105 OpcodeStr, !strconcat(Dt, "16"),
2106 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2107 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
2108 OpcodeStr, !strconcat(Dt, "32"),
2109 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2113 // Neon Multiply-Op vector operations,
2114 // element sizes of 8, 16 and 32 bits:
2115 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2116 InstrItinClass itinD16, InstrItinClass itinD32,
2117 InstrItinClass itinQ16, InstrItinClass itinQ32,
2118 string OpcodeStr, string Dt, SDNode OpNode> {
2119 // 64-bit vector types.
2120 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
2121 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
2122 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
2123 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
2124 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
2125 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
2127 // 128-bit vector types.
2128 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
2129 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
2130 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
2131 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
2132 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
2133 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
2136 multiclass N3VMulOpSL_HS<bits<4> op11_8,
2137 InstrItinClass itinD16, InstrItinClass itinD32,
2138 InstrItinClass itinQ16, InstrItinClass itinQ32,
2139 string OpcodeStr, string Dt, SDNode ShOp> {
2140 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
2141 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
2142 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
2143 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
2144 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
2145 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
2147 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
2148 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
2152 // Neon Intrinsic-Op vector operations,
2153 // element sizes of 8, 16 and 32 bits:
2154 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2155 InstrItinClass itinD, InstrItinClass itinQ,
2156 string OpcodeStr, string Dt, Intrinsic IntOp,
2158 // 64-bit vector types.
2159 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
2160 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
2161 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
2162 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
2163 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
2164 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
2166 // 128-bit vector types.
2167 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
2168 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
2169 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
2170 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
2171 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
2172 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
2175 // Neon 3-argument intrinsics,
2176 // element sizes of 8, 16 and 32 bits:
2177 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2178 InstrItinClass itinD, InstrItinClass itinQ,
2179 string OpcodeStr, string Dt, Intrinsic IntOp> {
2180 // 64-bit vector types.
2181 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
2182 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2183 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
2184 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
2185 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
2186 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
2188 // 128-bit vector types.
2189 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
2190 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
2191 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
2192 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
2193 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
2194 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
2198 // Neon Long Multiply-Op vector operations,
2199 // element sizes of 8, 16 and 32 bits:
2200 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2201 InstrItinClass itin16, InstrItinClass itin32,
2202 string OpcodeStr, string Dt, SDNode MulOp,
2204 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
2205 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
2206 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
2207 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
2208 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
2209 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
2212 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
2213 string Dt, SDNode MulOp, SDNode OpNode> {
2214 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
2215 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
2216 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
2217 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
2221 // Neon Long 3-argument intrinsics.
2223 // First with only element sizes of 16 and 32 bits:
2224 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2225 InstrItinClass itin16, InstrItinClass itin32,
2226 string OpcodeStr, string Dt, Intrinsic IntOp> {
2227 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
2228 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2229 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
2230 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2233 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
2234 string OpcodeStr, string Dt, Intrinsic IntOp> {
2235 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
2236 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
2237 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
2238 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2241 // ....then also with element size of 8 bits:
2242 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2243 InstrItinClass itin16, InstrItinClass itin32,
2244 string OpcodeStr, string Dt, Intrinsic IntOp>
2245 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
2246 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
2247 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
2250 // ....with explicit extend (VABAL).
2251 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2252 InstrItinClass itin, string OpcodeStr, string Dt,
2253 Intrinsic IntOp, SDNode ExtOp, SDNode OpNode> {
2254 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
2255 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
2256 IntOp, ExtOp, OpNode>;
2257 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
2258 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
2259 IntOp, ExtOp, OpNode>;
2260 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
2261 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
2262 IntOp, ExtOp, OpNode>;
2266 // Neon 2-register vector intrinsics,
2267 // element sizes of 8, 16 and 32 bits:
2268 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2269 bits<5> op11_7, bit op4,
2270 InstrItinClass itinD, InstrItinClass itinQ,
2271 string OpcodeStr, string Dt, Intrinsic IntOp> {
2272 // 64-bit vector types.
2273 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2274 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2275 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2276 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
2277 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2278 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
2280 // 128-bit vector types.
2281 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2282 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
2283 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2284 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
2285 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2286 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
2290 // Neon Pairwise long 2-register intrinsics,
2291 // element sizes of 8, 16 and 32 bits:
2292 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2293 bits<5> op11_7, bit op4,
2294 string OpcodeStr, string Dt, Intrinsic IntOp> {
2295 // 64-bit vector types.
2296 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2297 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
2298 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2299 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
2300 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2301 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
2303 // 128-bit vector types.
2304 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2305 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
2306 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2307 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
2308 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2309 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
2313 // Neon Pairwise long 2-register accumulate intrinsics,
2314 // element sizes of 8, 16 and 32 bits:
2315 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2316 bits<5> op11_7, bit op4,
2317 string OpcodeStr, string Dt, Intrinsic IntOp> {
2318 // 64-bit vector types.
2319 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2320 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
2321 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2322 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
2323 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2324 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
2326 // 128-bit vector types.
2327 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2328 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
2329 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2330 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
2331 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2332 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
2336 // Neon 2-register vector shift by immediate,
2337 // with f of either N2RegVShLFrm or N2RegVShRFrm
2338 // element sizes of 8, 16, 32 and 64 bits:
2339 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2340 InstrItinClass itin, string OpcodeStr, string Dt,
2341 SDNode OpNode, Format f> {
2342 // 64-bit vector types.
2343 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2344 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
2345 let Inst{21-19} = 0b001; // imm6 = 001xxx
2347 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2348 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
2349 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2351 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2352 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
2353 let Inst{21} = 0b1; // imm6 = 1xxxxx
2355 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, f, itin,
2356 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
2359 // 128-bit vector types.
2360 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
2361 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
2362 let Inst{21-19} = 0b001; // imm6 = 001xxx
2364 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
2365 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
2366 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2368 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
2369 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
2370 let Inst{21} = 0b1; // imm6 = 1xxxxx
2372 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, f, itin,
2373 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
2377 // Neon Shift-Accumulate vector operations,
2378 // element sizes of 8, 16, 32 and 64 bits:
2379 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2380 string OpcodeStr, string Dt, SDNode ShOp> {
2381 // 64-bit vector types.
2382 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4,
2383 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
2384 let Inst{21-19} = 0b001; // imm6 = 001xxx
2386 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4,
2387 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
2388 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2390 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4,
2391 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
2392 let Inst{21} = 0b1; // imm6 = 1xxxxx
2394 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4,
2395 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
2398 // 128-bit vector types.
2399 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4,
2400 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
2401 let Inst{21-19} = 0b001; // imm6 = 001xxx
2403 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4,
2404 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
2405 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2407 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4,
2408 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
2409 let Inst{21} = 0b1; // imm6 = 1xxxxx
2411 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4,
2412 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
2417 // Neon Shift-Insert vector operations,
2418 // with f of either N2RegVShLFrm or N2RegVShRFrm
2419 // element sizes of 8, 16, 32 and 64 bits:
2420 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2421 string OpcodeStr, SDNode ShOp,
2423 // 64-bit vector types.
2424 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4,
2425 f, OpcodeStr, "8", v8i8, ShOp> {
2426 let Inst{21-19} = 0b001; // imm6 = 001xxx
2428 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4,
2429 f, OpcodeStr, "16", v4i16, ShOp> {
2430 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2432 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4,
2433 f, OpcodeStr, "32", v2i32, ShOp> {
2434 let Inst{21} = 0b1; // imm6 = 1xxxxx
2436 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4,
2437 f, OpcodeStr, "64", v1i64, ShOp>;
2440 // 128-bit vector types.
2441 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4,
2442 f, OpcodeStr, "8", v16i8, ShOp> {
2443 let Inst{21-19} = 0b001; // imm6 = 001xxx
2445 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4,
2446 f, OpcodeStr, "16", v8i16, ShOp> {
2447 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2449 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4,
2450 f, OpcodeStr, "32", v4i32, ShOp> {
2451 let Inst{21} = 0b1; // imm6 = 1xxxxx
2453 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4,
2454 f, OpcodeStr, "64", v2i64, ShOp>;
2458 // Neon Shift Long operations,
2459 // element sizes of 8, 16, 32 bits:
2460 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
2461 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
2462 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
2463 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
2464 let Inst{21-19} = 0b001; // imm6 = 001xxx
2466 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
2467 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
2468 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2470 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
2471 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
2472 let Inst{21} = 0b1; // imm6 = 1xxxxx
2476 // Neon Shift Narrow operations,
2477 // element sizes of 16, 32, 64 bits:
2478 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
2479 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
2481 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
2482 OpcodeStr, !strconcat(Dt, "16"), v8i8, v8i16, OpNode> {
2483 let Inst{21-19} = 0b001; // imm6 = 001xxx
2485 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
2486 OpcodeStr, !strconcat(Dt, "32"), v4i16, v4i32, OpNode> {
2487 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2489 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
2490 OpcodeStr, !strconcat(Dt, "64"), v2i32, v2i64, OpNode> {
2491 let Inst{21} = 0b1; // imm6 = 1xxxxx
2495 //===----------------------------------------------------------------------===//
2496 // Instruction Definitions.
2497 //===----------------------------------------------------------------------===//
2499 // Vector Add Operations.
2501 // VADD : Vector Add (integer and floating-point)
2502 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
2504 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
2505 v2f32, v2f32, fadd, 1>;
2506 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
2507 v4f32, v4f32, fadd, 1>;
2508 // VADDL : Vector Add Long (Q = D + D)
2509 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
2510 "vaddl", "s", add, sext, 1>;
2511 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
2512 "vaddl", "u", add, zext, 1>;
2513 // VADDW : Vector Add Wide (Q = Q + D)
2514 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
2515 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
2516 // VHADD : Vector Halving Add
2517 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
2518 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2519 "vhadd", "s", int_arm_neon_vhadds, 1>;
2520 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
2521 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2522 "vhadd", "u", int_arm_neon_vhaddu, 1>;
2523 // VRHADD : Vector Rounding Halving Add
2524 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
2525 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2526 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
2527 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
2528 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2529 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
2530 // VQADD : Vector Saturating Add
2531 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
2532 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2533 "vqadd", "s", int_arm_neon_vqadds, 1>;
2534 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
2535 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2536 "vqadd", "u", int_arm_neon_vqaddu, 1>;
2537 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
2538 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
2539 int_arm_neon_vaddhn, 1>;
2540 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
2541 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
2542 int_arm_neon_vraddhn, 1>;
2544 // Vector Multiply Operations.
2546 // VMUL : Vector Multiply (integer, polynomial and floating-point)
2547 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
2548 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
2549 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
2550 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
2551 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
2552 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
2553 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
2554 v2f32, v2f32, fmul, 1>;
2555 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
2556 v4f32, v4f32, fmul, 1>;
2557 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
2558 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
2559 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
2562 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
2563 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
2564 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
2565 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2566 (DSubReg_i16_reg imm:$lane))),
2567 (SubReg_i16_lane imm:$lane)))>;
2568 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
2569 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
2570 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
2571 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2572 (DSubReg_i32_reg imm:$lane))),
2573 (SubReg_i32_lane imm:$lane)))>;
2574 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
2575 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
2576 (v4f32 (VMULslfq (v4f32 QPR:$src1),
2577 (v2f32 (EXTRACT_SUBREG QPR:$src2,
2578 (DSubReg_i32_reg imm:$lane))),
2579 (SubReg_i32_lane imm:$lane)))>;
2581 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
2582 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
2583 IIC_VMULi16Q, IIC_VMULi32Q,
2584 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
2585 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
2586 IIC_VMULi16Q, IIC_VMULi32Q,
2587 "vqdmulh", "s", int_arm_neon_vqdmulh>;
2588 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
2589 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
2591 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
2592 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2593 (DSubReg_i16_reg imm:$lane))),
2594 (SubReg_i16_lane imm:$lane)))>;
2595 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
2596 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
2598 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
2599 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2600 (DSubReg_i32_reg imm:$lane))),
2601 (SubReg_i32_lane imm:$lane)))>;
2603 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
2604 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
2605 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
2606 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
2607 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
2608 IIC_VMULi16Q, IIC_VMULi32Q,
2609 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
2610 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
2611 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
2613 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
2614 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2615 (DSubReg_i16_reg imm:$lane))),
2616 (SubReg_i16_lane imm:$lane)))>;
2617 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
2618 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
2620 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
2621 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2622 (DSubReg_i32_reg imm:$lane))),
2623 (SubReg_i32_lane imm:$lane)))>;
2625 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
2626 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
2627 "vmull", "s", NEONvmulls, 1>;
2628 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
2629 "vmull", "u", NEONvmullu, 1>;
2630 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
2631 v8i16, v8i8, int_arm_neon_vmullp, 1>;
2632 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
2633 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
2635 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
2636 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
2637 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
2638 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
2639 "vqdmull", "s", int_arm_neon_vqdmull>;
2641 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
2643 // VMLA : Vector Multiply Accumulate (integer and floating-point)
2644 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
2645 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
2646 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
2648 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
2650 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
2651 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
2652 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
2654 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
2655 v4f32, v2f32, fmul, fadd>;
2657 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
2658 (mul (v8i16 QPR:$src2),
2659 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
2660 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
2661 (v4i16 (EXTRACT_SUBREG QPR:$src3,
2662 (DSubReg_i16_reg imm:$lane))),
2663 (SubReg_i16_lane imm:$lane)))>;
2665 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
2666 (mul (v4i32 QPR:$src2),
2667 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
2668 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
2669 (v2i32 (EXTRACT_SUBREG QPR:$src3,
2670 (DSubReg_i32_reg imm:$lane))),
2671 (SubReg_i32_lane imm:$lane)))>;
2673 def : Pat<(v4f32 (fadd (v4f32 QPR:$src1),
2674 (fmul (v4f32 QPR:$src2),
2675 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
2676 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
2678 (v2f32 (EXTRACT_SUBREG QPR:$src3,
2679 (DSubReg_i32_reg imm:$lane))),
2680 (SubReg_i32_lane imm:$lane)))>;
2682 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
2683 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
2684 "vmlal", "s", NEONvmulls, add>;
2685 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
2686 "vmlal", "u", NEONvmullu, add>;
2688 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
2689 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
2691 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
2692 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
2693 "vqdmlal", "s", int_arm_neon_vqdmlal>;
2694 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
2696 // VMLS : Vector Multiply Subtract (integer and floating-point)
2697 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
2698 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
2699 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
2701 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
2703 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
2704 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
2705 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
2707 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
2708 v4f32, v2f32, fmul, fsub>;
2710 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
2711 (mul (v8i16 QPR:$src2),
2712 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
2713 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
2714 (v4i16 (EXTRACT_SUBREG QPR:$src3,
2715 (DSubReg_i16_reg imm:$lane))),
2716 (SubReg_i16_lane imm:$lane)))>;
2718 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
2719 (mul (v4i32 QPR:$src2),
2720 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
2721 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
2722 (v2i32 (EXTRACT_SUBREG QPR:$src3,
2723 (DSubReg_i32_reg imm:$lane))),
2724 (SubReg_i32_lane imm:$lane)))>;
2726 def : Pat<(v4f32 (fsub (v4f32 QPR:$src1),
2727 (fmul (v4f32 QPR:$src2),
2728 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
2729 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
2730 (v2f32 (EXTRACT_SUBREG QPR:$src3,
2731 (DSubReg_i32_reg imm:$lane))),
2732 (SubReg_i32_lane imm:$lane)))>;
2734 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
2735 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
2736 "vmlsl", "s", NEONvmulls, sub>;
2737 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
2738 "vmlsl", "u", NEONvmullu, sub>;
2740 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
2741 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
2743 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
2744 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
2745 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
2746 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
2748 // Vector Subtract Operations.
2750 // VSUB : Vector Subtract (integer and floating-point)
2751 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
2752 "vsub", "i", sub, 0>;
2753 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
2754 v2f32, v2f32, fsub, 0>;
2755 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
2756 v4f32, v4f32, fsub, 0>;
2757 // VSUBL : Vector Subtract Long (Q = D - D)
2758 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
2759 "vsubl", "s", sub, sext, 0>;
2760 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
2761 "vsubl", "u", sub, zext, 0>;
2762 // VSUBW : Vector Subtract Wide (Q = Q - D)
2763 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
2764 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
2765 // VHSUB : Vector Halving Subtract
2766 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
2767 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2768 "vhsub", "s", int_arm_neon_vhsubs, 0>;
2769 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
2770 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2771 "vhsub", "u", int_arm_neon_vhsubu, 0>;
2772 // VQSUB : Vector Saturing Subtract
2773 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
2774 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2775 "vqsub", "s", int_arm_neon_vqsubs, 0>;
2776 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
2777 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2778 "vqsub", "u", int_arm_neon_vqsubu, 0>;
2779 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
2780 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
2781 int_arm_neon_vsubhn, 0>;
2782 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
2783 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
2784 int_arm_neon_vrsubhn, 0>;
2786 // Vector Comparisons.
2788 // VCEQ : Vector Compare Equal
2789 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2790 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
2791 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
2793 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
2795 // For disassembly only.
2796 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
2799 // VCGE : Vector Compare Greater Than or Equal
2800 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2801 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
2802 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2803 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
2804 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
2806 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
2808 // For disassembly only.
2809 // FIXME: This instruction's encoding MAY NOT BE correct.
2810 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
2812 // For disassembly only.
2813 // FIXME: This instruction's encoding MAY NOT BE correct.
2814 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
2817 // VCGT : Vector Compare Greater Than
2818 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2819 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
2820 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2821 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
2822 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
2824 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
2826 // For disassembly only.
2827 // FIXME: This instruction's encoding MAY NOT BE correct.
2828 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
2830 // For disassembly only.
2831 // FIXME: This instruction's encoding MAY NOT BE correct.
2832 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
2835 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
2836 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
2837 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
2838 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
2839 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
2840 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
2841 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
2842 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
2843 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
2844 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
2845 // VTST : Vector Test Bits
2846 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2847 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
2849 // Vector Bitwise Operations.
2851 def vnotd : PatFrag<(ops node:$in),
2852 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
2853 def vnotq : PatFrag<(ops node:$in),
2854 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
2857 // VAND : Vector Bitwise AND
2858 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
2859 v2i32, v2i32, and, 1>;
2860 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
2861 v4i32, v4i32, and, 1>;
2863 // VEOR : Vector Bitwise Exclusive OR
2864 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
2865 v2i32, v2i32, xor, 1>;
2866 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
2867 v4i32, v4i32, xor, 1>;
2869 // VORR : Vector Bitwise OR
2870 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
2871 v2i32, v2i32, or, 1>;
2872 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
2873 v4i32, v4i32, or, 1>;
2875 // VBIC : Vector Bitwise Bit Clear (AND NOT)
2876 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2877 (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD,
2878 "vbic", "$dst, $src1, $src2", "",
2879 [(set DPR:$dst, (v2i32 (and DPR:$src1,
2880 (vnotd DPR:$src2))))]>;
2881 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2882 (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINiQ,
2883 "vbic", "$dst, $src1, $src2", "",
2884 [(set QPR:$dst, (v4i32 (and QPR:$src1,
2885 (vnotq QPR:$src2))))]>;
2887 // VORN : Vector Bitwise OR NOT
2888 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
2889 (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD,
2890 "vorn", "$dst, $src1, $src2", "",
2891 [(set DPR:$dst, (v2i32 (or DPR:$src1,
2892 (vnotd DPR:$src2))))]>;
2893 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
2894 (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINiQ,
2895 "vorn", "$dst, $src1, $src2", "",
2896 [(set QPR:$dst, (v4i32 (or QPR:$src1,
2897 (vnotq QPR:$src2))))]>;
2899 // VMVN : Vector Bitwise NOT (Immediate)
2901 let isReMaterializable = 1 in {
2902 // FIXME: This instruction's encoding MAY NOT BE correct.
2903 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$dst),
2904 (ins nModImm:$SIMM), IIC_VMOVImm,
2905 "vmvn", "i16", "$dst, $SIMM", "",
2906 [(set DPR:$dst, (v4i16 (NEONvmvnImm timm:$SIMM)))]>;
2907 // FIXME: This instruction's encoding MAY NOT BE correct.
2908 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$dst),
2909 (ins nModImm:$SIMM), IIC_VMOVImm,
2910 "vmvn", "i16", "$dst, $SIMM", "",
2911 [(set QPR:$dst, (v8i16 (NEONvmvnImm timm:$SIMM)))]>;
2912 // FIXME: This instruction's encoding MAY NOT BE correct.
2913 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$dst),
2914 (ins nModImm:$SIMM), IIC_VMOVImm,
2915 "vmvn", "i32", "$dst, $SIMM", "",
2916 [(set DPR:$dst, (v2i32 (NEONvmvnImm timm:$SIMM)))]>;
2917 // FIXME: This instruction's encoding MAY NOT BE correct.
2918 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$dst),
2919 (ins nModImm:$SIMM), IIC_VMOVImm,
2920 "vmvn", "i32", "$dst, $SIMM", "",
2921 [(set QPR:$dst, (v4i32 (NEONvmvnImm timm:$SIMM)))]>;
2924 // VMVN : Vector Bitwise NOT
2925 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
2926 (outs DPR:$dst), (ins DPR:$src), IIC_VSUBiD,
2927 "vmvn", "$dst, $src", "",
2928 [(set DPR:$dst, (v2i32 (vnotd DPR:$src)))]>;
2929 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
2930 (outs QPR:$dst), (ins QPR:$src), IIC_VSUBiD,
2931 "vmvn", "$dst, $src", "",
2932 [(set QPR:$dst, (v4i32 (vnotq QPR:$src)))]>;
2933 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
2934 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
2936 // VBSL : Vector Bitwise Select
2937 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
2938 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
2939 N3RegFrm, IIC_VCNTiD,
2940 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
2942 (v2i32 (or (and DPR:$Vn, DPR:$src1),
2943 (and DPR:$Vm, (vnotd DPR:$src1)))))]>;
2944 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
2945 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
2946 N3RegFrm, IIC_VCNTiQ,
2947 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
2949 (v4i32 (or (and QPR:$Vn, QPR:$src1),
2950 (and QPR:$Vm, (vnotq QPR:$src1)))))]>;
2952 // VBIF : Vector Bitwise Insert if False
2953 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
2954 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
2955 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
2956 N3RegFrm, IIC_VBINiD,
2957 "vbif", "$dst, $src2, $src3", "$src1 = $dst",
2958 [/* For disassembly only; pattern left blank */]>;
2959 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
2960 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
2961 N3RegFrm, IIC_VBINiQ,
2962 "vbif", "$dst, $src2, $src3", "$src1 = $dst",
2963 [/* For disassembly only; pattern left blank */]>;
2965 // VBIT : Vector Bitwise Insert if True
2966 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
2967 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
2968 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
2969 N3RegFrm, IIC_VBINiD,
2970 "vbit", "$dst, $src2, $src3", "$src1 = $dst",
2971 [/* For disassembly only; pattern left blank */]>;
2972 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
2973 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
2974 N3RegFrm, IIC_VBINiQ,
2975 "vbit", "$dst, $src2, $src3", "$src1 = $dst",
2976 [/* For disassembly only; pattern left blank */]>;
2978 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
2979 // for equivalent operations with different register constraints; it just
2982 // Vector Absolute Differences.
2984 // VABD : Vector Absolute Difference
2985 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
2986 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2987 "vabd", "s", int_arm_neon_vabds, 1>;
2988 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
2989 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2990 "vabd", "u", int_arm_neon_vabdu, 1>;
2991 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
2992 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
2993 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
2994 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
2996 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
2997 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
2998 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
2999 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
3000 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
3002 // VABA : Vector Absolute Difference and Accumulate
3003 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3004 "vaba", "s", int_arm_neon_vabds, add>;
3005 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3006 "vaba", "u", int_arm_neon_vabdu, add>;
3008 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
3009 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
3010 "vabal", "s", int_arm_neon_vabds, zext, add>;
3011 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
3012 "vabal", "u", int_arm_neon_vabdu, zext, add>;
3014 // Vector Maximum and Minimum.
3016 // VMAX : Vector Maximum
3017 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
3018 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3019 "vmax", "s", int_arm_neon_vmaxs, 1>;
3020 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
3021 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3022 "vmax", "u", int_arm_neon_vmaxu, 1>;
3023 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
3025 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
3026 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
3028 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
3030 // VMIN : Vector Minimum
3031 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
3032 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3033 "vmin", "s", int_arm_neon_vmins, 1>;
3034 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
3035 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3036 "vmin", "u", int_arm_neon_vminu, 1>;
3037 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
3039 v2f32, v2f32, int_arm_neon_vmins, 1>;
3040 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
3042 v4f32, v4f32, int_arm_neon_vmins, 1>;
3044 // Vector Pairwise Operations.
3046 // VPADD : Vector Pairwise Add
3047 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3049 v8i8, v8i8, int_arm_neon_vpadd, 0>;
3050 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3052 v4i16, v4i16, int_arm_neon_vpadd, 0>;
3053 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3055 v2i32, v2i32, int_arm_neon_vpadd, 0>;
3056 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
3057 IIC_VPBIND, "vpadd", "f32",
3058 v2f32, v2f32, int_arm_neon_vpadd, 0>;
3060 // VPADDL : Vector Pairwise Add Long
3061 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
3062 int_arm_neon_vpaddls>;
3063 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
3064 int_arm_neon_vpaddlu>;
3066 // VPADAL : Vector Pairwise Add and Accumulate Long
3067 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
3068 int_arm_neon_vpadals>;
3069 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
3070 int_arm_neon_vpadalu>;
3072 // VPMAX : Vector Pairwise Maximum
3073 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3074 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
3075 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3076 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
3077 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3078 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
3079 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3080 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
3081 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3082 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
3083 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3084 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
3085 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
3086 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
3088 // VPMIN : Vector Pairwise Minimum
3089 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3090 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
3091 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3092 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
3093 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3094 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
3095 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3096 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
3097 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3098 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
3099 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3100 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
3101 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
3102 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
3104 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
3106 // VRECPE : Vector Reciprocal Estimate
3107 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
3108 IIC_VUNAD, "vrecpe", "u32",
3109 v2i32, v2i32, int_arm_neon_vrecpe>;
3110 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
3111 IIC_VUNAQ, "vrecpe", "u32",
3112 v4i32, v4i32, int_arm_neon_vrecpe>;
3113 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
3114 IIC_VUNAD, "vrecpe", "f32",
3115 v2f32, v2f32, int_arm_neon_vrecpe>;
3116 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
3117 IIC_VUNAQ, "vrecpe", "f32",
3118 v4f32, v4f32, int_arm_neon_vrecpe>;
3120 // VRECPS : Vector Reciprocal Step
3121 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
3122 IIC_VRECSD, "vrecps", "f32",
3123 v2f32, v2f32, int_arm_neon_vrecps, 1>;
3124 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
3125 IIC_VRECSQ, "vrecps", "f32",
3126 v4f32, v4f32, int_arm_neon_vrecps, 1>;
3128 // VRSQRTE : Vector Reciprocal Square Root Estimate
3129 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
3130 IIC_VUNAD, "vrsqrte", "u32",
3131 v2i32, v2i32, int_arm_neon_vrsqrte>;
3132 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
3133 IIC_VUNAQ, "vrsqrte", "u32",
3134 v4i32, v4i32, int_arm_neon_vrsqrte>;
3135 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
3136 IIC_VUNAD, "vrsqrte", "f32",
3137 v2f32, v2f32, int_arm_neon_vrsqrte>;
3138 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
3139 IIC_VUNAQ, "vrsqrte", "f32",
3140 v4f32, v4f32, int_arm_neon_vrsqrte>;
3142 // VRSQRTS : Vector Reciprocal Square Root Step
3143 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
3144 IIC_VRECSD, "vrsqrts", "f32",
3145 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
3146 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
3147 IIC_VRECSQ, "vrsqrts", "f32",
3148 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
3152 // VSHL : Vector Shift
3153 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, N3RegVShFrm,
3154 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
3155 "vshl", "s", int_arm_neon_vshifts, 0>;
3156 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, N3RegVShFrm,
3157 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
3158 "vshl", "u", int_arm_neon_vshiftu, 0>;
3159 // VSHL : Vector Shift Left (Immediate)
3160 defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl,
3162 // VSHR : Vector Shift Right (Immediate)
3163 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", NEONvshrs,
3165 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", NEONvshru,
3168 // VSHLL : Vector Shift Left Long
3169 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
3170 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
3172 // VSHLL : Vector Shift Left Long (with maximum shift count)
3173 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
3174 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
3175 ValueType OpTy, SDNode OpNode>
3176 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
3177 ResTy, OpTy, OpNode> {
3178 let Inst{21-16} = op21_16;
3180 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
3181 v8i16, v8i8, NEONvshlli>;
3182 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
3183 v4i32, v4i16, NEONvshlli>;
3184 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
3185 v2i64, v2i32, NEONvshlli>;
3187 // VSHRN : Vector Shift Right and Narrow
3188 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
3191 // VRSHL : Vector Rounding Shift
3192 defm VRSHLs : N3VInt_QHSD<0, 0, 0b0101, 0, N3RegVShFrm,
3193 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3194 "vrshl", "s", int_arm_neon_vrshifts, 0>;
3195 defm VRSHLu : N3VInt_QHSD<1, 0, 0b0101, 0, N3RegVShFrm,
3196 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3197 "vrshl", "u", int_arm_neon_vrshiftu, 0>;
3198 // VRSHR : Vector Rounding Shift Right
3199 defm VRSHRs : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs,
3201 defm VRSHRu : N2VSh_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", NEONvrshru,
3204 // VRSHRN : Vector Rounding Shift Right and Narrow
3205 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
3208 // VQSHL : Vector Saturating Shift
3209 defm VQSHLs : N3VInt_QHSD<0, 0, 0b0100, 1, N3RegVShFrm,
3210 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3211 "vqshl", "s", int_arm_neon_vqshifts, 0>;
3212 defm VQSHLu : N3VInt_QHSD<1, 0, 0b0100, 1, N3RegVShFrm,
3213 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3214 "vqshl", "u", int_arm_neon_vqshiftu, 0>;
3215 // VQSHL : Vector Saturating Shift Left (Immediate)
3216 defm VQSHLsi : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls,
3218 defm VQSHLui : N2VSh_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu,
3220 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
3221 defm VQSHLsu : N2VSh_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu,
3224 // VQSHRN : Vector Saturating Shift Right and Narrow
3225 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
3227 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
3230 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
3231 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
3234 // VQRSHL : Vector Saturating Rounding Shift
3235 defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, N3RegVShFrm,
3236 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3237 "vqrshl", "s", int_arm_neon_vqrshifts, 0>;
3238 defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, N3RegVShFrm,
3239 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3240 "vqrshl", "u", int_arm_neon_vqrshiftu, 0>;
3242 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
3243 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
3245 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
3248 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
3249 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
3252 // VSRA : Vector Shift Right and Accumulate
3253 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
3254 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
3255 // VRSRA : Vector Rounding Shift Right and Accumulate
3256 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
3257 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
3259 // VSLI : Vector Shift Left and Insert
3260 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli", NEONvsli, N2RegVShLFrm>;
3261 // VSRI : Vector Shift Right and Insert
3262 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri", NEONvsri, N2RegVShRFrm>;
3264 // Vector Absolute and Saturating Absolute.
3266 // VABS : Vector Absolute Value
3267 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
3268 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
3270 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
3271 IIC_VUNAD, "vabs", "f32",
3272 v2f32, v2f32, int_arm_neon_vabs>;
3273 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
3274 IIC_VUNAQ, "vabs", "f32",
3275 v4f32, v4f32, int_arm_neon_vabs>;
3277 // VQABS : Vector Saturating Absolute Value
3278 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
3279 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
3280 int_arm_neon_vqabs>;
3284 def vnegd : PatFrag<(ops node:$in),
3285 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
3286 def vnegq : PatFrag<(ops node:$in),
3287 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
3289 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
3290 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
3291 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
3292 [(set DPR:$dst, (Ty (vnegd DPR:$src)))]>;
3293 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
3294 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
3295 IIC_VSHLiQ, OpcodeStr, Dt, "$dst, $src", "",
3296 [(set QPR:$dst, (Ty (vnegq QPR:$src)))]>;
3298 // VNEG : Vector Negate (integer)
3299 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
3300 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
3301 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
3302 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
3303 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
3304 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
3306 // VNEG : Vector Negate (floating-point)
3307 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
3308 (outs DPR:$dst), (ins DPR:$src), IIC_VUNAD,
3309 "vneg", "f32", "$dst, $src", "",
3310 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
3311 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
3312 (outs QPR:$dst), (ins QPR:$src), IIC_VUNAQ,
3313 "vneg", "f32", "$dst, $src", "",
3314 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
3316 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
3317 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
3318 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
3319 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
3320 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
3321 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
3323 // VQNEG : Vector Saturating Negate
3324 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
3325 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
3326 int_arm_neon_vqneg>;
3328 // Vector Bit Counting Operations.
3330 // VCLS : Vector Count Leading Sign Bits
3331 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
3332 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
3334 // VCLZ : Vector Count Leading Zeros
3335 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
3336 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
3338 // VCNT : Vector Count One Bits
3339 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
3340 IIC_VCNTiD, "vcnt", "8",
3341 v8i8, v8i8, int_arm_neon_vcnt>;
3342 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
3343 IIC_VCNTiQ, "vcnt", "8",
3344 v16i8, v16i8, int_arm_neon_vcnt>;
3346 // Vector Swap -- for disassembly only.
3347 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
3348 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
3349 "vswp", "$dst, $src", "", []>;
3350 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
3351 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
3352 "vswp", "$dst, $src", "", []>;
3354 // Vector Move Operations.
3356 // VMOV : Vector Move (Register)
3358 let neverHasSideEffects = 1 in {
3359 def VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
3360 N3RegFrm, IIC_VMOV, "vmov", "$dst, $src", "", []>;
3361 def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
3362 N3RegFrm, IIC_VMOV, "vmov", "$dst, $src", "", []>;
3364 // Pseudo vector move instructions for QQ and QQQQ registers. This should
3365 // be expanded after register allocation is completed.
3366 def VMOVQQ : PseudoInst<(outs QQPR:$dst), (ins QQPR:$src),
3367 NoItinerary, "", []>;
3369 def VMOVQQQQ : PseudoInst<(outs QQQQPR:$dst), (ins QQQQPR:$src),
3370 NoItinerary, "", []>;
3371 } // neverHasSideEffects
3373 // VMOV : Vector Move (Immediate)
3375 let isReMaterializable = 1 in {
3376 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
3377 (ins nModImm:$SIMM), IIC_VMOVImm,
3378 "vmov", "i8", "$dst, $SIMM", "",
3379 [(set DPR:$dst, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
3380 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
3381 (ins nModImm:$SIMM), IIC_VMOVImm,
3382 "vmov", "i8", "$dst, $SIMM", "",
3383 [(set QPR:$dst, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
3385 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$dst),
3386 (ins nModImm:$SIMM), IIC_VMOVImm,
3387 "vmov", "i16", "$dst, $SIMM", "",
3388 [(set DPR:$dst, (v4i16 (NEONvmovImm timm:$SIMM)))]>;
3389 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$dst),
3390 (ins nModImm:$SIMM), IIC_VMOVImm,
3391 "vmov", "i16", "$dst, $SIMM", "",
3392 [(set QPR:$dst, (v8i16 (NEONvmovImm timm:$SIMM)))]>;
3394 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$dst),
3395 (ins nModImm:$SIMM), IIC_VMOVImm,
3396 "vmov", "i32", "$dst, $SIMM", "",
3397 [(set DPR:$dst, (v2i32 (NEONvmovImm timm:$SIMM)))]>;
3398 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$dst),
3399 (ins nModImm:$SIMM), IIC_VMOVImm,
3400 "vmov", "i32", "$dst, $SIMM", "",
3401 [(set QPR:$dst, (v4i32 (NEONvmovImm timm:$SIMM)))]>;
3403 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
3404 (ins nModImm:$SIMM), IIC_VMOVImm,
3405 "vmov", "i64", "$dst, $SIMM", "",
3406 [(set DPR:$dst, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
3407 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
3408 (ins nModImm:$SIMM), IIC_VMOVImm,
3409 "vmov", "i64", "$dst, $SIMM", "",
3410 [(set QPR:$dst, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
3411 } // isReMaterializable
3413 // VMOV : Vector Get Lane (move scalar to ARM core register)
3415 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
3416 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3417 IIC_VMOVSI, "vmov", "s8", "$dst, $src[$lane]",
3418 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
3420 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
3421 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3422 IIC_VMOVSI, "vmov", "s16", "$dst, $src[$lane]",
3423 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
3425 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
3426 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3427 IIC_VMOVSI, "vmov", "u8", "$dst, $src[$lane]",
3428 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
3430 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
3431 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3432 IIC_VMOVSI, "vmov", "u16", "$dst, $src[$lane]",
3433 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
3435 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
3436 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3437 IIC_VMOVSI, "vmov", "32", "$dst, $src[$lane]",
3438 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
3440 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
3441 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
3442 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
3443 (DSubReg_i8_reg imm:$lane))),
3444 (SubReg_i8_lane imm:$lane))>;
3445 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
3446 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
3447 (DSubReg_i16_reg imm:$lane))),
3448 (SubReg_i16_lane imm:$lane))>;
3449 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
3450 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
3451 (DSubReg_i8_reg imm:$lane))),
3452 (SubReg_i8_lane imm:$lane))>;
3453 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
3454 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
3455 (DSubReg_i16_reg imm:$lane))),
3456 (SubReg_i16_lane imm:$lane))>;
3457 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
3458 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
3459 (DSubReg_i32_reg imm:$lane))),
3460 (SubReg_i32_lane imm:$lane))>;
3461 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
3462 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
3463 (SSubReg_f32_reg imm:$src2))>;
3464 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
3465 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
3466 (SSubReg_f32_reg imm:$src2))>;
3467 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
3468 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
3469 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
3470 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
3473 // VMOV : Vector Set Lane (move ARM core register to scalar)
3475 let Constraints = "$src1 = $dst" in {
3476 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$dst),
3477 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
3478 IIC_VMOVISL, "vmov", "8", "$dst[$lane], $src2",
3479 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
3480 GPR:$src2, imm:$lane))]>;
3481 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$dst),
3482 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
3483 IIC_VMOVISL, "vmov", "16", "$dst[$lane], $src2",
3484 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
3485 GPR:$src2, imm:$lane))]>;
3486 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$dst),
3487 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
3488 IIC_VMOVISL, "vmov", "32", "$dst[$lane], $src2",
3489 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
3490 GPR:$src2, imm:$lane))]>;
3492 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
3493 (v16i8 (INSERT_SUBREG QPR:$src1,
3494 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
3495 (DSubReg_i8_reg imm:$lane))),
3496 GPR:$src2, (SubReg_i8_lane imm:$lane))),
3497 (DSubReg_i8_reg imm:$lane)))>;
3498 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
3499 (v8i16 (INSERT_SUBREG QPR:$src1,
3500 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
3501 (DSubReg_i16_reg imm:$lane))),
3502 GPR:$src2, (SubReg_i16_lane imm:$lane))),
3503 (DSubReg_i16_reg imm:$lane)))>;
3504 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
3505 (v4i32 (INSERT_SUBREG QPR:$src1,
3506 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
3507 (DSubReg_i32_reg imm:$lane))),
3508 GPR:$src2, (SubReg_i32_lane imm:$lane))),
3509 (DSubReg_i32_reg imm:$lane)))>;
3511 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
3512 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
3513 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
3514 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
3515 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
3516 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
3518 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
3519 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
3520 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
3521 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
3523 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
3524 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
3525 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
3526 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
3527 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
3528 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
3530 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
3531 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
3532 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
3533 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
3534 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
3535 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
3537 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
3538 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3539 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
3541 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
3542 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
3543 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
3545 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
3546 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3547 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
3550 // VDUP : Vector Duplicate (from ARM core register to all elements)
3552 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
3553 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
3554 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
3555 [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
3556 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
3557 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
3558 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
3559 [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
3561 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
3562 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
3563 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
3564 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
3565 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
3566 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
3568 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
3569 IIC_VMOVIS, "vdup", "32", "$dst, $src",
3570 [(set DPR:$dst, (v2f32 (NEONvdup
3571 (f32 (bitconvert GPR:$src)))))]>;
3572 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
3573 IIC_VMOVIS, "vdup", "32", "$dst, $src",
3574 [(set QPR:$dst, (v4f32 (NEONvdup
3575 (f32 (bitconvert GPR:$src)))))]>;
3577 // VDUP : Vector Duplicate Lane (from scalar to all elements)
3579 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
3581 : NVDupLane<op19_16, 0, (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3582 IIC_VMOVD, OpcodeStr, Dt, "$dst, $src[$lane]",
3583 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
3585 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
3586 ValueType ResTy, ValueType OpTy>
3587 : NVDupLane<op19_16, 1, (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3588 IIC_VMOVQ, OpcodeStr, Dt, "$dst, $src[$lane]",
3589 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src),
3592 // Inst{19-16} is partially specified depending on the element size.
3594 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8>;
3595 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16>;
3596 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32>;
3597 def VDUPLNfd : VDUPLND<{?,1,0,0}, "vdup", "32", v2f32>;
3598 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8>;
3599 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16>;
3600 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32>;
3601 def VDUPLNfq : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4f32, v2f32>;
3603 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
3604 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
3605 (DSubReg_i8_reg imm:$lane))),
3606 (SubReg_i8_lane imm:$lane)))>;
3607 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
3608 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
3609 (DSubReg_i16_reg imm:$lane))),
3610 (SubReg_i16_lane imm:$lane)))>;
3611 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
3612 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
3613 (DSubReg_i32_reg imm:$lane))),
3614 (SubReg_i32_lane imm:$lane)))>;
3615 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
3616 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
3617 (DSubReg_i32_reg imm:$lane))),
3618 (SubReg_i32_lane imm:$lane)))>;
3620 def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
3621 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
3622 def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
3623 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
3625 // VMOVN : Vector Narrowing Move
3626 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
3627 "vmovn", "i", trunc>;
3628 // VQMOVN : Vector Saturating Narrowing Move
3629 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
3630 "vqmovn", "s", int_arm_neon_vqmovns>;
3631 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
3632 "vqmovn", "u", int_arm_neon_vqmovnu>;
3633 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
3634 "vqmovun", "s", int_arm_neon_vqmovnsu>;
3635 // VMOVL : Vector Lengthening Move
3636 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
3637 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
3639 // Vector Conversions.
3641 // VCVT : Vector Convert Between Floating-Point and Integers
3642 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3643 v2i32, v2f32, fp_to_sint>;
3644 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3645 v2i32, v2f32, fp_to_uint>;
3646 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3647 v2f32, v2i32, sint_to_fp>;
3648 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3649 v2f32, v2i32, uint_to_fp>;
3651 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3652 v4i32, v4f32, fp_to_sint>;
3653 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3654 v4i32, v4f32, fp_to_uint>;
3655 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3656 v4f32, v4i32, sint_to_fp>;
3657 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3658 v4f32, v4i32, uint_to_fp>;
3660 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
3661 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
3662 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
3663 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
3664 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
3665 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
3666 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
3667 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
3668 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
3670 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
3671 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
3672 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
3673 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
3674 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
3675 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
3676 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
3677 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
3681 // VREV64 : Vector Reverse elements within 64-bit doublewords
3683 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3684 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
3685 (ins DPR:$src), IIC_VMOVD,
3686 OpcodeStr, Dt, "$dst, $src", "",
3687 [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
3688 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3689 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
3690 (ins QPR:$src), IIC_VMOVQ,
3691 OpcodeStr, Dt, "$dst, $src", "",
3692 [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
3694 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
3695 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
3696 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
3697 def VREV64df : VREV64D<0b10, "vrev64", "32", v2f32>;
3699 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
3700 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
3701 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
3702 def VREV64qf : VREV64Q<0b10, "vrev64", "32", v4f32>;
3704 // VREV32 : Vector Reverse elements within 32-bit words
3706 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3707 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
3708 (ins DPR:$src), IIC_VMOVD,
3709 OpcodeStr, Dt, "$dst, $src", "",
3710 [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
3711 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3712 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
3713 (ins QPR:$src), IIC_VMOVQ,
3714 OpcodeStr, Dt, "$dst, $src", "",
3715 [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
3717 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
3718 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
3720 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
3721 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
3723 // VREV16 : Vector Reverse elements within 16-bit halfwords
3725 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3726 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
3727 (ins DPR:$src), IIC_VMOVD,
3728 OpcodeStr, Dt, "$dst, $src", "",
3729 [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
3730 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3731 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
3732 (ins QPR:$src), IIC_VMOVQ,
3733 OpcodeStr, Dt, "$dst, $src", "",
3734 [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
3736 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
3737 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
3739 // Other Vector Shuffles.
3741 // VEXT : Vector Extract
3743 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
3744 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$dst),
3745 (ins DPR:$lhs, DPR:$rhs, i32imm:$index), NVExtFrm,
3746 IIC_VEXTD, OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
3747 [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
3748 (Ty DPR:$rhs), imm:$index)))]>;
3750 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
3751 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$dst),
3752 (ins QPR:$lhs, QPR:$rhs, i32imm:$index), NVExtFrm,
3753 IIC_VEXTQ, OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
3754 [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
3755 (Ty QPR:$rhs), imm:$index)))]>;
3757 def VEXTd8 : VEXTd<"vext", "8", v8i8>;
3758 def VEXTd16 : VEXTd<"vext", "16", v4i16>;
3759 def VEXTd32 : VEXTd<"vext", "32", v2i32>;
3760 def VEXTdf : VEXTd<"vext", "32", v2f32>;
3762 def VEXTq8 : VEXTq<"vext", "8", v16i8>;
3763 def VEXTq16 : VEXTq<"vext", "16", v8i16>;
3764 def VEXTq32 : VEXTq<"vext", "32", v4i32>;
3765 def VEXTqf : VEXTq<"vext", "32", v4f32>;
3767 // VTRN : Vector Transpose
3769 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
3770 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
3771 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
3773 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
3774 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
3775 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
3777 // VUZP : Vector Unzip (Deinterleave)
3779 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
3780 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
3781 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
3783 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
3784 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
3785 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
3787 // VZIP : Vector Zip (Interleave)
3789 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
3790 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
3791 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
3793 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
3794 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
3795 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
3797 // Vector Table Lookup and Table Extension.
3799 // VTBL : Vector Table Lookup
3801 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
3802 (ins DPR:$tbl1, DPR:$src), NVTBLFrm, IIC_VTB1,
3803 "vtbl", "8", "$dst, \\{$tbl1\\}, $src", "",
3804 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
3805 let hasExtraSrcRegAllocReq = 1 in {
3807 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
3808 (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), NVTBLFrm, IIC_VTB2,
3809 "vtbl", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "", []>;
3811 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
3812 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), NVTBLFrm, IIC_VTB3,
3813 "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src", "", []>;
3815 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
3816 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src),
3818 "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src", "", []>;
3819 } // hasExtraSrcRegAllocReq = 1
3822 : PseudoNeonI<(outs DPR:$dst), (ins QPR:$tbl, DPR:$src), IIC_VTB2, "", []>;
3824 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
3826 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
3828 // VTBX : Vector Table Extension
3830 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
3831 (ins DPR:$orig, DPR:$tbl1, DPR:$src), NVTBLFrm, IIC_VTBX1,
3832 "vtbx", "8", "$dst, \\{$tbl1\\}, $src", "$orig = $dst",
3833 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
3834 DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
3835 let hasExtraSrcRegAllocReq = 1 in {
3837 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
3838 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), NVTBLFrm, IIC_VTBX2,
3839 "vtbx", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "$orig = $dst", []>;
3841 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
3842 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src),
3843 NVTBLFrm, IIC_VTBX3,
3844 "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src",
3845 "$orig = $dst", []>;
3847 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
3848 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), NVTBLFrm, IIC_VTBX4,
3849 "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src",
3850 "$orig = $dst", []>;
3851 } // hasExtraSrcRegAllocReq = 1
3854 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QPR:$tbl, DPR:$src),
3855 IIC_VTBX2, "$orig = $dst", []>;
3857 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
3858 IIC_VTBX3, "$orig = $dst", []>;
3860 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
3861 IIC_VTBX4, "$orig = $dst", []>;
3863 //===----------------------------------------------------------------------===//
3864 // NEON instructions for single-precision FP math
3865 //===----------------------------------------------------------------------===//
3867 class N2VSPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
3868 : NEONFPPat<(ResTy (OpNode SPR:$a)),
3869 (EXTRACT_SUBREG (OpTy (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)),
3873 class N3VSPat<SDNode OpNode, NeonI Inst>
3874 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
3875 (EXTRACT_SUBREG (v2f32
3876 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3878 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3882 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
3883 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
3884 (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3886 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3888 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3892 // These need separate instructions because they must use DPR_VFP2 register
3893 // class which have SPR sub-registers.
3895 // Vector Add Operations used for single-precision FP
3896 let neverHasSideEffects = 1 in
3897 def VADDfd_sfp : N3VS<0,0,0b00,0b1101,0, "vadd", "f32", v2f32, v2f32, fadd, 1>;
3898 def : N3VSPat<fadd, VADDfd_sfp>;
3900 // Vector Sub Operations used for single-precision FP
3901 let neverHasSideEffects = 1 in
3902 def VSUBfd_sfp : N3VS<0,0,0b10,0b1101,0, "vsub", "f32", v2f32, v2f32, fsub, 0>;
3903 def : N3VSPat<fsub, VSUBfd_sfp>;
3905 // Vector Multiply Operations used for single-precision FP
3906 let neverHasSideEffects = 1 in
3907 def VMULfd_sfp : N3VS<1,0,0b00,0b1101,1, "vmul", "f32", v2f32, v2f32, fmul, 1>;
3908 def : N3VSPat<fmul, VMULfd_sfp>;
3910 // Vector Multiply-Accumulate/Subtract used for single-precision FP
3911 // vml[as].f32 can cause 4-8 cycle stalls in following ASIMD instructions, so
3912 // we want to avoid them for now. e.g., alternating vmla/vadd instructions.
3914 //let neverHasSideEffects = 1 in
3915 //def VMLAfd_sfp : N3VSMulOp<0,0,0b00,0b1101,1, IIC_VMACD, "vmla", "f32",
3916 // v2f32, fmul, fadd>;
3917 //def : N3VSMulOpPat<fmul, fadd, VMLAfd_sfp>;
3919 //let neverHasSideEffects = 1 in
3920 //def VMLSfd_sfp : N3VSMulOp<0,0,0b10,0b1101,1, IIC_VMACD, "vmls", "f32",
3921 // v2f32, fmul, fsub>;
3922 //def : N3VSMulOpPat<fmul, fsub, VMLSfd_sfp>;
3924 // Vector Absolute used for single-precision FP
3925 let neverHasSideEffects = 1 in
3926 def VABSfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01110, 0, 0,
3927 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
3928 "vabs", "f32", "$dst, $src", "", []>;
3929 def : N2VSPat<fabs, f32, v2f32, VABSfd_sfp>;
3931 // Vector Negate used for single-precision FP
3932 let neverHasSideEffects = 1 in
3933 def VNEGfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
3934 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
3935 "vneg", "f32", "$dst, $src", "", []>;
3936 def : N2VSPat<fneg, f32, v2f32, VNEGfd_sfp>;
3938 // Vector Maximum used for single-precision FP
3939 let neverHasSideEffects = 1 in
3940 def VMAXfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
3941 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm, IIC_VBIND,
3942 "vmax", "f32", "$dst, $src1, $src2", "", []>;
3943 def : N3VSPat<NEONfmax, VMAXfd_sfp>;
3945 // Vector Minimum used for single-precision FP
3946 let neverHasSideEffects = 1 in
3947 def VMINfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
3948 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm, IIC_VBIND,
3949 "vmin", "f32", "$dst, $src1, $src2", "", []>;
3950 def : N3VSPat<NEONfmin, VMINfd_sfp>;
3952 // Vector Convert between single-precision FP and integer
3953 let neverHasSideEffects = 1 in
3954 def VCVTf2sd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3955 v2i32, v2f32, fp_to_sint>;
3956 def : N2VSPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
3958 let neverHasSideEffects = 1 in
3959 def VCVTf2ud_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3960 v2i32, v2f32, fp_to_uint>;
3961 def : N2VSPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
3963 let neverHasSideEffects = 1 in
3964 def VCVTs2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3965 v2f32, v2i32, sint_to_fp>;
3966 def : N2VSPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
3968 let neverHasSideEffects = 1 in
3969 def VCVTu2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3970 v2f32, v2i32, uint_to_fp>;
3971 def : N2VSPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
3973 //===----------------------------------------------------------------------===//
3974 // Non-Instruction Patterns
3975 //===----------------------------------------------------------------------===//
3978 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
3979 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
3980 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
3981 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
3982 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
3983 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
3984 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
3985 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
3986 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
3987 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
3988 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
3989 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
3990 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
3991 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
3992 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
3993 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
3994 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
3995 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
3996 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
3997 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
3998 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
3999 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
4000 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
4001 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
4002 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
4003 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
4004 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
4005 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
4006 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
4007 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
4009 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
4010 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
4011 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
4012 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
4013 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
4014 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
4015 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
4016 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
4017 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
4018 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
4019 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
4020 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
4021 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
4022 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
4023 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
4024 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
4025 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
4026 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
4027 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
4028 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
4029 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
4030 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
4031 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
4032 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
4033 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
4034 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
4035 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
4036 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
4037 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
4038 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;