1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
19 def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
21 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
22 def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
23 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
24 def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
25 def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
26 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
27 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
28 def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
29 def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
30 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
31 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
33 // Types for vector shift by immediates. The "SHX" version is for long and
34 // narrow operations where the source and destination vectors have different
35 // types. The "SHINS" version is for shift and insert operations.
36 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
38 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
40 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
43 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
44 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
45 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
46 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
47 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
48 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
49 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
51 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
52 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
53 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
55 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
56 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
57 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
58 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
59 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
60 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
62 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
63 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
64 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
66 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
67 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
69 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
71 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
72 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
74 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
75 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
76 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
78 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
80 def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
81 def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
83 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
85 // VDUPLANE can produce a quad-register result from a double-register source,
86 // so the result is not constrained to match the source.
87 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
88 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
91 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
92 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
93 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
95 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
96 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
97 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
98 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
100 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
102 SDTCisSameAs<0, 3>]>;
103 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
104 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
105 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
107 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
108 SDTCisSameAs<1, 2>]>;
109 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
110 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
112 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
113 SDTCisSameAs<0, 2>]>;
114 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
115 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
117 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
118 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
119 unsigned EltBits = 0;
120 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
121 return (EltBits == 32 && EltVal == 0);
124 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
125 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
126 unsigned EltBits = 0;
127 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
128 return (EltBits == 8 && EltVal == 0xff);
131 //===----------------------------------------------------------------------===//
132 // NEON operand definitions
133 //===----------------------------------------------------------------------===//
135 def nModImm : Operand<i32> {
136 let PrintMethod = "printNEONModImmOperand";
139 //===----------------------------------------------------------------------===//
140 // NEON load / store instructions
141 //===----------------------------------------------------------------------===//
143 // Use VLDM to load a Q register as a D register pair.
144 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
146 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
148 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
150 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
152 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
154 // Use VSTM to store a Q register as a D register pair.
155 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
157 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
159 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
161 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
163 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
165 // Classes for VLD* pseudo-instructions with multi-register operands.
166 // These are expanded to real instructions after register allocation.
167 class VLDQPseudo<InstrItinClass itin>
168 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
169 class VLDQWBPseudo<InstrItinClass itin>
170 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
171 (ins addrmode6:$addr, am6offset:$offset), itin,
173 class VLDQQPseudo<InstrItinClass itin>
174 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
175 class VLDQQWBPseudo<InstrItinClass itin>
176 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
177 (ins addrmode6:$addr, am6offset:$offset), itin,
179 class VLDQQQQWBPseudo<InstrItinClass itin>
180 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
181 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
182 "$addr.addr = $wb, $src = $dst">;
184 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
186 // VLD1 : Vector Load (multiple single elements)
187 class VLD1D<bits<4> op7_4, string Dt>
188 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd),
189 (ins addrmode6:$Rn), IIC_VLD1,
190 "vld1", Dt, "\\{$Vd\\}, $Rn", "", []> {
194 class VLD1Q<bits<4> op7_4, string Dt>
195 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2),
196 (ins addrmode6:$Rn), IIC_VLD1x2,
197 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
199 let Inst{5-4} = Rn{5-4};
202 def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
203 def VLD1d16 : VLD1D<{0,1,0,?}, "16">;
204 def VLD1d32 : VLD1D<{1,0,0,?}, "32">;
205 def VLD1d64 : VLD1D<{1,1,0,?}, "64">;
207 def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;
208 def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
209 def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
210 def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
212 def VLD1q8Pseudo : VLDQPseudo<IIC_VLD1x2>;
213 def VLD1q16Pseudo : VLDQPseudo<IIC_VLD1x2>;
214 def VLD1q32Pseudo : VLDQPseudo<IIC_VLD1x2>;
215 def VLD1q64Pseudo : VLDQPseudo<IIC_VLD1x2>;
217 // ...with address register writeback:
218 class VLD1DWB<bits<4> op7_4, string Dt>
219 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd, GPR:$wb),
220 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1u,
221 "vld1", Dt, "\\{$Vd\\}, $Rn$Rm",
222 "$Rn.addr = $wb", []> {
225 class VLD1QWB<bits<4> op7_4, string Dt>
226 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
227 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x2u,
228 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
229 "$Rn.addr = $wb", []> {
230 let Inst{5-4} = Rn{5-4};
233 def VLD1d8_UPD : VLD1DWB<{0,0,0,?}, "8">;
234 def VLD1d16_UPD : VLD1DWB<{0,1,0,?}, "16">;
235 def VLD1d32_UPD : VLD1DWB<{1,0,0,?}, "32">;
236 def VLD1d64_UPD : VLD1DWB<{1,1,0,?}, "64">;
238 def VLD1q8_UPD : VLD1QWB<{0,0,?,?}, "8">;
239 def VLD1q16_UPD : VLD1QWB<{0,1,?,?}, "16">;
240 def VLD1q32_UPD : VLD1QWB<{1,0,?,?}, "32">;
241 def VLD1q64_UPD : VLD1QWB<{1,1,?,?}, "64">;
243 def VLD1q8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
244 def VLD1q16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
245 def VLD1q32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
246 def VLD1q64Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
248 // ...with 3 registers (some of these are only for the disassembler):
249 class VLD1D3<bits<4> op7_4, string Dt>
250 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
251 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
252 "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
256 class VLD1D3WB<bits<4> op7_4, string Dt>
257 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
258 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x3u, "vld1", Dt,
259 "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
263 def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
264 def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;
265 def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;
266 def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;
268 def VLD1d8T_UPD : VLD1D3WB<{0,0,0,?}, "8">;
269 def VLD1d16T_UPD : VLD1D3WB<{0,1,0,?}, "16">;
270 def VLD1d32T_UPD : VLD1D3WB<{1,0,0,?}, "32">;
271 def VLD1d64T_UPD : VLD1D3WB<{1,1,0,?}, "64">;
273 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
274 def VLD1d64TPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x3u>;
276 // ...with 4 registers (some of these are only for the disassembler):
277 class VLD1D4<bits<4> op7_4, string Dt>
278 : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
279 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
280 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
282 let Inst{5-4} = Rn{5-4};
284 class VLD1D4WB<bits<4> op7_4, string Dt>
285 : NLdSt<0,0b10,0b0010,op7_4,
286 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
287 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4, "vld1", Dt,
288 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", "$Rn.addr = $wb",
290 let Inst{5-4} = Rn{5-4};
293 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
294 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;
295 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;
296 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;
298 def VLD1d8Q_UPD : VLD1D4WB<{0,0,?,?}, "8">;
299 def VLD1d16Q_UPD : VLD1D4WB<{0,1,?,?}, "16">;
300 def VLD1d32Q_UPD : VLD1D4WB<{1,0,?,?}, "32">;
301 def VLD1d64Q_UPD : VLD1D4WB<{1,1,?,?}, "64">;
303 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
304 def VLD1d64QPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x4u>;
306 // VLD2 : Vector Load (multiple 2-element structures)
307 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
308 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
309 (ins addrmode6:$Rn), IIC_VLD2,
310 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
312 let Inst{5-4} = Rn{5-4};
314 class VLD2Q<bits<4> op7_4, string Dt>
315 : NLdSt<0, 0b10, 0b0011, op7_4,
316 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
317 (ins addrmode6:$Rn), IIC_VLD2x2,
318 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
320 let Inst{5-4} = Rn{5-4};
323 def VLD2d8 : VLD2D<0b1000, {0,0,?,?}, "8">;
324 def VLD2d16 : VLD2D<0b1000, {0,1,?,?}, "16">;
325 def VLD2d32 : VLD2D<0b1000, {1,0,?,?}, "32">;
327 def VLD2q8 : VLD2Q<{0,0,?,?}, "8">;
328 def VLD2q16 : VLD2Q<{0,1,?,?}, "16">;
329 def VLD2q32 : VLD2Q<{1,0,?,?}, "32">;
331 def VLD2d8Pseudo : VLDQPseudo<IIC_VLD2>;
332 def VLD2d16Pseudo : VLDQPseudo<IIC_VLD2>;
333 def VLD2d32Pseudo : VLDQPseudo<IIC_VLD2>;
335 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
336 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
337 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
339 // ...with address register writeback:
340 class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
341 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
342 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2u,
343 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
344 "$Rn.addr = $wb", []> {
345 let Inst{5-4} = Rn{5-4};
347 class VLD2QWB<bits<4> op7_4, string Dt>
348 : NLdSt<0, 0b10, 0b0011, op7_4,
349 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
350 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2x2u,
351 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
352 "$Rn.addr = $wb", []> {
353 let Inst{5-4} = Rn{5-4};
356 def VLD2d8_UPD : VLD2DWB<0b1000, {0,0,?,?}, "8">;
357 def VLD2d16_UPD : VLD2DWB<0b1000, {0,1,?,?}, "16">;
358 def VLD2d32_UPD : VLD2DWB<0b1000, {1,0,?,?}, "32">;
360 def VLD2q8_UPD : VLD2QWB<{0,0,?,?}, "8">;
361 def VLD2q16_UPD : VLD2QWB<{0,1,?,?}, "16">;
362 def VLD2q32_UPD : VLD2QWB<{1,0,?,?}, "32">;
364 def VLD2d8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
365 def VLD2d16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
366 def VLD2d32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
368 def VLD2q8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
369 def VLD2q16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
370 def VLD2q32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
372 // ...with double-spaced registers (for disassembly only):
373 def VLD2b8 : VLD2D<0b1001, {0,0,?,?}, "8">;
374 def VLD2b16 : VLD2D<0b1001, {0,1,?,?}, "16">;
375 def VLD2b32 : VLD2D<0b1001, {1,0,?,?}, "32">;
376 def VLD2b8_UPD : VLD2DWB<0b1001, {0,0,?,?}, "8">;
377 def VLD2b16_UPD : VLD2DWB<0b1001, {0,1,?,?}, "16">;
378 def VLD2b32_UPD : VLD2DWB<0b1001, {1,0,?,?}, "32">;
380 // VLD3 : Vector Load (multiple 3-element structures)
381 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
382 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
383 (ins addrmode6:$Rn), IIC_VLD3,
384 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
389 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
390 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
391 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
393 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
394 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
395 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
397 // ...with address register writeback:
398 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
399 : NLdSt<0, 0b10, op11_8, op7_4,
400 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
401 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
402 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
403 "$Rn.addr = $wb", []> {
407 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
408 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
409 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
411 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
412 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
413 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
415 // ...with double-spaced registers (non-updating versions for disassembly only):
416 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
417 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
418 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
419 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
420 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
421 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
423 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
424 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
425 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
427 // ...alternate versions to be allocated odd register numbers:
428 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
429 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
430 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
432 // VLD4 : Vector Load (multiple 4-element structures)
433 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
434 : NLdSt<0, 0b10, op11_8, op7_4,
435 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
436 (ins addrmode6:$Rn), IIC_VLD4,
437 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
439 let Inst{5-4} = Rn{5-4};
442 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
443 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
444 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
446 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
447 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
448 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
450 // ...with address register writeback:
451 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
452 : NLdSt<0, 0b10, op11_8, op7_4,
453 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
454 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4,
455 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
456 "$Rn.addr = $wb", []> {
457 let Inst{5-4} = Rn{5-4};
460 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
461 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
462 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
464 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
465 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
466 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
468 // ...with double-spaced registers (non-updating versions for disassembly only):
469 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
470 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
471 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
472 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
473 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
474 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
476 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
477 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
478 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
480 // ...alternate versions to be allocated odd register numbers:
481 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
482 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
483 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
485 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
487 // Classes for VLD*LN pseudo-instructions with multi-register operands.
488 // These are expanded to real instructions after register allocation.
489 class VLDQLNPseudo<InstrItinClass itin>
490 : PseudoNLdSt<(outs QPR:$dst),
491 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
492 itin, "$src = $dst">;
493 class VLDQLNWBPseudo<InstrItinClass itin>
494 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
495 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
496 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
497 class VLDQQLNPseudo<InstrItinClass itin>
498 : PseudoNLdSt<(outs QQPR:$dst),
499 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
500 itin, "$src = $dst">;
501 class VLDQQLNWBPseudo<InstrItinClass itin>
502 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
503 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
504 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
505 class VLDQQQQLNPseudo<InstrItinClass itin>
506 : PseudoNLdSt<(outs QQQQPR:$dst),
507 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
508 itin, "$src = $dst">;
509 class VLDQQQQLNWBPseudo<InstrItinClass itin>
510 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
511 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
512 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
514 // VLD1LN : Vector Load (single element to one lane)
515 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
517 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
518 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
519 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
521 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
522 (i32 (LoadOp addrmode6:$Rn)),
526 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
527 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
528 (i32 (LoadOp addrmode6:$addr)),
532 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
533 let Inst{7-5} = lane{2-0};
535 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
536 let Inst{7-6} = lane{1-0};
539 def VLD1LNd32 : VLD1LN<0b1000, {?,0,?,?}, "32", v2i32, load> {
540 let Inst{7} = lane{0};
545 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
546 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
547 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
549 def : Pat<(vector_insert (v2f32 DPR:$src),
550 (f32 (load addrmode6:$addr)), imm:$lane),
551 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
552 def : Pat<(vector_insert (v4f32 QPR:$src),
553 (f32 (load addrmode6:$addr)), imm:$lane),
554 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
556 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
558 // ...with address register writeback:
559 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
560 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
561 (ins addrmode6:$Rn, am6offset:$Rm,
562 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
563 "\\{$Vd[$lane]\\}, $Rn$Rm",
564 "$src = $Vd, $Rn.addr = $wb", []>;
566 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
567 let Inst{7-5} = lane{2-0};
569 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
570 let Inst{7-6} = lane{1-0};
573 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
574 let Inst{7} = lane{0};
579 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
580 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
581 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
583 // VLD2LN : Vector Load (single 2-element structure to one lane)
584 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
585 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
586 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
587 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
588 "$src1 = $Vd, $src2 = $dst2", []> {
593 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
594 let Inst{7-5} = lane{2-0};
596 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
597 let Inst{7-6} = lane{1-0};
599 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
600 let Inst{7} = lane{0};
603 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
604 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
605 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
607 // ...with double-spaced registers:
608 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
609 let Inst{7-6} = lane{1-0};
611 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
612 let Inst{7} = lane{0};
615 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
616 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
618 // ...with address register writeback:
619 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
620 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
621 (ins addrmode6:$Rn, am6offset:$Rm,
622 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
623 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
624 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
628 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
629 let Inst{7-5} = lane{2-0};
631 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
632 let Inst{7-6} = lane{1-0};
634 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
635 let Inst{7} = lane{0};
638 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
639 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
640 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
642 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
643 let Inst{7-6} = lane{1-0};
645 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
646 let Inst{7} = lane{0};
649 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
650 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
652 // VLD3LN : Vector Load (single 3-element structure to one lane)
653 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
654 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
655 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
656 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
657 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
658 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
662 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
663 let Inst{7-5} = lane{2-0};
665 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
666 let Inst{7-6} = lane{1-0};
668 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
669 let Inst{7} = lane{0};
672 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
673 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
674 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
676 // ...with double-spaced registers:
677 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
678 let Inst{7-6} = lane{1-0};
680 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
681 let Inst{7} = lane{0};
684 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
685 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
687 // ...with address register writeback:
688 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
689 : NLdStLn<1, 0b10, op11_8, op7_4,
690 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
691 (ins addrmode6:$Rn, am6offset:$Rm,
692 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
693 IIC_VLD3lnu, "vld3", Dt,
694 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
695 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
698 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
699 let Inst{7-5} = lane{2-0};
701 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
702 let Inst{7-6} = lane{1-0};
704 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
705 let Inst{7} = lane{0};
708 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
709 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
710 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
712 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
713 let Inst{7-6} = lane{1-0};
715 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
716 let Inst{7} = lane{0};
719 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
720 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
722 // VLD4LN : Vector Load (single 4-element structure to one lane)
723 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
724 : NLdStLn<1, 0b10, op11_8, op7_4,
725 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
726 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
727 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
728 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
729 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
734 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
735 let Inst{7-5} = lane{2-0};
737 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
738 let Inst{7-6} = lane{1-0};
740 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
741 let Inst{7} = lane{0};
745 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
746 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
747 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
749 // ...with double-spaced registers:
750 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
751 let Inst{7-6} = lane{1-0};
753 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
754 let Inst{7} = lane{0};
758 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
759 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
761 // ...with address register writeback:
762 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
763 : NLdStLn<1, 0b10, op11_8, op7_4,
764 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
765 (ins addrmode6:$Rn, am6offset:$Rm,
766 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
767 IIC_VLD4ln, "vld4", Dt,
768 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
769 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
774 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
775 let Inst{7-5} = lane{2-0};
777 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
778 let Inst{7-6} = lane{1-0};
780 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
781 let Inst{7} = lane{0};
785 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
786 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
787 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
789 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
790 let Inst{7-6} = lane{1-0};
792 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
793 let Inst{7} = lane{0};
797 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
798 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
800 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
802 // VLD1DUP : Vector Load (single element to all lanes)
803 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
804 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd), (ins addrmode6dup:$Rn),
805 IIC_VLD1dup, "vld1", Dt, "\\{$Vd[]\\}, $Rn", "",
806 [(set DPR:$Vd, (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
810 class VLD1QDUPPseudo<ValueType Ty, PatFrag LoadOp> : VLDQPseudo<IIC_VLD1dup> {
811 let Pattern = [(set QPR:$dst,
812 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$addr)))))];
815 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
816 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;
817 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;
819 def VLD1DUPq8Pseudo : VLD1QDUPPseudo<v16i8, extloadi8>;
820 def VLD1DUPq16Pseudo : VLD1QDUPPseudo<v8i16, extloadi16>;
821 def VLD1DUPq32Pseudo : VLD1QDUPPseudo<v4i32, load>;
823 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
824 (VLD1DUPd32 addrmode6:$addr)>;
825 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
826 (VLD1DUPq32Pseudo addrmode6:$addr)>;
828 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
830 class VLD1QDUP<bits<4> op7_4, string Dt>
831 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2),
832 (ins addrmode6dup:$Rn), IIC_VLD1dup,
833 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
838 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8">;
839 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16">;
840 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32">;
842 // ...with address register writeback:
843 class VLD1DUPWB<bits<4> op7_4, string Dt>
844 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, GPR:$wb),
845 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
846 "vld1", Dt, "\\{$Vd[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
849 class VLD1QDUPWB<bits<4> op7_4, string Dt>
850 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
851 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
852 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
856 def VLD1DUPd8_UPD : VLD1DUPWB<{0,0,0,0}, "8">;
857 def VLD1DUPd16_UPD : VLD1DUPWB<{0,1,0,?}, "16">;
858 def VLD1DUPd32_UPD : VLD1DUPWB<{1,0,0,?}, "32">;
860 def VLD1DUPq8_UPD : VLD1QDUPWB<{0,0,1,0}, "8">;
861 def VLD1DUPq16_UPD : VLD1QDUPWB<{0,1,1,?}, "16">;
862 def VLD1DUPq32_UPD : VLD1QDUPWB<{1,0,1,?}, "32">;
864 def VLD1DUPq8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
865 def VLD1DUPq16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
866 def VLD1DUPq32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
868 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
869 class VLD2DUP<bits<4> op7_4, string Dt>
870 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2),
871 (ins addrmode6dup:$Rn), IIC_VLD2dup,
872 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
877 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8">;
878 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16">;
879 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32">;
881 def VLD2DUPd8Pseudo : VLDQPseudo<IIC_VLD2dup>;
882 def VLD2DUPd16Pseudo : VLDQPseudo<IIC_VLD2dup>;
883 def VLD2DUPd32Pseudo : VLDQPseudo<IIC_VLD2dup>;
885 // ...with double-spaced registers (not used for codegen):
886 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8">;
887 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16">;
888 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32">;
890 // ...with address register writeback:
891 class VLD2DUPWB<bits<4> op7_4, string Dt>
892 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
893 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD2dupu,
894 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
898 def VLD2DUPd8_UPD : VLD2DUPWB<{0,0,0,0}, "8">;
899 def VLD2DUPd16_UPD : VLD2DUPWB<{0,1,0,?}, "16">;
900 def VLD2DUPd32_UPD : VLD2DUPWB<{1,0,0,?}, "32">;
902 def VLD2DUPd8x2_UPD : VLD2DUPWB<{0,0,1,0}, "8">;
903 def VLD2DUPd16x2_UPD : VLD2DUPWB<{0,1,1,?}, "16">;
904 def VLD2DUPd32x2_UPD : VLD2DUPWB<{1,0,1,?}, "32">;
906 def VLD2DUPd8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
907 def VLD2DUPd16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
908 def VLD2DUPd32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
910 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
911 class VLD3DUP<bits<4> op7_4, string Dt>
912 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
913 (ins addrmode6dup:$Rn), IIC_VLD3dup,
914 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
919 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
920 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
921 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
923 def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>;
924 def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
925 def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
927 // ...with double-spaced registers (not used for codegen):
928 def VLD3DUPd8x2 : VLD3DUP<{0,0,1,?}, "8">;
929 def VLD3DUPd16x2 : VLD3DUP<{0,1,1,?}, "16">;
930 def VLD3DUPd32x2 : VLD3DUP<{1,0,1,?}, "32">;
932 // ...with address register writeback:
933 class VLD3DUPWB<bits<4> op7_4, string Dt>
934 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
935 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu,
936 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
937 "$Rn.addr = $wb", []> {
941 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;
942 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">;
943 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">;
945 def VLD3DUPd8x2_UPD : VLD3DUPWB<{0,0,1,0}, "8">;
946 def VLD3DUPd16x2_UPD : VLD3DUPWB<{0,1,1,?}, "16">;
947 def VLD3DUPd32x2_UPD : VLD3DUPWB<{1,0,1,?}, "32">;
949 def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
950 def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
951 def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
953 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
954 class VLD4DUP<bits<4> op7_4, string Dt>
955 : NLdSt<1, 0b10, 0b1111, op7_4,
956 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
957 (ins addrmode6dup:$Rn), IIC_VLD4dup,
958 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
963 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
964 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
965 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
967 def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>;
968 def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>;
969 def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>;
971 // ...with double-spaced registers (not used for codegen):
972 def VLD4DUPd8x2 : VLD4DUP<{0,0,1,?}, "8">;
973 def VLD4DUPd16x2 : VLD4DUP<{0,1,1,?}, "16">;
974 def VLD4DUPd32x2 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
976 // ...with address register writeback:
977 class VLD4DUPWB<bits<4> op7_4, string Dt>
978 : NLdSt<1, 0b10, 0b1111, op7_4,
979 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
980 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
981 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
982 "$Rn.addr = $wb", []> {
986 def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">;
987 def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">;
988 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
990 def VLD4DUPd8x2_UPD : VLD4DUPWB<{0,0,1,0}, "8">;
991 def VLD4DUPd16x2_UPD : VLD4DUPWB<{0,1,1,?}, "16">;
992 def VLD4DUPd32x2_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
994 def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
995 def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
996 def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
998 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1000 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1002 // Classes for VST* pseudo-instructions with multi-register operands.
1003 // These are expanded to real instructions after register allocation.
1004 class VSTQPseudo<InstrItinClass itin>
1005 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1006 class VSTQWBPseudo<InstrItinClass itin>
1007 : PseudoNLdSt<(outs GPR:$wb),
1008 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1009 "$addr.addr = $wb">;
1010 class VSTQQPseudo<InstrItinClass itin>
1011 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
1012 class VSTQQWBPseudo<InstrItinClass itin>
1013 : PseudoNLdSt<(outs GPR:$wb),
1014 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
1015 "$addr.addr = $wb">;
1016 class VSTQQQQWBPseudo<InstrItinClass itin>
1017 : PseudoNLdSt<(outs GPR:$wb),
1018 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
1019 "$addr.addr = $wb">;
1021 // VST1 : Vector Store (multiple single elements)
1022 class VST1D<bits<4> op7_4, string Dt>
1023 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, DPR:$Vd),
1024 IIC_VST1, "vst1", Dt, "\\{$Vd\\}, $Rn", "", []> {
1026 let Inst{4} = Rn{4};
1028 class VST1Q<bits<4> op7_4, string Dt>
1029 : NLdSt<0,0b00,0b1010,op7_4, (outs),
1030 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2), IIC_VST1x2,
1031 "vst1", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1033 let Inst{5-4} = Rn{5-4};
1036 def VST1d8 : VST1D<{0,0,0,?}, "8">;
1037 def VST1d16 : VST1D<{0,1,0,?}, "16">;
1038 def VST1d32 : VST1D<{1,0,0,?}, "32">;
1039 def VST1d64 : VST1D<{1,1,0,?}, "64">;
1041 def VST1q8 : VST1Q<{0,0,?,?}, "8">;
1042 def VST1q16 : VST1Q<{0,1,?,?}, "16">;
1043 def VST1q32 : VST1Q<{1,0,?,?}, "32">;
1044 def VST1q64 : VST1Q<{1,1,?,?}, "64">;
1046 def VST1q8Pseudo : VSTQPseudo<IIC_VST1x2>;
1047 def VST1q16Pseudo : VSTQPseudo<IIC_VST1x2>;
1048 def VST1q32Pseudo : VSTQPseudo<IIC_VST1x2>;
1049 def VST1q64Pseudo : VSTQPseudo<IIC_VST1x2>;
1051 // ...with address register writeback:
1052 class VST1DWB<bits<4> op7_4, string Dt>
1053 : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
1054 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd), IIC_VST1u,
1055 "vst1", Dt, "\\{$Vd\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
1056 let Inst{4} = Rn{4};
1058 class VST1QWB<bits<4> op7_4, string Dt>
1059 : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),
1060 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
1061 IIC_VST1x2u, "vst1", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
1062 "$Rn.addr = $wb", []> {
1063 let Inst{5-4} = Rn{5-4};
1066 def VST1d8_UPD : VST1DWB<{0,0,0,?}, "8">;
1067 def VST1d16_UPD : VST1DWB<{0,1,0,?}, "16">;
1068 def VST1d32_UPD : VST1DWB<{1,0,0,?}, "32">;
1069 def VST1d64_UPD : VST1DWB<{1,1,0,?}, "64">;
1071 def VST1q8_UPD : VST1QWB<{0,0,?,?}, "8">;
1072 def VST1q16_UPD : VST1QWB<{0,1,?,?}, "16">;
1073 def VST1q32_UPD : VST1QWB<{1,0,?,?}, "32">;
1074 def VST1q64_UPD : VST1QWB<{1,1,?,?}, "64">;
1076 def VST1q8Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1077 def VST1q16Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1078 def VST1q32Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1079 def VST1q64Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1081 // ...with 3 registers (some of these are only for the disassembler):
1082 class VST1D3<bits<4> op7_4, string Dt>
1083 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1084 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3),
1085 IIC_VST1x3, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1087 let Inst{4} = Rn{4};
1089 class VST1D3WB<bits<4> op7_4, string Dt>
1090 : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
1091 (ins addrmode6:$Rn, am6offset:$Rm,
1092 DPR:$Vd, DPR:$src2, DPR:$src3),
1093 IIC_VST1x3u, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1094 "$Rn.addr = $wb", []> {
1095 let Inst{4} = Rn{4};
1098 def VST1d8T : VST1D3<{0,0,0,?}, "8">;
1099 def VST1d16T : VST1D3<{0,1,0,?}, "16">;
1100 def VST1d32T : VST1D3<{1,0,0,?}, "32">;
1101 def VST1d64T : VST1D3<{1,1,0,?}, "64">;
1103 def VST1d8T_UPD : VST1D3WB<{0,0,0,?}, "8">;
1104 def VST1d16T_UPD : VST1D3WB<{0,1,0,?}, "16">;
1105 def VST1d32T_UPD : VST1D3WB<{1,0,0,?}, "32">;
1106 def VST1d64T_UPD : VST1D3WB<{1,1,0,?}, "64">;
1108 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
1109 def VST1d64TPseudo_UPD : VSTQQWBPseudo<IIC_VST1x3u>;
1111 // ...with 4 registers (some of these are only for the disassembler):
1112 class VST1D4<bits<4> op7_4, string Dt>
1113 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1114 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1115 IIC_VST1x4, "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", "",
1118 let Inst{5-4} = Rn{5-4};
1120 class VST1D4WB<bits<4> op7_4, string Dt>
1121 : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
1122 (ins addrmode6:$Rn, am6offset:$Rm,
1123 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST1x4u,
1124 "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1125 "$Rn.addr = $wb", []> {
1126 let Inst{5-4} = Rn{5-4};
1129 def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
1130 def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
1131 def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
1132 def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
1134 def VST1d8Q_UPD : VST1D4WB<{0,0,?,?}, "8">;
1135 def VST1d16Q_UPD : VST1D4WB<{0,1,?,?}, "16">;
1136 def VST1d32Q_UPD : VST1D4WB<{1,0,?,?}, "32">;
1137 def VST1d64Q_UPD : VST1D4WB<{1,1,?,?}, "64">;
1139 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
1140 def VST1d64QPseudo_UPD : VSTQQWBPseudo<IIC_VST1x4u>;
1142 // VST2 : Vector Store (multiple 2-element structures)
1143 class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
1144 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1145 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2),
1146 IIC_VST2, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1148 let Inst{5-4} = Rn{5-4};
1150 class VST2Q<bits<4> op7_4, string Dt>
1151 : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
1152 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1153 IIC_VST2x2, "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1156 let Inst{5-4} = Rn{5-4};
1159 def VST2d8 : VST2D<0b1000, {0,0,?,?}, "8">;
1160 def VST2d16 : VST2D<0b1000, {0,1,?,?}, "16">;
1161 def VST2d32 : VST2D<0b1000, {1,0,?,?}, "32">;
1163 def VST2q8 : VST2Q<{0,0,?,?}, "8">;
1164 def VST2q16 : VST2Q<{0,1,?,?}, "16">;
1165 def VST2q32 : VST2Q<{1,0,?,?}, "32">;
1167 def VST2d8Pseudo : VSTQPseudo<IIC_VST2>;
1168 def VST2d16Pseudo : VSTQPseudo<IIC_VST2>;
1169 def VST2d32Pseudo : VSTQPseudo<IIC_VST2>;
1171 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
1172 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
1173 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
1175 // ...with address register writeback:
1176 class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1177 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1178 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
1179 IIC_VST2u, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
1180 "$Rn.addr = $wb", []> {
1181 let Inst{5-4} = Rn{5-4};
1183 class VST2QWB<bits<4> op7_4, string Dt>
1184 : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1185 (ins addrmode6:$Rn, am6offset:$Rm,
1186 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST2x2u,
1187 "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1188 "$Rn.addr = $wb", []> {
1189 let Inst{5-4} = Rn{5-4};
1192 def VST2d8_UPD : VST2DWB<0b1000, {0,0,?,?}, "8">;
1193 def VST2d16_UPD : VST2DWB<0b1000, {0,1,?,?}, "16">;
1194 def VST2d32_UPD : VST2DWB<0b1000, {1,0,?,?}, "32">;
1196 def VST2q8_UPD : VST2QWB<{0,0,?,?}, "8">;
1197 def VST2q16_UPD : VST2QWB<{0,1,?,?}, "16">;
1198 def VST2q32_UPD : VST2QWB<{1,0,?,?}, "32">;
1200 def VST2d8Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1201 def VST2d16Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1202 def VST2d32Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1204 def VST2q8Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1205 def VST2q16Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1206 def VST2q32Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1208 // ...with double-spaced registers (for disassembly only):
1209 def VST2b8 : VST2D<0b1001, {0,0,?,?}, "8">;
1210 def VST2b16 : VST2D<0b1001, {0,1,?,?}, "16">;
1211 def VST2b32 : VST2D<0b1001, {1,0,?,?}, "32">;
1212 def VST2b8_UPD : VST2DWB<0b1001, {0,0,?,?}, "8">;
1213 def VST2b16_UPD : VST2DWB<0b1001, {0,1,?,?}, "16">;
1214 def VST2b32_UPD : VST2DWB<0b1001, {1,0,?,?}, "32">;
1216 // VST3 : Vector Store (multiple 3-element structures)
1217 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1218 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1219 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1220 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1222 let Inst{4} = Rn{4};
1225 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1226 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1227 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
1229 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1230 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1231 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
1233 // ...with address register writeback:
1234 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1235 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1236 (ins addrmode6:$Rn, am6offset:$Rm,
1237 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1238 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1239 "$Rn.addr = $wb", []> {
1240 let Inst{4} = Rn{4};
1243 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1244 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1245 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
1247 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1248 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1249 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1251 // ...with double-spaced registers (non-updating versions for disassembly only):
1252 def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1253 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1254 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1255 def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1256 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1257 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
1259 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1260 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1261 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1263 // ...alternate versions to be allocated odd register numbers:
1264 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1265 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1266 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1268 // VST4 : Vector Store (multiple 4-element structures)
1269 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1270 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1271 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1272 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1275 let Inst{5-4} = Rn{5-4};
1278 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1279 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1280 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
1282 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1283 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1284 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
1286 // ...with address register writeback:
1287 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1288 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1289 (ins addrmode6:$Rn, am6offset:$Rm,
1290 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1291 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1292 "$Rn.addr = $wb", []> {
1293 let Inst{5-4} = Rn{5-4};
1296 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
1297 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
1298 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
1300 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1301 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1302 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1304 // ...with double-spaced registers (non-updating versions for disassembly only):
1305 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
1306 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
1307 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
1308 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
1309 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
1310 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
1312 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1313 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1314 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1316 // ...alternate versions to be allocated odd register numbers:
1317 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1318 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1319 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1321 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1323 // Classes for VST*LN pseudo-instructions with multi-register operands.
1324 // These are expanded to real instructions after register allocation.
1325 class VSTQLNPseudo<InstrItinClass itin>
1326 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1328 class VSTQLNWBPseudo<InstrItinClass itin>
1329 : PseudoNLdSt<(outs GPR:$wb),
1330 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1331 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1332 class VSTQQLNPseudo<InstrItinClass itin>
1333 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1335 class VSTQQLNWBPseudo<InstrItinClass itin>
1336 : PseudoNLdSt<(outs GPR:$wb),
1337 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1338 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1339 class VSTQQQQLNPseudo<InstrItinClass itin>
1340 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1342 class VSTQQQQLNWBPseudo<InstrItinClass itin>
1343 : PseudoNLdSt<(outs GPR:$wb),
1344 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1345 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1347 // VST1LN : Vector Store (single element from one lane)
1348 class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1349 PatFrag StoreOp, SDNode ExtractOp>
1350 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1351 (ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane),
1352 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1353 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6:$Rn)]> {
1356 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1357 : VSTQLNPseudo<IIC_VST1ln> {
1358 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1362 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
1364 let Inst{7-5} = lane{2-0};
1366 def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
1368 let Inst{7-6} = lane{1-0};
1369 let Inst{4} = Rn{5};
1371 def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt> {
1372 let Inst{7} = lane{0};
1373 let Inst{5-4} = Rn{5-4};
1376 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
1377 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
1378 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
1380 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
1381 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1382 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
1383 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1385 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1387 // ...with address register writeback:
1388 class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1389 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1390 (ins addrmode6:$Rn, am6offset:$Rm,
1391 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
1392 "\\{$Vd[$lane]\\}, $Rn$Rm",
1393 "$Rn.addr = $wb", []>;
1395 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8"> {
1396 let Inst{7-5} = lane{2-0};
1398 def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16"> {
1399 let Inst{7-6} = lane{1-0};
1400 let Inst{4} = Rn{5};
1402 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32"> {
1403 let Inst{7} = lane{0};
1404 let Inst{5-4} = Rn{5-4};
1407 def VST1LNq8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST1lnu>;
1408 def VST1LNq16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST1lnu>;
1409 def VST1LNq32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST1lnu>;
1411 // VST2LN : Vector Store (single 2-element structure from one lane)
1412 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1413 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1414 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
1415 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
1418 let Inst{4} = Rn{4};
1421 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
1422 let Inst{7-5} = lane{2-0};
1424 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
1425 let Inst{7-6} = lane{1-0};
1427 def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
1428 let Inst{7} = lane{0};
1431 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1432 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1433 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1435 // ...with double-spaced registers:
1436 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
1437 let Inst{7-6} = lane{1-0};
1438 let Inst{4} = Rn{4};
1440 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
1441 let Inst{7} = lane{0};
1442 let Inst{4} = Rn{4};
1445 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1446 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1448 // ...with address register writeback:
1449 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1450 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1451 (ins addrmode6:$addr, am6offset:$offset,
1452 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
1453 "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset",
1454 "$addr.addr = $wb", []> {
1455 let Inst{4} = Rn{4};
1458 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
1459 let Inst{7-5} = lane{2-0};
1461 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
1462 let Inst{7-6} = lane{1-0};
1464 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
1465 let Inst{7} = lane{0};
1468 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1469 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1470 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1472 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
1473 let Inst{7-6} = lane{1-0};
1475 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
1476 let Inst{7} = lane{0};
1479 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1480 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1482 // VST3LN : Vector Store (single 3-element structure from one lane)
1483 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1484 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1485 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
1486 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
1487 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
1491 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
1492 let Inst{7-5} = lane{2-0};
1494 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
1495 let Inst{7-6} = lane{1-0};
1497 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
1498 let Inst{7} = lane{0};
1501 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1502 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1503 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1505 // ...with double-spaced registers:
1506 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
1507 let Inst{7-6} = lane{1-0};
1509 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
1510 let Inst{7} = lane{0};
1513 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1514 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1516 // ...with address register writeback:
1517 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1518 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1519 (ins addrmode6:$Rn, am6offset:$Rm,
1520 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1521 IIC_VST3lnu, "vst3", Dt,
1522 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
1523 "$Rn.addr = $wb", []>;
1525 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
1526 let Inst{7-5} = lane{2-0};
1528 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
1529 let Inst{7-6} = lane{1-0};
1531 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
1532 let Inst{7} = lane{0};
1535 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1536 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1537 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1539 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
1540 let Inst{7-6} = lane{1-0};
1542 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
1543 let Inst{7} = lane{0};
1546 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1547 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1549 // VST4LN : Vector Store (single 4-element structure from one lane)
1550 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1551 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1552 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
1553 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
1554 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
1557 let Inst{4} = Rn{4};
1560 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
1561 let Inst{7-5} = lane{2-0};
1563 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
1564 let Inst{7-6} = lane{1-0};
1566 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
1567 let Inst{7} = lane{0};
1568 let Inst{5} = Rn{5};
1571 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1572 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1573 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1575 // ...with double-spaced registers:
1576 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
1577 let Inst{7-6} = lane{1-0};
1579 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
1580 let Inst{7} = lane{0};
1581 let Inst{5} = Rn{5};
1584 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1585 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1587 // ...with address register writeback:
1588 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1589 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1590 (ins addrmode6:$Rn, am6offset:$Rm,
1591 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1592 IIC_VST4lnu, "vst4", Dt,
1593 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
1594 "$Rn.addr = $wb", []> {
1595 let Inst{4} = Rn{4};
1598 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
1599 let Inst{7-5} = lane{2-0};
1601 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
1602 let Inst{7-6} = lane{1-0};
1604 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
1605 let Inst{7} = lane{0};
1606 let Inst{5} = Rn{5};
1609 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1610 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1611 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1613 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
1614 let Inst{7-6} = lane{1-0};
1616 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
1617 let Inst{7} = lane{0};
1618 let Inst{5} = Rn{5};
1621 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1622 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1624 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1627 //===----------------------------------------------------------------------===//
1628 // NEON pattern fragments
1629 //===----------------------------------------------------------------------===//
1631 // Extract D sub-registers of Q registers.
1632 def DSubReg_i8_reg : SDNodeXForm<imm, [{
1633 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1634 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
1636 def DSubReg_i16_reg : SDNodeXForm<imm, [{
1637 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1638 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
1640 def DSubReg_i32_reg : SDNodeXForm<imm, [{
1641 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1642 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
1644 def DSubReg_f64_reg : SDNodeXForm<imm, [{
1645 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1646 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
1649 // Extract S sub-registers of Q/D registers.
1650 def SSubReg_f32_reg : SDNodeXForm<imm, [{
1651 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
1652 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
1655 // Translate lane numbers from Q registers to D subregs.
1656 def SubReg_i8_lane : SDNodeXForm<imm, [{
1657 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
1659 def SubReg_i16_lane : SDNodeXForm<imm, [{
1660 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
1662 def SubReg_i32_lane : SDNodeXForm<imm, [{
1663 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
1666 //===----------------------------------------------------------------------===//
1667 // Instruction Classes
1668 //===----------------------------------------------------------------------===//
1670 // Basic 2-register operations: single-, double- and quad-register.
1671 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1672 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1673 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1674 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
1675 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
1676 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
1677 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1678 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1679 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1680 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
1681 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
1682 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
1684 // Basic 2-register intrinsics, both double- and quad-register.
1685 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1686 bits<2> op17_16, bits<5> op11_7, bit op4,
1687 InstrItinClass itin, string OpcodeStr, string Dt,
1688 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1689 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
1690 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1691 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
1692 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1693 bits<2> op17_16, bits<5> op11_7, bit op4,
1694 InstrItinClass itin, string OpcodeStr, string Dt,
1695 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1696 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
1697 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1698 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
1700 // Narrow 2-register operations.
1701 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1702 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1703 InstrItinClass itin, string OpcodeStr, string Dt,
1704 ValueType TyD, ValueType TyQ, SDNode OpNode>
1705 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
1706 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1707 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
1709 // Narrow 2-register intrinsics.
1710 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1711 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1712 InstrItinClass itin, string OpcodeStr, string Dt,
1713 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
1714 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
1715 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1716 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
1718 // Long 2-register operations (currently only used for VMOVL).
1719 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1720 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1721 InstrItinClass itin, string OpcodeStr, string Dt,
1722 ValueType TyQ, ValueType TyD, SDNode OpNode>
1723 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
1724 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1725 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
1727 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
1728 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
1729 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
1730 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
1731 OpcodeStr, Dt, "$Vd, $Vm",
1732 "$src1 = $Vd, $src2 = $Vm", []>;
1733 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
1734 InstrItinClass itin, string OpcodeStr, string Dt>
1735 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
1736 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
1737 "$src1 = $Vd, $src2 = $Vm", []>;
1739 // Basic 3-register operations: single-, double- and quad-register.
1740 class N3VS<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1741 string OpcodeStr, string Dt>
1742 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1743 (outs DPR_VFP2:$Vd), (ins DPR_VFP2:$Vn, DPR_VFP2:$Vm), N3RegFrm,
1744 IIC_VBIND, OpcodeStr, Dt, "$Vd, $Vn, $Vm", "", []>;
1746 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1747 InstrItinClass itin, string OpcodeStr, string Dt,
1748 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1749 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1750 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1751 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1752 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
1753 let isCommutable = Commutable;
1755 // Same as N3VD but no data type.
1756 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1757 InstrItinClass itin, string OpcodeStr,
1758 ValueType ResTy, ValueType OpTy,
1759 SDNode OpNode, bit Commutable>
1760 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
1761 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1762 OpcodeStr, "$Vd, $Vn, $Vm", "",
1763 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
1764 let isCommutable = Commutable;
1767 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
1768 InstrItinClass itin, string OpcodeStr, string Dt,
1769 ValueType Ty, SDNode ShOp>
1770 : N3V<0, 1, op21_20, op11_8, 1, 0,
1771 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1772 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1774 (Ty (ShOp (Ty DPR:$Vn),
1775 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
1776 let isCommutable = 0;
1778 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
1779 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1780 : N3V<0, 1, op21_20, op11_8, 1, 0,
1781 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1782 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm[$lane]","",
1784 (Ty (ShOp (Ty DPR:$Vn),
1785 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
1786 let isCommutable = 0;
1789 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1790 InstrItinClass itin, string OpcodeStr, string Dt,
1791 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1792 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1793 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1794 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1795 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
1796 let isCommutable = Commutable;
1798 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1799 InstrItinClass itin, string OpcodeStr,
1800 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1801 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
1802 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1803 OpcodeStr, "$Vd, $Vn, $Vm", "",
1804 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
1805 let isCommutable = Commutable;
1807 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
1808 InstrItinClass itin, string OpcodeStr, string Dt,
1809 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1810 : N3V<1, 1, op21_20, op11_8, 1, 0,
1811 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1812 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1813 [(set (ResTy QPR:$Vd),
1814 (ResTy (ShOp (ResTy QPR:$Vn),
1815 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
1817 let isCommutable = 0;
1819 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
1820 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1821 : N3V<1, 1, op21_20, op11_8, 1, 0,
1822 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1823 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm[$lane]","",
1824 [(set (ResTy QPR:$Vd),
1825 (ResTy (ShOp (ResTy QPR:$Vn),
1826 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
1828 let isCommutable = 0;
1831 // Basic 3-register intrinsics, both double- and quad-register.
1832 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1833 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1834 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1835 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1836 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
1837 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1838 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
1839 let isCommutable = Commutable;
1841 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1842 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1843 : N3V<0, 1, op21_20, op11_8, 1, 0,
1844 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1845 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1847 (Ty (IntOp (Ty DPR:$Vn),
1848 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
1850 let isCommutable = 0;
1852 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1853 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1854 : N3V<0, 1, op21_20, op11_8, 1, 0,
1855 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1856 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1858 (Ty (IntOp (Ty DPR:$Vn),
1859 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
1860 let isCommutable = 0;
1862 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1863 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1864 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1865 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1866 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
1867 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
1868 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
1869 let isCommutable = 0;
1872 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1873 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1874 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1875 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1876 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
1877 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1878 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
1879 let isCommutable = Commutable;
1881 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1882 string OpcodeStr, string Dt,
1883 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1884 : N3V<1, 1, op21_20, op11_8, 1, 0,
1885 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1886 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1887 [(set (ResTy QPR:$Vd),
1888 (ResTy (IntOp (ResTy QPR:$Vn),
1889 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
1891 let isCommutable = 0;
1893 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1894 string OpcodeStr, string Dt,
1895 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1896 : N3V<1, 1, op21_20, op11_8, 1, 0,
1897 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1898 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1899 [(set (ResTy QPR:$Vd),
1900 (ResTy (IntOp (ResTy QPR:$Vn),
1901 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
1903 let isCommutable = 0;
1905 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1906 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1907 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1908 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1909 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
1910 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
1911 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
1912 let isCommutable = 0;
1915 // Multiply-Add/Sub operations: single-, double- and quad-register.
1916 class N3VSMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1917 InstrItinClass itin, string OpcodeStr, string Dt>
1918 : N3V<op24, op23, op21_20, op11_8, 0, op4, (outs DPR_VFP2:$Vd),
1919 (ins DPR_VFP2:$src1, DPR_VFP2:$Vn, DPR_VFP2:$Vm), N3RegFrm, itin,
1920 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd", []>;
1922 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1923 InstrItinClass itin, string OpcodeStr, string Dt,
1924 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode>
1925 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1926 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1927 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1928 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
1929 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
1931 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1932 string OpcodeStr, string Dt,
1933 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
1934 : N3V<0, 1, op21_20, op11_8, 1, 0,
1936 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1938 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
1940 (Ty (ShOp (Ty DPR:$src1),
1942 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
1944 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1945 string OpcodeStr, string Dt,
1946 ValueType Ty, SDNode MulOp, SDNode ShOp>
1947 : N3V<0, 1, op21_20, op11_8, 1, 0,
1949 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1951 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
1953 (Ty (ShOp (Ty DPR:$src1),
1955 (Ty (NEONvduplane (Ty DPR_8:$Vm),
1958 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1959 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
1960 SDPatternOperator MulOp, SDPatternOperator OpNode>
1961 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1962 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1963 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1964 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
1965 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
1966 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1967 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1968 SDPatternOperator MulOp, SDPatternOperator ShOp>
1969 : N3V<1, 1, op21_20, op11_8, 1, 0,
1971 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1973 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
1974 [(set (ResTy QPR:$Vd),
1975 (ResTy (ShOp (ResTy QPR:$src1),
1976 (ResTy (MulOp QPR:$Vn,
1977 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
1979 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1980 string OpcodeStr, string Dt,
1981 ValueType ResTy, ValueType OpTy,
1982 SDNode MulOp, SDNode ShOp>
1983 : N3V<1, 1, op21_20, op11_8, 1, 0,
1985 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1987 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
1988 [(set (ResTy QPR:$Vd),
1989 (ResTy (ShOp (ResTy QPR:$src1),
1990 (ResTy (MulOp QPR:$Vn,
1991 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
1994 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
1995 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1996 InstrItinClass itin, string OpcodeStr, string Dt,
1997 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
1998 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1999 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2000 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2001 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2002 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
2003 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2004 InstrItinClass itin, string OpcodeStr, string Dt,
2005 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2006 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2007 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2008 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2009 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2010 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2012 // Neon 3-argument intrinsics, both double- and quad-register.
2013 // The destination register is also used as the first source operand register.
2014 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2015 InstrItinClass itin, string OpcodeStr, string Dt,
2016 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2017 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2018 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2019 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2020 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2021 (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2022 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2023 InstrItinClass itin, string OpcodeStr, string Dt,
2024 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2025 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2026 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2027 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2028 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2029 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2031 // Long Multiply-Add/Sub operations.
2032 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2033 InstrItinClass itin, string OpcodeStr, string Dt,
2034 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2035 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2036 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2037 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2038 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2039 (TyQ (MulOp (TyD DPR:$Vn),
2040 (TyD DPR:$Vm)))))]>;
2041 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2042 InstrItinClass itin, string OpcodeStr, string Dt,
2043 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2044 : N3V<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2045 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2047 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2049 (OpNode (TyQ QPR:$src1),
2050 (TyQ (MulOp (TyD DPR:$Vn),
2051 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),
2053 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2054 InstrItinClass itin, string OpcodeStr, string Dt,
2055 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2056 : N3V<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2057 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2059 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2061 (OpNode (TyQ QPR:$src1),
2062 (TyQ (MulOp (TyD DPR:$Vn),
2063 (TyD (NEONvduplane (TyD DPR_8:$Vm),
2066 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
2067 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2068 InstrItinClass itin, string OpcodeStr, string Dt,
2069 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2071 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2072 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2073 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2074 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2075 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2076 (TyD DPR:$Vm)))))))]>;
2078 // Neon Long 3-argument intrinsic. The destination register is
2079 // a quad-register and is also used as the first source operand register.
2080 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2081 InstrItinClass itin, string OpcodeStr, string Dt,
2082 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
2083 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2084 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2085 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2087 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2088 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2089 string OpcodeStr, string Dt,
2090 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2091 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2093 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2095 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2096 [(set (ResTy QPR:$Vd),
2097 (ResTy (IntOp (ResTy QPR:$src1),
2099 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2101 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2102 InstrItinClass itin, string OpcodeStr, string Dt,
2103 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2104 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2106 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2108 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2109 [(set (ResTy QPR:$Vd),
2110 (ResTy (IntOp (ResTy QPR:$src1),
2112 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2115 // Narrowing 3-register intrinsics.
2116 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2117 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
2118 Intrinsic IntOp, bit Commutable>
2119 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2120 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2121 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2122 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2123 let isCommutable = Commutable;
2126 // Long 3-register operations.
2127 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2128 InstrItinClass itin, string OpcodeStr, string Dt,
2129 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
2130 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2131 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2132 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2133 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2134 let isCommutable = Commutable;
2136 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2137 InstrItinClass itin, string OpcodeStr, string Dt,
2138 ValueType TyQ, ValueType TyD, SDNode OpNode>
2139 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2140 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2141 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2143 (TyQ (OpNode (TyD DPR:$Vn),
2144 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
2145 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2146 InstrItinClass itin, string OpcodeStr, string Dt,
2147 ValueType TyQ, ValueType TyD, SDNode OpNode>
2148 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2149 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2150 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2152 (TyQ (OpNode (TyD DPR:$Vn),
2153 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
2155 // Long 3-register operations with explicitly extended operands.
2156 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2157 InstrItinClass itin, string OpcodeStr, string Dt,
2158 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
2160 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2161 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2162 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2163 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
2164 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2165 let isCommutable = Commutable;
2168 // Long 3-register intrinsics with explicit extend (VABDL).
2169 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2170 InstrItinClass itin, string OpcodeStr, string Dt,
2171 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2173 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2174 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2175 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2176 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2177 (TyD DPR:$Vm))))))]> {
2178 let isCommutable = Commutable;
2181 // Long 3-register intrinsics.
2182 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2183 InstrItinClass itin, string OpcodeStr, string Dt,
2184 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
2185 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2186 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2187 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2188 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2189 let isCommutable = Commutable;
2191 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2192 string OpcodeStr, string Dt,
2193 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2194 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2195 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2196 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2197 [(set (ResTy QPR:$Vd),
2198 (ResTy (IntOp (OpTy DPR:$Vn),
2199 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2201 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2202 InstrItinClass itin, string OpcodeStr, string Dt,
2203 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2204 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2205 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2206 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2207 [(set (ResTy QPR:$Vd),
2208 (ResTy (IntOp (OpTy DPR:$Vn),
2209 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2212 // Wide 3-register operations.
2213 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2214 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
2215 SDNode OpNode, SDNode ExtOp, bit Commutable>
2216 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2217 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
2218 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2219 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
2220 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2221 let isCommutable = Commutable;
2224 // Pairwise long 2-register intrinsics, both double- and quad-register.
2225 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2226 bits<2> op17_16, bits<5> op11_7, bit op4,
2227 string OpcodeStr, string Dt,
2228 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2229 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2230 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2231 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2232 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2233 bits<2> op17_16, bits<5> op11_7, bit op4,
2234 string OpcodeStr, string Dt,
2235 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2236 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2237 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2238 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2240 // Pairwise long 2-register accumulate intrinsics,
2241 // both double- and quad-register.
2242 // The destination register is also used as the first source operand register.
2243 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2244 bits<2> op17_16, bits<5> op11_7, bit op4,
2245 string OpcodeStr, string Dt,
2246 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2247 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
2248 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
2249 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2250 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
2251 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2252 bits<2> op17_16, bits<5> op11_7, bit op4,
2253 string OpcodeStr, string Dt,
2254 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2255 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
2256 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
2257 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2258 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
2260 // Shift by immediate,
2261 // both double- and quad-register.
2262 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2263 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2264 ValueType Ty, SDNode OpNode>
2265 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2266 (outs DPR:$Vd), (ins DPR:$Vm, i32imm:$SIMM), f, itin,
2267 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2268 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
2269 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2270 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2271 ValueType Ty, SDNode OpNode>
2272 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2273 (outs QPR:$Vd), (ins QPR:$Vm, i32imm:$SIMM), f, itin,
2274 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2275 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
2277 // Long shift by immediate.
2278 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2279 string OpcodeStr, string Dt,
2280 ValueType ResTy, ValueType OpTy, SDNode OpNode>
2281 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2282 (outs QPR:$Vd), (ins DPR:$Vm, i32imm:$SIMM), N2RegVShLFrm,
2283 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2284 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm),
2285 (i32 imm:$SIMM))))]>;
2287 // Narrow shift by immediate.
2288 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2289 InstrItinClass itin, string OpcodeStr, string Dt,
2290 ValueType ResTy, ValueType OpTy, SDNode OpNode>
2291 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2292 (outs DPR:$Vd), (ins QPR:$Vm, i32imm:$SIMM), N2RegVShRFrm, itin,
2293 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2294 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
2295 (i32 imm:$SIMM))))]>;
2297 // Shift right by immediate and accumulate,
2298 // both double- and quad-register.
2299 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2300 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2301 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2302 (ins DPR:$src1, DPR:$Vm, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2303 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2304 [(set DPR:$Vd, (Ty (add DPR:$src1,
2305 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
2306 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2307 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2308 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2309 (ins QPR:$src1, QPR:$Vm, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2310 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2311 [(set QPR:$Vd, (Ty (add QPR:$src1,
2312 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
2314 // Shift by immediate and insert,
2315 // both double- and quad-register.
2316 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2317 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
2318 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2319 (ins DPR:$src1, DPR:$Vm, i32imm:$SIMM), f, IIC_VSHLiD,
2320 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2321 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
2322 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2323 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
2324 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2325 (ins QPR:$src1, QPR:$Vm, i32imm:$SIMM), f, IIC_VSHLiQ,
2326 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2327 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
2329 // Convert, with fractional bits immediate,
2330 // both double- and quad-register.
2331 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2332 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2334 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2335 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2336 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2337 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
2338 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2339 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2341 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2342 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2343 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2344 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
2346 //===----------------------------------------------------------------------===//
2348 //===----------------------------------------------------------------------===//
2350 // Abbreviations used in multiclass suffixes:
2351 // Q = quarter int (8 bit) elements
2352 // H = half int (16 bit) elements
2353 // S = single int (32 bit) elements
2354 // D = double int (64 bit) elements
2356 // Neon 2-register vector operations -- for disassembly only.
2358 // First with only element sizes of 8, 16 and 32 bits:
2359 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2360 bits<5> op11_7, bit op4, string opc, string Dt,
2361 string asm, SDNode OpNode> {
2362 // 64-bit vector types.
2363 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
2364 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2365 opc, !strconcat(Dt, "8"), asm, "",
2366 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
2367 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
2368 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2369 opc, !strconcat(Dt, "16"), asm, "",
2370 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>;
2371 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2372 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2373 opc, !strconcat(Dt, "32"), asm, "",
2374 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>;
2375 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2376 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2377 opc, "f32", asm, "",
2378 [(set DPR:$Vd, (v2f32 (OpNode (v2f32 DPR:$Vm))))]> {
2379 let Inst{10} = 1; // overwrite F = 1
2382 // 128-bit vector types.
2383 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
2384 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2385 opc, !strconcat(Dt, "8"), asm, "",
2386 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
2387 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
2388 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2389 opc, !strconcat(Dt, "16"), asm, "",
2390 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
2391 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2392 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2393 opc, !strconcat(Dt, "32"), asm, "",
2394 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
2395 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2396 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2397 opc, "f32", asm, "",
2398 [(set QPR:$Vd, (v4f32 (OpNode (v4f32 QPR:$Vm))))]> {
2399 let Inst{10} = 1; // overwrite F = 1
2403 // Neon 3-register vector operations.
2405 // First with only element sizes of 8, 16 and 32 bits:
2406 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2407 InstrItinClass itinD16, InstrItinClass itinD32,
2408 InstrItinClass itinQ16, InstrItinClass itinQ32,
2409 string OpcodeStr, string Dt,
2410 SDNode OpNode, bit Commutable = 0> {
2411 // 64-bit vector types.
2412 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
2413 OpcodeStr, !strconcat(Dt, "8"),
2414 v8i8, v8i8, OpNode, Commutable>;
2415 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
2416 OpcodeStr, !strconcat(Dt, "16"),
2417 v4i16, v4i16, OpNode, Commutable>;
2418 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
2419 OpcodeStr, !strconcat(Dt, "32"),
2420 v2i32, v2i32, OpNode, Commutable>;
2422 // 128-bit vector types.
2423 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
2424 OpcodeStr, !strconcat(Dt, "8"),
2425 v16i8, v16i8, OpNode, Commutable>;
2426 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
2427 OpcodeStr, !strconcat(Dt, "16"),
2428 v8i16, v8i16, OpNode, Commutable>;
2429 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
2430 OpcodeStr, !strconcat(Dt, "32"),
2431 v4i32, v4i32, OpNode, Commutable>;
2434 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
2435 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2437 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
2439 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2440 v8i16, v4i16, ShOp>;
2441 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
2442 v4i32, v2i32, ShOp>;
2445 // ....then also with element size 64 bits:
2446 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2447 InstrItinClass itinD, InstrItinClass itinQ,
2448 string OpcodeStr, string Dt,
2449 SDNode OpNode, bit Commutable = 0>
2450 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
2451 OpcodeStr, Dt, OpNode, Commutable> {
2452 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
2453 OpcodeStr, !strconcat(Dt, "64"),
2454 v1i64, v1i64, OpNode, Commutable>;
2455 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
2456 OpcodeStr, !strconcat(Dt, "64"),
2457 v2i64, v2i64, OpNode, Commutable>;
2461 // Neon Narrowing 2-register vector operations,
2462 // source operand element sizes of 16, 32 and 64 bits:
2463 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2464 bits<5> op11_7, bit op6, bit op4,
2465 InstrItinClass itin, string OpcodeStr, string Dt,
2467 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2468 itin, OpcodeStr, !strconcat(Dt, "16"),
2469 v8i8, v8i16, OpNode>;
2470 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2471 itin, OpcodeStr, !strconcat(Dt, "32"),
2472 v4i16, v4i32, OpNode>;
2473 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2474 itin, OpcodeStr, !strconcat(Dt, "64"),
2475 v2i32, v2i64, OpNode>;
2478 // Neon Narrowing 2-register vector intrinsics,
2479 // source operand element sizes of 16, 32 and 64 bits:
2480 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2481 bits<5> op11_7, bit op6, bit op4,
2482 InstrItinClass itin, string OpcodeStr, string Dt,
2484 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2485 itin, OpcodeStr, !strconcat(Dt, "16"),
2486 v8i8, v8i16, IntOp>;
2487 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2488 itin, OpcodeStr, !strconcat(Dt, "32"),
2489 v4i16, v4i32, IntOp>;
2490 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2491 itin, OpcodeStr, !strconcat(Dt, "64"),
2492 v2i32, v2i64, IntOp>;
2496 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
2497 // source operand element sizes of 16, 32 and 64 bits:
2498 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
2499 string OpcodeStr, string Dt, SDNode OpNode> {
2500 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2501 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
2502 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2503 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2504 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2505 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2509 // Neon 3-register vector intrinsics.
2511 // First with only element sizes of 16 and 32 bits:
2512 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2513 InstrItinClass itinD16, InstrItinClass itinD32,
2514 InstrItinClass itinQ16, InstrItinClass itinQ32,
2515 string OpcodeStr, string Dt,
2516 Intrinsic IntOp, bit Commutable = 0> {
2517 // 64-bit vector types.
2518 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
2519 OpcodeStr, !strconcat(Dt, "16"),
2520 v4i16, v4i16, IntOp, Commutable>;
2521 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
2522 OpcodeStr, !strconcat(Dt, "32"),
2523 v2i32, v2i32, IntOp, Commutable>;
2525 // 128-bit vector types.
2526 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2527 OpcodeStr, !strconcat(Dt, "16"),
2528 v8i16, v8i16, IntOp, Commutable>;
2529 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2530 OpcodeStr, !strconcat(Dt, "32"),
2531 v4i32, v4i32, IntOp, Commutable>;
2533 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2534 InstrItinClass itinD16, InstrItinClass itinD32,
2535 InstrItinClass itinQ16, InstrItinClass itinQ32,
2536 string OpcodeStr, string Dt,
2538 // 64-bit vector types.
2539 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
2540 OpcodeStr, !strconcat(Dt, "16"),
2541 v4i16, v4i16, IntOp>;
2542 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
2543 OpcodeStr, !strconcat(Dt, "32"),
2544 v2i32, v2i32, IntOp>;
2546 // 128-bit vector types.
2547 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2548 OpcodeStr, !strconcat(Dt, "16"),
2549 v8i16, v8i16, IntOp>;
2550 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2551 OpcodeStr, !strconcat(Dt, "32"),
2552 v4i32, v4i32, IntOp>;
2555 multiclass N3VIntSL_HS<bits<4> op11_8,
2556 InstrItinClass itinD16, InstrItinClass itinD32,
2557 InstrItinClass itinQ16, InstrItinClass itinQ32,
2558 string OpcodeStr, string Dt, Intrinsic IntOp> {
2559 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
2560 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
2561 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
2562 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
2563 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
2564 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
2565 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
2566 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
2569 // ....then also with element size of 8 bits:
2570 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2571 InstrItinClass itinD16, InstrItinClass itinD32,
2572 InstrItinClass itinQ16, InstrItinClass itinQ32,
2573 string OpcodeStr, string Dt,
2574 Intrinsic IntOp, bit Commutable = 0>
2575 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2576 OpcodeStr, Dt, IntOp, Commutable> {
2577 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
2578 OpcodeStr, !strconcat(Dt, "8"),
2579 v8i8, v8i8, IntOp, Commutable>;
2580 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2581 OpcodeStr, !strconcat(Dt, "8"),
2582 v16i8, v16i8, IntOp, Commutable>;
2584 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2585 InstrItinClass itinD16, InstrItinClass itinD32,
2586 InstrItinClass itinQ16, InstrItinClass itinQ32,
2587 string OpcodeStr, string Dt,
2589 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2590 OpcodeStr, Dt, IntOp> {
2591 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
2592 OpcodeStr, !strconcat(Dt, "8"),
2594 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2595 OpcodeStr, !strconcat(Dt, "8"),
2596 v16i8, v16i8, IntOp>;
2600 // ....then also with element size of 64 bits:
2601 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2602 InstrItinClass itinD16, InstrItinClass itinD32,
2603 InstrItinClass itinQ16, InstrItinClass itinQ32,
2604 string OpcodeStr, string Dt,
2605 Intrinsic IntOp, bit Commutable = 0>
2606 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2607 OpcodeStr, Dt, IntOp, Commutable> {
2608 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
2609 OpcodeStr, !strconcat(Dt, "64"),
2610 v1i64, v1i64, IntOp, Commutable>;
2611 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2612 OpcodeStr, !strconcat(Dt, "64"),
2613 v2i64, v2i64, IntOp, Commutable>;
2615 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2616 InstrItinClass itinD16, InstrItinClass itinD32,
2617 InstrItinClass itinQ16, InstrItinClass itinQ32,
2618 string OpcodeStr, string Dt,
2620 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2621 OpcodeStr, Dt, IntOp> {
2622 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
2623 OpcodeStr, !strconcat(Dt, "64"),
2624 v1i64, v1i64, IntOp>;
2625 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2626 OpcodeStr, !strconcat(Dt, "64"),
2627 v2i64, v2i64, IntOp>;
2630 // Neon Narrowing 3-register vector intrinsics,
2631 // source operand element sizes of 16, 32 and 64 bits:
2632 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2633 string OpcodeStr, string Dt,
2634 Intrinsic IntOp, bit Commutable = 0> {
2635 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
2636 OpcodeStr, !strconcat(Dt, "16"),
2637 v8i8, v8i16, IntOp, Commutable>;
2638 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
2639 OpcodeStr, !strconcat(Dt, "32"),
2640 v4i16, v4i32, IntOp, Commutable>;
2641 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
2642 OpcodeStr, !strconcat(Dt, "64"),
2643 v2i32, v2i64, IntOp, Commutable>;
2647 // Neon Long 3-register vector operations.
2649 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2650 InstrItinClass itin16, InstrItinClass itin32,
2651 string OpcodeStr, string Dt,
2652 SDNode OpNode, bit Commutable = 0> {
2653 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
2654 OpcodeStr, !strconcat(Dt, "8"),
2655 v8i16, v8i8, OpNode, Commutable>;
2656 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
2657 OpcodeStr, !strconcat(Dt, "16"),
2658 v4i32, v4i16, OpNode, Commutable>;
2659 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
2660 OpcodeStr, !strconcat(Dt, "32"),
2661 v2i64, v2i32, OpNode, Commutable>;
2664 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
2665 InstrItinClass itin, string OpcodeStr, string Dt,
2667 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
2668 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2669 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
2670 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2673 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2674 InstrItinClass itin16, InstrItinClass itin32,
2675 string OpcodeStr, string Dt,
2676 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2677 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
2678 OpcodeStr, !strconcat(Dt, "8"),
2679 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2680 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
2681 OpcodeStr, !strconcat(Dt, "16"),
2682 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2683 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
2684 OpcodeStr, !strconcat(Dt, "32"),
2685 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2688 // Neon Long 3-register vector intrinsics.
2690 // First with only element sizes of 16 and 32 bits:
2691 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2692 InstrItinClass itin16, InstrItinClass itin32,
2693 string OpcodeStr, string Dt,
2694 Intrinsic IntOp, bit Commutable = 0> {
2695 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
2696 OpcodeStr, !strconcat(Dt, "16"),
2697 v4i32, v4i16, IntOp, Commutable>;
2698 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
2699 OpcodeStr, !strconcat(Dt, "32"),
2700 v2i64, v2i32, IntOp, Commutable>;
2703 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
2704 InstrItinClass itin, string OpcodeStr, string Dt,
2706 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
2707 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2708 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
2709 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2712 // ....then also with element size of 8 bits:
2713 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2714 InstrItinClass itin16, InstrItinClass itin32,
2715 string OpcodeStr, string Dt,
2716 Intrinsic IntOp, bit Commutable = 0>
2717 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
2718 IntOp, Commutable> {
2719 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
2720 OpcodeStr, !strconcat(Dt, "8"),
2721 v8i16, v8i8, IntOp, Commutable>;
2724 // ....with explicit extend (VABDL).
2725 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2726 InstrItinClass itin, string OpcodeStr, string Dt,
2727 Intrinsic IntOp, SDNode ExtOp, bit Commutable = 0> {
2728 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
2729 OpcodeStr, !strconcat(Dt, "8"),
2730 v8i16, v8i8, IntOp, ExtOp, Commutable>;
2731 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
2732 OpcodeStr, !strconcat(Dt, "16"),
2733 v4i32, v4i16, IntOp, ExtOp, Commutable>;
2734 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
2735 OpcodeStr, !strconcat(Dt, "32"),
2736 v2i64, v2i32, IntOp, ExtOp, Commutable>;
2740 // Neon Wide 3-register vector intrinsics,
2741 // source operand element sizes of 8, 16 and 32 bits:
2742 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2743 string OpcodeStr, string Dt,
2744 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2745 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
2746 OpcodeStr, !strconcat(Dt, "8"),
2747 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2748 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
2749 OpcodeStr, !strconcat(Dt, "16"),
2750 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2751 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
2752 OpcodeStr, !strconcat(Dt, "32"),
2753 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2757 // Neon Multiply-Op vector operations,
2758 // element sizes of 8, 16 and 32 bits:
2759 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2760 InstrItinClass itinD16, InstrItinClass itinD32,
2761 InstrItinClass itinQ16, InstrItinClass itinQ32,
2762 string OpcodeStr, string Dt, SDNode OpNode> {
2763 // 64-bit vector types.
2764 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
2765 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
2766 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
2767 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
2768 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
2769 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
2771 // 128-bit vector types.
2772 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
2773 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
2774 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
2775 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
2776 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
2777 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
2780 multiclass N3VMulOpSL_HS<bits<4> op11_8,
2781 InstrItinClass itinD16, InstrItinClass itinD32,
2782 InstrItinClass itinQ16, InstrItinClass itinQ32,
2783 string OpcodeStr, string Dt, SDNode ShOp> {
2784 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
2785 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
2786 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
2787 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
2788 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
2789 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
2791 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
2792 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
2796 // Neon Intrinsic-Op vector operations,
2797 // element sizes of 8, 16 and 32 bits:
2798 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2799 InstrItinClass itinD, InstrItinClass itinQ,
2800 string OpcodeStr, string Dt, Intrinsic IntOp,
2802 // 64-bit vector types.
2803 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
2804 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
2805 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
2806 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
2807 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
2808 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
2810 // 128-bit vector types.
2811 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
2812 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
2813 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
2814 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
2815 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
2816 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
2819 // Neon 3-argument intrinsics,
2820 // element sizes of 8, 16 and 32 bits:
2821 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2822 InstrItinClass itinD, InstrItinClass itinQ,
2823 string OpcodeStr, string Dt, Intrinsic IntOp> {
2824 // 64-bit vector types.
2825 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
2826 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2827 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
2828 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
2829 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
2830 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
2832 // 128-bit vector types.
2833 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
2834 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
2835 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
2836 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
2837 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
2838 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
2842 // Neon Long Multiply-Op vector operations,
2843 // element sizes of 8, 16 and 32 bits:
2844 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2845 InstrItinClass itin16, InstrItinClass itin32,
2846 string OpcodeStr, string Dt, SDNode MulOp,
2848 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
2849 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
2850 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
2851 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
2852 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
2853 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
2856 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
2857 string Dt, SDNode MulOp, SDNode OpNode> {
2858 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
2859 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
2860 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
2861 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
2865 // Neon Long 3-argument intrinsics.
2867 // First with only element sizes of 16 and 32 bits:
2868 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2869 InstrItinClass itin16, InstrItinClass itin32,
2870 string OpcodeStr, string Dt, Intrinsic IntOp> {
2871 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
2872 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2873 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
2874 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2877 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
2878 string OpcodeStr, string Dt, Intrinsic IntOp> {
2879 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
2880 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
2881 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
2882 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2885 // ....then also with element size of 8 bits:
2886 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2887 InstrItinClass itin16, InstrItinClass itin32,
2888 string OpcodeStr, string Dt, Intrinsic IntOp>
2889 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
2890 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
2891 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
2894 // ....with explicit extend (VABAL).
2895 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2896 InstrItinClass itin, string OpcodeStr, string Dt,
2897 Intrinsic IntOp, SDNode ExtOp, SDNode OpNode> {
2898 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
2899 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
2900 IntOp, ExtOp, OpNode>;
2901 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
2902 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
2903 IntOp, ExtOp, OpNode>;
2904 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
2905 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
2906 IntOp, ExtOp, OpNode>;
2910 // Neon 2-register vector intrinsics,
2911 // element sizes of 8, 16 and 32 bits:
2912 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2913 bits<5> op11_7, bit op4,
2914 InstrItinClass itinD, InstrItinClass itinQ,
2915 string OpcodeStr, string Dt, Intrinsic IntOp> {
2916 // 64-bit vector types.
2917 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2918 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2919 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2920 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
2921 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2922 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
2924 // 128-bit vector types.
2925 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2926 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
2927 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2928 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
2929 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2930 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
2934 // Neon Pairwise long 2-register intrinsics,
2935 // element sizes of 8, 16 and 32 bits:
2936 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2937 bits<5> op11_7, bit op4,
2938 string OpcodeStr, string Dt, Intrinsic IntOp> {
2939 // 64-bit vector types.
2940 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2941 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
2942 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2943 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
2944 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2945 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
2947 // 128-bit vector types.
2948 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2949 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
2950 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2951 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
2952 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2953 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
2957 // Neon Pairwise long 2-register accumulate intrinsics,
2958 // element sizes of 8, 16 and 32 bits:
2959 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2960 bits<5> op11_7, bit op4,
2961 string OpcodeStr, string Dt, Intrinsic IntOp> {
2962 // 64-bit vector types.
2963 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2964 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
2965 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2966 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
2967 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2968 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
2970 // 128-bit vector types.
2971 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2972 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
2973 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2974 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
2975 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2976 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
2980 // Neon 2-register vector shift by immediate,
2981 // with f of either N2RegVShLFrm or N2RegVShRFrm
2982 // element sizes of 8, 16, 32 and 64 bits:
2983 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2984 InstrItinClass itin, string OpcodeStr, string Dt,
2985 SDNode OpNode, Format f> {
2986 // 64-bit vector types.
2987 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2988 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
2989 let Inst{21-19} = 0b001; // imm6 = 001xxx
2991 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2992 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
2993 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2995 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2996 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
2997 let Inst{21} = 0b1; // imm6 = 1xxxxx
2999 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, f, itin,
3000 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3003 // 128-bit vector types.
3004 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
3005 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3006 let Inst{21-19} = 0b001; // imm6 = 001xxx
3008 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
3009 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3010 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3012 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
3013 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3014 let Inst{21} = 0b1; // imm6 = 1xxxxx
3016 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, f, itin,
3017 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3021 // Neon Shift-Accumulate vector operations,
3022 // element sizes of 8, 16, 32 and 64 bits:
3023 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3024 string OpcodeStr, string Dt, SDNode ShOp> {
3025 // 64-bit vector types.
3026 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4,
3027 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
3028 let Inst{21-19} = 0b001; // imm6 = 001xxx
3030 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4,
3031 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
3032 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3034 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4,
3035 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
3036 let Inst{21} = 0b1; // imm6 = 1xxxxx
3038 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4,
3039 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
3042 // 128-bit vector types.
3043 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4,
3044 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
3045 let Inst{21-19} = 0b001; // imm6 = 001xxx
3047 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4,
3048 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
3049 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3051 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4,
3052 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
3053 let Inst{21} = 0b1; // imm6 = 1xxxxx
3055 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4,
3056 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
3061 // Neon Shift-Insert vector operations,
3062 // with f of either N2RegVShLFrm or N2RegVShRFrm
3063 // element sizes of 8, 16, 32 and 64 bits:
3064 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3065 string OpcodeStr, SDNode ShOp,
3067 // 64-bit vector types.
3068 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4,
3069 f, OpcodeStr, "8", v8i8, ShOp> {
3070 let Inst{21-19} = 0b001; // imm6 = 001xxx
3072 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4,
3073 f, OpcodeStr, "16", v4i16, ShOp> {
3074 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3076 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4,
3077 f, OpcodeStr, "32", v2i32, ShOp> {
3078 let Inst{21} = 0b1; // imm6 = 1xxxxx
3080 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4,
3081 f, OpcodeStr, "64", v1i64, ShOp>;
3084 // 128-bit vector types.
3085 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4,
3086 f, OpcodeStr, "8", v16i8, ShOp> {
3087 let Inst{21-19} = 0b001; // imm6 = 001xxx
3089 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4,
3090 f, OpcodeStr, "16", v8i16, ShOp> {
3091 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3093 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4,
3094 f, OpcodeStr, "32", v4i32, ShOp> {
3095 let Inst{21} = 0b1; // imm6 = 1xxxxx
3097 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4,
3098 f, OpcodeStr, "64", v2i64, ShOp>;
3102 // Neon Shift Long operations,
3103 // element sizes of 8, 16, 32 bits:
3104 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3105 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
3106 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3107 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
3108 let Inst{21-19} = 0b001; // imm6 = 001xxx
3110 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3111 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
3112 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3114 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3115 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
3116 let Inst{21} = 0b1; // imm6 = 1xxxxx
3120 // Neon Shift Narrow operations,
3121 // element sizes of 16, 32, 64 bits:
3122 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3123 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
3125 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3126 OpcodeStr, !strconcat(Dt, "16"), v8i8, v8i16, OpNode> {
3127 let Inst{21-19} = 0b001; // imm6 = 001xxx
3129 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3130 OpcodeStr, !strconcat(Dt, "32"), v4i16, v4i32, OpNode> {
3131 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3133 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3134 OpcodeStr, !strconcat(Dt, "64"), v2i32, v2i64, OpNode> {
3135 let Inst{21} = 0b1; // imm6 = 1xxxxx
3139 //===----------------------------------------------------------------------===//
3140 // Instruction Definitions.
3141 //===----------------------------------------------------------------------===//
3143 // Vector Add Operations.
3145 // VADD : Vector Add (integer and floating-point)
3146 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
3148 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
3149 v2f32, v2f32, fadd, 1>;
3150 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
3151 v4f32, v4f32, fadd, 1>;
3152 // VADDL : Vector Add Long (Q = D + D)
3153 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3154 "vaddl", "s", add, sext, 1>;
3155 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3156 "vaddl", "u", add, zext, 1>;
3157 // VADDW : Vector Add Wide (Q = Q + D)
3158 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
3159 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
3160 // VHADD : Vector Halving Add
3161 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
3162 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3163 "vhadd", "s", int_arm_neon_vhadds, 1>;
3164 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
3165 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3166 "vhadd", "u", int_arm_neon_vhaddu, 1>;
3167 // VRHADD : Vector Rounding Halving Add
3168 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
3169 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3170 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
3171 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
3172 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3173 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
3174 // VQADD : Vector Saturating Add
3175 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
3176 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3177 "vqadd", "s", int_arm_neon_vqadds, 1>;
3178 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
3179 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3180 "vqadd", "u", int_arm_neon_vqaddu, 1>;
3181 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
3182 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
3183 int_arm_neon_vaddhn, 1>;
3184 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
3185 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
3186 int_arm_neon_vraddhn, 1>;
3188 // Vector Multiply Operations.
3190 // VMUL : Vector Multiply (integer, polynomial and floating-point)
3191 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
3192 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
3193 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
3194 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
3195 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
3196 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
3197 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
3198 v2f32, v2f32, fmul, 1>;
3199 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
3200 v4f32, v4f32, fmul, 1>;
3201 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
3202 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
3203 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
3206 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
3207 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
3208 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
3209 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3210 (DSubReg_i16_reg imm:$lane))),
3211 (SubReg_i16_lane imm:$lane)))>;
3212 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
3213 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
3214 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
3215 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3216 (DSubReg_i32_reg imm:$lane))),
3217 (SubReg_i32_lane imm:$lane)))>;
3218 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
3219 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
3220 (v4f32 (VMULslfq (v4f32 QPR:$src1),
3221 (v2f32 (EXTRACT_SUBREG QPR:$src2,
3222 (DSubReg_i32_reg imm:$lane))),
3223 (SubReg_i32_lane imm:$lane)))>;
3225 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
3226 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
3227 IIC_VMULi16Q, IIC_VMULi32Q,
3228 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
3229 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
3230 IIC_VMULi16Q, IIC_VMULi32Q,
3231 "vqdmulh", "s", int_arm_neon_vqdmulh>;
3232 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
3233 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3235 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
3236 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3237 (DSubReg_i16_reg imm:$lane))),
3238 (SubReg_i16_lane imm:$lane)))>;
3239 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
3240 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3242 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
3243 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3244 (DSubReg_i32_reg imm:$lane))),
3245 (SubReg_i32_lane imm:$lane)))>;
3247 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
3248 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
3249 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
3250 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
3251 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
3252 IIC_VMULi16Q, IIC_VMULi32Q,
3253 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
3254 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
3255 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3257 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
3258 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3259 (DSubReg_i16_reg imm:$lane))),
3260 (SubReg_i16_lane imm:$lane)))>;
3261 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
3262 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3264 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
3265 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3266 (DSubReg_i32_reg imm:$lane))),
3267 (SubReg_i32_lane imm:$lane)))>;
3269 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
3270 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3271 "vmull", "s", NEONvmulls, 1>;
3272 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3273 "vmull", "u", NEONvmullu, 1>;
3274 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
3275 v8i16, v8i8, int_arm_neon_vmullp, 1>;
3276 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
3277 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
3279 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
3280 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
3281 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
3282 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
3283 "vqdmull", "s", int_arm_neon_vqdmull>;
3285 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
3287 // VMLA : Vector Multiply Accumulate (integer and floating-point)
3288 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3289 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3290 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
3291 v2f32, fmul_su, fadd_mlx>,
3292 Requires<[HasNEON, UseFPVMLx]>;
3293 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
3294 v4f32, fmul_su, fadd_mlx>,
3295 Requires<[HasNEON, UseFPVMLx]>;
3296 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
3297 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3298 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
3299 v2f32, fmul_su, fadd_mlx>,
3300 Requires<[HasNEON, UseFPVMLx]>;
3301 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
3302 v4f32, v2f32, fmul_su, fadd_mlx>,
3303 Requires<[HasNEON, UseFPVMLx]>;
3305 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
3306 (mul (v8i16 QPR:$src2),
3307 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3308 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3309 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3310 (DSubReg_i16_reg imm:$lane))),
3311 (SubReg_i16_lane imm:$lane)))>;
3313 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
3314 (mul (v4i32 QPR:$src2),
3315 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3316 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3317 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3318 (DSubReg_i32_reg imm:$lane))),
3319 (SubReg_i32_lane imm:$lane)))>;
3321 def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1),
3322 (fmul_su (v4f32 QPR:$src2),
3323 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3324 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
3326 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3327 (DSubReg_i32_reg imm:$lane))),
3328 (SubReg_i32_lane imm:$lane)))>,
3329 Requires<[HasNEON, UseFPVMLx]>;
3331 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
3332 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3333 "vmlal", "s", NEONvmulls, add>;
3334 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3335 "vmlal", "u", NEONvmullu, add>;
3337 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
3338 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
3340 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
3341 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3342 "vqdmlal", "s", int_arm_neon_vqdmlal>;
3343 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
3345 // VMLS : Vector Multiply Subtract (integer and floating-point)
3346 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3347 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3348 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
3349 v2f32, fmul_su, fsub_mlx>,
3350 Requires<[HasNEON, UseFPVMLx]>;
3351 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
3352 v4f32, fmul_su, fsub_mlx>,
3353 Requires<[HasNEON, UseFPVMLx]>;
3354 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
3355 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3356 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
3357 v2f32, fmul_su, fsub_mlx>,
3358 Requires<[HasNEON, UseFPVMLx]>;
3359 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
3360 v4f32, v2f32, fmul_su, fsub_mlx>,
3361 Requires<[HasNEON, UseFPVMLx]>;
3363 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
3364 (mul (v8i16 QPR:$src2),
3365 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3366 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3367 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3368 (DSubReg_i16_reg imm:$lane))),
3369 (SubReg_i16_lane imm:$lane)))>;
3371 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
3372 (mul (v4i32 QPR:$src2),
3373 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3374 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3375 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3376 (DSubReg_i32_reg imm:$lane))),
3377 (SubReg_i32_lane imm:$lane)))>;
3379 def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1),
3380 (fmul_su (v4f32 QPR:$src2),
3381 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3382 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
3383 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3384 (DSubReg_i32_reg imm:$lane))),
3385 (SubReg_i32_lane imm:$lane)))>,
3386 Requires<[HasNEON, UseFPVMLx]>;
3388 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
3389 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3390 "vmlsl", "s", NEONvmulls, sub>;
3391 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3392 "vmlsl", "u", NEONvmullu, sub>;
3394 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
3395 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
3397 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
3398 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
3399 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3400 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3402 // Vector Subtract Operations.
3404 // VSUB : Vector Subtract (integer and floating-point)
3405 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
3406 "vsub", "i", sub, 0>;
3407 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
3408 v2f32, v2f32, fsub, 0>;
3409 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
3410 v4f32, v4f32, fsub, 0>;
3411 // VSUBL : Vector Subtract Long (Q = D - D)
3412 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3413 "vsubl", "s", sub, sext, 0>;
3414 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3415 "vsubl", "u", sub, zext, 0>;
3416 // VSUBW : Vector Subtract Wide (Q = Q - D)
3417 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
3418 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
3419 // VHSUB : Vector Halving Subtract
3420 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
3421 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3422 "vhsub", "s", int_arm_neon_vhsubs, 0>;
3423 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
3424 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3425 "vhsub", "u", int_arm_neon_vhsubu, 0>;
3426 // VQSUB : Vector Saturing Subtract
3427 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
3428 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3429 "vqsub", "s", int_arm_neon_vqsubs, 0>;
3430 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
3431 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3432 "vqsub", "u", int_arm_neon_vqsubu, 0>;
3433 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
3434 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
3435 int_arm_neon_vsubhn, 0>;
3436 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
3437 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
3438 int_arm_neon_vrsubhn, 0>;
3440 // Vector Comparisons.
3442 // VCEQ : Vector Compare Equal
3443 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3444 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
3445 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
3447 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
3450 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
3451 "$Vd, $Vm, #0", NEONvceqz>;
3453 // VCGE : Vector Compare Greater Than or Equal
3454 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3455 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
3456 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3457 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
3458 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
3460 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
3463 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
3464 "$Vd, $Vm, #0", NEONvcgez>;
3465 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
3466 "$Vd, $Vm, #0", NEONvclez>;
3468 // VCGT : Vector Compare Greater Than
3469 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3470 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
3471 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3472 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
3473 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
3475 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
3478 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
3479 "$Vd, $Vm, #0", NEONvcgtz>;
3480 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
3481 "$Vd, $Vm, #0", NEONvcltz>;
3483 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
3484 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
3485 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
3486 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
3487 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
3488 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
3489 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
3490 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
3491 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
3492 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
3493 // VTST : Vector Test Bits
3494 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
3495 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
3497 // Vector Bitwise Operations.
3499 def vnotd : PatFrag<(ops node:$in),
3500 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
3501 def vnotq : PatFrag<(ops node:$in),
3502 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
3505 // VAND : Vector Bitwise AND
3506 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
3507 v2i32, v2i32, and, 1>;
3508 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
3509 v4i32, v4i32, and, 1>;
3511 // VEOR : Vector Bitwise Exclusive OR
3512 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
3513 v2i32, v2i32, xor, 1>;
3514 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
3515 v4i32, v4i32, xor, 1>;
3517 // VORR : Vector Bitwise OR
3518 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
3519 v2i32, v2i32, or, 1>;
3520 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
3521 v4i32, v4i32, or, 1>;
3523 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
3524 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3526 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3528 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3529 let Inst{9} = SIMM{9};
3532 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
3533 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3535 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3537 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3538 let Inst{10-9} = SIMM{10-9};
3541 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
3542 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3544 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3546 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3547 let Inst{9} = SIMM{9};
3550 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
3551 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3553 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3555 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3556 let Inst{10-9} = SIMM{10-9};
3560 // VBIC : Vector Bitwise Bit Clear (AND NOT)
3561 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
3562 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
3563 "vbic", "$Vd, $Vn, $Vm", "",
3564 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
3565 (vnotd DPR:$Vm))))]>;
3566 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
3567 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
3568 "vbic", "$Vd, $Vn, $Vm", "",
3569 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
3570 (vnotq QPR:$Vm))))]>;
3572 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
3573 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3575 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3577 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3578 let Inst{9} = SIMM{9};
3581 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
3582 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3584 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3586 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3587 let Inst{10-9} = SIMM{10-9};
3590 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
3591 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3593 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3595 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3596 let Inst{9} = SIMM{9};
3599 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
3600 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3602 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3604 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3605 let Inst{10-9} = SIMM{10-9};
3608 // VORN : Vector Bitwise OR NOT
3609 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
3610 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
3611 "vorn", "$Vd, $Vn, $Vm", "",
3612 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
3613 (vnotd DPR:$Vm))))]>;
3614 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
3615 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
3616 "vorn", "$Vd, $Vn, $Vm", "",
3617 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
3618 (vnotq QPR:$Vm))))]>;
3620 // VMVN : Vector Bitwise NOT (Immediate)
3622 let isReMaterializable = 1 in {
3624 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
3625 (ins nModImm:$SIMM), IIC_VMOVImm,
3626 "vmvn", "i16", "$Vd, $SIMM", "",
3627 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
3628 let Inst{9} = SIMM{9};
3631 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
3632 (ins nModImm:$SIMM), IIC_VMOVImm,
3633 "vmvn", "i16", "$Vd, $SIMM", "",
3634 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
3635 let Inst{9} = SIMM{9};
3638 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
3639 (ins nModImm:$SIMM), IIC_VMOVImm,
3640 "vmvn", "i32", "$Vd, $SIMM", "",
3641 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
3642 let Inst{11-8} = SIMM{11-8};
3645 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
3646 (ins nModImm:$SIMM), IIC_VMOVImm,
3647 "vmvn", "i32", "$Vd, $SIMM", "",
3648 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
3649 let Inst{11-8} = SIMM{11-8};
3653 // VMVN : Vector Bitwise NOT
3654 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
3655 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
3656 "vmvn", "$Vd, $Vm", "",
3657 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
3658 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
3659 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
3660 "vmvn", "$Vd, $Vm", "",
3661 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
3662 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
3663 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
3665 // VBSL : Vector Bitwise Select
3666 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
3667 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3668 N3RegFrm, IIC_VCNTiD,
3669 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3671 (v2i32 (or (and DPR:$Vn, DPR:$src1),
3672 (and DPR:$Vm, (vnotd DPR:$src1)))))]>;
3673 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
3674 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3675 N3RegFrm, IIC_VCNTiQ,
3676 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3678 (v4i32 (or (and QPR:$Vn, QPR:$src1),
3679 (and QPR:$Vm, (vnotq QPR:$src1)))))]>;
3681 // VBIF : Vector Bitwise Insert if False
3682 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
3683 // FIXME: This instruction's encoding MAY NOT BE correct.
3684 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
3685 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3686 N3RegFrm, IIC_VBINiD,
3687 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3688 [/* For disassembly only; pattern left blank */]>;
3689 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
3690 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3691 N3RegFrm, IIC_VBINiQ,
3692 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3693 [/* For disassembly only; pattern left blank */]>;
3695 // VBIT : Vector Bitwise Insert if True
3696 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
3697 // FIXME: This instruction's encoding MAY NOT BE correct.
3698 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
3699 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3700 N3RegFrm, IIC_VBINiD,
3701 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3702 [/* For disassembly only; pattern left blank */]>;
3703 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
3704 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3705 N3RegFrm, IIC_VBINiQ,
3706 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3707 [/* For disassembly only; pattern left blank */]>;
3709 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
3710 // for equivalent operations with different register constraints; it just
3713 // Vector Absolute Differences.
3715 // VABD : Vector Absolute Difference
3716 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
3717 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3718 "vabd", "s", int_arm_neon_vabds, 1>;
3719 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
3720 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3721 "vabd", "u", int_arm_neon_vabdu, 1>;
3722 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
3723 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
3724 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
3725 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
3727 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
3728 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
3729 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
3730 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
3731 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
3733 // VABA : Vector Absolute Difference and Accumulate
3734 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3735 "vaba", "s", int_arm_neon_vabds, add>;
3736 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3737 "vaba", "u", int_arm_neon_vabdu, add>;
3739 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
3740 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
3741 "vabal", "s", int_arm_neon_vabds, zext, add>;
3742 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
3743 "vabal", "u", int_arm_neon_vabdu, zext, add>;
3745 // Vector Maximum and Minimum.
3747 // VMAX : Vector Maximum
3748 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
3749 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3750 "vmax", "s", int_arm_neon_vmaxs, 1>;
3751 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
3752 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3753 "vmax", "u", int_arm_neon_vmaxu, 1>;
3754 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
3756 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
3757 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
3759 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
3761 // VMIN : Vector Minimum
3762 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
3763 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3764 "vmin", "s", int_arm_neon_vmins, 1>;
3765 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
3766 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3767 "vmin", "u", int_arm_neon_vminu, 1>;
3768 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
3770 v2f32, v2f32, int_arm_neon_vmins, 1>;
3771 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
3773 v4f32, v4f32, int_arm_neon_vmins, 1>;
3775 // Vector Pairwise Operations.
3777 // VPADD : Vector Pairwise Add
3778 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3780 v8i8, v8i8, int_arm_neon_vpadd, 0>;
3781 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3783 v4i16, v4i16, int_arm_neon_vpadd, 0>;
3784 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3786 v2i32, v2i32, int_arm_neon_vpadd, 0>;
3787 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
3788 IIC_VPBIND, "vpadd", "f32",
3789 v2f32, v2f32, int_arm_neon_vpadd, 0>;
3791 // VPADDL : Vector Pairwise Add Long
3792 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
3793 int_arm_neon_vpaddls>;
3794 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
3795 int_arm_neon_vpaddlu>;
3797 // VPADAL : Vector Pairwise Add and Accumulate Long
3798 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
3799 int_arm_neon_vpadals>;
3800 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
3801 int_arm_neon_vpadalu>;
3803 // VPMAX : Vector Pairwise Maximum
3804 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3805 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
3806 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3807 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
3808 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3809 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
3810 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3811 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
3812 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3813 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
3814 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3815 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
3816 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
3817 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
3819 // VPMIN : Vector Pairwise Minimum
3820 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3821 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
3822 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3823 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
3824 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3825 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
3826 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3827 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
3828 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3829 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
3830 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3831 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
3832 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
3833 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
3835 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
3837 // VRECPE : Vector Reciprocal Estimate
3838 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
3839 IIC_VUNAD, "vrecpe", "u32",
3840 v2i32, v2i32, int_arm_neon_vrecpe>;
3841 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
3842 IIC_VUNAQ, "vrecpe", "u32",
3843 v4i32, v4i32, int_arm_neon_vrecpe>;
3844 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
3845 IIC_VUNAD, "vrecpe", "f32",
3846 v2f32, v2f32, int_arm_neon_vrecpe>;
3847 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
3848 IIC_VUNAQ, "vrecpe", "f32",
3849 v4f32, v4f32, int_arm_neon_vrecpe>;
3851 // VRECPS : Vector Reciprocal Step
3852 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
3853 IIC_VRECSD, "vrecps", "f32",
3854 v2f32, v2f32, int_arm_neon_vrecps, 1>;
3855 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
3856 IIC_VRECSQ, "vrecps", "f32",
3857 v4f32, v4f32, int_arm_neon_vrecps, 1>;
3859 // VRSQRTE : Vector Reciprocal Square Root Estimate
3860 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
3861 IIC_VUNAD, "vrsqrte", "u32",
3862 v2i32, v2i32, int_arm_neon_vrsqrte>;
3863 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
3864 IIC_VUNAQ, "vrsqrte", "u32",
3865 v4i32, v4i32, int_arm_neon_vrsqrte>;
3866 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
3867 IIC_VUNAD, "vrsqrte", "f32",
3868 v2f32, v2f32, int_arm_neon_vrsqrte>;
3869 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
3870 IIC_VUNAQ, "vrsqrte", "f32",
3871 v4f32, v4f32, int_arm_neon_vrsqrte>;
3873 // VRSQRTS : Vector Reciprocal Square Root Step
3874 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
3875 IIC_VRECSD, "vrsqrts", "f32",
3876 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
3877 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
3878 IIC_VRECSQ, "vrsqrts", "f32",
3879 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
3883 // VSHL : Vector Shift
3884 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
3885 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
3886 "vshl", "s", int_arm_neon_vshifts>;
3887 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
3888 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
3889 "vshl", "u", int_arm_neon_vshiftu>;
3890 // VSHL : Vector Shift Left (Immediate)
3891 defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl,
3893 // VSHR : Vector Shift Right (Immediate)
3894 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", NEONvshrs,
3896 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", NEONvshru,
3899 // VSHLL : Vector Shift Left Long
3900 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
3901 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
3903 // VSHLL : Vector Shift Left Long (with maximum shift count)
3904 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
3905 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
3906 ValueType OpTy, SDNode OpNode>
3907 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
3908 ResTy, OpTy, OpNode> {
3909 let Inst{21-16} = op21_16;
3911 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
3912 v8i16, v8i8, NEONvshlli>;
3913 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
3914 v4i32, v4i16, NEONvshlli>;
3915 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
3916 v2i64, v2i32, NEONvshlli>;
3918 // VSHRN : Vector Shift Right and Narrow
3919 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
3922 // VRSHL : Vector Rounding Shift
3923 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
3924 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3925 "vrshl", "s", int_arm_neon_vrshifts>;
3926 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
3927 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3928 "vrshl", "u", int_arm_neon_vrshiftu>;
3929 // VRSHR : Vector Rounding Shift Right
3930 defm VRSHRs : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs,
3932 defm VRSHRu : N2VSh_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", NEONvrshru,
3935 // VRSHRN : Vector Rounding Shift Right and Narrow
3936 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
3939 // VQSHL : Vector Saturating Shift
3940 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
3941 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3942 "vqshl", "s", int_arm_neon_vqshifts>;
3943 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
3944 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3945 "vqshl", "u", int_arm_neon_vqshiftu>;
3946 // VQSHL : Vector Saturating Shift Left (Immediate)
3947 defm VQSHLsi : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls,
3949 defm VQSHLui : N2VSh_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu,
3951 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
3952 defm VQSHLsu : N2VSh_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu,
3955 // VQSHRN : Vector Saturating Shift Right and Narrow
3956 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
3958 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
3961 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
3962 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
3965 // VQRSHL : Vector Saturating Rounding Shift
3966 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
3967 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3968 "vqrshl", "s", int_arm_neon_vqrshifts>;
3969 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
3970 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3971 "vqrshl", "u", int_arm_neon_vqrshiftu>;
3973 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
3974 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
3976 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
3979 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
3980 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
3983 // VSRA : Vector Shift Right and Accumulate
3984 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
3985 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
3986 // VRSRA : Vector Rounding Shift Right and Accumulate
3987 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
3988 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
3990 // VSLI : Vector Shift Left and Insert
3991 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli", NEONvsli, N2RegVShLFrm>;
3992 // VSRI : Vector Shift Right and Insert
3993 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri", NEONvsri, N2RegVShRFrm>;
3995 // Vector Absolute and Saturating Absolute.
3997 // VABS : Vector Absolute Value
3998 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
3999 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
4001 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4002 IIC_VUNAD, "vabs", "f32",
4003 v2f32, v2f32, int_arm_neon_vabs>;
4004 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4005 IIC_VUNAQ, "vabs", "f32",
4006 v4f32, v4f32, int_arm_neon_vabs>;
4008 // VQABS : Vector Saturating Absolute Value
4009 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
4010 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
4011 int_arm_neon_vqabs>;
4015 def vnegd : PatFrag<(ops node:$in),
4016 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
4017 def vnegq : PatFrag<(ops node:$in),
4018 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
4020 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4021 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
4022 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
4023 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
4024 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4025 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
4026 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
4027 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
4029 // VNEG : Vector Negate (integer)
4030 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
4031 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
4032 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
4033 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
4034 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
4035 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
4037 // VNEG : Vector Negate (floating-point)
4038 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
4039 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
4040 "vneg", "f32", "$Vd, $Vm", "",
4041 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
4042 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
4043 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
4044 "vneg", "f32", "$Vd, $Vm", "",
4045 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
4047 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
4048 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
4049 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
4050 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
4051 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
4052 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
4054 // VQNEG : Vector Saturating Negate
4055 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
4056 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
4057 int_arm_neon_vqneg>;
4059 // Vector Bit Counting Operations.
4061 // VCLS : Vector Count Leading Sign Bits
4062 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
4063 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
4065 // VCLZ : Vector Count Leading Zeros
4066 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
4067 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
4069 // VCNT : Vector Count One Bits
4070 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4071 IIC_VCNTiD, "vcnt", "8",
4072 v8i8, v8i8, int_arm_neon_vcnt>;
4073 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4074 IIC_VCNTiQ, "vcnt", "8",
4075 v16i8, v16i8, int_arm_neon_vcnt>;
4077 // Vector Swap -- for disassembly only.
4078 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
4079 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
4080 "vswp", "$Vd, $Vm", "", []>;
4081 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
4082 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
4083 "vswp", "$Vd, $Vm", "", []>;
4085 // Vector Move Operations.
4087 // VMOV : Vector Move (Register)
4089 let neverHasSideEffects = 1 in {
4090 def VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$Vd), (ins DPR:$Vm),
4091 N3RegFrm, IIC_VMOV, "vmov", "$Vd, $Vm", "", []> {
4092 let Vn{4-0} = Vm{4-0};
4094 def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$Vd), (ins QPR:$Vm),
4095 N3RegFrm, IIC_VMOV, "vmov", "$Vd, $Vm", "", []> {
4096 let Vn{4-0} = Vm{4-0};
4099 // Pseudo vector move instructions for QQ and QQQQ registers. This should
4100 // be expanded after register allocation is completed.
4101 def VMOVQQ : PseudoInst<(outs QQPR:$dst), (ins QQPR:$src),
4104 def VMOVQQQQ : PseudoInst<(outs QQQQPR:$dst), (ins QQQQPR:$src),
4106 } // neverHasSideEffects
4108 // VMOV : Vector Move (Immediate)
4110 let isReMaterializable = 1 in {
4111 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
4112 (ins nModImm:$SIMM), IIC_VMOVImm,
4113 "vmov", "i8", "$Vd, $SIMM", "",
4114 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
4115 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
4116 (ins nModImm:$SIMM), IIC_VMOVImm,
4117 "vmov", "i8", "$Vd, $SIMM", "",
4118 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
4120 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
4121 (ins nModImm:$SIMM), IIC_VMOVImm,
4122 "vmov", "i16", "$Vd, $SIMM", "",
4123 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
4124 let Inst{9} = SIMM{9};
4127 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
4128 (ins nModImm:$SIMM), IIC_VMOVImm,
4129 "vmov", "i16", "$Vd, $SIMM", "",
4130 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
4131 let Inst{9} = SIMM{9};
4134 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
4135 (ins nModImm:$SIMM), IIC_VMOVImm,
4136 "vmov", "i32", "$Vd, $SIMM", "",
4137 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
4138 let Inst{11-8} = SIMM{11-8};
4141 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
4142 (ins nModImm:$SIMM), IIC_VMOVImm,
4143 "vmov", "i32", "$Vd, $SIMM", "",
4144 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
4145 let Inst{11-8} = SIMM{11-8};
4148 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
4149 (ins nModImm:$SIMM), IIC_VMOVImm,
4150 "vmov", "i64", "$Vd, $SIMM", "",
4151 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
4152 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
4153 (ins nModImm:$SIMM), IIC_VMOVImm,
4154 "vmov", "i64", "$Vd, $SIMM", "",
4155 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
4156 } // isReMaterializable
4158 // VMOV : Vector Get Lane (move scalar to ARM core register)
4160 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
4161 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4162 IIC_VMOVSI, "vmov", "s8", "$R, $V[$lane]",
4163 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
4165 let Inst{21} = lane{2};
4166 let Inst{6-5} = lane{1-0};
4168 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
4169 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4170 IIC_VMOVSI, "vmov", "s16", "$R, $V[$lane]",
4171 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
4173 let Inst{21} = lane{1};
4174 let Inst{6} = lane{0};
4176 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
4177 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4178 IIC_VMOVSI, "vmov", "u8", "$R, $V[$lane]",
4179 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
4181 let Inst{21} = lane{2};
4182 let Inst{6-5} = lane{1-0};
4184 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
4185 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4186 IIC_VMOVSI, "vmov", "u16", "$R, $V[$lane]",
4187 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
4189 let Inst{21} = lane{1};
4190 let Inst{6} = lane{0};
4192 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
4193 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4194 IIC_VMOVSI, "vmov", "32", "$R, $V[$lane]",
4195 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
4197 let Inst{21} = lane{0};
4199 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
4200 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
4201 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4202 (DSubReg_i8_reg imm:$lane))),
4203 (SubReg_i8_lane imm:$lane))>;
4204 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
4205 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4206 (DSubReg_i16_reg imm:$lane))),
4207 (SubReg_i16_lane imm:$lane))>;
4208 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
4209 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4210 (DSubReg_i8_reg imm:$lane))),
4211 (SubReg_i8_lane imm:$lane))>;
4212 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
4213 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4214 (DSubReg_i16_reg imm:$lane))),
4215 (SubReg_i16_lane imm:$lane))>;
4216 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
4217 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
4218 (DSubReg_i32_reg imm:$lane))),
4219 (SubReg_i32_lane imm:$lane))>;
4220 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
4221 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
4222 (SSubReg_f32_reg imm:$src2))>;
4223 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
4224 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
4225 (SSubReg_f32_reg imm:$src2))>;
4226 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
4227 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4228 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
4229 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4232 // VMOV : Vector Set Lane (move ARM core register to scalar)
4234 let Constraints = "$src1 = $V" in {
4235 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
4236 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4237 IIC_VMOVISL, "vmov", "8", "$V[$lane], $R",
4238 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
4239 GPR:$R, imm:$lane))]> {
4240 let Inst{21} = lane{2};
4241 let Inst{6-5} = lane{1-0};
4243 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
4244 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4245 IIC_VMOVISL, "vmov", "16", "$V[$lane], $R",
4246 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
4247 GPR:$R, imm:$lane))]> {
4248 let Inst{21} = lane{1};
4249 let Inst{6} = lane{0};
4251 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
4252 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4253 IIC_VMOVISL, "vmov", "32", "$V[$lane], $R",
4254 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
4255 GPR:$R, imm:$lane))]> {
4256 let Inst{21} = lane{0};
4259 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
4260 (v16i8 (INSERT_SUBREG QPR:$src1,
4261 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
4262 (DSubReg_i8_reg imm:$lane))),
4263 GPR:$src2, (SubReg_i8_lane imm:$lane))),
4264 (DSubReg_i8_reg imm:$lane)))>;
4265 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
4266 (v8i16 (INSERT_SUBREG QPR:$src1,
4267 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
4268 (DSubReg_i16_reg imm:$lane))),
4269 GPR:$src2, (SubReg_i16_lane imm:$lane))),
4270 (DSubReg_i16_reg imm:$lane)))>;
4271 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
4272 (v4i32 (INSERT_SUBREG QPR:$src1,
4273 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
4274 (DSubReg_i32_reg imm:$lane))),
4275 GPR:$src2, (SubReg_i32_lane imm:$lane))),
4276 (DSubReg_i32_reg imm:$lane)))>;
4278 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
4279 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
4280 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4281 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
4282 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
4283 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4285 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4286 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4287 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4288 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4290 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
4291 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4292 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
4293 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
4294 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
4295 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4297 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
4298 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4299 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
4300 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4301 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
4302 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4304 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
4305 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4306 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4308 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
4309 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
4310 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4312 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
4313 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4314 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4317 // VDUP : Vector Duplicate (from ARM core register to all elements)
4319 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4320 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
4321 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4322 [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4323 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4324 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
4325 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4326 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4328 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
4329 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
4330 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
4331 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
4332 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
4333 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
4335 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$V), (ins GPR:$R),
4336 IIC_VMOVIS, "vdup", "32", "$V, $R",
4337 [(set DPR:$V, (v2f32 (NEONvdup
4338 (f32 (bitconvert GPR:$R)))))]>;
4339 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$V), (ins GPR:$R),
4340 IIC_VMOVIS, "vdup", "32", "$V, $R",
4341 [(set QPR:$V, (v4f32 (NEONvdup
4342 (f32 (bitconvert GPR:$R)))))]>;
4344 // VDUP : Vector Duplicate Lane (from scalar to all elements)
4346 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
4348 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, nohash_imm:$lane),
4349 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm[$lane]",
4350 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
4352 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
4353 ValueType ResTy, ValueType OpTy>
4354 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, nohash_imm:$lane),
4355 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm[$lane]",
4356 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
4359 // Inst{19-16} is partially specified depending on the element size.
4361 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8> {
4362 let Inst{19-17} = lane{2-0};
4364 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16> {
4365 let Inst{19-18} = lane{1-0};
4367 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32> {
4368 let Inst{19} = lane{0};
4370 def VDUPLNfd : VDUPLND<{?,1,0,0}, "vdup", "32", v2f32> {
4371 let Inst{19} = lane{0};
4373 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8> {
4374 let Inst{19-17} = lane{2-0};
4376 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16> {
4377 let Inst{19-18} = lane{1-0};
4379 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32> {
4380 let Inst{19} = lane{0};
4382 def VDUPLNfq : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4f32, v2f32> {
4383 let Inst{19} = lane{0};
4386 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
4387 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
4388 (DSubReg_i8_reg imm:$lane))),
4389 (SubReg_i8_lane imm:$lane)))>;
4390 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
4391 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
4392 (DSubReg_i16_reg imm:$lane))),
4393 (SubReg_i16_lane imm:$lane)))>;
4394 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
4395 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
4396 (DSubReg_i32_reg imm:$lane))),
4397 (SubReg_i32_lane imm:$lane)))>;
4398 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
4399 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
4400 (DSubReg_i32_reg imm:$lane))),
4401 (SubReg_i32_lane imm:$lane)))>;
4403 def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4404 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
4405 def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4406 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
4408 // VMOVN : Vector Narrowing Move
4409 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
4410 "vmovn", "i", trunc>;
4411 // VQMOVN : Vector Saturating Narrowing Move
4412 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
4413 "vqmovn", "s", int_arm_neon_vqmovns>;
4414 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
4415 "vqmovn", "u", int_arm_neon_vqmovnu>;
4416 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
4417 "vqmovun", "s", int_arm_neon_vqmovnsu>;
4418 // VMOVL : Vector Lengthening Move
4419 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
4420 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
4422 // Vector Conversions.
4424 // VCVT : Vector Convert Between Floating-Point and Integers
4425 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4426 v2i32, v2f32, fp_to_sint>;
4427 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4428 v2i32, v2f32, fp_to_uint>;
4429 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4430 v2f32, v2i32, sint_to_fp>;
4431 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4432 v2f32, v2i32, uint_to_fp>;
4434 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4435 v4i32, v4f32, fp_to_sint>;
4436 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4437 v4i32, v4f32, fp_to_uint>;
4438 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4439 v4f32, v4i32, sint_to_fp>;
4440 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4441 v4f32, v4i32, uint_to_fp>;
4443 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
4444 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4445 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
4446 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4447 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
4448 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4449 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
4450 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4451 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
4453 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4454 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
4455 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4456 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
4457 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4458 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
4459 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4460 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
4464 // VREV64 : Vector Reverse elements within 64-bit doublewords
4466 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4467 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
4468 (ins DPR:$Vm), IIC_VMOVD,
4469 OpcodeStr, Dt, "$Vd, $Vm", "",
4470 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
4471 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4472 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
4473 (ins QPR:$Vm), IIC_VMOVQ,
4474 OpcodeStr, Dt, "$Vd, $Vm", "",
4475 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
4477 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
4478 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
4479 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
4480 def VREV64df : VREV64D<0b10, "vrev64", "32", v2f32>;
4482 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
4483 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
4484 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
4485 def VREV64qf : VREV64Q<0b10, "vrev64", "32", v4f32>;
4487 // VREV32 : Vector Reverse elements within 32-bit words
4489 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4490 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
4491 (ins DPR:$Vm), IIC_VMOVD,
4492 OpcodeStr, Dt, "$Vd, $Vm", "",
4493 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
4494 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4495 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
4496 (ins QPR:$Vm), IIC_VMOVQ,
4497 OpcodeStr, Dt, "$Vd, $Vm", "",
4498 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
4500 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
4501 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
4503 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
4504 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
4506 // VREV16 : Vector Reverse elements within 16-bit halfwords
4508 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4509 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
4510 (ins DPR:$Vm), IIC_VMOVD,
4511 OpcodeStr, Dt, "$Vd, $Vm", "",
4512 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
4513 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4514 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
4515 (ins QPR:$Vm), IIC_VMOVQ,
4516 OpcodeStr, Dt, "$Vd, $Vm", "",
4517 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
4519 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
4520 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
4522 // Other Vector Shuffles.
4524 // VEXT : Vector Extract
4526 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
4527 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
4528 (ins DPR:$Vn, DPR:$Vm, i32imm:$index), NVExtFrm,
4529 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4530 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
4531 (Ty DPR:$Vm), imm:$index)))]> {
4533 let Inst{11-8} = index{3-0};
4536 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
4537 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
4538 (ins QPR:$Vn, QPR:$Vm, i32imm:$index), NVExtFrm,
4539 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4540 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
4541 (Ty QPR:$Vm), imm:$index)))]> {
4543 let Inst{11-8} = index{3-0};
4546 def VEXTd8 : VEXTd<"vext", "8", v8i8> {
4547 let Inst{11-8} = index{3-0};
4549 def VEXTd16 : VEXTd<"vext", "16", v4i16> {
4550 let Inst{11-9} = index{2-0};
4553 def VEXTd32 : VEXTd<"vext", "32", v2i32> {
4554 let Inst{11-10} = index{1-0};
4555 let Inst{9-8} = 0b00;
4557 def VEXTdf : VEXTd<"vext", "32", v2f32> {
4558 let Inst{11} = index{0};
4559 let Inst{10-8} = 0b000;
4562 def VEXTq8 : VEXTq<"vext", "8", v16i8> {
4563 let Inst{11-8} = index{3-0};
4565 def VEXTq16 : VEXTq<"vext", "16", v8i16> {
4566 let Inst{11-9} = index{2-0};
4569 def VEXTq32 : VEXTq<"vext", "32", v4i32> {
4570 let Inst{11-10} = index{1-0};
4571 let Inst{9-8} = 0b00;
4573 def VEXTqf : VEXTq<"vext", "32", v4f32> {
4574 let Inst{11} = index{0};
4575 let Inst{10-8} = 0b000;
4578 // VTRN : Vector Transpose
4580 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
4581 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
4582 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
4584 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
4585 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
4586 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
4588 // VUZP : Vector Unzip (Deinterleave)
4590 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
4591 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
4592 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
4594 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
4595 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
4596 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
4598 // VZIP : Vector Zip (Interleave)
4600 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
4601 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
4602 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
4604 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
4605 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
4606 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
4608 // Vector Table Lookup and Table Extension.
4610 // VTBL : Vector Table Lookup
4612 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
4613 (ins DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
4614 "vtbl", "8", "$Vd, \\{$Vn\\}, $Vm", "",
4615 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 DPR:$Vn, DPR:$Vm)))]>;
4616 let hasExtraSrcRegAllocReq = 1 in {
4618 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
4619 (ins DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTB2,
4620 "vtbl", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "", []>;
4622 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
4623 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm), NVTBLFrm, IIC_VTB3,
4624 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm", "", []>;
4626 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
4627 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm),
4629 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm", "", []>;
4630 } // hasExtraSrcRegAllocReq = 1
4633 : PseudoNeonI<(outs DPR:$dst), (ins QPR:$tbl, DPR:$src), IIC_VTB2, "", []>;
4635 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
4637 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
4639 // VTBX : Vector Table Extension
4641 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
4642 (ins DPR:$orig, DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
4643 "vtbx", "8", "$Vd, \\{$Vn\\}, $Vm", "$orig = $Vd",
4644 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
4645 DPR:$orig, DPR:$Vn, DPR:$Vm)))]>;
4646 let hasExtraSrcRegAllocReq = 1 in {
4648 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
4649 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
4650 "vtbx", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "$orig = $Vd", []>;
4652 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
4653 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm),
4654 NVTBLFrm, IIC_VTBX3,
4655 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm",
4658 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd), (ins DPR:$orig, DPR:$Vn,
4659 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
4660 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm",
4662 } // hasExtraSrcRegAllocReq = 1
4665 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QPR:$tbl, DPR:$src),
4666 IIC_VTBX2, "$orig = $dst", []>;
4668 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4669 IIC_VTBX3, "$orig = $dst", []>;
4671 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4672 IIC_VTBX4, "$orig = $dst", []>;
4674 //===----------------------------------------------------------------------===//
4675 // NEON instructions for single-precision FP math
4676 //===----------------------------------------------------------------------===//
4678 class N2VSPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
4679 : NEONFPPat<(ResTy (OpNode SPR:$a)),
4681 (OpTy (COPY_TO_REGCLASS
4682 (OpTy (Inst (INSERT_SUBREG
4683 (OpTy (COPY_TO_REGCLASS (OpTy (IMPLICIT_DEF)), DPR_VFP2)),
4685 DPR_VFP2)), ssub_0)>;
4687 class N3VSPat<SDNode OpNode, NeonI Inst>
4688 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
4689 (EXTRACT_SUBREG (v2f32
4690 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
4692 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
4696 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
4697 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
4698 (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
4700 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
4702 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
4706 // These need separate instructions because they must use DPR_VFP2 register
4707 // class which have SPR sub-registers.
4709 // Vector Add Operations used for single-precision FP
4710 let neverHasSideEffects = 1 in
4711 def VADDfd_sfp : N3VS<0,0,0b00,0b1101,0, "vadd", "f32">;
4712 def : N3VSPat<fadd, VADDfd_sfp>;
4714 // Vector Sub Operations used for single-precision FP
4715 let neverHasSideEffects = 1 in
4716 def VSUBfd_sfp : N3VS<0,0,0b10,0b1101,0, "vsub", "f32">;
4717 def : N3VSPat<fsub, VSUBfd_sfp>;
4719 // Vector Multiply Operations used for single-precision FP
4720 let neverHasSideEffects = 1 in
4721 def VMULfd_sfp : N3VS<1,0,0b00,0b1101,1, "vmul", "f32">;
4722 def : N3VSPat<fmul, VMULfd_sfp>;
4724 // Vector Multiply-Accumulate/Subtract used for single-precision FP
4725 // vml[as].f32 can cause 4-8 cycle stalls in following ASIMD instructions, so
4726 // we want to avoid them for now. e.g., alternating vmla/vadd instructions.
4728 let neverHasSideEffects = 1 in
4729 def VMLAfd_sfp : N3VSMulOp<0,0,0b00,0b1101,1, IIC_VMACD, "vmla", "f32">;
4730 def : N3VSMulOpPat<fmul, fadd, VMLAfd_sfp>,
4731 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
4733 let neverHasSideEffects = 1 in
4734 def VMLSfd_sfp : N3VSMulOp<0,0,0b10,0b1101,1, IIC_VMACD, "vmls", "f32">;
4735 def : N3VSMulOpPat<fmul, fsub, VMLSfd_sfp>,
4736 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
4738 // Vector Absolute used for single-precision FP
4739 def : N2VSPat<fabs, f32, v2f32, VABSfd>;
4741 // Vector Negate used for single-precision FP
4742 def : N2VSPat<fneg, f32, v2f32, VNEGfd>;
4744 // Vector Maximum used for single-precision FP
4745 let neverHasSideEffects = 1 in
4746 def VMAXfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$Vd),
4747 (ins DPR_VFP2:$Vn, DPR_VFP2:$Vm), N3RegFrm, IIC_VBIND,
4748 "vmax", "f32", "$Vd, $Vn, $Vm", "", []>;
4749 def : N3VSPat<NEONfmax, VMAXfd_sfp>;
4751 // Vector Minimum used for single-precision FP
4752 let neverHasSideEffects = 1 in
4753 def VMINfd_sfp : N3V<0, 0, 0b10, 0b1111, 0, 0, (outs DPR_VFP2:$Vd),
4754 (ins DPR_VFP2:$Vn, DPR_VFP2:$Vm), N3RegFrm, IIC_VBIND,
4755 "vmin", "f32", "$Vd, $Vn, $Vm", "", []>;
4756 def : N3VSPat<NEONfmin, VMINfd_sfp>;
4758 // Vector Convert between single-precision FP and integer
4759 def : N2VSPat<arm_ftosi, f32, v2f32, VCVTf2sd>;
4760 def : N2VSPat<arm_ftoui, f32, v2f32, VCVTf2ud>;
4761 def : N2VSPat<arm_sitof, f32, v2i32, VCVTs2fd>;
4762 def : N2VSPat<arm_uitof, f32, v2i32, VCVTu2fd>;
4764 //===----------------------------------------------------------------------===//
4765 // Non-Instruction Patterns
4766 //===----------------------------------------------------------------------===//
4769 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
4770 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
4771 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
4772 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
4773 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
4774 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
4775 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
4776 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
4777 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
4778 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
4779 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
4780 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
4781 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
4782 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
4783 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
4784 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
4785 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
4786 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
4787 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
4788 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
4789 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
4790 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
4791 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
4792 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
4793 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
4794 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
4795 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
4796 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
4797 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
4798 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
4800 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
4801 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
4802 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
4803 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
4804 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
4805 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
4806 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
4807 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
4808 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
4809 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
4810 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
4811 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
4812 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
4813 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
4814 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
4815 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
4816 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
4817 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
4818 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
4819 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
4820 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
4821 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
4822 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
4823 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
4824 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
4825 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
4826 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
4827 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
4828 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
4829 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;