1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
70 // VDUPLANE can produce a quad-register result from a double-register source,
71 // so the result is not constrained to match the source.
72 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
73 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
76 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
77 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
78 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
80 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
81 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
82 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
83 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
85 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
86 SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>]>;
87 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
88 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
89 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
91 //===----------------------------------------------------------------------===//
92 // NEON operand definitions
93 //===----------------------------------------------------------------------===//
95 // addrmode_neonldstm := reg
97 /* TODO: Take advantage of vldm.
98 def addrmode_neonldstm : Operand<i32>,
99 ComplexPattern<i32, 2, "SelectAddrModeNeonLdStM", []> {
100 let PrintMethod = "printAddrNeonLdStMOperand";
101 let MIOperandInfo = (ops GPR, i32imm);
105 def h8imm : Operand<i8> {
106 let PrintMethod = "printHex8ImmOperand";
108 def h16imm : Operand<i16> {
109 let PrintMethod = "printHex16ImmOperand";
111 def h32imm : Operand<i32> {
112 let PrintMethod = "printHex32ImmOperand";
114 def h64imm : Operand<i64> {
115 let PrintMethod = "printHex64ImmOperand";
118 //===----------------------------------------------------------------------===//
119 // NEON load / store instructions
120 //===----------------------------------------------------------------------===//
122 /* TODO: Take advantage of vldm.
123 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
124 def VLDMD : NI<(outs),
125 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
127 "vldm${addr:submode} ${addr:base}, $dst1",
129 let Inst{27-25} = 0b110;
131 let Inst{11-9} = 0b101;
134 def VLDMS : NI<(outs),
135 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
137 "vldm${addr:submode} ${addr:base}, $dst1",
139 let Inst{27-25} = 0b110;
141 let Inst{11-9} = 0b101;
146 // Use vldmia to load a Q register as a D register pair.
147 def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr),
149 "vldmia $addr, ${dst:dregpair}",
150 [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]> {
151 let Inst{27-25} = 0b110;
152 let Inst{24} = 0; // P bit
153 let Inst{23} = 1; // U bit
155 let Inst{11-9} = 0b101;
158 // Use vstmia to store a Q register as a D register pair.
159 def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr),
161 "vstmia $addr, ${src:dregpair}",
162 [(store (v2f64 QPR:$src), addrmode4:$addr)]> {
163 let Inst{27-25} = 0b110;
164 let Inst{24} = 0; // P bit
165 let Inst{23} = 1; // U bit
167 let Inst{11-9} = 0b101;
170 // VLD1 : Vector Load (multiple single elements)
171 class VLD1D<bits<4> op7_4, string OpcodeStr, ValueType Ty, Intrinsic IntOp>
172 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst), (ins addrmode6:$addr), IIC_VLD1,
173 !strconcat(OpcodeStr, "\t\\{$dst\\}, $addr"), "",
174 [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
175 class VLD1Q<bits<4> op7_4, string OpcodeStr, ValueType Ty, Intrinsic IntOp>
176 : NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst), (ins addrmode6:$addr), IIC_VLD1,
177 !strconcat(OpcodeStr, "\t${dst:dregpair}, $addr"), "",
178 [(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
180 def VLD1d8 : VLD1D<0b0000, "vld1.8", v8i8, int_arm_neon_vld1>;
181 def VLD1d16 : VLD1D<0b0100, "vld1.16", v4i16, int_arm_neon_vld1>;
182 def VLD1d32 : VLD1D<0b1000, "vld1.32", v2i32, int_arm_neon_vld1>;
183 def VLD1df : VLD1D<0b1000, "vld1.32", v2f32, int_arm_neon_vld1>;
184 def VLD1d64 : VLD1D<0b1100, "vld1.64", v1i64, int_arm_neon_vld1>;
186 def VLD1q8 : VLD1Q<0b0000, "vld1.8", v16i8, int_arm_neon_vld1>;
187 def VLD1q16 : VLD1Q<0b0100, "vld1.16", v8i16, int_arm_neon_vld1>;
188 def VLD1q32 : VLD1Q<0b1000, "vld1.32", v4i32, int_arm_neon_vld1>;
189 def VLD1qf : VLD1Q<0b1000, "vld1.32", v4f32, int_arm_neon_vld1>;
190 def VLD1q64 : VLD1Q<0b1100, "vld1.64", v2i64, int_arm_neon_vld1>;
192 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
194 // VLD2 : Vector Load (multiple 2-element structures)
195 class VLD2D<bits<4> op7_4, string OpcodeStr>
196 : NLdSt<0,0b10,0b1000,op7_4, (outs DPR:$dst1, DPR:$dst2),
197 (ins addrmode6:$addr), IIC_VLD2,
198 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2\\}, $addr"), "", []>;
199 class VLD2Q<bits<4> op7_4, string OpcodeStr>
200 : NLdSt<0,0b10,0b0011,op7_4,
201 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
202 (ins addrmode6:$addr), IIC_VLD2,
203 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"),
206 def VLD2d8 : VLD2D<0b0000, "vld2.8">;
207 def VLD2d16 : VLD2D<0b0100, "vld2.16">;
208 def VLD2d32 : VLD2D<0b1000, "vld2.32">;
209 def VLD2d64 : NLdSt<0,0b10,0b1010,0b1100, (outs DPR:$dst1, DPR:$dst2),
210 (ins addrmode6:$addr), IIC_VLD1,
211 "vld1.64\t\\{$dst1,$dst2\\}, $addr", "", []>;
213 def VLD2q8 : VLD2Q<0b0000, "vld2.8">;
214 def VLD2q16 : VLD2Q<0b0100, "vld2.16">;
215 def VLD2q32 : VLD2Q<0b1000, "vld2.32">;
217 // VLD3 : Vector Load (multiple 3-element structures)
218 class VLD3D<bits<4> op7_4, string OpcodeStr>
219 : NLdSt<0,0b10,0b0100,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
220 (ins addrmode6:$addr), IIC_VLD3,
221 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"), "", []>;
222 class VLD3WB<bits<4> op7_4, string OpcodeStr>
223 : NLdSt<0,0b10,0b0101,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
224 (ins addrmode6:$addr), IIC_VLD3,
225 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"),
226 "$addr.addr = $wb", []>;
228 def VLD3d8 : VLD3D<0b0000, "vld3.8">;
229 def VLD3d16 : VLD3D<0b0100, "vld3.16">;
230 def VLD3d32 : VLD3D<0b1000, "vld3.32">;
231 def VLD3d64 : NLdSt<0,0b10,0b0110,0b1100,
232 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
233 (ins addrmode6:$addr), IIC_VLD1,
234 "vld1.64\t\\{$dst1,$dst2,$dst3\\}, $addr", "", []>;
236 // vld3 to double-spaced even registers.
237 def VLD3q8a : VLD3WB<0b0000, "vld3.8">;
238 def VLD3q16a : VLD3WB<0b0100, "vld3.16">;
239 def VLD3q32a : VLD3WB<0b1000, "vld3.32">;
241 // vld3 to double-spaced odd registers.
242 def VLD3q8b : VLD3WB<0b0000, "vld3.8">;
243 def VLD3q16b : VLD3WB<0b0100, "vld3.16">;
244 def VLD3q32b : VLD3WB<0b1000, "vld3.32">;
246 // VLD4 : Vector Load (multiple 4-element structures)
247 class VLD4D<bits<4> op7_4, string OpcodeStr>
248 : NLdSt<0,0b10,0b0000,op7_4,
249 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
250 (ins addrmode6:$addr), IIC_VLD4,
251 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"),
253 class VLD4WB<bits<4> op7_4, string OpcodeStr>
254 : NLdSt<0,0b10,0b0001,op7_4,
255 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
256 (ins addrmode6:$addr), IIC_VLD4,
257 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"),
258 "$addr.addr = $wb", []>;
260 def VLD4d8 : VLD4D<0b0000, "vld4.8">;
261 def VLD4d16 : VLD4D<0b0100, "vld4.16">;
262 def VLD4d32 : VLD4D<0b1000, "vld4.32">;
263 def VLD4d64 : NLdSt<0,0b10,0b0010,0b1100,
264 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
265 (ins addrmode6:$addr), IIC_VLD1,
266 "vld1.64\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr", "", []>;
268 // vld4 to double-spaced even registers.
269 def VLD4q8a : VLD4WB<0b0000, "vld4.8">;
270 def VLD4q16a : VLD4WB<0b0100, "vld4.16">;
271 def VLD4q32a : VLD4WB<0b1000, "vld4.32">;
273 // vld4 to double-spaced odd registers.
274 def VLD4q8b : VLD4WB<0b0000, "vld4.8">;
275 def VLD4q16b : VLD4WB<0b0100, "vld4.16">;
276 def VLD4q32b : VLD4WB<0b1000, "vld4.32">;
278 // VLD1LN : Vector Load (single element to one lane)
279 // FIXME: Not yet implemented.
281 // VLD2LN : Vector Load (single 2-element structure to one lane)
282 class VLD2LN<bits<4> op11_8, string OpcodeStr>
283 : NLdSt<1,0b10,op11_8,0b0000, (outs DPR:$dst1, DPR:$dst2),
284 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
286 !strconcat(OpcodeStr, "\t\\{$dst1[$lane],$dst2[$lane]\\}, $addr"),
287 "$src1 = $dst1, $src2 = $dst2", []>;
289 def VLD2LNd8 : VLD2LN<0b0001, "vld2.8">;
290 def VLD2LNd16 : VLD2LN<0b0101, "vld2.16">;
291 def VLD2LNd32 : VLD2LN<0b1001, "vld2.32">;
293 // vld2 to double-spaced even registers.
294 def VLD2LNq16a: VLD2LN<0b0101, "vld2.16">;
295 def VLD2LNq32a: VLD2LN<0b1001, "vld2.32">;
297 // vld2 to double-spaced odd registers.
298 def VLD2LNq16b: VLD2LN<0b0101, "vld2.16">;
299 def VLD2LNq32b: VLD2LN<0b1001, "vld2.32">;
301 // VLD3LN : Vector Load (single 3-element structure to one lane)
302 class VLD3LN<bits<4> op11_8, string OpcodeStr>
303 : NLdSt<1,0b10,op11_8,0b0000, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
304 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
305 nohash_imm:$lane), IIC_VLD3,
306 !strconcat(OpcodeStr,
307 "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane]\\}, $addr"),
308 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
310 def VLD3LNd8 : VLD3LN<0b0010, "vld3.8">;
311 def VLD3LNd16 : VLD3LN<0b0110, "vld3.16">;
312 def VLD3LNd32 : VLD3LN<0b1010, "vld3.32">;
314 // vld3 to double-spaced even registers.
315 def VLD3LNq16a: VLD3LN<0b0110, "vld3.16">;
316 def VLD3LNq32a: VLD3LN<0b1010, "vld3.32">;
318 // vld3 to double-spaced odd registers.
319 def VLD3LNq16b: VLD3LN<0b0110, "vld3.16">;
320 def VLD3LNq32b: VLD3LN<0b1010, "vld3.32">;
322 // VLD4LN : Vector Load (single 4-element structure to one lane)
323 class VLD4LN<bits<4> op11_8, string OpcodeStr>
324 : NLdSt<1,0b10,op11_8,0b0000,
325 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
326 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
327 nohash_imm:$lane), IIC_VLD4,
328 !strconcat(OpcodeStr,
329 "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane],$dst4[$lane]\\}, $addr"),
330 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
332 def VLD4LNd8 : VLD4LN<0b0011, "vld4.8">;
333 def VLD4LNd16 : VLD4LN<0b0111, "vld4.16">;
334 def VLD4LNd32 : VLD4LN<0b1011, "vld4.32">;
336 // vld4 to double-spaced even registers.
337 def VLD4LNq16a: VLD4LN<0b0111, "vld4.16">;
338 def VLD4LNq32a: VLD4LN<0b1011, "vld4.32">;
340 // vld4 to double-spaced odd registers.
341 def VLD4LNq16b: VLD4LN<0b0111, "vld4.16">;
342 def VLD4LNq32b: VLD4LN<0b1011, "vld4.32">;
344 // VLD1DUP : Vector Load (single element to all lanes)
345 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
346 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
347 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
348 // FIXME: Not yet implemented.
349 } // mayLoad = 1, hasExtraDefRegAllocReq = 1
351 // VST1 : Vector Store (multiple single elements)
352 class VST1D<bits<4> op7_4, string OpcodeStr, ValueType Ty, Intrinsic IntOp>
353 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src), IIC_VST,
354 !strconcat(OpcodeStr, "\t\\{$src\\}, $addr"), "",
355 [(IntOp addrmode6:$addr, (Ty DPR:$src))]>;
356 class VST1Q<bits<4> op7_4, string OpcodeStr, ValueType Ty, Intrinsic IntOp>
357 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$addr, QPR:$src), IIC_VST,
358 !strconcat(OpcodeStr, "\t${src:dregpair}, $addr"), "",
359 [(IntOp addrmode6:$addr, (Ty QPR:$src))]>;
361 let hasExtraSrcRegAllocReq = 1 in {
362 def VST1d8 : VST1D<0b0000, "vst1.8", v8i8, int_arm_neon_vst1>;
363 def VST1d16 : VST1D<0b0100, "vst1.16", v4i16, int_arm_neon_vst1>;
364 def VST1d32 : VST1D<0b1000, "vst1.32", v2i32, int_arm_neon_vst1>;
365 def VST1df : VST1D<0b1000, "vst1.32", v2f32, int_arm_neon_vst1>;
366 def VST1d64 : VST1D<0b1100, "vst1.64", v1i64, int_arm_neon_vst1>;
368 def VST1q8 : VST1Q<0b0000, "vst1.8", v16i8, int_arm_neon_vst1>;
369 def VST1q16 : VST1Q<0b0100, "vst1.16", v8i16, int_arm_neon_vst1>;
370 def VST1q32 : VST1Q<0b1000, "vst1.32", v4i32, int_arm_neon_vst1>;
371 def VST1qf : VST1Q<0b1000, "vst1.32", v4f32, int_arm_neon_vst1>;
372 def VST1q64 : VST1Q<0b1100, "vst1.64", v2i64, int_arm_neon_vst1>;
373 } // hasExtraSrcRegAllocReq
375 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
377 // VST2 : Vector Store (multiple 2-element structures)
378 class VST2D<bits<4> op7_4, string OpcodeStr>
379 : NLdSt<0,0b00,0b1000,op7_4, (outs),
380 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
381 !strconcat(OpcodeStr, "\t\\{$src1,$src2\\}, $addr"), "", []>;
382 class VST2Q<bits<4> op7_4, string OpcodeStr>
383 : NLdSt<0,0b00,0b0011,op7_4, (outs),
384 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
386 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"),
389 def VST2d8 : VST2D<0b0000, "vst2.8">;
390 def VST2d16 : VST2D<0b0100, "vst2.16">;
391 def VST2d32 : VST2D<0b1000, "vst2.32">;
392 def VST2d64 : NLdSt<0,0b00,0b1010,0b1100, (outs),
393 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
394 "vst1.64\t\\{$src1,$src2\\}, $addr", "", []>;
396 def VST2q8 : VST2Q<0b0000, "vst2.8">;
397 def VST2q16 : VST2Q<0b0100, "vst2.16">;
398 def VST2q32 : VST2Q<0b1000, "vst2.32">;
400 // VST3 : Vector Store (multiple 3-element structures)
401 class VST3D<bits<4> op7_4, string OpcodeStr>
402 : NLdSt<0,0b00,0b0100,op7_4, (outs),
403 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
404 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"), "", []>;
405 class VST3WB<bits<4> op7_4, string OpcodeStr>
406 : NLdSt<0,0b00,0b0101,op7_4, (outs GPR:$wb),
407 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
408 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"),
409 "$addr.addr = $wb", []>;
411 def VST3d8 : VST3D<0b0000, "vst3.8">;
412 def VST3d16 : VST3D<0b0100, "vst3.16">;
413 def VST3d32 : VST3D<0b1000, "vst3.32">;
414 def VST3d64 : NLdSt<0,0b00,0b0110,0b1100, (outs),
415 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
417 "vst1.64\t\\{$src1,$src2,$src3\\}, $addr", "", []>;
419 // vst3 to double-spaced even registers.
420 def VST3q8a : VST3WB<0b0000, "vst3.8">;
421 def VST3q16a : VST3WB<0b0100, "vst3.16">;
422 def VST3q32a : VST3WB<0b1000, "vst3.32">;
424 // vst3 to double-spaced odd registers.
425 def VST3q8b : VST3WB<0b0000, "vst3.8">;
426 def VST3q16b : VST3WB<0b0100, "vst3.16">;
427 def VST3q32b : VST3WB<0b1000, "vst3.32">;
429 // VST4 : Vector Store (multiple 4-element structures)
430 class VST4D<bits<4> op7_4, string OpcodeStr>
431 : NLdSt<0,0b00,0b0000,op7_4, (outs),
432 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
434 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"),
436 class VST4WB<bits<4> op7_4, string OpcodeStr>
437 : NLdSt<0,0b00,0b0001,op7_4, (outs GPR:$wb),
438 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
440 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"),
441 "$addr.addr = $wb", []>;
443 def VST4d8 : VST4D<0b0000, "vst4.8">;
444 def VST4d16 : VST4D<0b0100, "vst4.16">;
445 def VST4d32 : VST4D<0b1000, "vst4.32">;
446 def VST4d64 : NLdSt<0,0b00,0b0010,0b1100, (outs),
447 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
449 "vst1.64\t\\{$src1,$src2,$src3,$src4\\}, $addr", "", []>;
451 // vst4 to double-spaced even registers.
452 def VST4q8a : VST4WB<0b0000, "vst4.8">;
453 def VST4q16a : VST4WB<0b0100, "vst4.16">;
454 def VST4q32a : VST4WB<0b1000, "vst4.32">;
456 // vst4 to double-spaced odd registers.
457 def VST4q8b : VST4WB<0b0000, "vst4.8">;
458 def VST4q16b : VST4WB<0b0100, "vst4.16">;
459 def VST4q32b : VST4WB<0b1000, "vst4.32">;
461 // VST1LN : Vector Store (single element from one lane)
462 // FIXME: Not yet implemented.
464 // VST2LN : Vector Store (single 2-element structure from one lane)
465 class VST2LN<bits<4> op11_8, string OpcodeStr>
466 : NLdSt<1,0b00,op11_8,0b0000, (outs),
467 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
469 !strconcat(OpcodeStr, "\t\\{$src1[$lane],$src2[$lane]\\}, $addr"),
472 def VST2LNd8 : VST2LN<0b0001, "vst2.8">;
473 def VST2LNd16 : VST2LN<0b0101, "vst2.16">;
474 def VST2LNd32 : VST2LN<0b1001, "vst2.32">;
476 // vst2 to double-spaced even registers.
477 def VST2LNq16a: VST2LN<0b0101, "vst2.16">;
478 def VST2LNq32a: VST2LN<0b1001, "vst2.32">;
480 // vst2 to double-spaced odd registers.
481 def VST2LNq16b: VST2LN<0b0101, "vst2.16">;
482 def VST2LNq32b: VST2LN<0b1001, "vst2.32">;
484 // VST3LN : Vector Store (single 3-element structure from one lane)
485 class VST3LN<bits<4> op11_8, string OpcodeStr>
486 : NLdSt<1,0b00,op11_8,0b0000, (outs),
487 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
488 nohash_imm:$lane), IIC_VST,
489 !strconcat(OpcodeStr,
490 "\t\\{$src1[$lane],$src2[$lane],$src3[$lane]\\}, $addr"), "", []>;
492 def VST3LNd8 : VST3LN<0b0010, "vst3.8">;
493 def VST3LNd16 : VST3LN<0b0110, "vst3.16">;
494 def VST3LNd32 : VST3LN<0b1010, "vst3.32">;
496 // vst3 to double-spaced even registers.
497 def VST3LNq16a: VST3LN<0b0110, "vst3.16">;
498 def VST3LNq32a: VST3LN<0b1010, "vst3.32">;
500 // vst3 to double-spaced odd registers.
501 def VST3LNq16b: VST3LN<0b0110, "vst3.16">;
502 def VST3LNq32b: VST3LN<0b1010, "vst3.32">;
504 // VST4LN : Vector Store (single 4-element structure from one lane)
505 class VST4LN<bits<4> op11_8, string OpcodeStr>
506 : NLdSt<1,0b00,op11_8,0b0000, (outs),
507 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
508 nohash_imm:$lane), IIC_VST,
509 !strconcat(OpcodeStr,
510 "\t\\{$src1[$lane],$src2[$lane],$src3[$lane],$src4[$lane]\\}, $addr"),
513 def VST4LNd8 : VST4LN<0b0011, "vst4.8">;
514 def VST4LNd16 : VST4LN<0b0111, "vst4.16">;
515 def VST4LNd32 : VST4LN<0b1011, "vst4.32">;
517 // vst4 to double-spaced even registers.
518 def VST4LNq16a: VST4LN<0b0111, "vst4.16">;
519 def VST4LNq32a: VST4LN<0b1011, "vst4.32">;
521 // vst4 to double-spaced odd registers.
522 def VST4LNq16b: VST4LN<0b0111, "vst4.16">;
523 def VST4LNq32b: VST4LN<0b1011, "vst4.32">;
525 } // mayStore = 1, hasExtraSrcRegAllocReq = 1
528 //===----------------------------------------------------------------------===//
529 // NEON pattern fragments
530 //===----------------------------------------------------------------------===//
532 // Extract D sub-registers of Q registers.
533 // (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
534 def DSubReg_i8_reg : SDNodeXForm<imm, [{
535 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
537 def DSubReg_i16_reg : SDNodeXForm<imm, [{
538 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
540 def DSubReg_i32_reg : SDNodeXForm<imm, [{
541 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
543 def DSubReg_f64_reg : SDNodeXForm<imm, [{
544 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
546 def DSubReg_f64_other_reg : SDNodeXForm<imm, [{
547 return CurDAG->getTargetConstant(5 + (1 - N->getZExtValue()), MVT::i32);
550 // Extract S sub-registers of Q/D registers.
551 // (arm_ssubreg_0 is 1; arm_ssubreg_1 is 2; etc.)
552 def SSubReg_f32_reg : SDNodeXForm<imm, [{
553 return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32);
556 // Translate lane numbers from Q registers to D subregs.
557 def SubReg_i8_lane : SDNodeXForm<imm, [{
558 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
560 def SubReg_i16_lane : SDNodeXForm<imm, [{
561 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
563 def SubReg_i32_lane : SDNodeXForm<imm, [{
564 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
567 //===----------------------------------------------------------------------===//
568 // Instruction Classes
569 //===----------------------------------------------------------------------===//
571 // Basic 2-register operations, both double- and quad-register.
572 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
573 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
574 ValueType ResTy, ValueType OpTy, SDNode OpNode>
575 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
576 (ins DPR:$src), IIC_VUNAD, !strconcat(OpcodeStr, "\t$dst, $src"), "",
577 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
578 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
579 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
580 ValueType ResTy, ValueType OpTy, SDNode OpNode>
581 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
582 (ins QPR:$src), IIC_VUNAQ, !strconcat(OpcodeStr, "\t$dst, $src"), "",
583 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
585 // Basic 2-register operations, scalar single-precision.
586 class N2VDs<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
587 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
588 ValueType ResTy, ValueType OpTy, SDNode OpNode>
589 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
590 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
591 IIC_VUNAD, !strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
593 class N2VDsPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
594 : NEONFPPat<(ResTy (OpNode SPR:$a)),
596 (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
599 // Basic 2-register intrinsics, both double- and quad-register.
600 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
601 bits<2> op17_16, bits<5> op11_7, bit op4,
602 InstrItinClass itin, string OpcodeStr,
603 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
604 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
605 (ins DPR:$src), itin, !strconcat(OpcodeStr, "\t$dst, $src"), "",
606 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
607 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
608 bits<2> op17_16, bits<5> op11_7, bit op4,
609 InstrItinClass itin, string OpcodeStr,
610 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
611 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
612 (ins QPR:$src), itin, !strconcat(OpcodeStr, "\t$dst, $src"), "",
613 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
615 // Basic 2-register intrinsics, scalar single-precision
616 class N2VDInts<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
617 bits<2> op17_16, bits<5> op11_7, bit op4,
618 InstrItinClass itin, string OpcodeStr,
619 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
620 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
621 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), itin,
622 !strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
624 class N2VDIntsPat<SDNode OpNode, NeonI Inst>
625 : NEONFPPat<(f32 (OpNode SPR:$a)),
627 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
630 // Narrow 2-register intrinsics.
631 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
632 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
633 InstrItinClass itin, string OpcodeStr,
634 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
635 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
636 (ins QPR:$src), itin, !strconcat(OpcodeStr, "\t$dst, $src"), "",
637 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
639 // Long 2-register intrinsics (currently only used for VMOVL).
640 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
641 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
642 InstrItinClass itin, string OpcodeStr,
643 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
644 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$dst),
645 (ins DPR:$src), itin, !strconcat(OpcodeStr, "\t$dst, $src"), "",
646 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
648 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
649 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr>
650 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
651 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
652 !strconcat(OpcodeStr, "\t$dst1, $dst2"),
653 "$src1 = $dst1, $src2 = $dst2", []>;
654 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
655 InstrItinClass itin, string OpcodeStr>
656 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
657 (ins QPR:$src1, QPR:$src2), itin,
658 !strconcat(OpcodeStr, "\t$dst1, $dst2"),
659 "$src1 = $dst1, $src2 = $dst2", []>;
661 // Basic 3-register operations, both double- and quad-register.
662 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
663 InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy,
664 SDNode OpNode, bit Commutable>
665 : N3V<op24, op23, op21_20, op11_8, 0, op4,
666 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
667 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
668 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
669 let isCommutable = Commutable;
671 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
672 InstrItinClass itin, string OpcodeStr, ValueType Ty, SDNode ShOp>
673 : N3V<0, 1, op21_20, op11_8, 1, 0,
674 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
675 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
677 (Ty (ShOp (Ty DPR:$src1),
678 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
680 let isCommutable = 0;
682 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
683 string OpcodeStr, ValueType Ty, SDNode ShOp>
684 : N3V<0, 1, op21_20, op11_8, 1, 0,
685 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
687 !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
689 (Ty (ShOp (Ty DPR:$src1),
690 (Ty (NEONvduplane (Ty DPR_8:$src2),
692 let isCommutable = 0;
695 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
696 InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy,
697 SDNode OpNode, bit Commutable>
698 : N3V<op24, op23, op21_20, op11_8, 1, op4,
699 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
700 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
701 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
702 let isCommutable = Commutable;
704 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
705 InstrItinClass itin, string OpcodeStr,
706 ValueType ResTy, ValueType OpTy, SDNode ShOp>
707 : N3V<1, 1, op21_20, op11_8, 1, 0,
708 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
709 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
710 [(set (ResTy QPR:$dst),
711 (ResTy (ShOp (ResTy QPR:$src1),
712 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
714 let isCommutable = 0;
716 class N3VQSL16<bits<2> op21_20, bits<4> op11_8,
717 string OpcodeStr, ValueType ResTy, ValueType OpTy, SDNode ShOp>
718 : N3V<1, 1, op21_20, op11_8, 1, 0,
719 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
721 !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
722 [(set (ResTy QPR:$dst),
723 (ResTy (ShOp (ResTy QPR:$src1),
724 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
726 let isCommutable = 0;
729 // Basic 3-register operations, scalar single-precision
730 class N3VDs<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
731 string OpcodeStr, ValueType ResTy, ValueType OpTy,
732 SDNode OpNode, bit Commutable>
733 : N3V<op24, op23, op21_20, op11_8, 0, op4,
734 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), IIC_VBIND,
735 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", []> {
736 let isCommutable = Commutable;
738 class N3VDsPat<SDNode OpNode, NeonI Inst>
739 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
741 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
742 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
745 // Basic 3-register intrinsics, both double- and quad-register.
746 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
747 InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy,
748 Intrinsic IntOp, bit Commutable>
749 : N3V<op24, op23, op21_20, op11_8, 0, op4,
750 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
751 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
752 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
753 let isCommutable = Commutable;
755 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
756 string OpcodeStr, ValueType Ty, Intrinsic IntOp>
757 : N3V<0, 1, op21_20, op11_8, 1, 0,
758 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
759 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
761 (Ty (IntOp (Ty DPR:$src1),
762 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
764 let isCommutable = 0;
766 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
767 string OpcodeStr, ValueType Ty, Intrinsic IntOp>
768 : N3V<0, 1, op21_20, op11_8, 1, 0,
769 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
770 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
772 (Ty (IntOp (Ty DPR:$src1),
773 (Ty (NEONvduplane (Ty DPR_8:$src2),
775 let isCommutable = 0;
778 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
779 InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy,
780 Intrinsic IntOp, bit Commutable>
781 : N3V<op24, op23, op21_20, op11_8, 1, op4,
782 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
783 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
784 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
785 let isCommutable = Commutable;
787 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
788 string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
789 : N3V<1, 1, op21_20, op11_8, 1, 0,
790 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
791 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
792 [(set (ResTy QPR:$dst),
793 (ResTy (IntOp (ResTy QPR:$src1),
794 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
796 let isCommutable = 0;
798 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
799 string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
800 : N3V<1, 1, op21_20, op11_8, 1, 0,
801 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
802 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
803 [(set (ResTy QPR:$dst),
804 (ResTy (IntOp (ResTy QPR:$src1),
805 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
807 let isCommutable = 0;
810 // Multiply-Add/Sub operations, both double- and quad-register.
811 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
812 InstrItinClass itin, string OpcodeStr,
813 ValueType Ty, SDNode MulOp, SDNode OpNode>
814 : N3V<op24, op23, op21_20, op11_8, 0, op4,
815 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin,
816 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
817 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
818 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
819 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
820 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode ShOp>
821 : N3V<0, 1, op21_20, op11_8, 1, 0,
823 (ins DPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
824 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
826 (Ty (ShOp (Ty DPR:$src1),
827 (Ty (MulOp DPR:$src2,
828 (Ty (NEONvduplane (Ty DPR_VFP2:$src3),
830 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
831 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode ShOp>
832 : N3V<0, 1, op21_20, op11_8, 1, 0,
834 (ins DPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
835 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
837 (Ty (ShOp (Ty DPR:$src1),
838 (Ty (MulOp DPR:$src2,
839 (Ty (NEONvduplane (Ty DPR_8:$src3),
842 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
843 InstrItinClass itin, string OpcodeStr, ValueType Ty,
844 SDNode MulOp, SDNode OpNode>
845 : N3V<op24, op23, op21_20, op11_8, 1, op4,
846 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin,
847 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
848 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
849 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
850 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
851 string OpcodeStr, ValueType ResTy, ValueType OpTy,
852 SDNode MulOp, SDNode ShOp>
853 : N3V<1, 1, op21_20, op11_8, 1, 0,
855 (ins QPR:$src1, QPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
856 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
857 [(set (ResTy QPR:$dst),
858 (ResTy (ShOp (ResTy QPR:$src1),
859 (ResTy (MulOp QPR:$src2,
860 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src3),
862 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
863 string OpcodeStr, ValueType ResTy, ValueType OpTy,
864 SDNode MulOp, SDNode ShOp>
865 : N3V<1, 1, op21_20, op11_8, 1, 0,
867 (ins QPR:$src1, QPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
868 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
869 [(set (ResTy QPR:$dst),
870 (ResTy (ShOp (ResTy QPR:$src1),
871 (ResTy (MulOp QPR:$src2,
872 (ResTy (NEONvduplane (OpTy DPR_8:$src3),
875 // Multiply-Add/Sub operations, scalar single-precision
876 class N3VDMulOps<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
877 InstrItinClass itin, string OpcodeStr,
878 ValueType Ty, SDNode MulOp, SDNode OpNode>
879 : N3V<op24, op23, op21_20, op11_8, 0, op4,
880 (outs DPR_VFP2:$dst),
881 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), itin,
882 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", []>;
884 class N3VDMulOpsPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
885 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
887 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$acc, arm_ssubreg_0),
888 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
889 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
892 // Neon 3-argument intrinsics, both double- and quad-register.
893 // The destination register is also used as the first source operand register.
894 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
895 InstrItinClass itin, string OpcodeStr,
896 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
897 : N3V<op24, op23, op21_20, op11_8, 0, op4,
898 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin,
899 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
900 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
901 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
902 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
903 InstrItinClass itin, string OpcodeStr,
904 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
905 : N3V<op24, op23, op21_20, op11_8, 1, op4,
906 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin,
907 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
908 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
909 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
911 // Neon Long 3-argument intrinsic. The destination register is
912 // a quad-register and is also used as the first source operand register.
913 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
914 InstrItinClass itin, string OpcodeStr,
915 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
916 : N3V<op24, op23, op21_20, op11_8, 0, op4,
917 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), itin,
918 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
920 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
921 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
922 string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
923 : N3V<op24, 1, op21_20, op11_8, 1, 0,
925 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
926 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
927 [(set (ResTy QPR:$dst),
928 (ResTy (IntOp (ResTy QPR:$src1),
930 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src3),
932 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
933 string OpcodeStr, ValueType ResTy, ValueType OpTy,
935 : N3V<op24, 1, op21_20, op11_8, 1, 0,
937 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
938 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
939 [(set (ResTy QPR:$dst),
940 (ResTy (IntOp (ResTy QPR:$src1),
942 (OpTy (NEONvduplane (OpTy DPR_8:$src3),
946 // Narrowing 3-register intrinsics.
947 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
948 string OpcodeStr, ValueType TyD, ValueType TyQ,
949 Intrinsic IntOp, bit Commutable>
950 : N3V<op24, op23, op21_20, op11_8, 0, op4,
951 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VBINi4D,
952 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
953 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
954 let isCommutable = Commutable;
957 // Long 3-register intrinsics.
958 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
959 InstrItinClass itin, string OpcodeStr, ValueType TyQ, ValueType TyD,
960 Intrinsic IntOp, bit Commutable>
961 : N3V<op24, op23, op21_20, op11_8, 0, op4,
962 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
963 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
964 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
965 let isCommutable = Commutable;
967 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
968 string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
969 : N3V<op24, 1, op21_20, op11_8, 1, 0,
970 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
971 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
972 [(set (ResTy QPR:$dst),
973 (ResTy (IntOp (OpTy DPR:$src1),
974 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src2),
976 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
977 string OpcodeStr, ValueType ResTy, ValueType OpTy,
979 : N3V<op24, 1, op21_20, op11_8, 1, 0,
980 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
981 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
982 [(set (ResTy QPR:$dst),
983 (ResTy (IntOp (OpTy DPR:$src1),
984 (OpTy (NEONvduplane (OpTy DPR_8:$src2),
987 // Wide 3-register intrinsics.
988 class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
989 string OpcodeStr, ValueType TyQ, ValueType TyD,
990 Intrinsic IntOp, bit Commutable>
991 : N3V<op24, op23, op21_20, op11_8, 0, op4,
992 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), IIC_VSUBiD,
993 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
994 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
995 let isCommutable = Commutable;
998 // Pairwise long 2-register intrinsics, both double- and quad-register.
999 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1000 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1001 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1002 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1003 (ins DPR:$src), IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "",
1004 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
1005 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1006 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1007 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1008 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1009 (ins QPR:$src), IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "",
1010 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
1012 // Pairwise long 2-register accumulate intrinsics,
1013 // both double- and quad-register.
1014 // The destination register is also used as the first source operand register.
1015 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1016 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1017 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1018 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
1019 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), IIC_VPALiD,
1020 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
1021 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
1022 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1023 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1024 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1025 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
1026 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VPALiQ,
1027 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
1028 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
1030 // Shift by immediate,
1031 // both double- and quad-register.
1032 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1033 InstrItinClass itin, string OpcodeStr, ValueType Ty, SDNode OpNode>
1034 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1035 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), itin,
1036 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
1037 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
1038 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1039 InstrItinClass itin, string OpcodeStr, ValueType Ty, SDNode OpNode>
1040 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1041 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin,
1042 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
1043 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
1045 // Long shift by immediate.
1046 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1047 string OpcodeStr, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1048 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1049 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VSHLiD,
1050 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
1051 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
1052 (i32 imm:$SIMM))))]>;
1054 // Narrow shift by immediate.
1055 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1056 InstrItinClass itin, string OpcodeStr,
1057 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1058 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1059 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin,
1060 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
1061 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
1062 (i32 imm:$SIMM))))]>;
1064 // Shift right by immediate and accumulate,
1065 // both double- and quad-register.
1066 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1067 string OpcodeStr, ValueType Ty, SDNode ShOp>
1068 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1069 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), IIC_VPALiD,
1070 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
1071 [(set DPR:$dst, (Ty (add DPR:$src1,
1072 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
1073 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1074 string OpcodeStr, ValueType Ty, SDNode ShOp>
1075 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1076 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), IIC_VPALiD,
1077 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
1078 [(set QPR:$dst, (Ty (add QPR:$src1,
1079 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
1081 // Shift by immediate and insert,
1082 // both double- and quad-register.
1083 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1084 string OpcodeStr, ValueType Ty, SDNode ShOp>
1085 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1086 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), IIC_VSHLiD,
1087 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
1088 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
1089 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1090 string OpcodeStr, ValueType Ty, SDNode ShOp>
1091 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1092 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), IIC_VSHLiQ,
1093 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
1094 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
1096 // Convert, with fractional bits immediate,
1097 // both double- and quad-register.
1098 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1099 string OpcodeStr, ValueType ResTy, ValueType OpTy,
1101 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1102 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VUNAD,
1103 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
1104 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
1105 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1106 string OpcodeStr, ValueType ResTy, ValueType OpTy,
1108 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1109 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), IIC_VUNAQ,
1110 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
1111 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
1113 //===----------------------------------------------------------------------===//
1115 //===----------------------------------------------------------------------===//
1117 // Abbreviations used in multiclass suffixes:
1118 // Q = quarter int (8 bit) elements
1119 // H = half int (16 bit) elements
1120 // S = single int (32 bit) elements
1121 // D = double int (64 bit) elements
1123 // Neon 3-register vector operations.
1125 // First with only element sizes of 8, 16 and 32 bits:
1126 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1127 InstrItinClass itinD16, InstrItinClass itinD32,
1128 InstrItinClass itinQ16, InstrItinClass itinQ32,
1129 string OpcodeStr, SDNode OpNode, bit Commutable = 0> {
1130 // 64-bit vector types.
1131 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
1132 !strconcat(OpcodeStr, "8"), v8i8, v8i8, OpNode, Commutable>;
1133 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
1134 !strconcat(OpcodeStr, "16"), v4i16, v4i16, OpNode, Commutable>;
1135 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
1136 !strconcat(OpcodeStr, "32"), v2i32, v2i32, OpNode, Commutable>;
1138 // 128-bit vector types.
1139 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
1140 !strconcat(OpcodeStr, "8"), v16i8, v16i8, OpNode, Commutable>;
1141 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
1142 !strconcat(OpcodeStr, "16"), v8i16, v8i16, OpNode, Commutable>;
1143 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
1144 !strconcat(OpcodeStr, "32"), v4i32, v4i32, OpNode, Commutable>;
1147 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, SDNode ShOp> {
1148 def v4i16 : N3VDSL16<0b01, op11_8, !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
1149 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
1150 def v8i16 : N3VQSL16<0b01, op11_8, !strconcat(OpcodeStr, "16"), v8i16, v4i16, ShOp>;
1151 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, !strconcat(OpcodeStr, "32"), v4i32, v2i32, ShOp>;
1154 // ....then also with element size 64 bits:
1155 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1156 InstrItinClass itinD, InstrItinClass itinQ,
1157 string OpcodeStr, SDNode OpNode, bit Commutable = 0>
1158 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
1159 OpcodeStr, OpNode, Commutable> {
1160 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
1161 !strconcat(OpcodeStr, "64"), v1i64, v1i64, OpNode, Commutable>;
1162 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
1163 !strconcat(OpcodeStr, "64"), v2i64, v2i64, OpNode, Commutable>;
1167 // Neon Narrowing 2-register vector intrinsics,
1168 // source operand element sizes of 16, 32 and 64 bits:
1169 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1170 bits<5> op11_7, bit op6, bit op4,
1171 InstrItinClass itin, string OpcodeStr,
1173 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
1174 itin, !strconcat(OpcodeStr, "16"), v8i8, v8i16, IntOp>;
1175 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
1176 itin, !strconcat(OpcodeStr, "32"), v4i16, v4i32, IntOp>;
1177 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
1178 itin, !strconcat(OpcodeStr, "64"), v2i32, v2i64, IntOp>;
1182 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
1183 // source operand element sizes of 16, 32 and 64 bits:
1184 multiclass N2VLInt_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
1185 string OpcodeStr, Intrinsic IntOp> {
1186 def v8i16 : N2VLInt<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1187 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
1188 def v4i32 : N2VLInt<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1189 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
1190 def v2i64 : N2VLInt<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1191 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
1195 // Neon 3-register vector intrinsics.
1197 // First with only element sizes of 16 and 32 bits:
1198 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1199 InstrItinClass itinD16, InstrItinClass itinD32,
1200 InstrItinClass itinQ16, InstrItinClass itinQ32,
1201 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
1202 // 64-bit vector types.
1203 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, itinD16, !strconcat(OpcodeStr,"16"),
1204 v4i16, v4i16, IntOp, Commutable>;
1205 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, itinD32, !strconcat(OpcodeStr,"32"),
1206 v2i32, v2i32, IntOp, Commutable>;
1208 // 128-bit vector types.
1209 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, itinQ16, !strconcat(OpcodeStr,"16"),
1210 v8i16, v8i16, IntOp, Commutable>;
1211 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, itinQ32, !strconcat(OpcodeStr,"32"),
1212 v4i32, v4i32, IntOp, Commutable>;
1215 multiclass N3VIntSL_HS<bits<4> op11_8,
1216 InstrItinClass itinD16, InstrItinClass itinD32,
1217 InstrItinClass itinQ16, InstrItinClass itinQ32,
1218 string OpcodeStr, Intrinsic IntOp> {
1219 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16, !strconcat(OpcodeStr, "16"), v4i16, IntOp>;
1220 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32, !strconcat(OpcodeStr, "32"), v2i32, IntOp>;
1221 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16, !strconcat(OpcodeStr, "16"), v8i16, v4i16, IntOp>;
1222 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32, !strconcat(OpcodeStr, "32"), v4i32, v2i32, IntOp>;
1225 // ....then also with element size of 8 bits:
1226 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1227 InstrItinClass itinD16, InstrItinClass itinD32,
1228 InstrItinClass itinQ16, InstrItinClass itinQ32,
1229 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
1230 : N3VInt_HS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
1231 OpcodeStr, IntOp, Commutable> {
1232 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, itinD16,
1233 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp, Commutable>;
1234 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, itinQ16,
1235 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp, Commutable>;
1238 // ....then also with element size of 64 bits:
1239 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1240 InstrItinClass itinD16, InstrItinClass itinD32,
1241 InstrItinClass itinQ16, InstrItinClass itinQ32,
1242 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
1243 : N3VInt_QHS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
1244 OpcodeStr, IntOp, Commutable> {
1245 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, itinD32,
1246 !strconcat(OpcodeStr,"64"), v1i64, v1i64, IntOp, Commutable>;
1247 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, itinQ32,
1248 !strconcat(OpcodeStr,"64"), v2i64, v2i64, IntOp, Commutable>;
1252 // Neon Narrowing 3-register vector intrinsics,
1253 // source operand element sizes of 16, 32 and 64 bits:
1254 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1255 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
1256 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr,"16"),
1257 v8i8, v8i16, IntOp, Commutable>;
1258 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"32"),
1259 v4i16, v4i32, IntOp, Commutable>;
1260 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"64"),
1261 v2i32, v2i64, IntOp, Commutable>;
1265 // Neon Long 3-register vector intrinsics.
1267 // First with only element sizes of 16 and 32 bits:
1268 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1269 InstrItinClass itin, string OpcodeStr,
1270 Intrinsic IntOp, bit Commutable = 0> {
1271 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin,
1272 !strconcat(OpcodeStr,"16"), v4i32, v4i16, IntOp, Commutable>;
1273 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin,
1274 !strconcat(OpcodeStr,"32"), v2i64, v2i32, IntOp, Commutable>;
1277 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
1278 InstrItinClass itin, string OpcodeStr, Intrinsic IntOp> {
1279 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
1280 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
1281 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
1282 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
1285 // ....then also with element size of 8 bits:
1286 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1287 InstrItinClass itin, string OpcodeStr,
1288 Intrinsic IntOp, bit Commutable = 0>
1289 : N3VLInt_HS<op24, op23, op11_8, op4, itin, OpcodeStr, IntOp, Commutable> {
1290 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin,
1291 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp, Commutable>;
1295 // Neon Wide 3-register vector intrinsics,
1296 // source operand element sizes of 8, 16 and 32 bits:
1297 multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1298 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
1299 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
1300 v8i16, v8i8, IntOp, Commutable>;
1301 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
1302 v4i32, v4i16, IntOp, Commutable>;
1303 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
1304 v2i64, v2i32, IntOp, Commutable>;
1308 // Neon Multiply-Op vector operations,
1309 // element sizes of 8, 16 and 32 bits:
1310 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1311 InstrItinClass itinD16, InstrItinClass itinD32,
1312 InstrItinClass itinQ16, InstrItinClass itinQ32,
1313 string OpcodeStr, SDNode OpNode> {
1314 // 64-bit vector types.
1315 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
1316 !strconcat(OpcodeStr, "8"), v8i8, mul, OpNode>;
1317 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
1318 !strconcat(OpcodeStr, "16"), v4i16, mul, OpNode>;
1319 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
1320 !strconcat(OpcodeStr, "32"), v2i32, mul, OpNode>;
1322 // 128-bit vector types.
1323 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
1324 !strconcat(OpcodeStr, "8"), v16i8, mul, OpNode>;
1325 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
1326 !strconcat(OpcodeStr, "16"), v8i16, mul, OpNode>;
1327 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
1328 !strconcat(OpcodeStr, "32"), v4i32, mul, OpNode>;
1331 multiclass N3VMulOpSL_HS<bits<4> op11_8,
1332 InstrItinClass itinD16, InstrItinClass itinD32,
1333 InstrItinClass itinQ16, InstrItinClass itinQ32,
1334 string OpcodeStr, SDNode ShOp> {
1335 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
1336 !strconcat(OpcodeStr, "16"), v4i16, mul, ShOp>;
1337 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
1338 !strconcat(OpcodeStr, "32"), v2i32, mul, ShOp>;
1339 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
1340 !strconcat(OpcodeStr, "16"), v8i16, v4i16, mul, ShOp>;
1341 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
1342 !strconcat(OpcodeStr, "32"), v4i32, v2i32, mul, ShOp>;
1345 // Neon 3-argument intrinsics,
1346 // element sizes of 8, 16 and 32 bits:
1347 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1348 string OpcodeStr, Intrinsic IntOp> {
1349 // 64-bit vector types.
1350 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16D,
1351 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
1352 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
1353 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
1354 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32D,
1355 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
1357 // 128-bit vector types.
1358 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16Q,
1359 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
1360 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16Q,
1361 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
1362 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32Q,
1363 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
1367 // Neon Long 3-argument intrinsics.
1369 // First with only element sizes of 16 and 32 bits:
1370 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1371 string OpcodeStr, Intrinsic IntOp> {
1372 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
1373 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
1374 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi16D,
1375 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
1378 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
1379 string OpcodeStr, Intrinsic IntOp> {
1380 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
1381 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
1382 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
1383 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
1386 // ....then also with element size of 8 bits:
1387 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1388 string OpcodeStr, Intrinsic IntOp>
1389 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp> {
1390 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16D,
1391 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
1395 // Neon 2-register vector intrinsics,
1396 // element sizes of 8, 16 and 32 bits:
1397 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1398 bits<5> op11_7, bit op4,
1399 InstrItinClass itinD, InstrItinClass itinQ,
1400 string OpcodeStr, Intrinsic IntOp> {
1401 // 64-bit vector types.
1402 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1403 itinD, !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
1404 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1405 itinD, !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
1406 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1407 itinD, !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
1409 // 128-bit vector types.
1410 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1411 itinQ, !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
1412 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1413 itinQ, !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
1414 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1415 itinQ, !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
1419 // Neon Pairwise long 2-register intrinsics,
1420 // element sizes of 8, 16 and 32 bits:
1421 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1422 bits<5> op11_7, bit op4,
1423 string OpcodeStr, Intrinsic IntOp> {
1424 // 64-bit vector types.
1425 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1426 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
1427 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1428 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
1429 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1430 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
1432 // 128-bit vector types.
1433 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1434 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
1435 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1436 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
1437 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1438 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
1442 // Neon Pairwise long 2-register accumulate intrinsics,
1443 // element sizes of 8, 16 and 32 bits:
1444 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1445 bits<5> op11_7, bit op4,
1446 string OpcodeStr, Intrinsic IntOp> {
1447 // 64-bit vector types.
1448 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1449 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
1450 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1451 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
1452 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1453 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
1455 // 128-bit vector types.
1456 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1457 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
1458 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1459 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
1460 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1461 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
1465 // Neon 2-register vector shift by immediate,
1466 // element sizes of 8, 16, 32 and 64 bits:
1467 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1468 InstrItinClass itin, string OpcodeStr, SDNode OpNode> {
1469 // 64-bit vector types.
1470 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
1471 !strconcat(OpcodeStr, "8"), v8i8, OpNode> {
1472 let Inst{21-19} = 0b001; // imm6 = 001xxx
1474 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
1475 !strconcat(OpcodeStr, "16"), v4i16, OpNode> {
1476 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1478 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
1479 !strconcat(OpcodeStr, "32"), v2i32, OpNode> {
1480 let Inst{21} = 0b1; // imm6 = 1xxxxx
1482 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, itin,
1483 !strconcat(OpcodeStr, "64"), v1i64, OpNode>;
1486 // 128-bit vector types.
1487 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
1488 !strconcat(OpcodeStr, "8"), v16i8, OpNode> {
1489 let Inst{21-19} = 0b001; // imm6 = 001xxx
1491 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
1492 !strconcat(OpcodeStr, "16"), v8i16, OpNode> {
1493 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1495 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
1496 !strconcat(OpcodeStr, "32"), v4i32, OpNode> {
1497 let Inst{21} = 0b1; // imm6 = 1xxxxx
1499 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, itin,
1500 !strconcat(OpcodeStr, "64"), v2i64, OpNode>;
1505 // Neon Shift-Accumulate vector operations,
1506 // element sizes of 8, 16, 32 and 64 bits:
1507 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1508 string OpcodeStr, SDNode ShOp> {
1509 // 64-bit vector types.
1510 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1511 !strconcat(OpcodeStr, "8"), v8i8, ShOp> {
1512 let Inst{21-19} = 0b001; // imm6 = 001xxx
1514 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1515 !strconcat(OpcodeStr, "16"), v4i16, ShOp> {
1516 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1518 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1519 !strconcat(OpcodeStr, "32"), v2i32, ShOp> {
1520 let Inst{21} = 0b1; // imm6 = 1xxxxx
1522 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4,
1523 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
1526 // 128-bit vector types.
1527 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1528 !strconcat(OpcodeStr, "8"), v16i8, ShOp> {
1529 let Inst{21-19} = 0b001; // imm6 = 001xxx
1531 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1532 !strconcat(OpcodeStr, "16"), v8i16, ShOp> {
1533 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1535 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1536 !strconcat(OpcodeStr, "32"), v4i32, ShOp> {
1537 let Inst{21} = 0b1; // imm6 = 1xxxxx
1539 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4,
1540 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
1545 // Neon Shift-Insert vector operations,
1546 // element sizes of 8, 16, 32 and 64 bits:
1547 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1548 string OpcodeStr, SDNode ShOp> {
1549 // 64-bit vector types.
1550 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4,
1551 !strconcat(OpcodeStr, "8"), v8i8, ShOp> {
1552 let Inst{21-19} = 0b001; // imm6 = 001xxx
1554 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4,
1555 !strconcat(OpcodeStr, "16"), v4i16, ShOp> {
1556 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1558 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4,
1559 !strconcat(OpcodeStr, "32"), v2i32, ShOp> {
1560 let Inst{21} = 0b1; // imm6 = 1xxxxx
1562 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4,
1563 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
1566 // 128-bit vector types.
1567 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4,
1568 !strconcat(OpcodeStr, "8"), v16i8, ShOp> {
1569 let Inst{21-19} = 0b001; // imm6 = 001xxx
1571 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4,
1572 !strconcat(OpcodeStr, "16"), v8i16, ShOp> {
1573 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1575 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4,
1576 !strconcat(OpcodeStr, "32"), v4i32, ShOp> {
1577 let Inst{21} = 0b1; // imm6 = 1xxxxx
1579 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4,
1580 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
1584 // Neon Shift Long operations,
1585 // element sizes of 8, 16, 32 bits:
1586 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
1587 bit op4, string OpcodeStr, SDNode OpNode> {
1588 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1589 !strconcat(OpcodeStr, "8"), v8i16, v8i8, OpNode> {
1590 let Inst{21-19} = 0b001; // imm6 = 001xxx
1592 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1593 !strconcat(OpcodeStr, "16"), v4i32, v4i16, OpNode> {
1594 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1596 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1597 !strconcat(OpcodeStr, "32"), v2i64, v2i32, OpNode> {
1598 let Inst{21} = 0b1; // imm6 = 1xxxxx
1602 // Neon Shift Narrow operations,
1603 // element sizes of 16, 32, 64 bits:
1604 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
1605 bit op4, InstrItinClass itin, string OpcodeStr,
1607 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1608 !strconcat(OpcodeStr, "16"), v8i8, v8i16, OpNode> {
1609 let Inst{21-19} = 0b001; // imm6 = 001xxx
1611 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1612 !strconcat(OpcodeStr, "32"), v4i16, v4i32, OpNode> {
1613 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1615 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1616 !strconcat(OpcodeStr, "64"), v2i32, v2i64, OpNode> {
1617 let Inst{21} = 0b1; // imm6 = 1xxxxx
1621 //===----------------------------------------------------------------------===//
1622 // Instruction Definitions.
1623 //===----------------------------------------------------------------------===//
1625 // Vector Add Operations.
1627 // VADD : Vector Add (integer and floating-point)
1628 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd.i", add, 1>;
1629 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd.f32", v2f32, v2f32, fadd, 1>;
1630 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd.f32", v4f32, v4f32, fadd, 1>;
1631 // VADDL : Vector Add Long (Q = D + D)
1632 defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, IIC_VSHLiD, "vaddl.s", int_arm_neon_vaddls, 1>;
1633 defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, IIC_VSHLiD, "vaddl.u", int_arm_neon_vaddlu, 1>;
1634 // VADDW : Vector Add Wide (Q = Q + D)
1635 defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw.s", int_arm_neon_vaddws, 0>;
1636 defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw.u", int_arm_neon_vaddwu, 0>;
1637 // VHADD : Vector Halving Add
1638 defm VHADDs : N3VInt_QHS<0,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1639 IIC_VBINi4Q, "vhadd.s", int_arm_neon_vhadds, 1>;
1640 defm VHADDu : N3VInt_QHS<1,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1641 IIC_VBINi4Q, "vhadd.u", int_arm_neon_vhaddu, 1>;
1642 // VRHADD : Vector Rounding Halving Add
1643 defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1644 IIC_VBINi4Q, "vrhadd.s", int_arm_neon_vrhadds, 1>;
1645 defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1646 IIC_VBINi4Q, "vrhadd.u", int_arm_neon_vrhaddu, 1>;
1647 // VQADD : Vector Saturating Add
1648 defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1649 IIC_VBINi4Q, "vqadd.s", int_arm_neon_vqadds, 1>;
1650 defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1651 IIC_VBINi4Q, "vqadd.u", int_arm_neon_vqaddu, 1>;
1652 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
1653 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn.i", int_arm_neon_vaddhn, 1>;
1654 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
1655 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn.i", int_arm_neon_vraddhn, 1>;
1657 // Vector Multiply Operations.
1659 // VMUL : Vector Multiply (integer, polynomial and floating-point)
1660 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D, IIC_VMULi16Q,
1661 IIC_VMULi32Q, "vmul.i", mul, 1>;
1662 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16D, "vmul.p8", v8i8, v8i8,
1663 int_arm_neon_vmulp, 1>;
1664 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16Q, "vmul.p8", v16i8, v16i8,
1665 int_arm_neon_vmulp, 1>;
1666 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VBIND, "vmul.f32", v2f32, v2f32, fmul, 1>;
1667 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VBINQ, "vmul.f32", v4f32, v4f32, fmul, 1>;
1668 defm VMULsl : N3VSL_HS<0b1000, "vmul.i", mul>;
1669 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul.f32", v2f32, fmul>;
1670 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul.f32", v4f32, v2f32, fmul>;
1671 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
1672 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
1673 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
1674 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1675 (DSubReg_i16_reg imm:$lane))),
1676 (SubReg_i16_lane imm:$lane)))>;
1677 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
1678 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
1679 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
1680 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1681 (DSubReg_i32_reg imm:$lane))),
1682 (SubReg_i32_lane imm:$lane)))>;
1683 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
1684 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
1685 (v4f32 (VMULslfq (v4f32 QPR:$src1),
1686 (v2f32 (EXTRACT_SUBREG QPR:$src2,
1687 (DSubReg_i32_reg imm:$lane))),
1688 (SubReg_i32_lane imm:$lane)))>;
1690 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
1691 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
1692 IIC_VMULi16Q, IIC_VMULi32Q,
1693 "vqdmulh.s", int_arm_neon_vqdmulh, 1>;
1694 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
1695 IIC_VMULi16Q, IIC_VMULi32Q,
1696 "vqdmulh.s", int_arm_neon_vqdmulh>;
1697 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
1698 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
1699 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
1700 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1701 (DSubReg_i16_reg imm:$lane))),
1702 (SubReg_i16_lane imm:$lane)))>;
1703 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
1704 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
1705 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
1706 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1707 (DSubReg_i32_reg imm:$lane))),
1708 (SubReg_i32_lane imm:$lane)))>;
1710 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
1711 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
1712 IIC_VMULi16Q, IIC_VMULi32Q,
1713 "vqrdmulh.s", int_arm_neon_vqrdmulh, 1>;
1714 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
1715 IIC_VMULi16Q, IIC_VMULi32Q,
1716 "vqrdmulh.s", int_arm_neon_vqrdmulh>;
1717 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
1718 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
1719 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
1720 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1721 (DSubReg_i16_reg imm:$lane))),
1722 (SubReg_i16_lane imm:$lane)))>;
1723 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
1724 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
1725 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
1726 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1727 (DSubReg_i32_reg imm:$lane))),
1728 (SubReg_i32_lane imm:$lane)))>;
1730 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
1731 defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, IIC_VMULi16D, "vmull.s", int_arm_neon_vmulls, 1>;
1732 defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, IIC_VMULi16D, "vmull.u", int_arm_neon_vmullu, 1>;
1733 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull.p8", v8i16, v8i8,
1734 int_arm_neon_vmullp, 1>;
1735 defm VMULLsls : N3VLIntSL_HS<0, 0b1010, IIC_VMULi16D, "vmull.s", int_arm_neon_vmulls>;
1736 defm VMULLslu : N3VLIntSL_HS<1, 0b1010, IIC_VMULi16D, "vmull.u", int_arm_neon_vmullu>;
1738 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
1739 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, "vqdmull.s", int_arm_neon_vqdmull, 1>;
1740 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D, "vqdmull.s", int_arm_neon_vqdmull>;
1742 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
1744 // VMLA : Vector Multiply Accumulate (integer and floating-point)
1745 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
1746 IIC_VMACi16Q, IIC_VMACi32Q, "vmla.i", add>;
1747 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla.f32", v2f32, fmul, fadd>;
1748 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla.f32", v4f32, fmul, fadd>;
1749 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
1750 IIC_VMACi16Q, IIC_VMACi32Q, "vmla.i", add>;
1751 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla.f32", v2f32, fmul, fadd>;
1752 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla.f32", v4f32, v2f32, fmul, fadd>;
1754 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
1755 (mul (v8i16 QPR:$src2),
1756 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
1757 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1),
1759 (v4i16 (EXTRACT_SUBREG QPR:$src3,
1760 (DSubReg_i16_reg imm:$lane))),
1761 (SubReg_i16_lane imm:$lane)))>;
1763 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
1764 (mul (v4i32 QPR:$src2),
1765 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
1766 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1),
1768 (v2i32 (EXTRACT_SUBREG QPR:$src3,
1769 (DSubReg_i32_reg imm:$lane))),
1770 (SubReg_i32_lane imm:$lane)))>;
1772 def : Pat<(v4f32 (fadd (v4f32 QPR:$src1),
1773 (fmul (v4f32 QPR:$src2),
1774 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
1775 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
1777 (v2f32 (EXTRACT_SUBREG QPR:$src3,
1778 (DSubReg_i32_reg imm:$lane))),
1779 (SubReg_i32_lane imm:$lane)))>;
1781 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
1782 defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal.s", int_arm_neon_vmlals>;
1783 defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal.u", int_arm_neon_vmlalu>;
1785 defm VMLALsls : N3VLInt3SL_HS<0, 0b0010, "vmlal.s", int_arm_neon_vmlals>;
1786 defm VMLALslu : N3VLInt3SL_HS<1, 0b0010, "vmlal.u", int_arm_neon_vmlalu>;
1788 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
1789 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal.s", int_arm_neon_vqdmlal>;
1790 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal.s", int_arm_neon_vqdmlal>;
1792 // VMLS : Vector Multiply Subtract (integer and floating-point)
1793 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
1794 IIC_VMACi16Q, IIC_VMACi32Q, "vmls.i", sub>;
1795 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls.f32", v2f32, fmul, fsub>;
1796 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls.f32", v4f32, fmul, fsub>;
1797 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
1798 IIC_VMACi16Q, IIC_VMACi32Q, "vmls.i", sub>;
1799 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls.f32", v2f32, fmul, fsub>;
1800 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls.f32", v4f32, v2f32, fmul, fsub>;
1802 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
1803 (mul (v8i16 QPR:$src2),
1804 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
1805 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1),
1807 (v4i16 (EXTRACT_SUBREG QPR:$src3,
1808 (DSubReg_i16_reg imm:$lane))),
1809 (SubReg_i16_lane imm:$lane)))>;
1811 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
1812 (mul (v4i32 QPR:$src2),
1813 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
1814 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1),
1816 (v2i32 (EXTRACT_SUBREG QPR:$src3,
1817 (DSubReg_i32_reg imm:$lane))),
1818 (SubReg_i32_lane imm:$lane)))>;
1820 def : Pat<(v4f32 (fsub (v4f32 QPR:$src1),
1821 (fmul (v4f32 QPR:$src2),
1822 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
1823 (v4f32 (VMLSslfq (v4f32 QPR:$src1),
1825 (v2f32 (EXTRACT_SUBREG QPR:$src3,
1826 (DSubReg_i32_reg imm:$lane))),
1827 (SubReg_i32_lane imm:$lane)))>;
1829 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
1830 defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl.s", int_arm_neon_vmlsls>;
1831 defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl.u", int_arm_neon_vmlslu>;
1833 defm VMLSLsls : N3VLInt3SL_HS<0, 0b0110, "vmlsl.s", int_arm_neon_vmlsls>;
1834 defm VMLSLslu : N3VLInt3SL_HS<1, 0b0110, "vmlsl.u", int_arm_neon_vmlslu>;
1836 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
1837 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl.s", int_arm_neon_vqdmlsl>;
1838 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl.s", int_arm_neon_vqdmlsl>;
1840 // Vector Subtract Operations.
1842 // VSUB : Vector Subtract (integer and floating-point)
1843 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ, "vsub.i", sub, 0>;
1844 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub.f32", v2f32, v2f32, fsub, 0>;
1845 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub.f32", v4f32, v4f32, fsub, 0>;
1846 // VSUBL : Vector Subtract Long (Q = D - D)
1847 defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, IIC_VSHLiD, "vsubl.s", int_arm_neon_vsubls, 1>;
1848 defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, IIC_VSHLiD, "vsubl.u", int_arm_neon_vsublu, 1>;
1849 // VSUBW : Vector Subtract Wide (Q = Q - D)
1850 defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw.s", int_arm_neon_vsubws, 0>;
1851 defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw.u", int_arm_neon_vsubwu, 0>;
1852 // VHSUB : Vector Halving Subtract
1853 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1854 IIC_VBINi4Q, "vhsub.s", int_arm_neon_vhsubs, 0>;
1855 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1856 IIC_VBINi4Q, "vhsub.u", int_arm_neon_vhsubu, 0>;
1857 // VQSUB : Vector Saturing Subtract
1858 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1859 IIC_VBINi4Q, "vqsub.s", int_arm_neon_vqsubs, 0>;
1860 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1861 IIC_VBINi4Q, "vqsub.u", int_arm_neon_vqsubu, 0>;
1862 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
1863 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn.i", int_arm_neon_vsubhn, 0>;
1864 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
1865 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn.i", int_arm_neon_vrsubhn, 0>;
1867 // Vector Comparisons.
1869 // VCEQ : Vector Compare Equal
1870 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1871 IIC_VBINi4Q, "vceq.i", NEONvceq, 1>;
1872 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq.f32", v2i32, v2f32, NEONvceq, 1>;
1873 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq.f32", v4i32, v4f32, NEONvceq, 1>;
1874 // VCGE : Vector Compare Greater Than or Equal
1875 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1876 IIC_VBINi4Q, "vcge.s", NEONvcge, 0>;
1877 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1878 IIC_VBINi4Q, "vcge.u", NEONvcgeu, 0>;
1879 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge.f32", v2i32, v2f32, NEONvcge, 0>;
1880 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge.f32", v4i32, v4f32, NEONvcge, 0>;
1881 // VCGT : Vector Compare Greater Than
1882 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1883 IIC_VBINi4Q, "vcgt.s", NEONvcgt, 0>;
1884 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1885 IIC_VBINi4Q, "vcgt.u", NEONvcgtu, 0>;
1886 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt.f32", v2i32, v2f32, NEONvcgt, 0>;
1887 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt.f32", v4i32, v4f32, NEONvcgt, 0>;
1888 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
1889 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, IIC_VBIND, "vacge.f32", v2i32, v2f32,
1890 int_arm_neon_vacged, 0>;
1891 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, IIC_VBINQ, "vacge.f32", v4i32, v4f32,
1892 int_arm_neon_vacgeq, 0>;
1893 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
1894 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, IIC_VBIND, "vacgt.f32", v2i32, v2f32,
1895 int_arm_neon_vacgtd, 0>;
1896 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, IIC_VBINQ, "vacgt.f32", v4i32, v4f32,
1897 int_arm_neon_vacgtq, 0>;
1898 // VTST : Vector Test Bits
1899 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1900 IIC_VBINi4Q, "vtst.i", NEONvtst, 1>;
1902 // Vector Bitwise Operations.
1904 // VAND : Vector Bitwise AND
1905 def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand", v2i32, v2i32, and, 1>;
1906 def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand", v4i32, v4i32, and, 1>;
1908 // VEOR : Vector Bitwise Exclusive OR
1909 def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor", v2i32, v2i32, xor, 1>;
1910 def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor", v4i32, v4i32, xor, 1>;
1912 // VORR : Vector Bitwise OR
1913 def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr", v2i32, v2i32, or, 1>;
1914 def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr", v4i32, v4i32, or, 1>;
1916 // VBIC : Vector Bitwise Bit Clear (AND NOT)
1917 def VBICd : N3V<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1918 (ins DPR:$src1, DPR:$src2), IIC_VBINiD,
1919 "vbic\t$dst, $src1, $src2", "",
1920 [(set DPR:$dst, (v2i32 (and DPR:$src1,
1921 (vnot_conv DPR:$src2))))]>;
1922 def VBICq : N3V<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1923 (ins QPR:$src1, QPR:$src2), IIC_VBINiQ,
1924 "vbic\t$dst, $src1, $src2", "",
1925 [(set QPR:$dst, (v4i32 (and QPR:$src1,
1926 (vnot_conv QPR:$src2))))]>;
1928 // VORN : Vector Bitwise OR NOT
1929 def VORNd : N3V<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
1930 (ins DPR:$src1, DPR:$src2), IIC_VBINiD,
1931 "vorn\t$dst, $src1, $src2", "",
1932 [(set DPR:$dst, (v2i32 (or DPR:$src1,
1933 (vnot_conv DPR:$src2))))]>;
1934 def VORNq : N3V<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
1935 (ins QPR:$src1, QPR:$src2), IIC_VBINiQ,
1936 "vorn\t$dst, $src1, $src2", "",
1937 [(set QPR:$dst, (v4i32 (or QPR:$src1,
1938 (vnot_conv QPR:$src2))))]>;
1940 // VMVN : Vector Bitwise NOT
1941 def VMVNd : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
1942 (outs DPR:$dst), (ins DPR:$src), IIC_VSHLiD,
1943 "vmvn\t$dst, $src", "",
1944 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>;
1945 def VMVNq : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
1946 (outs QPR:$dst), (ins QPR:$src), IIC_VSHLiD,
1947 "vmvn\t$dst, $src", "",
1948 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>;
1949 def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>;
1950 def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>;
1952 // VBSL : Vector Bitwise Select
1953 def VBSLd : N3V<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1954 (ins DPR:$src1, DPR:$src2, DPR:$src3), IIC_VCNTiD,
1955 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1957 (v2i32 (or (and DPR:$src2, DPR:$src1),
1958 (and DPR:$src3, (vnot_conv DPR:$src1)))))]>;
1959 def VBSLq : N3V<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1960 (ins QPR:$src1, QPR:$src2, QPR:$src3), IIC_VCNTiQ,
1961 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1963 (v4i32 (or (and QPR:$src2, QPR:$src1),
1964 (and QPR:$src3, (vnot_conv QPR:$src1)))))]>;
1966 // VBIF : Vector Bitwise Insert if False
1967 // like VBSL but with: "vbif\t$dst, $src3, $src1", "$src2 = $dst",
1968 // VBIT : Vector Bitwise Insert if True
1969 // like VBSL but with: "vbit\t$dst, $src2, $src1", "$src3 = $dst",
1970 // These are not yet implemented. The TwoAddress pass will not go looking
1971 // for equivalent operations with different register constraints; it just
1974 // Vector Absolute Differences.
1976 // VABD : Vector Absolute Difference
1977 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1978 IIC_VBINi4Q, "vabd.s", int_arm_neon_vabds, 0>;
1979 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1980 IIC_VBINi4Q, "vabd.u", int_arm_neon_vabdu, 0>;
1981 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, IIC_VBIND, "vabd.f32", v2f32, v2f32,
1982 int_arm_neon_vabds, 0>;
1983 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vabd.f32", v4f32, v4f32,
1984 int_arm_neon_vabds, 0>;
1986 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
1987 defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, IIC_VBINi4Q, "vabdl.s", int_arm_neon_vabdls, 0>;
1988 defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, IIC_VBINi4Q, "vabdl.u", int_arm_neon_vabdlu, 0>;
1990 // VABA : Vector Absolute Difference and Accumulate
1991 defm VABAs : N3VInt3_QHS<0,0,0b0111,1, "vaba.s", int_arm_neon_vabas>;
1992 defm VABAu : N3VInt3_QHS<1,0,0b0111,1, "vaba.u", int_arm_neon_vabau>;
1994 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
1995 defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal.s", int_arm_neon_vabals>;
1996 defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal.u", int_arm_neon_vabalu>;
1998 // Vector Maximum and Minimum.
2000 // VMAX : Vector Maximum
2001 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2002 IIC_VBINi4Q, "vmax.s", int_arm_neon_vmaxs, 1>;
2003 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2004 IIC_VBINi4Q, "vmax.u", int_arm_neon_vmaxu, 1>;
2005 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, IIC_VBIND, "vmax.f32", v2f32, v2f32,
2006 int_arm_neon_vmaxs, 1>;
2007 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, IIC_VBINQ, "vmax.f32", v4f32, v4f32,
2008 int_arm_neon_vmaxs, 1>;
2010 // VMIN : Vector Minimum
2011 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2012 IIC_VBINi4Q, "vmin.s", int_arm_neon_vmins, 1>;
2013 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2014 IIC_VBINi4Q, "vmin.u", int_arm_neon_vminu, 1>;
2015 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, IIC_VBIND, "vmin.f32", v2f32, v2f32,
2016 int_arm_neon_vmins, 1>;
2017 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, IIC_VBINQ, "vmin.f32", v4f32, v4f32,
2018 int_arm_neon_vmins, 1>;
2020 // Vector Pairwise Operations.
2022 // VPADD : Vector Pairwise Add
2023 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, IIC_VBINiD, "vpadd.i8", v8i8, v8i8,
2024 int_arm_neon_vpadd, 0>;
2025 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, IIC_VBINiD, "vpadd.i16", v4i16, v4i16,
2026 int_arm_neon_vpadd, 0>;
2027 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, IIC_VBINiD, "vpadd.i32", v2i32, v2i32,
2028 int_arm_neon_vpadd, 0>;
2029 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, IIC_VBIND, "vpadd.f32", v2f32, v2f32,
2030 int_arm_neon_vpadd, 0>;
2032 // VPADDL : Vector Pairwise Add Long
2033 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl.s",
2034 int_arm_neon_vpaddls>;
2035 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl.u",
2036 int_arm_neon_vpaddlu>;
2038 // VPADAL : Vector Pairwise Add and Accumulate Long
2039 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal.s",
2040 int_arm_neon_vpadals>;
2041 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal.u",
2042 int_arm_neon_vpadalu>;
2044 // VPMAX : Vector Pairwise Maximum
2045 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax.s8", v8i8, v8i8,
2046 int_arm_neon_vpmaxs, 0>;
2047 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax.s16", v4i16, v4i16,
2048 int_arm_neon_vpmaxs, 0>;
2049 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax.s32", v2i32, v2i32,
2050 int_arm_neon_vpmaxs, 0>;
2051 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax.u8", v8i8, v8i8,
2052 int_arm_neon_vpmaxu, 0>;
2053 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax.u16", v4i16, v4i16,
2054 int_arm_neon_vpmaxu, 0>;
2055 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax.u32", v2i32, v2i32,
2056 int_arm_neon_vpmaxu, 0>;
2057 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, IIC_VBINi4D, "vpmax.f32", v2f32, v2f32,
2058 int_arm_neon_vpmaxs, 0>;
2060 // VPMIN : Vector Pairwise Minimum
2061 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin.s8", v8i8, v8i8,
2062 int_arm_neon_vpmins, 0>;
2063 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin.s16", v4i16, v4i16,
2064 int_arm_neon_vpmins, 0>;
2065 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin.s32", v2i32, v2i32,
2066 int_arm_neon_vpmins, 0>;
2067 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin.u8", v8i8, v8i8,
2068 int_arm_neon_vpminu, 0>;
2069 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin.u16", v4i16, v4i16,
2070 int_arm_neon_vpminu, 0>;
2071 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin.u32", v2i32, v2i32,
2072 int_arm_neon_vpminu, 0>;
2073 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, IIC_VBINi4D, "vpmin.f32", v2f32, v2f32,
2074 int_arm_neon_vpmins, 0>;
2076 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
2078 // VRECPE : Vector Reciprocal Estimate
2079 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
2080 IIC_VUNAD, "vrecpe.u32",
2081 v2i32, v2i32, int_arm_neon_vrecpe>;
2082 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
2083 IIC_VUNAQ, "vrecpe.u32",
2084 v4i32, v4i32, int_arm_neon_vrecpe>;
2085 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
2086 IIC_VUNAD, "vrecpe.f32",
2087 v2f32, v2f32, int_arm_neon_vrecpe>;
2088 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
2089 IIC_VUNAQ, "vrecpe.f32",
2090 v4f32, v4f32, int_arm_neon_vrecpe>;
2092 // VRECPS : Vector Reciprocal Step
2093 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, IIC_VRECSD, "vrecps.f32", v2f32, v2f32,
2094 int_arm_neon_vrecps, 1>;
2095 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, IIC_VRECSQ, "vrecps.f32", v4f32, v4f32,
2096 int_arm_neon_vrecps, 1>;
2098 // VRSQRTE : Vector Reciprocal Square Root Estimate
2099 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
2100 IIC_VUNAD, "vrsqrte.u32",
2101 v2i32, v2i32, int_arm_neon_vrsqrte>;
2102 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
2103 IIC_VUNAQ, "vrsqrte.u32",
2104 v4i32, v4i32, int_arm_neon_vrsqrte>;
2105 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
2106 IIC_VUNAD, "vrsqrte.f32",
2107 v2f32, v2f32, int_arm_neon_vrsqrte>;
2108 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
2109 IIC_VUNAQ, "vrsqrte.f32",
2110 v4f32, v4f32, int_arm_neon_vrsqrte>;
2112 // VRSQRTS : Vector Reciprocal Square Root Step
2113 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, IIC_VRECSD, "vrsqrts.f32", v2f32, v2f32,
2114 int_arm_neon_vrsqrts, 1>;
2115 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, IIC_VRECSQ, "vrsqrts.f32", v4f32, v4f32,
2116 int_arm_neon_vrsqrts, 1>;
2120 // VSHL : Vector Shift
2121 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
2122 IIC_VSHLiQ, "vshl.s", int_arm_neon_vshifts, 0>;
2123 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
2124 IIC_VSHLiQ, "vshl.u", int_arm_neon_vshiftu, 0>;
2125 // VSHL : Vector Shift Left (Immediate)
2126 defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl.i", NEONvshl>;
2127 // VSHR : Vector Shift Right (Immediate)
2128 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr.s", NEONvshrs>;
2129 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr.u", NEONvshru>;
2131 // VSHLL : Vector Shift Left Long
2132 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll.s", NEONvshlls>;
2133 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll.u", NEONvshllu>;
2135 // VSHLL : Vector Shift Left Long (with maximum shift count)
2136 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
2137 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
2138 ValueType OpTy, SDNode OpNode>
2139 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, ResTy, OpTy, OpNode> {
2140 let Inst{21-16} = op21_16;
2142 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll.i8",
2143 v8i16, v8i8, NEONvshlli>;
2144 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll.i16",
2145 v4i32, v4i16, NEONvshlli>;
2146 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll.i32",
2147 v2i64, v2i32, NEONvshlli>;
2149 // VSHRN : Vector Shift Right and Narrow
2150 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn.i", NEONvshrn>;
2152 // VRSHL : Vector Rounding Shift
2153 defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2154 IIC_VSHLi4Q, "vrshl.s", int_arm_neon_vrshifts, 0>;
2155 defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2156 IIC_VSHLi4Q, "vrshl.u", int_arm_neon_vrshiftu, 0>;
2157 // VRSHR : Vector Rounding Shift Right
2158 defm VRSHRs : N2VSh_QHSD<0, 1, 0b0010, 1, IIC_VSHLi4D, "vrshr.s", NEONvrshrs>;
2159 defm VRSHRu : N2VSh_QHSD<1, 1, 0b0010, 1, IIC_VSHLi4D, "vrshr.u", NEONvrshru>;
2161 // VRSHRN : Vector Rounding Shift Right and Narrow
2162 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn.i",
2165 // VQSHL : Vector Saturating Shift
2166 defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2167 IIC_VSHLi4Q, "vqshl.s", int_arm_neon_vqshifts, 0>;
2168 defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2169 IIC_VSHLi4Q, "vqshl.u", int_arm_neon_vqshiftu, 0>;
2170 // VQSHL : Vector Saturating Shift Left (Immediate)
2171 defm VQSHLsi : N2VSh_QHSD<0, 1, 0b0111, 1, IIC_VSHLi4D, "vqshl.s", NEONvqshls>;
2172 defm VQSHLui : N2VSh_QHSD<1, 1, 0b0111, 1, IIC_VSHLi4D, "vqshl.u", NEONvqshlu>;
2173 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
2174 defm VQSHLsu : N2VSh_QHSD<1, 1, 0b0110, 1, IIC_VSHLi4D, "vqshlu.s", NEONvqshlsu>;
2176 // VQSHRN : Vector Saturating Shift Right and Narrow
2177 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn.s",
2179 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn.u",
2182 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
2183 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun.s",
2186 // VQRSHL : Vector Saturating Rounding Shift
2187 defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2188 IIC_VSHLi4Q, "vqrshl.s", int_arm_neon_vqrshifts, 0>;
2189 defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2190 IIC_VSHLi4Q, "vqrshl.u", int_arm_neon_vqrshiftu, 0>;
2192 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
2193 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn.s",
2195 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn.u",
2198 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
2199 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun.s",
2202 // VSRA : Vector Shift Right and Accumulate
2203 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra.s", NEONvshrs>;
2204 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra.u", NEONvshru>;
2205 // VRSRA : Vector Rounding Shift Right and Accumulate
2206 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra.s", NEONvrshrs>;
2207 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra.u", NEONvrshru>;
2209 // VSLI : Vector Shift Left and Insert
2210 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli.", NEONvsli>;
2211 // VSRI : Vector Shift Right and Insert
2212 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri.", NEONvsri>;
2214 // Vector Absolute and Saturating Absolute.
2216 // VABS : Vector Absolute Value
2217 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
2218 IIC_VUNAiD, IIC_VUNAiQ, "vabs.s",
2220 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2221 IIC_VUNAD, "vabs.f32",
2222 v2f32, v2f32, int_arm_neon_vabs>;
2223 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2224 IIC_VUNAQ, "vabs.f32",
2225 v4f32, v4f32, int_arm_neon_vabs>;
2227 // VQABS : Vector Saturating Absolute Value
2228 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
2229 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs.s",
2230 int_arm_neon_vqabs>;
2234 def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
2235 def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>;
2237 class VNEGD<bits<2> size, string OpcodeStr, ValueType Ty>
2238 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
2239 IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "",
2240 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>;
2241 class VNEGQ<bits<2> size, string OpcodeStr, ValueType Ty>
2242 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
2243 IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "",
2244 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>;
2246 // VNEG : Vector Negate
2247 def VNEGs8d : VNEGD<0b00, "vneg.s8", v8i8>;
2248 def VNEGs16d : VNEGD<0b01, "vneg.s16", v4i16>;
2249 def VNEGs32d : VNEGD<0b10, "vneg.s32", v2i32>;
2250 def VNEGs8q : VNEGQ<0b00, "vneg.s8", v16i8>;
2251 def VNEGs16q : VNEGQ<0b01, "vneg.s16", v8i16>;
2252 def VNEGs32q : VNEGQ<0b10, "vneg.s32", v4i32>;
2254 // VNEG : Vector Negate (floating-point)
2255 def VNEGf32d : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
2256 (outs DPR:$dst), (ins DPR:$src), IIC_VUNAD,
2257 "vneg.f32\t$dst, $src", "",
2258 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
2259 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
2260 (outs QPR:$dst), (ins QPR:$src), IIC_VUNAQ,
2261 "vneg.f32\t$dst, $src", "",
2262 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
2264 def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
2265 def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
2266 def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>;
2267 def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>;
2268 def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>;
2269 def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>;
2271 // VQNEG : Vector Saturating Negate
2272 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
2273 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg.s",
2274 int_arm_neon_vqneg>;
2276 // Vector Bit Counting Operations.
2278 // VCLS : Vector Count Leading Sign Bits
2279 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
2280 IIC_VCNTiD, IIC_VCNTiQ, "vcls.s",
2282 // VCLZ : Vector Count Leading Zeros
2283 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
2284 IIC_VCNTiD, IIC_VCNTiQ, "vclz.i",
2286 // VCNT : Vector Count One Bits
2287 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2288 IIC_VCNTiD, "vcnt.8",
2289 v8i8, v8i8, int_arm_neon_vcnt>;
2290 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2291 IIC_VCNTiQ, "vcnt.8",
2292 v16i8, v16i8, int_arm_neon_vcnt>;
2294 // Vector Move Operations.
2296 // VMOV : Vector Move (Register)
2298 def VMOVD : N3V<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
2299 IIC_VMOVD, "vmov\t$dst, $src", "", []>;
2300 def VMOVQ : N3V<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
2301 IIC_VMOVD, "vmov\t$dst, $src", "", []>;
2303 // VMOV : Vector Move (Immediate)
2305 // VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
2306 def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
2307 return ARM::getVMOVImm(N, 1, *CurDAG);
2309 def vmovImm8 : PatLeaf<(build_vector), [{
2310 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
2313 // VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
2314 def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
2315 return ARM::getVMOVImm(N, 2, *CurDAG);
2317 def vmovImm16 : PatLeaf<(build_vector), [{
2318 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
2319 }], VMOV_get_imm16>;
2321 // VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
2322 def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
2323 return ARM::getVMOVImm(N, 4, *CurDAG);
2325 def vmovImm32 : PatLeaf<(build_vector), [{
2326 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
2327 }], VMOV_get_imm32>;
2329 // VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
2330 def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
2331 return ARM::getVMOVImm(N, 8, *CurDAG);
2333 def vmovImm64 : PatLeaf<(build_vector), [{
2334 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
2335 }], VMOV_get_imm64>;
2337 // Note: Some of the cmode bits in the following VMOV instructions need to
2338 // be encoded based on the immed values.
2340 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
2341 (ins h8imm:$SIMM), IIC_VMOVImm,
2342 "vmov.i8\t$dst, $SIMM", "",
2343 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
2344 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
2345 (ins h8imm:$SIMM), IIC_VMOVImm,
2346 "vmov.i8\t$dst, $SIMM", "",
2347 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
2349 def VMOVv4i16 : N1ModImm<1, 0b000, 0b1000, 0, 0, 0, 1, (outs DPR:$dst),
2350 (ins h16imm:$SIMM), IIC_VMOVImm,
2351 "vmov.i16\t$dst, $SIMM", "",
2352 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
2353 def VMOVv8i16 : N1ModImm<1, 0b000, 0b1000, 0, 1, 0, 1, (outs QPR:$dst),
2354 (ins h16imm:$SIMM), IIC_VMOVImm,
2355 "vmov.i16\t$dst, $SIMM", "",
2356 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
2358 def VMOVv2i32 : N1ModImm<1, 0b000, 0b0000, 0, 0, 0, 1, (outs DPR:$dst),
2359 (ins h32imm:$SIMM), IIC_VMOVImm,
2360 "vmov.i32\t$dst, $SIMM", "",
2361 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
2362 def VMOVv4i32 : N1ModImm<1, 0b000, 0b0000, 0, 1, 0, 1, (outs QPR:$dst),
2363 (ins h32imm:$SIMM), IIC_VMOVImm,
2364 "vmov.i32\t$dst, $SIMM", "",
2365 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
2367 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
2368 (ins h64imm:$SIMM), IIC_VMOVImm,
2369 "vmov.i64\t$dst, $SIMM", "",
2370 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
2371 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
2372 (ins h64imm:$SIMM), IIC_VMOVImm,
2373 "vmov.i64\t$dst, $SIMM", "",
2374 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
2376 // VMOV : Vector Get Lane (move scalar to ARM core register)
2378 def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00,
2379 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2380 IIC_VMOVSI, "vmov", ".s8\t$dst, $src[$lane]",
2381 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
2383 def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01,
2384 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2385 IIC_VMOVSI, "vmov", ".s16\t$dst, $src[$lane]",
2386 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
2388 def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00,
2389 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2390 IIC_VMOVSI, "vmov", ".u8\t$dst, $src[$lane]",
2391 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
2393 def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01,
2394 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2395 IIC_VMOVSI, "vmov", ".u16\t$dst, $src[$lane]",
2396 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
2398 def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00,
2399 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2400 IIC_VMOVSI, "vmov", ".32\t$dst, $src[$lane]",
2401 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
2403 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
2404 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
2405 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2406 (DSubReg_i8_reg imm:$lane))),
2407 (SubReg_i8_lane imm:$lane))>;
2408 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
2409 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2410 (DSubReg_i16_reg imm:$lane))),
2411 (SubReg_i16_lane imm:$lane))>;
2412 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
2413 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2414 (DSubReg_i8_reg imm:$lane))),
2415 (SubReg_i8_lane imm:$lane))>;
2416 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
2417 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2418 (DSubReg_i16_reg imm:$lane))),
2419 (SubReg_i16_lane imm:$lane))>;
2420 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
2421 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
2422 (DSubReg_i32_reg imm:$lane))),
2423 (SubReg_i32_lane imm:$lane))>;
2424 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
2425 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1), DPR_VFP2)),
2426 (SSubReg_f32_reg imm:$src2))>;
2427 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
2428 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1), QPR_VFP2)),
2429 (SSubReg_f32_reg imm:$src2))>;
2430 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
2431 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2432 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
2433 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2436 // VMOV : Vector Set Lane (move ARM core register to scalar)
2438 let Constraints = "$src1 = $dst" in {
2439 def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst),
2440 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2441 IIC_VMOVISL, "vmov", ".8\t$dst[$lane], $src2",
2442 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
2443 GPR:$src2, imm:$lane))]>;
2444 def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst),
2445 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2446 IIC_VMOVISL, "vmov", ".16\t$dst[$lane], $src2",
2447 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
2448 GPR:$src2, imm:$lane))]>;
2449 def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst),
2450 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2451 IIC_VMOVISL, "vmov", ".32\t$dst[$lane], $src2",
2452 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
2453 GPR:$src2, imm:$lane))]>;
2455 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
2456 (v16i8 (INSERT_SUBREG QPR:$src1,
2457 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
2458 (DSubReg_i8_reg imm:$lane))),
2459 GPR:$src2, (SubReg_i8_lane imm:$lane)),
2460 (DSubReg_i8_reg imm:$lane)))>;
2461 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
2462 (v8i16 (INSERT_SUBREG QPR:$src1,
2463 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
2464 (DSubReg_i16_reg imm:$lane))),
2465 GPR:$src2, (SubReg_i16_lane imm:$lane)),
2466 (DSubReg_i16_reg imm:$lane)))>;
2467 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
2468 (v4i32 (INSERT_SUBREG QPR:$src1,
2469 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
2470 (DSubReg_i32_reg imm:$lane))),
2471 GPR:$src2, (SubReg_i32_lane imm:$lane)),
2472 (DSubReg_i32_reg imm:$lane)))>;
2474 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
2475 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
2476 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
2477 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
2478 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
2479 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
2481 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
2482 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
2483 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
2484 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
2486 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
2487 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
2488 def : Pat<(v2f64 (scalar_to_vector DPR:$src)),
2489 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, arm_dsubreg_0)>;
2490 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
2491 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
2493 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
2494 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2495 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
2496 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2497 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
2498 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2500 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
2501 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
2502 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2504 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
2505 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
2506 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2508 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
2509 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
2510 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2513 // VDUP : Vector Duplicate (from ARM core register to all elements)
2515 class VDUPD<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
2516 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
2517 IIC_VMOVIS, "vdup", !strconcat(asmSize, "\t$dst, $src"),
2518 [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
2519 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
2520 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
2521 IIC_VMOVIS, "vdup", !strconcat(asmSize, "\t$dst, $src"),
2522 [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
2524 def VDUP8d : VDUPD<0b11101100, 0b00, ".8", v8i8>;
2525 def VDUP16d : VDUPD<0b11101000, 0b01, ".16", v4i16>;
2526 def VDUP32d : VDUPD<0b11101000, 0b00, ".32", v2i32>;
2527 def VDUP8q : VDUPQ<0b11101110, 0b00, ".8", v16i8>;
2528 def VDUP16q : VDUPQ<0b11101010, 0b01, ".16", v8i16>;
2529 def VDUP32q : VDUPQ<0b11101010, 0b00, ".32", v4i32>;
2531 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
2532 IIC_VMOVIS, "vdup", ".32\t$dst, $src",
2533 [(set DPR:$dst, (v2f32 (NEONvdup
2534 (f32 (bitconvert GPR:$src)))))]>;
2535 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
2536 IIC_VMOVIS, "vdup", ".32\t$dst, $src",
2537 [(set QPR:$dst, (v4f32 (NEONvdup
2538 (f32 (bitconvert GPR:$src)))))]>;
2540 // VDUP : Vector Duplicate Lane (from scalar to all elements)
2542 class VDUPLND<string OpcodeStr, ValueType Ty>
2543 : N2VDup<0b11, 0b11, 0b11000, 0, 0,
2544 (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
2545 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
2546 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
2548 class VDUPLNQ<string OpcodeStr, ValueType ResTy, ValueType OpTy>
2549 : N2VDup<0b11, 0b11, 0b11000, 1, 0,
2550 (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
2551 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
2552 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src), imm:$lane)))]>;
2554 // Inst{19-16} is partially specified depending on the element size.
2556 def VDUPLN8d : VDUPLND<"vdup.8", v8i8> { let Inst{16} = 1; }
2557 def VDUPLN16d : VDUPLND<"vdup.16", v4i16> { let Inst{17-16} = 0b10; }
2558 def VDUPLN32d : VDUPLND<"vdup.32", v2i32> { let Inst{18-16} = 0b100; }
2559 def VDUPLNfd : VDUPLND<"vdup.32", v2f32> { let Inst{18-16} = 0b100; }
2560 def VDUPLN8q : VDUPLNQ<"vdup.8", v16i8, v8i8> { let Inst{16} = 1; }
2561 def VDUPLN16q : VDUPLNQ<"vdup.16", v8i16, v4i16> { let Inst{17-16} = 0b10; }
2562 def VDUPLN32q : VDUPLNQ<"vdup.32", v4i32, v2i32> { let Inst{18-16} = 0b100; }
2563 def VDUPLNfq : VDUPLNQ<"vdup.32", v4f32, v2f32> { let Inst{18-16} = 0b100; }
2565 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
2566 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
2567 (DSubReg_i8_reg imm:$lane))),
2568 (SubReg_i8_lane imm:$lane)))>;
2569 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
2570 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
2571 (DSubReg_i16_reg imm:$lane))),
2572 (SubReg_i16_lane imm:$lane)))>;
2573 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
2574 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
2575 (DSubReg_i32_reg imm:$lane))),
2576 (SubReg_i32_lane imm:$lane)))>;
2577 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
2578 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
2579 (DSubReg_i32_reg imm:$lane))),
2580 (SubReg_i32_lane imm:$lane)))>;
2582 def VDUPfdf : N2VDup<0b11, 0b11, 0b11000, 0, 0,
2583 (outs DPR:$dst), (ins SPR:$src),
2584 IIC_VMOVD, "vdup.32\t$dst, ${src:lane}", "",
2585 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]> {
2586 let Inst{18-16} = 0b100;
2589 def VDUPfqf : N2VDup<0b11, 0b11, 0b11000, 1, 0,
2590 (outs QPR:$dst), (ins SPR:$src),
2591 IIC_VMOVD, "vdup.32\t$dst, ${src:lane}", "",
2592 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]> {
2593 let Inst{18-16} = 0b100;
2596 def : Pat<(v2i64 (NEONvduplane (v2i64 QPR:$src), imm:$lane)),
2597 (INSERT_SUBREG QPR:$src,
2598 (i64 (EXTRACT_SUBREG QPR:$src, (DSubReg_f64_reg imm:$lane))),
2599 (DSubReg_f64_other_reg imm:$lane))>;
2600 def : Pat<(v2f64 (NEONvduplane (v2f64 QPR:$src), imm:$lane)),
2601 (INSERT_SUBREG QPR:$src,
2602 (f64 (EXTRACT_SUBREG QPR:$src, (DSubReg_f64_reg imm:$lane))),
2603 (DSubReg_f64_other_reg imm:$lane))>;
2605 // VMOVN : Vector Narrowing Move
2606 defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVD, "vmovn.i",
2607 int_arm_neon_vmovn>;
2608 // VQMOVN : Vector Saturating Narrowing Move
2609 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD, "vqmovn.s",
2610 int_arm_neon_vqmovns>;
2611 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD, "vqmovn.u",
2612 int_arm_neon_vqmovnu>;
2613 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD, "vqmovun.s",
2614 int_arm_neon_vqmovnsu>;
2615 // VMOVL : Vector Lengthening Move
2616 defm VMOVLs : N2VLInt_QHS<0b01,0b10100,0,1, "vmovl.s", int_arm_neon_vmovls>;
2617 defm VMOVLu : N2VLInt_QHS<0b11,0b10100,0,1, "vmovl.u", int_arm_neon_vmovlu>;
2619 // Vector Conversions.
2621 // VCVT : Vector Convert Between Floating-Point and Integers
2622 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
2623 v2i32, v2f32, fp_to_sint>;
2624 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
2625 v2i32, v2f32, fp_to_uint>;
2626 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
2627 v2f32, v2i32, sint_to_fp>;
2628 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
2629 v2f32, v2i32, uint_to_fp>;
2631 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
2632 v4i32, v4f32, fp_to_sint>;
2633 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
2634 v4i32, v4f32, fp_to_uint>;
2635 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
2636 v4f32, v4i32, sint_to_fp>;
2637 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
2638 v4f32, v4i32, uint_to_fp>;
2640 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
2641 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt.s32.f32",
2642 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
2643 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt.u32.f32",
2644 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
2645 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt.f32.s32",
2646 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
2647 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt.f32.u32",
2648 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
2650 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt.s32.f32",
2651 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
2652 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt.u32.f32",
2653 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
2654 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt.f32.s32",
2655 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
2656 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt.f32.u32",
2657 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
2661 // VREV64 : Vector Reverse elements within 64-bit doublewords
2663 class VREV64D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2664 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
2665 (ins DPR:$src), IIC_VMOVD,
2666 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2667 [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
2668 class VREV64Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2669 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
2670 (ins QPR:$src), IIC_VMOVD,
2671 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2672 [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
2674 def VREV64d8 : VREV64D<0b00, "vrev64.8", v8i8>;
2675 def VREV64d16 : VREV64D<0b01, "vrev64.16", v4i16>;
2676 def VREV64d32 : VREV64D<0b10, "vrev64.32", v2i32>;
2677 def VREV64df : VREV64D<0b10, "vrev64.32", v2f32>;
2679 def VREV64q8 : VREV64Q<0b00, "vrev64.8", v16i8>;
2680 def VREV64q16 : VREV64Q<0b01, "vrev64.16", v8i16>;
2681 def VREV64q32 : VREV64Q<0b10, "vrev64.32", v4i32>;
2682 def VREV64qf : VREV64Q<0b10, "vrev64.32", v4f32>;
2684 // VREV32 : Vector Reverse elements within 32-bit words
2686 class VREV32D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2687 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
2688 (ins DPR:$src), IIC_VMOVD,
2689 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2690 [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
2691 class VREV32Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2692 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
2693 (ins QPR:$src), IIC_VMOVD,
2694 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2695 [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
2697 def VREV32d8 : VREV32D<0b00, "vrev32.8", v8i8>;
2698 def VREV32d16 : VREV32D<0b01, "vrev32.16", v4i16>;
2700 def VREV32q8 : VREV32Q<0b00, "vrev32.8", v16i8>;
2701 def VREV32q16 : VREV32Q<0b01, "vrev32.16", v8i16>;
2703 // VREV16 : Vector Reverse elements within 16-bit halfwords
2705 class VREV16D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2706 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
2707 (ins DPR:$src), IIC_VMOVD,
2708 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2709 [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
2710 class VREV16Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2711 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
2712 (ins QPR:$src), IIC_VMOVD,
2713 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2714 [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
2716 def VREV16d8 : VREV16D<0b00, "vrev16.8", v8i8>;
2717 def VREV16q8 : VREV16Q<0b00, "vrev16.8", v16i8>;
2719 // Other Vector Shuffles.
2721 // VEXT : Vector Extract
2723 class VEXTd<string OpcodeStr, ValueType Ty>
2724 : N3VImm<0,1,0b11,0,0, (outs DPR:$dst),
2725 (ins DPR:$lhs, DPR:$rhs, i32imm:$index), IIC_VEXTD,
2726 !strconcat(OpcodeStr, "\t$dst, $lhs, $rhs, $index"), "",
2727 [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
2728 (Ty DPR:$rhs), imm:$index)))]>;
2730 class VEXTq<string OpcodeStr, ValueType Ty>
2731 : N3VImm<0,1,0b11,1,0, (outs QPR:$dst),
2732 (ins QPR:$lhs, QPR:$rhs, i32imm:$index), IIC_VEXTQ,
2733 !strconcat(OpcodeStr, "\t$dst, $lhs, $rhs, $index"), "",
2734 [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
2735 (Ty QPR:$rhs), imm:$index)))]>;
2737 def VEXTd8 : VEXTd<"vext.8", v8i8>;
2738 def VEXTd16 : VEXTd<"vext.16", v4i16>;
2739 def VEXTd32 : VEXTd<"vext.32", v2i32>;
2740 def VEXTdf : VEXTd<"vext.32", v2f32>;
2742 def VEXTq8 : VEXTq<"vext.8", v16i8>;
2743 def VEXTq16 : VEXTq<"vext.16", v8i16>;
2744 def VEXTq32 : VEXTq<"vext.32", v4i32>;
2745 def VEXTqf : VEXTq<"vext.32", v4f32>;
2747 // VTRN : Vector Transpose
2749 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn.8">;
2750 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn.16">;
2751 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn.32">;
2753 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn.8">;
2754 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn.16">;
2755 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn.32">;
2757 // VUZP : Vector Unzip (Deinterleave)
2759 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp.8">;
2760 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp.16">;
2761 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp.32">;
2763 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp.8">;
2764 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp.16">;
2765 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp.32">;
2767 // VZIP : Vector Zip (Interleave)
2769 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip.8">;
2770 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip.16">;
2771 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip.32">;
2773 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip.8">;
2774 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip.16">;
2775 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip.32">;
2777 // Vector Table Lookup and Table Extension.
2779 // VTBL : Vector Table Lookup
2781 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
2782 (ins DPR:$tbl1, DPR:$src), IIC_VTB1,
2783 "vtbl.8\t$dst, \\{$tbl1\\}, $src", "",
2784 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
2785 let hasExtraSrcRegAllocReq = 1 in {
2787 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
2788 (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTB2,
2789 "vtbl.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "",
2790 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl2
2791 DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
2793 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
2794 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTB3,
2795 "vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "",
2796 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl3
2797 DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
2799 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
2800 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTB4,
2801 "vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "",
2802 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl4 DPR:$tbl1, DPR:$tbl2,
2803 DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
2804 } // hasExtraSrcRegAllocReq = 1
2806 // VTBX : Vector Table Extension
2808 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
2809 (ins DPR:$orig, DPR:$tbl1, DPR:$src), IIC_VTBX1,
2810 "vtbx.8\t$dst, \\{$tbl1\\}, $src", "$orig = $dst",
2811 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
2812 DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
2813 let hasExtraSrcRegAllocReq = 1 in {
2815 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
2816 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTBX2,
2817 "vtbx.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "$orig = $dst",
2818 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx2
2819 DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
2821 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
2822 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTBX3,
2823 "vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "$orig = $dst",
2824 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx3 DPR:$orig, DPR:$tbl1,
2825 DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
2827 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
2828 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTBX4,
2829 "vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "$orig = $dst",
2830 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx4 DPR:$orig, DPR:$tbl1,
2831 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
2832 } // hasExtraSrcRegAllocReq = 1
2834 //===----------------------------------------------------------------------===//
2835 // NEON instructions for single-precision FP math
2836 //===----------------------------------------------------------------------===//
2838 // These need separate instructions because they must use DPR_VFP2 register
2839 // class which have SPR sub-registers.
2841 // Vector Add Operations used for single-precision FP
2842 let neverHasSideEffects = 1 in
2843 def VADDfd_sfp : N3VDs<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd,1>;
2844 def : N3VDsPat<fadd, VADDfd_sfp>;
2846 // Vector Sub Operations used for single-precision FP
2847 let neverHasSideEffects = 1 in
2848 def VSUBfd_sfp : N3VDs<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub,0>;
2849 def : N3VDsPat<fsub, VSUBfd_sfp>;
2851 // Vector Multiply Operations used for single-precision FP
2852 let neverHasSideEffects = 1 in
2853 def VMULfd_sfp : N3VDs<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul,1>;
2854 def : N3VDsPat<fmul, VMULfd_sfp>;
2856 // Vector Multiply-Accumulate/Subtract used for single-precision FP
2857 // vml[as].f32 can cause 4-8 cycle stalls in following ASIMD instructions, so
2858 // we want to avoid them for now. e.g., alternating vmla/vadd instructions.
2860 //let neverHasSideEffects = 1 in
2861 //def VMLAfd_sfp : N3VDMulOps<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla.f32", v2f32,fmul,fadd>;
2862 //def : N3VDMulOpsPat<fmul, fadd, VMLAfd_sfp>;
2864 //let neverHasSideEffects = 1 in
2865 //def VMLSfd_sfp : N3VDMulOps<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls.f32", v2f32,fmul,fsub>;
2866 //def : N3VDMulOpsPat<fmul, fsub, VMLSfd_sfp>;
2868 // Vector Absolute used for single-precision FP
2869 let neverHasSideEffects = 1 in
2870 def VABSfd_sfp : N2VDInts<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2871 IIC_VUNAD, "vabs.f32",
2872 v2f32, v2f32, int_arm_neon_vabs>;
2873 def : N2VDIntsPat<fabs, VABSfd_sfp>;
2875 // Vector Negate used for single-precision FP
2876 let neverHasSideEffects = 1 in
2877 def VNEGf32d_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
2878 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
2879 "vneg.f32\t$dst, $src", "", []>;
2880 def : N2VDIntsPat<fneg, VNEGf32d_sfp>;
2882 // Vector Convert between single-precision FP and integer
2883 let neverHasSideEffects = 1 in
2884 def VCVTf2sd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
2885 v2i32, v2f32, fp_to_sint>;
2886 def : N2VDsPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
2888 let neverHasSideEffects = 1 in
2889 def VCVTf2ud_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
2890 v2i32, v2f32, fp_to_uint>;
2891 def : N2VDsPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
2893 let neverHasSideEffects = 1 in
2894 def VCVTs2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
2895 v2f32, v2i32, sint_to_fp>;
2896 def : N2VDsPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
2898 let neverHasSideEffects = 1 in
2899 def VCVTu2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
2900 v2f32, v2i32, uint_to_fp>;
2901 def : N2VDsPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
2903 //===----------------------------------------------------------------------===//
2904 // Non-Instruction Patterns
2905 //===----------------------------------------------------------------------===//
2908 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
2909 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
2910 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
2911 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
2912 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
2913 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
2914 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
2915 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
2916 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
2917 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
2918 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
2919 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
2920 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
2921 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
2922 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
2923 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
2924 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
2925 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
2926 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
2927 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
2928 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
2929 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
2930 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
2931 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
2932 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
2933 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
2934 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
2935 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
2936 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
2937 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
2939 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
2940 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
2941 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
2942 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
2943 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
2944 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
2945 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
2946 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
2947 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
2948 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
2949 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
2950 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
2951 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
2952 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
2953 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
2954 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
2955 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
2956 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
2957 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
2958 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
2959 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
2960 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
2961 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
2962 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
2963 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
2964 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
2965 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
2966 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
2967 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
2968 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;