1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
19 def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
21 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
22 def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
23 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
24 def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
25 def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
26 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
27 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
28 def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
29 def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
30 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
31 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
33 // Types for vector shift by immediates. The "SHX" version is for long and
34 // narrow operations where the source and destination vectors have different
35 // types. The "SHINS" version is for shift and insert operations.
36 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
38 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
40 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
43 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
44 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
45 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
46 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
47 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
48 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
49 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
51 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
52 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
53 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
55 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
56 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
57 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
58 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
59 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
60 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
62 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
63 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
64 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
66 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
67 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
69 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
71 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
72 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
74 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
75 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
76 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
78 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
80 def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
81 def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
83 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
85 // VDUPLANE can produce a quad-register result from a double-register source,
86 // so the result is not constrained to match the source.
87 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
88 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
91 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
92 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
93 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
95 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
96 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
97 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
98 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
100 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
102 SDTCisSameAs<0, 3>]>;
103 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
104 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
105 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
107 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
108 SDTCisSameAs<1, 2>]>;
109 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
110 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
112 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
113 SDTCisSameAs<0, 2>]>;
114 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
115 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
117 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
118 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
119 unsigned EltBits = 0;
120 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
121 return (EltBits == 32 && EltVal == 0);
124 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
125 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
126 unsigned EltBits = 0;
127 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
128 return (EltBits == 8 && EltVal == 0xff);
131 //===----------------------------------------------------------------------===//
132 // NEON operand definitions
133 //===----------------------------------------------------------------------===//
135 def nModImm : Operand<i32> {
136 let PrintMethod = "printNEONModImmOperand";
139 //===----------------------------------------------------------------------===//
140 // NEON load / store instructions
141 //===----------------------------------------------------------------------===//
143 // Use VLDM to load a Q register as a D register pair.
144 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
146 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
148 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
150 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
152 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
154 // Use VSTM to store a Q register as a D register pair.
155 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
157 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
159 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
161 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
163 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
165 // Classes for VLD* pseudo-instructions with multi-register operands.
166 // These are expanded to real instructions after register allocation.
167 class VLDQPseudo<InstrItinClass itin>
168 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
169 class VLDQWBPseudo<InstrItinClass itin>
170 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
171 (ins addrmode6:$addr, am6offset:$offset), itin,
173 class VLDQQPseudo<InstrItinClass itin>
174 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
175 class VLDQQWBPseudo<InstrItinClass itin>
176 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
177 (ins addrmode6:$addr, am6offset:$offset), itin,
179 class VLDQQQQPseudo<InstrItinClass itin>
180 : PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src), itin,"">;
181 class VLDQQQQWBPseudo<InstrItinClass itin>
182 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
183 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
184 "$addr.addr = $wb, $src = $dst">;
186 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
188 // VLD1 : Vector Load (multiple single elements)
189 class VLD1D<bits<4> op7_4, string Dt>
190 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd),
191 (ins addrmode6:$Rn), IIC_VLD1,
192 "vld1", Dt, "\\{$Vd\\}, $Rn", "", []> {
196 class VLD1Q<bits<4> op7_4, string Dt>
197 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2),
198 (ins addrmode6:$Rn), IIC_VLD1x2,
199 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
201 let Inst{5-4} = Rn{5-4};
204 def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
205 def VLD1d16 : VLD1D<{0,1,0,?}, "16">;
206 def VLD1d32 : VLD1D<{1,0,0,?}, "32">;
207 def VLD1d64 : VLD1D<{1,1,0,?}, "64">;
209 def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;
210 def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
211 def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
212 def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
214 def VLD1q8Pseudo : VLDQPseudo<IIC_VLD1x2>;
215 def VLD1q16Pseudo : VLDQPseudo<IIC_VLD1x2>;
216 def VLD1q32Pseudo : VLDQPseudo<IIC_VLD1x2>;
217 def VLD1q64Pseudo : VLDQPseudo<IIC_VLD1x2>;
219 // ...with address register writeback:
220 class VLD1DWB<bits<4> op7_4, string Dt>
221 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd, GPR:$wb),
222 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1u,
223 "vld1", Dt, "\\{$Vd\\}, $Rn$Rm",
224 "$Rn.addr = $wb", []> {
227 class VLD1QWB<bits<4> op7_4, string Dt>
228 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
229 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x2u,
230 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
231 "$Rn.addr = $wb", []> {
232 let Inst{5-4} = Rn{5-4};
235 def VLD1d8_UPD : VLD1DWB<{0,0,0,?}, "8">;
236 def VLD1d16_UPD : VLD1DWB<{0,1,0,?}, "16">;
237 def VLD1d32_UPD : VLD1DWB<{1,0,0,?}, "32">;
238 def VLD1d64_UPD : VLD1DWB<{1,1,0,?}, "64">;
240 def VLD1q8_UPD : VLD1QWB<{0,0,?,?}, "8">;
241 def VLD1q16_UPD : VLD1QWB<{0,1,?,?}, "16">;
242 def VLD1q32_UPD : VLD1QWB<{1,0,?,?}, "32">;
243 def VLD1q64_UPD : VLD1QWB<{1,1,?,?}, "64">;
245 def VLD1q8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
246 def VLD1q16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
247 def VLD1q32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
248 def VLD1q64Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
250 // ...with 3 registers (some of these are only for the disassembler):
251 class VLD1D3<bits<4> op7_4, string Dt>
252 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
253 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
254 "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
258 class VLD1D3WB<bits<4> op7_4, string Dt>
259 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
260 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x3u, "vld1", Dt,
261 "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
265 def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
266 def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;
267 def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;
268 def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;
270 def VLD1d8T_UPD : VLD1D3WB<{0,0,0,?}, "8">;
271 def VLD1d16T_UPD : VLD1D3WB<{0,1,0,?}, "16">;
272 def VLD1d32T_UPD : VLD1D3WB<{1,0,0,?}, "32">;
273 def VLD1d64T_UPD : VLD1D3WB<{1,1,0,?}, "64">;
275 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
276 def VLD1d64TPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x3u>;
278 // ...with 4 registers (some of these are only for the disassembler):
279 class VLD1D4<bits<4> op7_4, string Dt>
280 : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
281 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
282 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
284 let Inst{5-4} = Rn{5-4};
286 class VLD1D4WB<bits<4> op7_4, string Dt>
287 : NLdSt<0,0b10,0b0010,op7_4,
288 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
289 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x4u, "vld1", Dt,
290 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", "$Rn.addr = $wb",
292 let Inst{5-4} = Rn{5-4};
295 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
296 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;
297 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;
298 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;
300 def VLD1d8Q_UPD : VLD1D4WB<{0,0,?,?}, "8">;
301 def VLD1d16Q_UPD : VLD1D4WB<{0,1,?,?}, "16">;
302 def VLD1d32Q_UPD : VLD1D4WB<{1,0,?,?}, "32">;
303 def VLD1d64Q_UPD : VLD1D4WB<{1,1,?,?}, "64">;
305 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
306 def VLD1d64QPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x4u>;
308 // VLD2 : Vector Load (multiple 2-element structures)
309 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
310 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
311 (ins addrmode6:$Rn), IIC_VLD2,
312 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
314 let Inst{5-4} = Rn{5-4};
316 class VLD2Q<bits<4> op7_4, string Dt>
317 : NLdSt<0, 0b10, 0b0011, op7_4,
318 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
319 (ins addrmode6:$Rn), IIC_VLD2x2,
320 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
322 let Inst{5-4} = Rn{5-4};
325 def VLD2d8 : VLD2D<0b1000, {0,0,?,?}, "8">;
326 def VLD2d16 : VLD2D<0b1000, {0,1,?,?}, "16">;
327 def VLD2d32 : VLD2D<0b1000, {1,0,?,?}, "32">;
329 def VLD2q8 : VLD2Q<{0,0,?,?}, "8">;
330 def VLD2q16 : VLD2Q<{0,1,?,?}, "16">;
331 def VLD2q32 : VLD2Q<{1,0,?,?}, "32">;
333 def VLD2d8Pseudo : VLDQPseudo<IIC_VLD2>;
334 def VLD2d16Pseudo : VLDQPseudo<IIC_VLD2>;
335 def VLD2d32Pseudo : VLDQPseudo<IIC_VLD2>;
337 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
338 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
339 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
341 // ...with address register writeback:
342 class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
343 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
344 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2u,
345 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
346 "$Rn.addr = $wb", []> {
347 let Inst{5-4} = Rn{5-4};
349 class VLD2QWB<bits<4> op7_4, string Dt>
350 : NLdSt<0, 0b10, 0b0011, op7_4,
351 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
352 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2x2u,
353 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
354 "$Rn.addr = $wb", []> {
355 let Inst{5-4} = Rn{5-4};
358 def VLD2d8_UPD : VLD2DWB<0b1000, {0,0,?,?}, "8">;
359 def VLD2d16_UPD : VLD2DWB<0b1000, {0,1,?,?}, "16">;
360 def VLD2d32_UPD : VLD2DWB<0b1000, {1,0,?,?}, "32">;
362 def VLD2q8_UPD : VLD2QWB<{0,0,?,?}, "8">;
363 def VLD2q16_UPD : VLD2QWB<{0,1,?,?}, "16">;
364 def VLD2q32_UPD : VLD2QWB<{1,0,?,?}, "32">;
366 def VLD2d8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
367 def VLD2d16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
368 def VLD2d32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
370 def VLD2q8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
371 def VLD2q16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
372 def VLD2q32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
374 // ...with double-spaced registers (for disassembly only):
375 def VLD2b8 : VLD2D<0b1001, {0,0,?,?}, "8">;
376 def VLD2b16 : VLD2D<0b1001, {0,1,?,?}, "16">;
377 def VLD2b32 : VLD2D<0b1001, {1,0,?,?}, "32">;
378 def VLD2b8_UPD : VLD2DWB<0b1001, {0,0,?,?}, "8">;
379 def VLD2b16_UPD : VLD2DWB<0b1001, {0,1,?,?}, "16">;
380 def VLD2b32_UPD : VLD2DWB<0b1001, {1,0,?,?}, "32">;
382 // VLD3 : Vector Load (multiple 3-element structures)
383 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
384 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
385 (ins addrmode6:$Rn), IIC_VLD3,
386 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
391 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
392 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
393 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
395 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
396 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
397 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
399 // ...with address register writeback:
400 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
401 : NLdSt<0, 0b10, op11_8, op7_4,
402 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
403 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
404 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
405 "$Rn.addr = $wb", []> {
409 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
410 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
411 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
413 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
414 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
415 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
417 // ...with double-spaced registers:
418 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
419 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
420 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
421 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
422 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
423 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
425 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
426 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
427 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
429 // ...alternate versions to be allocated odd register numbers:
430 def VLD3q8oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
431 def VLD3q16oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
432 def VLD3q32oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
434 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
435 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
436 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
438 // VLD4 : Vector Load (multiple 4-element structures)
439 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
440 : NLdSt<0, 0b10, op11_8, op7_4,
441 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
442 (ins addrmode6:$Rn), IIC_VLD4,
443 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
445 let Inst{5-4} = Rn{5-4};
448 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
449 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
450 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
452 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
453 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
454 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
456 // ...with address register writeback:
457 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
458 : NLdSt<0, 0b10, op11_8, op7_4,
459 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
460 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u,
461 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
462 "$Rn.addr = $wb", []> {
463 let Inst{5-4} = Rn{5-4};
466 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
467 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
468 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
470 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
471 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
472 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
474 // ...with double-spaced registers:
475 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
476 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
477 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
478 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
479 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
480 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
482 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
483 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
484 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
486 // ...alternate versions to be allocated odd register numbers:
487 def VLD4q8oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
488 def VLD4q16oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
489 def VLD4q32oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
491 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
492 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
493 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
495 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
497 // Classes for VLD*LN pseudo-instructions with multi-register operands.
498 // These are expanded to real instructions after register allocation.
499 class VLDQLNPseudo<InstrItinClass itin>
500 : PseudoNLdSt<(outs QPR:$dst),
501 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
502 itin, "$src = $dst">;
503 class VLDQLNWBPseudo<InstrItinClass itin>
504 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
505 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
506 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
507 class VLDQQLNPseudo<InstrItinClass itin>
508 : PseudoNLdSt<(outs QQPR:$dst),
509 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
510 itin, "$src = $dst">;
511 class VLDQQLNWBPseudo<InstrItinClass itin>
512 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
513 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
514 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
515 class VLDQQQQLNPseudo<InstrItinClass itin>
516 : PseudoNLdSt<(outs QQQQPR:$dst),
517 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
518 itin, "$src = $dst">;
519 class VLDQQQQLNWBPseudo<InstrItinClass itin>
520 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
521 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
522 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
524 // VLD1LN : Vector Load (single element to one lane)
525 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
527 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
528 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
529 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
531 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
532 (i32 (LoadOp addrmode6:$Rn)),
536 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
537 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
538 (i32 (LoadOp addrmode6:$addr)),
542 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
543 let Inst{7-5} = lane{2-0};
545 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
546 let Inst{7-6} = lane{1-0};
549 def VLD1LNd32 : VLD1LN<0b1000, {?,0,?,?}, "32", v2i32, load> {
550 let Inst{7} = lane{0};
555 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
556 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
557 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
559 def : Pat<(vector_insert (v2f32 DPR:$src),
560 (f32 (load addrmode6:$addr)), imm:$lane),
561 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
562 def : Pat<(vector_insert (v4f32 QPR:$src),
563 (f32 (load addrmode6:$addr)), imm:$lane),
564 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
566 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
568 // ...with address register writeback:
569 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
570 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
571 (ins addrmode6:$Rn, am6offset:$Rm,
572 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
573 "\\{$Vd[$lane]\\}, $Rn$Rm",
574 "$src = $Vd, $Rn.addr = $wb", []>;
576 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
577 let Inst{7-5} = lane{2-0};
579 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
580 let Inst{7-6} = lane{1-0};
583 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
584 let Inst{7} = lane{0};
589 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
590 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
591 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
593 // VLD2LN : Vector Load (single 2-element structure to one lane)
594 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
595 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
596 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
597 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
598 "$src1 = $Vd, $src2 = $dst2", []> {
603 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
604 let Inst{7-5} = lane{2-0};
606 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
607 let Inst{7-6} = lane{1-0};
609 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
610 let Inst{7} = lane{0};
613 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
614 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
615 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
617 // ...with double-spaced registers:
618 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
619 let Inst{7-6} = lane{1-0};
621 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
622 let Inst{7} = lane{0};
625 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
626 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
628 // ...with address register writeback:
629 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
630 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
631 (ins addrmode6:$Rn, am6offset:$Rm,
632 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
633 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
634 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
638 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
639 let Inst{7-5} = lane{2-0};
641 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
642 let Inst{7-6} = lane{1-0};
644 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
645 let Inst{7} = lane{0};
648 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
649 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
650 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
652 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
653 let Inst{7-6} = lane{1-0};
655 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
656 let Inst{7} = lane{0};
659 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
660 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
662 // VLD3LN : Vector Load (single 3-element structure to one lane)
663 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
664 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
665 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
666 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
667 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
668 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
672 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
673 let Inst{7-5} = lane{2-0};
675 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
676 let Inst{7-6} = lane{1-0};
678 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
679 let Inst{7} = lane{0};
682 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
683 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
684 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
686 // ...with double-spaced registers:
687 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
688 let Inst{7-6} = lane{1-0};
690 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
691 let Inst{7} = lane{0};
694 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
695 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
697 // ...with address register writeback:
698 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
699 : NLdStLn<1, 0b10, op11_8, op7_4,
700 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
701 (ins addrmode6:$Rn, am6offset:$Rm,
702 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
703 IIC_VLD3lnu, "vld3", Dt,
704 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
705 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
708 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
709 let Inst{7-5} = lane{2-0};
711 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
712 let Inst{7-6} = lane{1-0};
714 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
715 let Inst{7} = lane{0};
718 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
719 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
720 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
722 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
723 let Inst{7-6} = lane{1-0};
725 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
726 let Inst{7} = lane{0};
729 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
730 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
732 // VLD4LN : Vector Load (single 4-element structure to one lane)
733 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
734 : NLdStLn<1, 0b10, op11_8, op7_4,
735 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
736 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
737 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
738 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
739 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
744 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
745 let Inst{7-5} = lane{2-0};
747 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
748 let Inst{7-6} = lane{1-0};
750 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
751 let Inst{7} = lane{0};
755 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
756 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
757 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
759 // ...with double-spaced registers:
760 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
761 let Inst{7-6} = lane{1-0};
763 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
764 let Inst{7} = lane{0};
768 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
769 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
771 // ...with address register writeback:
772 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
773 : NLdStLn<1, 0b10, op11_8, op7_4,
774 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
775 (ins addrmode6:$Rn, am6offset:$Rm,
776 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
777 IIC_VLD4lnu, "vld4", Dt,
778 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
779 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
784 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
785 let Inst{7-5} = lane{2-0};
787 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
788 let Inst{7-6} = lane{1-0};
790 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
791 let Inst{7} = lane{0};
795 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
796 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
797 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
799 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
800 let Inst{7-6} = lane{1-0};
802 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
803 let Inst{7} = lane{0};
807 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
808 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
810 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
812 // VLD1DUP : Vector Load (single element to all lanes)
813 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
814 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd), (ins addrmode6dup:$Rn),
815 IIC_VLD1dup, "vld1", Dt, "\\{$Vd[]\\}, $Rn", "",
816 [(set DPR:$Vd, (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
820 class VLD1QDUPPseudo<ValueType Ty, PatFrag LoadOp> : VLDQPseudo<IIC_VLD1dup> {
821 let Pattern = [(set QPR:$dst,
822 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$addr)))))];
825 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
826 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;
827 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;
829 def VLD1DUPq8Pseudo : VLD1QDUPPseudo<v16i8, extloadi8>;
830 def VLD1DUPq16Pseudo : VLD1QDUPPseudo<v8i16, extloadi16>;
831 def VLD1DUPq32Pseudo : VLD1QDUPPseudo<v4i32, load>;
833 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
834 (VLD1DUPd32 addrmode6:$addr)>;
835 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
836 (VLD1DUPq32Pseudo addrmode6:$addr)>;
838 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
840 class VLD1QDUP<bits<4> op7_4, string Dt>
841 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2),
842 (ins addrmode6dup:$Rn), IIC_VLD1dup,
843 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
848 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8">;
849 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16">;
850 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32">;
852 // ...with address register writeback:
853 class VLD1DUPWB<bits<4> op7_4, string Dt>
854 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, GPR:$wb),
855 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
856 "vld1", Dt, "\\{$Vd[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
859 class VLD1QDUPWB<bits<4> op7_4, string Dt>
860 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
861 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
862 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
866 def VLD1DUPd8_UPD : VLD1DUPWB<{0,0,0,0}, "8">;
867 def VLD1DUPd16_UPD : VLD1DUPWB<{0,1,0,?}, "16">;
868 def VLD1DUPd32_UPD : VLD1DUPWB<{1,0,0,?}, "32">;
870 def VLD1DUPq8_UPD : VLD1QDUPWB<{0,0,1,0}, "8">;
871 def VLD1DUPq16_UPD : VLD1QDUPWB<{0,1,1,?}, "16">;
872 def VLD1DUPq32_UPD : VLD1QDUPWB<{1,0,1,?}, "32">;
874 def VLD1DUPq8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
875 def VLD1DUPq16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
876 def VLD1DUPq32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
878 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
879 class VLD2DUP<bits<4> op7_4, string Dt>
880 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2),
881 (ins addrmode6dup:$Rn), IIC_VLD2dup,
882 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
887 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8">;
888 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16">;
889 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32">;
891 def VLD2DUPd8Pseudo : VLDQPseudo<IIC_VLD2dup>;
892 def VLD2DUPd16Pseudo : VLDQPseudo<IIC_VLD2dup>;
893 def VLD2DUPd32Pseudo : VLDQPseudo<IIC_VLD2dup>;
895 // ...with double-spaced registers (not used for codegen):
896 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8">;
897 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16">;
898 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32">;
900 // ...with address register writeback:
901 class VLD2DUPWB<bits<4> op7_4, string Dt>
902 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
903 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD2dupu,
904 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
908 def VLD2DUPd8_UPD : VLD2DUPWB<{0,0,0,0}, "8">;
909 def VLD2DUPd16_UPD : VLD2DUPWB<{0,1,0,?}, "16">;
910 def VLD2DUPd32_UPD : VLD2DUPWB<{1,0,0,?}, "32">;
912 def VLD2DUPd8x2_UPD : VLD2DUPWB<{0,0,1,0}, "8">;
913 def VLD2DUPd16x2_UPD : VLD2DUPWB<{0,1,1,?}, "16">;
914 def VLD2DUPd32x2_UPD : VLD2DUPWB<{1,0,1,?}, "32">;
916 def VLD2DUPd8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
917 def VLD2DUPd16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
918 def VLD2DUPd32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
920 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
921 class VLD3DUP<bits<4> op7_4, string Dt>
922 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
923 (ins addrmode6dup:$Rn), IIC_VLD3dup,
924 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
929 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
930 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
931 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
933 def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>;
934 def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
935 def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
937 // ...with double-spaced registers (not used for codegen):
938 def VLD3DUPd8x2 : VLD3DUP<{0,0,1,?}, "8">;
939 def VLD3DUPd16x2 : VLD3DUP<{0,1,1,?}, "16">;
940 def VLD3DUPd32x2 : VLD3DUP<{1,0,1,?}, "32">;
942 // ...with address register writeback:
943 class VLD3DUPWB<bits<4> op7_4, string Dt>
944 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
945 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu,
946 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
947 "$Rn.addr = $wb", []> {
951 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;
952 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">;
953 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">;
955 def VLD3DUPd8x2_UPD : VLD3DUPWB<{0,0,1,0}, "8">;
956 def VLD3DUPd16x2_UPD : VLD3DUPWB<{0,1,1,?}, "16">;
957 def VLD3DUPd32x2_UPD : VLD3DUPWB<{1,0,1,?}, "32">;
959 def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
960 def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
961 def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
963 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
964 class VLD4DUP<bits<4> op7_4, string Dt>
965 : NLdSt<1, 0b10, 0b1111, op7_4,
966 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
967 (ins addrmode6dup:$Rn), IIC_VLD4dup,
968 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
973 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
974 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
975 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
977 def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>;
978 def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>;
979 def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>;
981 // ...with double-spaced registers (not used for codegen):
982 def VLD4DUPd8x2 : VLD4DUP<{0,0,1,?}, "8">;
983 def VLD4DUPd16x2 : VLD4DUP<{0,1,1,?}, "16">;
984 def VLD4DUPd32x2 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
986 // ...with address register writeback:
987 class VLD4DUPWB<bits<4> op7_4, string Dt>
988 : NLdSt<1, 0b10, 0b1111, op7_4,
989 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
990 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
991 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
992 "$Rn.addr = $wb", []> {
996 def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">;
997 def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">;
998 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1000 def VLD4DUPd8x2_UPD : VLD4DUPWB<{0,0,1,0}, "8">;
1001 def VLD4DUPd16x2_UPD : VLD4DUPWB<{0,1,1,?}, "16">;
1002 def VLD4DUPd32x2_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1004 def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1005 def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1006 def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1008 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1010 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1012 // Classes for VST* pseudo-instructions with multi-register operands.
1013 // These are expanded to real instructions after register allocation.
1014 class VSTQPseudo<InstrItinClass itin>
1015 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1016 class VSTQWBPseudo<InstrItinClass itin>
1017 : PseudoNLdSt<(outs GPR:$wb),
1018 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1019 "$addr.addr = $wb">;
1020 class VSTQQPseudo<InstrItinClass itin>
1021 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
1022 class VSTQQWBPseudo<InstrItinClass itin>
1023 : PseudoNLdSt<(outs GPR:$wb),
1024 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
1025 "$addr.addr = $wb">;
1026 class VSTQQQQPseudo<InstrItinClass itin>
1027 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src), itin, "">;
1028 class VSTQQQQWBPseudo<InstrItinClass itin>
1029 : PseudoNLdSt<(outs GPR:$wb),
1030 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
1031 "$addr.addr = $wb">;
1033 // VST1 : Vector Store (multiple single elements)
1034 class VST1D<bits<4> op7_4, string Dt>
1035 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, DPR:$Vd),
1036 IIC_VST1, "vst1", Dt, "\\{$Vd\\}, $Rn", "", []> {
1038 let Inst{4} = Rn{4};
1040 class VST1Q<bits<4> op7_4, string Dt>
1041 : NLdSt<0,0b00,0b1010,op7_4, (outs),
1042 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2), IIC_VST1x2,
1043 "vst1", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1045 let Inst{5-4} = Rn{5-4};
1048 def VST1d8 : VST1D<{0,0,0,?}, "8">;
1049 def VST1d16 : VST1D<{0,1,0,?}, "16">;
1050 def VST1d32 : VST1D<{1,0,0,?}, "32">;
1051 def VST1d64 : VST1D<{1,1,0,?}, "64">;
1053 def VST1q8 : VST1Q<{0,0,?,?}, "8">;
1054 def VST1q16 : VST1Q<{0,1,?,?}, "16">;
1055 def VST1q32 : VST1Q<{1,0,?,?}, "32">;
1056 def VST1q64 : VST1Q<{1,1,?,?}, "64">;
1058 def VST1q8Pseudo : VSTQPseudo<IIC_VST1x2>;
1059 def VST1q16Pseudo : VSTQPseudo<IIC_VST1x2>;
1060 def VST1q32Pseudo : VSTQPseudo<IIC_VST1x2>;
1061 def VST1q64Pseudo : VSTQPseudo<IIC_VST1x2>;
1063 // ...with address register writeback:
1064 class VST1DWB<bits<4> op7_4, string Dt>
1065 : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
1066 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd), IIC_VST1u,
1067 "vst1", Dt, "\\{$Vd\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
1068 let Inst{4} = Rn{4};
1070 class VST1QWB<bits<4> op7_4, string Dt>
1071 : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),
1072 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
1073 IIC_VST1x2u, "vst1", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
1074 "$Rn.addr = $wb", []> {
1075 let Inst{5-4} = Rn{5-4};
1078 def VST1d8_UPD : VST1DWB<{0,0,0,?}, "8">;
1079 def VST1d16_UPD : VST1DWB<{0,1,0,?}, "16">;
1080 def VST1d32_UPD : VST1DWB<{1,0,0,?}, "32">;
1081 def VST1d64_UPD : VST1DWB<{1,1,0,?}, "64">;
1083 def VST1q8_UPD : VST1QWB<{0,0,?,?}, "8">;
1084 def VST1q16_UPD : VST1QWB<{0,1,?,?}, "16">;
1085 def VST1q32_UPD : VST1QWB<{1,0,?,?}, "32">;
1086 def VST1q64_UPD : VST1QWB<{1,1,?,?}, "64">;
1088 def VST1q8Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1089 def VST1q16Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1090 def VST1q32Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1091 def VST1q64Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1093 // ...with 3 registers (some of these are only for the disassembler):
1094 class VST1D3<bits<4> op7_4, string Dt>
1095 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1096 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3),
1097 IIC_VST1x3, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1099 let Inst{4} = Rn{4};
1101 class VST1D3WB<bits<4> op7_4, string Dt>
1102 : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
1103 (ins addrmode6:$Rn, am6offset:$Rm,
1104 DPR:$Vd, DPR:$src2, DPR:$src3),
1105 IIC_VST1x3u, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1106 "$Rn.addr = $wb", []> {
1107 let Inst{4} = Rn{4};
1110 def VST1d8T : VST1D3<{0,0,0,?}, "8">;
1111 def VST1d16T : VST1D3<{0,1,0,?}, "16">;
1112 def VST1d32T : VST1D3<{1,0,0,?}, "32">;
1113 def VST1d64T : VST1D3<{1,1,0,?}, "64">;
1115 def VST1d8T_UPD : VST1D3WB<{0,0,0,?}, "8">;
1116 def VST1d16T_UPD : VST1D3WB<{0,1,0,?}, "16">;
1117 def VST1d32T_UPD : VST1D3WB<{1,0,0,?}, "32">;
1118 def VST1d64T_UPD : VST1D3WB<{1,1,0,?}, "64">;
1120 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
1121 def VST1d64TPseudo_UPD : VSTQQWBPseudo<IIC_VST1x3u>;
1123 // ...with 4 registers (some of these are only for the disassembler):
1124 class VST1D4<bits<4> op7_4, string Dt>
1125 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1126 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1127 IIC_VST1x4, "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", "",
1130 let Inst{5-4} = Rn{5-4};
1132 class VST1D4WB<bits<4> op7_4, string Dt>
1133 : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
1134 (ins addrmode6:$Rn, am6offset:$Rm,
1135 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST1x4u,
1136 "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1137 "$Rn.addr = $wb", []> {
1138 let Inst{5-4} = Rn{5-4};
1141 def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
1142 def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
1143 def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
1144 def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
1146 def VST1d8Q_UPD : VST1D4WB<{0,0,?,?}, "8">;
1147 def VST1d16Q_UPD : VST1D4WB<{0,1,?,?}, "16">;
1148 def VST1d32Q_UPD : VST1D4WB<{1,0,?,?}, "32">;
1149 def VST1d64Q_UPD : VST1D4WB<{1,1,?,?}, "64">;
1151 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
1152 def VST1d64QPseudo_UPD : VSTQQWBPseudo<IIC_VST1x4u>;
1154 // VST2 : Vector Store (multiple 2-element structures)
1155 class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
1156 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1157 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2),
1158 IIC_VST2, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1160 let Inst{5-4} = Rn{5-4};
1162 class VST2Q<bits<4> op7_4, string Dt>
1163 : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
1164 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1165 IIC_VST2x2, "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1168 let Inst{5-4} = Rn{5-4};
1171 def VST2d8 : VST2D<0b1000, {0,0,?,?}, "8">;
1172 def VST2d16 : VST2D<0b1000, {0,1,?,?}, "16">;
1173 def VST2d32 : VST2D<0b1000, {1,0,?,?}, "32">;
1175 def VST2q8 : VST2Q<{0,0,?,?}, "8">;
1176 def VST2q16 : VST2Q<{0,1,?,?}, "16">;
1177 def VST2q32 : VST2Q<{1,0,?,?}, "32">;
1179 def VST2d8Pseudo : VSTQPseudo<IIC_VST2>;
1180 def VST2d16Pseudo : VSTQPseudo<IIC_VST2>;
1181 def VST2d32Pseudo : VSTQPseudo<IIC_VST2>;
1183 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
1184 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
1185 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
1187 // ...with address register writeback:
1188 class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1189 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1190 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
1191 IIC_VST2u, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
1192 "$Rn.addr = $wb", []> {
1193 let Inst{5-4} = Rn{5-4};
1195 class VST2QWB<bits<4> op7_4, string Dt>
1196 : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1197 (ins addrmode6:$Rn, am6offset:$Rm,
1198 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST2x2u,
1199 "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1200 "$Rn.addr = $wb", []> {
1201 let Inst{5-4} = Rn{5-4};
1204 def VST2d8_UPD : VST2DWB<0b1000, {0,0,?,?}, "8">;
1205 def VST2d16_UPD : VST2DWB<0b1000, {0,1,?,?}, "16">;
1206 def VST2d32_UPD : VST2DWB<0b1000, {1,0,?,?}, "32">;
1208 def VST2q8_UPD : VST2QWB<{0,0,?,?}, "8">;
1209 def VST2q16_UPD : VST2QWB<{0,1,?,?}, "16">;
1210 def VST2q32_UPD : VST2QWB<{1,0,?,?}, "32">;
1212 def VST2d8Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1213 def VST2d16Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1214 def VST2d32Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1216 def VST2q8Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1217 def VST2q16Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1218 def VST2q32Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1220 // ...with double-spaced registers (for disassembly only):
1221 def VST2b8 : VST2D<0b1001, {0,0,?,?}, "8">;
1222 def VST2b16 : VST2D<0b1001, {0,1,?,?}, "16">;
1223 def VST2b32 : VST2D<0b1001, {1,0,?,?}, "32">;
1224 def VST2b8_UPD : VST2DWB<0b1001, {0,0,?,?}, "8">;
1225 def VST2b16_UPD : VST2DWB<0b1001, {0,1,?,?}, "16">;
1226 def VST2b32_UPD : VST2DWB<0b1001, {1,0,?,?}, "32">;
1228 // VST3 : Vector Store (multiple 3-element structures)
1229 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1230 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1231 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1232 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1234 let Inst{4} = Rn{4};
1237 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1238 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1239 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
1241 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1242 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1243 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
1245 // ...with address register writeback:
1246 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1247 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1248 (ins addrmode6:$Rn, am6offset:$Rm,
1249 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1250 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1251 "$Rn.addr = $wb", []> {
1252 let Inst{4} = Rn{4};
1255 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1256 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1257 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
1259 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1260 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1261 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1263 // ...with double-spaced registers:
1264 def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1265 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1266 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1267 def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1268 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1269 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
1271 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1272 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1273 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1275 // ...alternate versions to be allocated odd register numbers:
1276 def VST3q8oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1277 def VST3q16oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1278 def VST3q32oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1280 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1281 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1282 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1284 // VST4 : Vector Store (multiple 4-element structures)
1285 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1286 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1287 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1288 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1291 let Inst{5-4} = Rn{5-4};
1294 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1295 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1296 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
1298 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1299 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1300 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
1302 // ...with address register writeback:
1303 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1304 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1305 (ins addrmode6:$Rn, am6offset:$Rm,
1306 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1307 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1308 "$Rn.addr = $wb", []> {
1309 let Inst{5-4} = Rn{5-4};
1312 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
1313 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
1314 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
1316 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1317 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1318 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1320 // ...with double-spaced registers:
1321 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
1322 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
1323 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
1324 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
1325 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
1326 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
1328 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1329 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1330 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1332 // ...alternate versions to be allocated odd register numbers:
1333 def VST4q8oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1334 def VST4q16oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1335 def VST4q32oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1337 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1338 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1339 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1341 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1343 // Classes for VST*LN pseudo-instructions with multi-register operands.
1344 // These are expanded to real instructions after register allocation.
1345 class VSTQLNPseudo<InstrItinClass itin>
1346 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1348 class VSTQLNWBPseudo<InstrItinClass itin>
1349 : PseudoNLdSt<(outs GPR:$wb),
1350 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1351 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1352 class VSTQQLNPseudo<InstrItinClass itin>
1353 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1355 class VSTQQLNWBPseudo<InstrItinClass itin>
1356 : PseudoNLdSt<(outs GPR:$wb),
1357 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1358 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1359 class VSTQQQQLNPseudo<InstrItinClass itin>
1360 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1362 class VSTQQQQLNWBPseudo<InstrItinClass itin>
1363 : PseudoNLdSt<(outs GPR:$wb),
1364 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1365 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1367 // VST1LN : Vector Store (single element from one lane)
1368 class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1369 PatFrag StoreOp, SDNode ExtractOp>
1370 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1371 (ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane),
1372 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1373 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6:$Rn)]> {
1376 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1377 : VSTQLNPseudo<IIC_VST1ln> {
1378 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1382 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
1384 let Inst{7-5} = lane{2-0};
1386 def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
1388 let Inst{7-6} = lane{1-0};
1389 let Inst{4} = Rn{5};
1391 def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt> {
1392 let Inst{7} = lane{0};
1393 let Inst{5-4} = Rn{5-4};
1396 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
1397 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
1398 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
1400 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
1401 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1402 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
1403 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1405 // ...with address register writeback:
1406 class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1407 PatFrag StoreOp, SDNode ExtractOp>
1408 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1409 (ins addrmode6:$Rn, am6offset:$Rm,
1410 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
1411 "\\{$Vd[$lane]\\}, $Rn$Rm",
1413 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
1414 addrmode6:$Rn, am6offset:$Rm))]>;
1415 class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1416 : VSTQLNWBPseudo<IIC_VST1lnu> {
1417 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1418 addrmode6:$addr, am6offset:$offset))];
1421 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8,
1423 let Inst{7-5} = lane{2-0};
1425 def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16", v4i16, post_truncsti16,
1427 let Inst{7-6} = lane{1-0};
1428 let Inst{4} = Rn{5};
1430 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32", v2i32, post_store,
1432 let Inst{7} = lane{0};
1433 let Inst{5-4} = Rn{5-4};
1436 def VST1LNq8Pseudo_UPD : VST1QLNWBPseudo<v16i8, post_truncsti8, NEONvgetlaneu>;
1437 def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,NEONvgetlaneu>;
1438 def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
1440 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1442 // VST2LN : Vector Store (single 2-element structure from one lane)
1443 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1444 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1445 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
1446 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
1449 let Inst{4} = Rn{4};
1452 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
1453 let Inst{7-5} = lane{2-0};
1455 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
1456 let Inst{7-6} = lane{1-0};
1458 def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
1459 let Inst{7} = lane{0};
1462 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1463 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1464 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1466 // ...with double-spaced registers:
1467 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
1468 let Inst{7-6} = lane{1-0};
1469 let Inst{4} = Rn{4};
1471 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
1472 let Inst{7} = lane{0};
1473 let Inst{4} = Rn{4};
1476 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1477 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1479 // ...with address register writeback:
1480 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1481 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1482 (ins addrmode6:$addr, am6offset:$offset,
1483 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
1484 "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset",
1485 "$addr.addr = $wb", []> {
1486 let Inst{4} = Rn{4};
1489 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
1490 let Inst{7-5} = lane{2-0};
1492 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
1493 let Inst{7-6} = lane{1-0};
1495 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
1496 let Inst{7} = lane{0};
1499 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1500 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1501 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1503 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
1504 let Inst{7-6} = lane{1-0};
1506 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
1507 let Inst{7} = lane{0};
1510 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1511 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1513 // VST3LN : Vector Store (single 3-element structure from one lane)
1514 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1515 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1516 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
1517 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
1518 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
1522 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
1523 let Inst{7-5} = lane{2-0};
1525 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
1526 let Inst{7-6} = lane{1-0};
1528 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
1529 let Inst{7} = lane{0};
1532 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1533 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1534 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1536 // ...with double-spaced registers:
1537 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
1538 let Inst{7-6} = lane{1-0};
1540 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
1541 let Inst{7} = lane{0};
1544 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1545 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1547 // ...with address register writeback:
1548 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1549 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1550 (ins addrmode6:$Rn, am6offset:$Rm,
1551 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1552 IIC_VST3lnu, "vst3", Dt,
1553 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
1554 "$Rn.addr = $wb", []>;
1556 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
1557 let Inst{7-5} = lane{2-0};
1559 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
1560 let Inst{7-6} = lane{1-0};
1562 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
1563 let Inst{7} = lane{0};
1566 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1567 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1568 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1570 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
1571 let Inst{7-6} = lane{1-0};
1573 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
1574 let Inst{7} = lane{0};
1577 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1578 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1580 // VST4LN : Vector Store (single 4-element structure from one lane)
1581 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1582 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1583 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
1584 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
1585 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
1588 let Inst{4} = Rn{4};
1591 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
1592 let Inst{7-5} = lane{2-0};
1594 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
1595 let Inst{7-6} = lane{1-0};
1597 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
1598 let Inst{7} = lane{0};
1599 let Inst{5} = Rn{5};
1602 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1603 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1604 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1606 // ...with double-spaced registers:
1607 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
1608 let Inst{7-6} = lane{1-0};
1610 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
1611 let Inst{7} = lane{0};
1612 let Inst{5} = Rn{5};
1615 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1616 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1618 // ...with address register writeback:
1619 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1620 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1621 (ins addrmode6:$Rn, am6offset:$Rm,
1622 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1623 IIC_VST4lnu, "vst4", Dt,
1624 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
1625 "$Rn.addr = $wb", []> {
1626 let Inst{4} = Rn{4};
1629 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
1630 let Inst{7-5} = lane{2-0};
1632 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
1633 let Inst{7-6} = lane{1-0};
1635 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
1636 let Inst{7} = lane{0};
1637 let Inst{5} = Rn{5};
1640 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1641 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1642 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1644 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
1645 let Inst{7-6} = lane{1-0};
1647 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
1648 let Inst{7} = lane{0};
1649 let Inst{5} = Rn{5};
1652 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1653 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1655 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1658 //===----------------------------------------------------------------------===//
1659 // NEON pattern fragments
1660 //===----------------------------------------------------------------------===//
1662 // Extract D sub-registers of Q registers.
1663 def DSubReg_i8_reg : SDNodeXForm<imm, [{
1664 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1665 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
1667 def DSubReg_i16_reg : SDNodeXForm<imm, [{
1668 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1669 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
1671 def DSubReg_i32_reg : SDNodeXForm<imm, [{
1672 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1673 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
1675 def DSubReg_f64_reg : SDNodeXForm<imm, [{
1676 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1677 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
1680 // Extract S sub-registers of Q/D registers.
1681 def SSubReg_f32_reg : SDNodeXForm<imm, [{
1682 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
1683 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
1686 // Translate lane numbers from Q registers to D subregs.
1687 def SubReg_i8_lane : SDNodeXForm<imm, [{
1688 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
1690 def SubReg_i16_lane : SDNodeXForm<imm, [{
1691 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
1693 def SubReg_i32_lane : SDNodeXForm<imm, [{
1694 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
1697 //===----------------------------------------------------------------------===//
1698 // Instruction Classes
1699 //===----------------------------------------------------------------------===//
1701 // Basic 2-register operations: double- and quad-register.
1702 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1703 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1704 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1705 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
1706 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
1707 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
1708 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1709 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1710 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1711 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
1712 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
1713 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
1715 // Basic 2-register intrinsics, both double- and quad-register.
1716 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1717 bits<2> op17_16, bits<5> op11_7, bit op4,
1718 InstrItinClass itin, string OpcodeStr, string Dt,
1719 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1720 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
1721 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1722 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
1723 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1724 bits<2> op17_16, bits<5> op11_7, bit op4,
1725 InstrItinClass itin, string OpcodeStr, string Dt,
1726 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1727 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
1728 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1729 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
1731 // Narrow 2-register operations.
1732 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1733 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1734 InstrItinClass itin, string OpcodeStr, string Dt,
1735 ValueType TyD, ValueType TyQ, SDNode OpNode>
1736 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
1737 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1738 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
1740 // Narrow 2-register intrinsics.
1741 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1742 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1743 InstrItinClass itin, string OpcodeStr, string Dt,
1744 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
1745 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
1746 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1747 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
1749 // Long 2-register operations (currently only used for VMOVL).
1750 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1751 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1752 InstrItinClass itin, string OpcodeStr, string Dt,
1753 ValueType TyQ, ValueType TyD, SDNode OpNode>
1754 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
1755 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1756 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
1758 // Long 2-register intrinsics.
1759 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1760 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1761 InstrItinClass itin, string OpcodeStr, string Dt,
1762 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
1763 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
1764 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1765 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
1767 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
1768 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
1769 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
1770 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
1771 OpcodeStr, Dt, "$Vd, $Vm",
1772 "$src1 = $Vd, $src2 = $Vm", []>;
1773 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
1774 InstrItinClass itin, string OpcodeStr, string Dt>
1775 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
1776 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
1777 "$src1 = $Vd, $src2 = $Vm", []>;
1779 // Basic 3-register operations: double- and quad-register.
1780 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1781 InstrItinClass itin, string OpcodeStr, string Dt,
1782 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1783 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1784 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1785 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1786 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
1787 let isCommutable = Commutable;
1789 // Same as N3VD but no data type.
1790 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1791 InstrItinClass itin, string OpcodeStr,
1792 ValueType ResTy, ValueType OpTy,
1793 SDNode OpNode, bit Commutable>
1794 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
1795 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1796 OpcodeStr, "$Vd, $Vn, $Vm", "",
1797 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
1798 let isCommutable = Commutable;
1801 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
1802 InstrItinClass itin, string OpcodeStr, string Dt,
1803 ValueType Ty, SDNode ShOp>
1804 : N3V<0, 1, op21_20, op11_8, 1, 0,
1805 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1806 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1808 (Ty (ShOp (Ty DPR:$Vn),
1809 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
1810 let isCommutable = 0;
1812 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
1813 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1814 : N3V<0, 1, op21_20, op11_8, 1, 0,
1815 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1816 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm[$lane]","",
1818 (Ty (ShOp (Ty DPR:$Vn),
1819 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
1820 let isCommutable = 0;
1823 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1824 InstrItinClass itin, string OpcodeStr, string Dt,
1825 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1826 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1827 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1828 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1829 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
1830 let isCommutable = Commutable;
1832 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1833 InstrItinClass itin, string OpcodeStr,
1834 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1835 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
1836 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1837 OpcodeStr, "$Vd, $Vn, $Vm", "",
1838 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
1839 let isCommutable = Commutable;
1841 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
1842 InstrItinClass itin, string OpcodeStr, string Dt,
1843 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1844 : N3V<1, 1, op21_20, op11_8, 1, 0,
1845 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1846 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1847 [(set (ResTy QPR:$Vd),
1848 (ResTy (ShOp (ResTy QPR:$Vn),
1849 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
1851 let isCommutable = 0;
1853 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
1854 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1855 : N3V<1, 1, op21_20, op11_8, 1, 0,
1856 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1857 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm[$lane]","",
1858 [(set (ResTy QPR:$Vd),
1859 (ResTy (ShOp (ResTy QPR:$Vn),
1860 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
1862 let isCommutable = 0;
1865 // Basic 3-register intrinsics, both double- and quad-register.
1866 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1867 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1868 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1869 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1870 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
1871 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1872 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
1873 let isCommutable = Commutable;
1875 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1876 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1877 : N3V<0, 1, op21_20, op11_8, 1, 0,
1878 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1879 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1881 (Ty (IntOp (Ty DPR:$Vn),
1882 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
1884 let isCommutable = 0;
1886 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1887 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1888 : N3V<0, 1, op21_20, op11_8, 1, 0,
1889 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1890 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1892 (Ty (IntOp (Ty DPR:$Vn),
1893 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
1894 let isCommutable = 0;
1896 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1897 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1898 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1899 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1900 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
1901 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
1902 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
1903 let isCommutable = 0;
1906 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1907 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1908 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1909 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1910 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
1911 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1912 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
1913 let isCommutable = Commutable;
1915 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1916 string OpcodeStr, string Dt,
1917 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1918 : N3V<1, 1, op21_20, op11_8, 1, 0,
1919 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1920 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1921 [(set (ResTy QPR:$Vd),
1922 (ResTy (IntOp (ResTy QPR:$Vn),
1923 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
1925 let isCommutable = 0;
1927 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1928 string OpcodeStr, string Dt,
1929 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1930 : N3V<1, 1, op21_20, op11_8, 1, 0,
1931 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1932 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1933 [(set (ResTy QPR:$Vd),
1934 (ResTy (IntOp (ResTy QPR:$Vn),
1935 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
1937 let isCommutable = 0;
1939 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1940 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1941 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1942 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1943 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
1944 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
1945 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
1946 let isCommutable = 0;
1949 // Multiply-Add/Sub operations: double- and quad-register.
1950 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1951 InstrItinClass itin, string OpcodeStr, string Dt,
1952 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode>
1953 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1954 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1955 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1956 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
1957 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
1959 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1960 string OpcodeStr, string Dt,
1961 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
1962 : N3V<0, 1, op21_20, op11_8, 1, 0,
1964 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1966 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
1968 (Ty (ShOp (Ty DPR:$src1),
1970 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
1972 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1973 string OpcodeStr, string Dt,
1974 ValueType Ty, SDNode MulOp, SDNode ShOp>
1975 : N3V<0, 1, op21_20, op11_8, 1, 0,
1977 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1979 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
1981 (Ty (ShOp (Ty DPR:$src1),
1983 (Ty (NEONvduplane (Ty DPR_8:$Vm),
1986 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1987 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
1988 SDPatternOperator MulOp, SDPatternOperator OpNode>
1989 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1990 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1991 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1992 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
1993 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
1994 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1995 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1996 SDPatternOperator MulOp, SDPatternOperator ShOp>
1997 : N3V<1, 1, op21_20, op11_8, 1, 0,
1999 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2001 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2002 [(set (ResTy QPR:$Vd),
2003 (ResTy (ShOp (ResTy QPR:$src1),
2004 (ResTy (MulOp QPR:$Vn,
2005 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2007 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2008 string OpcodeStr, string Dt,
2009 ValueType ResTy, ValueType OpTy,
2010 SDNode MulOp, SDNode ShOp>
2011 : N3V<1, 1, op21_20, op11_8, 1, 0,
2013 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2015 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2016 [(set (ResTy QPR:$Vd),
2017 (ResTy (ShOp (ResTy QPR:$src1),
2018 (ResTy (MulOp QPR:$Vn,
2019 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2022 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
2023 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2024 InstrItinClass itin, string OpcodeStr, string Dt,
2025 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2026 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2027 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2028 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2029 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2030 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
2031 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2032 InstrItinClass itin, string OpcodeStr, string Dt,
2033 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2034 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2035 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2036 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2037 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2038 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2040 // Neon 3-argument intrinsics, both double- and quad-register.
2041 // The destination register is also used as the first source operand register.
2042 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2043 InstrItinClass itin, string OpcodeStr, string Dt,
2044 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2045 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2046 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2047 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2048 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2049 (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2050 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2051 InstrItinClass itin, string OpcodeStr, string Dt,
2052 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2053 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2054 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2055 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2056 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2057 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2059 // Long Multiply-Add/Sub operations.
2060 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2061 InstrItinClass itin, string OpcodeStr, string Dt,
2062 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2063 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2064 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2065 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2066 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2067 (TyQ (MulOp (TyD DPR:$Vn),
2068 (TyD DPR:$Vm)))))]>;
2069 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2070 InstrItinClass itin, string OpcodeStr, string Dt,
2071 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2072 : N3V<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2073 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2075 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2077 (OpNode (TyQ QPR:$src1),
2078 (TyQ (MulOp (TyD DPR:$Vn),
2079 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),
2081 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2082 InstrItinClass itin, string OpcodeStr, string Dt,
2083 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2084 : N3V<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2085 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2087 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2089 (OpNode (TyQ QPR:$src1),
2090 (TyQ (MulOp (TyD DPR:$Vn),
2091 (TyD (NEONvduplane (TyD DPR_8:$Vm),
2094 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
2095 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2096 InstrItinClass itin, string OpcodeStr, string Dt,
2097 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2099 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2100 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2101 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2102 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2103 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2104 (TyD DPR:$Vm)))))))]>;
2106 // Neon Long 3-argument intrinsic. The destination register is
2107 // a quad-register and is also used as the first source operand register.
2108 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2109 InstrItinClass itin, string OpcodeStr, string Dt,
2110 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
2111 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2112 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2113 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2115 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2116 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2117 string OpcodeStr, string Dt,
2118 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2119 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2121 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2123 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2124 [(set (ResTy QPR:$Vd),
2125 (ResTy (IntOp (ResTy QPR:$src1),
2127 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2129 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2130 InstrItinClass itin, string OpcodeStr, string Dt,
2131 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2132 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2134 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2136 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2137 [(set (ResTy QPR:$Vd),
2138 (ResTy (IntOp (ResTy QPR:$src1),
2140 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2143 // Narrowing 3-register intrinsics.
2144 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2145 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
2146 Intrinsic IntOp, bit Commutable>
2147 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2148 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2149 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2150 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2151 let isCommutable = Commutable;
2154 // Long 3-register operations.
2155 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2156 InstrItinClass itin, string OpcodeStr, string Dt,
2157 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
2158 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2159 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2160 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2161 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2162 let isCommutable = Commutable;
2164 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2165 InstrItinClass itin, string OpcodeStr, string Dt,
2166 ValueType TyQ, ValueType TyD, SDNode OpNode>
2167 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2168 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2169 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2171 (TyQ (OpNode (TyD DPR:$Vn),
2172 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
2173 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2174 InstrItinClass itin, string OpcodeStr, string Dt,
2175 ValueType TyQ, ValueType TyD, SDNode OpNode>
2176 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2177 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2178 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2180 (TyQ (OpNode (TyD DPR:$Vn),
2181 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
2183 // Long 3-register operations with explicitly extended operands.
2184 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2185 InstrItinClass itin, string OpcodeStr, string Dt,
2186 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
2188 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2189 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2190 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2191 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
2192 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2193 let isCommutable = Commutable;
2196 // Long 3-register intrinsics with explicit extend (VABDL).
2197 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2198 InstrItinClass itin, string OpcodeStr, string Dt,
2199 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2201 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2202 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2203 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2204 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2205 (TyD DPR:$Vm))))))]> {
2206 let isCommutable = Commutable;
2209 // Long 3-register intrinsics.
2210 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2211 InstrItinClass itin, string OpcodeStr, string Dt,
2212 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
2213 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2214 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2215 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2216 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2217 let isCommutable = Commutable;
2219 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2220 string OpcodeStr, string Dt,
2221 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2222 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2223 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2224 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2225 [(set (ResTy QPR:$Vd),
2226 (ResTy (IntOp (OpTy DPR:$Vn),
2227 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2229 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2230 InstrItinClass itin, string OpcodeStr, string Dt,
2231 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2232 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2233 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2234 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2235 [(set (ResTy QPR:$Vd),
2236 (ResTy (IntOp (OpTy DPR:$Vn),
2237 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2240 // Wide 3-register operations.
2241 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2242 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
2243 SDNode OpNode, SDNode ExtOp, bit Commutable>
2244 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2245 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
2246 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2247 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
2248 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2249 let isCommutable = Commutable;
2252 // Pairwise long 2-register intrinsics, both double- and quad-register.
2253 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2254 bits<2> op17_16, bits<5> op11_7, bit op4,
2255 string OpcodeStr, string Dt,
2256 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2257 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2258 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2259 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2260 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2261 bits<2> op17_16, bits<5> op11_7, bit op4,
2262 string OpcodeStr, string Dt,
2263 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2264 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2265 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2266 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2268 // Pairwise long 2-register accumulate intrinsics,
2269 // both double- and quad-register.
2270 // The destination register is also used as the first source operand register.
2271 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2272 bits<2> op17_16, bits<5> op11_7, bit op4,
2273 string OpcodeStr, string Dt,
2274 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2275 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
2276 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
2277 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2278 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
2279 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2280 bits<2> op17_16, bits<5> op11_7, bit op4,
2281 string OpcodeStr, string Dt,
2282 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2283 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
2284 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
2285 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2286 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
2288 // Shift by immediate,
2289 // both double- and quad-register.
2290 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2291 Format f, InstrItinClass itin, Operand ImmTy,
2292 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2293 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2294 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
2295 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2296 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
2297 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2298 Format f, InstrItinClass itin, Operand ImmTy,
2299 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2300 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2301 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
2302 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2303 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
2305 // Long shift by immediate.
2306 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2307 string OpcodeStr, string Dt,
2308 ValueType ResTy, ValueType OpTy, SDNode OpNode>
2309 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2310 (outs QPR:$Vd), (ins DPR:$Vm, i32imm:$SIMM), N2RegVShLFrm,
2311 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2312 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm),
2313 (i32 imm:$SIMM))))]>;
2315 // Narrow shift by immediate.
2316 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2317 InstrItinClass itin, string OpcodeStr, string Dt,
2318 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode>
2319 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2320 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
2321 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2322 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
2323 (i32 imm:$SIMM))))]>;
2325 // Shift right by immediate and accumulate,
2326 // both double- and quad-register.
2327 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2328 Operand ImmTy, string OpcodeStr, string Dt,
2329 ValueType Ty, SDNode ShOp>
2330 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2331 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2332 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2333 [(set DPR:$Vd, (Ty (add DPR:$src1,
2334 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
2335 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2336 Operand ImmTy, string OpcodeStr, string Dt,
2337 ValueType Ty, SDNode ShOp>
2338 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2339 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2340 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2341 [(set QPR:$Vd, (Ty (add QPR:$src1,
2342 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
2344 // Shift by immediate and insert,
2345 // both double- and quad-register.
2346 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2347 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2348 ValueType Ty,SDNode ShOp>
2349 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2350 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiD,
2351 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2352 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
2353 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2354 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2355 ValueType Ty,SDNode ShOp>
2356 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2357 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiQ,
2358 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2359 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
2361 // Convert, with fractional bits immediate,
2362 // both double- and quad-register.
2363 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2364 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2366 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2367 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2368 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2369 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
2370 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2371 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2373 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2374 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2375 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2376 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
2378 //===----------------------------------------------------------------------===//
2380 //===----------------------------------------------------------------------===//
2382 // Abbreviations used in multiclass suffixes:
2383 // Q = quarter int (8 bit) elements
2384 // H = half int (16 bit) elements
2385 // S = single int (32 bit) elements
2386 // D = double int (64 bit) elements
2388 // Neon 2-register vector operations and intrinsics.
2390 // Neon 2-register comparisons.
2391 // source operand element sizes of 8, 16 and 32 bits:
2392 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2393 bits<5> op11_7, bit op4, string opc, string Dt,
2394 string asm, SDNode OpNode> {
2395 // 64-bit vector types.
2396 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
2397 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2398 opc, !strconcat(Dt, "8"), asm, "",
2399 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
2400 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
2401 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2402 opc, !strconcat(Dt, "16"), asm, "",
2403 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>;
2404 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2405 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2406 opc, !strconcat(Dt, "32"), asm, "",
2407 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>;
2408 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2409 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2410 opc, "f32", asm, "",
2411 [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> {
2412 let Inst{10} = 1; // overwrite F = 1
2415 // 128-bit vector types.
2416 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
2417 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2418 opc, !strconcat(Dt, "8"), asm, "",
2419 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
2420 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
2421 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2422 opc, !strconcat(Dt, "16"), asm, "",
2423 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
2424 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2425 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2426 opc, !strconcat(Dt, "32"), asm, "",
2427 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
2428 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2429 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2430 opc, "f32", asm, "",
2431 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
2432 let Inst{10} = 1; // overwrite F = 1
2437 // Neon 2-register vector intrinsics,
2438 // element sizes of 8, 16 and 32 bits:
2439 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2440 bits<5> op11_7, bit op4,
2441 InstrItinClass itinD, InstrItinClass itinQ,
2442 string OpcodeStr, string Dt, Intrinsic IntOp> {
2443 // 64-bit vector types.
2444 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2445 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2446 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2447 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
2448 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2449 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
2451 // 128-bit vector types.
2452 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2453 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
2454 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2455 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
2456 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2457 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
2461 // Neon Narrowing 2-register vector operations,
2462 // source operand element sizes of 16, 32 and 64 bits:
2463 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2464 bits<5> op11_7, bit op6, bit op4,
2465 InstrItinClass itin, string OpcodeStr, string Dt,
2467 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2468 itin, OpcodeStr, !strconcat(Dt, "16"),
2469 v8i8, v8i16, OpNode>;
2470 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2471 itin, OpcodeStr, !strconcat(Dt, "32"),
2472 v4i16, v4i32, OpNode>;
2473 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2474 itin, OpcodeStr, !strconcat(Dt, "64"),
2475 v2i32, v2i64, OpNode>;
2478 // Neon Narrowing 2-register vector intrinsics,
2479 // source operand element sizes of 16, 32 and 64 bits:
2480 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2481 bits<5> op11_7, bit op6, bit op4,
2482 InstrItinClass itin, string OpcodeStr, string Dt,
2484 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2485 itin, OpcodeStr, !strconcat(Dt, "16"),
2486 v8i8, v8i16, IntOp>;
2487 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2488 itin, OpcodeStr, !strconcat(Dt, "32"),
2489 v4i16, v4i32, IntOp>;
2490 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2491 itin, OpcodeStr, !strconcat(Dt, "64"),
2492 v2i32, v2i64, IntOp>;
2496 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
2497 // source operand element sizes of 16, 32 and 64 bits:
2498 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
2499 string OpcodeStr, string Dt, SDNode OpNode> {
2500 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2501 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
2502 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2503 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2504 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2505 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2509 // Neon 3-register vector operations.
2511 // First with only element sizes of 8, 16 and 32 bits:
2512 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2513 InstrItinClass itinD16, InstrItinClass itinD32,
2514 InstrItinClass itinQ16, InstrItinClass itinQ32,
2515 string OpcodeStr, string Dt,
2516 SDNode OpNode, bit Commutable = 0> {
2517 // 64-bit vector types.
2518 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
2519 OpcodeStr, !strconcat(Dt, "8"),
2520 v8i8, v8i8, OpNode, Commutable>;
2521 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
2522 OpcodeStr, !strconcat(Dt, "16"),
2523 v4i16, v4i16, OpNode, Commutable>;
2524 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
2525 OpcodeStr, !strconcat(Dt, "32"),
2526 v2i32, v2i32, OpNode, Commutable>;
2528 // 128-bit vector types.
2529 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
2530 OpcodeStr, !strconcat(Dt, "8"),
2531 v16i8, v16i8, OpNode, Commutable>;
2532 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
2533 OpcodeStr, !strconcat(Dt, "16"),
2534 v8i16, v8i16, OpNode, Commutable>;
2535 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
2536 OpcodeStr, !strconcat(Dt, "32"),
2537 v4i32, v4i32, OpNode, Commutable>;
2540 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
2541 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2543 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
2545 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2546 v8i16, v4i16, ShOp>;
2547 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
2548 v4i32, v2i32, ShOp>;
2551 // ....then also with element size 64 bits:
2552 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2553 InstrItinClass itinD, InstrItinClass itinQ,
2554 string OpcodeStr, string Dt,
2555 SDNode OpNode, bit Commutable = 0>
2556 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
2557 OpcodeStr, Dt, OpNode, Commutable> {
2558 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
2559 OpcodeStr, !strconcat(Dt, "64"),
2560 v1i64, v1i64, OpNode, Commutable>;
2561 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
2562 OpcodeStr, !strconcat(Dt, "64"),
2563 v2i64, v2i64, OpNode, Commutable>;
2567 // Neon 3-register vector intrinsics.
2569 // First with only element sizes of 16 and 32 bits:
2570 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2571 InstrItinClass itinD16, InstrItinClass itinD32,
2572 InstrItinClass itinQ16, InstrItinClass itinQ32,
2573 string OpcodeStr, string Dt,
2574 Intrinsic IntOp, bit Commutable = 0> {
2575 // 64-bit vector types.
2576 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
2577 OpcodeStr, !strconcat(Dt, "16"),
2578 v4i16, v4i16, IntOp, Commutable>;
2579 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
2580 OpcodeStr, !strconcat(Dt, "32"),
2581 v2i32, v2i32, IntOp, Commutable>;
2583 // 128-bit vector types.
2584 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2585 OpcodeStr, !strconcat(Dt, "16"),
2586 v8i16, v8i16, IntOp, Commutable>;
2587 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2588 OpcodeStr, !strconcat(Dt, "32"),
2589 v4i32, v4i32, IntOp, Commutable>;
2591 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2592 InstrItinClass itinD16, InstrItinClass itinD32,
2593 InstrItinClass itinQ16, InstrItinClass itinQ32,
2594 string OpcodeStr, string Dt,
2596 // 64-bit vector types.
2597 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
2598 OpcodeStr, !strconcat(Dt, "16"),
2599 v4i16, v4i16, IntOp>;
2600 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
2601 OpcodeStr, !strconcat(Dt, "32"),
2602 v2i32, v2i32, IntOp>;
2604 // 128-bit vector types.
2605 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2606 OpcodeStr, !strconcat(Dt, "16"),
2607 v8i16, v8i16, IntOp>;
2608 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2609 OpcodeStr, !strconcat(Dt, "32"),
2610 v4i32, v4i32, IntOp>;
2613 multiclass N3VIntSL_HS<bits<4> op11_8,
2614 InstrItinClass itinD16, InstrItinClass itinD32,
2615 InstrItinClass itinQ16, InstrItinClass itinQ32,
2616 string OpcodeStr, string Dt, Intrinsic IntOp> {
2617 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
2618 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
2619 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
2620 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
2621 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
2622 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
2623 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
2624 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
2627 // ....then also with element size of 8 bits:
2628 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2629 InstrItinClass itinD16, InstrItinClass itinD32,
2630 InstrItinClass itinQ16, InstrItinClass itinQ32,
2631 string OpcodeStr, string Dt,
2632 Intrinsic IntOp, bit Commutable = 0>
2633 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2634 OpcodeStr, Dt, IntOp, Commutable> {
2635 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
2636 OpcodeStr, !strconcat(Dt, "8"),
2637 v8i8, v8i8, IntOp, Commutable>;
2638 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2639 OpcodeStr, !strconcat(Dt, "8"),
2640 v16i8, v16i8, IntOp, Commutable>;
2642 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2643 InstrItinClass itinD16, InstrItinClass itinD32,
2644 InstrItinClass itinQ16, InstrItinClass itinQ32,
2645 string OpcodeStr, string Dt,
2647 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2648 OpcodeStr, Dt, IntOp> {
2649 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
2650 OpcodeStr, !strconcat(Dt, "8"),
2652 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2653 OpcodeStr, !strconcat(Dt, "8"),
2654 v16i8, v16i8, IntOp>;
2658 // ....then also with element size of 64 bits:
2659 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2660 InstrItinClass itinD16, InstrItinClass itinD32,
2661 InstrItinClass itinQ16, InstrItinClass itinQ32,
2662 string OpcodeStr, string Dt,
2663 Intrinsic IntOp, bit Commutable = 0>
2664 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2665 OpcodeStr, Dt, IntOp, Commutable> {
2666 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
2667 OpcodeStr, !strconcat(Dt, "64"),
2668 v1i64, v1i64, IntOp, Commutable>;
2669 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2670 OpcodeStr, !strconcat(Dt, "64"),
2671 v2i64, v2i64, IntOp, Commutable>;
2673 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2674 InstrItinClass itinD16, InstrItinClass itinD32,
2675 InstrItinClass itinQ16, InstrItinClass itinQ32,
2676 string OpcodeStr, string Dt,
2678 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2679 OpcodeStr, Dt, IntOp> {
2680 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
2681 OpcodeStr, !strconcat(Dt, "64"),
2682 v1i64, v1i64, IntOp>;
2683 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2684 OpcodeStr, !strconcat(Dt, "64"),
2685 v2i64, v2i64, IntOp>;
2688 // Neon Narrowing 3-register vector intrinsics,
2689 // source operand element sizes of 16, 32 and 64 bits:
2690 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2691 string OpcodeStr, string Dt,
2692 Intrinsic IntOp, bit Commutable = 0> {
2693 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
2694 OpcodeStr, !strconcat(Dt, "16"),
2695 v8i8, v8i16, IntOp, Commutable>;
2696 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
2697 OpcodeStr, !strconcat(Dt, "32"),
2698 v4i16, v4i32, IntOp, Commutable>;
2699 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
2700 OpcodeStr, !strconcat(Dt, "64"),
2701 v2i32, v2i64, IntOp, Commutable>;
2705 // Neon Long 3-register vector operations.
2707 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2708 InstrItinClass itin16, InstrItinClass itin32,
2709 string OpcodeStr, string Dt,
2710 SDNode OpNode, bit Commutable = 0> {
2711 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
2712 OpcodeStr, !strconcat(Dt, "8"),
2713 v8i16, v8i8, OpNode, Commutable>;
2714 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
2715 OpcodeStr, !strconcat(Dt, "16"),
2716 v4i32, v4i16, OpNode, Commutable>;
2717 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
2718 OpcodeStr, !strconcat(Dt, "32"),
2719 v2i64, v2i32, OpNode, Commutable>;
2722 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
2723 InstrItinClass itin, string OpcodeStr, string Dt,
2725 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
2726 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2727 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
2728 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2731 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2732 InstrItinClass itin16, InstrItinClass itin32,
2733 string OpcodeStr, string Dt,
2734 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2735 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
2736 OpcodeStr, !strconcat(Dt, "8"),
2737 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2738 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
2739 OpcodeStr, !strconcat(Dt, "16"),
2740 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2741 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
2742 OpcodeStr, !strconcat(Dt, "32"),
2743 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2746 // Neon Long 3-register vector intrinsics.
2748 // First with only element sizes of 16 and 32 bits:
2749 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2750 InstrItinClass itin16, InstrItinClass itin32,
2751 string OpcodeStr, string Dt,
2752 Intrinsic IntOp, bit Commutable = 0> {
2753 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
2754 OpcodeStr, !strconcat(Dt, "16"),
2755 v4i32, v4i16, IntOp, Commutable>;
2756 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
2757 OpcodeStr, !strconcat(Dt, "32"),
2758 v2i64, v2i32, IntOp, Commutable>;
2761 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
2762 InstrItinClass itin, string OpcodeStr, string Dt,
2764 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
2765 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2766 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
2767 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2770 // ....then also with element size of 8 bits:
2771 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2772 InstrItinClass itin16, InstrItinClass itin32,
2773 string OpcodeStr, string Dt,
2774 Intrinsic IntOp, bit Commutable = 0>
2775 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
2776 IntOp, Commutable> {
2777 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
2778 OpcodeStr, !strconcat(Dt, "8"),
2779 v8i16, v8i8, IntOp, Commutable>;
2782 // ....with explicit extend (VABDL).
2783 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2784 InstrItinClass itin, string OpcodeStr, string Dt,
2785 Intrinsic IntOp, SDNode ExtOp, bit Commutable = 0> {
2786 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
2787 OpcodeStr, !strconcat(Dt, "8"),
2788 v8i16, v8i8, IntOp, ExtOp, Commutable>;
2789 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
2790 OpcodeStr, !strconcat(Dt, "16"),
2791 v4i32, v4i16, IntOp, ExtOp, Commutable>;
2792 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
2793 OpcodeStr, !strconcat(Dt, "32"),
2794 v2i64, v2i32, IntOp, ExtOp, Commutable>;
2798 // Neon Wide 3-register vector intrinsics,
2799 // source operand element sizes of 8, 16 and 32 bits:
2800 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2801 string OpcodeStr, string Dt,
2802 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2803 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
2804 OpcodeStr, !strconcat(Dt, "8"),
2805 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2806 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
2807 OpcodeStr, !strconcat(Dt, "16"),
2808 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2809 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
2810 OpcodeStr, !strconcat(Dt, "32"),
2811 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2815 // Neon Multiply-Op vector operations,
2816 // element sizes of 8, 16 and 32 bits:
2817 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2818 InstrItinClass itinD16, InstrItinClass itinD32,
2819 InstrItinClass itinQ16, InstrItinClass itinQ32,
2820 string OpcodeStr, string Dt, SDNode OpNode> {
2821 // 64-bit vector types.
2822 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
2823 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
2824 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
2825 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
2826 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
2827 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
2829 // 128-bit vector types.
2830 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
2831 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
2832 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
2833 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
2834 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
2835 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
2838 multiclass N3VMulOpSL_HS<bits<4> op11_8,
2839 InstrItinClass itinD16, InstrItinClass itinD32,
2840 InstrItinClass itinQ16, InstrItinClass itinQ32,
2841 string OpcodeStr, string Dt, SDNode ShOp> {
2842 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
2843 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
2844 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
2845 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
2846 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
2847 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
2849 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
2850 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
2854 // Neon Intrinsic-Op vector operations,
2855 // element sizes of 8, 16 and 32 bits:
2856 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2857 InstrItinClass itinD, InstrItinClass itinQ,
2858 string OpcodeStr, string Dt, Intrinsic IntOp,
2860 // 64-bit vector types.
2861 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
2862 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
2863 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
2864 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
2865 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
2866 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
2868 // 128-bit vector types.
2869 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
2870 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
2871 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
2872 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
2873 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
2874 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
2877 // Neon 3-argument intrinsics,
2878 // element sizes of 8, 16 and 32 bits:
2879 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2880 InstrItinClass itinD, InstrItinClass itinQ,
2881 string OpcodeStr, string Dt, Intrinsic IntOp> {
2882 // 64-bit vector types.
2883 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
2884 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2885 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
2886 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
2887 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
2888 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
2890 // 128-bit vector types.
2891 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
2892 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
2893 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
2894 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
2895 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
2896 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
2900 // Neon Long Multiply-Op vector operations,
2901 // element sizes of 8, 16 and 32 bits:
2902 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2903 InstrItinClass itin16, InstrItinClass itin32,
2904 string OpcodeStr, string Dt, SDNode MulOp,
2906 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
2907 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
2908 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
2909 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
2910 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
2911 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
2914 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
2915 string Dt, SDNode MulOp, SDNode OpNode> {
2916 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
2917 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
2918 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
2919 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
2923 // Neon Long 3-argument intrinsics.
2925 // First with only element sizes of 16 and 32 bits:
2926 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2927 InstrItinClass itin16, InstrItinClass itin32,
2928 string OpcodeStr, string Dt, Intrinsic IntOp> {
2929 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
2930 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2931 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
2932 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2935 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
2936 string OpcodeStr, string Dt, Intrinsic IntOp> {
2937 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
2938 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
2939 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
2940 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2943 // ....then also with element size of 8 bits:
2944 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2945 InstrItinClass itin16, InstrItinClass itin32,
2946 string OpcodeStr, string Dt, Intrinsic IntOp>
2947 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
2948 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
2949 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
2952 // ....with explicit extend (VABAL).
2953 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2954 InstrItinClass itin, string OpcodeStr, string Dt,
2955 Intrinsic IntOp, SDNode ExtOp, SDNode OpNode> {
2956 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
2957 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
2958 IntOp, ExtOp, OpNode>;
2959 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
2960 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
2961 IntOp, ExtOp, OpNode>;
2962 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
2963 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
2964 IntOp, ExtOp, OpNode>;
2968 // Neon Pairwise long 2-register intrinsics,
2969 // element sizes of 8, 16 and 32 bits:
2970 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2971 bits<5> op11_7, bit op4,
2972 string OpcodeStr, string Dt, Intrinsic IntOp> {
2973 // 64-bit vector types.
2974 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2975 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
2976 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2977 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
2978 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2979 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
2981 // 128-bit vector types.
2982 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2983 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
2984 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2985 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
2986 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2987 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
2991 // Neon Pairwise long 2-register accumulate intrinsics,
2992 // element sizes of 8, 16 and 32 bits:
2993 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2994 bits<5> op11_7, bit op4,
2995 string OpcodeStr, string Dt, Intrinsic IntOp> {
2996 // 64-bit vector types.
2997 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2998 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
2999 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3000 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3001 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3002 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3004 // 128-bit vector types.
3005 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3006 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3007 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3008 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3009 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3010 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3014 // Neon 2-register vector shift by immediate,
3015 // with f of either N2RegVShLFrm or N2RegVShRFrm
3016 // element sizes of 8, 16, 32 and 64 bits:
3017 multiclass N2VShL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3018 InstrItinClass itin, string OpcodeStr, string Dt,
3020 // 64-bit vector types.
3021 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3022 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3023 let Inst{21-19} = 0b001; // imm6 = 001xxx
3025 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3026 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3027 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3029 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3030 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3031 let Inst{21} = 0b1; // imm6 = 1xxxxx
3033 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3034 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3037 // 128-bit vector types.
3038 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3039 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3040 let Inst{21-19} = 0b001; // imm6 = 001xxx
3042 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3043 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3044 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3046 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3047 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3048 let Inst{21} = 0b1; // imm6 = 1xxxxx
3050 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3051 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3054 multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3055 InstrItinClass itin, string OpcodeStr, string Dt,
3057 // 64-bit vector types.
3058 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3059 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3060 let Inst{21-19} = 0b001; // imm6 = 001xxx
3062 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3063 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3064 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3066 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3067 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3068 let Inst{21} = 0b1; // imm6 = 1xxxxx
3070 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3071 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3074 // 128-bit vector types.
3075 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3076 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3077 let Inst{21-19} = 0b001; // imm6 = 001xxx
3079 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3080 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3081 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3083 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3084 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3085 let Inst{21} = 0b1; // imm6 = 1xxxxx
3087 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3088 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3092 // Neon Shift-Accumulate vector operations,
3093 // element sizes of 8, 16, 32 and 64 bits:
3094 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3095 string OpcodeStr, string Dt, SDNode ShOp> {
3096 // 64-bit vector types.
3097 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3098 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
3099 let Inst{21-19} = 0b001; // imm6 = 001xxx
3101 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3102 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
3103 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3105 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3106 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
3107 let Inst{21} = 0b1; // imm6 = 1xxxxx
3109 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3110 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
3113 // 128-bit vector types.
3114 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3115 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
3116 let Inst{21-19} = 0b001; // imm6 = 001xxx
3118 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3119 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
3120 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3122 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3123 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
3124 let Inst{21} = 0b1; // imm6 = 1xxxxx
3126 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3127 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
3131 // Neon Shift-Insert vector operations,
3132 // with f of either N2RegVShLFrm or N2RegVShRFrm
3133 // element sizes of 8, 16, 32 and 64 bits:
3134 multiclass N2VShInsL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3136 // 64-bit vector types.
3137 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3138 N2RegVShLFrm, OpcodeStr, "8", v8i8, NEONvsli> {
3139 let Inst{21-19} = 0b001; // imm6 = 001xxx
3141 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3142 N2RegVShLFrm, OpcodeStr, "16", v4i16, NEONvsli> {
3143 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3145 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3146 N2RegVShLFrm, OpcodeStr, "32", v2i32, NEONvsli> {
3147 let Inst{21} = 0b1; // imm6 = 1xxxxx
3149 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, i32imm,
3150 N2RegVShLFrm, OpcodeStr, "64", v1i64, NEONvsli>;
3153 // 128-bit vector types.
3154 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3155 N2RegVShLFrm, OpcodeStr, "8", v16i8, NEONvsli> {
3156 let Inst{21-19} = 0b001; // imm6 = 001xxx
3158 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3159 N2RegVShLFrm, OpcodeStr, "16", v8i16, NEONvsli> {
3160 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3162 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3163 N2RegVShLFrm, OpcodeStr, "32", v4i32, NEONvsli> {
3164 let Inst{21} = 0b1; // imm6 = 1xxxxx
3166 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, i32imm,
3167 N2RegVShLFrm, OpcodeStr, "64", v2i64, NEONvsli>;
3170 multiclass N2VShInsR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3172 // 64-bit vector types.
3173 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3174 N2RegVShRFrm, OpcodeStr, "8", v8i8, NEONvsri> {
3175 let Inst{21-19} = 0b001; // imm6 = 001xxx
3177 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3178 N2RegVShRFrm, OpcodeStr, "16", v4i16, NEONvsri> {
3179 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3181 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3182 N2RegVShRFrm, OpcodeStr, "32", v2i32, NEONvsri> {
3183 let Inst{21} = 0b1; // imm6 = 1xxxxx
3185 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3186 N2RegVShRFrm, OpcodeStr, "64", v1i64, NEONvsri>;
3189 // 128-bit vector types.
3190 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3191 N2RegVShRFrm, OpcodeStr, "8", v16i8, NEONvsri> {
3192 let Inst{21-19} = 0b001; // imm6 = 001xxx
3194 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3195 N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsri> {
3196 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3198 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3199 N2RegVShRFrm, OpcodeStr, "32", v4i32, NEONvsri> {
3200 let Inst{21} = 0b1; // imm6 = 1xxxxx
3202 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3203 N2RegVShRFrm, OpcodeStr, "64", v2i64, NEONvsri>;
3207 // Neon Shift Long operations,
3208 // element sizes of 8, 16, 32 bits:
3209 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3210 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
3211 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3212 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
3213 let Inst{21-19} = 0b001; // imm6 = 001xxx
3215 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3216 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
3217 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3219 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3220 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
3221 let Inst{21} = 0b1; // imm6 = 1xxxxx
3225 // Neon Shift Narrow operations,
3226 // element sizes of 16, 32, 64 bits:
3227 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3228 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
3230 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3231 OpcodeStr, !strconcat(Dt, "16"),
3232 v8i8, v8i16, shr_imm8, OpNode> {
3233 let Inst{21-19} = 0b001; // imm6 = 001xxx
3235 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3236 OpcodeStr, !strconcat(Dt, "32"),
3237 v4i16, v4i32, shr_imm16, OpNode> {
3238 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3240 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3241 OpcodeStr, !strconcat(Dt, "64"),
3242 v2i32, v2i64, shr_imm32, OpNode> {
3243 let Inst{21} = 0b1; // imm6 = 1xxxxx
3247 //===----------------------------------------------------------------------===//
3248 // Instruction Definitions.
3249 //===----------------------------------------------------------------------===//
3251 // Vector Add Operations.
3253 // VADD : Vector Add (integer and floating-point)
3254 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
3256 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
3257 v2f32, v2f32, fadd, 1>;
3258 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
3259 v4f32, v4f32, fadd, 1>;
3260 // VADDL : Vector Add Long (Q = D + D)
3261 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3262 "vaddl", "s", add, sext, 1>;
3263 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3264 "vaddl", "u", add, zext, 1>;
3265 // VADDW : Vector Add Wide (Q = Q + D)
3266 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
3267 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
3268 // VHADD : Vector Halving Add
3269 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
3270 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3271 "vhadd", "s", int_arm_neon_vhadds, 1>;
3272 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
3273 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3274 "vhadd", "u", int_arm_neon_vhaddu, 1>;
3275 // VRHADD : Vector Rounding Halving Add
3276 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
3277 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3278 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
3279 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
3280 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3281 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
3282 // VQADD : Vector Saturating Add
3283 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
3284 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3285 "vqadd", "s", int_arm_neon_vqadds, 1>;
3286 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
3287 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3288 "vqadd", "u", int_arm_neon_vqaddu, 1>;
3289 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
3290 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
3291 int_arm_neon_vaddhn, 1>;
3292 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
3293 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
3294 int_arm_neon_vraddhn, 1>;
3296 // Vector Multiply Operations.
3298 // VMUL : Vector Multiply (integer, polynomial and floating-point)
3299 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
3300 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
3301 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
3302 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
3303 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
3304 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
3305 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
3306 v2f32, v2f32, fmul, 1>;
3307 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
3308 v4f32, v4f32, fmul, 1>;
3309 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
3310 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
3311 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
3314 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
3315 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
3316 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
3317 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3318 (DSubReg_i16_reg imm:$lane))),
3319 (SubReg_i16_lane imm:$lane)))>;
3320 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
3321 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
3322 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
3323 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3324 (DSubReg_i32_reg imm:$lane))),
3325 (SubReg_i32_lane imm:$lane)))>;
3326 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
3327 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
3328 (v4f32 (VMULslfq (v4f32 QPR:$src1),
3329 (v2f32 (EXTRACT_SUBREG QPR:$src2,
3330 (DSubReg_i32_reg imm:$lane))),
3331 (SubReg_i32_lane imm:$lane)))>;
3333 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
3334 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
3335 IIC_VMULi16Q, IIC_VMULi32Q,
3336 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
3337 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
3338 IIC_VMULi16Q, IIC_VMULi32Q,
3339 "vqdmulh", "s", int_arm_neon_vqdmulh>;
3340 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
3341 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3343 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
3344 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3345 (DSubReg_i16_reg imm:$lane))),
3346 (SubReg_i16_lane imm:$lane)))>;
3347 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
3348 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3350 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
3351 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3352 (DSubReg_i32_reg imm:$lane))),
3353 (SubReg_i32_lane imm:$lane)))>;
3355 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
3356 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
3357 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
3358 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
3359 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
3360 IIC_VMULi16Q, IIC_VMULi32Q,
3361 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
3362 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
3363 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3365 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
3366 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3367 (DSubReg_i16_reg imm:$lane))),
3368 (SubReg_i16_lane imm:$lane)))>;
3369 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
3370 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3372 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
3373 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3374 (DSubReg_i32_reg imm:$lane))),
3375 (SubReg_i32_lane imm:$lane)))>;
3377 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
3378 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3379 "vmull", "s", NEONvmulls, 1>;
3380 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3381 "vmull", "u", NEONvmullu, 1>;
3382 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
3383 v8i16, v8i8, int_arm_neon_vmullp, 1>;
3384 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
3385 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
3387 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
3388 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
3389 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
3390 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
3391 "vqdmull", "s", int_arm_neon_vqdmull>;
3393 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
3395 // VMLA : Vector Multiply Accumulate (integer and floating-point)
3396 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3397 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3398 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
3399 v2f32, fmul_su, fadd_mlx>,
3400 Requires<[HasNEON, UseFPVMLx]>;
3401 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
3402 v4f32, fmul_su, fadd_mlx>,
3403 Requires<[HasNEON, UseFPVMLx]>;
3404 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
3405 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3406 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
3407 v2f32, fmul_su, fadd_mlx>,
3408 Requires<[HasNEON, UseFPVMLx]>;
3409 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
3410 v4f32, v2f32, fmul_su, fadd_mlx>,
3411 Requires<[HasNEON, UseFPVMLx]>;
3413 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
3414 (mul (v8i16 QPR:$src2),
3415 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3416 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3417 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3418 (DSubReg_i16_reg imm:$lane))),
3419 (SubReg_i16_lane imm:$lane)))>;
3421 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
3422 (mul (v4i32 QPR:$src2),
3423 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3424 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3425 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3426 (DSubReg_i32_reg imm:$lane))),
3427 (SubReg_i32_lane imm:$lane)))>;
3429 def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1),
3430 (fmul_su (v4f32 QPR:$src2),
3431 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3432 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
3434 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3435 (DSubReg_i32_reg imm:$lane))),
3436 (SubReg_i32_lane imm:$lane)))>,
3437 Requires<[HasNEON, UseFPVMLx]>;
3439 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
3440 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3441 "vmlal", "s", NEONvmulls, add>;
3442 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3443 "vmlal", "u", NEONvmullu, add>;
3445 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
3446 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
3448 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
3449 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3450 "vqdmlal", "s", int_arm_neon_vqdmlal>;
3451 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
3453 // VMLS : Vector Multiply Subtract (integer and floating-point)
3454 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3455 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3456 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
3457 v2f32, fmul_su, fsub_mlx>,
3458 Requires<[HasNEON, UseFPVMLx]>;
3459 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
3460 v4f32, fmul_su, fsub_mlx>,
3461 Requires<[HasNEON, UseFPVMLx]>;
3462 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
3463 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3464 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
3465 v2f32, fmul_su, fsub_mlx>,
3466 Requires<[HasNEON, UseFPVMLx]>;
3467 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
3468 v4f32, v2f32, fmul_su, fsub_mlx>,
3469 Requires<[HasNEON, UseFPVMLx]>;
3471 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
3472 (mul (v8i16 QPR:$src2),
3473 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3474 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3475 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3476 (DSubReg_i16_reg imm:$lane))),
3477 (SubReg_i16_lane imm:$lane)))>;
3479 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
3480 (mul (v4i32 QPR:$src2),
3481 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3482 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3483 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3484 (DSubReg_i32_reg imm:$lane))),
3485 (SubReg_i32_lane imm:$lane)))>;
3487 def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1),
3488 (fmul_su (v4f32 QPR:$src2),
3489 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3490 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
3491 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3492 (DSubReg_i32_reg imm:$lane))),
3493 (SubReg_i32_lane imm:$lane)))>,
3494 Requires<[HasNEON, UseFPVMLx]>;
3496 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
3497 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3498 "vmlsl", "s", NEONvmulls, sub>;
3499 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3500 "vmlsl", "u", NEONvmullu, sub>;
3502 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
3503 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
3505 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
3506 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
3507 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3508 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3510 // Vector Subtract Operations.
3512 // VSUB : Vector Subtract (integer and floating-point)
3513 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
3514 "vsub", "i", sub, 0>;
3515 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
3516 v2f32, v2f32, fsub, 0>;
3517 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
3518 v4f32, v4f32, fsub, 0>;
3519 // VSUBL : Vector Subtract Long (Q = D - D)
3520 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3521 "vsubl", "s", sub, sext, 0>;
3522 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3523 "vsubl", "u", sub, zext, 0>;
3524 // VSUBW : Vector Subtract Wide (Q = Q - D)
3525 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
3526 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
3527 // VHSUB : Vector Halving Subtract
3528 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
3529 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3530 "vhsub", "s", int_arm_neon_vhsubs, 0>;
3531 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
3532 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3533 "vhsub", "u", int_arm_neon_vhsubu, 0>;
3534 // VQSUB : Vector Saturing Subtract
3535 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
3536 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3537 "vqsub", "s", int_arm_neon_vqsubs, 0>;
3538 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
3539 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3540 "vqsub", "u", int_arm_neon_vqsubu, 0>;
3541 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
3542 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
3543 int_arm_neon_vsubhn, 0>;
3544 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
3545 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
3546 int_arm_neon_vrsubhn, 0>;
3548 // Vector Comparisons.
3550 // VCEQ : Vector Compare Equal
3551 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3552 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
3553 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
3555 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
3558 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
3559 "$Vd, $Vm, #0", NEONvceqz>;
3561 // VCGE : Vector Compare Greater Than or Equal
3562 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3563 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
3564 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3565 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
3566 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
3568 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
3571 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
3572 "$Vd, $Vm, #0", NEONvcgez>;
3573 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
3574 "$Vd, $Vm, #0", NEONvclez>;
3576 // VCGT : Vector Compare Greater Than
3577 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3578 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
3579 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3580 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
3581 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
3583 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
3586 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
3587 "$Vd, $Vm, #0", NEONvcgtz>;
3588 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
3589 "$Vd, $Vm, #0", NEONvcltz>;
3591 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
3592 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
3593 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
3594 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
3595 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
3596 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
3597 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
3598 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
3599 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
3600 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
3601 // VTST : Vector Test Bits
3602 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
3603 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
3605 // Vector Bitwise Operations.
3607 def vnotd : PatFrag<(ops node:$in),
3608 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
3609 def vnotq : PatFrag<(ops node:$in),
3610 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
3613 // VAND : Vector Bitwise AND
3614 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
3615 v2i32, v2i32, and, 1>;
3616 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
3617 v4i32, v4i32, and, 1>;
3619 // VEOR : Vector Bitwise Exclusive OR
3620 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
3621 v2i32, v2i32, xor, 1>;
3622 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
3623 v4i32, v4i32, xor, 1>;
3625 // VORR : Vector Bitwise OR
3626 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
3627 v2i32, v2i32, or, 1>;
3628 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
3629 v4i32, v4i32, or, 1>;
3631 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
3632 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3634 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3636 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3637 let Inst{9} = SIMM{9};
3640 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
3641 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3643 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3645 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3646 let Inst{10-9} = SIMM{10-9};
3649 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
3650 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3652 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3654 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3655 let Inst{9} = SIMM{9};
3658 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
3659 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3661 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3663 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3664 let Inst{10-9} = SIMM{10-9};
3668 // VBIC : Vector Bitwise Bit Clear (AND NOT)
3669 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
3670 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
3671 "vbic", "$Vd, $Vn, $Vm", "",
3672 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
3673 (vnotd DPR:$Vm))))]>;
3674 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
3675 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
3676 "vbic", "$Vd, $Vn, $Vm", "",
3677 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
3678 (vnotq QPR:$Vm))))]>;
3680 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
3681 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3683 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3685 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3686 let Inst{9} = SIMM{9};
3689 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
3690 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3692 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3694 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3695 let Inst{10-9} = SIMM{10-9};
3698 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
3699 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3701 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3703 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3704 let Inst{9} = SIMM{9};
3707 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
3708 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3710 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3712 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3713 let Inst{10-9} = SIMM{10-9};
3716 // VORN : Vector Bitwise OR NOT
3717 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
3718 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
3719 "vorn", "$Vd, $Vn, $Vm", "",
3720 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
3721 (vnotd DPR:$Vm))))]>;
3722 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
3723 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
3724 "vorn", "$Vd, $Vn, $Vm", "",
3725 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
3726 (vnotq QPR:$Vm))))]>;
3728 // VMVN : Vector Bitwise NOT (Immediate)
3730 let isReMaterializable = 1 in {
3732 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
3733 (ins nModImm:$SIMM), IIC_VMOVImm,
3734 "vmvn", "i16", "$Vd, $SIMM", "",
3735 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
3736 let Inst{9} = SIMM{9};
3739 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
3740 (ins nModImm:$SIMM), IIC_VMOVImm,
3741 "vmvn", "i16", "$Vd, $SIMM", "",
3742 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
3743 let Inst{9} = SIMM{9};
3746 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
3747 (ins nModImm:$SIMM), IIC_VMOVImm,
3748 "vmvn", "i32", "$Vd, $SIMM", "",
3749 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
3750 let Inst{11-8} = SIMM{11-8};
3753 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
3754 (ins nModImm:$SIMM), IIC_VMOVImm,
3755 "vmvn", "i32", "$Vd, $SIMM", "",
3756 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
3757 let Inst{11-8} = SIMM{11-8};
3761 // VMVN : Vector Bitwise NOT
3762 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
3763 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
3764 "vmvn", "$Vd, $Vm", "",
3765 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
3766 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
3767 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
3768 "vmvn", "$Vd, $Vm", "",
3769 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
3770 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
3771 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
3773 // VBSL : Vector Bitwise Select
3774 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
3775 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3776 N3RegFrm, IIC_VCNTiD,
3777 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3779 (v2i32 (or (and DPR:$Vn, DPR:$src1),
3780 (and DPR:$Vm, (vnotd DPR:$src1)))))]>;
3781 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
3782 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3783 N3RegFrm, IIC_VCNTiQ,
3784 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3786 (v4i32 (or (and QPR:$Vn, QPR:$src1),
3787 (and QPR:$Vm, (vnotq QPR:$src1)))))]>;
3789 // VBIF : Vector Bitwise Insert if False
3790 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
3791 // FIXME: This instruction's encoding MAY NOT BE correct.
3792 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
3793 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3794 N3RegFrm, IIC_VBINiD,
3795 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3796 [/* For disassembly only; pattern left blank */]>;
3797 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
3798 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3799 N3RegFrm, IIC_VBINiQ,
3800 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3801 [/* For disassembly only; pattern left blank */]>;
3803 // VBIT : Vector Bitwise Insert if True
3804 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
3805 // FIXME: This instruction's encoding MAY NOT BE correct.
3806 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
3807 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3808 N3RegFrm, IIC_VBINiD,
3809 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3810 [/* For disassembly only; pattern left blank */]>;
3811 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
3812 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3813 N3RegFrm, IIC_VBINiQ,
3814 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3815 [/* For disassembly only; pattern left blank */]>;
3817 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
3818 // for equivalent operations with different register constraints; it just
3821 // Vector Absolute Differences.
3823 // VABD : Vector Absolute Difference
3824 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
3825 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3826 "vabd", "s", int_arm_neon_vabds, 1>;
3827 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
3828 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3829 "vabd", "u", int_arm_neon_vabdu, 1>;
3830 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
3831 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
3832 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
3833 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
3835 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
3836 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
3837 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
3838 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
3839 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
3841 // VABA : Vector Absolute Difference and Accumulate
3842 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3843 "vaba", "s", int_arm_neon_vabds, add>;
3844 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3845 "vaba", "u", int_arm_neon_vabdu, add>;
3847 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
3848 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
3849 "vabal", "s", int_arm_neon_vabds, zext, add>;
3850 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
3851 "vabal", "u", int_arm_neon_vabdu, zext, add>;
3853 // Vector Maximum and Minimum.
3855 // VMAX : Vector Maximum
3856 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
3857 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3858 "vmax", "s", int_arm_neon_vmaxs, 1>;
3859 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
3860 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3861 "vmax", "u", int_arm_neon_vmaxu, 1>;
3862 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
3864 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
3865 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
3867 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
3869 // VMIN : Vector Minimum
3870 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
3871 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3872 "vmin", "s", int_arm_neon_vmins, 1>;
3873 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
3874 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3875 "vmin", "u", int_arm_neon_vminu, 1>;
3876 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
3878 v2f32, v2f32, int_arm_neon_vmins, 1>;
3879 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
3881 v4f32, v4f32, int_arm_neon_vmins, 1>;
3883 // Vector Pairwise Operations.
3885 // VPADD : Vector Pairwise Add
3886 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3888 v8i8, v8i8, int_arm_neon_vpadd, 0>;
3889 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3891 v4i16, v4i16, int_arm_neon_vpadd, 0>;
3892 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3894 v2i32, v2i32, int_arm_neon_vpadd, 0>;
3895 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
3896 IIC_VPBIND, "vpadd", "f32",
3897 v2f32, v2f32, int_arm_neon_vpadd, 0>;
3899 // VPADDL : Vector Pairwise Add Long
3900 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
3901 int_arm_neon_vpaddls>;
3902 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
3903 int_arm_neon_vpaddlu>;
3905 // VPADAL : Vector Pairwise Add and Accumulate Long
3906 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
3907 int_arm_neon_vpadals>;
3908 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
3909 int_arm_neon_vpadalu>;
3911 // VPMAX : Vector Pairwise Maximum
3912 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3913 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
3914 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3915 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
3916 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3917 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
3918 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3919 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
3920 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3921 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
3922 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3923 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
3924 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
3925 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
3927 // VPMIN : Vector Pairwise Minimum
3928 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3929 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
3930 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3931 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
3932 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3933 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
3934 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3935 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
3936 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3937 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
3938 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3939 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
3940 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
3941 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
3943 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
3945 // VRECPE : Vector Reciprocal Estimate
3946 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
3947 IIC_VUNAD, "vrecpe", "u32",
3948 v2i32, v2i32, int_arm_neon_vrecpe>;
3949 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
3950 IIC_VUNAQ, "vrecpe", "u32",
3951 v4i32, v4i32, int_arm_neon_vrecpe>;
3952 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
3953 IIC_VUNAD, "vrecpe", "f32",
3954 v2f32, v2f32, int_arm_neon_vrecpe>;
3955 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
3956 IIC_VUNAQ, "vrecpe", "f32",
3957 v4f32, v4f32, int_arm_neon_vrecpe>;
3959 // VRECPS : Vector Reciprocal Step
3960 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
3961 IIC_VRECSD, "vrecps", "f32",
3962 v2f32, v2f32, int_arm_neon_vrecps, 1>;
3963 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
3964 IIC_VRECSQ, "vrecps", "f32",
3965 v4f32, v4f32, int_arm_neon_vrecps, 1>;
3967 // VRSQRTE : Vector Reciprocal Square Root Estimate
3968 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
3969 IIC_VUNAD, "vrsqrte", "u32",
3970 v2i32, v2i32, int_arm_neon_vrsqrte>;
3971 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
3972 IIC_VUNAQ, "vrsqrte", "u32",
3973 v4i32, v4i32, int_arm_neon_vrsqrte>;
3974 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
3975 IIC_VUNAD, "vrsqrte", "f32",
3976 v2f32, v2f32, int_arm_neon_vrsqrte>;
3977 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
3978 IIC_VUNAQ, "vrsqrte", "f32",
3979 v4f32, v4f32, int_arm_neon_vrsqrte>;
3981 // VRSQRTS : Vector Reciprocal Square Root Step
3982 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
3983 IIC_VRECSD, "vrsqrts", "f32",
3984 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
3985 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
3986 IIC_VRECSQ, "vrsqrts", "f32",
3987 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
3991 // VSHL : Vector Shift
3992 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
3993 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
3994 "vshl", "s", int_arm_neon_vshifts>;
3995 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
3996 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
3997 "vshl", "u", int_arm_neon_vshiftu>;
3999 // VSHL : Vector Shift Left (Immediate)
4000 defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
4002 // VSHR : Vector Shift Right (Immediate)
4003 defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s",NEONvshrs>;
4004 defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u",NEONvshru>;
4006 // VSHLL : Vector Shift Left Long
4007 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
4008 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
4010 // VSHLL : Vector Shift Left Long (with maximum shift count)
4011 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
4012 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
4013 ValueType OpTy, SDNode OpNode>
4014 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
4015 ResTy, OpTy, OpNode> {
4016 let Inst{21-16} = op21_16;
4018 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
4019 v8i16, v8i8, NEONvshlli>;
4020 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
4021 v4i32, v4i16, NEONvshlli>;
4022 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
4023 v2i64, v2i32, NEONvshlli>;
4025 // VSHRN : Vector Shift Right and Narrow
4026 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
4029 // VRSHL : Vector Rounding Shift
4030 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
4031 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4032 "vrshl", "s", int_arm_neon_vrshifts>;
4033 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
4034 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4035 "vrshl", "u", int_arm_neon_vrshiftu>;
4036 // VRSHR : Vector Rounding Shift Right
4037 defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s",NEONvrshrs>;
4038 defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u",NEONvrshru>;
4040 // VRSHRN : Vector Rounding Shift Right and Narrow
4041 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
4044 // VQSHL : Vector Saturating Shift
4045 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
4046 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4047 "vqshl", "s", int_arm_neon_vqshifts>;
4048 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
4049 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4050 "vqshl", "u", int_arm_neon_vqshiftu>;
4051 // VQSHL : Vector Saturating Shift Left (Immediate)
4052 defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls>;
4053 defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu>;
4055 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
4056 defm VQSHLsu : N2VShL_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu>;
4058 // VQSHRN : Vector Saturating Shift Right and Narrow
4059 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
4061 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
4064 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
4065 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
4068 // VQRSHL : Vector Saturating Rounding Shift
4069 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
4070 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4071 "vqrshl", "s", int_arm_neon_vqrshifts>;
4072 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
4073 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4074 "vqrshl", "u", int_arm_neon_vqrshiftu>;
4076 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
4077 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
4079 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
4082 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
4083 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
4086 // VSRA : Vector Shift Right and Accumulate
4087 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
4088 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
4089 // VRSRA : Vector Rounding Shift Right and Accumulate
4090 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
4091 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
4093 // VSLI : Vector Shift Left and Insert
4094 defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">;
4096 // VSRI : Vector Shift Right and Insert
4097 defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;
4099 // Vector Absolute and Saturating Absolute.
4101 // VABS : Vector Absolute Value
4102 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
4103 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
4105 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4106 IIC_VUNAD, "vabs", "f32",
4107 v2f32, v2f32, int_arm_neon_vabs>;
4108 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4109 IIC_VUNAQ, "vabs", "f32",
4110 v4f32, v4f32, int_arm_neon_vabs>;
4112 // VQABS : Vector Saturating Absolute Value
4113 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
4114 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
4115 int_arm_neon_vqabs>;
4119 def vnegd : PatFrag<(ops node:$in),
4120 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
4121 def vnegq : PatFrag<(ops node:$in),
4122 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
4124 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4125 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
4126 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
4127 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
4128 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4129 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
4130 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
4131 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
4133 // VNEG : Vector Negate (integer)
4134 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
4135 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
4136 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
4137 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
4138 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
4139 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
4141 // VNEG : Vector Negate (floating-point)
4142 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
4143 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
4144 "vneg", "f32", "$Vd, $Vm", "",
4145 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
4146 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
4147 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
4148 "vneg", "f32", "$Vd, $Vm", "",
4149 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
4151 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
4152 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
4153 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
4154 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
4155 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
4156 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
4158 // VQNEG : Vector Saturating Negate
4159 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
4160 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
4161 int_arm_neon_vqneg>;
4163 // Vector Bit Counting Operations.
4165 // VCLS : Vector Count Leading Sign Bits
4166 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
4167 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
4169 // VCLZ : Vector Count Leading Zeros
4170 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
4171 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
4173 // VCNT : Vector Count One Bits
4174 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4175 IIC_VCNTiD, "vcnt", "8",
4176 v8i8, v8i8, int_arm_neon_vcnt>;
4177 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4178 IIC_VCNTiQ, "vcnt", "8",
4179 v16i8, v16i8, int_arm_neon_vcnt>;
4181 // Vector Swap -- for disassembly only.
4182 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
4183 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
4184 "vswp", "$Vd, $Vm", "", []>;
4185 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
4186 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
4187 "vswp", "$Vd, $Vm", "", []>;
4189 // Vector Move Operations.
4191 // VMOV : Vector Move (Register)
4193 let neverHasSideEffects = 1 in {
4194 def VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$Vd), (ins DPR:$Vm),
4195 N3RegFrm, IIC_VMOV, "vmov", "$Vd, $Vm", "", []> {
4196 let Vn{4-0} = Vm{4-0};
4198 def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$Vd), (ins QPR:$Vm),
4199 N3RegFrm, IIC_VMOV, "vmov", "$Vd, $Vm", "", []> {
4200 let Vn{4-0} = Vm{4-0};
4203 // Pseudo vector move instructions for QQ and QQQQ registers. This should
4204 // be expanded after register allocation is completed.
4205 def VMOVQQ : PseudoInst<(outs QQPR:$dst), (ins QQPR:$src),
4208 def VMOVQQQQ : PseudoInst<(outs QQQQPR:$dst), (ins QQQQPR:$src),
4210 } // neverHasSideEffects
4212 // VMOV : Vector Move (Immediate)
4214 let isReMaterializable = 1 in {
4215 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
4216 (ins nModImm:$SIMM), IIC_VMOVImm,
4217 "vmov", "i8", "$Vd, $SIMM", "",
4218 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
4219 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
4220 (ins nModImm:$SIMM), IIC_VMOVImm,
4221 "vmov", "i8", "$Vd, $SIMM", "",
4222 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
4224 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
4225 (ins nModImm:$SIMM), IIC_VMOVImm,
4226 "vmov", "i16", "$Vd, $SIMM", "",
4227 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
4228 let Inst{9} = SIMM{9};
4231 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
4232 (ins nModImm:$SIMM), IIC_VMOVImm,
4233 "vmov", "i16", "$Vd, $SIMM", "",
4234 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
4235 let Inst{9} = SIMM{9};
4238 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
4239 (ins nModImm:$SIMM), IIC_VMOVImm,
4240 "vmov", "i32", "$Vd, $SIMM", "",
4241 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
4242 let Inst{11-8} = SIMM{11-8};
4245 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
4246 (ins nModImm:$SIMM), IIC_VMOVImm,
4247 "vmov", "i32", "$Vd, $SIMM", "",
4248 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
4249 let Inst{11-8} = SIMM{11-8};
4252 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
4253 (ins nModImm:$SIMM), IIC_VMOVImm,
4254 "vmov", "i64", "$Vd, $SIMM", "",
4255 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
4256 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
4257 (ins nModImm:$SIMM), IIC_VMOVImm,
4258 "vmov", "i64", "$Vd, $SIMM", "",
4259 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
4260 } // isReMaterializable
4262 // VMOV : Vector Get Lane (move scalar to ARM core register)
4264 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
4265 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4266 IIC_VMOVSI, "vmov", "s8", "$R, $V[$lane]",
4267 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
4269 let Inst{21} = lane{2};
4270 let Inst{6-5} = lane{1-0};
4272 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
4273 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4274 IIC_VMOVSI, "vmov", "s16", "$R, $V[$lane]",
4275 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
4277 let Inst{21} = lane{1};
4278 let Inst{6} = lane{0};
4280 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
4281 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4282 IIC_VMOVSI, "vmov", "u8", "$R, $V[$lane]",
4283 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
4285 let Inst{21} = lane{2};
4286 let Inst{6-5} = lane{1-0};
4288 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
4289 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4290 IIC_VMOVSI, "vmov", "u16", "$R, $V[$lane]",
4291 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
4293 let Inst{21} = lane{1};
4294 let Inst{6} = lane{0};
4296 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
4297 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4298 IIC_VMOVSI, "vmov", "32", "$R, $V[$lane]",
4299 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
4301 let Inst{21} = lane{0};
4303 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
4304 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
4305 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4306 (DSubReg_i8_reg imm:$lane))),
4307 (SubReg_i8_lane imm:$lane))>;
4308 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
4309 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4310 (DSubReg_i16_reg imm:$lane))),
4311 (SubReg_i16_lane imm:$lane))>;
4312 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
4313 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4314 (DSubReg_i8_reg imm:$lane))),
4315 (SubReg_i8_lane imm:$lane))>;
4316 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
4317 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4318 (DSubReg_i16_reg imm:$lane))),
4319 (SubReg_i16_lane imm:$lane))>;
4320 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
4321 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
4322 (DSubReg_i32_reg imm:$lane))),
4323 (SubReg_i32_lane imm:$lane))>;
4324 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
4325 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
4326 (SSubReg_f32_reg imm:$src2))>;
4327 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
4328 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
4329 (SSubReg_f32_reg imm:$src2))>;
4330 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
4331 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4332 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
4333 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4336 // VMOV : Vector Set Lane (move ARM core register to scalar)
4338 let Constraints = "$src1 = $V" in {
4339 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
4340 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4341 IIC_VMOVISL, "vmov", "8", "$V[$lane], $R",
4342 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
4343 GPR:$R, imm:$lane))]> {
4344 let Inst{21} = lane{2};
4345 let Inst{6-5} = lane{1-0};
4347 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
4348 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4349 IIC_VMOVISL, "vmov", "16", "$V[$lane], $R",
4350 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
4351 GPR:$R, imm:$lane))]> {
4352 let Inst{21} = lane{1};
4353 let Inst{6} = lane{0};
4355 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
4356 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4357 IIC_VMOVISL, "vmov", "32", "$V[$lane], $R",
4358 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
4359 GPR:$R, imm:$lane))]> {
4360 let Inst{21} = lane{0};
4363 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
4364 (v16i8 (INSERT_SUBREG QPR:$src1,
4365 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
4366 (DSubReg_i8_reg imm:$lane))),
4367 GPR:$src2, (SubReg_i8_lane imm:$lane))),
4368 (DSubReg_i8_reg imm:$lane)))>;
4369 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
4370 (v8i16 (INSERT_SUBREG QPR:$src1,
4371 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
4372 (DSubReg_i16_reg imm:$lane))),
4373 GPR:$src2, (SubReg_i16_lane imm:$lane))),
4374 (DSubReg_i16_reg imm:$lane)))>;
4375 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
4376 (v4i32 (INSERT_SUBREG QPR:$src1,
4377 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
4378 (DSubReg_i32_reg imm:$lane))),
4379 GPR:$src2, (SubReg_i32_lane imm:$lane))),
4380 (DSubReg_i32_reg imm:$lane)))>;
4382 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
4383 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
4384 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4385 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
4386 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
4387 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4389 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4390 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4391 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4392 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4394 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
4395 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4396 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
4397 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
4398 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
4399 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4401 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
4402 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4403 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
4404 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4405 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
4406 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4408 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
4409 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4410 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4412 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
4413 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
4414 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4416 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
4417 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4418 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4421 // VDUP : Vector Duplicate (from ARM core register to all elements)
4423 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4424 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
4425 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4426 [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4427 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4428 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
4429 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4430 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4432 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
4433 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
4434 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
4435 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
4436 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
4437 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
4439 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$V), (ins GPR:$R),
4440 IIC_VMOVIS, "vdup", "32", "$V, $R",
4441 [(set DPR:$V, (v2f32 (NEONvdup
4442 (f32 (bitconvert GPR:$R)))))]>;
4443 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$V), (ins GPR:$R),
4444 IIC_VMOVIS, "vdup", "32", "$V, $R",
4445 [(set QPR:$V, (v4f32 (NEONvdup
4446 (f32 (bitconvert GPR:$R)))))]>;
4448 // VDUP : Vector Duplicate Lane (from scalar to all elements)
4450 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
4452 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, nohash_imm:$lane),
4453 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm[$lane]",
4454 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
4456 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
4457 ValueType ResTy, ValueType OpTy>
4458 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, nohash_imm:$lane),
4459 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm[$lane]",
4460 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
4463 // Inst{19-16} is partially specified depending on the element size.
4465 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8> {
4466 let Inst{19-17} = lane{2-0};
4468 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16> {
4469 let Inst{19-18} = lane{1-0};
4471 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32> {
4472 let Inst{19} = lane{0};
4474 def VDUPLNfd : VDUPLND<{?,1,0,0}, "vdup", "32", v2f32> {
4475 let Inst{19} = lane{0};
4477 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8> {
4478 let Inst{19-17} = lane{2-0};
4480 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16> {
4481 let Inst{19-18} = lane{1-0};
4483 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32> {
4484 let Inst{19} = lane{0};
4486 def VDUPLNfq : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4f32, v2f32> {
4487 let Inst{19} = lane{0};
4490 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
4491 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
4492 (DSubReg_i8_reg imm:$lane))),
4493 (SubReg_i8_lane imm:$lane)))>;
4494 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
4495 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
4496 (DSubReg_i16_reg imm:$lane))),
4497 (SubReg_i16_lane imm:$lane)))>;
4498 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
4499 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
4500 (DSubReg_i32_reg imm:$lane))),
4501 (SubReg_i32_lane imm:$lane)))>;
4502 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
4503 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
4504 (DSubReg_i32_reg imm:$lane))),
4505 (SubReg_i32_lane imm:$lane)))>;
4507 def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4508 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
4509 def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4510 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
4512 // VMOVN : Vector Narrowing Move
4513 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
4514 "vmovn", "i", trunc>;
4515 // VQMOVN : Vector Saturating Narrowing Move
4516 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
4517 "vqmovn", "s", int_arm_neon_vqmovns>;
4518 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
4519 "vqmovn", "u", int_arm_neon_vqmovnu>;
4520 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
4521 "vqmovun", "s", int_arm_neon_vqmovnsu>;
4522 // VMOVL : Vector Lengthening Move
4523 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
4524 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
4526 // Vector Conversions.
4528 // VCVT : Vector Convert Between Floating-Point and Integers
4529 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4530 v2i32, v2f32, fp_to_sint>;
4531 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4532 v2i32, v2f32, fp_to_uint>;
4533 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4534 v2f32, v2i32, sint_to_fp>;
4535 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4536 v2f32, v2i32, uint_to_fp>;
4538 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4539 v4i32, v4f32, fp_to_sint>;
4540 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4541 v4i32, v4f32, fp_to_uint>;
4542 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4543 v4f32, v4i32, sint_to_fp>;
4544 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4545 v4f32, v4i32, uint_to_fp>;
4547 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
4548 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4549 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
4550 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4551 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
4552 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4553 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
4554 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4555 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
4557 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4558 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
4559 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4560 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
4561 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4562 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
4563 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4564 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
4566 // VCVT : Vector Convert Between Half-Precision and Single-Precision.
4567 def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
4568 IIC_VUNAQ, "vcvt", "f16.f32",
4569 v4i16, v4f32, int_arm_neon_vcvtfp2hf>,
4570 Requires<[HasNEON, HasFP16]>;
4571 def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
4572 IIC_VUNAQ, "vcvt", "f32.f16",
4573 v4f32, v4i16, int_arm_neon_vcvthf2fp>,
4574 Requires<[HasNEON, HasFP16]>;
4578 // VREV64 : Vector Reverse elements within 64-bit doublewords
4580 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4581 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
4582 (ins DPR:$Vm), IIC_VMOVD,
4583 OpcodeStr, Dt, "$Vd, $Vm", "",
4584 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
4585 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4586 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
4587 (ins QPR:$Vm), IIC_VMOVQ,
4588 OpcodeStr, Dt, "$Vd, $Vm", "",
4589 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
4591 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
4592 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
4593 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
4594 def VREV64df : VREV64D<0b10, "vrev64", "32", v2f32>;
4596 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
4597 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
4598 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
4599 def VREV64qf : VREV64Q<0b10, "vrev64", "32", v4f32>;
4601 // VREV32 : Vector Reverse elements within 32-bit words
4603 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4604 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
4605 (ins DPR:$Vm), IIC_VMOVD,
4606 OpcodeStr, Dt, "$Vd, $Vm", "",
4607 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
4608 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4609 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
4610 (ins QPR:$Vm), IIC_VMOVQ,
4611 OpcodeStr, Dt, "$Vd, $Vm", "",
4612 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
4614 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
4615 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
4617 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
4618 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
4620 // VREV16 : Vector Reverse elements within 16-bit halfwords
4622 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4623 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
4624 (ins DPR:$Vm), IIC_VMOVD,
4625 OpcodeStr, Dt, "$Vd, $Vm", "",
4626 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
4627 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4628 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
4629 (ins QPR:$Vm), IIC_VMOVQ,
4630 OpcodeStr, Dt, "$Vd, $Vm", "",
4631 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
4633 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
4634 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
4636 // Other Vector Shuffles.
4638 // Aligned extractions: really just dropping registers
4640 class AlignedVEXTq<ValueType DestTy, ValueType SrcTy, SDNodeXForm LaneCVT>
4641 : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))),
4642 (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>;
4644 def : AlignedVEXTq<v8i8, v16i8, DSubReg_i8_reg>;
4646 def : AlignedVEXTq<v4i16, v8i16, DSubReg_i16_reg>;
4648 def : AlignedVEXTq<v2i32, v4i32, DSubReg_i32_reg>;
4650 def : AlignedVEXTq<v1i64, v2i64, DSubReg_f64_reg>;
4652 def : AlignedVEXTq<v2f32, v4f32, DSubReg_i32_reg>;
4655 // VEXT : Vector Extract
4657 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
4658 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
4659 (ins DPR:$Vn, DPR:$Vm, i32imm:$index), NVExtFrm,
4660 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4661 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
4662 (Ty DPR:$Vm), imm:$index)))]> {
4664 let Inst{11-8} = index{3-0};
4667 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
4668 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
4669 (ins QPR:$Vn, QPR:$Vm, i32imm:$index), NVExtFrm,
4670 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4671 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
4672 (Ty QPR:$Vm), imm:$index)))]> {
4674 let Inst{11-8} = index{3-0};
4677 def VEXTd8 : VEXTd<"vext", "8", v8i8> {
4678 let Inst{11-8} = index{3-0};
4680 def VEXTd16 : VEXTd<"vext", "16", v4i16> {
4681 let Inst{11-9} = index{2-0};
4684 def VEXTd32 : VEXTd<"vext", "32", v2i32> {
4685 let Inst{11-10} = index{1-0};
4686 let Inst{9-8} = 0b00;
4688 def VEXTdf : VEXTd<"vext", "32", v2f32> {
4689 let Inst{11} = index{0};
4690 let Inst{10-8} = 0b000;
4693 def VEXTq8 : VEXTq<"vext", "8", v16i8> {
4694 let Inst{11-8} = index{3-0};
4696 def VEXTq16 : VEXTq<"vext", "16", v8i16> {
4697 let Inst{11-9} = index{2-0};
4700 def VEXTq32 : VEXTq<"vext", "32", v4i32> {
4701 let Inst{11-10} = index{1-0};
4702 let Inst{9-8} = 0b00;
4704 def VEXTqf : VEXTq<"vext", "32", v4f32> {
4705 let Inst{11} = index{0};
4706 let Inst{10-8} = 0b000;
4709 // VTRN : Vector Transpose
4711 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
4712 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
4713 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
4715 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
4716 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
4717 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
4719 // VUZP : Vector Unzip (Deinterleave)
4721 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
4722 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
4723 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
4725 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
4726 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
4727 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
4729 // VZIP : Vector Zip (Interleave)
4731 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
4732 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
4733 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
4735 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
4736 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
4737 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
4739 // Vector Table Lookup and Table Extension.
4741 // VTBL : Vector Table Lookup
4743 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
4744 (ins DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
4745 "vtbl", "8", "$Vd, \\{$Vn\\}, $Vm", "",
4746 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 DPR:$Vn, DPR:$Vm)))]>;
4747 let hasExtraSrcRegAllocReq = 1 in {
4749 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
4750 (ins DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTB2,
4751 "vtbl", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "", []>;
4753 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
4754 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm), NVTBLFrm, IIC_VTB3,
4755 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm", "", []>;
4757 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
4758 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm),
4760 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm", "", []>;
4761 } // hasExtraSrcRegAllocReq = 1
4764 : PseudoNeonI<(outs DPR:$dst), (ins QPR:$tbl, DPR:$src), IIC_VTB2, "", []>;
4766 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
4768 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
4770 // VTBX : Vector Table Extension
4772 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
4773 (ins DPR:$orig, DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
4774 "vtbx", "8", "$Vd, \\{$Vn\\}, $Vm", "$orig = $Vd",
4775 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
4776 DPR:$orig, DPR:$Vn, DPR:$Vm)))]>;
4777 let hasExtraSrcRegAllocReq = 1 in {
4779 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
4780 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
4781 "vtbx", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "$orig = $Vd", []>;
4783 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
4784 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm),
4785 NVTBLFrm, IIC_VTBX3,
4786 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm",
4789 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd), (ins DPR:$orig, DPR:$Vn,
4790 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
4791 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm",
4793 } // hasExtraSrcRegAllocReq = 1
4796 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QPR:$tbl, DPR:$src),
4797 IIC_VTBX2, "$orig = $dst", []>;
4799 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4800 IIC_VTBX3, "$orig = $dst", []>;
4802 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4803 IIC_VTBX4, "$orig = $dst", []>;
4805 //===----------------------------------------------------------------------===//
4806 // NEON instructions for single-precision FP math
4807 //===----------------------------------------------------------------------===//
4809 class N2VSPat<SDNode OpNode, NeonI Inst>
4810 : NEONFPPat<(f32 (OpNode SPR:$a)),
4812 (v2f32 (COPY_TO_REGCLASS (Inst
4814 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4815 SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>;
4817 class N3VSPat<SDNode OpNode, NeonI Inst>
4818 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
4820 (v2f32 (COPY_TO_REGCLASS (Inst
4822 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4825 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4826 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
4828 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
4829 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
4831 (v2f32 (COPY_TO_REGCLASS (Inst
4833 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4836 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4839 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4840 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
4842 def : N3VSPat<fadd, VADDfd>;
4843 def : N3VSPat<fsub, VSUBfd>;
4844 def : N3VSPat<fmul, VMULfd>;
4845 def : N3VSMulOpPat<fmul, fadd, VMLAfd>,
4846 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
4847 def : N3VSMulOpPat<fmul, fsub, VMLSfd>,
4848 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
4849 def : N2VSPat<fabs, VABSfd>;
4850 def : N2VSPat<fneg, VNEGfd>;
4851 def : N3VSPat<NEONfmax, VMAXfd>;
4852 def : N3VSPat<NEONfmin, VMINfd>;
4853 def : N2VSPat<arm_ftosi, VCVTf2sd>;
4854 def : N2VSPat<arm_ftoui, VCVTf2ud>;
4855 def : N2VSPat<arm_sitof, VCVTs2fd>;
4856 def : N2VSPat<arm_uitof, VCVTu2fd>;
4858 //===----------------------------------------------------------------------===//
4859 // Non-Instruction Patterns
4860 //===----------------------------------------------------------------------===//
4863 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
4864 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
4865 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
4866 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
4867 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
4868 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
4869 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
4870 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
4871 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
4872 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
4873 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
4874 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
4875 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
4876 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
4877 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
4878 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
4879 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
4880 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
4881 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
4882 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
4883 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
4884 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
4885 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
4886 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
4887 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
4888 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
4889 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
4890 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
4891 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
4892 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
4894 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
4895 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
4896 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
4897 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
4898 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
4899 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
4900 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
4901 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
4902 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
4903 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
4904 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
4905 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
4906 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
4907 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
4908 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
4909 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
4910 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
4911 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
4912 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
4913 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
4914 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
4915 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
4916 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
4917 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
4918 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
4919 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
4920 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
4921 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
4922 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
4923 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;