1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
69 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
70 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
72 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
74 // VDUPLANE can produce a quad-register result from a double-register source,
75 // so the result is not constrained to match the source.
76 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
77 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
80 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
81 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
82 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
84 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
85 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
86 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
87 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
89 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
92 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
93 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
94 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
96 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
98 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
99 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
101 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
102 SDTCisSameAs<0, 2>]>;
103 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
104 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
106 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
107 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
108 unsigned EltBits = 0;
109 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
110 return (EltBits == 32 && EltVal == 0);
113 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
114 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
115 unsigned EltBits = 0;
116 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
117 return (EltBits == 8 && EltVal == 0xff);
120 //===----------------------------------------------------------------------===//
121 // NEON operand definitions
122 //===----------------------------------------------------------------------===//
124 def nModImm : Operand<i32> {
125 let PrintMethod = "printNEONModImmOperand";
128 //===----------------------------------------------------------------------===//
129 // NEON load / store instructions
130 //===----------------------------------------------------------------------===//
132 // Use VLDM to load a Q register as a D register pair.
133 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
135 : PseudoVFPLdStM<(outs QPR:$dst), (ins addrmode4:$addr), IIC_fpLoadm, "",
136 [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]>;
138 // Use VSTM to store a Q register as a D register pair.
139 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
141 : PseudoVFPLdStM<(outs), (ins QPR:$src, addrmode4:$addr), IIC_fpStorem, "",
142 [(store (v2f64 QPR:$src), addrmode4:$addr)]>;
144 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
146 // Classes for VLD* pseudo-instructions with multi-register operands.
147 // These are expanded to real instructions after register allocation.
148 class VLDQPseudo<InstrItinClass itin>
149 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
150 class VLDQWBPseudo<InstrItinClass itin>
151 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
152 (ins addrmode6:$addr, am6offset:$offset), itin,
154 class VLDQQPseudo<InstrItinClass itin>
155 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
156 class VLDQQWBPseudo<InstrItinClass itin>
157 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
158 (ins addrmode6:$addr, am6offset:$offset), itin,
160 class VLDQQQQWBPseudo<InstrItinClass itin>
161 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
162 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
163 "$addr.addr = $wb, $src = $dst">;
165 // VLD1 : Vector Load (multiple single elements)
166 class VLD1D<bits<4> op7_4, string Dt>
167 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst),
168 (ins addrmode6:$addr), IIC_VLD1,
169 "vld1", Dt, "\\{$dst\\}, $addr", "", []>;
170 class VLD1Q<bits<4> op7_4, string Dt>
171 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$dst1, DPR:$dst2),
172 (ins addrmode6:$addr), IIC_VLD2,
173 "vld1", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>;
175 def VLD1d8 : VLD1D<0b0000, "8">;
176 def VLD1d16 : VLD1D<0b0100, "16">;
177 def VLD1d32 : VLD1D<0b1000, "32">;
178 def VLD1d64 : VLD1D<0b1100, "64">;
180 def VLD1q8 : VLD1Q<0b0000, "8">;
181 def VLD1q16 : VLD1Q<0b0100, "16">;
182 def VLD1q32 : VLD1Q<0b1000, "32">;
183 def VLD1q64 : VLD1Q<0b1100, "64">;
185 def VLD1q8Pseudo : VLDQPseudo<IIC_VLD2>;
186 def VLD1q16Pseudo : VLDQPseudo<IIC_VLD2>;
187 def VLD1q32Pseudo : VLDQPseudo<IIC_VLD2>;
188 def VLD1q64Pseudo : VLDQPseudo<IIC_VLD2>;
190 // ...with address register writeback:
191 class VLD1DWB<bits<4> op7_4, string Dt>
192 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst, GPR:$wb),
193 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1,
194 "vld1", Dt, "\\{$dst\\}, $addr$offset",
195 "$addr.addr = $wb", []>;
196 class VLD1QWB<bits<4> op7_4, string Dt>
197 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
198 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2,
199 "vld1", Dt, "\\{$dst1, $dst2\\}, $addr$offset",
200 "$addr.addr = $wb", []>;
202 def VLD1d8_UPD : VLD1DWB<0b0000, "8">;
203 def VLD1d16_UPD : VLD1DWB<0b0100, "16">;
204 def VLD1d32_UPD : VLD1DWB<0b1000, "32">;
205 def VLD1d64_UPD : VLD1DWB<0b1100, "64">;
207 def VLD1q8_UPD : VLD1QWB<0b0000, "8">;
208 def VLD1q16_UPD : VLD1QWB<0b0100, "16">;
209 def VLD1q32_UPD : VLD1QWB<0b1000, "32">;
210 def VLD1q64_UPD : VLD1QWB<0b1100, "64">;
212 def VLD1q8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2>;
213 def VLD1q16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2>;
214 def VLD1q32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2>;
215 def VLD1q64Pseudo_UPD : VLDQWBPseudo<IIC_VLD2>;
217 // ...with 3 registers (some of these are only for the disassembler):
218 class VLD1D3<bits<4> op7_4, string Dt>
219 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
220 (ins addrmode6:$addr), IIC_VLD3, "vld1", Dt,
221 "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
222 class VLD1D3WB<bits<4> op7_4, string Dt>
223 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
224 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD3, "vld1", Dt,
225 "\\{$dst1, $dst2, $dst3\\}, $addr$offset", "$addr.addr = $wb", []>;
227 def VLD1d8T : VLD1D3<0b0000, "8">;
228 def VLD1d16T : VLD1D3<0b0100, "16">;
229 def VLD1d32T : VLD1D3<0b1000, "32">;
230 def VLD1d64T : VLD1D3<0b1100, "64">;
232 def VLD1d8T_UPD : VLD1D3WB<0b0000, "8">;
233 def VLD1d16T_UPD : VLD1D3WB<0b0100, "16">;
234 def VLD1d32T_UPD : VLD1D3WB<0b1000, "32">;
235 def VLD1d64T_UPD : VLD1D3WB<0b1100, "64">;
237 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD3>;
238 def VLD1d64TPseudo_UPD : VLDQQWBPseudo<IIC_VLD3>;
240 // ...with 4 registers (some of these are only for the disassembler):
241 class VLD1D4<bits<4> op7_4, string Dt>
242 : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
243 (ins addrmode6:$addr), IIC_VLD4, "vld1", Dt,
244 "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
245 class VLD1D4WB<bits<4> op7_4, string Dt>
246 : NLdSt<0,0b10,0b0010,op7_4,
247 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
248 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD4, "vld1", Dt,
249 "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset", "$addr.addr = $wb",
252 def VLD1d8Q : VLD1D4<0b0000, "8">;
253 def VLD1d16Q : VLD1D4<0b0100, "16">;
254 def VLD1d32Q : VLD1D4<0b1000, "32">;
255 def VLD1d64Q : VLD1D4<0b1100, "64">;
257 def VLD1d8Q_UPD : VLD1D4WB<0b0000, "8">;
258 def VLD1d16Q_UPD : VLD1D4WB<0b0100, "16">;
259 def VLD1d32Q_UPD : VLD1D4WB<0b1000, "32">;
260 def VLD1d64Q_UPD : VLD1D4WB<0b1100, "64">;
262 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD4>;
263 def VLD1d64QPseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
265 // VLD2 : Vector Load (multiple 2-element structures)
266 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
267 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2),
268 (ins addrmode6:$addr), IIC_VLD2,
269 "vld2", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>;
270 class VLD2Q<bits<4> op7_4, string Dt>
271 : NLdSt<0, 0b10, 0b0011, op7_4,
272 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
273 (ins addrmode6:$addr), IIC_VLD4,
274 "vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
276 def VLD2d8 : VLD2D<0b1000, 0b0000, "8">;
277 def VLD2d16 : VLD2D<0b1000, 0b0100, "16">;
278 def VLD2d32 : VLD2D<0b1000, 0b1000, "32">;
280 def VLD2q8 : VLD2Q<0b0000, "8">;
281 def VLD2q16 : VLD2Q<0b0100, "16">;
282 def VLD2q32 : VLD2Q<0b1000, "32">;
284 def VLD2d8Pseudo : VLDQPseudo<IIC_VLD2>;
285 def VLD2d16Pseudo : VLDQPseudo<IIC_VLD2>;
286 def VLD2d32Pseudo : VLDQPseudo<IIC_VLD2>;
288 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD4>;
289 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD4>;
290 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD4>;
292 // ...with address register writeback:
293 class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
294 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
295 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2,
296 "vld2", Dt, "\\{$dst1, $dst2\\}, $addr$offset",
297 "$addr.addr = $wb", []>;
298 class VLD2QWB<bits<4> op7_4, string Dt>
299 : NLdSt<0, 0b10, 0b0011, op7_4,
300 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
301 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD4,
302 "vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset",
303 "$addr.addr = $wb", []>;
305 def VLD2d8_UPD : VLD2DWB<0b1000, 0b0000, "8">;
306 def VLD2d16_UPD : VLD2DWB<0b1000, 0b0100, "16">;
307 def VLD2d32_UPD : VLD2DWB<0b1000, 0b1000, "32">;
309 def VLD2q8_UPD : VLD2QWB<0b0000, "8">;
310 def VLD2q16_UPD : VLD2QWB<0b0100, "16">;
311 def VLD2q32_UPD : VLD2QWB<0b1000, "32">;
313 def VLD2d8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2>;
314 def VLD2d16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2>;
315 def VLD2d32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2>;
317 def VLD2q8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
318 def VLD2q16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
319 def VLD2q32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
321 // ...with double-spaced registers (for disassembly only):
322 def VLD2b8 : VLD2D<0b1001, 0b0000, "8">;
323 def VLD2b16 : VLD2D<0b1001, 0b0100, "16">;
324 def VLD2b32 : VLD2D<0b1001, 0b1000, "32">;
325 def VLD2b8_UPD : VLD2DWB<0b1001, 0b0000, "8">;
326 def VLD2b16_UPD : VLD2DWB<0b1001, 0b0100, "16">;
327 def VLD2b32_UPD : VLD2DWB<0b1001, 0b1000, "32">;
329 // VLD3 : Vector Load (multiple 3-element structures)
330 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
331 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
332 (ins addrmode6:$addr), IIC_VLD3,
333 "vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
335 def VLD3d8 : VLD3D<0b0100, 0b0000, "8">;
336 def VLD3d16 : VLD3D<0b0100, 0b0100, "16">;
337 def VLD3d32 : VLD3D<0b0100, 0b1000, "32">;
339 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
340 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
341 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
343 // ...with address register writeback:
344 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
345 : NLdSt<0, 0b10, op11_8, op7_4,
346 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
347 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD3,
348 "vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr$offset",
349 "$addr.addr = $wb", []>;
351 def VLD3d8_UPD : VLD3DWB<0b0100, 0b0000, "8">;
352 def VLD3d16_UPD : VLD3DWB<0b0100, 0b0100, "16">;
353 def VLD3d32_UPD : VLD3DWB<0b0100, 0b1000, "32">;
355 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3>;
356 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3>;
357 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3>;
359 // ...with double-spaced registers (non-updating versions for disassembly only):
360 def VLD3q8 : VLD3D<0b0101, 0b0000, "8">;
361 def VLD3q16 : VLD3D<0b0101, 0b0100, "16">;
362 def VLD3q32 : VLD3D<0b0101, 0b1000, "32">;
363 def VLD3q8_UPD : VLD3DWB<0b0101, 0b0000, "8">;
364 def VLD3q16_UPD : VLD3DWB<0b0101, 0b0100, "16">;
365 def VLD3q32_UPD : VLD3DWB<0b0101, 0b1000, "32">;
367 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3>;
368 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3>;
369 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3>;
371 // ...alternate versions to be allocated odd register numbers:
372 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3>;
373 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3>;
374 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3>;
376 // VLD4 : Vector Load (multiple 4-element structures)
377 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
378 : NLdSt<0, 0b10, op11_8, op7_4,
379 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
380 (ins addrmode6:$addr), IIC_VLD4,
381 "vld4", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
383 def VLD4d8 : VLD4D<0b0000, 0b0000, "8">;
384 def VLD4d16 : VLD4D<0b0000, 0b0100, "16">;
385 def VLD4d32 : VLD4D<0b0000, 0b1000, "32">;
387 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
388 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
389 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
391 // ...with address register writeback:
392 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
393 : NLdSt<0, 0b10, op11_8, op7_4,
394 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
395 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD4,
396 "vld4", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset",
397 "$addr.addr = $wb", []>;
399 def VLD4d8_UPD : VLD4DWB<0b0000, 0b0000, "8">;
400 def VLD4d16_UPD : VLD4DWB<0b0000, 0b0100, "16">;
401 def VLD4d32_UPD : VLD4DWB<0b0000, 0b1000, "32">;
403 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
404 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
405 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
407 // ...with double-spaced registers (non-updating versions for disassembly only):
408 def VLD4q8 : VLD4D<0b0001, 0b0000, "8">;
409 def VLD4q16 : VLD4D<0b0001, 0b0100, "16">;
410 def VLD4q32 : VLD4D<0b0001, 0b1000, "32">;
411 def VLD4q8_UPD : VLD4DWB<0b0001, 0b0000, "8">;
412 def VLD4q16_UPD : VLD4DWB<0b0001, 0b0100, "16">;
413 def VLD4q32_UPD : VLD4DWB<0b0001, 0b1000, "32">;
415 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
416 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
417 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
419 // ...alternate versions to be allocated odd register numbers:
420 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
421 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
422 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
424 // Classes for VLD*LN pseudo-instructions with multi-register operands.
425 // These are expanded to real instructions after register allocation.
426 class VLDQLNPseudo<InstrItinClass itin>
427 : PseudoNLdSt<(outs QPR:$dst),
428 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
429 itin, "$src = $dst">;
430 class VLDQLNWBPseudo<InstrItinClass itin>
431 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
432 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
433 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
434 class VLDQQLNPseudo<InstrItinClass itin>
435 : PseudoNLdSt<(outs QQPR:$dst),
436 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
437 itin, "$src = $dst">;
438 class VLDQQLNWBPseudo<InstrItinClass itin>
439 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
440 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
441 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
442 class VLDQQQQLNPseudo<InstrItinClass itin>
443 : PseudoNLdSt<(outs QQQQPR:$dst),
444 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
445 itin, "$src = $dst">;
446 class VLDQQQQLNWBPseudo<InstrItinClass itin>
447 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
448 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
449 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
451 // VLD1LN : Vector Load (single element to one lane)
452 // FIXME: Not yet implemented.
454 // VLD2LN : Vector Load (single 2-element structure to one lane)
455 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
456 : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2),
457 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
458 IIC_VLD2, "vld2", Dt, "\\{$dst1[$lane], $dst2[$lane]\\}, $addr",
459 "$src1 = $dst1, $src2 = $dst2", []>;
461 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8">;
462 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16">;
463 def VLD2LNd32 : VLD2LN<0b1001, {?,0,?,?}, "32">;
465 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2>;
466 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2>;
467 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2>;
469 // ...with double-spaced registers:
470 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16">;
471 def VLD2LNq32 : VLD2LN<0b1001, {?,1,?,?}, "32">;
473 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2>;
474 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2>;
476 // ...with address register writeback:
477 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
478 : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
479 (ins addrmode6:$addr, am6offset:$offset,
480 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2, "vld2", Dt,
481 "\\{$dst1[$lane], $dst2[$lane]\\}, $addr$offset",
482 "$src1 = $dst1, $src2 = $dst2, $addr.addr = $wb", []>;
484 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8">;
485 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16">;
486 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,?,?}, "32">;
488 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2>;
489 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2>;
490 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2>;
492 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16">;
493 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,?,?}, "32">;
495 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2>;
496 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2>;
498 // VLD3LN : Vector Load (single 3-element structure to one lane)
499 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
500 : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
501 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
502 nohash_imm:$lane), IIC_VLD3, "vld3", Dt,
503 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr",
504 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
506 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8">;
507 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16">;
508 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32">;
510 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3>;
511 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3>;
512 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3>;
514 // ...with double-spaced registers:
515 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16">;
516 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32">;
518 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3>;
519 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3>;
521 // ...with address register writeback:
522 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
523 : NLdSt<1, 0b10, op11_8, op7_4,
524 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
525 (ins addrmode6:$addr, am6offset:$offset,
526 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
527 IIC_VLD3, "vld3", Dt,
528 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr$offset",
529 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $addr.addr = $wb",
532 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8">;
533 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16">;
534 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32">;
536 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3>;
537 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3>;
538 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3>;
540 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16">;
541 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32">;
543 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3>;
544 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3>;
546 // VLD4LN : Vector Load (single 4-element structure to one lane)
547 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
548 : NLdSt<1, 0b10, op11_8, op7_4,
549 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
550 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
551 nohash_imm:$lane), IIC_VLD4, "vld4", Dt,
552 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr",
553 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
555 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8">;
556 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16">;
557 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32">;
559 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4>;
560 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4>;
561 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4>;
563 // ...with double-spaced registers:
564 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16">;
565 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32">;
567 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4>;
568 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4>;
570 // ...with address register writeback:
571 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
572 : NLdSt<1, 0b10, op11_8, op7_4,
573 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
574 (ins addrmode6:$addr, am6offset:$offset,
575 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
576 IIC_VLD4, "vld4", Dt,
577 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr$offset",
578 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $addr.addr = $wb",
581 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8">;
582 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16">;
583 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32">;
585 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4>;
586 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4>;
587 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4>;
589 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16">;
590 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32">;
592 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4>;
593 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4>;
595 // VLD1DUP : Vector Load (single element to all lanes)
596 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
597 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
598 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
599 // FIXME: Not yet implemented.
600 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
602 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
604 // Classes for VST* pseudo-instructions with multi-register operands.
605 // These are expanded to real instructions after register allocation.
606 class VSTQPseudo<InstrItinClass itin>
607 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
608 class VSTQWBPseudo<InstrItinClass itin>
609 : PseudoNLdSt<(outs GPR:$wb),
610 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
612 class VSTQQPseudo<InstrItinClass itin>
613 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
614 class VSTQQWBPseudo<InstrItinClass itin>
615 : PseudoNLdSt<(outs GPR:$wb),
616 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
618 class VSTQQQQWBPseudo<InstrItinClass itin>
619 : PseudoNLdSt<(outs GPR:$wb),
620 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), IIC_VST,
623 // VST1 : Vector Store (multiple single elements)
624 class VST1D<bits<4> op7_4, string Dt>
625 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src), IIC_VST,
626 "vst1", Dt, "\\{$src\\}, $addr", "", []>;
627 class VST1Q<bits<4> op7_4, string Dt>
628 : NLdSt<0,0b00,0b1010,op7_4, (outs),
629 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
630 "vst1", Dt, "\\{$src1, $src2\\}, $addr", "", []>;
632 def VST1d8 : VST1D<0b0000, "8">;
633 def VST1d16 : VST1D<0b0100, "16">;
634 def VST1d32 : VST1D<0b1000, "32">;
635 def VST1d64 : VST1D<0b1100, "64">;
637 def VST1q8 : VST1Q<0b0000, "8">;
638 def VST1q16 : VST1Q<0b0100, "16">;
639 def VST1q32 : VST1Q<0b1000, "32">;
640 def VST1q64 : VST1Q<0b1100, "64">;
642 def VST1q8Pseudo : VSTQPseudo<IIC_VST>;
643 def VST1q16Pseudo : VSTQPseudo<IIC_VST>;
644 def VST1q32Pseudo : VSTQPseudo<IIC_VST>;
645 def VST1q64Pseudo : VSTQPseudo<IIC_VST>;
647 // ...with address register writeback:
648 class VST1DWB<bits<4> op7_4, string Dt>
649 : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
650 (ins addrmode6:$addr, am6offset:$offset, DPR:$src), IIC_VST,
651 "vst1", Dt, "\\{$src\\}, $addr$offset", "$addr.addr = $wb", []>;
652 class VST1QWB<bits<4> op7_4, string Dt>
653 : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),
654 (ins addrmode6:$addr, am6offset:$offset, DPR:$src1, DPR:$src2),
655 IIC_VST, "vst1", Dt, "\\{$src1, $src2\\}, $addr$offset",
656 "$addr.addr = $wb", []>;
658 def VST1d8_UPD : VST1DWB<0b0000, "8">;
659 def VST1d16_UPD : VST1DWB<0b0100, "16">;
660 def VST1d32_UPD : VST1DWB<0b1000, "32">;
661 def VST1d64_UPD : VST1DWB<0b1100, "64">;
663 def VST1q8_UPD : VST1QWB<0b0000, "8">;
664 def VST1q16_UPD : VST1QWB<0b0100, "16">;
665 def VST1q32_UPD : VST1QWB<0b1000, "32">;
666 def VST1q64_UPD : VST1QWB<0b1100, "64">;
668 def VST1q8Pseudo_UPD : VSTQWBPseudo<IIC_VST>;
669 def VST1q16Pseudo_UPD : VSTQWBPseudo<IIC_VST>;
670 def VST1q32Pseudo_UPD : VSTQWBPseudo<IIC_VST>;
671 def VST1q64Pseudo_UPD : VSTQWBPseudo<IIC_VST>;
673 // ...with 3 registers (some of these are only for the disassembler):
674 class VST1D3<bits<4> op7_4, string Dt>
675 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
676 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
677 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>;
678 class VST1D3WB<bits<4> op7_4, string Dt>
679 : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
680 (ins addrmode6:$addr, am6offset:$offset,
681 DPR:$src1, DPR:$src2, DPR:$src3),
682 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr$offset",
683 "$addr.addr = $wb", []>;
685 def VST1d8T : VST1D3<0b0000, "8">;
686 def VST1d16T : VST1D3<0b0100, "16">;
687 def VST1d32T : VST1D3<0b1000, "32">;
688 def VST1d64T : VST1D3<0b1100, "64">;
690 def VST1d8T_UPD : VST1D3WB<0b0000, "8">;
691 def VST1d16T_UPD : VST1D3WB<0b0100, "16">;
692 def VST1d32T_UPD : VST1D3WB<0b1000, "32">;
693 def VST1d64T_UPD : VST1D3WB<0b1100, "64">;
695 def VST1d64TPseudo : VSTQQPseudo<IIC_VST>;
696 def VST1d64TPseudo_UPD : VSTQQWBPseudo<IIC_VST>;
698 // ...with 4 registers (some of these are only for the disassembler):
699 class VST1D4<bits<4> op7_4, string Dt>
700 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
701 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
702 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr", "",
704 class VST1D4WB<bits<4> op7_4, string Dt>
705 : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
706 (ins addrmode6:$addr, am6offset:$offset,
707 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
708 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
709 "$addr.addr = $wb", []>;
711 def VST1d8Q : VST1D4<0b0000, "8">;
712 def VST1d16Q : VST1D4<0b0100, "16">;
713 def VST1d32Q : VST1D4<0b1000, "32">;
714 def VST1d64Q : VST1D4<0b1100, "64">;
716 def VST1d8Q_UPD : VST1D4WB<0b0000, "8">;
717 def VST1d16Q_UPD : VST1D4WB<0b0100, "16">;
718 def VST1d32Q_UPD : VST1D4WB<0b1000, "32">;
719 def VST1d64Q_UPD : VST1D4WB<0b1100, "64">;
721 def VST1d64QPseudo : VSTQQPseudo<IIC_VST>;
722 def VST1d64QPseudo_UPD : VSTQQWBPseudo<IIC_VST>;
724 // VST2 : Vector Store (multiple 2-element structures)
725 class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
726 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
727 (ins addrmode6:$addr, DPR:$src1, DPR:$src2),
728 IIC_VST, "vst2", Dt, "\\{$src1, $src2\\}, $addr", "", []>;
729 class VST2Q<bits<4> op7_4, string Dt>
730 : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
731 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
732 IIC_VST, "vst2", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
735 def VST2d8 : VST2D<0b1000, 0b0000, "8">;
736 def VST2d16 : VST2D<0b1000, 0b0100, "16">;
737 def VST2d32 : VST2D<0b1000, 0b1000, "32">;
739 def VST2q8 : VST2Q<0b0000, "8">;
740 def VST2q16 : VST2Q<0b0100, "16">;
741 def VST2q32 : VST2Q<0b1000, "32">;
743 def VST2d8Pseudo : VSTQPseudo<IIC_VST>;
744 def VST2d16Pseudo : VSTQPseudo<IIC_VST>;
745 def VST2d32Pseudo : VSTQPseudo<IIC_VST>;
747 def VST2q8Pseudo : VSTQQPseudo<IIC_VST>;
748 def VST2q16Pseudo : VSTQQPseudo<IIC_VST>;
749 def VST2q32Pseudo : VSTQQPseudo<IIC_VST>;
751 // ...with address register writeback:
752 class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
753 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
754 (ins addrmode6:$addr, am6offset:$offset, DPR:$src1, DPR:$src2),
755 IIC_VST, "vst2", Dt, "\\{$src1, $src2\\}, $addr$offset",
756 "$addr.addr = $wb", []>;
757 class VST2QWB<bits<4> op7_4, string Dt>
758 : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
759 (ins addrmode6:$addr, am6offset:$offset,
760 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
761 IIC_VST, "vst2", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
762 "$addr.addr = $wb", []>;
764 def VST2d8_UPD : VST2DWB<0b1000, 0b0000, "8">;
765 def VST2d16_UPD : VST2DWB<0b1000, 0b0100, "16">;
766 def VST2d32_UPD : VST2DWB<0b1000, 0b1000, "32">;
768 def VST2q8_UPD : VST2QWB<0b0000, "8">;
769 def VST2q16_UPD : VST2QWB<0b0100, "16">;
770 def VST2q32_UPD : VST2QWB<0b1000, "32">;
772 def VST2d8Pseudo_UPD : VSTQWBPseudo<IIC_VST>;
773 def VST2d16Pseudo_UPD : VSTQWBPseudo<IIC_VST>;
774 def VST2d32Pseudo_UPD : VSTQWBPseudo<IIC_VST>;
776 def VST2q8Pseudo_UPD : VSTQQWBPseudo<IIC_VST>;
777 def VST2q16Pseudo_UPD : VSTQQWBPseudo<IIC_VST>;
778 def VST2q32Pseudo_UPD : VSTQQWBPseudo<IIC_VST>;
780 // ...with double-spaced registers (for disassembly only):
781 def VST2b8 : VST2D<0b1001, 0b0000, "8">;
782 def VST2b16 : VST2D<0b1001, 0b0100, "16">;
783 def VST2b32 : VST2D<0b1001, 0b1000, "32">;
784 def VST2b8_UPD : VST2DWB<0b1001, 0b0000, "8">;
785 def VST2b16_UPD : VST2DWB<0b1001, 0b0100, "16">;
786 def VST2b32_UPD : VST2DWB<0b1001, 0b1000, "32">;
788 // VST3 : Vector Store (multiple 3-element structures)
789 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
790 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
791 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
792 "vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>;
794 def VST3d8 : VST3D<0b0100, 0b0000, "8">;
795 def VST3d16 : VST3D<0b0100, 0b0100, "16">;
796 def VST3d32 : VST3D<0b0100, 0b1000, "32">;
798 def VST3d8Pseudo : VSTQQPseudo<IIC_VST>;
799 def VST3d16Pseudo : VSTQQPseudo<IIC_VST>;
800 def VST3d32Pseudo : VSTQQPseudo<IIC_VST>;
802 // ...with address register writeback:
803 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
804 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
805 (ins addrmode6:$addr, am6offset:$offset,
806 DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
807 "vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr$offset",
808 "$addr.addr = $wb", []>;
810 def VST3d8_UPD : VST3DWB<0b0100, 0b0000, "8">;
811 def VST3d16_UPD : VST3DWB<0b0100, 0b0100, "16">;
812 def VST3d32_UPD : VST3DWB<0b0100, 0b1000, "32">;
814 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST>;
815 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST>;
816 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST>;
818 // ...with double-spaced registers (non-updating versions for disassembly only):
819 def VST3q8 : VST3D<0b0101, 0b0000, "8">;
820 def VST3q16 : VST3D<0b0101, 0b0100, "16">;
821 def VST3q32 : VST3D<0b0101, 0b1000, "32">;
822 def VST3q8_UPD : VST3DWB<0b0101, 0b0000, "8">;
823 def VST3q16_UPD : VST3DWB<0b0101, 0b0100, "16">;
824 def VST3q32_UPD : VST3DWB<0b0101, 0b1000, "32">;
826 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST>;
827 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST>;
828 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST>;
830 // ...alternate versions to be allocated odd register numbers:
831 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST>;
832 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST>;
833 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST>;
835 // VST4 : Vector Store (multiple 4-element structures)
836 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
837 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
838 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
839 IIC_VST, "vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
842 def VST4d8 : VST4D<0b0000, 0b0000, "8">;
843 def VST4d16 : VST4D<0b0000, 0b0100, "16">;
844 def VST4d32 : VST4D<0b0000, 0b1000, "32">;
846 def VST4d8Pseudo : VSTQQPseudo<IIC_VST>;
847 def VST4d16Pseudo : VSTQQPseudo<IIC_VST>;
848 def VST4d32Pseudo : VSTQQPseudo<IIC_VST>;
850 // ...with address register writeback:
851 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
852 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
853 (ins addrmode6:$addr, am6offset:$offset,
854 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST,
855 "vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
856 "$addr.addr = $wb", []>;
858 def VST4d8_UPD : VST4DWB<0b0000, 0b0000, "8">;
859 def VST4d16_UPD : VST4DWB<0b0000, 0b0100, "16">;
860 def VST4d32_UPD : VST4DWB<0b0000, 0b1000, "32">;
862 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST>;
863 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST>;
864 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST>;
866 // ...with double-spaced registers (non-updating versions for disassembly only):
867 def VST4q8 : VST4D<0b0001, 0b0000, "8">;
868 def VST4q16 : VST4D<0b0001, 0b0100, "16">;
869 def VST4q32 : VST4D<0b0001, 0b1000, "32">;
870 def VST4q8_UPD : VST4DWB<0b0001, 0b0000, "8">;
871 def VST4q16_UPD : VST4DWB<0b0001, 0b0100, "16">;
872 def VST4q32_UPD : VST4DWB<0b0001, 0b1000, "32">;
874 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST>;
875 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST>;
876 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST>;
878 // ...alternate versions to be allocated odd register numbers:
879 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST>;
880 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST>;
881 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST>;
883 // Classes for VST*LN pseudo-instructions with multi-register operands.
884 // These are expanded to real instructions after register allocation.
885 class VSTQLNPseudo<InstrItinClass itin>
886 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
888 class VSTQLNWBPseudo<InstrItinClass itin>
889 : PseudoNLdSt<(outs GPR:$wb),
890 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
891 nohash_imm:$lane), itin, "$addr.addr = $wb">;
892 class VSTQQLNPseudo<InstrItinClass itin>
893 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
895 class VSTQQLNWBPseudo<InstrItinClass itin>
896 : PseudoNLdSt<(outs GPR:$wb),
897 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
898 nohash_imm:$lane), itin, "$addr.addr = $wb">;
899 class VSTQQQQLNPseudo<InstrItinClass itin>
900 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
902 class VSTQQQQLNWBPseudo<InstrItinClass itin>
903 : PseudoNLdSt<(outs GPR:$wb),
904 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
905 nohash_imm:$lane), itin, "$addr.addr = $wb">;
907 // VST1LN : Vector Store (single element from one lane)
908 // FIXME: Not yet implemented.
910 // VST2LN : Vector Store (single 2-element structure from one lane)
911 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
912 : NLdSt<1, 0b00, op11_8, op7_4, (outs),
913 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
914 IIC_VST, "vst2", Dt, "\\{$src1[$lane], $src2[$lane]\\}, $addr",
917 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8">;
918 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16">;
919 def VST2LNd32 : VST2LN<0b1001, {?,0,?,?}, "32">;
921 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST>;
922 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST>;
923 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST>;
925 // ...with double-spaced registers:
926 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16">;
927 def VST2LNq32 : VST2LN<0b1001, {?,1,?,?}, "32">;
929 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST>;
930 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST>;
932 // ...with address register writeback:
933 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
934 : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
935 (ins addrmode6:$addr, am6offset:$offset,
936 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST, "vst2", Dt,
937 "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset",
938 "$addr.addr = $wb", []>;
940 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8">;
941 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16">;
942 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,?,?}, "32">;
944 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST>;
945 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST>;
946 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST>;
948 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16">;
949 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,?,?}, "32">;
951 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST>;
952 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST>;
954 // VST3LN : Vector Store (single 3-element structure from one lane)
955 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
956 : NLdSt<1, 0b00, op11_8, op7_4, (outs),
957 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
958 nohash_imm:$lane), IIC_VST, "vst3", Dt,
959 "\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr", "", []>;
961 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8">;
962 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16">;
963 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32">;
965 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST>;
966 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST>;
967 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST>;
969 // ...with double-spaced registers:
970 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16">;
971 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32">;
973 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST>;
974 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST>;
976 // ...with address register writeback:
977 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
978 : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
979 (ins addrmode6:$addr, am6offset:$offset,
980 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
982 "\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr$offset",
983 "$addr.addr = $wb", []>;
985 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8">;
986 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16">;
987 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32">;
989 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST>;
990 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST>;
991 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST>;
993 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16">;
994 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32">;
996 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST>;
997 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST>;
999 // VST4LN : Vector Store (single 4-element structure from one lane)
1000 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1001 : NLdSt<1, 0b00, op11_8, op7_4, (outs),
1002 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
1003 nohash_imm:$lane), IIC_VST, "vst4", Dt,
1004 "\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr",
1007 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8">;
1008 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16">;
1009 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32">;
1011 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST>;
1012 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST>;
1013 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST>;
1015 // ...with double-spaced registers:
1016 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16">;
1017 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32">;
1019 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST>;
1020 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST>;
1022 // ...with address register writeback:
1023 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1024 : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1025 (ins addrmode6:$addr, am6offset:$offset,
1026 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1027 IIC_VST, "vst4", Dt,
1028 "\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr$offset",
1029 "$addr.addr = $wb", []>;
1031 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8">;
1032 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16">;
1033 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32">;
1035 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST>;
1036 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST>;
1037 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST>;
1039 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16">;
1040 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32">;
1042 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST>;
1043 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST>;
1045 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1048 //===----------------------------------------------------------------------===//
1049 // NEON pattern fragments
1050 //===----------------------------------------------------------------------===//
1052 // Extract D sub-registers of Q registers.
1053 def DSubReg_i8_reg : SDNodeXForm<imm, [{
1054 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1055 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
1057 def DSubReg_i16_reg : SDNodeXForm<imm, [{
1058 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1059 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
1061 def DSubReg_i32_reg : SDNodeXForm<imm, [{
1062 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1063 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
1065 def DSubReg_f64_reg : SDNodeXForm<imm, [{
1066 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1067 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
1070 // Extract S sub-registers of Q/D registers.
1071 def SSubReg_f32_reg : SDNodeXForm<imm, [{
1072 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
1073 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
1076 // Translate lane numbers from Q registers to D subregs.
1077 def SubReg_i8_lane : SDNodeXForm<imm, [{
1078 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
1080 def SubReg_i16_lane : SDNodeXForm<imm, [{
1081 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
1083 def SubReg_i32_lane : SDNodeXForm<imm, [{
1084 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
1087 //===----------------------------------------------------------------------===//
1088 // Instruction Classes
1089 //===----------------------------------------------------------------------===//
1091 // Basic 2-register operations: single-, double- and quad-register.
1092 class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1093 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1094 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1095 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
1096 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
1097 IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
1098 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1099 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1100 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1101 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1102 (ins DPR:$src), IIC_VUNAD, OpcodeStr, Dt,"$dst, $src", "",
1103 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
1104 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1105 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1106 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1107 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1108 (ins QPR:$src), IIC_VUNAQ, OpcodeStr, Dt,"$dst, $src", "",
1109 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
1111 // Basic 2-register intrinsics, both double- and quad-register.
1112 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1113 bits<2> op17_16, bits<5> op11_7, bit op4,
1114 InstrItinClass itin, string OpcodeStr, string Dt,
1115 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1116 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1117 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1118 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
1119 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1120 bits<2> op17_16, bits<5> op11_7, bit op4,
1121 InstrItinClass itin, string OpcodeStr, string Dt,
1122 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1123 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1124 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1125 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
1127 // Narrow 2-register operations.
1128 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1129 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1130 InstrItinClass itin, string OpcodeStr, string Dt,
1131 ValueType TyD, ValueType TyQ, SDNode OpNode>
1132 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
1133 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1134 [(set DPR:$dst, (TyD (OpNode (TyQ QPR:$src))))]>;
1136 // Narrow 2-register intrinsics.
1137 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1138 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1139 InstrItinClass itin, string OpcodeStr, string Dt,
1140 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
1141 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
1142 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1143 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
1145 // Long 2-register operations (currently only used for VMOVL).
1146 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1147 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1148 InstrItinClass itin, string OpcodeStr, string Dt,
1149 ValueType TyQ, ValueType TyD, SDNode OpNode>
1150 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$dst),
1151 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1152 [(set QPR:$dst, (TyQ (OpNode (TyD DPR:$src))))]>;
1154 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
1155 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
1156 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
1157 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
1158 OpcodeStr, Dt, "$dst1, $dst2",
1159 "$src1 = $dst1, $src2 = $dst2", []>;
1160 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
1161 InstrItinClass itin, string OpcodeStr, string Dt>
1162 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
1163 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$dst1, $dst2",
1164 "$src1 = $dst1, $src2 = $dst2", []>;
1166 // Basic 3-register operations: single-, double- and quad-register.
1167 class N3VS<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1168 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1169 SDNode OpNode, bit Commutable>
1170 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1171 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm,
1172 IIC_VBIND, OpcodeStr, Dt, "$dst, $src1, $src2", "", []> {
1173 let isCommutable = Commutable;
1176 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1177 InstrItinClass itin, string OpcodeStr, string Dt,
1178 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1179 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1180 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1181 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1182 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
1183 let isCommutable = Commutable;
1185 // Same as N3VD but no data type.
1186 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1187 InstrItinClass itin, string OpcodeStr,
1188 ValueType ResTy, ValueType OpTy,
1189 SDNode OpNode, bit Commutable>
1190 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
1191 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1192 OpcodeStr, "$dst, $src1, $src2", "",
1193 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]>{
1194 let isCommutable = Commutable;
1197 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
1198 InstrItinClass itin, string OpcodeStr, string Dt,
1199 ValueType Ty, SDNode ShOp>
1200 : N3V<0, 1, op21_20, op11_8, 1, 0,
1201 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1202 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1203 [(set (Ty DPR:$dst),
1204 (Ty (ShOp (Ty DPR:$src1),
1205 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),imm:$lane)))))]> {
1206 let isCommutable = 0;
1208 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
1209 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1210 : N3V<0, 1, op21_20, op11_8, 1, 0,
1211 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1212 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$dst, $src1, $src2[$lane]","",
1213 [(set (Ty DPR:$dst),
1214 (Ty (ShOp (Ty DPR:$src1),
1215 (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
1216 let isCommutable = 0;
1219 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1220 InstrItinClass itin, string OpcodeStr, string Dt,
1221 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1222 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1223 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, itin,
1224 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1225 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
1226 let isCommutable = Commutable;
1228 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1229 InstrItinClass itin, string OpcodeStr,
1230 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1231 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
1232 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, itin,
1233 OpcodeStr, "$dst, $src1, $src2", "",
1234 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]>{
1235 let isCommutable = Commutable;
1237 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
1238 InstrItinClass itin, string OpcodeStr, string Dt,
1239 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1240 : N3V<1, 1, op21_20, op11_8, 1, 0,
1241 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1242 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1243 [(set (ResTy QPR:$dst),
1244 (ResTy (ShOp (ResTy QPR:$src1),
1245 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1247 let isCommutable = 0;
1249 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
1250 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1251 : N3V<1, 1, op21_20, op11_8, 1, 0,
1252 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1253 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$dst, $src1, $src2[$lane]","",
1254 [(set (ResTy QPR:$dst),
1255 (ResTy (ShOp (ResTy QPR:$src1),
1256 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
1258 let isCommutable = 0;
1261 // Basic 3-register intrinsics, both double- and quad-register.
1262 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1263 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1264 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1265 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1266 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), f, itin,
1267 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1268 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
1269 let isCommutable = Commutable;
1271 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1272 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1273 : N3V<0, 1, op21_20, op11_8, 1, 0,
1274 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1275 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1276 [(set (Ty DPR:$dst),
1277 (Ty (IntOp (Ty DPR:$src1),
1278 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
1280 let isCommutable = 0;
1282 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1283 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1284 : N3V<0, 1, op21_20, op11_8, 1, 0,
1285 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1286 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1287 [(set (Ty DPR:$dst),
1288 (Ty (IntOp (Ty DPR:$src1),
1289 (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
1290 let isCommutable = 0;
1293 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1294 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1295 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1296 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1297 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), f, itin,
1298 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1299 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
1300 let isCommutable = Commutable;
1302 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1303 string OpcodeStr, string Dt,
1304 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1305 : N3V<1, 1, op21_20, op11_8, 1, 0,
1306 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1307 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1308 [(set (ResTy QPR:$dst),
1309 (ResTy (IntOp (ResTy QPR:$src1),
1310 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1312 let isCommutable = 0;
1314 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1315 string OpcodeStr, string Dt,
1316 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1317 : N3V<1, 1, op21_20, op11_8, 1, 0,
1318 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1319 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1320 [(set (ResTy QPR:$dst),
1321 (ResTy (IntOp (ResTy QPR:$src1),
1322 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
1324 let isCommutable = 0;
1327 // Multiply-Add/Sub operations: single-, double- and quad-register.
1328 class N3VSMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1329 InstrItinClass itin, string OpcodeStr, string Dt,
1330 ValueType Ty, SDNode MulOp, SDNode OpNode>
1331 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1332 (outs DPR_VFP2:$dst),
1333 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), N3RegFrm, itin,
1334 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst", []>;
1336 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1337 InstrItinClass itin, string OpcodeStr, string Dt,
1338 ValueType Ty, SDNode MulOp, SDNode OpNode>
1339 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1340 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1341 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1342 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
1343 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
1344 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1345 string OpcodeStr, string Dt,
1346 ValueType Ty, SDNode MulOp, SDNode ShOp>
1347 : N3V<0, 1, op21_20, op11_8, 1, 0,
1349 (ins DPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1351 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1352 [(set (Ty DPR:$dst),
1353 (Ty (ShOp (Ty DPR:$src1),
1354 (Ty (MulOp DPR:$src2,
1355 (Ty (NEONvduplane (Ty DPR_VFP2:$src3),
1357 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1358 string OpcodeStr, string Dt,
1359 ValueType Ty, SDNode MulOp, SDNode ShOp>
1360 : N3V<0, 1, op21_20, op11_8, 1, 0,
1362 (ins DPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1364 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1365 [(set (Ty DPR:$dst),
1366 (Ty (ShOp (Ty DPR:$src1),
1367 (Ty (MulOp DPR:$src2,
1368 (Ty (NEONvduplane (Ty DPR_8:$src3),
1371 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1372 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
1373 SDNode MulOp, SDNode OpNode>
1374 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1375 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), N3RegFrm, itin,
1376 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1377 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
1378 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
1379 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1380 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1381 SDNode MulOp, SDNode ShOp>
1382 : N3V<1, 1, op21_20, op11_8, 1, 0,
1384 (ins QPR:$src1, QPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1386 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1387 [(set (ResTy QPR:$dst),
1388 (ResTy (ShOp (ResTy QPR:$src1),
1389 (ResTy (MulOp QPR:$src2,
1390 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src3),
1392 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1393 string OpcodeStr, string Dt,
1394 ValueType ResTy, ValueType OpTy,
1395 SDNode MulOp, SDNode ShOp>
1396 : N3V<1, 1, op21_20, op11_8, 1, 0,
1398 (ins QPR:$src1, QPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1400 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1401 [(set (ResTy QPR:$dst),
1402 (ResTy (ShOp (ResTy QPR:$src1),
1403 (ResTy (MulOp QPR:$src2,
1404 (ResTy (NEONvduplane (OpTy DPR_8:$src3),
1407 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
1408 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1409 InstrItinClass itin, string OpcodeStr, string Dt,
1410 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
1411 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1412 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1413 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1414 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
1415 (Ty (IntOp (Ty DPR:$src2), (Ty DPR:$src3))))))]>;
1416 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1417 InstrItinClass itin, string OpcodeStr, string Dt,
1418 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
1419 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1420 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), N3RegFrm, itin,
1421 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1422 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
1423 (Ty (IntOp (Ty QPR:$src2), (Ty QPR:$src3))))))]>;
1425 // Neon 3-argument intrinsics, both double- and quad-register.
1426 // The destination register is also used as the first source operand register.
1427 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1428 InstrItinClass itin, string OpcodeStr, string Dt,
1429 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1430 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1431 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1432 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1433 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
1434 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
1435 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1436 InstrItinClass itin, string OpcodeStr, string Dt,
1437 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1438 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1439 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), N3RegFrm, itin,
1440 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1441 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
1442 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
1444 // Long Multiply-Add/Sub operations.
1445 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1446 InstrItinClass itin, string OpcodeStr, string Dt,
1447 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
1448 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1449 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1450 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1451 [(set QPR:$dst, (OpNode (TyQ QPR:$src1),
1452 (TyQ (MulOp (TyD DPR:$src2),
1453 (TyD DPR:$src3)))))]>;
1454 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
1455 InstrItinClass itin, string OpcodeStr, string Dt,
1456 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
1457 : N3V<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$dst),
1458 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1460 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1462 (OpNode (TyQ QPR:$src1),
1463 (TyQ (MulOp (TyD DPR:$src2),
1464 (TyD (NEONvduplane (TyD DPR_VFP2:$src3),
1466 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1467 InstrItinClass itin, string OpcodeStr, string Dt,
1468 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
1469 : N3V<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$dst),
1470 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1472 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1474 (OpNode (TyQ QPR:$src1),
1475 (TyQ (MulOp (TyD DPR:$src2),
1476 (TyD (NEONvduplane (TyD DPR_8:$src3),
1479 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
1480 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1481 InstrItinClass itin, string OpcodeStr, string Dt,
1482 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
1484 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1485 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1486 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1487 [(set QPR:$dst, (OpNode (TyQ QPR:$src1),
1488 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$src2),
1489 (TyD DPR:$src3)))))))]>;
1491 // Neon Long 3-argument intrinsic. The destination register is
1492 // a quad-register and is also used as the first source operand register.
1493 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1494 InstrItinClass itin, string OpcodeStr, string Dt,
1495 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
1496 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1497 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1498 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1500 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
1501 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1502 string OpcodeStr, string Dt,
1503 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1504 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1506 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1508 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1509 [(set (ResTy QPR:$dst),
1510 (ResTy (IntOp (ResTy QPR:$src1),
1512 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src3),
1514 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1515 InstrItinClass itin, string OpcodeStr, string Dt,
1516 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1517 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1519 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1521 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1522 [(set (ResTy QPR:$dst),
1523 (ResTy (IntOp (ResTy QPR:$src1),
1525 (OpTy (NEONvduplane (OpTy DPR_8:$src3),
1528 // Narrowing 3-register intrinsics.
1529 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1530 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
1531 Intrinsic IntOp, bit Commutable>
1532 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1533 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINi4D,
1534 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1535 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
1536 let isCommutable = Commutable;
1539 // Long 3-register operations.
1540 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1541 InstrItinClass itin, string OpcodeStr, string Dt,
1542 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
1543 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1544 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1545 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1546 [(set QPR:$dst, (TyQ (OpNode (TyD DPR:$src1), (TyD DPR:$src2))))]> {
1547 let isCommutable = Commutable;
1549 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
1550 InstrItinClass itin, string OpcodeStr, string Dt,
1551 ValueType TyQ, ValueType TyD, SDNode OpNode>
1552 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1553 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1554 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1556 (TyQ (OpNode (TyD DPR:$src1),
1557 (TyD (NEONvduplane (TyD DPR_VFP2:$src2),imm:$lane)))))]>;
1558 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1559 InstrItinClass itin, string OpcodeStr, string Dt,
1560 ValueType TyQ, ValueType TyD, SDNode OpNode>
1561 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1562 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1563 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1565 (TyQ (OpNode (TyD DPR:$src1),
1566 (TyD (NEONvduplane (TyD DPR_8:$src2), imm:$lane)))))]>;
1568 // Long 3-register operations with explicitly extended operands.
1569 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1570 InstrItinClass itin, string OpcodeStr, string Dt,
1571 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
1573 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1574 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1575 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1576 [(set QPR:$dst, (OpNode (TyQ (ExtOp (TyD DPR:$src1))),
1577 (TyQ (ExtOp (TyD DPR:$src2)))))]> {
1578 let isCommutable = Commutable;
1581 // Long 3-register intrinsics with explicit extend (VABDL).
1582 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1583 InstrItinClass itin, string OpcodeStr, string Dt,
1584 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
1586 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1587 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1588 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1589 [(set QPR:$dst, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$src1),
1590 (TyD DPR:$src2))))))]> {
1591 let isCommutable = Commutable;
1594 // Long 3-register intrinsics.
1595 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1596 InstrItinClass itin, string OpcodeStr, string Dt,
1597 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
1598 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1599 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1600 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1601 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
1602 let isCommutable = Commutable;
1604 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1605 string OpcodeStr, string Dt,
1606 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1607 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1608 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1609 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1610 [(set (ResTy QPR:$dst),
1611 (ResTy (IntOp (OpTy DPR:$src1),
1612 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1614 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1615 InstrItinClass itin, string OpcodeStr, string Dt,
1616 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1617 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1618 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1619 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1620 [(set (ResTy QPR:$dst),
1621 (ResTy (IntOp (OpTy DPR:$src1),
1622 (OpTy (NEONvduplane (OpTy DPR_8:$src2),
1625 // Wide 3-register operations.
1626 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1627 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
1628 SDNode OpNode, SDNode ExtOp, bit Commutable>
1629 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1630 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), N3RegFrm, IIC_VSUBiD,
1631 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1632 [(set QPR:$dst, (OpNode (TyQ QPR:$src1),
1633 (TyQ (ExtOp (TyD DPR:$src2)))))]> {
1634 let isCommutable = Commutable;
1637 // Pairwise long 2-register intrinsics, both double- and quad-register.
1638 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1639 bits<2> op17_16, bits<5> op11_7, bit op4,
1640 string OpcodeStr, string Dt,
1641 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1642 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1643 (ins DPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
1644 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
1645 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1646 bits<2> op17_16, bits<5> op11_7, bit op4,
1647 string OpcodeStr, string Dt,
1648 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1649 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1650 (ins QPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
1651 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
1653 // Pairwise long 2-register accumulate intrinsics,
1654 // both double- and quad-register.
1655 // The destination register is also used as the first source operand register.
1656 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1657 bits<2> op17_16, bits<5> op11_7, bit op4,
1658 string OpcodeStr, string Dt,
1659 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1660 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
1661 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), IIC_VPALiD,
1662 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
1663 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
1664 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1665 bits<2> op17_16, bits<5> op11_7, bit op4,
1666 string OpcodeStr, string Dt,
1667 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1668 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
1669 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VPALiQ,
1670 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
1671 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
1673 // Shift by immediate,
1674 // both double- and quad-register.
1675 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1676 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1677 ValueType Ty, SDNode OpNode>
1678 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1679 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), f, itin,
1680 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1681 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
1682 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1683 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1684 ValueType Ty, SDNode OpNode>
1685 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1686 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), f, itin,
1687 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1688 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
1690 // Long shift by immediate.
1691 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1692 string OpcodeStr, string Dt,
1693 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1694 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1695 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), N2RegVShLFrm,
1696 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1697 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
1698 (i32 imm:$SIMM))))]>;
1700 // Narrow shift by immediate.
1701 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1702 InstrItinClass itin, string OpcodeStr, string Dt,
1703 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1704 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1705 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), N2RegVShRFrm, itin,
1706 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1707 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
1708 (i32 imm:$SIMM))))]>;
1710 // Shift right by immediate and accumulate,
1711 // both double- and quad-register.
1712 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1713 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1714 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1715 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
1716 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1717 [(set DPR:$dst, (Ty (add DPR:$src1,
1718 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
1719 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1720 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1721 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1722 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
1723 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1724 [(set QPR:$dst, (Ty (add QPR:$src1,
1725 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
1727 // Shift by immediate and insert,
1728 // both double- and quad-register.
1729 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1730 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
1731 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1732 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), f, IIC_VSHLiD,
1733 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1734 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
1735 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1736 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
1737 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1738 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), f, IIC_VSHLiQ,
1739 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1740 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
1742 // Convert, with fractional bits immediate,
1743 // both double- and quad-register.
1744 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1745 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1747 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1748 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NVCVTFrm,
1749 IIC_VUNAD, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1750 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
1751 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1752 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1754 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1755 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NVCVTFrm,
1756 IIC_VUNAQ, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1757 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
1759 //===----------------------------------------------------------------------===//
1761 //===----------------------------------------------------------------------===//
1763 // Abbreviations used in multiclass suffixes:
1764 // Q = quarter int (8 bit) elements
1765 // H = half int (16 bit) elements
1766 // S = single int (32 bit) elements
1767 // D = double int (64 bit) elements
1769 // Neon 2-register vector operations -- for disassembly only.
1771 // First with only element sizes of 8, 16 and 32 bits:
1772 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1773 bits<5> op11_7, bit op4, string opc, string Dt,
1775 // 64-bit vector types.
1776 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
1777 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1778 opc, !strconcat(Dt, "8"), asm, "", []>;
1779 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
1780 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1781 opc, !strconcat(Dt, "16"), asm, "", []>;
1782 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
1783 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1784 opc, !strconcat(Dt, "32"), asm, "", []>;
1785 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
1786 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1787 opc, "f32", asm, "", []> {
1788 let Inst{10} = 1; // overwrite F = 1
1791 // 128-bit vector types.
1792 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
1793 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1794 opc, !strconcat(Dt, "8"), asm, "", []>;
1795 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
1796 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1797 opc, !strconcat(Dt, "16"), asm, "", []>;
1798 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
1799 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1800 opc, !strconcat(Dt, "32"), asm, "", []>;
1801 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
1802 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1803 opc, "f32", asm, "", []> {
1804 let Inst{10} = 1; // overwrite F = 1
1808 // Neon 3-register vector operations.
1810 // First with only element sizes of 8, 16 and 32 bits:
1811 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1812 InstrItinClass itinD16, InstrItinClass itinD32,
1813 InstrItinClass itinQ16, InstrItinClass itinQ32,
1814 string OpcodeStr, string Dt,
1815 SDNode OpNode, bit Commutable = 0> {
1816 // 64-bit vector types.
1817 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
1818 OpcodeStr, !strconcat(Dt, "8"),
1819 v8i8, v8i8, OpNode, Commutable>;
1820 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
1821 OpcodeStr, !strconcat(Dt, "16"),
1822 v4i16, v4i16, OpNode, Commutable>;
1823 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
1824 OpcodeStr, !strconcat(Dt, "32"),
1825 v2i32, v2i32, OpNode, Commutable>;
1827 // 128-bit vector types.
1828 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
1829 OpcodeStr, !strconcat(Dt, "8"),
1830 v16i8, v16i8, OpNode, Commutable>;
1831 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
1832 OpcodeStr, !strconcat(Dt, "16"),
1833 v8i16, v8i16, OpNode, Commutable>;
1834 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
1835 OpcodeStr, !strconcat(Dt, "32"),
1836 v4i32, v4i32, OpNode, Commutable>;
1839 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
1840 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1842 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
1844 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1845 v8i16, v4i16, ShOp>;
1846 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
1847 v4i32, v2i32, ShOp>;
1850 // ....then also with element size 64 bits:
1851 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1852 InstrItinClass itinD, InstrItinClass itinQ,
1853 string OpcodeStr, string Dt,
1854 SDNode OpNode, bit Commutable = 0>
1855 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
1856 OpcodeStr, Dt, OpNode, Commutable> {
1857 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
1858 OpcodeStr, !strconcat(Dt, "64"),
1859 v1i64, v1i64, OpNode, Commutable>;
1860 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
1861 OpcodeStr, !strconcat(Dt, "64"),
1862 v2i64, v2i64, OpNode, Commutable>;
1866 // Neon Narrowing 2-register vector operations,
1867 // source operand element sizes of 16, 32 and 64 bits:
1868 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1869 bits<5> op11_7, bit op6, bit op4,
1870 InstrItinClass itin, string OpcodeStr, string Dt,
1872 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
1873 itin, OpcodeStr, !strconcat(Dt, "16"),
1874 v8i8, v8i16, OpNode>;
1875 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
1876 itin, OpcodeStr, !strconcat(Dt, "32"),
1877 v4i16, v4i32, OpNode>;
1878 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
1879 itin, OpcodeStr, !strconcat(Dt, "64"),
1880 v2i32, v2i64, OpNode>;
1883 // Neon Narrowing 2-register vector intrinsics,
1884 // source operand element sizes of 16, 32 and 64 bits:
1885 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1886 bits<5> op11_7, bit op6, bit op4,
1887 InstrItinClass itin, string OpcodeStr, string Dt,
1889 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
1890 itin, OpcodeStr, !strconcat(Dt, "16"),
1891 v8i8, v8i16, IntOp>;
1892 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
1893 itin, OpcodeStr, !strconcat(Dt, "32"),
1894 v4i16, v4i32, IntOp>;
1895 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
1896 itin, OpcodeStr, !strconcat(Dt, "64"),
1897 v2i32, v2i64, IntOp>;
1901 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
1902 // source operand element sizes of 16, 32 and 64 bits:
1903 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
1904 string OpcodeStr, string Dt, SDNode OpNode> {
1905 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1906 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
1907 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1908 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
1909 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1910 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
1914 // Neon 3-register vector intrinsics.
1916 // First with only element sizes of 16 and 32 bits:
1917 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
1918 InstrItinClass itinD16, InstrItinClass itinD32,
1919 InstrItinClass itinQ16, InstrItinClass itinQ32,
1920 string OpcodeStr, string Dt,
1921 Intrinsic IntOp, bit Commutable = 0> {
1922 // 64-bit vector types.
1923 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
1924 OpcodeStr, !strconcat(Dt, "16"),
1925 v4i16, v4i16, IntOp, Commutable>;
1926 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
1927 OpcodeStr, !strconcat(Dt, "32"),
1928 v2i32, v2i32, IntOp, Commutable>;
1930 // 128-bit vector types.
1931 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
1932 OpcodeStr, !strconcat(Dt, "16"),
1933 v8i16, v8i16, IntOp, Commutable>;
1934 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
1935 OpcodeStr, !strconcat(Dt, "32"),
1936 v4i32, v4i32, IntOp, Commutable>;
1939 multiclass N3VIntSL_HS<bits<4> op11_8,
1940 InstrItinClass itinD16, InstrItinClass itinD32,
1941 InstrItinClass itinQ16, InstrItinClass itinQ32,
1942 string OpcodeStr, string Dt, Intrinsic IntOp> {
1943 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
1944 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
1945 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
1946 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
1947 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
1948 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
1949 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
1950 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
1953 // ....then also with element size of 8 bits:
1954 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
1955 InstrItinClass itinD16, InstrItinClass itinD32,
1956 InstrItinClass itinQ16, InstrItinClass itinQ32,
1957 string OpcodeStr, string Dt,
1958 Intrinsic IntOp, bit Commutable = 0>
1959 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
1960 OpcodeStr, Dt, IntOp, Commutable> {
1961 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
1962 OpcodeStr, !strconcat(Dt, "8"),
1963 v8i8, v8i8, IntOp, Commutable>;
1964 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
1965 OpcodeStr, !strconcat(Dt, "8"),
1966 v16i8, v16i8, IntOp, Commutable>;
1969 // ....then also with element size of 64 bits:
1970 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
1971 InstrItinClass itinD16, InstrItinClass itinD32,
1972 InstrItinClass itinQ16, InstrItinClass itinQ32,
1973 string OpcodeStr, string Dt,
1974 Intrinsic IntOp, bit Commutable = 0>
1975 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
1976 OpcodeStr, Dt, IntOp, Commutable> {
1977 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
1978 OpcodeStr, !strconcat(Dt, "64"),
1979 v1i64, v1i64, IntOp, Commutable>;
1980 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
1981 OpcodeStr, !strconcat(Dt, "64"),
1982 v2i64, v2i64, IntOp, Commutable>;
1985 // Neon Narrowing 3-register vector intrinsics,
1986 // source operand element sizes of 16, 32 and 64 bits:
1987 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1988 string OpcodeStr, string Dt,
1989 Intrinsic IntOp, bit Commutable = 0> {
1990 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
1991 OpcodeStr, !strconcat(Dt, "16"),
1992 v8i8, v8i16, IntOp, Commutable>;
1993 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
1994 OpcodeStr, !strconcat(Dt, "32"),
1995 v4i16, v4i32, IntOp, Commutable>;
1996 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
1997 OpcodeStr, !strconcat(Dt, "64"),
1998 v2i32, v2i64, IntOp, Commutable>;
2002 // Neon Long 3-register vector operations.
2004 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2005 InstrItinClass itin16, InstrItinClass itin32,
2006 string OpcodeStr, string Dt,
2007 SDNode OpNode, bit Commutable = 0> {
2008 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
2009 OpcodeStr, !strconcat(Dt, "8"),
2010 v8i16, v8i8, OpNode, Commutable>;
2011 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
2012 OpcodeStr, !strconcat(Dt, "16"),
2013 v4i32, v4i16, OpNode, Commutable>;
2014 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
2015 OpcodeStr, !strconcat(Dt, "32"),
2016 v2i64, v2i32, OpNode, Commutable>;
2019 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
2020 InstrItinClass itin, string OpcodeStr, string Dt,
2022 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
2023 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2024 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
2025 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2028 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2029 InstrItinClass itin16, InstrItinClass itin32,
2030 string OpcodeStr, string Dt,
2031 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2032 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
2033 OpcodeStr, !strconcat(Dt, "8"),
2034 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2035 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
2036 OpcodeStr, !strconcat(Dt, "16"),
2037 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2038 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
2039 OpcodeStr, !strconcat(Dt, "32"),
2040 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2043 // Neon Long 3-register vector intrinsics.
2045 // First with only element sizes of 16 and 32 bits:
2046 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2047 InstrItinClass itin16, InstrItinClass itin32,
2048 string OpcodeStr, string Dt,
2049 Intrinsic IntOp, bit Commutable = 0> {
2050 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
2051 OpcodeStr, !strconcat(Dt, "16"),
2052 v4i32, v4i16, IntOp, Commutable>;
2053 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
2054 OpcodeStr, !strconcat(Dt, "32"),
2055 v2i64, v2i32, IntOp, Commutable>;
2058 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
2059 InstrItinClass itin, string OpcodeStr, string Dt,
2061 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
2062 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2063 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
2064 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2067 // ....then also with element size of 8 bits:
2068 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2069 InstrItinClass itin16, InstrItinClass itin32,
2070 string OpcodeStr, string Dt,
2071 Intrinsic IntOp, bit Commutable = 0>
2072 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
2073 IntOp, Commutable> {
2074 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
2075 OpcodeStr, !strconcat(Dt, "8"),
2076 v8i16, v8i8, IntOp, Commutable>;
2079 // ....with explicit extend (VABDL).
2080 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2081 InstrItinClass itin, string OpcodeStr, string Dt,
2082 Intrinsic IntOp, SDNode ExtOp, bit Commutable = 0> {
2083 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
2084 OpcodeStr, !strconcat(Dt, "8"),
2085 v8i16, v8i8, IntOp, ExtOp, Commutable>;
2086 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
2087 OpcodeStr, !strconcat(Dt, "16"),
2088 v4i32, v4i16, IntOp, ExtOp, Commutable>;
2089 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
2090 OpcodeStr, !strconcat(Dt, "32"),
2091 v2i64, v2i32, IntOp, ExtOp, Commutable>;
2095 // Neon Wide 3-register vector intrinsics,
2096 // source operand element sizes of 8, 16 and 32 bits:
2097 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2098 string OpcodeStr, string Dt,
2099 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2100 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
2101 OpcodeStr, !strconcat(Dt, "8"),
2102 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2103 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
2104 OpcodeStr, !strconcat(Dt, "16"),
2105 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2106 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
2107 OpcodeStr, !strconcat(Dt, "32"),
2108 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2112 // Neon Multiply-Op vector operations,
2113 // element sizes of 8, 16 and 32 bits:
2114 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2115 InstrItinClass itinD16, InstrItinClass itinD32,
2116 InstrItinClass itinQ16, InstrItinClass itinQ32,
2117 string OpcodeStr, string Dt, SDNode OpNode> {
2118 // 64-bit vector types.
2119 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
2120 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
2121 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
2122 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
2123 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
2124 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
2126 // 128-bit vector types.
2127 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
2128 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
2129 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
2130 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
2131 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
2132 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
2135 multiclass N3VMulOpSL_HS<bits<4> op11_8,
2136 InstrItinClass itinD16, InstrItinClass itinD32,
2137 InstrItinClass itinQ16, InstrItinClass itinQ32,
2138 string OpcodeStr, string Dt, SDNode ShOp> {
2139 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
2140 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
2141 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
2142 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
2143 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
2144 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
2146 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
2147 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
2151 // Neon Intrinsic-Op vector operations,
2152 // element sizes of 8, 16 and 32 bits:
2153 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2154 InstrItinClass itinD, InstrItinClass itinQ,
2155 string OpcodeStr, string Dt, Intrinsic IntOp,
2157 // 64-bit vector types.
2158 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
2159 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
2160 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
2161 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
2162 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
2163 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
2165 // 128-bit vector types.
2166 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
2167 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
2168 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
2169 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
2170 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
2171 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
2174 // Neon 3-argument intrinsics,
2175 // element sizes of 8, 16 and 32 bits:
2176 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2177 InstrItinClass itinD, InstrItinClass itinQ,
2178 string OpcodeStr, string Dt, Intrinsic IntOp> {
2179 // 64-bit vector types.
2180 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
2181 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2182 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
2183 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
2184 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
2185 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
2187 // 128-bit vector types.
2188 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
2189 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
2190 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
2191 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
2192 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
2193 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
2197 // Neon Long Multiply-Op vector operations,
2198 // element sizes of 8, 16 and 32 bits:
2199 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2200 InstrItinClass itin16, InstrItinClass itin32,
2201 string OpcodeStr, string Dt, SDNode MulOp,
2203 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
2204 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
2205 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
2206 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
2207 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
2208 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
2211 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
2212 string Dt, SDNode MulOp, SDNode OpNode> {
2213 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
2214 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
2215 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
2216 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
2220 // Neon Long 3-argument intrinsics.
2222 // First with only element sizes of 16 and 32 bits:
2223 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2224 InstrItinClass itin16, InstrItinClass itin32,
2225 string OpcodeStr, string Dt, Intrinsic IntOp> {
2226 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
2227 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2228 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
2229 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2232 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
2233 string OpcodeStr, string Dt, Intrinsic IntOp> {
2234 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
2235 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
2236 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
2237 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2240 // ....then also with element size of 8 bits:
2241 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2242 InstrItinClass itin16, InstrItinClass itin32,
2243 string OpcodeStr, string Dt, Intrinsic IntOp>
2244 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
2245 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
2246 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
2249 // ....with explicit extend (VABAL).
2250 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2251 InstrItinClass itin, string OpcodeStr, string Dt,
2252 Intrinsic IntOp, SDNode ExtOp, SDNode OpNode> {
2253 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
2254 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
2255 IntOp, ExtOp, OpNode>;
2256 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
2257 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
2258 IntOp, ExtOp, OpNode>;
2259 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
2260 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
2261 IntOp, ExtOp, OpNode>;
2265 // Neon 2-register vector intrinsics,
2266 // element sizes of 8, 16 and 32 bits:
2267 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2268 bits<5> op11_7, bit op4,
2269 InstrItinClass itinD, InstrItinClass itinQ,
2270 string OpcodeStr, string Dt, Intrinsic IntOp> {
2271 // 64-bit vector types.
2272 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2273 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2274 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2275 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
2276 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2277 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
2279 // 128-bit vector types.
2280 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2281 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
2282 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2283 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
2284 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2285 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
2289 // Neon Pairwise long 2-register intrinsics,
2290 // element sizes of 8, 16 and 32 bits:
2291 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2292 bits<5> op11_7, bit op4,
2293 string OpcodeStr, string Dt, Intrinsic IntOp> {
2294 // 64-bit vector types.
2295 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2296 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
2297 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2298 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
2299 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2300 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
2302 // 128-bit vector types.
2303 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2304 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
2305 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2306 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
2307 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2308 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
2312 // Neon Pairwise long 2-register accumulate intrinsics,
2313 // element sizes of 8, 16 and 32 bits:
2314 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2315 bits<5> op11_7, bit op4,
2316 string OpcodeStr, string Dt, Intrinsic IntOp> {
2317 // 64-bit vector types.
2318 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2319 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
2320 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2321 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
2322 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2323 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
2325 // 128-bit vector types.
2326 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2327 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
2328 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2329 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
2330 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2331 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
2335 // Neon 2-register vector shift by immediate,
2336 // with f of either N2RegVShLFrm or N2RegVShRFrm
2337 // element sizes of 8, 16, 32 and 64 bits:
2338 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2339 InstrItinClass itin, string OpcodeStr, string Dt,
2340 SDNode OpNode, Format f> {
2341 // 64-bit vector types.
2342 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2343 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
2344 let Inst{21-19} = 0b001; // imm6 = 001xxx
2346 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2347 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
2348 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2350 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2351 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
2352 let Inst{21} = 0b1; // imm6 = 1xxxxx
2354 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, f, itin,
2355 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
2358 // 128-bit vector types.
2359 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
2360 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
2361 let Inst{21-19} = 0b001; // imm6 = 001xxx
2363 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
2364 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
2365 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2367 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
2368 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
2369 let Inst{21} = 0b1; // imm6 = 1xxxxx
2371 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, f, itin,
2372 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
2376 // Neon Shift-Accumulate vector operations,
2377 // element sizes of 8, 16, 32 and 64 bits:
2378 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2379 string OpcodeStr, string Dt, SDNode ShOp> {
2380 // 64-bit vector types.
2381 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4,
2382 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
2383 let Inst{21-19} = 0b001; // imm6 = 001xxx
2385 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4,
2386 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
2387 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2389 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4,
2390 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
2391 let Inst{21} = 0b1; // imm6 = 1xxxxx
2393 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4,
2394 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
2397 // 128-bit vector types.
2398 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4,
2399 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
2400 let Inst{21-19} = 0b001; // imm6 = 001xxx
2402 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4,
2403 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
2404 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2406 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4,
2407 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
2408 let Inst{21} = 0b1; // imm6 = 1xxxxx
2410 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4,
2411 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
2416 // Neon Shift-Insert vector operations,
2417 // with f of either N2RegVShLFrm or N2RegVShRFrm
2418 // element sizes of 8, 16, 32 and 64 bits:
2419 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2420 string OpcodeStr, SDNode ShOp,
2422 // 64-bit vector types.
2423 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4,
2424 f, OpcodeStr, "8", v8i8, ShOp> {
2425 let Inst{21-19} = 0b001; // imm6 = 001xxx
2427 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4,
2428 f, OpcodeStr, "16", v4i16, ShOp> {
2429 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2431 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4,
2432 f, OpcodeStr, "32", v2i32, ShOp> {
2433 let Inst{21} = 0b1; // imm6 = 1xxxxx
2435 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4,
2436 f, OpcodeStr, "64", v1i64, ShOp>;
2439 // 128-bit vector types.
2440 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4,
2441 f, OpcodeStr, "8", v16i8, ShOp> {
2442 let Inst{21-19} = 0b001; // imm6 = 001xxx
2444 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4,
2445 f, OpcodeStr, "16", v8i16, ShOp> {
2446 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2448 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4,
2449 f, OpcodeStr, "32", v4i32, ShOp> {
2450 let Inst{21} = 0b1; // imm6 = 1xxxxx
2452 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4,
2453 f, OpcodeStr, "64", v2i64, ShOp>;
2457 // Neon Shift Long operations,
2458 // element sizes of 8, 16, 32 bits:
2459 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
2460 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
2461 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
2462 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
2463 let Inst{21-19} = 0b001; // imm6 = 001xxx
2465 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
2466 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
2467 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2469 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
2470 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
2471 let Inst{21} = 0b1; // imm6 = 1xxxxx
2475 // Neon Shift Narrow operations,
2476 // element sizes of 16, 32, 64 bits:
2477 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
2478 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
2480 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
2481 OpcodeStr, !strconcat(Dt, "16"), v8i8, v8i16, OpNode> {
2482 let Inst{21-19} = 0b001; // imm6 = 001xxx
2484 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
2485 OpcodeStr, !strconcat(Dt, "32"), v4i16, v4i32, OpNode> {
2486 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2488 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
2489 OpcodeStr, !strconcat(Dt, "64"), v2i32, v2i64, OpNode> {
2490 let Inst{21} = 0b1; // imm6 = 1xxxxx
2494 //===----------------------------------------------------------------------===//
2495 // Instruction Definitions.
2496 //===----------------------------------------------------------------------===//
2498 // Vector Add Operations.
2500 // VADD : Vector Add (integer and floating-point)
2501 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
2503 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
2504 v2f32, v2f32, fadd, 1>;
2505 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
2506 v4f32, v4f32, fadd, 1>;
2507 // VADDL : Vector Add Long (Q = D + D)
2508 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
2509 "vaddl", "s", add, sext, 1>;
2510 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
2511 "vaddl", "u", add, zext, 1>;
2512 // VADDW : Vector Add Wide (Q = Q + D)
2513 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
2514 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
2515 // VHADD : Vector Halving Add
2516 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
2517 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2518 "vhadd", "s", int_arm_neon_vhadds, 1>;
2519 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
2520 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2521 "vhadd", "u", int_arm_neon_vhaddu, 1>;
2522 // VRHADD : Vector Rounding Halving Add
2523 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
2524 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2525 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
2526 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
2527 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2528 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
2529 // VQADD : Vector Saturating Add
2530 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
2531 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2532 "vqadd", "s", int_arm_neon_vqadds, 1>;
2533 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
2534 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2535 "vqadd", "u", int_arm_neon_vqaddu, 1>;
2536 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
2537 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
2538 int_arm_neon_vaddhn, 1>;
2539 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
2540 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
2541 int_arm_neon_vraddhn, 1>;
2543 // Vector Multiply Operations.
2545 // VMUL : Vector Multiply (integer, polynomial and floating-point)
2546 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
2547 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
2548 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
2549 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
2550 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
2551 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
2552 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VBIND, "vmul", "f32",
2553 v2f32, v2f32, fmul, 1>;
2554 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VBINQ, "vmul", "f32",
2555 v4f32, v4f32, fmul, 1>;
2556 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
2557 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
2558 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
2561 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
2562 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
2563 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
2564 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2565 (DSubReg_i16_reg imm:$lane))),
2566 (SubReg_i16_lane imm:$lane)))>;
2567 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
2568 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
2569 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
2570 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2571 (DSubReg_i32_reg imm:$lane))),
2572 (SubReg_i32_lane imm:$lane)))>;
2573 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
2574 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
2575 (v4f32 (VMULslfq (v4f32 QPR:$src1),
2576 (v2f32 (EXTRACT_SUBREG QPR:$src2,
2577 (DSubReg_i32_reg imm:$lane))),
2578 (SubReg_i32_lane imm:$lane)))>;
2580 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
2581 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
2582 IIC_VMULi16Q, IIC_VMULi32Q,
2583 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
2584 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
2585 IIC_VMULi16Q, IIC_VMULi32Q,
2586 "vqdmulh", "s", int_arm_neon_vqdmulh>;
2587 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
2588 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
2590 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
2591 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2592 (DSubReg_i16_reg imm:$lane))),
2593 (SubReg_i16_lane imm:$lane)))>;
2594 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
2595 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
2597 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
2598 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2599 (DSubReg_i32_reg imm:$lane))),
2600 (SubReg_i32_lane imm:$lane)))>;
2602 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
2603 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
2604 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
2605 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
2606 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
2607 IIC_VMULi16Q, IIC_VMULi32Q,
2608 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
2609 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
2610 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
2612 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
2613 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2614 (DSubReg_i16_reg imm:$lane))),
2615 (SubReg_i16_lane imm:$lane)))>;
2616 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
2617 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
2619 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
2620 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2621 (DSubReg_i32_reg imm:$lane))),
2622 (SubReg_i32_lane imm:$lane)))>;
2624 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
2625 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
2626 "vmull", "s", NEONvmulls, 1>;
2627 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
2628 "vmull", "u", NEONvmullu, 1>;
2629 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
2630 v8i16, v8i8, int_arm_neon_vmullp, 1>;
2631 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
2632 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
2634 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
2635 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
2636 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
2637 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
2638 "vqdmull", "s", int_arm_neon_vqdmull>;
2640 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
2642 // VMLA : Vector Multiply Accumulate (integer and floating-point)
2643 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
2644 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
2645 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
2647 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
2649 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
2650 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
2651 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
2653 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
2654 v4f32, v2f32, fmul, fadd>;
2656 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
2657 (mul (v8i16 QPR:$src2),
2658 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
2659 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
2660 (v4i16 (EXTRACT_SUBREG QPR:$src3,
2661 (DSubReg_i16_reg imm:$lane))),
2662 (SubReg_i16_lane imm:$lane)))>;
2664 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
2665 (mul (v4i32 QPR:$src2),
2666 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
2667 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
2668 (v2i32 (EXTRACT_SUBREG QPR:$src3,
2669 (DSubReg_i32_reg imm:$lane))),
2670 (SubReg_i32_lane imm:$lane)))>;
2672 def : Pat<(v4f32 (fadd (v4f32 QPR:$src1),
2673 (fmul (v4f32 QPR:$src2),
2674 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
2675 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
2677 (v2f32 (EXTRACT_SUBREG QPR:$src3,
2678 (DSubReg_i32_reg imm:$lane))),
2679 (SubReg_i32_lane imm:$lane)))>;
2681 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
2682 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
2683 "vmlal", "s", NEONvmulls, add>;
2684 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
2685 "vmlal", "u", NEONvmullu, add>;
2687 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
2688 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
2690 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
2691 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
2692 "vqdmlal", "s", int_arm_neon_vqdmlal>;
2693 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
2695 // VMLS : Vector Multiply Subtract (integer and floating-point)
2696 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
2697 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
2698 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
2700 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
2702 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
2703 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
2704 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
2706 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
2707 v4f32, v2f32, fmul, fsub>;
2709 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
2710 (mul (v8i16 QPR:$src2),
2711 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
2712 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
2713 (v4i16 (EXTRACT_SUBREG QPR:$src3,
2714 (DSubReg_i16_reg imm:$lane))),
2715 (SubReg_i16_lane imm:$lane)))>;
2717 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
2718 (mul (v4i32 QPR:$src2),
2719 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
2720 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
2721 (v2i32 (EXTRACT_SUBREG QPR:$src3,
2722 (DSubReg_i32_reg imm:$lane))),
2723 (SubReg_i32_lane imm:$lane)))>;
2725 def : Pat<(v4f32 (fsub (v4f32 QPR:$src1),
2726 (fmul (v4f32 QPR:$src2),
2727 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
2728 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
2729 (v2f32 (EXTRACT_SUBREG QPR:$src3,
2730 (DSubReg_i32_reg imm:$lane))),
2731 (SubReg_i32_lane imm:$lane)))>;
2733 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
2734 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
2735 "vmlsl", "s", NEONvmulls, sub>;
2736 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
2737 "vmlsl", "u", NEONvmullu, sub>;
2739 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
2740 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
2742 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
2743 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
2744 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
2745 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
2747 // Vector Subtract Operations.
2749 // VSUB : Vector Subtract (integer and floating-point)
2750 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
2751 "vsub", "i", sub, 0>;
2752 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
2753 v2f32, v2f32, fsub, 0>;
2754 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
2755 v4f32, v4f32, fsub, 0>;
2756 // VSUBL : Vector Subtract Long (Q = D - D)
2757 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
2758 "vsubl", "s", sub, sext, 0>;
2759 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
2760 "vsubl", "u", sub, zext, 0>;
2761 // VSUBW : Vector Subtract Wide (Q = Q - D)
2762 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
2763 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
2764 // VHSUB : Vector Halving Subtract
2765 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
2766 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2767 "vhsub", "s", int_arm_neon_vhsubs, 0>;
2768 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
2769 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2770 "vhsub", "u", int_arm_neon_vhsubu, 0>;
2771 // VQSUB : Vector Saturing Subtract
2772 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
2773 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2774 "vqsub", "s", int_arm_neon_vqsubs, 0>;
2775 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
2776 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2777 "vqsub", "u", int_arm_neon_vqsubu, 0>;
2778 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
2779 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
2780 int_arm_neon_vsubhn, 0>;
2781 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
2782 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
2783 int_arm_neon_vrsubhn, 0>;
2785 // Vector Comparisons.
2787 // VCEQ : Vector Compare Equal
2788 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2789 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
2790 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
2792 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
2794 // For disassembly only.
2795 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
2798 // VCGE : Vector Compare Greater Than or Equal
2799 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2800 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
2801 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2802 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
2803 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
2805 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
2807 // For disassembly only.
2808 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
2810 // For disassembly only.
2811 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
2814 // VCGT : Vector Compare Greater Than
2815 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2816 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
2817 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2818 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
2819 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
2821 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
2823 // For disassembly only.
2824 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
2826 // For disassembly only.
2827 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
2830 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
2831 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
2832 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
2833 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
2834 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
2835 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
2836 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
2837 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
2838 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
2839 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
2840 // VTST : Vector Test Bits
2841 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2842 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
2844 // Vector Bitwise Operations.
2846 def vnotd : PatFrag<(ops node:$in),
2847 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
2848 def vnotq : PatFrag<(ops node:$in),
2849 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
2852 // VAND : Vector Bitwise AND
2853 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
2854 v2i32, v2i32, and, 1>;
2855 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
2856 v4i32, v4i32, and, 1>;
2858 // VEOR : Vector Bitwise Exclusive OR
2859 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
2860 v2i32, v2i32, xor, 1>;
2861 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
2862 v4i32, v4i32, xor, 1>;
2864 // VORR : Vector Bitwise OR
2865 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
2866 v2i32, v2i32, or, 1>;
2867 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
2868 v4i32, v4i32, or, 1>;
2870 // VBIC : Vector Bitwise Bit Clear (AND NOT)
2871 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2872 (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD,
2873 "vbic", "$dst, $src1, $src2", "",
2874 [(set DPR:$dst, (v2i32 (and DPR:$src1,
2875 (vnotd DPR:$src2))))]>;
2876 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2877 (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINiQ,
2878 "vbic", "$dst, $src1, $src2", "",
2879 [(set QPR:$dst, (v4i32 (and QPR:$src1,
2880 (vnotq QPR:$src2))))]>;
2882 // VORN : Vector Bitwise OR NOT
2883 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
2884 (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD,
2885 "vorn", "$dst, $src1, $src2", "",
2886 [(set DPR:$dst, (v2i32 (or DPR:$src1,
2887 (vnotd DPR:$src2))))]>;
2888 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
2889 (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINiQ,
2890 "vorn", "$dst, $src1, $src2", "",
2891 [(set QPR:$dst, (v4i32 (or QPR:$src1,
2892 (vnotq QPR:$src2))))]>;
2894 // VMVN : Vector Bitwise NOT (Immediate)
2896 let isReMaterializable = 1 in {
2897 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$dst),
2898 (ins nModImm:$SIMM), IIC_VMOVImm,
2899 "vmvn", "i16", "$dst, $SIMM", "",
2900 [(set DPR:$dst, (v4i16 (NEONvmvnImm timm:$SIMM)))]>;
2901 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$dst),
2902 (ins nModImm:$SIMM), IIC_VMOVImm,
2903 "vmvn", "i16", "$dst, $SIMM", "",
2904 [(set QPR:$dst, (v8i16 (NEONvmvnImm timm:$SIMM)))]>;
2906 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$dst),
2907 (ins nModImm:$SIMM), IIC_VMOVImm,
2908 "vmvn", "i32", "$dst, $SIMM", "",
2909 [(set DPR:$dst, (v2i32 (NEONvmvnImm timm:$SIMM)))]>;
2910 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$dst),
2911 (ins nModImm:$SIMM), IIC_VMOVImm,
2912 "vmvn", "i32", "$dst, $SIMM", "",
2913 [(set QPR:$dst, (v4i32 (NEONvmvnImm timm:$SIMM)))]>;
2916 // VMVN : Vector Bitwise NOT
2917 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
2918 (outs DPR:$dst), (ins DPR:$src), IIC_VSUBiD,
2919 "vmvn", "$dst, $src", "",
2920 [(set DPR:$dst, (v2i32 (vnotd DPR:$src)))]>;
2921 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
2922 (outs QPR:$dst), (ins QPR:$src), IIC_VSUBiD,
2923 "vmvn", "$dst, $src", "",
2924 [(set QPR:$dst, (v4i32 (vnotq QPR:$src)))]>;
2925 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
2926 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
2928 // VBSL : Vector Bitwise Select
2929 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2930 (ins DPR:$src1, DPR:$src2, DPR:$src3),
2931 N3RegFrm, IIC_VCNTiD,
2932 "vbsl", "$dst, $src2, $src3", "$src1 = $dst",
2934 (v2i32 (or (and DPR:$src2, DPR:$src1),
2935 (and DPR:$src3, (vnotd DPR:$src1)))))]>;
2936 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2937 (ins QPR:$src1, QPR:$src2, QPR:$src3),
2938 N3RegFrm, IIC_VCNTiQ,
2939 "vbsl", "$dst, $src2, $src3", "$src1 = $dst",
2941 (v4i32 (or (and QPR:$src2, QPR:$src1),
2942 (and QPR:$src3, (vnotq QPR:$src1)))))]>;
2944 // VBIF : Vector Bitwise Insert if False
2945 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
2946 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
2947 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
2948 N3RegFrm, IIC_VBINiD,
2949 "vbif", "$dst, $src2, $src3", "$src1 = $dst",
2950 [/* For disassembly only; pattern left blank */]>;
2951 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
2952 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
2953 N3RegFrm, IIC_VBINiQ,
2954 "vbif", "$dst, $src2, $src3", "$src1 = $dst",
2955 [/* For disassembly only; pattern left blank */]>;
2957 // VBIT : Vector Bitwise Insert if True
2958 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
2959 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
2960 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
2961 N3RegFrm, IIC_VBINiD,
2962 "vbit", "$dst, $src2, $src3", "$src1 = $dst",
2963 [/* For disassembly only; pattern left blank */]>;
2964 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
2965 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
2966 N3RegFrm, IIC_VBINiQ,
2967 "vbit", "$dst, $src2, $src3", "$src1 = $dst",
2968 [/* For disassembly only; pattern left blank */]>;
2970 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
2971 // for equivalent operations with different register constraints; it just
2974 // Vector Absolute Differences.
2976 // VABD : Vector Absolute Difference
2977 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
2978 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2979 "vabd", "s", int_arm_neon_vabds, 1>;
2980 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
2981 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2982 "vabd", "u", int_arm_neon_vabdu, 1>;
2983 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
2984 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
2985 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
2986 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
2988 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
2989 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
2990 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
2991 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
2992 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
2994 // VABA : Vector Absolute Difference and Accumulate
2995 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
2996 "vaba", "s", int_arm_neon_vabds, add>;
2997 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
2998 "vaba", "u", int_arm_neon_vabdu, add>;
3000 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
3001 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
3002 "vabal", "s", int_arm_neon_vabds, zext, add>;
3003 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
3004 "vabal", "u", int_arm_neon_vabdu, zext, add>;
3006 // Vector Maximum and Minimum.
3008 // VMAX : Vector Maximum
3009 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
3010 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3011 "vmax", "s", int_arm_neon_vmaxs, 1>;
3012 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
3013 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3014 "vmax", "u", int_arm_neon_vmaxu, 1>;
3015 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
3017 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
3018 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
3020 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
3022 // VMIN : Vector Minimum
3023 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
3024 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3025 "vmin", "s", int_arm_neon_vmins, 1>;
3026 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
3027 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3028 "vmin", "u", int_arm_neon_vminu, 1>;
3029 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
3031 v2f32, v2f32, int_arm_neon_vmins, 1>;
3032 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
3034 v4f32, v4f32, int_arm_neon_vmins, 1>;
3036 // Vector Pairwise Operations.
3038 // VPADD : Vector Pairwise Add
3039 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3041 v8i8, v8i8, int_arm_neon_vpadd, 0>;
3042 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3044 v4i16, v4i16, int_arm_neon_vpadd, 0>;
3045 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3047 v2i32, v2i32, int_arm_neon_vpadd, 0>;
3048 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
3049 IIC_VBIND, "vpadd", "f32",
3050 v2f32, v2f32, int_arm_neon_vpadd, 0>;
3052 // VPADDL : Vector Pairwise Add Long
3053 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
3054 int_arm_neon_vpaddls>;
3055 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
3056 int_arm_neon_vpaddlu>;
3058 // VPADAL : Vector Pairwise Add and Accumulate Long
3059 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
3060 int_arm_neon_vpadals>;
3061 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
3062 int_arm_neon_vpadalu>;
3064 // VPMAX : Vector Pairwise Maximum
3065 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3066 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
3067 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3068 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
3069 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3070 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
3071 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3072 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
3073 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3074 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
3075 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3076 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
3077 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3078 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
3080 // VPMIN : Vector Pairwise Minimum
3081 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3082 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
3083 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3084 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
3085 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3086 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
3087 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3088 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
3089 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3090 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
3091 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3092 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
3093 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VSUBi4D, "vpmin",
3094 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
3096 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
3098 // VRECPE : Vector Reciprocal Estimate
3099 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
3100 IIC_VUNAD, "vrecpe", "u32",
3101 v2i32, v2i32, int_arm_neon_vrecpe>;
3102 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
3103 IIC_VUNAQ, "vrecpe", "u32",
3104 v4i32, v4i32, int_arm_neon_vrecpe>;
3105 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
3106 IIC_VUNAD, "vrecpe", "f32",
3107 v2f32, v2f32, int_arm_neon_vrecpe>;
3108 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
3109 IIC_VUNAQ, "vrecpe", "f32",
3110 v4f32, v4f32, int_arm_neon_vrecpe>;
3112 // VRECPS : Vector Reciprocal Step
3113 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
3114 IIC_VRECSD, "vrecps", "f32",
3115 v2f32, v2f32, int_arm_neon_vrecps, 1>;
3116 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
3117 IIC_VRECSQ, "vrecps", "f32",
3118 v4f32, v4f32, int_arm_neon_vrecps, 1>;
3120 // VRSQRTE : Vector Reciprocal Square Root Estimate
3121 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
3122 IIC_VUNAD, "vrsqrte", "u32",
3123 v2i32, v2i32, int_arm_neon_vrsqrte>;
3124 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
3125 IIC_VUNAQ, "vrsqrte", "u32",
3126 v4i32, v4i32, int_arm_neon_vrsqrte>;
3127 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
3128 IIC_VUNAD, "vrsqrte", "f32",
3129 v2f32, v2f32, int_arm_neon_vrsqrte>;
3130 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
3131 IIC_VUNAQ, "vrsqrte", "f32",
3132 v4f32, v4f32, int_arm_neon_vrsqrte>;
3134 // VRSQRTS : Vector Reciprocal Square Root Step
3135 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
3136 IIC_VRECSD, "vrsqrts", "f32",
3137 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
3138 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
3139 IIC_VRECSQ, "vrsqrts", "f32",
3140 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
3144 // VSHL : Vector Shift
3145 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, N3RegVShFrm,
3146 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
3147 "vshl", "s", int_arm_neon_vshifts, 0>;
3148 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, N3RegVShFrm,
3149 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
3150 "vshl", "u", int_arm_neon_vshiftu, 0>;
3151 // VSHL : Vector Shift Left (Immediate)
3152 defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl,
3154 // VSHR : Vector Shift Right (Immediate)
3155 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", NEONvshrs,
3157 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", NEONvshru,
3160 // VSHLL : Vector Shift Left Long
3161 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
3162 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
3164 // VSHLL : Vector Shift Left Long (with maximum shift count)
3165 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
3166 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
3167 ValueType OpTy, SDNode OpNode>
3168 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
3169 ResTy, OpTy, OpNode> {
3170 let Inst{21-16} = op21_16;
3172 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
3173 v8i16, v8i8, NEONvshlli>;
3174 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
3175 v4i32, v4i16, NEONvshlli>;
3176 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
3177 v2i64, v2i32, NEONvshlli>;
3179 // VSHRN : Vector Shift Right and Narrow
3180 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
3183 // VRSHL : Vector Rounding Shift
3184 defm VRSHLs : N3VInt_QHSD<0, 0, 0b0101, 0, N3RegVShFrm,
3185 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3186 "vrshl", "s", int_arm_neon_vrshifts, 0>;
3187 defm VRSHLu : N3VInt_QHSD<1, 0, 0b0101, 0, N3RegVShFrm,
3188 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3189 "vrshl", "u", int_arm_neon_vrshiftu, 0>;
3190 // VRSHR : Vector Rounding Shift Right
3191 defm VRSHRs : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs,
3193 defm VRSHRu : N2VSh_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", NEONvrshru,
3196 // VRSHRN : Vector Rounding Shift Right and Narrow
3197 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
3200 // VQSHL : Vector Saturating Shift
3201 defm VQSHLs : N3VInt_QHSD<0, 0, 0b0100, 1, N3RegVShFrm,
3202 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3203 "vqshl", "s", int_arm_neon_vqshifts, 0>;
3204 defm VQSHLu : N3VInt_QHSD<1, 0, 0b0100, 1, N3RegVShFrm,
3205 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3206 "vqshl", "u", int_arm_neon_vqshiftu, 0>;
3207 // VQSHL : Vector Saturating Shift Left (Immediate)
3208 defm VQSHLsi : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls,
3210 defm VQSHLui : N2VSh_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu,
3212 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
3213 defm VQSHLsu : N2VSh_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu,
3216 // VQSHRN : Vector Saturating Shift Right and Narrow
3217 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
3219 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
3222 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
3223 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
3226 // VQRSHL : Vector Saturating Rounding Shift
3227 defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, N3RegVShFrm,
3228 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3229 "vqrshl", "s", int_arm_neon_vqrshifts, 0>;
3230 defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, N3RegVShFrm,
3231 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3232 "vqrshl", "u", int_arm_neon_vqrshiftu, 0>;
3234 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
3235 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
3237 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
3240 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
3241 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
3244 // VSRA : Vector Shift Right and Accumulate
3245 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
3246 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
3247 // VRSRA : Vector Rounding Shift Right and Accumulate
3248 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
3249 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
3251 // VSLI : Vector Shift Left and Insert
3252 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli", NEONvsli, N2RegVShLFrm>;
3253 // VSRI : Vector Shift Right and Insert
3254 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri", NEONvsri, N2RegVShRFrm>;
3256 // Vector Absolute and Saturating Absolute.
3258 // VABS : Vector Absolute Value
3259 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
3260 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
3262 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
3263 IIC_VUNAD, "vabs", "f32",
3264 v2f32, v2f32, int_arm_neon_vabs>;
3265 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
3266 IIC_VUNAQ, "vabs", "f32",
3267 v4f32, v4f32, int_arm_neon_vabs>;
3269 // VQABS : Vector Saturating Absolute Value
3270 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
3271 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
3272 int_arm_neon_vqabs>;
3276 def vnegd : PatFrag<(ops node:$in),
3277 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
3278 def vnegq : PatFrag<(ops node:$in),
3279 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
3281 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
3282 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
3283 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
3284 [(set DPR:$dst, (Ty (vnegd DPR:$src)))]>;
3285 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
3286 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
3287 IIC_VSHLiQ, OpcodeStr, Dt, "$dst, $src", "",
3288 [(set QPR:$dst, (Ty (vnegq QPR:$src)))]>;
3290 // VNEG : Vector Negate (integer)
3291 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
3292 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
3293 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
3294 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
3295 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
3296 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
3298 // VNEG : Vector Negate (floating-point)
3299 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
3300 (outs DPR:$dst), (ins DPR:$src), IIC_VUNAD,
3301 "vneg", "f32", "$dst, $src", "",
3302 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
3303 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
3304 (outs QPR:$dst), (ins QPR:$src), IIC_VUNAQ,
3305 "vneg", "f32", "$dst, $src", "",
3306 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
3308 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
3309 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
3310 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
3311 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
3312 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
3313 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
3315 // VQNEG : Vector Saturating Negate
3316 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
3317 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
3318 int_arm_neon_vqneg>;
3320 // Vector Bit Counting Operations.
3322 // VCLS : Vector Count Leading Sign Bits
3323 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
3324 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
3326 // VCLZ : Vector Count Leading Zeros
3327 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
3328 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
3330 // VCNT : Vector Count One Bits
3331 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
3332 IIC_VCNTiD, "vcnt", "8",
3333 v8i8, v8i8, int_arm_neon_vcnt>;
3334 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
3335 IIC_VCNTiQ, "vcnt", "8",
3336 v16i8, v16i8, int_arm_neon_vcnt>;
3338 // Vector Swap -- for disassembly only.
3339 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
3340 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
3341 "vswp", "$dst, $src", "", []>;
3342 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
3343 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
3344 "vswp", "$dst, $src", "", []>;
3346 // Vector Move Operations.
3348 // VMOV : Vector Move (Register)
3350 let neverHasSideEffects = 1 in {
3351 def VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
3352 N3RegFrm, IIC_VMOV, "vmov", "$dst, $src", "", []>;
3353 def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
3354 N3RegFrm, IIC_VMOV, "vmov", "$dst, $src", "", []>;
3356 // Pseudo vector move instructions for QQ and QQQQ registers. This should
3357 // be expanded after register allocation is completed.
3358 def VMOVQQ : PseudoInst<(outs QQPR:$dst), (ins QQPR:$src),
3359 NoItinerary, "", []>;
3361 def VMOVQQQQ : PseudoInst<(outs QQQQPR:$dst), (ins QQQQPR:$src),
3362 NoItinerary, "", []>;
3363 } // neverHasSideEffects
3365 // VMOV : Vector Move (Immediate)
3367 let isReMaterializable = 1 in {
3368 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
3369 (ins nModImm:$SIMM), IIC_VMOVImm,
3370 "vmov", "i8", "$dst, $SIMM", "",
3371 [(set DPR:$dst, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
3372 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
3373 (ins nModImm:$SIMM), IIC_VMOVImm,
3374 "vmov", "i8", "$dst, $SIMM", "",
3375 [(set QPR:$dst, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
3377 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$dst),
3378 (ins nModImm:$SIMM), IIC_VMOVImm,
3379 "vmov", "i16", "$dst, $SIMM", "",
3380 [(set DPR:$dst, (v4i16 (NEONvmovImm timm:$SIMM)))]>;
3381 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$dst),
3382 (ins nModImm:$SIMM), IIC_VMOVImm,
3383 "vmov", "i16", "$dst, $SIMM", "",
3384 [(set QPR:$dst, (v8i16 (NEONvmovImm timm:$SIMM)))]>;
3386 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$dst),
3387 (ins nModImm:$SIMM), IIC_VMOVImm,
3388 "vmov", "i32", "$dst, $SIMM", "",
3389 [(set DPR:$dst, (v2i32 (NEONvmovImm timm:$SIMM)))]>;
3390 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$dst),
3391 (ins nModImm:$SIMM), IIC_VMOVImm,
3392 "vmov", "i32", "$dst, $SIMM", "",
3393 [(set QPR:$dst, (v4i32 (NEONvmovImm timm:$SIMM)))]>;
3395 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
3396 (ins nModImm:$SIMM), IIC_VMOVImm,
3397 "vmov", "i64", "$dst, $SIMM", "",
3398 [(set DPR:$dst, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
3399 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
3400 (ins nModImm:$SIMM), IIC_VMOVImm,
3401 "vmov", "i64", "$dst, $SIMM", "",
3402 [(set QPR:$dst, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
3403 } // isReMaterializable
3405 // VMOV : Vector Get Lane (move scalar to ARM core register)
3407 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
3408 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3409 IIC_VMOVSI, "vmov", "s8", "$dst, $src[$lane]",
3410 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
3412 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
3413 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3414 IIC_VMOVSI, "vmov", "s16", "$dst, $src[$lane]",
3415 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
3417 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
3418 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3419 IIC_VMOVSI, "vmov", "u8", "$dst, $src[$lane]",
3420 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
3422 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
3423 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3424 IIC_VMOVSI, "vmov", "u16", "$dst, $src[$lane]",
3425 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
3427 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
3428 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3429 IIC_VMOVSI, "vmov", "32", "$dst, $src[$lane]",
3430 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
3432 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
3433 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
3434 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
3435 (DSubReg_i8_reg imm:$lane))),
3436 (SubReg_i8_lane imm:$lane))>;
3437 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
3438 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
3439 (DSubReg_i16_reg imm:$lane))),
3440 (SubReg_i16_lane imm:$lane))>;
3441 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
3442 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
3443 (DSubReg_i8_reg imm:$lane))),
3444 (SubReg_i8_lane imm:$lane))>;
3445 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
3446 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
3447 (DSubReg_i16_reg imm:$lane))),
3448 (SubReg_i16_lane imm:$lane))>;
3449 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
3450 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
3451 (DSubReg_i32_reg imm:$lane))),
3452 (SubReg_i32_lane imm:$lane))>;
3453 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
3454 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
3455 (SSubReg_f32_reg imm:$src2))>;
3456 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
3457 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
3458 (SSubReg_f32_reg imm:$src2))>;
3459 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
3460 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
3461 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
3462 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
3465 // VMOV : Vector Set Lane (move ARM core register to scalar)
3467 let Constraints = "$src1 = $dst" in {
3468 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$dst),
3469 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
3470 IIC_VMOVISL, "vmov", "8", "$dst[$lane], $src2",
3471 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
3472 GPR:$src2, imm:$lane))]>;
3473 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$dst),
3474 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
3475 IIC_VMOVISL, "vmov", "16", "$dst[$lane], $src2",
3476 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
3477 GPR:$src2, imm:$lane))]>;
3478 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$dst),
3479 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
3480 IIC_VMOVISL, "vmov", "32", "$dst[$lane], $src2",
3481 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
3482 GPR:$src2, imm:$lane))]>;
3484 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
3485 (v16i8 (INSERT_SUBREG QPR:$src1,
3486 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
3487 (DSubReg_i8_reg imm:$lane))),
3488 GPR:$src2, (SubReg_i8_lane imm:$lane))),
3489 (DSubReg_i8_reg imm:$lane)))>;
3490 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
3491 (v8i16 (INSERT_SUBREG QPR:$src1,
3492 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
3493 (DSubReg_i16_reg imm:$lane))),
3494 GPR:$src2, (SubReg_i16_lane imm:$lane))),
3495 (DSubReg_i16_reg imm:$lane)))>;
3496 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
3497 (v4i32 (INSERT_SUBREG QPR:$src1,
3498 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
3499 (DSubReg_i32_reg imm:$lane))),
3500 GPR:$src2, (SubReg_i32_lane imm:$lane))),
3501 (DSubReg_i32_reg imm:$lane)))>;
3503 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
3504 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
3505 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
3506 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
3507 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
3508 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
3510 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
3511 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
3512 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
3513 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
3515 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
3516 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
3517 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
3518 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
3519 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
3520 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
3522 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
3523 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
3524 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
3525 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
3526 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
3527 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
3529 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
3530 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3531 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
3533 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
3534 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
3535 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
3537 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
3538 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3539 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
3542 // VDUP : Vector Duplicate (from ARM core register to all elements)
3544 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
3545 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
3546 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
3547 [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
3548 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
3549 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
3550 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
3551 [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
3553 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
3554 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
3555 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
3556 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
3557 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
3558 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
3560 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
3561 IIC_VMOVIS, "vdup", "32", "$dst, $src",
3562 [(set DPR:$dst, (v2f32 (NEONvdup
3563 (f32 (bitconvert GPR:$src)))))]>;
3564 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
3565 IIC_VMOVIS, "vdup", "32", "$dst, $src",
3566 [(set QPR:$dst, (v4f32 (NEONvdup
3567 (f32 (bitconvert GPR:$src)))))]>;
3569 // VDUP : Vector Duplicate Lane (from scalar to all elements)
3571 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
3573 : NVDupLane<op19_16, 0, (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3574 IIC_VMOVD, OpcodeStr, Dt, "$dst, $src[$lane]",
3575 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
3577 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
3578 ValueType ResTy, ValueType OpTy>
3579 : NVDupLane<op19_16, 1, (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3580 IIC_VMOVQ, OpcodeStr, Dt, "$dst, $src[$lane]",
3581 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src),
3584 // Inst{19-16} is partially specified depending on the element size.
3586 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8>;
3587 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16>;
3588 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32>;
3589 def VDUPLNfd : VDUPLND<{?,1,0,0}, "vdup", "32", v2f32>;
3590 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8>;
3591 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16>;
3592 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32>;
3593 def VDUPLNfq : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4f32, v2f32>;
3595 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
3596 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
3597 (DSubReg_i8_reg imm:$lane))),
3598 (SubReg_i8_lane imm:$lane)))>;
3599 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
3600 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
3601 (DSubReg_i16_reg imm:$lane))),
3602 (SubReg_i16_lane imm:$lane)))>;
3603 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
3604 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
3605 (DSubReg_i32_reg imm:$lane))),
3606 (SubReg_i32_lane imm:$lane)))>;
3607 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
3608 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
3609 (DSubReg_i32_reg imm:$lane))),
3610 (SubReg_i32_lane imm:$lane)))>;
3612 def VDUPfdf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 0, 0,
3613 (outs DPR:$dst), (ins SPR:$src),
3614 IIC_VMOVD, "vdup", "32", "$dst, ${src:lane}", "",
3615 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
3617 def VDUPfqf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 1, 0,
3618 (outs QPR:$dst), (ins SPR:$src),
3619 IIC_VMOVQ, "vdup", "32", "$dst, ${src:lane}", "",
3620 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
3622 // VMOVN : Vector Narrowing Move
3623 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
3624 "vmovn", "i", trunc>;
3625 // VQMOVN : Vector Saturating Narrowing Move
3626 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
3627 "vqmovn", "s", int_arm_neon_vqmovns>;
3628 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
3629 "vqmovn", "u", int_arm_neon_vqmovnu>;
3630 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
3631 "vqmovun", "s", int_arm_neon_vqmovnsu>;
3632 // VMOVL : Vector Lengthening Move
3633 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
3634 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
3636 // Vector Conversions.
3638 // VCVT : Vector Convert Between Floating-Point and Integers
3639 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3640 v2i32, v2f32, fp_to_sint>;
3641 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3642 v2i32, v2f32, fp_to_uint>;
3643 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3644 v2f32, v2i32, sint_to_fp>;
3645 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3646 v2f32, v2i32, uint_to_fp>;
3648 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3649 v4i32, v4f32, fp_to_sint>;
3650 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3651 v4i32, v4f32, fp_to_uint>;
3652 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3653 v4f32, v4i32, sint_to_fp>;
3654 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3655 v4f32, v4i32, uint_to_fp>;
3657 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
3658 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
3659 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
3660 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
3661 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
3662 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
3663 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
3664 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
3665 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
3667 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
3668 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
3669 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
3670 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
3671 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
3672 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
3673 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
3674 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
3678 // VREV64 : Vector Reverse elements within 64-bit doublewords
3680 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3681 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
3682 (ins DPR:$src), IIC_VMOVD,
3683 OpcodeStr, Dt, "$dst, $src", "",
3684 [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
3685 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3686 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
3687 (ins QPR:$src), IIC_VMOVQ,
3688 OpcodeStr, Dt, "$dst, $src", "",
3689 [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
3691 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
3692 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
3693 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
3694 def VREV64df : VREV64D<0b10, "vrev64", "32", v2f32>;
3696 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
3697 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
3698 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
3699 def VREV64qf : VREV64Q<0b10, "vrev64", "32", v4f32>;
3701 // VREV32 : Vector Reverse elements within 32-bit words
3703 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3704 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
3705 (ins DPR:$src), IIC_VMOVD,
3706 OpcodeStr, Dt, "$dst, $src", "",
3707 [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
3708 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3709 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
3710 (ins QPR:$src), IIC_VMOVQ,
3711 OpcodeStr, Dt, "$dst, $src", "",
3712 [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
3714 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
3715 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
3717 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
3718 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
3720 // VREV16 : Vector Reverse elements within 16-bit halfwords
3722 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3723 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
3724 (ins DPR:$src), IIC_VMOVD,
3725 OpcodeStr, Dt, "$dst, $src", "",
3726 [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
3727 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3728 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
3729 (ins QPR:$src), IIC_VMOVQ,
3730 OpcodeStr, Dt, "$dst, $src", "",
3731 [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
3733 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
3734 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
3736 // Other Vector Shuffles.
3738 // VEXT : Vector Extract
3740 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
3741 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$dst),
3742 (ins DPR:$lhs, DPR:$rhs, i32imm:$index), NVExtFrm,
3743 IIC_VEXTD, OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
3744 [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
3745 (Ty DPR:$rhs), imm:$index)))]>;
3747 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
3748 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$dst),
3749 (ins QPR:$lhs, QPR:$rhs, i32imm:$index), NVExtFrm,
3750 IIC_VEXTQ, OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
3751 [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
3752 (Ty QPR:$rhs), imm:$index)))]>;
3754 def VEXTd8 : VEXTd<"vext", "8", v8i8>;
3755 def VEXTd16 : VEXTd<"vext", "16", v4i16>;
3756 def VEXTd32 : VEXTd<"vext", "32", v2i32>;
3757 def VEXTdf : VEXTd<"vext", "32", v2f32>;
3759 def VEXTq8 : VEXTq<"vext", "8", v16i8>;
3760 def VEXTq16 : VEXTq<"vext", "16", v8i16>;
3761 def VEXTq32 : VEXTq<"vext", "32", v4i32>;
3762 def VEXTqf : VEXTq<"vext", "32", v4f32>;
3764 // VTRN : Vector Transpose
3766 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
3767 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
3768 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
3770 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
3771 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
3772 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
3774 // VUZP : Vector Unzip (Deinterleave)
3776 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
3777 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
3778 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
3780 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
3781 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
3782 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
3784 // VZIP : Vector Zip (Interleave)
3786 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
3787 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
3788 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
3790 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
3791 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
3792 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
3794 // Vector Table Lookup and Table Extension.
3796 // VTBL : Vector Table Lookup
3798 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
3799 (ins DPR:$tbl1, DPR:$src), NVTBLFrm, IIC_VTB1,
3800 "vtbl", "8", "$dst, \\{$tbl1\\}, $src", "",
3801 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
3802 let hasExtraSrcRegAllocReq = 1 in {
3804 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
3805 (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), NVTBLFrm, IIC_VTB2,
3806 "vtbl", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "", []>;
3808 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
3809 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), NVTBLFrm, IIC_VTB3,
3810 "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src", "", []>;
3812 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
3813 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src),
3815 "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src", "", []>;
3816 } // hasExtraSrcRegAllocReq = 1
3819 : PseudoNeonI<(outs DPR:$dst), (ins QPR:$tbl, DPR:$src), IIC_VTB2, "">;
3821 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "">;
3823 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "">;
3825 // VTBX : Vector Table Extension
3827 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
3828 (ins DPR:$orig, DPR:$tbl1, DPR:$src), NVTBLFrm, IIC_VTBX1,
3829 "vtbx", "8", "$dst, \\{$tbl1\\}, $src", "$orig = $dst",
3830 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
3831 DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
3832 let hasExtraSrcRegAllocReq = 1 in {
3834 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
3835 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), NVTBLFrm, IIC_VTBX2,
3836 "vtbx", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "$orig = $dst", []>;
3838 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
3839 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src),
3840 NVTBLFrm, IIC_VTBX3,
3841 "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src",
3842 "$orig = $dst", []>;
3844 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
3845 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), NVTBLFrm, IIC_VTBX4,
3846 "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src",
3847 "$orig = $dst", []>;
3848 } // hasExtraSrcRegAllocReq = 1
3851 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QPR:$tbl, DPR:$src),
3852 IIC_VTBX2, "$orig = $dst">;
3854 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
3855 IIC_VTBX3, "$orig = $dst">;
3857 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
3858 IIC_VTBX4, "$orig = $dst">;
3860 //===----------------------------------------------------------------------===//
3861 // NEON instructions for single-precision FP math
3862 //===----------------------------------------------------------------------===//
3864 class N2VSPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
3865 : NEONFPPat<(ResTy (OpNode SPR:$a)),
3866 (EXTRACT_SUBREG (OpTy (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)),
3870 class N3VSPat<SDNode OpNode, NeonI Inst>
3871 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
3872 (EXTRACT_SUBREG (v2f32
3873 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3875 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3879 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
3880 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
3881 (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3883 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3885 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3889 // These need separate instructions because they must use DPR_VFP2 register
3890 // class which have SPR sub-registers.
3892 // Vector Add Operations used for single-precision FP
3893 let neverHasSideEffects = 1 in
3894 def VADDfd_sfp : N3VS<0,0,0b00,0b1101,0, "vadd", "f32", v2f32, v2f32, fadd, 1>;
3895 def : N3VSPat<fadd, VADDfd_sfp>;
3897 // Vector Sub Operations used for single-precision FP
3898 let neverHasSideEffects = 1 in
3899 def VSUBfd_sfp : N3VS<0,0,0b10,0b1101,0, "vsub", "f32", v2f32, v2f32, fsub, 0>;
3900 def : N3VSPat<fsub, VSUBfd_sfp>;
3902 // Vector Multiply Operations used for single-precision FP
3903 let neverHasSideEffects = 1 in
3904 def VMULfd_sfp : N3VS<1,0,0b00,0b1101,1, "vmul", "f32", v2f32, v2f32, fmul, 1>;
3905 def : N3VSPat<fmul, VMULfd_sfp>;
3907 // Vector Multiply-Accumulate/Subtract used for single-precision FP
3908 // vml[as].f32 can cause 4-8 cycle stalls in following ASIMD instructions, so
3909 // we want to avoid them for now. e.g., alternating vmla/vadd instructions.
3911 //let neverHasSideEffects = 1 in
3912 //def VMLAfd_sfp : N3VSMulOp<0,0,0b00,0b1101,1, IIC_VMACD, "vmla", "f32",
3913 // v2f32, fmul, fadd>;
3914 //def : N3VSMulOpPat<fmul, fadd, VMLAfd_sfp>;
3916 //let neverHasSideEffects = 1 in
3917 //def VMLSfd_sfp : N3VSMulOp<0,0,0b10,0b1101,1, IIC_VMACD, "vmls", "f32",
3918 // v2f32, fmul, fsub>;
3919 //def : N3VSMulOpPat<fmul, fsub, VMLSfd_sfp>;
3921 // Vector Absolute used for single-precision FP
3922 let neverHasSideEffects = 1 in
3923 def VABSfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01110, 0, 0,
3924 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
3925 "vabs", "f32", "$dst, $src", "", []>;
3926 def : N2VSPat<fabs, f32, v2f32, VABSfd_sfp>;
3928 // Vector Negate used for single-precision FP
3929 let neverHasSideEffects = 1 in
3930 def VNEGfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
3931 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
3932 "vneg", "f32", "$dst, $src", "", []>;
3933 def : N2VSPat<fneg, f32, v2f32, VNEGfd_sfp>;
3935 // Vector Maximum used for single-precision FP
3936 let neverHasSideEffects = 1 in
3937 def VMAXfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
3938 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm, IIC_VBIND,
3939 "vmax", "f32", "$dst, $src1, $src2", "", []>;
3940 def : N3VSPat<NEONfmax, VMAXfd_sfp>;
3942 // Vector Minimum used for single-precision FP
3943 let neverHasSideEffects = 1 in
3944 def VMINfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
3945 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm, IIC_VBIND,
3946 "vmin", "f32", "$dst, $src1, $src2", "", []>;
3947 def : N3VSPat<NEONfmin, VMINfd_sfp>;
3949 // Vector Convert between single-precision FP and integer
3950 let neverHasSideEffects = 1 in
3951 def VCVTf2sd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3952 v2i32, v2f32, fp_to_sint>;
3953 def : N2VSPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
3955 let neverHasSideEffects = 1 in
3956 def VCVTf2ud_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3957 v2i32, v2f32, fp_to_uint>;
3958 def : N2VSPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
3960 let neverHasSideEffects = 1 in
3961 def VCVTs2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3962 v2f32, v2i32, sint_to_fp>;
3963 def : N2VSPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
3965 let neverHasSideEffects = 1 in
3966 def VCVTu2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3967 v2f32, v2i32, uint_to_fp>;
3968 def : N2VSPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
3970 //===----------------------------------------------------------------------===//
3971 // Non-Instruction Patterns
3972 //===----------------------------------------------------------------------===//
3975 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
3976 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
3977 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
3978 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
3979 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
3980 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
3981 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
3982 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
3983 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
3984 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
3985 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
3986 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
3987 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
3988 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
3989 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
3990 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
3991 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
3992 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
3993 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
3994 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
3995 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
3996 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
3997 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
3998 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
3999 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
4000 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
4001 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
4002 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
4003 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
4004 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
4006 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
4007 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
4008 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
4009 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
4010 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
4011 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
4012 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
4013 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
4014 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
4015 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
4016 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
4017 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
4018 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
4019 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
4020 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
4021 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
4022 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
4023 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
4024 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
4025 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
4026 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
4027 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
4028 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
4029 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
4030 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
4031 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
4032 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
4033 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
4034 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
4035 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;