1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
70 // VDUPLANE can produce a quad-register result from a double-register source,
71 // so the result is not constrained to match the source.
72 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
73 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
76 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
77 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
78 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
80 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
81 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
82 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
83 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
85 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
86 SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>]>;
87 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
88 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
89 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
91 //===----------------------------------------------------------------------===//
92 // NEON operand definitions
93 //===----------------------------------------------------------------------===//
95 // addrmode_neonldstm := reg
97 /* TODO: Take advantage of vldm.
98 def addrmode_neonldstm : Operand<i32>,
99 ComplexPattern<i32, 2, "SelectAddrModeNeonLdStM", []> {
100 let PrintMethod = "printAddrNeonLdStMOperand";
101 let MIOperandInfo = (ops GPR, i32imm);
105 //===----------------------------------------------------------------------===//
106 // NEON load / store instructions
107 //===----------------------------------------------------------------------===//
109 /* TODO: Take advantage of vldm.
110 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
111 def VLDMD : NI<(outs),
112 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
114 "vldm${addr:submode} ${addr:base}, $dst1",
116 let Inst{27-25} = 0b110;
118 let Inst{11-9} = 0b101;
121 def VLDMS : NI<(outs),
122 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
124 "vldm${addr:submode} ${addr:base}, $dst1",
126 let Inst{27-25} = 0b110;
128 let Inst{11-9} = 0b101;
133 // Use vldmia to load a Q register as a D register pair.
134 def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr),
136 "vldmia $addr, ${dst:dregpair}",
137 [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]> {
138 let Inst{27-25} = 0b110;
139 let Inst{24} = 0; // P bit
140 let Inst{23} = 1; // U bit
142 let Inst{11-9} = 0b101;
145 // Use vstmia to store a Q register as a D register pair.
146 def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr),
148 "vstmia $addr, ${src:dregpair}",
149 [(store (v2f64 QPR:$src), addrmode4:$addr)]> {
150 let Inst{27-25} = 0b110;
151 let Inst{24} = 0; // P bit
152 let Inst{23} = 1; // U bit
154 let Inst{11-9} = 0b101;
157 // VLD1 : Vector Load (multiple single elements)
158 class VLD1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
159 : NLdSt<(outs DPR:$dst), (ins addrmode6:$addr), IIC_VLD1,
160 !strconcat(OpcodeStr, "\t\\{$dst\\}, $addr"), "",
161 [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
162 class VLD1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
163 : NLdSt<(outs QPR:$dst), (ins addrmode6:$addr), IIC_VLD1,
164 !strconcat(OpcodeStr, "\t${dst:dregpair}, $addr"), "",
165 [(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
167 def VLD1d8 : VLD1D<"vld1.8", v8i8, int_arm_neon_vld1>;
168 def VLD1d16 : VLD1D<"vld1.16", v4i16, int_arm_neon_vld1>;
169 def VLD1d32 : VLD1D<"vld1.32", v2i32, int_arm_neon_vld1>;
170 def VLD1df : VLD1D<"vld1.32", v2f32, int_arm_neon_vld1>;
171 def VLD1d64 : VLD1D<"vld1.64", v1i64, int_arm_neon_vld1>;
173 def VLD1q8 : VLD1Q<"vld1.8", v16i8, int_arm_neon_vld1>;
174 def VLD1q16 : VLD1Q<"vld1.16", v8i16, int_arm_neon_vld1>;
175 def VLD1q32 : VLD1Q<"vld1.32", v4i32, int_arm_neon_vld1>;
176 def VLD1qf : VLD1Q<"vld1.32", v4f32, int_arm_neon_vld1>;
177 def VLD1q64 : VLD1Q<"vld1.64", v2i64, int_arm_neon_vld1>;
179 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
181 // VLD2 : Vector Load (multiple 2-element structures)
182 class VLD2D<string OpcodeStr>
183 : NLdSt<(outs DPR:$dst1, DPR:$dst2), (ins addrmode6:$addr), IIC_VLD2,
184 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2\\}, $addr"), "", []>;
186 def VLD2d8 : VLD2D<"vld2.8">;
187 def VLD2d16 : VLD2D<"vld2.16">;
188 def VLD2d32 : VLD2D<"vld2.32">;
190 // VLD3 : Vector Load (multiple 3-element structures)
191 class VLD3D<string OpcodeStr>
192 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3), (ins addrmode6:$addr),
194 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"), "", []>;
196 def VLD3d8 : VLD3D<"vld3.8">;
197 def VLD3d16 : VLD3D<"vld3.16">;
198 def VLD3d32 : VLD3D<"vld3.32">;
200 // VLD4 : Vector Load (multiple 4-element structures)
201 class VLD4D<string OpcodeStr>
202 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
203 (ins addrmode6:$addr), IIC_VLD4,
204 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"),
207 def VLD4d8 : VLD4D<"vld4.8">;
208 def VLD4d16 : VLD4D<"vld4.16">;
209 def VLD4d32 : VLD4D<"vld4.32">;
211 // VLD2LN : Vector Load (single 2-element structure to one lane)
212 class VLD2LND<string OpcodeStr>
213 : NLdSt<(outs DPR:$dst1, DPR:$dst2),
214 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
216 !strconcat(OpcodeStr, "\t\\{$dst1[$lane],$dst2[$lane]\\}, $addr"),
217 "$src1 = $dst1, $src2 = $dst2", []>;
219 def VLD2LNd8 : VLD2LND<"vld2.8">;
220 def VLD2LNd16 : VLD2LND<"vld2.16">;
221 def VLD2LNd32 : VLD2LND<"vld2.32">;
223 // VLD3LN : Vector Load (single 3-element structure to one lane)
224 class VLD3LND<string OpcodeStr>
225 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
226 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
227 nohash_imm:$lane), IIC_VLD3,
228 !strconcat(OpcodeStr,
229 "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane]\\}, $addr"),
230 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
232 def VLD3LNd8 : VLD3LND<"vld3.8">;
233 def VLD3LNd16 : VLD3LND<"vld3.16">;
234 def VLD3LNd32 : VLD3LND<"vld3.32">;
236 // VLD4LN : Vector Load (single 4-element structure to one lane)
237 class VLD4LND<string OpcodeStr>
238 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
239 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
240 nohash_imm:$lane), IIC_VLD4,
241 !strconcat(OpcodeStr,
242 "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane],$dst4[$lane]\\}, $addr"),
243 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
245 def VLD4LNd8 : VLD4LND<"vld4.8">;
246 def VLD4LNd16 : VLD4LND<"vld4.16">;
247 def VLD4LNd32 : VLD4LND<"vld4.32">;
248 } // mayLoad = 1, hasExtraDefRegAllocReq = 1
250 // VST1 : Vector Store (multiple single elements)
251 class VST1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
252 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src), IIC_VST,
253 !strconcat(OpcodeStr, "\t\\{$src\\}, $addr"), "",
254 [(IntOp addrmode6:$addr, (Ty DPR:$src))]>;
255 class VST1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
256 : NLdSt<(outs), (ins addrmode6:$addr, QPR:$src), IIC_VST,
257 !strconcat(OpcodeStr, "\t${src:dregpair}, $addr"), "",
258 [(IntOp addrmode6:$addr, (Ty QPR:$src))]>;
260 let hasExtraSrcRegAllocReq = 1 in {
261 def VST1d8 : VST1D<"vst1.8", v8i8, int_arm_neon_vst1>;
262 def VST1d16 : VST1D<"vst1.16", v4i16, int_arm_neon_vst1>;
263 def VST1d32 : VST1D<"vst1.32", v2i32, int_arm_neon_vst1>;
264 def VST1df : VST1D<"vst1.32", v2f32, int_arm_neon_vst1>;
265 def VST1d64 : VST1D<"vst1.64", v1i64, int_arm_neon_vst1>;
267 def VST1q8 : VST1Q<"vst1.8", v16i8, int_arm_neon_vst1>;
268 def VST1q16 : VST1Q<"vst1.16", v8i16, int_arm_neon_vst1>;
269 def VST1q32 : VST1Q<"vst1.32", v4i32, int_arm_neon_vst1>;
270 def VST1qf : VST1Q<"vst1.32", v4f32, int_arm_neon_vst1>;
271 def VST1q64 : VST1Q<"vst1.64", v2i64, int_arm_neon_vst1>;
272 } // hasExtraSrcRegAllocReq
274 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
276 // VST2 : Vector Store (multiple 2-element structures)
277 class VST2D<string OpcodeStr>
278 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
279 !strconcat(OpcodeStr, "\t\\{$src1,$src2\\}, $addr"), "", []>;
281 def VST2d8 : VST2D<"vst2.8">;
282 def VST2d16 : VST2D<"vst2.16">;
283 def VST2d32 : VST2D<"vst2.32">;
285 // VST3 : Vector Store (multiple 3-element structures)
286 class VST3D<string OpcodeStr>
287 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
289 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"), "", []>;
291 def VST3d8 : VST3D<"vst3.8">;
292 def VST3d16 : VST3D<"vst3.16">;
293 def VST3d32 : VST3D<"vst3.32">;
295 // VST4 : Vector Store (multiple 4-element structures)
296 class VST4D<string OpcodeStr>
297 : NLdSt<(outs), (ins addrmode6:$addr,
298 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST,
299 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"),
302 def VST4d8 : VST4D<"vst4.8">;
303 def VST4d16 : VST4D<"vst4.16">;
304 def VST4d32 : VST4D<"vst4.32">;
306 // VST2LN : Vector Store (single 2-element structure from one lane)
307 class VST2LND<string OpcodeStr>
308 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
310 !strconcat(OpcodeStr, "\t\\{$src1[$lane],$src2[$lane]\\}, $addr"),
313 def VST2LNd8 : VST2LND<"vst2.8">;
314 def VST2LNd16 : VST2LND<"vst2.16">;
315 def VST2LNd32 : VST2LND<"vst2.32">;
317 // VST3LN : Vector Store (single 3-element structure from one lane)
318 class VST3LND<string OpcodeStr>
319 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
320 nohash_imm:$lane), IIC_VST,
321 !strconcat(OpcodeStr,
322 "\t\\{$src1[$lane],$src2[$lane],$src3[$lane]\\}, $addr"), "", []>;
324 def VST3LNd8 : VST3LND<"vst3.8">;
325 def VST3LNd16 : VST3LND<"vst3.16">;
326 def VST3LNd32 : VST3LND<"vst3.32">;
328 // VST4LN : Vector Store (single 4-element structure from one lane)
329 class VST4LND<string OpcodeStr>
330 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
331 DPR:$src4, nohash_imm:$lane), IIC_VST,
332 !strconcat(OpcodeStr,
333 "\t\\{$src1[$lane],$src2[$lane],$src3[$lane],$src4[$lane]\\}, $addr"),
336 def VST4LNd8 : VST4LND<"vst4.8">;
337 def VST4LNd16 : VST4LND<"vst4.16">;
338 def VST4LNd32 : VST4LND<"vst4.32">;
339 } // mayStore = 1, hasExtraSrcRegAllocReq = 1
342 //===----------------------------------------------------------------------===//
343 // NEON pattern fragments
344 //===----------------------------------------------------------------------===//
346 // Extract D sub-registers of Q registers.
347 // (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
348 def DSubReg_i8_reg : SDNodeXForm<imm, [{
349 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
351 def DSubReg_i16_reg : SDNodeXForm<imm, [{
352 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
354 def DSubReg_i32_reg : SDNodeXForm<imm, [{
355 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
357 def DSubReg_f64_reg : SDNodeXForm<imm, [{
358 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
360 def DSubReg_f64_other_reg : SDNodeXForm<imm, [{
361 return CurDAG->getTargetConstant(5 + (1 - N->getZExtValue()), MVT::i32);
364 // Extract S sub-registers of Q/D registers.
365 // (arm_ssubreg_0 is 1; arm_ssubreg_1 is 2; etc.)
366 def SSubReg_f32_reg : SDNodeXForm<imm, [{
367 return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32);
370 // Translate lane numbers from Q registers to D subregs.
371 def SubReg_i8_lane : SDNodeXForm<imm, [{
372 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
374 def SubReg_i16_lane : SDNodeXForm<imm, [{
375 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
377 def SubReg_i32_lane : SDNodeXForm<imm, [{
378 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
381 //===----------------------------------------------------------------------===//
382 // Instruction Classes
383 //===----------------------------------------------------------------------===//
385 // Basic 2-register operations, both double- and quad-register.
386 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
387 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
388 ValueType ResTy, ValueType OpTy, SDNode OpNode>
389 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
390 (ins DPR:$src), IIC_VUNAD, !strconcat(OpcodeStr, "\t$dst, $src"), "",
391 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
392 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
393 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
394 ValueType ResTy, ValueType OpTy, SDNode OpNode>
395 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
396 (ins QPR:$src), IIC_VUNAQ, !strconcat(OpcodeStr, "\t$dst, $src"), "",
397 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
399 // Basic 2-register operations, scalar single-precision.
400 class N2VDs<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
401 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
402 ValueType ResTy, ValueType OpTy, SDNode OpNode>
403 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
404 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
405 IIC_VUNAD, !strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
407 class N2VDsPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
408 : NEONFPPat<(ResTy (OpNode SPR:$a)),
410 (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
413 // Basic 2-register intrinsics, both double- and quad-register.
414 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
415 bits<2> op17_16, bits<5> op11_7, bit op4,
416 InstrItinClass itin, string OpcodeStr,
417 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
418 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
419 (ins DPR:$src), itin, !strconcat(OpcodeStr, "\t$dst, $src"), "",
420 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
421 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
422 bits<2> op17_16, bits<5> op11_7, bit op4,
423 InstrItinClass itin, string OpcodeStr,
424 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
425 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
426 (ins QPR:$src), itin, !strconcat(OpcodeStr, "\t$dst, $src"), "",
427 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
429 // Basic 2-register intrinsics, scalar single-precision
430 class N2VDInts<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
431 bits<2> op17_16, bits<5> op11_7, bit op4,
432 InstrItinClass itin, string OpcodeStr,
433 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
434 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
435 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), itin,
436 !strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
438 class N2VDIntsPat<SDNode OpNode, NeonI Inst>
439 : NEONFPPat<(f32 (OpNode SPR:$a)),
441 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
444 // Narrow 2-register intrinsics.
445 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
446 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
447 InstrItinClass itin, string OpcodeStr,
448 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
449 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
450 (ins QPR:$src), itin, !strconcat(OpcodeStr, "\t$dst, $src"), "",
451 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
453 // Long 2-register intrinsics. (This is currently only used for VMOVL and is
454 // derived from N2VImm instead of N2V because of the way the size is encoded.)
455 class N2VLInt<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
456 bit op6, bit op4, InstrItinClass itin, string OpcodeStr,
457 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
458 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4, (outs QPR:$dst),
459 (ins DPR:$src), itin, !strconcat(OpcodeStr, "\t$dst, $src"), "",
460 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
462 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
463 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr>
464 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
465 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
466 !strconcat(OpcodeStr, "\t$dst1, $dst2"),
467 "$src1 = $dst1, $src2 = $dst2", []>;
468 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
469 InstrItinClass itin, string OpcodeStr>
470 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
471 (ins QPR:$src1, QPR:$src2), itin,
472 !strconcat(OpcodeStr, "\t$dst1, $dst2"),
473 "$src1 = $dst1, $src2 = $dst2", []>;
475 // Basic 3-register operations, both double- and quad-register.
476 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
477 InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy,
478 SDNode OpNode, bit Commutable>
479 : N3V<op24, op23, op21_20, op11_8, 0, op4,
480 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
481 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
482 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
483 let isCommutable = Commutable;
485 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
486 InstrItinClass itin, string OpcodeStr, ValueType Ty, SDNode ShOp>
487 : N3V<0, 1, op21_20, op11_8, 1, 0,
488 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
489 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
491 (Ty (ShOp (Ty DPR:$src1),
492 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
494 let isCommutable = 0;
496 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
497 string OpcodeStr, ValueType Ty, SDNode ShOp>
498 : N3V<0, 1, op21_20, op11_8, 1, 0,
499 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
501 !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
503 (Ty (ShOp (Ty DPR:$src1),
504 (Ty (NEONvduplane (Ty DPR_8:$src2),
506 let isCommutable = 0;
509 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
510 InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy,
511 SDNode OpNode, bit Commutable>
512 : N3V<op24, op23, op21_20, op11_8, 1, op4,
513 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
514 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
515 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
516 let isCommutable = Commutable;
518 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
519 InstrItinClass itin, string OpcodeStr,
520 ValueType ResTy, ValueType OpTy, SDNode ShOp>
521 : N3V<1, 1, op21_20, op11_8, 1, 0,
522 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
523 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
524 [(set (ResTy QPR:$dst),
525 (ResTy (ShOp (ResTy QPR:$src1),
526 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
528 let isCommutable = 0;
530 class N3VQSL16<bits<2> op21_20, bits<4> op11_8,
531 string OpcodeStr, ValueType ResTy, ValueType OpTy, SDNode ShOp>
532 : N3V<1, 1, op21_20, op11_8, 1, 0,
533 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
535 !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
536 [(set (ResTy QPR:$dst),
537 (ResTy (ShOp (ResTy QPR:$src1),
538 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
540 let isCommutable = 0;
543 // Basic 3-register operations, scalar single-precision
544 class N3VDs<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
545 string OpcodeStr, ValueType ResTy, ValueType OpTy,
546 SDNode OpNode, bit Commutable>
547 : N3V<op24, op23, op21_20, op11_8, 0, op4,
548 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), IIC_VBIND,
549 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", []> {
550 let isCommutable = Commutable;
552 class N3VDsPat<SDNode OpNode, NeonI Inst>
553 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
555 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
556 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
559 // Basic 3-register intrinsics, both double- and quad-register.
560 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
561 InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy,
562 Intrinsic IntOp, bit Commutable>
563 : N3V<op24, op23, op21_20, op11_8, 0, op4,
564 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
565 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
566 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
567 let isCommutable = Commutable;
569 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
570 string OpcodeStr, ValueType Ty, Intrinsic IntOp>
571 : N3V<0, 1, op21_20, op11_8, 1, 0,
572 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
573 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
575 (Ty (IntOp (Ty DPR:$src1),
576 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
578 let isCommutable = 0;
580 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
581 string OpcodeStr, ValueType Ty, Intrinsic IntOp>
582 : N3V<0, 1, op21_20, op11_8, 1, 0,
583 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
584 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
586 (Ty (IntOp (Ty DPR:$src1),
587 (Ty (NEONvduplane (Ty DPR_8:$src2),
589 let isCommutable = 0;
592 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
593 InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy,
594 Intrinsic IntOp, bit Commutable>
595 : N3V<op24, op23, op21_20, op11_8, 1, op4,
596 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
597 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
598 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
599 let isCommutable = Commutable;
601 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
602 string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
603 : N3V<1, 1, op21_20, op11_8, 1, 0,
604 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
605 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
606 [(set (ResTy QPR:$dst),
607 (ResTy (IntOp (ResTy QPR:$src1),
608 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
610 let isCommutable = 0;
612 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
613 string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
614 : N3V<1, 1, op21_20, op11_8, 1, 0,
615 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
616 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
617 [(set (ResTy QPR:$dst),
618 (ResTy (IntOp (ResTy QPR:$src1),
619 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
621 let isCommutable = 0;
624 // Multiply-Add/Sub operations, both double- and quad-register.
625 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
626 InstrItinClass itin, string OpcodeStr,
627 ValueType Ty, SDNode MulOp, SDNode OpNode>
628 : N3V<op24, op23, op21_20, op11_8, 0, op4,
629 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin,
630 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
631 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
632 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
633 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
634 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode ShOp>
635 : N3V<0, 1, op21_20, op11_8, 1, 0,
637 (ins DPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
638 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
640 (Ty (ShOp (Ty DPR:$src1),
641 (Ty (MulOp DPR:$src2,
642 (Ty (NEONvduplane (Ty DPR_VFP2:$src3),
644 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
645 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode ShOp>
646 : N3V<0, 1, op21_20, op11_8, 1, 0,
648 (ins DPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
649 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
651 (Ty (ShOp (Ty DPR:$src1),
652 (Ty (MulOp DPR:$src2,
653 (Ty (NEONvduplane (Ty DPR_8:$src3),
656 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
657 InstrItinClass itin, string OpcodeStr, ValueType Ty,
658 SDNode MulOp, SDNode OpNode>
659 : N3V<op24, op23, op21_20, op11_8, 1, op4,
660 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin,
661 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
662 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
663 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
664 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
665 string OpcodeStr, ValueType ResTy, ValueType OpTy,
666 SDNode MulOp, SDNode ShOp>
667 : N3V<1, 1, op21_20, op11_8, 1, 0,
669 (ins QPR:$src1, QPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
670 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
671 [(set (ResTy QPR:$dst),
672 (ResTy (ShOp (ResTy QPR:$src1),
673 (ResTy (MulOp QPR:$src2,
674 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src3),
676 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
677 string OpcodeStr, ValueType ResTy, ValueType OpTy,
678 SDNode MulOp, SDNode ShOp>
679 : N3V<1, 1, op21_20, op11_8, 1, 0,
681 (ins QPR:$src1, QPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
682 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
683 [(set (ResTy QPR:$dst),
684 (ResTy (ShOp (ResTy QPR:$src1),
685 (ResTy (MulOp QPR:$src2,
686 (ResTy (NEONvduplane (OpTy DPR_8:$src3),
689 // Multiply-Add/Sub operations, scalar single-precision
690 class N3VDMulOps<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
691 InstrItinClass itin, string OpcodeStr,
692 ValueType Ty, SDNode MulOp, SDNode OpNode>
693 : N3V<op24, op23, op21_20, op11_8, 0, op4,
694 (outs DPR_VFP2:$dst),
695 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), itin,
696 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", []>;
698 class N3VDMulOpsPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
699 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
701 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$acc, arm_ssubreg_0),
702 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
703 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
706 // Neon 3-argument intrinsics, both double- and quad-register.
707 // The destination register is also used as the first source operand register.
708 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
709 InstrItinClass itin, string OpcodeStr,
710 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
711 : N3V<op24, op23, op21_20, op11_8, 0, op4,
712 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin,
713 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
714 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
715 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
716 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
717 InstrItinClass itin, string OpcodeStr,
718 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
719 : N3V<op24, op23, op21_20, op11_8, 1, op4,
720 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin,
721 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
722 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
723 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
725 // Neon Long 3-argument intrinsic. The destination register is
726 // a quad-register and is also used as the first source operand register.
727 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
728 InstrItinClass itin, string OpcodeStr,
729 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
730 : N3V<op24, op23, op21_20, op11_8, 0, op4,
731 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), itin,
732 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
734 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
735 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
736 string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
737 : N3V<op24, 1, op21_20, op11_8, 1, 0,
739 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
740 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
741 [(set (ResTy QPR:$dst),
742 (ResTy (IntOp (ResTy QPR:$src1),
744 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src3),
746 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
747 string OpcodeStr, ValueType ResTy, ValueType OpTy,
749 : N3V<op24, 1, op21_20, op11_8, 1, 0,
751 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
752 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
753 [(set (ResTy QPR:$dst),
754 (ResTy (IntOp (ResTy QPR:$src1),
756 (OpTy (NEONvduplane (OpTy DPR_8:$src3),
760 // Narrowing 3-register intrinsics.
761 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
762 string OpcodeStr, ValueType TyD, ValueType TyQ,
763 Intrinsic IntOp, bit Commutable>
764 : N3V<op24, op23, op21_20, op11_8, 0, op4,
765 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VBINi4D,
766 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
767 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
768 let isCommutable = Commutable;
771 // Long 3-register intrinsics.
772 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
773 InstrItinClass itin, string OpcodeStr, ValueType TyQ, ValueType TyD,
774 Intrinsic IntOp, bit Commutable>
775 : N3V<op24, op23, op21_20, op11_8, 0, op4,
776 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
777 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
778 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
779 let isCommutable = Commutable;
781 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
782 string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
783 : N3V<op24, 1, op21_20, op11_8, 1, 0,
784 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
785 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
786 [(set (ResTy QPR:$dst),
787 (ResTy (IntOp (OpTy DPR:$src1),
788 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src2),
790 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
791 string OpcodeStr, ValueType ResTy, ValueType OpTy,
793 : N3V<op24, 1, op21_20, op11_8, 1, 0,
794 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
795 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
796 [(set (ResTy QPR:$dst),
797 (ResTy (IntOp (OpTy DPR:$src1),
798 (OpTy (NEONvduplane (OpTy DPR_8:$src2),
801 // Wide 3-register intrinsics.
802 class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
803 string OpcodeStr, ValueType TyQ, ValueType TyD,
804 Intrinsic IntOp, bit Commutable>
805 : N3V<op24, op23, op21_20, op11_8, 0, op4,
806 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), IIC_VSUBiD,
807 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
808 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
809 let isCommutable = Commutable;
812 // Pairwise long 2-register intrinsics, both double- and quad-register.
813 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
814 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
815 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
816 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
817 (ins DPR:$src), IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "",
818 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
819 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
820 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
821 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
822 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
823 (ins QPR:$src), IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "",
824 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
826 // Pairwise long 2-register accumulate intrinsics,
827 // both double- and quad-register.
828 // The destination register is also used as the first source operand register.
829 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
830 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
831 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
832 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
833 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), IIC_VPALiD,
834 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
835 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
836 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
837 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
838 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
839 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
840 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VPALiQ,
841 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
842 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
844 // Shift by immediate,
845 // both double- and quad-register.
846 class N2VDSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
847 bit op4, InstrItinClass itin, string OpcodeStr,
848 ValueType Ty, SDNode OpNode>
849 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
850 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), itin,
851 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
852 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
853 class N2VQSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
854 bit op4, InstrItinClass itin, string OpcodeStr,
855 ValueType Ty, SDNode OpNode>
856 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
857 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin,
858 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
859 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
861 // Long shift by immediate.
862 class N2VLSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
863 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
864 ValueType OpTy, SDNode OpNode>
865 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
866 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VSHLiD,
867 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
868 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
869 (i32 imm:$SIMM))))]>;
871 // Narrow shift by immediate.
872 class N2VNSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
873 bit op6, bit op4, InstrItinClass itin, string OpcodeStr,
874 ValueType ResTy, ValueType OpTy, SDNode OpNode>
875 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
876 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin,
877 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
878 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
879 (i32 imm:$SIMM))))]>;
881 // Shift right by immediate and accumulate,
882 // both double- and quad-register.
883 class N2VDShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
884 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
885 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
886 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
888 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
889 [(set DPR:$dst, (Ty (add DPR:$src1,
890 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
891 class N2VQShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
892 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
893 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
894 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
896 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
897 [(set QPR:$dst, (Ty (add QPR:$src1,
898 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
900 // Shift by immediate and insert,
901 // both double- and quad-register.
902 class N2VDShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
903 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
904 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
905 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
907 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
908 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
909 class N2VQShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
910 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
911 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
912 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
914 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
915 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
917 // Convert, with fractional bits immediate,
918 // both double- and quad-register.
919 class N2VCvtD<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
920 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
922 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
923 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VUNAD,
924 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
925 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
926 class N2VCvtQ<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
927 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
929 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
930 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), IIC_VUNAQ,
931 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
932 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
934 //===----------------------------------------------------------------------===//
936 //===----------------------------------------------------------------------===//
938 // Abbreviations used in multiclass suffixes:
939 // Q = quarter int (8 bit) elements
940 // H = half int (16 bit) elements
941 // S = single int (32 bit) elements
942 // D = double int (64 bit) elements
944 // Neon 3-register vector operations.
946 // First with only element sizes of 8, 16 and 32 bits:
947 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
948 InstrItinClass itinD16, InstrItinClass itinD32,
949 InstrItinClass itinQ16, InstrItinClass itinQ32,
950 string OpcodeStr, SDNode OpNode, bit Commutable = 0> {
951 // 64-bit vector types.
952 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
953 !strconcat(OpcodeStr, "8"), v8i8, v8i8, OpNode, Commutable>;
954 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
955 !strconcat(OpcodeStr, "16"), v4i16, v4i16, OpNode, Commutable>;
956 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
957 !strconcat(OpcodeStr, "32"), v2i32, v2i32, OpNode, Commutable>;
959 // 128-bit vector types.
960 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
961 !strconcat(OpcodeStr, "8"), v16i8, v16i8, OpNode, Commutable>;
962 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
963 !strconcat(OpcodeStr, "16"), v8i16, v8i16, OpNode, Commutable>;
964 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
965 !strconcat(OpcodeStr, "32"), v4i32, v4i32, OpNode, Commutable>;
968 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, SDNode ShOp> {
969 def v4i16 : N3VDSL16<0b01, op11_8, !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
970 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
971 def v8i16 : N3VQSL16<0b01, op11_8, !strconcat(OpcodeStr, "16"), v8i16, v4i16, ShOp>;
972 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, !strconcat(OpcodeStr, "32"), v4i32, v2i32, ShOp>;
975 // ....then also with element size 64 bits:
976 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
977 InstrItinClass itinD, InstrItinClass itinQ,
978 string OpcodeStr, SDNode OpNode, bit Commutable = 0>
979 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
980 OpcodeStr, OpNode, Commutable> {
981 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
982 !strconcat(OpcodeStr, "64"), v1i64, v1i64, OpNode, Commutable>;
983 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
984 !strconcat(OpcodeStr, "64"), v2i64, v2i64, OpNode, Commutable>;
988 // Neon Narrowing 2-register vector intrinsics,
989 // source operand element sizes of 16, 32 and 64 bits:
990 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
991 bits<5> op11_7, bit op6, bit op4,
992 InstrItinClass itin, string OpcodeStr,
994 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
995 itin, !strconcat(OpcodeStr, "16"), v8i8, v8i16, IntOp>;
996 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
997 itin, !strconcat(OpcodeStr, "32"), v4i16, v4i32, IntOp>;
998 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
999 itin, !strconcat(OpcodeStr, "64"), v2i32, v2i64, IntOp>;
1003 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
1004 // source operand element sizes of 16, 32 and 64 bits:
1005 multiclass N2VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
1006 bit op4, string OpcodeStr, Intrinsic IntOp> {
1007 def v8i16 : N2VLInt<op24, op23, 0b001000, op11_8, op7, op6, op4,
1008 IIC_VQUNAiD, !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
1009 def v4i32 : N2VLInt<op24, op23, 0b010000, op11_8, op7, op6, op4,
1010 IIC_VQUNAiD, !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
1011 def v2i64 : N2VLInt<op24, op23, 0b100000, op11_8, op7, op6, op4,
1012 IIC_VQUNAiD, !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
1016 // Neon 3-register vector intrinsics.
1018 // First with only element sizes of 16 and 32 bits:
1019 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1020 InstrItinClass itinD16, InstrItinClass itinD32,
1021 InstrItinClass itinQ16, InstrItinClass itinQ32,
1022 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
1023 // 64-bit vector types.
1024 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, itinD16, !strconcat(OpcodeStr,"16"),
1025 v4i16, v4i16, IntOp, Commutable>;
1026 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, itinD32, !strconcat(OpcodeStr,"32"),
1027 v2i32, v2i32, IntOp, Commutable>;
1029 // 128-bit vector types.
1030 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, itinQ16, !strconcat(OpcodeStr,"16"),
1031 v8i16, v8i16, IntOp, Commutable>;
1032 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, itinQ32, !strconcat(OpcodeStr,"32"),
1033 v4i32, v4i32, IntOp, Commutable>;
1036 multiclass N3VIntSL_HS<bits<4> op11_8,
1037 InstrItinClass itinD16, InstrItinClass itinD32,
1038 InstrItinClass itinQ16, InstrItinClass itinQ32,
1039 string OpcodeStr, Intrinsic IntOp> {
1040 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16, !strconcat(OpcodeStr, "16"), v4i16, IntOp>;
1041 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32, !strconcat(OpcodeStr, "32"), v2i32, IntOp>;
1042 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16, !strconcat(OpcodeStr, "16"), v8i16, v4i16, IntOp>;
1043 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32, !strconcat(OpcodeStr, "32"), v4i32, v2i32, IntOp>;
1046 // ....then also with element size of 8 bits:
1047 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1048 InstrItinClass itinD16, InstrItinClass itinD32,
1049 InstrItinClass itinQ16, InstrItinClass itinQ32,
1050 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
1051 : N3VInt_HS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
1052 OpcodeStr, IntOp, Commutable> {
1053 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, itinD16,
1054 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp, Commutable>;
1055 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, itinQ16,
1056 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp, Commutable>;
1059 // ....then also with element size of 64 bits:
1060 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1061 InstrItinClass itinD16, InstrItinClass itinD32,
1062 InstrItinClass itinQ16, InstrItinClass itinQ32,
1063 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
1064 : N3VInt_QHS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
1065 OpcodeStr, IntOp, Commutable> {
1066 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, itinD32,
1067 !strconcat(OpcodeStr,"64"), v1i64, v1i64, IntOp, Commutable>;
1068 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, itinQ32,
1069 !strconcat(OpcodeStr,"64"), v2i64, v2i64, IntOp, Commutable>;
1073 // Neon Narrowing 3-register vector intrinsics,
1074 // source operand element sizes of 16, 32 and 64 bits:
1075 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1076 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
1077 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr,"16"),
1078 v8i8, v8i16, IntOp, Commutable>;
1079 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"32"),
1080 v4i16, v4i32, IntOp, Commutable>;
1081 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"64"),
1082 v2i32, v2i64, IntOp, Commutable>;
1086 // Neon Long 3-register vector intrinsics.
1088 // First with only element sizes of 16 and 32 bits:
1089 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1090 InstrItinClass itin, string OpcodeStr,
1091 Intrinsic IntOp, bit Commutable = 0> {
1092 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin,
1093 !strconcat(OpcodeStr,"16"), v4i32, v4i16, IntOp, Commutable>;
1094 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin,
1095 !strconcat(OpcodeStr,"32"), v2i64, v2i32, IntOp, Commutable>;
1098 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
1099 InstrItinClass itin, string OpcodeStr, Intrinsic IntOp> {
1100 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
1101 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
1102 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
1103 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
1106 // ....then also with element size of 8 bits:
1107 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1108 InstrItinClass itin, string OpcodeStr,
1109 Intrinsic IntOp, bit Commutable = 0>
1110 : N3VLInt_HS<op24, op23, op11_8, op4, itin, OpcodeStr, IntOp, Commutable> {
1111 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin,
1112 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp, Commutable>;
1116 // Neon Wide 3-register vector intrinsics,
1117 // source operand element sizes of 8, 16 and 32 bits:
1118 multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1119 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
1120 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
1121 v8i16, v8i8, IntOp, Commutable>;
1122 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
1123 v4i32, v4i16, IntOp, Commutable>;
1124 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
1125 v2i64, v2i32, IntOp, Commutable>;
1129 // Neon Multiply-Op vector operations,
1130 // element sizes of 8, 16 and 32 bits:
1131 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1132 InstrItinClass itinD16, InstrItinClass itinD32,
1133 InstrItinClass itinQ16, InstrItinClass itinQ32,
1134 string OpcodeStr, SDNode OpNode> {
1135 // 64-bit vector types.
1136 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
1137 !strconcat(OpcodeStr, "8"), v8i8, mul, OpNode>;
1138 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
1139 !strconcat(OpcodeStr, "16"), v4i16, mul, OpNode>;
1140 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
1141 !strconcat(OpcodeStr, "32"), v2i32, mul, OpNode>;
1143 // 128-bit vector types.
1144 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
1145 !strconcat(OpcodeStr, "8"), v16i8, mul, OpNode>;
1146 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
1147 !strconcat(OpcodeStr, "16"), v8i16, mul, OpNode>;
1148 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
1149 !strconcat(OpcodeStr, "32"), v4i32, mul, OpNode>;
1152 multiclass N3VMulOpSL_HS<bits<4> op11_8,
1153 InstrItinClass itinD16, InstrItinClass itinD32,
1154 InstrItinClass itinQ16, InstrItinClass itinQ32,
1155 string OpcodeStr, SDNode ShOp> {
1156 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
1157 !strconcat(OpcodeStr, "16"), v4i16, mul, ShOp>;
1158 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
1159 !strconcat(OpcodeStr, "32"), v2i32, mul, ShOp>;
1160 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
1161 !strconcat(OpcodeStr, "16"), v8i16, v4i16, mul, ShOp>;
1162 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
1163 !strconcat(OpcodeStr, "32"), v4i32, v2i32, mul, ShOp>;
1166 // Neon 3-argument intrinsics,
1167 // element sizes of 8, 16 and 32 bits:
1168 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1169 string OpcodeStr, Intrinsic IntOp> {
1170 // 64-bit vector types.
1171 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16D,
1172 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
1173 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
1174 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
1175 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32D,
1176 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
1178 // 128-bit vector types.
1179 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16Q,
1180 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
1181 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16Q,
1182 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
1183 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32Q,
1184 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
1188 // Neon Long 3-argument intrinsics.
1190 // First with only element sizes of 16 and 32 bits:
1191 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1192 string OpcodeStr, Intrinsic IntOp> {
1193 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
1194 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
1195 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi16D,
1196 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
1199 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
1200 string OpcodeStr, Intrinsic IntOp> {
1201 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
1202 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
1203 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
1204 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
1207 // ....then also with element size of 8 bits:
1208 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1209 string OpcodeStr, Intrinsic IntOp>
1210 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp> {
1211 def v8i16 : N3VLInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
1212 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
1216 // Neon 2-register vector intrinsics,
1217 // element sizes of 8, 16 and 32 bits:
1218 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1219 bits<5> op11_7, bit op4,
1220 InstrItinClass itinD, InstrItinClass itinQ,
1221 string OpcodeStr, Intrinsic IntOp> {
1222 // 64-bit vector types.
1223 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1224 itinD, !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
1225 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1226 itinD, !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
1227 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1228 itinD, !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
1230 // 128-bit vector types.
1231 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1232 itinQ, !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
1233 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1234 itinQ, !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
1235 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1236 itinQ, !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
1240 // Neon Pairwise long 2-register intrinsics,
1241 // element sizes of 8, 16 and 32 bits:
1242 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1243 bits<5> op11_7, bit op4,
1244 string OpcodeStr, Intrinsic IntOp> {
1245 // 64-bit vector types.
1246 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1247 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
1248 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1249 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
1250 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1251 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
1253 // 128-bit vector types.
1254 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1255 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
1256 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1257 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
1258 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1259 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
1263 // Neon Pairwise long 2-register accumulate intrinsics,
1264 // element sizes of 8, 16 and 32 bits:
1265 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1266 bits<5> op11_7, bit op4,
1267 string OpcodeStr, Intrinsic IntOp> {
1268 // 64-bit vector types.
1269 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1270 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
1271 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1272 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
1273 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1274 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
1276 // 128-bit vector types.
1277 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1278 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
1279 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1280 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
1281 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1282 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
1286 // Neon 2-register vector shift by immediate,
1287 // element sizes of 8, 16, 32 and 64 bits:
1288 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1289 InstrItinClass itin, string OpcodeStr, SDNode OpNode> {
1290 // 64-bit vector types.
1291 def v8i8 : N2VDSh<op24, op23, 0b001000, op11_8, 0, op4, itin,
1292 !strconcat(OpcodeStr, "8"), v8i8, OpNode>;
1293 def v4i16 : N2VDSh<op24, op23, 0b010000, op11_8, 0, op4, itin,
1294 !strconcat(OpcodeStr, "16"), v4i16, OpNode>;
1295 def v2i32 : N2VDSh<op24, op23, 0b100000, op11_8, 0, op4, itin,
1296 !strconcat(OpcodeStr, "32"), v2i32, OpNode>;
1297 def v1i64 : N2VDSh<op24, op23, 0b000000, op11_8, 1, op4, itin,
1298 !strconcat(OpcodeStr, "64"), v1i64, OpNode>;
1300 // 128-bit vector types.
1301 def v16i8 : N2VQSh<op24, op23, 0b001000, op11_8, 0, op4, itin,
1302 !strconcat(OpcodeStr, "8"), v16i8, OpNode>;
1303 def v8i16 : N2VQSh<op24, op23, 0b010000, op11_8, 0, op4, itin,
1304 !strconcat(OpcodeStr, "16"), v8i16, OpNode>;
1305 def v4i32 : N2VQSh<op24, op23, 0b100000, op11_8, 0, op4, itin,
1306 !strconcat(OpcodeStr, "32"), v4i32, OpNode>;
1307 def v2i64 : N2VQSh<op24, op23, 0b000000, op11_8, 1, op4, itin,
1308 !strconcat(OpcodeStr, "64"), v2i64, OpNode>;
1312 // Neon Shift-Accumulate vector operations,
1313 // element sizes of 8, 16, 32 and 64 bits:
1314 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1315 string OpcodeStr, SDNode ShOp> {
1316 // 64-bit vector types.
1317 def v8i8 : N2VDShAdd<op24, op23, 0b001000, op11_8, 0, op4,
1318 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
1319 def v4i16 : N2VDShAdd<op24, op23, 0b010000, op11_8, 0, op4,
1320 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
1321 def v2i32 : N2VDShAdd<op24, op23, 0b100000, op11_8, 0, op4,
1322 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
1323 def v1i64 : N2VDShAdd<op24, op23, 0b000000, op11_8, 1, op4,
1324 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
1326 // 128-bit vector types.
1327 def v16i8 : N2VQShAdd<op24, op23, 0b001000, op11_8, 0, op4,
1328 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
1329 def v8i16 : N2VQShAdd<op24, op23, 0b010000, op11_8, 0, op4,
1330 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
1331 def v4i32 : N2VQShAdd<op24, op23, 0b100000, op11_8, 0, op4,
1332 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
1333 def v2i64 : N2VQShAdd<op24, op23, 0b000000, op11_8, 1, op4,
1334 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
1338 // Neon Shift-Insert vector operations,
1339 // element sizes of 8, 16, 32 and 64 bits:
1340 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1341 string OpcodeStr, SDNode ShOp> {
1342 // 64-bit vector types.
1343 def v8i8 : N2VDShIns<op24, op23, 0b001000, op11_8, 0, op4,
1344 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
1345 def v4i16 : N2VDShIns<op24, op23, 0b010000, op11_8, 0, op4,
1346 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
1347 def v2i32 : N2VDShIns<op24, op23, 0b100000, op11_8, 0, op4,
1348 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
1349 def v1i64 : N2VDShIns<op24, op23, 0b000000, op11_8, 1, op4,
1350 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
1352 // 128-bit vector types.
1353 def v16i8 : N2VQShIns<op24, op23, 0b001000, op11_8, 0, op4,
1354 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
1355 def v8i16 : N2VQShIns<op24, op23, 0b010000, op11_8, 0, op4,
1356 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
1357 def v4i32 : N2VQShIns<op24, op23, 0b100000, op11_8, 0, op4,
1358 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
1359 def v2i64 : N2VQShIns<op24, op23, 0b000000, op11_8, 1, op4,
1360 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
1363 //===----------------------------------------------------------------------===//
1364 // Instruction Definitions.
1365 //===----------------------------------------------------------------------===//
1367 // Vector Add Operations.
1369 // VADD : Vector Add (integer and floating-point)
1370 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd.i", add, 1>;
1371 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd.f32", v2f32, v2f32, fadd, 1>;
1372 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd.f32", v4f32, v4f32, fadd, 1>;
1373 // VADDL : Vector Add Long (Q = D + D)
1374 defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, IIC_VSHLiD, "vaddl.s", int_arm_neon_vaddls, 1>;
1375 defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, IIC_VSHLiD, "vaddl.u", int_arm_neon_vaddlu, 1>;
1376 // VADDW : Vector Add Wide (Q = Q + D)
1377 defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw.s", int_arm_neon_vaddws, 0>;
1378 defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw.u", int_arm_neon_vaddwu, 0>;
1379 // VHADD : Vector Halving Add
1380 defm VHADDs : N3VInt_QHS<0,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1381 IIC_VBINi4Q, "vhadd.s", int_arm_neon_vhadds, 1>;
1382 defm VHADDu : N3VInt_QHS<1,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1383 IIC_VBINi4Q, "vhadd.u", int_arm_neon_vhaddu, 1>;
1384 // VRHADD : Vector Rounding Halving Add
1385 defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1386 IIC_VBINi4Q, "vrhadd.s", int_arm_neon_vrhadds, 1>;
1387 defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1388 IIC_VBINi4Q, "vrhadd.u", int_arm_neon_vrhaddu, 1>;
1389 // VQADD : Vector Saturating Add
1390 defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1391 IIC_VBINi4Q, "vqadd.s", int_arm_neon_vqadds, 1>;
1392 defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1393 IIC_VBINi4Q, "vqadd.u", int_arm_neon_vqaddu, 1>;
1394 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
1395 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn.i", int_arm_neon_vaddhn, 1>;
1396 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
1397 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn.i", int_arm_neon_vraddhn, 1>;
1399 // Vector Multiply Operations.
1401 // VMUL : Vector Multiply (integer, polynomial and floating-point)
1402 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D, IIC_VMULi16Q,
1403 IIC_VMULi32Q, "vmul.i", mul, 1>;
1404 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16D, "vmul.p8", v8i8, v8i8,
1405 int_arm_neon_vmulp, 1>;
1406 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16Q, "vmul.p8", v16i8, v16i8,
1407 int_arm_neon_vmulp, 1>;
1408 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VBIND, "vmul.f32", v2f32, v2f32, fmul, 1>;
1409 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VBINQ, "vmul.f32", v4f32, v4f32, fmul, 1>;
1410 defm VMULsl : N3VSL_HS<0b1000, "vmul.i", mul>;
1411 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul.f32", v2f32, fmul>;
1412 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul.f32", v4f32, v2f32, fmul>;
1413 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
1414 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
1415 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
1416 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1417 (DSubReg_i16_reg imm:$lane))),
1418 (SubReg_i16_lane imm:$lane)))>;
1419 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
1420 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
1421 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
1422 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1423 (DSubReg_i32_reg imm:$lane))),
1424 (SubReg_i32_lane imm:$lane)))>;
1425 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
1426 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
1427 (v4f32 (VMULslfq (v4f32 QPR:$src1),
1428 (v2f32 (EXTRACT_SUBREG QPR:$src2,
1429 (DSubReg_i32_reg imm:$lane))),
1430 (SubReg_i32_lane imm:$lane)))>;
1432 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
1433 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
1434 IIC_VMULi16Q, IIC_VMULi32Q,
1435 "vqdmulh.s", int_arm_neon_vqdmulh, 1>;
1436 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
1437 IIC_VMULi16Q, IIC_VMULi32Q,
1438 "vqdmulh.s", int_arm_neon_vqdmulh>;
1439 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
1440 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
1441 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
1442 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1443 (DSubReg_i16_reg imm:$lane))),
1444 (SubReg_i16_lane imm:$lane)))>;
1445 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
1446 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
1447 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
1448 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1449 (DSubReg_i32_reg imm:$lane))),
1450 (SubReg_i32_lane imm:$lane)))>;
1452 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
1453 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
1454 IIC_VMULi16Q, IIC_VMULi32Q,
1455 "vqrdmulh.s", int_arm_neon_vqrdmulh, 1>;
1456 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
1457 IIC_VMULi16Q, IIC_VMULi32Q,
1458 "vqrdmulh.s", int_arm_neon_vqrdmulh>;
1459 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
1460 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
1461 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
1462 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1463 (DSubReg_i16_reg imm:$lane))),
1464 (SubReg_i16_lane imm:$lane)))>;
1465 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
1466 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
1467 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
1468 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1469 (DSubReg_i32_reg imm:$lane))),
1470 (SubReg_i32_lane imm:$lane)))>;
1472 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
1473 defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, IIC_VMULi16D, "vmull.s", int_arm_neon_vmulls, 1>;
1474 defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, IIC_VMULi16D, "vmull.u", int_arm_neon_vmullu, 1>;
1475 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull.p8", v8i16, v8i8,
1476 int_arm_neon_vmullp, 1>;
1477 defm VMULLsls : N3VLIntSL_HS<0, 0b1010, IIC_VMULi16D, "vmull.s", int_arm_neon_vmulls>;
1478 defm VMULLslu : N3VLIntSL_HS<1, 0b1010, IIC_VMULi16D, "vmull.u", int_arm_neon_vmullu>;
1480 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
1481 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, "vqdmull.s", int_arm_neon_vqdmull, 1>;
1482 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D, "vqdmull.s", int_arm_neon_vqdmull>;
1484 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
1486 // VMLA : Vector Multiply Accumulate (integer and floating-point)
1487 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
1488 IIC_VMACi16Q, IIC_VMACi32Q, "vmla.i", add>;
1489 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla.f32", v2f32, fmul, fadd>;
1490 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla.f32", v4f32, fmul, fadd>;
1491 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
1492 IIC_VMACi16Q, IIC_VMACi32Q, "vmla.i", add>;
1493 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla.f32", v2f32, fmul, fadd>;
1494 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla.f32", v4f32, v2f32, fmul, fadd>;
1496 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
1497 (mul (v8i16 QPR:$src2),
1498 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
1499 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1),
1501 (v4i16 (EXTRACT_SUBREG QPR:$src3,
1502 (DSubReg_i16_reg imm:$lane))),
1503 (SubReg_i16_lane imm:$lane)))>;
1505 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
1506 (mul (v4i32 QPR:$src2),
1507 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
1508 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1),
1510 (v2i32 (EXTRACT_SUBREG QPR:$src3,
1511 (DSubReg_i32_reg imm:$lane))),
1512 (SubReg_i32_lane imm:$lane)))>;
1514 def : Pat<(v4f32 (fadd (v4f32 QPR:$src1),
1515 (fmul (v4f32 QPR:$src2),
1516 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
1517 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
1519 (v2f32 (EXTRACT_SUBREG QPR:$src3,
1520 (DSubReg_i32_reg imm:$lane))),
1521 (SubReg_i32_lane imm:$lane)))>;
1523 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
1524 defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal.s", int_arm_neon_vmlals>;
1525 defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal.u", int_arm_neon_vmlalu>;
1527 defm VMLALsls : N3VLInt3SL_HS<0, 0b0010, "vmlal.s", int_arm_neon_vmlals>;
1528 defm VMLALslu : N3VLInt3SL_HS<1, 0b0010, "vmlal.u", int_arm_neon_vmlalu>;
1530 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
1531 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal.s", int_arm_neon_vqdmlal>;
1532 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal.s", int_arm_neon_vqdmlal>;
1534 // VMLS : Vector Multiply Subtract (integer and floating-point)
1535 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
1536 IIC_VMACi16Q, IIC_VMACi32Q, "vmls.i", sub>;
1537 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls.f32", v2f32, fmul, fsub>;
1538 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls.f32", v4f32, fmul, fsub>;
1539 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
1540 IIC_VMACi16Q, IIC_VMACi32Q, "vmls.i", sub>;
1541 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls.f32", v2f32, fmul, fsub>;
1542 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls.f32", v4f32, v2f32, fmul, fsub>;
1544 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
1545 (mul (v8i16 QPR:$src2),
1546 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
1547 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1),
1549 (v4i16 (EXTRACT_SUBREG QPR:$src3,
1550 (DSubReg_i16_reg imm:$lane))),
1551 (SubReg_i16_lane imm:$lane)))>;
1553 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
1554 (mul (v4i32 QPR:$src2),
1555 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
1556 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1),
1558 (v2i32 (EXTRACT_SUBREG QPR:$src3,
1559 (DSubReg_i32_reg imm:$lane))),
1560 (SubReg_i32_lane imm:$lane)))>;
1562 def : Pat<(v4f32 (fsub (v4f32 QPR:$src1),
1563 (fmul (v4f32 QPR:$src2),
1564 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
1565 (v4f32 (VMLSslfq (v4f32 QPR:$src1),
1567 (v2f32 (EXTRACT_SUBREG QPR:$src3,
1568 (DSubReg_i32_reg imm:$lane))),
1569 (SubReg_i32_lane imm:$lane)))>;
1571 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
1572 defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl.s", int_arm_neon_vmlsls>;
1573 defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl.u", int_arm_neon_vmlslu>;
1575 defm VMLSLsls : N3VLInt3SL_HS<0, 0b0110, "vmlsl.s", int_arm_neon_vmlsls>;
1576 defm VMLSLslu : N3VLInt3SL_HS<1, 0b0110, "vmlsl.u", int_arm_neon_vmlslu>;
1578 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
1579 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl.s", int_arm_neon_vqdmlsl>;
1580 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl.s", int_arm_neon_vqdmlsl>;
1582 // Vector Subtract Operations.
1584 // VSUB : Vector Subtract (integer and floating-point)
1585 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ, "vsub.i", sub, 0>;
1586 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub.f32", v2f32, v2f32, fsub, 0>;
1587 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub.f32", v4f32, v4f32, fsub, 0>;
1588 // VSUBL : Vector Subtract Long (Q = D - D)
1589 defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, IIC_VSHLiD, "vsubl.s", int_arm_neon_vsubls, 1>;
1590 defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, IIC_VSHLiD, "vsubl.u", int_arm_neon_vsublu, 1>;
1591 // VSUBW : Vector Subtract Wide (Q = Q - D)
1592 defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw.s", int_arm_neon_vsubws, 0>;
1593 defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw.u", int_arm_neon_vsubwu, 0>;
1594 // VHSUB : Vector Halving Subtract
1595 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1596 IIC_VBINi4Q, "vhsub.s", int_arm_neon_vhsubs, 0>;
1597 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1598 IIC_VBINi4Q, "vhsub.u", int_arm_neon_vhsubu, 0>;
1599 // VQSUB : Vector Saturing Subtract
1600 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1601 IIC_VBINi4Q, "vqsub.s", int_arm_neon_vqsubs, 0>;
1602 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1603 IIC_VBINi4Q, "vqsub.u", int_arm_neon_vqsubu, 0>;
1604 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
1605 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn.i", int_arm_neon_vsubhn, 0>;
1606 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
1607 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn.i", int_arm_neon_vrsubhn, 0>;
1609 // Vector Comparisons.
1611 // VCEQ : Vector Compare Equal
1612 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1613 IIC_VBINi4Q, "vceq.i", NEONvceq, 1>;
1614 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq.f32", v2i32, v2f32, NEONvceq, 1>;
1615 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq.f32", v4i32, v4f32, NEONvceq, 1>;
1616 // VCGE : Vector Compare Greater Than or Equal
1617 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1618 IIC_VBINi4Q, "vcge.s", NEONvcge, 0>;
1619 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1620 IIC_VBINi4Q, "vcge.u", NEONvcgeu, 0>;
1621 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge.f32", v2i32, v2f32, NEONvcge, 0>;
1622 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge.f32", v4i32, v4f32, NEONvcge, 0>;
1623 // VCGT : Vector Compare Greater Than
1624 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1625 IIC_VBINi4Q, "vcgt.s", NEONvcgt, 0>;
1626 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1627 IIC_VBINi4Q, "vcgt.u", NEONvcgtu, 0>;
1628 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt.f32", v2i32, v2f32, NEONvcgt, 0>;
1629 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt.f32", v4i32, v4f32, NEONvcgt, 0>;
1630 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
1631 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, IIC_VBIND, "vacge.f32", v2i32, v2f32,
1632 int_arm_neon_vacged, 0>;
1633 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, IIC_VBINQ, "vacge.f32", v4i32, v4f32,
1634 int_arm_neon_vacgeq, 0>;
1635 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
1636 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, IIC_VBIND, "vacgt.f32", v2i32, v2f32,
1637 int_arm_neon_vacgtd, 0>;
1638 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, IIC_VBINQ, "vacgt.f32", v4i32, v4f32,
1639 int_arm_neon_vacgtq, 0>;
1640 // VTST : Vector Test Bits
1641 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1642 IIC_VBINi4Q, "vtst.i", NEONvtst, 1>;
1644 // Vector Bitwise Operations.
1646 // VAND : Vector Bitwise AND
1647 def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand", v2i32, v2i32, and, 1>;
1648 def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand", v4i32, v4i32, and, 1>;
1650 // VEOR : Vector Bitwise Exclusive OR
1651 def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor", v2i32, v2i32, xor, 1>;
1652 def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor", v4i32, v4i32, xor, 1>;
1654 // VORR : Vector Bitwise OR
1655 def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr", v2i32, v2i32, or, 1>;
1656 def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr", v4i32, v4i32, or, 1>;
1658 // VBIC : Vector Bitwise Bit Clear (AND NOT)
1659 def VBICd : N3V<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1660 (ins DPR:$src1, DPR:$src2), IIC_VBINiD,
1661 "vbic\t$dst, $src1, $src2", "",
1662 [(set DPR:$dst, (v2i32 (and DPR:$src1,
1663 (vnot_conv DPR:$src2))))]>;
1664 def VBICq : N3V<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1665 (ins QPR:$src1, QPR:$src2), IIC_VBINiQ,
1666 "vbic\t$dst, $src1, $src2", "",
1667 [(set QPR:$dst, (v4i32 (and QPR:$src1,
1668 (vnot_conv QPR:$src2))))]>;
1670 // VORN : Vector Bitwise OR NOT
1671 def VORNd : N3V<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
1672 (ins DPR:$src1, DPR:$src2), IIC_VBINiD,
1673 "vorn\t$dst, $src1, $src2", "",
1674 [(set DPR:$dst, (v2i32 (or DPR:$src1,
1675 (vnot_conv DPR:$src2))))]>;
1676 def VORNq : N3V<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
1677 (ins QPR:$src1, QPR:$src2), IIC_VBINiQ,
1678 "vorn\t$dst, $src1, $src2", "",
1679 [(set QPR:$dst, (v4i32 (or QPR:$src1,
1680 (vnot_conv QPR:$src2))))]>;
1682 // VMVN : Vector Bitwise NOT
1683 def VMVNd : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
1684 (outs DPR:$dst), (ins DPR:$src), IIC_VSHLiD,
1685 "vmvn\t$dst, $src", "",
1686 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>;
1687 def VMVNq : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
1688 (outs QPR:$dst), (ins QPR:$src), IIC_VSHLiD,
1689 "vmvn\t$dst, $src", "",
1690 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>;
1691 def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>;
1692 def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>;
1694 // VBSL : Vector Bitwise Select
1695 def VBSLd : N3V<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1696 (ins DPR:$src1, DPR:$src2, DPR:$src3), IIC_VCNTiD,
1697 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1699 (v2i32 (or (and DPR:$src2, DPR:$src1),
1700 (and DPR:$src3, (vnot_conv DPR:$src1)))))]>;
1701 def VBSLq : N3V<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1702 (ins QPR:$src1, QPR:$src2, QPR:$src3), IIC_VCNTiQ,
1703 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1705 (v4i32 (or (and QPR:$src2, QPR:$src1),
1706 (and QPR:$src3, (vnot_conv QPR:$src1)))))]>;
1708 // VBIF : Vector Bitwise Insert if False
1709 // like VBSL but with: "vbif\t$dst, $src3, $src1", "$src2 = $dst",
1710 // VBIT : Vector Bitwise Insert if True
1711 // like VBSL but with: "vbit\t$dst, $src2, $src1", "$src3 = $dst",
1712 // These are not yet implemented. The TwoAddress pass will not go looking
1713 // for equivalent operations with different register constraints; it just
1716 // Vector Absolute Differences.
1718 // VABD : Vector Absolute Difference
1719 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1720 IIC_VBINi4Q, "vabd.s", int_arm_neon_vabds, 0>;
1721 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1722 IIC_VBINi4Q, "vabd.u", int_arm_neon_vabdu, 0>;
1723 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, IIC_VBIND, "vabd.f32", v2f32, v2f32,
1724 int_arm_neon_vabds, 0>;
1725 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vabd.f32", v4f32, v4f32,
1726 int_arm_neon_vabds, 0>;
1728 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
1729 defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, IIC_VBINi4Q, "vabdl.s", int_arm_neon_vabdls, 0>;
1730 defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, IIC_VBINi4Q, "vabdl.u", int_arm_neon_vabdlu, 0>;
1732 // VABA : Vector Absolute Difference and Accumulate
1733 defm VABAs : N3VInt3_QHS<0,1,0b0101,0, "vaba.s", int_arm_neon_vabas>;
1734 defm VABAu : N3VInt3_QHS<1,1,0b0101,0, "vaba.u", int_arm_neon_vabau>;
1736 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
1737 defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal.s", int_arm_neon_vabals>;
1738 defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal.u", int_arm_neon_vabalu>;
1740 // Vector Maximum and Minimum.
1742 // VMAX : Vector Maximum
1743 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1744 IIC_VBINi4Q, "vmax.s", int_arm_neon_vmaxs, 1>;
1745 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1746 IIC_VBINi4Q, "vmax.u", int_arm_neon_vmaxu, 1>;
1747 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, IIC_VBIND, "vmax.f32", v2f32, v2f32,
1748 int_arm_neon_vmaxs, 1>;
1749 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, IIC_VBINQ, "vmax.f32", v4f32, v4f32,
1750 int_arm_neon_vmaxs, 1>;
1752 // VMIN : Vector Minimum
1753 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1754 IIC_VBINi4Q, "vmin.s", int_arm_neon_vmins, 1>;
1755 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1756 IIC_VBINi4Q, "vmin.u", int_arm_neon_vminu, 1>;
1757 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, IIC_VBIND, "vmin.f32", v2f32, v2f32,
1758 int_arm_neon_vmins, 1>;
1759 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, IIC_VBINQ, "vmin.f32", v4f32, v4f32,
1760 int_arm_neon_vmins, 1>;
1762 // Vector Pairwise Operations.
1764 // VPADD : Vector Pairwise Add
1765 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, IIC_VBINiD, "vpadd.i8", v8i8, v8i8,
1766 int_arm_neon_vpadd, 0>;
1767 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, IIC_VBINiD, "vpadd.i16", v4i16, v4i16,
1768 int_arm_neon_vpadd, 0>;
1769 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, IIC_VBINiD, "vpadd.i32", v2i32, v2i32,
1770 int_arm_neon_vpadd, 0>;
1771 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, IIC_VBIND, "vpadd.f32", v2f32, v2f32,
1772 int_arm_neon_vpadd, 0>;
1774 // VPADDL : Vector Pairwise Add Long
1775 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl.s",
1776 int_arm_neon_vpaddls>;
1777 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl.u",
1778 int_arm_neon_vpaddlu>;
1780 // VPADAL : Vector Pairwise Add and Accumulate Long
1781 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpadal.s",
1782 int_arm_neon_vpadals>;
1783 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpadal.u",
1784 int_arm_neon_vpadalu>;
1786 // VPMAX : Vector Pairwise Maximum
1787 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax.s8", v8i8, v8i8,
1788 int_arm_neon_vpmaxs, 0>;
1789 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax.s16", v4i16, v4i16,
1790 int_arm_neon_vpmaxs, 0>;
1791 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax.s32", v2i32, v2i32,
1792 int_arm_neon_vpmaxs, 0>;
1793 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax.u8", v8i8, v8i8,
1794 int_arm_neon_vpmaxu, 0>;
1795 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax.u16", v4i16, v4i16,
1796 int_arm_neon_vpmaxu, 0>;
1797 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax.u32", v2i32, v2i32,
1798 int_arm_neon_vpmaxu, 0>;
1799 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, IIC_VBINi4D, "vpmax.f32", v2f32, v2f32,
1800 int_arm_neon_vpmaxs, 0>;
1802 // VPMIN : Vector Pairwise Minimum
1803 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin.s8", v8i8, v8i8,
1804 int_arm_neon_vpmins, 0>;
1805 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin.s16", v4i16, v4i16,
1806 int_arm_neon_vpmins, 0>;
1807 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin.s32", v2i32, v2i32,
1808 int_arm_neon_vpmins, 0>;
1809 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin.u8", v8i8, v8i8,
1810 int_arm_neon_vpminu, 0>;
1811 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin.u16", v4i16, v4i16,
1812 int_arm_neon_vpminu, 0>;
1813 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin.u32", v2i32, v2i32,
1814 int_arm_neon_vpminu, 0>;
1815 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, IIC_VBINi4D, "vpmin.f32", v2f32, v2f32,
1816 int_arm_neon_vpmins, 0>;
1818 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
1820 // VRECPE : Vector Reciprocal Estimate
1821 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
1822 IIC_VUNAD, "vrecpe.u32",
1823 v2i32, v2i32, int_arm_neon_vrecpe>;
1824 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
1825 IIC_VUNAQ, "vrecpe.u32",
1826 v4i32, v4i32, int_arm_neon_vrecpe>;
1827 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
1828 IIC_VUNAD, "vrecpe.f32",
1829 v2f32, v2f32, int_arm_neon_vrecpe>;
1830 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
1831 IIC_VUNAQ, "vrecpe.f32",
1832 v4f32, v4f32, int_arm_neon_vrecpe>;
1834 // VRECPS : Vector Reciprocal Step
1835 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, IIC_VRECSD, "vrecps.f32", v2f32, v2f32,
1836 int_arm_neon_vrecps, 1>;
1837 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, IIC_VRECSQ, "vrecps.f32", v4f32, v4f32,
1838 int_arm_neon_vrecps, 1>;
1840 // VRSQRTE : Vector Reciprocal Square Root Estimate
1841 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
1842 IIC_VUNAD, "vrsqrte.u32",
1843 v2i32, v2i32, int_arm_neon_vrsqrte>;
1844 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
1845 IIC_VUNAQ, "vrsqrte.u32",
1846 v4i32, v4i32, int_arm_neon_vrsqrte>;
1847 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
1848 IIC_VUNAD, "vrsqrte.f32",
1849 v2f32, v2f32, int_arm_neon_vrsqrte>;
1850 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
1851 IIC_VUNAQ, "vrsqrte.f32",
1852 v4f32, v4f32, int_arm_neon_vrsqrte>;
1854 // VRSQRTS : Vector Reciprocal Square Root Step
1855 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, IIC_VRECSD, "vrsqrts.f32", v2f32, v2f32,
1856 int_arm_neon_vrsqrts, 1>;
1857 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, IIC_VRECSQ, "vrsqrts.f32", v4f32, v4f32,
1858 int_arm_neon_vrsqrts, 1>;
1862 // VSHL : Vector Shift
1863 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
1864 IIC_VSHLiQ, "vshl.s", int_arm_neon_vshifts, 0>;
1865 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
1866 IIC_VSHLiQ, "vshl.u", int_arm_neon_vshiftu, 0>;
1867 // VSHL : Vector Shift Left (Immediate)
1868 defm VSHLi : N2VSh_QHSD<0, 1, 0b0111, 1, IIC_VSHLiD, "vshl.i", NEONvshl>;
1869 // VSHR : Vector Shift Right (Immediate)
1870 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr.s", NEONvshrs>;
1871 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr.u", NEONvshru>;
1873 // VSHLL : Vector Shift Left Long
1874 def VSHLLs8 : N2VLSh<0, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.s8",
1875 v8i16, v8i8, NEONvshlls>;
1876 def VSHLLs16 : N2VLSh<0, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.s16",
1877 v4i32, v4i16, NEONvshlls>;
1878 def VSHLLs32 : N2VLSh<0, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.s32",
1879 v2i64, v2i32, NEONvshlls>;
1880 def VSHLLu8 : N2VLSh<1, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.u8",
1881 v8i16, v8i8, NEONvshllu>;
1882 def VSHLLu16 : N2VLSh<1, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.u16",
1883 v4i32, v4i16, NEONvshllu>;
1884 def VSHLLu32 : N2VLSh<1, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.u32",
1885 v2i64, v2i32, NEONvshllu>;
1887 // VSHLL : Vector Shift Left Long (with maximum shift count)
1888 def VSHLLi8 : N2VLSh<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll.i8",
1889 v8i16, v8i8, NEONvshlli>;
1890 def VSHLLi16 : N2VLSh<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll.i16",
1891 v4i32, v4i16, NEONvshlli>;
1892 def VSHLLi32 : N2VLSh<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll.i32",
1893 v2i64, v2i32, NEONvshlli>;
1895 // VSHRN : Vector Shift Right and Narrow
1896 def VSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 0, 1,
1897 IIC_VSHLiD, "vshrn.i16", v8i8, v8i16, NEONvshrn>;
1898 def VSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 0, 1,
1899 IIC_VSHLiD, "vshrn.i32", v4i16, v4i32, NEONvshrn>;
1900 def VSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 0, 1,
1901 IIC_VSHLiD, "vshrn.i64", v2i32, v2i64, NEONvshrn>;
1903 // VRSHL : Vector Rounding Shift
1904 defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
1905 IIC_VSHLi4Q, "vrshl.s", int_arm_neon_vrshifts, 0>;
1906 defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
1907 IIC_VSHLi4Q, "vrshl.u", int_arm_neon_vrshiftu, 0>;
1908 // VRSHR : Vector Rounding Shift Right
1909 defm VRSHRs : N2VSh_QHSD<0, 1, 0b0010, 1, IIC_VSHLi4D, "vrshr.s", NEONvrshrs>;
1910 defm VRSHRu : N2VSh_QHSD<1, 1, 0b0010, 1, IIC_VSHLi4D, "vrshr.u", NEONvrshru>;
1912 // VRSHRN : Vector Rounding Shift Right and Narrow
1913 def VRSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 1, 1,
1914 IIC_VSHLi4D, "vrshrn.i16", v8i8, v8i16, NEONvrshrn>;
1915 def VRSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 1, 1,
1916 IIC_VSHLi4D, "vrshrn.i32", v4i16, v4i32, NEONvrshrn>;
1917 def VRSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 1, 1,
1918 IIC_VSHLi4D, "vrshrn.i64", v2i32, v2i64, NEONvrshrn>;
1920 // VQSHL : Vector Saturating Shift
1921 defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
1922 IIC_VSHLi4Q, "vqshl.s", int_arm_neon_vqshifts, 0>;
1923 defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
1924 IIC_VSHLi4Q, "vqshl.u", int_arm_neon_vqshiftu, 0>;
1925 // VQSHL : Vector Saturating Shift Left (Immediate)
1926 defm VQSHLsi : N2VSh_QHSD<0, 1, 0b0111, 1, IIC_VSHLi4D, "vqshl.s", NEONvqshls>;
1927 defm VQSHLui : N2VSh_QHSD<1, 1, 0b0111, 1, IIC_VSHLi4D, "vqshl.u", NEONvqshlu>;
1928 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
1929 defm VQSHLsu : N2VSh_QHSD<1, 1, 0b0110, 1, IIC_VSHLi4D, "vqshlu.s", NEONvqshlsu>;
1931 // VQSHRN : Vector Saturating Shift Right and Narrow
1932 def VQSHRNs16 : N2VNSh<0, 1, 0b001000, 0b1001, 0, 0, 1,
1933 IIC_VSHLi4D, "vqshrn.s16", v8i8, v8i16, NEONvqshrns>;
1934 def VQSHRNs32 : N2VNSh<0, 1, 0b010000, 0b1001, 0, 0, 1,
1935 IIC_VSHLi4D, "vqshrn.s32", v4i16, v4i32, NEONvqshrns>;
1936 def VQSHRNs64 : N2VNSh<0, 1, 0b100000, 0b1001, 0, 0, 1,
1937 IIC_VSHLi4D, "vqshrn.s64", v2i32, v2i64, NEONvqshrns>;
1938 def VQSHRNu16 : N2VNSh<1, 1, 0b001000, 0b1001, 0, 0, 1,
1939 IIC_VSHLi4D, "vqshrn.u16", v8i8, v8i16, NEONvqshrnu>;
1940 def VQSHRNu32 : N2VNSh<1, 1, 0b010000, 0b1001, 0, 0, 1,
1941 IIC_VSHLi4D, "vqshrn.u32", v4i16, v4i32, NEONvqshrnu>;
1942 def VQSHRNu64 : N2VNSh<1, 1, 0b100000, 0b1001, 0, 0, 1,
1943 IIC_VSHLi4D, "vqshrn.u64", v2i32, v2i64, NEONvqshrnu>;
1945 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
1946 def VQSHRUN16 : N2VNSh<1, 1, 0b001000, 0b1000, 0, 0, 1,
1947 IIC_VSHLi4D, "vqshrun.s16", v8i8, v8i16, NEONvqshrnsu>;
1948 def VQSHRUN32 : N2VNSh<1, 1, 0b010000, 0b1000, 0, 0, 1,
1949 IIC_VSHLi4D, "vqshrun.s32", v4i16, v4i32, NEONvqshrnsu>;
1950 def VQSHRUN64 : N2VNSh<1, 1, 0b100000, 0b1000, 0, 0, 1,
1951 IIC_VSHLi4D, "vqshrun.s64", v2i32, v2i64, NEONvqshrnsu>;
1953 // VQRSHL : Vector Saturating Rounding Shift
1954 defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
1955 IIC_VSHLi4Q, "vqrshl.s", int_arm_neon_vqrshifts, 0>;
1956 defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
1957 IIC_VSHLi4Q, "vqrshl.u", int_arm_neon_vqrshiftu, 0>;
1959 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
1960 def VQRSHRNs16: N2VNSh<0, 1, 0b001000, 0b1001, 0, 1, 1,
1961 IIC_VSHLi4D, "vqrshrn.s16", v8i8, v8i16, NEONvqrshrns>;
1962 def VQRSHRNs32: N2VNSh<0, 1, 0b010000, 0b1001, 0, 1, 1,
1963 IIC_VSHLi4D, "vqrshrn.s32", v4i16, v4i32, NEONvqrshrns>;
1964 def VQRSHRNs64: N2VNSh<0, 1, 0b100000, 0b1001, 0, 1, 1,
1965 IIC_VSHLi4D, "vqrshrn.s64", v2i32, v2i64, NEONvqrshrns>;
1966 def VQRSHRNu16: N2VNSh<1, 1, 0b001000, 0b1001, 0, 1, 1,
1967 IIC_VSHLi4D, "vqrshrn.u16", v8i8, v8i16, NEONvqrshrnu>;
1968 def VQRSHRNu32: N2VNSh<1, 1, 0b010000, 0b1001, 0, 1, 1,
1969 IIC_VSHLi4D, "vqrshrn.u32", v4i16, v4i32, NEONvqrshrnu>;
1970 def VQRSHRNu64: N2VNSh<1, 1, 0b100000, 0b1001, 0, 1, 1,
1971 IIC_VSHLi4D, "vqrshrn.u64", v2i32, v2i64, NEONvqrshrnu>;
1973 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
1974 def VQRSHRUN16: N2VNSh<1, 1, 0b001000, 0b1000, 0, 1, 1,
1975 IIC_VSHLi4D, "vqrshrun.s16", v8i8, v8i16, NEONvqrshrnsu>;
1976 def VQRSHRUN32: N2VNSh<1, 1, 0b010000, 0b1000, 0, 1, 1,
1977 IIC_VSHLi4D, "vqrshrun.s32", v4i16, v4i32, NEONvqrshrnsu>;
1978 def VQRSHRUN64: N2VNSh<1, 1, 0b100000, 0b1000, 0, 1, 1,
1979 IIC_VSHLi4D, "vqrshrun.s64", v2i32, v2i64, NEONvqrshrnsu>;
1981 // VSRA : Vector Shift Right and Accumulate
1982 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra.s", NEONvshrs>;
1983 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra.u", NEONvshru>;
1984 // VRSRA : Vector Rounding Shift Right and Accumulate
1985 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra.s", NEONvrshrs>;
1986 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra.u", NEONvrshru>;
1988 // VSLI : Vector Shift Left and Insert
1989 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli.", NEONvsli>;
1990 // VSRI : Vector Shift Right and Insert
1991 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri.", NEONvsri>;
1993 // Vector Absolute and Saturating Absolute.
1995 // VABS : Vector Absolute Value
1996 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
1997 IIC_VUNAiD, IIC_VUNAiQ, "vabs.s",
1999 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2000 IIC_VUNAD, "vabs.f32",
2001 v2f32, v2f32, int_arm_neon_vabs>;
2002 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2003 IIC_VUNAQ, "vabs.f32",
2004 v4f32, v4f32, int_arm_neon_vabs>;
2006 // VQABS : Vector Saturating Absolute Value
2007 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
2008 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs.s",
2009 int_arm_neon_vqabs>;
2013 def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
2014 def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>;
2016 class VNEGD<bits<2> size, string OpcodeStr, ValueType Ty>
2017 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
2018 IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "",
2019 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>;
2020 class VNEGQ<bits<2> size, string OpcodeStr, ValueType Ty>
2021 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
2022 IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "",
2023 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>;
2025 // VNEG : Vector Negate
2026 def VNEGs8d : VNEGD<0b00, "vneg.s8", v8i8>;
2027 def VNEGs16d : VNEGD<0b01, "vneg.s16", v4i16>;
2028 def VNEGs32d : VNEGD<0b10, "vneg.s32", v2i32>;
2029 def VNEGs8q : VNEGQ<0b00, "vneg.s8", v16i8>;
2030 def VNEGs16q : VNEGQ<0b01, "vneg.s16", v8i16>;
2031 def VNEGs32q : VNEGQ<0b10, "vneg.s32", v4i32>;
2033 // VNEG : Vector Negate (floating-point)
2034 def VNEGf32d : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
2035 (outs DPR:$dst), (ins DPR:$src), IIC_VUNAD,
2036 "vneg.f32\t$dst, $src", "",
2037 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
2038 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
2039 (outs QPR:$dst), (ins QPR:$src), IIC_VUNAQ,
2040 "vneg.f32\t$dst, $src", "",
2041 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
2043 def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
2044 def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
2045 def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>;
2046 def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>;
2047 def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>;
2048 def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>;
2050 // VQNEG : Vector Saturating Negate
2051 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
2052 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg.s",
2053 int_arm_neon_vqneg>;
2055 // Vector Bit Counting Operations.
2057 // VCLS : Vector Count Leading Sign Bits
2058 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
2059 IIC_VCNTiD, IIC_VCNTiQ, "vcls.s",
2061 // VCLZ : Vector Count Leading Zeros
2062 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
2063 IIC_VCNTiD, IIC_VCNTiQ, "vclz.i",
2065 // VCNT : Vector Count One Bits
2066 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2067 IIC_VCNTiD, "vcnt.8",
2068 v8i8, v8i8, int_arm_neon_vcnt>;
2069 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2070 IIC_VCNTiQ, "vcnt.8",
2071 v16i8, v16i8, int_arm_neon_vcnt>;
2073 // Vector Move Operations.
2075 // VMOV : Vector Move (Register)
2077 def VMOVD : N3V<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
2078 IIC_VMOVD, "vmov\t$dst, $src", "", []>;
2079 def VMOVQ : N3V<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
2080 IIC_VMOVD, "vmov\t$dst, $src", "", []>;
2082 // VMOV : Vector Move (Immediate)
2084 // VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
2085 def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
2086 return ARM::getVMOVImm(N, 1, *CurDAG);
2088 def vmovImm8 : PatLeaf<(build_vector), [{
2089 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
2092 // VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
2093 def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
2094 return ARM::getVMOVImm(N, 2, *CurDAG);
2096 def vmovImm16 : PatLeaf<(build_vector), [{
2097 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
2098 }], VMOV_get_imm16>;
2100 // VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
2101 def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
2102 return ARM::getVMOVImm(N, 4, *CurDAG);
2104 def vmovImm32 : PatLeaf<(build_vector), [{
2105 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
2106 }], VMOV_get_imm32>;
2108 // VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
2109 def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
2110 return ARM::getVMOVImm(N, 8, *CurDAG);
2112 def vmovImm64 : PatLeaf<(build_vector), [{
2113 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
2114 }], VMOV_get_imm64>;
2116 // Note: Some of the cmode bits in the following VMOV instructions need to
2117 // be encoded based on the immed values.
2119 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
2120 (ins i8imm:$SIMM), IIC_VMOVImm,
2121 "vmov.i8\t$dst, $SIMM", "",
2122 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
2123 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
2124 (ins i8imm:$SIMM), IIC_VMOVImm,
2125 "vmov.i8\t$dst, $SIMM", "",
2126 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
2128 def VMOVv4i16 : N1ModImm<1, 0b000, 0b1000, 0, 0, 0, 1, (outs DPR:$dst),
2129 (ins i16imm:$SIMM), IIC_VMOVImm,
2130 "vmov.i16\t$dst, $SIMM", "",
2131 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
2132 def VMOVv8i16 : N1ModImm<1, 0b000, 0b1000, 0, 1, 0, 1, (outs QPR:$dst),
2133 (ins i16imm:$SIMM), IIC_VMOVImm,
2134 "vmov.i16\t$dst, $SIMM", "",
2135 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
2137 def VMOVv2i32 : N1ModImm<1, 0b000, 0b0000, 0, 0, 0, 1, (outs DPR:$dst),
2138 (ins i32imm:$SIMM), IIC_VMOVImm,
2139 "vmov.i32\t$dst, $SIMM", "",
2140 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
2141 def VMOVv4i32 : N1ModImm<1, 0b000, 0b0000, 0, 1, 0, 1, (outs QPR:$dst),
2142 (ins i32imm:$SIMM), IIC_VMOVImm,
2143 "vmov.i32\t$dst, $SIMM", "",
2144 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
2146 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
2147 (ins i64imm:$SIMM), IIC_VMOVImm,
2148 "vmov.i64\t$dst, $SIMM", "",
2149 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
2150 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
2151 (ins i64imm:$SIMM), IIC_VMOVImm,
2152 "vmov.i64\t$dst, $SIMM", "",
2153 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
2155 // VMOV : Vector Get Lane (move scalar to ARM core register)
2157 def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00,
2158 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2159 IIC_VMOVSI, "vmov", ".s8\t$dst, $src[$lane]",
2160 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
2162 def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01,
2163 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2164 IIC_VMOVSI, "vmov", ".s16\t$dst, $src[$lane]",
2165 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
2167 def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00,
2168 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2169 IIC_VMOVSI, "vmov", ".u8\t$dst, $src[$lane]",
2170 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
2172 def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01,
2173 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2174 IIC_VMOVSI, "vmov", ".u16\t$dst, $src[$lane]",
2175 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
2177 def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00,
2178 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2179 IIC_VMOVSI, "vmov", ".32\t$dst, $src[$lane]",
2180 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
2182 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
2183 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
2184 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2185 (DSubReg_i8_reg imm:$lane))),
2186 (SubReg_i8_lane imm:$lane))>;
2187 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
2188 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2189 (DSubReg_i16_reg imm:$lane))),
2190 (SubReg_i16_lane imm:$lane))>;
2191 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
2192 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2193 (DSubReg_i8_reg imm:$lane))),
2194 (SubReg_i8_lane imm:$lane))>;
2195 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
2196 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2197 (DSubReg_i16_reg imm:$lane))),
2198 (SubReg_i16_lane imm:$lane))>;
2199 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
2200 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
2201 (DSubReg_i32_reg imm:$lane))),
2202 (SubReg_i32_lane imm:$lane))>;
2203 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
2204 (EXTRACT_SUBREG (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2),
2205 (SSubReg_f32_reg imm:$src2))>;
2206 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
2207 (EXTRACT_SUBREG (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2),
2208 (SSubReg_f32_reg imm:$src2))>;
2209 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
2210 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2211 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
2212 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2215 // VMOV : Vector Set Lane (move ARM core register to scalar)
2217 let Constraints = "$src1 = $dst" in {
2218 def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst),
2219 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2220 IIC_VMOVISL, "vmov", ".8\t$dst[$lane], $src2",
2221 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
2222 GPR:$src2, imm:$lane))]>;
2223 def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst),
2224 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2225 IIC_VMOVISL, "vmov", ".16\t$dst[$lane], $src2",
2226 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
2227 GPR:$src2, imm:$lane))]>;
2228 def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst),
2229 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2230 IIC_VMOVISL, "vmov", ".32\t$dst[$lane], $src2",
2231 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
2232 GPR:$src2, imm:$lane))]>;
2234 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
2235 (v16i8 (INSERT_SUBREG QPR:$src1,
2236 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
2237 (DSubReg_i8_reg imm:$lane))),
2238 GPR:$src2, (SubReg_i8_lane imm:$lane)),
2239 (DSubReg_i8_reg imm:$lane)))>;
2240 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
2241 (v8i16 (INSERT_SUBREG QPR:$src1,
2242 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
2243 (DSubReg_i16_reg imm:$lane))),
2244 GPR:$src2, (SubReg_i16_lane imm:$lane)),
2245 (DSubReg_i16_reg imm:$lane)))>;
2246 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
2247 (v4i32 (INSERT_SUBREG QPR:$src1,
2248 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
2249 (DSubReg_i32_reg imm:$lane))),
2250 GPR:$src2, (SubReg_i32_lane imm:$lane)),
2251 (DSubReg_i32_reg imm:$lane)))>;
2253 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
2254 (INSERT_SUBREG (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2),
2255 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
2256 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
2257 (INSERT_SUBREG (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2),
2258 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
2260 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
2261 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
2262 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
2263 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
2265 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
2266 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
2267 def : Pat<(v2f64 (scalar_to_vector DPR:$src)),
2268 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, arm_dsubreg_0)>;
2269 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
2270 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
2272 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
2273 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2274 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
2275 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2276 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
2277 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2279 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
2280 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
2281 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2283 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
2284 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
2285 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2287 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
2288 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
2289 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2292 // VDUP : Vector Duplicate (from ARM core register to all elements)
2294 class VDUPD<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
2295 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
2296 IIC_VMOVIS, "vdup", !strconcat(asmSize, "\t$dst, $src"),
2297 [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
2298 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
2299 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
2300 IIC_VMOVIS, "vdup", !strconcat(asmSize, "\t$dst, $src"),
2301 [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
2303 def VDUP8d : VDUPD<0b11101100, 0b00, ".8", v8i8>;
2304 def VDUP16d : VDUPD<0b11101000, 0b01, ".16", v4i16>;
2305 def VDUP32d : VDUPD<0b11101000, 0b00, ".32", v2i32>;
2306 def VDUP8q : VDUPQ<0b11101110, 0b00, ".8", v16i8>;
2307 def VDUP16q : VDUPQ<0b11101010, 0b01, ".16", v8i16>;
2308 def VDUP32q : VDUPQ<0b11101010, 0b00, ".32", v4i32>;
2310 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
2311 IIC_VMOVIS, "vdup", ".32\t$dst, $src",
2312 [(set DPR:$dst, (v2f32 (NEONvdup
2313 (f32 (bitconvert GPR:$src)))))]>;
2314 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
2315 IIC_VMOVIS, "vdup", ".32\t$dst, $src",
2316 [(set QPR:$dst, (v4f32 (NEONvdup
2317 (f32 (bitconvert GPR:$src)))))]>;
2319 // VDUP : Vector Duplicate Lane (from scalar to all elements)
2321 class VDUPLND<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty>
2322 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
2323 (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
2324 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
2325 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
2327 class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr,
2328 ValueType ResTy, ValueType OpTy>
2329 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
2330 (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
2331 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
2332 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src), imm:$lane)))]>;
2334 def VDUPLN8d : VDUPLND<0b00, 0b01, "vdup.8", v8i8>;
2335 def VDUPLN16d : VDUPLND<0b00, 0b10, "vdup.16", v4i16>;
2336 def VDUPLN32d : VDUPLND<0b01, 0b00, "vdup.32", v2i32>;
2337 def VDUPLNfd : VDUPLND<0b01, 0b00, "vdup.32", v2f32>;
2338 def VDUPLN8q : VDUPLNQ<0b00, 0b01, "vdup.8", v16i8, v8i8>;
2339 def VDUPLN16q : VDUPLNQ<0b00, 0b10, "vdup.16", v8i16, v4i16>;
2340 def VDUPLN32q : VDUPLNQ<0b01, 0b00, "vdup.32", v4i32, v2i32>;
2341 def VDUPLNfq : VDUPLNQ<0b01, 0b00, "vdup.32", v4f32, v2f32>;
2343 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
2344 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
2345 (DSubReg_i8_reg imm:$lane))),
2346 (SubReg_i8_lane imm:$lane)))>;
2347 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
2348 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
2349 (DSubReg_i16_reg imm:$lane))),
2350 (SubReg_i16_lane imm:$lane)))>;
2351 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
2352 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
2353 (DSubReg_i32_reg imm:$lane))),
2354 (SubReg_i32_lane imm:$lane)))>;
2355 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
2356 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
2357 (DSubReg_i32_reg imm:$lane))),
2358 (SubReg_i32_lane imm:$lane)))>;
2360 def VDUPfdf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 0, 0,
2361 (outs DPR:$dst), (ins SPR:$src),
2362 IIC_VMOVD, "vdup.32\t$dst, ${src:lane}", "",
2363 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
2365 def VDUPfqf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 1, 0,
2366 (outs QPR:$dst), (ins SPR:$src),
2367 IIC_VMOVD, "vdup.32\t$dst, ${src:lane}", "",
2368 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
2370 def : Pat<(v2i64 (NEONvduplane (v2i64 QPR:$src), imm:$lane)),
2371 (INSERT_SUBREG QPR:$src,
2372 (i64 (EXTRACT_SUBREG QPR:$src, (DSubReg_f64_reg imm:$lane))),
2373 (DSubReg_f64_other_reg imm:$lane))>;
2374 def : Pat<(v2f64 (NEONvduplane (v2f64 QPR:$src), imm:$lane)),
2375 (INSERT_SUBREG QPR:$src,
2376 (f64 (EXTRACT_SUBREG QPR:$src, (DSubReg_f64_reg imm:$lane))),
2377 (DSubReg_f64_other_reg imm:$lane))>;
2379 // VMOVN : Vector Narrowing Move
2380 defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVD, "vmovn.i",
2381 int_arm_neon_vmovn>;
2382 // VQMOVN : Vector Saturating Narrowing Move
2383 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD, "vqmovn.s",
2384 int_arm_neon_vqmovns>;
2385 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD, "vqmovn.u",
2386 int_arm_neon_vqmovnu>;
2387 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD, "vqmovun.s",
2388 int_arm_neon_vqmovnsu>;
2389 // VMOVL : Vector Lengthening Move
2390 defm VMOVLs : N2VLInt_QHS<0,1,0b1010,0,0,1, "vmovl.s", int_arm_neon_vmovls>;
2391 defm VMOVLu : N2VLInt_QHS<1,1,0b1010,0,0,1, "vmovl.u", int_arm_neon_vmovlu>;
2393 // Vector Conversions.
2395 // VCVT : Vector Convert Between Floating-Point and Integers
2396 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
2397 v2i32, v2f32, fp_to_sint>;
2398 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
2399 v2i32, v2f32, fp_to_uint>;
2400 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
2401 v2f32, v2i32, sint_to_fp>;
2402 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
2403 v2f32, v2i32, uint_to_fp>;
2405 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
2406 v4i32, v4f32, fp_to_sint>;
2407 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
2408 v4i32, v4f32, fp_to_uint>;
2409 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
2410 v4f32, v4i32, sint_to_fp>;
2411 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
2412 v4f32, v4i32, uint_to_fp>;
2414 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
2415 // Note: Some of the opcode bits in the following VCVT instructions need to
2416 // be encoded based on the immed values.
2417 def VCVTf2xsd : N2VCvtD<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
2418 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
2419 def VCVTf2xud : N2VCvtD<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
2420 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
2421 def VCVTxs2fd : N2VCvtD<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
2422 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
2423 def VCVTxu2fd : N2VCvtD<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
2424 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
2426 def VCVTf2xsq : N2VCvtQ<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
2427 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
2428 def VCVTf2xuq : N2VCvtQ<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
2429 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
2430 def VCVTxs2fq : N2VCvtQ<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
2431 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
2432 def VCVTxu2fq : N2VCvtQ<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
2433 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
2437 // VREV64 : Vector Reverse elements within 64-bit doublewords
2439 class VREV64D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2440 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
2441 (ins DPR:$src), IIC_VMOVD,
2442 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2443 [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
2444 class VREV64Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2445 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
2446 (ins QPR:$src), IIC_VMOVD,
2447 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2448 [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
2450 def VREV64d8 : VREV64D<0b00, "vrev64.8", v8i8>;
2451 def VREV64d16 : VREV64D<0b01, "vrev64.16", v4i16>;
2452 def VREV64d32 : VREV64D<0b10, "vrev64.32", v2i32>;
2453 def VREV64df : VREV64D<0b10, "vrev64.32", v2f32>;
2455 def VREV64q8 : VREV64Q<0b00, "vrev64.8", v16i8>;
2456 def VREV64q16 : VREV64Q<0b01, "vrev64.16", v8i16>;
2457 def VREV64q32 : VREV64Q<0b10, "vrev64.32", v4i32>;
2458 def VREV64qf : VREV64Q<0b10, "vrev64.32", v4f32>;
2460 // VREV32 : Vector Reverse elements within 32-bit words
2462 class VREV32D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2463 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
2464 (ins DPR:$src), IIC_VMOVD,
2465 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2466 [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
2467 class VREV32Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2468 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
2469 (ins QPR:$src), IIC_VMOVD,
2470 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2471 [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
2473 def VREV32d8 : VREV32D<0b00, "vrev32.8", v8i8>;
2474 def VREV32d16 : VREV32D<0b01, "vrev32.16", v4i16>;
2476 def VREV32q8 : VREV32Q<0b00, "vrev32.8", v16i8>;
2477 def VREV32q16 : VREV32Q<0b01, "vrev32.16", v8i16>;
2479 // VREV16 : Vector Reverse elements within 16-bit halfwords
2481 class VREV16D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2482 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
2483 (ins DPR:$src), IIC_VMOVD,
2484 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2485 [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
2486 class VREV16Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2487 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
2488 (ins QPR:$src), IIC_VMOVD,
2489 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2490 [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
2492 def VREV16d8 : VREV16D<0b00, "vrev16.8", v8i8>;
2493 def VREV16q8 : VREV16Q<0b00, "vrev16.8", v16i8>;
2495 // Other Vector Shuffles.
2497 // VEXT : Vector Extract
2499 class VEXTd<string OpcodeStr, ValueType Ty>
2500 : N3V<0,1,0b11,0b0000,0,0, (outs DPR:$dst),
2501 (ins DPR:$lhs, DPR:$rhs, i32imm:$index), IIC_VEXTD,
2502 !strconcat(OpcodeStr, "\t$dst, $lhs, $rhs, $index"), "",
2503 [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
2504 (Ty DPR:$rhs), imm:$index)))]>;
2506 class VEXTq<string OpcodeStr, ValueType Ty>
2507 : N3V<0,1,0b11,0b0000,1,0, (outs QPR:$dst),
2508 (ins QPR:$lhs, QPR:$rhs, i32imm:$index), IIC_VEXTQ,
2509 !strconcat(OpcodeStr, "\t$dst, $lhs, $rhs, $index"), "",
2510 [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
2511 (Ty QPR:$rhs), imm:$index)))]>;
2513 def VEXTd8 : VEXTd<"vext.8", v8i8>;
2514 def VEXTd16 : VEXTd<"vext.16", v4i16>;
2515 def VEXTd32 : VEXTd<"vext.32", v2i32>;
2516 def VEXTdf : VEXTd<"vext.32", v2f32>;
2518 def VEXTq8 : VEXTq<"vext.8", v16i8>;
2519 def VEXTq16 : VEXTq<"vext.16", v8i16>;
2520 def VEXTq32 : VEXTq<"vext.32", v4i32>;
2521 def VEXTqf : VEXTq<"vext.32", v4f32>;
2523 // VTRN : Vector Transpose
2525 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn.8">;
2526 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn.16">;
2527 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn.32">;
2529 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn.8">;
2530 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn.16">;
2531 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn.32">;
2533 // VUZP : Vector Unzip (Deinterleave)
2535 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp.8">;
2536 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp.16">;
2537 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp.32">;
2539 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp.8">;
2540 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp.16">;
2541 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp.32">;
2543 // VZIP : Vector Zip (Interleave)
2545 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip.8">;
2546 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip.16">;
2547 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip.32">;
2549 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip.8">;
2550 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip.16">;
2551 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip.32">;
2553 // Vector Table Lookup and Table Extension.
2555 // VTBL : Vector Table Lookup
2557 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
2558 (ins DPR:$tbl1, DPR:$src), IIC_VTB1,
2559 "vtbl.8\t$dst, \\{$tbl1\\}, $src", "",
2560 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
2561 let hasExtraSrcRegAllocReq = 1 in {
2563 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
2564 (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTB2,
2565 "vtbl.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "",
2566 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl2
2567 DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
2569 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
2570 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTB3,
2571 "vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "",
2572 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl3
2573 DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
2575 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
2576 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTB4,
2577 "vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "",
2578 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl4 DPR:$tbl1, DPR:$tbl2,
2579 DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
2580 } // hasExtraSrcRegAllocReq = 1
2582 // VTBX : Vector Table Extension
2584 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
2585 (ins DPR:$orig, DPR:$tbl1, DPR:$src), IIC_VTBX1,
2586 "vtbx.8\t$dst, \\{$tbl1\\}, $src", "$orig = $dst",
2587 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
2588 DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
2589 let hasExtraSrcRegAllocReq = 1 in {
2591 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
2592 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTBX2,
2593 "vtbx.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "$orig = $dst",
2594 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx2
2595 DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
2597 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
2598 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTBX3,
2599 "vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "$orig = $dst",
2600 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx3 DPR:$orig, DPR:$tbl1,
2601 DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
2603 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
2604 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTBX4,
2605 "vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "$orig = $dst",
2606 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx4 DPR:$orig, DPR:$tbl1,
2607 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
2608 } // hasExtraSrcRegAllocReq = 1
2610 //===----------------------------------------------------------------------===//
2611 // NEON instructions for single-precision FP math
2612 //===----------------------------------------------------------------------===//
2614 // These need separate instructions because they must use DPR_VFP2 register
2615 // class which have SPR sub-registers.
2617 // Vector Add Operations used for single-precision FP
2618 let neverHasSideEffects = 1 in
2619 def VADDfd_sfp : N3VDs<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd,1>;
2620 def : N3VDsPat<fadd, VADDfd_sfp>;
2622 // Vector Sub Operations used for single-precision FP
2623 let neverHasSideEffects = 1 in
2624 def VSUBfd_sfp : N3VDs<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub,0>;
2625 def : N3VDsPat<fsub, VSUBfd_sfp>;
2627 // Vector Multiply Operations used for single-precision FP
2628 let neverHasSideEffects = 1 in
2629 def VMULfd_sfp : N3VDs<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul,1>;
2630 def : N3VDsPat<fmul, VMULfd_sfp>;
2632 // Vector Multiply-Accumulate/Subtract used for single-precision FP
2633 let neverHasSideEffects = 1 in
2634 def VMLAfd_sfp : N3VDMulOps<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla.f32", v2f32,fmul,fadd>;
2635 def : N3VDMulOpsPat<fmul, fadd, VMLAfd_sfp>;
2637 let neverHasSideEffects = 1 in
2638 def VMLSfd_sfp : N3VDMulOps<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls.f32", v2f32,fmul,fsub>;
2639 def : N3VDMulOpsPat<fmul, fsub, VMLSfd_sfp>;
2641 // Vector Absolute used for single-precision FP
2642 let neverHasSideEffects = 1 in
2643 def VABSfd_sfp : N2VDInts<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2644 IIC_VUNAD, "vabs.f32",
2645 v2f32, v2f32, int_arm_neon_vabs>;
2646 def : N2VDIntsPat<fabs, VABSfd_sfp>;
2648 // Vector Negate used for single-precision FP
2649 let neverHasSideEffects = 1 in
2650 def VNEGf32d_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
2651 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
2652 "vneg.f32\t$dst, $src", "", []>;
2653 def : N2VDIntsPat<fneg, VNEGf32d_sfp>;
2655 // Vector Convert between single-precision FP and integer
2656 let neverHasSideEffects = 1 in
2657 def VCVTf2sd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
2658 v2i32, v2f32, fp_to_sint>;
2659 def : N2VDsPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
2661 let neverHasSideEffects = 1 in
2662 def VCVTf2ud_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
2663 v2i32, v2f32, fp_to_uint>;
2664 def : N2VDsPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
2666 let neverHasSideEffects = 1 in
2667 def VCVTs2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
2668 v2f32, v2i32, sint_to_fp>;
2669 def : N2VDsPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
2671 let neverHasSideEffects = 1 in
2672 def VCVTu2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
2673 v2f32, v2i32, uint_to_fp>;
2674 def : N2VDsPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
2676 //===----------------------------------------------------------------------===//
2677 // Non-Instruction Patterns
2678 //===----------------------------------------------------------------------===//
2681 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
2682 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
2683 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
2684 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
2685 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
2686 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
2687 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
2688 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
2689 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
2690 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
2691 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
2692 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
2693 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
2694 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
2695 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
2696 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
2697 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
2698 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
2699 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
2700 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
2701 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
2702 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
2703 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
2704 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
2705 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
2706 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
2707 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
2708 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
2709 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
2710 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
2712 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
2713 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
2714 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
2715 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
2716 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
2717 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
2718 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
2719 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
2720 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
2721 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
2722 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
2723 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
2724 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
2725 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
2726 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
2727 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
2728 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
2729 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
2730 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
2731 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
2732 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
2733 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
2734 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
2735 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
2736 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
2737 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
2738 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
2739 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
2740 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
2741 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;