1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
70 // VDUPLANE can produce a quad-register result from a double-register source,
71 // so the result is not constrained to match the source.
72 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
73 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
76 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
77 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
78 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
80 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
81 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
82 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
83 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
85 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
86 SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>]>;
87 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
88 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
89 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
91 //===----------------------------------------------------------------------===//
92 // NEON operand definitions
93 //===----------------------------------------------------------------------===//
95 // addrmode_neonldstm := reg
97 /* TODO: Take advantage of vldm.
98 def addrmode_neonldstm : Operand<i32>,
99 ComplexPattern<i32, 2, "SelectAddrModeNeonLdStM", []> {
100 let PrintMethod = "printAddrNeonLdStMOperand";
101 let MIOperandInfo = (ops GPR, i32imm);
105 //===----------------------------------------------------------------------===//
106 // NEON load / store instructions
107 //===----------------------------------------------------------------------===//
109 /* TODO: Take advantage of vldm.
110 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
111 def VLDMD : NI<(outs),
112 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
114 "vldm${addr:submode} ${addr:base}, $dst1",
116 let Inst{27-25} = 0b110;
118 let Inst{11-9} = 0b101;
121 def VLDMS : NI<(outs),
122 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
124 "vldm${addr:submode} ${addr:base}, $dst1",
126 let Inst{27-25} = 0b110;
128 let Inst{11-9} = 0b101;
133 // Use vldmia to load a Q register as a D register pair.
134 def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr),
136 "vldmia $addr, ${dst:dregpair}",
137 [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]> {
138 let Inst{27-25} = 0b110;
139 let Inst{24} = 0; // P bit
140 let Inst{23} = 1; // U bit
142 let Inst{11-9} = 0b101;
145 // Use vstmia to store a Q register as a D register pair.
146 def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr),
148 "vstmia $addr, ${src:dregpair}",
149 [(store (v2f64 QPR:$src), addrmode4:$addr)]> {
150 let Inst{27-25} = 0b110;
151 let Inst{24} = 0; // P bit
152 let Inst{23} = 1; // U bit
154 let Inst{11-9} = 0b101;
157 // VLD1 : Vector Load (multiple single elements)
158 class VLD1D<bits<4> op7_4, string OpcodeStr, ValueType Ty, Intrinsic IntOp>
159 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst), (ins addrmode6:$addr), IIC_VLD1,
160 !strconcat(OpcodeStr, "\t\\{$dst\\}, $addr"), "",
161 [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
162 class VLD1Q<bits<4> op7_4, string OpcodeStr, ValueType Ty, Intrinsic IntOp>
163 : NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst), (ins addrmode6:$addr), IIC_VLD1,
164 !strconcat(OpcodeStr, "\t${dst:dregpair}, $addr"), "",
165 [(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
167 def VLD1d8 : VLD1D<0b0000, "vld1.8", v8i8, int_arm_neon_vld1>;
168 def VLD1d16 : VLD1D<0b0100, "vld1.16", v4i16, int_arm_neon_vld1>;
169 def VLD1d32 : VLD1D<0b1000, "vld1.32", v2i32, int_arm_neon_vld1>;
170 def VLD1df : VLD1D<0b1000, "vld1.32", v2f32, int_arm_neon_vld1>;
171 def VLD1d64 : VLD1D<0b1100, "vld1.64", v1i64, int_arm_neon_vld1>;
173 def VLD1q8 : VLD1Q<0b0000, "vld1.8", v16i8, int_arm_neon_vld1>;
174 def VLD1q16 : VLD1Q<0b0100, "vld1.16", v8i16, int_arm_neon_vld1>;
175 def VLD1q32 : VLD1Q<0b1000, "vld1.32", v4i32, int_arm_neon_vld1>;
176 def VLD1qf : VLD1Q<0b1000, "vld1.32", v4f32, int_arm_neon_vld1>;
177 def VLD1q64 : VLD1Q<0b1100, "vld1.64", v2i64, int_arm_neon_vld1>;
179 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
181 // VLD2 : Vector Load (multiple 2-element structures)
182 class VLD2D<bits<4> op7_4, string OpcodeStr>
183 : NLdSt<0,0b10,0b1000,op7_4, (outs DPR:$dst1, DPR:$dst2),
184 (ins addrmode6:$addr), IIC_VLD2,
185 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2\\}, $addr"), "", []>;
186 class VLD2Q<bits<4> op7_4, string OpcodeStr>
187 : NLdSt<0,0b10,0b0011,op7_4,
188 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
189 (ins addrmode6:$addr), IIC_VLD2,
190 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"),
193 def VLD2d8 : VLD2D<0b0000, "vld2.8">;
194 def VLD2d16 : VLD2D<0b0100, "vld2.16">;
195 def VLD2d32 : VLD2D<0b1000, "vld2.32">;
196 def VLD2d64 : NLdSt<0,0b10,0b1010,0b1100, (outs DPR:$dst1, DPR:$dst2),
197 (ins addrmode6:$addr), IIC_VLD1,
198 "vld1.64\t\\{$dst1,$dst2\\}, $addr", "", []>;
200 def VLD2q8 : VLD2Q<0b0000, "vld2.8">;
201 def VLD2q16 : VLD2Q<0b0100, "vld2.16">;
202 def VLD2q32 : VLD2Q<0b1000, "vld2.32">;
204 // VLD3 : Vector Load (multiple 3-element structures)
205 class VLD3D<bits<4> op7_4, string OpcodeStr>
206 : NLdSt<0,0b10,0b0100,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
207 (ins addrmode6:$addr), IIC_VLD3,
208 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"), "", []>;
209 class VLD3WB<bits<4> op7_4, string OpcodeStr>
210 : NLdSt<0,0b10,0b0101,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
211 (ins addrmode6:$addr), IIC_VLD3,
212 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"),
213 "$addr.addr = $wb", []>;
215 def VLD3d8 : VLD3D<0b0000, "vld3.8">;
216 def VLD3d16 : VLD3D<0b0100, "vld3.16">;
217 def VLD3d32 : VLD3D<0b1000, "vld3.32">;
219 // vld3 to double-spaced even registers.
220 def VLD3q8a : VLD3WB<0b0000, "vld3.8">;
221 def VLD3q16a : VLD3WB<0b0100, "vld3.16">;
222 def VLD3q32a : VLD3WB<0b1000, "vld3.32">;
224 // vld3 to double-spaced odd registers.
225 def VLD3q8b : VLD3WB<0b0000, "vld3.8">;
226 def VLD3q16b : VLD3WB<0b0100, "vld3.16">;
227 def VLD3q32b : VLD3WB<0b1000, "vld3.32">;
229 // VLD4 : Vector Load (multiple 4-element structures)
230 class VLD4D<bits<4> op7_4, string OpcodeStr>
231 : NLdSt<0,0b10,0b0000,op7_4,
232 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
233 (ins addrmode6:$addr), IIC_VLD4,
234 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"),
236 class VLD4WB<bits<4> op7_4, string OpcodeStr>
237 : NLdSt<0,0b10,0b0001,op7_4,
238 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
239 (ins addrmode6:$addr), IIC_VLD4,
240 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"),
241 "$addr.addr = $wb", []>;
243 def VLD4d8 : VLD4D<0b0000, "vld4.8">;
244 def VLD4d16 : VLD4D<0b0100, "vld4.16">;
245 def VLD4d32 : VLD4D<0b1000, "vld4.32">;
247 // vld4 to double-spaced even registers.
248 def VLD4q8a : VLD4WB<0b0000, "vld4.8">;
249 def VLD4q16a : VLD4WB<0b0100, "vld4.16">;
250 def VLD4q32a : VLD4WB<0b1000, "vld4.32">;
252 // vld4 to double-spaced odd registers.
253 def VLD4q8b : VLD4WB<0b0000, "vld4.8">;
254 def VLD4q16b : VLD4WB<0b0100, "vld4.16">;
255 def VLD4q32b : VLD4WB<0b1000, "vld4.32">;
257 // VLD1LN : Vector Load (single element to one lane)
258 // FIXME: Not yet implemented.
260 // VLD2LN : Vector Load (single 2-element structure to one lane)
261 class VLD2LND<bits<4> op11_8, string OpcodeStr>
262 : NLdSt<1,0b10,op11_8,0b0000, (outs DPR:$dst1, DPR:$dst2),
263 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
265 !strconcat(OpcodeStr, "\t\\{$dst1[$lane],$dst2[$lane]\\}, $addr"),
266 "$src1 = $dst1, $src2 = $dst2", []>;
268 def VLD2LNd8 : VLD2LND<0b0001, "vld2.8">;
269 def VLD2LNd16 : VLD2LND<0b0101, "vld2.16">;
270 def VLD2LNd32 : VLD2LND<0b1001, "vld2.32">;
272 // VLD3LN : Vector Load (single 3-element structure to one lane)
273 class VLD3LND<bits<4> op11_8, string OpcodeStr>
274 : NLdSt<1,0b10,op11_8,0b0000, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
275 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
276 nohash_imm:$lane), IIC_VLD3,
277 !strconcat(OpcodeStr,
278 "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane]\\}, $addr"),
279 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
281 def VLD3LNd8 : VLD3LND<0b0010, "vld3.8">;
282 def VLD3LNd16 : VLD3LND<0b0110, "vld3.16">;
283 def VLD3LNd32 : VLD3LND<0b1010, "vld3.32">;
285 // VLD4LN : Vector Load (single 4-element structure to one lane)
286 class VLD4LND<bits<4> op11_8, string OpcodeStr>
287 : NLdSt<1,0b10,op11_8,0b0000,
288 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
289 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
290 nohash_imm:$lane), IIC_VLD4,
291 !strconcat(OpcodeStr,
292 "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane],$dst4[$lane]\\}, $addr"),
293 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
295 def VLD4LNd8 : VLD4LND<0b0011, "vld4.8">;
296 def VLD4LNd16 : VLD4LND<0b0111, "vld4.16">;
297 def VLD4LNd32 : VLD4LND<0b1011, "vld4.32">;
299 // VLD1DUP : Vector Load (single element to all lanes)
300 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
301 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
302 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
303 // FIXME: Not yet implemented.
304 } // mayLoad = 1, hasExtraDefRegAllocReq = 1
306 // VST1 : Vector Store (multiple single elements)
307 class VST1D<bits<4> op7_4, string OpcodeStr, ValueType Ty, Intrinsic IntOp>
308 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src), IIC_VST,
309 !strconcat(OpcodeStr, "\t\\{$src\\}, $addr"), "",
310 [(IntOp addrmode6:$addr, (Ty DPR:$src))]>;
311 class VST1Q<bits<4> op7_4, string OpcodeStr, ValueType Ty, Intrinsic IntOp>
312 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$addr, QPR:$src), IIC_VST,
313 !strconcat(OpcodeStr, "\t${src:dregpair}, $addr"), "",
314 [(IntOp addrmode6:$addr, (Ty QPR:$src))]>;
316 let hasExtraSrcRegAllocReq = 1 in {
317 def VST1d8 : VST1D<0b0000, "vst1.8", v8i8, int_arm_neon_vst1>;
318 def VST1d16 : VST1D<0b0100, "vst1.16", v4i16, int_arm_neon_vst1>;
319 def VST1d32 : VST1D<0b1000, "vst1.32", v2i32, int_arm_neon_vst1>;
320 def VST1df : VST1D<0b1000, "vst1.32", v2f32, int_arm_neon_vst1>;
321 def VST1d64 : VST1D<0b1100, "vst1.64", v1i64, int_arm_neon_vst1>;
323 def VST1q8 : VST1Q<0b0000, "vst1.8", v16i8, int_arm_neon_vst1>;
324 def VST1q16 : VST1Q<0b0100, "vst1.16", v8i16, int_arm_neon_vst1>;
325 def VST1q32 : VST1Q<0b1000, "vst1.32", v4i32, int_arm_neon_vst1>;
326 def VST1qf : VST1Q<0b1000, "vst1.32", v4f32, int_arm_neon_vst1>;
327 def VST1q64 : VST1Q<0b1100, "vst1.64", v2i64, int_arm_neon_vst1>;
328 } // hasExtraSrcRegAllocReq
330 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
332 // VST2 : Vector Store (multiple 2-element structures)
333 class VST2D<bits<4> op7_4, string OpcodeStr>
334 : NLdSt<0,0b00,0b1000,op7_4, (outs),
335 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
336 !strconcat(OpcodeStr, "\t\\{$src1,$src2\\}, $addr"), "", []>;
337 class VST2Q<bits<4> op7_4, string OpcodeStr>
338 : NLdSt<0,0b00,0b0011,op7_4, (outs),
339 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
341 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"),
344 def VST2d8 : VST2D<0b0000, "vst2.8">;
345 def VST2d16 : VST2D<0b0100, "vst2.16">;
346 def VST2d32 : VST2D<0b1000, "vst2.32">;
348 def VST2q8 : VST2Q<0b0000, "vst2.8">;
349 def VST2q16 : VST2Q<0b0100, "vst2.16">;
350 def VST2q32 : VST2Q<0b1000, "vst2.32">;
352 // VST3 : Vector Store (multiple 3-element structures)
353 class VST3D<bits<4> op7_4, string OpcodeStr>
354 : NLdSt<0,0b00,0b0100,op7_4, (outs),
355 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
356 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"), "", []>;
357 class VST3WB<bits<4> op7_4, string OpcodeStr>
358 : NLdSt<0,0b00,0b0101,op7_4, (outs GPR:$wb),
359 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
360 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"),
361 "$addr.addr = $wb", []>;
363 def VST3d8 : VST3D<0b0000, "vst3.8">;
364 def VST3d16 : VST3D<0b0100, "vst3.16">;
365 def VST3d32 : VST3D<0b1000, "vst3.32">;
367 // vst3 to double-spaced even registers.
368 def VST3q8a : VST3WB<0b0000, "vst3.8">;
369 def VST3q16a : VST3WB<0b0100, "vst3.16">;
370 def VST3q32a : VST3WB<0b1000, "vst3.32">;
372 // vst3 to double-spaced odd registers.
373 def VST3q8b : VST3WB<0b0000, "vst3.8">;
374 def VST3q16b : VST3WB<0b0100, "vst3.16">;
375 def VST3q32b : VST3WB<0b1000, "vst3.32">;
377 // VST4 : Vector Store (multiple 4-element structures)
378 class VST4D<bits<4> op7_4, string OpcodeStr>
379 : NLdSt<0,0b00,0b0000,op7_4, (outs),
380 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
382 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"),
384 class VST4WB<bits<4> op7_4, string OpcodeStr>
385 : NLdSt<0,0b00,0b0001,op7_4, (outs GPR:$wb),
386 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
388 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"),
389 "$addr.addr = $wb", []>;
391 def VST4d8 : VST4D<0b0000, "vst4.8">;
392 def VST4d16 : VST4D<0b0100, "vst4.16">;
393 def VST4d32 : VST4D<0b1000, "vst4.32">;
395 // vst4 to double-spaced even registers.
396 def VST4q8a : VST4WB<0b0000, "vst4.8">;
397 def VST4q16a : VST4WB<0b0100, "vst4.16">;
398 def VST4q32a : VST4WB<0b1000, "vst4.32">;
400 // vst4 to double-spaced odd registers.
401 def VST4q8b : VST4WB<0b0000, "vst4.8">;
402 def VST4q16b : VST4WB<0b0100, "vst4.16">;
403 def VST4q32b : VST4WB<0b1000, "vst4.32">;
405 // VST1LN : Vector Store (single element from one lane)
406 // FIXME: Not yet implemented.
408 // VST2LN : Vector Store (single 2-element structure from one lane)
409 class VST2LND<bits<4> op11_8, string OpcodeStr>
410 : NLdSt<1,0b00,op11_8,0b0000, (outs),
411 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
413 !strconcat(OpcodeStr, "\t\\{$src1[$lane],$src2[$lane]\\}, $addr"),
416 def VST2LNd8 : VST2LND<0b0000, "vst2.8">;
417 def VST2LNd16 : VST2LND<0b0100, "vst2.16">;
418 def VST2LNd32 : VST2LND<0b1000, "vst2.32">;
420 // VST3LN : Vector Store (single 3-element structure from one lane)
421 class VST3LND<bits<4> op11_8, string OpcodeStr>
422 : NLdSt<1,0b00,op11_8,0b0000, (outs),
423 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
424 nohash_imm:$lane), IIC_VST,
425 !strconcat(OpcodeStr,
426 "\t\\{$src1[$lane],$src2[$lane],$src3[$lane]\\}, $addr"), "", []>;
428 def VST3LNd8 : VST3LND<0b0010, "vst3.8">;
429 def VST3LNd16 : VST3LND<0b0110, "vst3.16">;
430 def VST3LNd32 : VST3LND<0b1010, "vst3.32">;
432 // VST4LN : Vector Store (single 4-element structure from one lane)
433 class VST4LND<bits<4> op11_8, string OpcodeStr>
434 : NLdSt<1,0b00,op11_8,0b0000, (outs),
435 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
436 nohash_imm:$lane), IIC_VST,
437 !strconcat(OpcodeStr,
438 "\t\\{$src1[$lane],$src2[$lane],$src3[$lane],$src4[$lane]\\}, $addr"),
441 def VST4LNd8 : VST4LND<0b0011, "vst4.8">;
442 def VST4LNd16 : VST4LND<0b0111, "vst4.16">;
443 def VST4LNd32 : VST4LND<0b1011, "vst4.32">;
444 } // mayStore = 1, hasExtraSrcRegAllocReq = 1
447 //===----------------------------------------------------------------------===//
448 // NEON pattern fragments
449 //===----------------------------------------------------------------------===//
451 // Extract D sub-registers of Q registers.
452 // (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
453 def DSubReg_i8_reg : SDNodeXForm<imm, [{
454 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
456 def DSubReg_i16_reg : SDNodeXForm<imm, [{
457 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
459 def DSubReg_i32_reg : SDNodeXForm<imm, [{
460 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
462 def DSubReg_f64_reg : SDNodeXForm<imm, [{
463 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
465 def DSubReg_f64_other_reg : SDNodeXForm<imm, [{
466 return CurDAG->getTargetConstant(5 + (1 - N->getZExtValue()), MVT::i32);
469 // Extract S sub-registers of Q/D registers.
470 // (arm_ssubreg_0 is 1; arm_ssubreg_1 is 2; etc.)
471 def SSubReg_f32_reg : SDNodeXForm<imm, [{
472 return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32);
475 // Translate lane numbers from Q registers to D subregs.
476 def SubReg_i8_lane : SDNodeXForm<imm, [{
477 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
479 def SubReg_i16_lane : SDNodeXForm<imm, [{
480 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
482 def SubReg_i32_lane : SDNodeXForm<imm, [{
483 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
486 //===----------------------------------------------------------------------===//
487 // Instruction Classes
488 //===----------------------------------------------------------------------===//
490 // Basic 2-register operations, both double- and quad-register.
491 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
492 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
493 ValueType ResTy, ValueType OpTy, SDNode OpNode>
494 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
495 (ins DPR:$src), IIC_VUNAD, !strconcat(OpcodeStr, "\t$dst, $src"), "",
496 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
497 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
498 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
499 ValueType ResTy, ValueType OpTy, SDNode OpNode>
500 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
501 (ins QPR:$src), IIC_VUNAQ, !strconcat(OpcodeStr, "\t$dst, $src"), "",
502 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
504 // Basic 2-register operations, scalar single-precision.
505 class N2VDs<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
506 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
507 ValueType ResTy, ValueType OpTy, SDNode OpNode>
508 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
509 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
510 IIC_VUNAD, !strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
512 class N2VDsPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
513 : NEONFPPat<(ResTy (OpNode SPR:$a)),
515 (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
518 // Basic 2-register intrinsics, both double- and quad-register.
519 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
520 bits<2> op17_16, bits<5> op11_7, bit op4,
521 InstrItinClass itin, string OpcodeStr,
522 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
523 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
524 (ins DPR:$src), itin, !strconcat(OpcodeStr, "\t$dst, $src"), "",
525 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
526 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
527 bits<2> op17_16, bits<5> op11_7, bit op4,
528 InstrItinClass itin, string OpcodeStr,
529 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
530 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
531 (ins QPR:$src), itin, !strconcat(OpcodeStr, "\t$dst, $src"), "",
532 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
534 // Basic 2-register intrinsics, scalar single-precision
535 class N2VDInts<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
536 bits<2> op17_16, bits<5> op11_7, bit op4,
537 InstrItinClass itin, string OpcodeStr,
538 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
539 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
540 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), itin,
541 !strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
543 class N2VDIntsPat<SDNode OpNode, NeonI Inst>
544 : NEONFPPat<(f32 (OpNode SPR:$a)),
546 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
549 // Narrow 2-register intrinsics.
550 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
551 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
552 InstrItinClass itin, string OpcodeStr,
553 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
554 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
555 (ins QPR:$src), itin, !strconcat(OpcodeStr, "\t$dst, $src"), "",
556 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
558 // Long 2-register intrinsics. (This is currently only used for VMOVL and is
559 // derived from N2VImm instead of N2V because of the way the size is encoded.)
560 class N2VLInt<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
561 bit op6, bit op4, InstrItinClass itin, string OpcodeStr,
562 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
563 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4, (outs QPR:$dst),
564 (ins DPR:$src), itin, !strconcat(OpcodeStr, "\t$dst, $src"), "",
565 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
567 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
568 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr>
569 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
570 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
571 !strconcat(OpcodeStr, "\t$dst1, $dst2"),
572 "$src1 = $dst1, $src2 = $dst2", []>;
573 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
574 InstrItinClass itin, string OpcodeStr>
575 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
576 (ins QPR:$src1, QPR:$src2), itin,
577 !strconcat(OpcodeStr, "\t$dst1, $dst2"),
578 "$src1 = $dst1, $src2 = $dst2", []>;
580 // Basic 3-register operations, both double- and quad-register.
581 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
582 InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy,
583 SDNode OpNode, bit Commutable>
584 : N3V<op24, op23, op21_20, op11_8, 0, op4,
585 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
586 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
587 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
588 let isCommutable = Commutable;
590 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
591 InstrItinClass itin, string OpcodeStr, ValueType Ty, SDNode ShOp>
592 : N3V<0, 1, op21_20, op11_8, 1, 0,
593 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
594 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
596 (Ty (ShOp (Ty DPR:$src1),
597 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
599 let isCommutable = 0;
601 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
602 string OpcodeStr, ValueType Ty, SDNode ShOp>
603 : N3V<0, 1, op21_20, op11_8, 1, 0,
604 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
606 !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
608 (Ty (ShOp (Ty DPR:$src1),
609 (Ty (NEONvduplane (Ty DPR_8:$src2),
611 let isCommutable = 0;
614 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
615 InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy,
616 SDNode OpNode, bit Commutable>
617 : N3V<op24, op23, op21_20, op11_8, 1, op4,
618 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
619 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
620 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
621 let isCommutable = Commutable;
623 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
624 InstrItinClass itin, string OpcodeStr,
625 ValueType ResTy, ValueType OpTy, SDNode ShOp>
626 : N3V<1, 1, op21_20, op11_8, 1, 0,
627 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
628 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
629 [(set (ResTy QPR:$dst),
630 (ResTy (ShOp (ResTy QPR:$src1),
631 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
633 let isCommutable = 0;
635 class N3VQSL16<bits<2> op21_20, bits<4> op11_8,
636 string OpcodeStr, ValueType ResTy, ValueType OpTy, SDNode ShOp>
637 : N3V<1, 1, op21_20, op11_8, 1, 0,
638 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
640 !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
641 [(set (ResTy QPR:$dst),
642 (ResTy (ShOp (ResTy QPR:$src1),
643 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
645 let isCommutable = 0;
648 // Basic 3-register operations, scalar single-precision
649 class N3VDs<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
650 string OpcodeStr, ValueType ResTy, ValueType OpTy,
651 SDNode OpNode, bit Commutable>
652 : N3V<op24, op23, op21_20, op11_8, 0, op4,
653 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), IIC_VBIND,
654 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", []> {
655 let isCommutable = Commutable;
657 class N3VDsPat<SDNode OpNode, NeonI Inst>
658 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
660 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
661 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
664 // Basic 3-register intrinsics, both double- and quad-register.
665 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
666 InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy,
667 Intrinsic IntOp, bit Commutable>
668 : N3V<op24, op23, op21_20, op11_8, 0, op4,
669 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
670 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
671 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
672 let isCommutable = Commutable;
674 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
675 string OpcodeStr, ValueType Ty, Intrinsic IntOp>
676 : N3V<0, 1, op21_20, op11_8, 1, 0,
677 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
678 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
680 (Ty (IntOp (Ty DPR:$src1),
681 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
683 let isCommutable = 0;
685 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
686 string OpcodeStr, ValueType Ty, Intrinsic IntOp>
687 : N3V<0, 1, op21_20, op11_8, 1, 0,
688 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
689 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
691 (Ty (IntOp (Ty DPR:$src1),
692 (Ty (NEONvduplane (Ty DPR_8:$src2),
694 let isCommutable = 0;
697 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
698 InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy,
699 Intrinsic IntOp, bit Commutable>
700 : N3V<op24, op23, op21_20, op11_8, 1, op4,
701 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
702 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
703 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
704 let isCommutable = Commutable;
706 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
707 string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
708 : N3V<1, 1, op21_20, op11_8, 1, 0,
709 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
710 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
711 [(set (ResTy QPR:$dst),
712 (ResTy (IntOp (ResTy QPR:$src1),
713 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
715 let isCommutable = 0;
717 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
718 string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
719 : N3V<1, 1, op21_20, op11_8, 1, 0,
720 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
721 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
722 [(set (ResTy QPR:$dst),
723 (ResTy (IntOp (ResTy QPR:$src1),
724 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
726 let isCommutable = 0;
729 // Multiply-Add/Sub operations, both double- and quad-register.
730 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
731 InstrItinClass itin, string OpcodeStr,
732 ValueType Ty, SDNode MulOp, SDNode OpNode>
733 : N3V<op24, op23, op21_20, op11_8, 0, op4,
734 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin,
735 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
736 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
737 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
738 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
739 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode ShOp>
740 : N3V<0, 1, op21_20, op11_8, 1, 0,
742 (ins DPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
743 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
745 (Ty (ShOp (Ty DPR:$src1),
746 (Ty (MulOp DPR:$src2,
747 (Ty (NEONvduplane (Ty DPR_VFP2:$src3),
749 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
750 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode ShOp>
751 : N3V<0, 1, op21_20, op11_8, 1, 0,
753 (ins DPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
754 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
756 (Ty (ShOp (Ty DPR:$src1),
757 (Ty (MulOp DPR:$src2,
758 (Ty (NEONvduplane (Ty DPR_8:$src3),
761 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
762 InstrItinClass itin, string OpcodeStr, ValueType Ty,
763 SDNode MulOp, SDNode OpNode>
764 : N3V<op24, op23, op21_20, op11_8, 1, op4,
765 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin,
766 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
767 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
768 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
769 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
770 string OpcodeStr, ValueType ResTy, ValueType OpTy,
771 SDNode MulOp, SDNode ShOp>
772 : N3V<1, 1, op21_20, op11_8, 1, 0,
774 (ins QPR:$src1, QPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
775 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
776 [(set (ResTy QPR:$dst),
777 (ResTy (ShOp (ResTy QPR:$src1),
778 (ResTy (MulOp QPR:$src2,
779 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src3),
781 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
782 string OpcodeStr, ValueType ResTy, ValueType OpTy,
783 SDNode MulOp, SDNode ShOp>
784 : N3V<1, 1, op21_20, op11_8, 1, 0,
786 (ins QPR:$src1, QPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
787 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
788 [(set (ResTy QPR:$dst),
789 (ResTy (ShOp (ResTy QPR:$src1),
790 (ResTy (MulOp QPR:$src2,
791 (ResTy (NEONvduplane (OpTy DPR_8:$src3),
794 // Multiply-Add/Sub operations, scalar single-precision
795 class N3VDMulOps<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
796 InstrItinClass itin, string OpcodeStr,
797 ValueType Ty, SDNode MulOp, SDNode OpNode>
798 : N3V<op24, op23, op21_20, op11_8, 0, op4,
799 (outs DPR_VFP2:$dst),
800 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), itin,
801 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", []>;
803 class N3VDMulOpsPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
804 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
806 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$acc, arm_ssubreg_0),
807 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
808 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
811 // Neon 3-argument intrinsics, both double- and quad-register.
812 // The destination register is also used as the first source operand register.
813 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
814 InstrItinClass itin, string OpcodeStr,
815 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
816 : N3V<op24, op23, op21_20, op11_8, 0, op4,
817 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin,
818 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
819 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
820 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
821 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
822 InstrItinClass itin, string OpcodeStr,
823 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
824 : N3V<op24, op23, op21_20, op11_8, 1, op4,
825 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin,
826 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
827 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
828 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
830 // Neon Long 3-argument intrinsic. The destination register is
831 // a quad-register and is also used as the first source operand register.
832 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
833 InstrItinClass itin, string OpcodeStr,
834 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
835 : N3V<op24, op23, op21_20, op11_8, 0, op4,
836 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), itin,
837 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
839 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
840 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
841 string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
842 : N3V<op24, 1, op21_20, op11_8, 1, 0,
844 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
845 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
846 [(set (ResTy QPR:$dst),
847 (ResTy (IntOp (ResTy QPR:$src1),
849 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src3),
851 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
852 string OpcodeStr, ValueType ResTy, ValueType OpTy,
854 : N3V<op24, 1, op21_20, op11_8, 1, 0,
856 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
857 !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
858 [(set (ResTy QPR:$dst),
859 (ResTy (IntOp (ResTy QPR:$src1),
861 (OpTy (NEONvduplane (OpTy DPR_8:$src3),
865 // Narrowing 3-register intrinsics.
866 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
867 string OpcodeStr, ValueType TyD, ValueType TyQ,
868 Intrinsic IntOp, bit Commutable>
869 : N3V<op24, op23, op21_20, op11_8, 0, op4,
870 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VBINi4D,
871 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
872 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
873 let isCommutable = Commutable;
876 // Long 3-register intrinsics.
877 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
878 InstrItinClass itin, string OpcodeStr, ValueType TyQ, ValueType TyD,
879 Intrinsic IntOp, bit Commutable>
880 : N3V<op24, op23, op21_20, op11_8, 0, op4,
881 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
882 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
883 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
884 let isCommutable = Commutable;
886 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
887 string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
888 : N3V<op24, 1, op21_20, op11_8, 1, 0,
889 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
890 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
891 [(set (ResTy QPR:$dst),
892 (ResTy (IntOp (OpTy DPR:$src1),
893 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src2),
895 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
896 string OpcodeStr, ValueType ResTy, ValueType OpTy,
898 : N3V<op24, 1, op21_20, op11_8, 1, 0,
899 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
900 itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
901 [(set (ResTy QPR:$dst),
902 (ResTy (IntOp (OpTy DPR:$src1),
903 (OpTy (NEONvduplane (OpTy DPR_8:$src2),
906 // Wide 3-register intrinsics.
907 class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
908 string OpcodeStr, ValueType TyQ, ValueType TyD,
909 Intrinsic IntOp, bit Commutable>
910 : N3V<op24, op23, op21_20, op11_8, 0, op4,
911 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), IIC_VSUBiD,
912 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
913 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
914 let isCommutable = Commutable;
917 // Pairwise long 2-register intrinsics, both double- and quad-register.
918 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
919 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
920 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
921 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
922 (ins DPR:$src), IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "",
923 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
924 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
925 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
926 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
927 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
928 (ins QPR:$src), IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "",
929 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
931 // Pairwise long 2-register accumulate intrinsics,
932 // both double- and quad-register.
933 // The destination register is also used as the first source operand register.
934 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
935 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
936 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
937 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
938 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), IIC_VPALiD,
939 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
940 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
941 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
942 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
943 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
944 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
945 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VPALiQ,
946 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
947 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
949 // Shift by immediate,
950 // both double- and quad-register.
951 class N2VDSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
952 bit op4, InstrItinClass itin, string OpcodeStr,
953 ValueType Ty, SDNode OpNode>
954 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
955 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), itin,
956 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
957 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
958 class N2VQSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
959 bit op4, InstrItinClass itin, string OpcodeStr,
960 ValueType Ty, SDNode OpNode>
961 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
962 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin,
963 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
964 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
966 // Long shift by immediate.
967 class N2VLSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
968 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
969 ValueType OpTy, SDNode OpNode>
970 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
971 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VSHLiD,
972 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
973 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
974 (i32 imm:$SIMM))))]>;
976 // Narrow shift by immediate.
977 class N2VNSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
978 bit op6, bit op4, InstrItinClass itin, string OpcodeStr,
979 ValueType ResTy, ValueType OpTy, SDNode OpNode>
980 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
981 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin,
982 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
983 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
984 (i32 imm:$SIMM))))]>;
986 // Shift right by immediate and accumulate,
987 // both double- and quad-register.
988 class N2VDShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
989 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
990 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
991 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
993 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
994 [(set DPR:$dst, (Ty (add DPR:$src1,
995 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
996 class N2VQShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
997 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
998 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
999 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
1001 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
1002 [(set QPR:$dst, (Ty (add QPR:$src1,
1003 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
1005 // Shift by immediate and insert,
1006 // both double- and quad-register.
1007 class N2VDShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
1008 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
1009 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
1010 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
1012 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
1013 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
1014 class N2VQShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
1015 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
1016 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
1017 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
1019 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
1020 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
1022 // Convert, with fractional bits immediate,
1023 // both double- and quad-register.
1024 class N2VCvtD<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
1025 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
1027 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
1028 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VUNAD,
1029 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
1030 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
1031 class N2VCvtQ<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
1032 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
1034 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
1035 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), IIC_VUNAQ,
1036 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
1037 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
1039 //===----------------------------------------------------------------------===//
1041 //===----------------------------------------------------------------------===//
1043 // Abbreviations used in multiclass suffixes:
1044 // Q = quarter int (8 bit) elements
1045 // H = half int (16 bit) elements
1046 // S = single int (32 bit) elements
1047 // D = double int (64 bit) elements
1049 // Neon 3-register vector operations.
1051 // First with only element sizes of 8, 16 and 32 bits:
1052 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1053 InstrItinClass itinD16, InstrItinClass itinD32,
1054 InstrItinClass itinQ16, InstrItinClass itinQ32,
1055 string OpcodeStr, SDNode OpNode, bit Commutable = 0> {
1056 // 64-bit vector types.
1057 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
1058 !strconcat(OpcodeStr, "8"), v8i8, v8i8, OpNode, Commutable>;
1059 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
1060 !strconcat(OpcodeStr, "16"), v4i16, v4i16, OpNode, Commutable>;
1061 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
1062 !strconcat(OpcodeStr, "32"), v2i32, v2i32, OpNode, Commutable>;
1064 // 128-bit vector types.
1065 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
1066 !strconcat(OpcodeStr, "8"), v16i8, v16i8, OpNode, Commutable>;
1067 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
1068 !strconcat(OpcodeStr, "16"), v8i16, v8i16, OpNode, Commutable>;
1069 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
1070 !strconcat(OpcodeStr, "32"), v4i32, v4i32, OpNode, Commutable>;
1073 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, SDNode ShOp> {
1074 def v4i16 : N3VDSL16<0b01, op11_8, !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
1075 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
1076 def v8i16 : N3VQSL16<0b01, op11_8, !strconcat(OpcodeStr, "16"), v8i16, v4i16, ShOp>;
1077 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, !strconcat(OpcodeStr, "32"), v4i32, v2i32, ShOp>;
1080 // ....then also with element size 64 bits:
1081 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1082 InstrItinClass itinD, InstrItinClass itinQ,
1083 string OpcodeStr, SDNode OpNode, bit Commutable = 0>
1084 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
1085 OpcodeStr, OpNode, Commutable> {
1086 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
1087 !strconcat(OpcodeStr, "64"), v1i64, v1i64, OpNode, Commutable>;
1088 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
1089 !strconcat(OpcodeStr, "64"), v2i64, v2i64, OpNode, Commutable>;
1093 // Neon Narrowing 2-register vector intrinsics,
1094 // source operand element sizes of 16, 32 and 64 bits:
1095 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1096 bits<5> op11_7, bit op6, bit op4,
1097 InstrItinClass itin, string OpcodeStr,
1099 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
1100 itin, !strconcat(OpcodeStr, "16"), v8i8, v8i16, IntOp>;
1101 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
1102 itin, !strconcat(OpcodeStr, "32"), v4i16, v4i32, IntOp>;
1103 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
1104 itin, !strconcat(OpcodeStr, "64"), v2i32, v2i64, IntOp>;
1108 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
1109 // source operand element sizes of 16, 32 and 64 bits:
1110 multiclass N2VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
1111 bit op4, string OpcodeStr, Intrinsic IntOp> {
1112 def v8i16 : N2VLInt<op24, op23, 0b001000, op11_8, op7, op6, op4,
1113 IIC_VQUNAiD, !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
1114 def v4i32 : N2VLInt<op24, op23, 0b010000, op11_8, op7, op6, op4,
1115 IIC_VQUNAiD, !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
1116 def v2i64 : N2VLInt<op24, op23, 0b100000, op11_8, op7, op6, op4,
1117 IIC_VQUNAiD, !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
1121 // Neon 3-register vector intrinsics.
1123 // First with only element sizes of 16 and 32 bits:
1124 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1125 InstrItinClass itinD16, InstrItinClass itinD32,
1126 InstrItinClass itinQ16, InstrItinClass itinQ32,
1127 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
1128 // 64-bit vector types.
1129 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, itinD16, !strconcat(OpcodeStr,"16"),
1130 v4i16, v4i16, IntOp, Commutable>;
1131 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, itinD32, !strconcat(OpcodeStr,"32"),
1132 v2i32, v2i32, IntOp, Commutable>;
1134 // 128-bit vector types.
1135 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, itinQ16, !strconcat(OpcodeStr,"16"),
1136 v8i16, v8i16, IntOp, Commutable>;
1137 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, itinQ32, !strconcat(OpcodeStr,"32"),
1138 v4i32, v4i32, IntOp, Commutable>;
1141 multiclass N3VIntSL_HS<bits<4> op11_8,
1142 InstrItinClass itinD16, InstrItinClass itinD32,
1143 InstrItinClass itinQ16, InstrItinClass itinQ32,
1144 string OpcodeStr, Intrinsic IntOp> {
1145 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16, !strconcat(OpcodeStr, "16"), v4i16, IntOp>;
1146 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32, !strconcat(OpcodeStr, "32"), v2i32, IntOp>;
1147 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16, !strconcat(OpcodeStr, "16"), v8i16, v4i16, IntOp>;
1148 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32, !strconcat(OpcodeStr, "32"), v4i32, v2i32, IntOp>;
1151 // ....then also with element size of 8 bits:
1152 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1153 InstrItinClass itinD16, InstrItinClass itinD32,
1154 InstrItinClass itinQ16, InstrItinClass itinQ32,
1155 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
1156 : N3VInt_HS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
1157 OpcodeStr, IntOp, Commutable> {
1158 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, itinD16,
1159 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp, Commutable>;
1160 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, itinQ16,
1161 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp, Commutable>;
1164 // ....then also with element size of 64 bits:
1165 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1166 InstrItinClass itinD16, InstrItinClass itinD32,
1167 InstrItinClass itinQ16, InstrItinClass itinQ32,
1168 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
1169 : N3VInt_QHS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
1170 OpcodeStr, IntOp, Commutable> {
1171 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, itinD32,
1172 !strconcat(OpcodeStr,"64"), v1i64, v1i64, IntOp, Commutable>;
1173 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, itinQ32,
1174 !strconcat(OpcodeStr,"64"), v2i64, v2i64, IntOp, Commutable>;
1178 // Neon Narrowing 3-register vector intrinsics,
1179 // source operand element sizes of 16, 32 and 64 bits:
1180 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1181 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
1182 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr,"16"),
1183 v8i8, v8i16, IntOp, Commutable>;
1184 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"32"),
1185 v4i16, v4i32, IntOp, Commutable>;
1186 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"64"),
1187 v2i32, v2i64, IntOp, Commutable>;
1191 // Neon Long 3-register vector intrinsics.
1193 // First with only element sizes of 16 and 32 bits:
1194 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1195 InstrItinClass itin, string OpcodeStr,
1196 Intrinsic IntOp, bit Commutable = 0> {
1197 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin,
1198 !strconcat(OpcodeStr,"16"), v4i32, v4i16, IntOp, Commutable>;
1199 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin,
1200 !strconcat(OpcodeStr,"32"), v2i64, v2i32, IntOp, Commutable>;
1203 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
1204 InstrItinClass itin, string OpcodeStr, Intrinsic IntOp> {
1205 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
1206 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
1207 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
1208 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
1211 // ....then also with element size of 8 bits:
1212 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1213 InstrItinClass itin, string OpcodeStr,
1214 Intrinsic IntOp, bit Commutable = 0>
1215 : N3VLInt_HS<op24, op23, op11_8, op4, itin, OpcodeStr, IntOp, Commutable> {
1216 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin,
1217 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp, Commutable>;
1221 // Neon Wide 3-register vector intrinsics,
1222 // source operand element sizes of 8, 16 and 32 bits:
1223 multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1224 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
1225 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
1226 v8i16, v8i8, IntOp, Commutable>;
1227 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
1228 v4i32, v4i16, IntOp, Commutable>;
1229 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
1230 v2i64, v2i32, IntOp, Commutable>;
1234 // Neon Multiply-Op vector operations,
1235 // element sizes of 8, 16 and 32 bits:
1236 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1237 InstrItinClass itinD16, InstrItinClass itinD32,
1238 InstrItinClass itinQ16, InstrItinClass itinQ32,
1239 string OpcodeStr, SDNode OpNode> {
1240 // 64-bit vector types.
1241 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
1242 !strconcat(OpcodeStr, "8"), v8i8, mul, OpNode>;
1243 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
1244 !strconcat(OpcodeStr, "16"), v4i16, mul, OpNode>;
1245 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
1246 !strconcat(OpcodeStr, "32"), v2i32, mul, OpNode>;
1248 // 128-bit vector types.
1249 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
1250 !strconcat(OpcodeStr, "8"), v16i8, mul, OpNode>;
1251 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
1252 !strconcat(OpcodeStr, "16"), v8i16, mul, OpNode>;
1253 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
1254 !strconcat(OpcodeStr, "32"), v4i32, mul, OpNode>;
1257 multiclass N3VMulOpSL_HS<bits<4> op11_8,
1258 InstrItinClass itinD16, InstrItinClass itinD32,
1259 InstrItinClass itinQ16, InstrItinClass itinQ32,
1260 string OpcodeStr, SDNode ShOp> {
1261 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
1262 !strconcat(OpcodeStr, "16"), v4i16, mul, ShOp>;
1263 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
1264 !strconcat(OpcodeStr, "32"), v2i32, mul, ShOp>;
1265 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
1266 !strconcat(OpcodeStr, "16"), v8i16, v4i16, mul, ShOp>;
1267 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
1268 !strconcat(OpcodeStr, "32"), v4i32, v2i32, mul, ShOp>;
1271 // Neon 3-argument intrinsics,
1272 // element sizes of 8, 16 and 32 bits:
1273 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1274 string OpcodeStr, Intrinsic IntOp> {
1275 // 64-bit vector types.
1276 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16D,
1277 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
1278 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
1279 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
1280 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32D,
1281 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
1283 // 128-bit vector types.
1284 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16Q,
1285 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
1286 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16Q,
1287 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
1288 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32Q,
1289 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
1293 // Neon Long 3-argument intrinsics.
1295 // First with only element sizes of 16 and 32 bits:
1296 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1297 string OpcodeStr, Intrinsic IntOp> {
1298 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
1299 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
1300 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi16D,
1301 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
1304 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
1305 string OpcodeStr, Intrinsic IntOp> {
1306 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
1307 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
1308 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
1309 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
1312 // ....then also with element size of 8 bits:
1313 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1314 string OpcodeStr, Intrinsic IntOp>
1315 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp> {
1316 def v8i16 : N3VLInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
1317 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
1321 // Neon 2-register vector intrinsics,
1322 // element sizes of 8, 16 and 32 bits:
1323 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1324 bits<5> op11_7, bit op4,
1325 InstrItinClass itinD, InstrItinClass itinQ,
1326 string OpcodeStr, Intrinsic IntOp> {
1327 // 64-bit vector types.
1328 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1329 itinD, !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
1330 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1331 itinD, !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
1332 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1333 itinD, !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
1335 // 128-bit vector types.
1336 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1337 itinQ, !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
1338 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1339 itinQ, !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
1340 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1341 itinQ, !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
1345 // Neon Pairwise long 2-register intrinsics,
1346 // element sizes of 8, 16 and 32 bits:
1347 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1348 bits<5> op11_7, bit op4,
1349 string OpcodeStr, Intrinsic IntOp> {
1350 // 64-bit vector types.
1351 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1352 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
1353 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1354 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
1355 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1356 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
1358 // 128-bit vector types.
1359 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1360 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
1361 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1362 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
1363 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1364 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
1368 // Neon Pairwise long 2-register accumulate intrinsics,
1369 // element sizes of 8, 16 and 32 bits:
1370 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1371 bits<5> op11_7, bit op4,
1372 string OpcodeStr, Intrinsic IntOp> {
1373 // 64-bit vector types.
1374 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1375 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
1376 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1377 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
1378 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1379 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
1381 // 128-bit vector types.
1382 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1383 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
1384 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1385 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
1386 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1387 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
1391 // Neon 2-register vector shift by immediate,
1392 // element sizes of 8, 16, 32 and 64 bits:
1393 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1394 InstrItinClass itin, string OpcodeStr, SDNode OpNode> {
1395 // 64-bit vector types.
1396 def v8i8 : N2VDSh<op24, op23, 0b001000, op11_8, 0, op4, itin,
1397 !strconcat(OpcodeStr, "8"), v8i8, OpNode>;
1398 def v4i16 : N2VDSh<op24, op23, 0b010000, op11_8, 0, op4, itin,
1399 !strconcat(OpcodeStr, "16"), v4i16, OpNode>;
1400 def v2i32 : N2VDSh<op24, op23, 0b100000, op11_8, 0, op4, itin,
1401 !strconcat(OpcodeStr, "32"), v2i32, OpNode>;
1402 def v1i64 : N2VDSh<op24, op23, 0b000000, op11_8, 1, op4, itin,
1403 !strconcat(OpcodeStr, "64"), v1i64, OpNode>;
1405 // 128-bit vector types.
1406 def v16i8 : N2VQSh<op24, op23, 0b001000, op11_8, 0, op4, itin,
1407 !strconcat(OpcodeStr, "8"), v16i8, OpNode>;
1408 def v8i16 : N2VQSh<op24, op23, 0b010000, op11_8, 0, op4, itin,
1409 !strconcat(OpcodeStr, "16"), v8i16, OpNode>;
1410 def v4i32 : N2VQSh<op24, op23, 0b100000, op11_8, 0, op4, itin,
1411 !strconcat(OpcodeStr, "32"), v4i32, OpNode>;
1412 def v2i64 : N2VQSh<op24, op23, 0b000000, op11_8, 1, op4, itin,
1413 !strconcat(OpcodeStr, "64"), v2i64, OpNode>;
1417 // Neon Shift-Accumulate vector operations,
1418 // element sizes of 8, 16, 32 and 64 bits:
1419 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1420 string OpcodeStr, SDNode ShOp> {
1421 // 64-bit vector types.
1422 def v8i8 : N2VDShAdd<op24, op23, 0b001000, op11_8, 0, op4,
1423 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
1424 def v4i16 : N2VDShAdd<op24, op23, 0b010000, op11_8, 0, op4,
1425 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
1426 def v2i32 : N2VDShAdd<op24, op23, 0b100000, op11_8, 0, op4,
1427 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
1428 def v1i64 : N2VDShAdd<op24, op23, 0b000000, op11_8, 1, op4,
1429 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
1431 // 128-bit vector types.
1432 def v16i8 : N2VQShAdd<op24, op23, 0b001000, op11_8, 0, op4,
1433 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
1434 def v8i16 : N2VQShAdd<op24, op23, 0b010000, op11_8, 0, op4,
1435 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
1436 def v4i32 : N2VQShAdd<op24, op23, 0b100000, op11_8, 0, op4,
1437 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
1438 def v2i64 : N2VQShAdd<op24, op23, 0b000000, op11_8, 1, op4,
1439 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
1443 // Neon Shift-Insert vector operations,
1444 // element sizes of 8, 16, 32 and 64 bits:
1445 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1446 string OpcodeStr, SDNode ShOp> {
1447 // 64-bit vector types.
1448 def v8i8 : N2VDShIns<op24, op23, 0b001000, op11_8, 0, op4,
1449 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
1450 def v4i16 : N2VDShIns<op24, op23, 0b010000, op11_8, 0, op4,
1451 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
1452 def v2i32 : N2VDShIns<op24, op23, 0b100000, op11_8, 0, op4,
1453 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
1454 def v1i64 : N2VDShIns<op24, op23, 0b000000, op11_8, 1, op4,
1455 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
1457 // 128-bit vector types.
1458 def v16i8 : N2VQShIns<op24, op23, 0b001000, op11_8, 0, op4,
1459 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
1460 def v8i16 : N2VQShIns<op24, op23, 0b010000, op11_8, 0, op4,
1461 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
1462 def v4i32 : N2VQShIns<op24, op23, 0b100000, op11_8, 0, op4,
1463 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
1464 def v2i64 : N2VQShIns<op24, op23, 0b000000, op11_8, 1, op4,
1465 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
1468 //===----------------------------------------------------------------------===//
1469 // Instruction Definitions.
1470 //===----------------------------------------------------------------------===//
1472 // Vector Add Operations.
1474 // VADD : Vector Add (integer and floating-point)
1475 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd.i", add, 1>;
1476 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd.f32", v2f32, v2f32, fadd, 1>;
1477 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd.f32", v4f32, v4f32, fadd, 1>;
1478 // VADDL : Vector Add Long (Q = D + D)
1479 defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, IIC_VSHLiD, "vaddl.s", int_arm_neon_vaddls, 1>;
1480 defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, IIC_VSHLiD, "vaddl.u", int_arm_neon_vaddlu, 1>;
1481 // VADDW : Vector Add Wide (Q = Q + D)
1482 defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw.s", int_arm_neon_vaddws, 0>;
1483 defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw.u", int_arm_neon_vaddwu, 0>;
1484 // VHADD : Vector Halving Add
1485 defm VHADDs : N3VInt_QHS<0,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1486 IIC_VBINi4Q, "vhadd.s", int_arm_neon_vhadds, 1>;
1487 defm VHADDu : N3VInt_QHS<1,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1488 IIC_VBINi4Q, "vhadd.u", int_arm_neon_vhaddu, 1>;
1489 // VRHADD : Vector Rounding Halving Add
1490 defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1491 IIC_VBINi4Q, "vrhadd.s", int_arm_neon_vrhadds, 1>;
1492 defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1493 IIC_VBINi4Q, "vrhadd.u", int_arm_neon_vrhaddu, 1>;
1494 // VQADD : Vector Saturating Add
1495 defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1496 IIC_VBINi4Q, "vqadd.s", int_arm_neon_vqadds, 1>;
1497 defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1498 IIC_VBINi4Q, "vqadd.u", int_arm_neon_vqaddu, 1>;
1499 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
1500 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn.i", int_arm_neon_vaddhn, 1>;
1501 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
1502 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn.i", int_arm_neon_vraddhn, 1>;
1504 // Vector Multiply Operations.
1506 // VMUL : Vector Multiply (integer, polynomial and floating-point)
1507 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D, IIC_VMULi16Q,
1508 IIC_VMULi32Q, "vmul.i", mul, 1>;
1509 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16D, "vmul.p8", v8i8, v8i8,
1510 int_arm_neon_vmulp, 1>;
1511 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16Q, "vmul.p8", v16i8, v16i8,
1512 int_arm_neon_vmulp, 1>;
1513 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VBIND, "vmul.f32", v2f32, v2f32, fmul, 1>;
1514 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VBINQ, "vmul.f32", v4f32, v4f32, fmul, 1>;
1515 defm VMULsl : N3VSL_HS<0b1000, "vmul.i", mul>;
1516 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul.f32", v2f32, fmul>;
1517 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul.f32", v4f32, v2f32, fmul>;
1518 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
1519 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
1520 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
1521 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1522 (DSubReg_i16_reg imm:$lane))),
1523 (SubReg_i16_lane imm:$lane)))>;
1524 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
1525 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
1526 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
1527 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1528 (DSubReg_i32_reg imm:$lane))),
1529 (SubReg_i32_lane imm:$lane)))>;
1530 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
1531 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
1532 (v4f32 (VMULslfq (v4f32 QPR:$src1),
1533 (v2f32 (EXTRACT_SUBREG QPR:$src2,
1534 (DSubReg_i32_reg imm:$lane))),
1535 (SubReg_i32_lane imm:$lane)))>;
1537 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
1538 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
1539 IIC_VMULi16Q, IIC_VMULi32Q,
1540 "vqdmulh.s", int_arm_neon_vqdmulh, 1>;
1541 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
1542 IIC_VMULi16Q, IIC_VMULi32Q,
1543 "vqdmulh.s", int_arm_neon_vqdmulh>;
1544 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
1545 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
1546 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
1547 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1548 (DSubReg_i16_reg imm:$lane))),
1549 (SubReg_i16_lane imm:$lane)))>;
1550 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
1551 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
1552 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
1553 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1554 (DSubReg_i32_reg imm:$lane))),
1555 (SubReg_i32_lane imm:$lane)))>;
1557 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
1558 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
1559 IIC_VMULi16Q, IIC_VMULi32Q,
1560 "vqrdmulh.s", int_arm_neon_vqrdmulh, 1>;
1561 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
1562 IIC_VMULi16Q, IIC_VMULi32Q,
1563 "vqrdmulh.s", int_arm_neon_vqrdmulh>;
1564 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
1565 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
1566 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
1567 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1568 (DSubReg_i16_reg imm:$lane))),
1569 (SubReg_i16_lane imm:$lane)))>;
1570 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
1571 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
1572 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
1573 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1574 (DSubReg_i32_reg imm:$lane))),
1575 (SubReg_i32_lane imm:$lane)))>;
1577 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
1578 defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, IIC_VMULi16D, "vmull.s", int_arm_neon_vmulls, 1>;
1579 defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, IIC_VMULi16D, "vmull.u", int_arm_neon_vmullu, 1>;
1580 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull.p8", v8i16, v8i8,
1581 int_arm_neon_vmullp, 1>;
1582 defm VMULLsls : N3VLIntSL_HS<0, 0b1010, IIC_VMULi16D, "vmull.s", int_arm_neon_vmulls>;
1583 defm VMULLslu : N3VLIntSL_HS<1, 0b1010, IIC_VMULi16D, "vmull.u", int_arm_neon_vmullu>;
1585 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
1586 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, "vqdmull.s", int_arm_neon_vqdmull, 1>;
1587 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D, "vqdmull.s", int_arm_neon_vqdmull>;
1589 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
1591 // VMLA : Vector Multiply Accumulate (integer and floating-point)
1592 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
1593 IIC_VMACi16Q, IIC_VMACi32Q, "vmla.i", add>;
1594 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla.f32", v2f32, fmul, fadd>;
1595 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla.f32", v4f32, fmul, fadd>;
1596 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
1597 IIC_VMACi16Q, IIC_VMACi32Q, "vmla.i", add>;
1598 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla.f32", v2f32, fmul, fadd>;
1599 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla.f32", v4f32, v2f32, fmul, fadd>;
1601 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
1602 (mul (v8i16 QPR:$src2),
1603 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
1604 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1),
1606 (v4i16 (EXTRACT_SUBREG QPR:$src3,
1607 (DSubReg_i16_reg imm:$lane))),
1608 (SubReg_i16_lane imm:$lane)))>;
1610 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
1611 (mul (v4i32 QPR:$src2),
1612 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
1613 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1),
1615 (v2i32 (EXTRACT_SUBREG QPR:$src3,
1616 (DSubReg_i32_reg imm:$lane))),
1617 (SubReg_i32_lane imm:$lane)))>;
1619 def : Pat<(v4f32 (fadd (v4f32 QPR:$src1),
1620 (fmul (v4f32 QPR:$src2),
1621 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
1622 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
1624 (v2f32 (EXTRACT_SUBREG QPR:$src3,
1625 (DSubReg_i32_reg imm:$lane))),
1626 (SubReg_i32_lane imm:$lane)))>;
1628 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
1629 defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal.s", int_arm_neon_vmlals>;
1630 defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal.u", int_arm_neon_vmlalu>;
1632 defm VMLALsls : N3VLInt3SL_HS<0, 0b0010, "vmlal.s", int_arm_neon_vmlals>;
1633 defm VMLALslu : N3VLInt3SL_HS<1, 0b0010, "vmlal.u", int_arm_neon_vmlalu>;
1635 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
1636 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal.s", int_arm_neon_vqdmlal>;
1637 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal.s", int_arm_neon_vqdmlal>;
1639 // VMLS : Vector Multiply Subtract (integer and floating-point)
1640 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
1641 IIC_VMACi16Q, IIC_VMACi32Q, "vmls.i", sub>;
1642 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls.f32", v2f32, fmul, fsub>;
1643 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls.f32", v4f32, fmul, fsub>;
1644 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
1645 IIC_VMACi16Q, IIC_VMACi32Q, "vmls.i", sub>;
1646 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls.f32", v2f32, fmul, fsub>;
1647 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls.f32", v4f32, v2f32, fmul, fsub>;
1649 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
1650 (mul (v8i16 QPR:$src2),
1651 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
1652 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1),
1654 (v4i16 (EXTRACT_SUBREG QPR:$src3,
1655 (DSubReg_i16_reg imm:$lane))),
1656 (SubReg_i16_lane imm:$lane)))>;
1658 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
1659 (mul (v4i32 QPR:$src2),
1660 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
1661 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1),
1663 (v2i32 (EXTRACT_SUBREG QPR:$src3,
1664 (DSubReg_i32_reg imm:$lane))),
1665 (SubReg_i32_lane imm:$lane)))>;
1667 def : Pat<(v4f32 (fsub (v4f32 QPR:$src1),
1668 (fmul (v4f32 QPR:$src2),
1669 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
1670 (v4f32 (VMLSslfq (v4f32 QPR:$src1),
1672 (v2f32 (EXTRACT_SUBREG QPR:$src3,
1673 (DSubReg_i32_reg imm:$lane))),
1674 (SubReg_i32_lane imm:$lane)))>;
1676 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
1677 defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl.s", int_arm_neon_vmlsls>;
1678 defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl.u", int_arm_neon_vmlslu>;
1680 defm VMLSLsls : N3VLInt3SL_HS<0, 0b0110, "vmlsl.s", int_arm_neon_vmlsls>;
1681 defm VMLSLslu : N3VLInt3SL_HS<1, 0b0110, "vmlsl.u", int_arm_neon_vmlslu>;
1683 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
1684 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl.s", int_arm_neon_vqdmlsl>;
1685 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl.s", int_arm_neon_vqdmlsl>;
1687 // Vector Subtract Operations.
1689 // VSUB : Vector Subtract (integer and floating-point)
1690 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ, "vsub.i", sub, 0>;
1691 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub.f32", v2f32, v2f32, fsub, 0>;
1692 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub.f32", v4f32, v4f32, fsub, 0>;
1693 // VSUBL : Vector Subtract Long (Q = D - D)
1694 defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, IIC_VSHLiD, "vsubl.s", int_arm_neon_vsubls, 1>;
1695 defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, IIC_VSHLiD, "vsubl.u", int_arm_neon_vsublu, 1>;
1696 // VSUBW : Vector Subtract Wide (Q = Q - D)
1697 defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw.s", int_arm_neon_vsubws, 0>;
1698 defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw.u", int_arm_neon_vsubwu, 0>;
1699 // VHSUB : Vector Halving Subtract
1700 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1701 IIC_VBINi4Q, "vhsub.s", int_arm_neon_vhsubs, 0>;
1702 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1703 IIC_VBINi4Q, "vhsub.u", int_arm_neon_vhsubu, 0>;
1704 // VQSUB : Vector Saturing Subtract
1705 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1706 IIC_VBINi4Q, "vqsub.s", int_arm_neon_vqsubs, 0>;
1707 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1708 IIC_VBINi4Q, "vqsub.u", int_arm_neon_vqsubu, 0>;
1709 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
1710 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn.i", int_arm_neon_vsubhn, 0>;
1711 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
1712 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn.i", int_arm_neon_vrsubhn, 0>;
1714 // Vector Comparisons.
1716 // VCEQ : Vector Compare Equal
1717 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1718 IIC_VBINi4Q, "vceq.i", NEONvceq, 1>;
1719 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq.f32", v2i32, v2f32, NEONvceq, 1>;
1720 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq.f32", v4i32, v4f32, NEONvceq, 1>;
1721 // VCGE : Vector Compare Greater Than or Equal
1722 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1723 IIC_VBINi4Q, "vcge.s", NEONvcge, 0>;
1724 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1725 IIC_VBINi4Q, "vcge.u", NEONvcgeu, 0>;
1726 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge.f32", v2i32, v2f32, NEONvcge, 0>;
1727 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge.f32", v4i32, v4f32, NEONvcge, 0>;
1728 // VCGT : Vector Compare Greater Than
1729 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1730 IIC_VBINi4Q, "vcgt.s", NEONvcgt, 0>;
1731 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1732 IIC_VBINi4Q, "vcgt.u", NEONvcgtu, 0>;
1733 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt.f32", v2i32, v2f32, NEONvcgt, 0>;
1734 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt.f32", v4i32, v4f32, NEONvcgt, 0>;
1735 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
1736 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, IIC_VBIND, "vacge.f32", v2i32, v2f32,
1737 int_arm_neon_vacged, 0>;
1738 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, IIC_VBINQ, "vacge.f32", v4i32, v4f32,
1739 int_arm_neon_vacgeq, 0>;
1740 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
1741 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, IIC_VBIND, "vacgt.f32", v2i32, v2f32,
1742 int_arm_neon_vacgtd, 0>;
1743 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, IIC_VBINQ, "vacgt.f32", v4i32, v4f32,
1744 int_arm_neon_vacgtq, 0>;
1745 // VTST : Vector Test Bits
1746 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1747 IIC_VBINi4Q, "vtst.i", NEONvtst, 1>;
1749 // Vector Bitwise Operations.
1751 // VAND : Vector Bitwise AND
1752 def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand", v2i32, v2i32, and, 1>;
1753 def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand", v4i32, v4i32, and, 1>;
1755 // VEOR : Vector Bitwise Exclusive OR
1756 def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor", v2i32, v2i32, xor, 1>;
1757 def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor", v4i32, v4i32, xor, 1>;
1759 // VORR : Vector Bitwise OR
1760 def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr", v2i32, v2i32, or, 1>;
1761 def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr", v4i32, v4i32, or, 1>;
1763 // VBIC : Vector Bitwise Bit Clear (AND NOT)
1764 def VBICd : N3V<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1765 (ins DPR:$src1, DPR:$src2), IIC_VBINiD,
1766 "vbic\t$dst, $src1, $src2", "",
1767 [(set DPR:$dst, (v2i32 (and DPR:$src1,
1768 (vnot_conv DPR:$src2))))]>;
1769 def VBICq : N3V<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1770 (ins QPR:$src1, QPR:$src2), IIC_VBINiQ,
1771 "vbic\t$dst, $src1, $src2", "",
1772 [(set QPR:$dst, (v4i32 (and QPR:$src1,
1773 (vnot_conv QPR:$src2))))]>;
1775 // VORN : Vector Bitwise OR NOT
1776 def VORNd : N3V<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
1777 (ins DPR:$src1, DPR:$src2), IIC_VBINiD,
1778 "vorn\t$dst, $src1, $src2", "",
1779 [(set DPR:$dst, (v2i32 (or DPR:$src1,
1780 (vnot_conv DPR:$src2))))]>;
1781 def VORNq : N3V<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
1782 (ins QPR:$src1, QPR:$src2), IIC_VBINiQ,
1783 "vorn\t$dst, $src1, $src2", "",
1784 [(set QPR:$dst, (v4i32 (or QPR:$src1,
1785 (vnot_conv QPR:$src2))))]>;
1787 // VMVN : Vector Bitwise NOT
1788 def VMVNd : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
1789 (outs DPR:$dst), (ins DPR:$src), IIC_VSHLiD,
1790 "vmvn\t$dst, $src", "",
1791 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>;
1792 def VMVNq : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
1793 (outs QPR:$dst), (ins QPR:$src), IIC_VSHLiD,
1794 "vmvn\t$dst, $src", "",
1795 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>;
1796 def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>;
1797 def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>;
1799 // VBSL : Vector Bitwise Select
1800 def VBSLd : N3V<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1801 (ins DPR:$src1, DPR:$src2, DPR:$src3), IIC_VCNTiD,
1802 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1804 (v2i32 (or (and DPR:$src2, DPR:$src1),
1805 (and DPR:$src3, (vnot_conv DPR:$src1)))))]>;
1806 def VBSLq : N3V<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1807 (ins QPR:$src1, QPR:$src2, QPR:$src3), IIC_VCNTiQ,
1808 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1810 (v4i32 (or (and QPR:$src2, QPR:$src1),
1811 (and QPR:$src3, (vnot_conv QPR:$src1)))))]>;
1813 // VBIF : Vector Bitwise Insert if False
1814 // like VBSL but with: "vbif\t$dst, $src3, $src1", "$src2 = $dst",
1815 // VBIT : Vector Bitwise Insert if True
1816 // like VBSL but with: "vbit\t$dst, $src2, $src1", "$src3 = $dst",
1817 // These are not yet implemented. The TwoAddress pass will not go looking
1818 // for equivalent operations with different register constraints; it just
1821 // Vector Absolute Differences.
1823 // VABD : Vector Absolute Difference
1824 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1825 IIC_VBINi4Q, "vabd.s", int_arm_neon_vabds, 0>;
1826 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1827 IIC_VBINi4Q, "vabd.u", int_arm_neon_vabdu, 0>;
1828 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, IIC_VBIND, "vabd.f32", v2f32, v2f32,
1829 int_arm_neon_vabds, 0>;
1830 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vabd.f32", v4f32, v4f32,
1831 int_arm_neon_vabds, 0>;
1833 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
1834 defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, IIC_VBINi4Q, "vabdl.s", int_arm_neon_vabdls, 0>;
1835 defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, IIC_VBINi4Q, "vabdl.u", int_arm_neon_vabdlu, 0>;
1837 // VABA : Vector Absolute Difference and Accumulate
1838 defm VABAs : N3VInt3_QHS<0,1,0b0101,0, "vaba.s", int_arm_neon_vabas>;
1839 defm VABAu : N3VInt3_QHS<1,1,0b0101,0, "vaba.u", int_arm_neon_vabau>;
1841 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
1842 defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal.s", int_arm_neon_vabals>;
1843 defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal.u", int_arm_neon_vabalu>;
1845 // Vector Maximum and Minimum.
1847 // VMAX : Vector Maximum
1848 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1849 IIC_VBINi4Q, "vmax.s", int_arm_neon_vmaxs, 1>;
1850 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1851 IIC_VBINi4Q, "vmax.u", int_arm_neon_vmaxu, 1>;
1852 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, IIC_VBIND, "vmax.f32", v2f32, v2f32,
1853 int_arm_neon_vmaxs, 1>;
1854 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, IIC_VBINQ, "vmax.f32", v4f32, v4f32,
1855 int_arm_neon_vmaxs, 1>;
1857 // VMIN : Vector Minimum
1858 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1859 IIC_VBINi4Q, "vmin.s", int_arm_neon_vmins, 1>;
1860 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1861 IIC_VBINi4Q, "vmin.u", int_arm_neon_vminu, 1>;
1862 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, IIC_VBIND, "vmin.f32", v2f32, v2f32,
1863 int_arm_neon_vmins, 1>;
1864 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, IIC_VBINQ, "vmin.f32", v4f32, v4f32,
1865 int_arm_neon_vmins, 1>;
1867 // Vector Pairwise Operations.
1869 // VPADD : Vector Pairwise Add
1870 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, IIC_VBINiD, "vpadd.i8", v8i8, v8i8,
1871 int_arm_neon_vpadd, 0>;
1872 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, IIC_VBINiD, "vpadd.i16", v4i16, v4i16,
1873 int_arm_neon_vpadd, 0>;
1874 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, IIC_VBINiD, "vpadd.i32", v2i32, v2i32,
1875 int_arm_neon_vpadd, 0>;
1876 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, IIC_VBIND, "vpadd.f32", v2f32, v2f32,
1877 int_arm_neon_vpadd, 0>;
1879 // VPADDL : Vector Pairwise Add Long
1880 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl.s",
1881 int_arm_neon_vpaddls>;
1882 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl.u",
1883 int_arm_neon_vpaddlu>;
1885 // VPADAL : Vector Pairwise Add and Accumulate Long
1886 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpadal.s",
1887 int_arm_neon_vpadals>;
1888 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpadal.u",
1889 int_arm_neon_vpadalu>;
1891 // VPMAX : Vector Pairwise Maximum
1892 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax.s8", v8i8, v8i8,
1893 int_arm_neon_vpmaxs, 0>;
1894 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax.s16", v4i16, v4i16,
1895 int_arm_neon_vpmaxs, 0>;
1896 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax.s32", v2i32, v2i32,
1897 int_arm_neon_vpmaxs, 0>;
1898 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax.u8", v8i8, v8i8,
1899 int_arm_neon_vpmaxu, 0>;
1900 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax.u16", v4i16, v4i16,
1901 int_arm_neon_vpmaxu, 0>;
1902 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax.u32", v2i32, v2i32,
1903 int_arm_neon_vpmaxu, 0>;
1904 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, IIC_VBINi4D, "vpmax.f32", v2f32, v2f32,
1905 int_arm_neon_vpmaxs, 0>;
1907 // VPMIN : Vector Pairwise Minimum
1908 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin.s8", v8i8, v8i8,
1909 int_arm_neon_vpmins, 0>;
1910 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin.s16", v4i16, v4i16,
1911 int_arm_neon_vpmins, 0>;
1912 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin.s32", v2i32, v2i32,
1913 int_arm_neon_vpmins, 0>;
1914 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin.u8", v8i8, v8i8,
1915 int_arm_neon_vpminu, 0>;
1916 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin.u16", v4i16, v4i16,
1917 int_arm_neon_vpminu, 0>;
1918 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin.u32", v2i32, v2i32,
1919 int_arm_neon_vpminu, 0>;
1920 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, IIC_VBINi4D, "vpmin.f32", v2f32, v2f32,
1921 int_arm_neon_vpmins, 0>;
1923 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
1925 // VRECPE : Vector Reciprocal Estimate
1926 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
1927 IIC_VUNAD, "vrecpe.u32",
1928 v2i32, v2i32, int_arm_neon_vrecpe>;
1929 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
1930 IIC_VUNAQ, "vrecpe.u32",
1931 v4i32, v4i32, int_arm_neon_vrecpe>;
1932 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
1933 IIC_VUNAD, "vrecpe.f32",
1934 v2f32, v2f32, int_arm_neon_vrecpe>;
1935 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
1936 IIC_VUNAQ, "vrecpe.f32",
1937 v4f32, v4f32, int_arm_neon_vrecpe>;
1939 // VRECPS : Vector Reciprocal Step
1940 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, IIC_VRECSD, "vrecps.f32", v2f32, v2f32,
1941 int_arm_neon_vrecps, 1>;
1942 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, IIC_VRECSQ, "vrecps.f32", v4f32, v4f32,
1943 int_arm_neon_vrecps, 1>;
1945 // VRSQRTE : Vector Reciprocal Square Root Estimate
1946 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
1947 IIC_VUNAD, "vrsqrte.u32",
1948 v2i32, v2i32, int_arm_neon_vrsqrte>;
1949 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
1950 IIC_VUNAQ, "vrsqrte.u32",
1951 v4i32, v4i32, int_arm_neon_vrsqrte>;
1952 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
1953 IIC_VUNAD, "vrsqrte.f32",
1954 v2f32, v2f32, int_arm_neon_vrsqrte>;
1955 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
1956 IIC_VUNAQ, "vrsqrte.f32",
1957 v4f32, v4f32, int_arm_neon_vrsqrte>;
1959 // VRSQRTS : Vector Reciprocal Square Root Step
1960 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, IIC_VRECSD, "vrsqrts.f32", v2f32, v2f32,
1961 int_arm_neon_vrsqrts, 1>;
1962 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, IIC_VRECSQ, "vrsqrts.f32", v4f32, v4f32,
1963 int_arm_neon_vrsqrts, 1>;
1967 // VSHL : Vector Shift
1968 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
1969 IIC_VSHLiQ, "vshl.s", int_arm_neon_vshifts, 0>;
1970 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
1971 IIC_VSHLiQ, "vshl.u", int_arm_neon_vshiftu, 0>;
1972 // VSHL : Vector Shift Left (Immediate)
1973 defm VSHLi : N2VSh_QHSD<0, 1, 0b0111, 1, IIC_VSHLiD, "vshl.i", NEONvshl>;
1974 // VSHR : Vector Shift Right (Immediate)
1975 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr.s", NEONvshrs>;
1976 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr.u", NEONvshru>;
1978 // VSHLL : Vector Shift Left Long
1979 def VSHLLs8 : N2VLSh<0, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.s8",
1980 v8i16, v8i8, NEONvshlls>;
1981 def VSHLLs16 : N2VLSh<0, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.s16",
1982 v4i32, v4i16, NEONvshlls>;
1983 def VSHLLs32 : N2VLSh<0, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.s32",
1984 v2i64, v2i32, NEONvshlls>;
1985 def VSHLLu8 : N2VLSh<1, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.u8",
1986 v8i16, v8i8, NEONvshllu>;
1987 def VSHLLu16 : N2VLSh<1, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.u16",
1988 v4i32, v4i16, NEONvshllu>;
1989 def VSHLLu32 : N2VLSh<1, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.u32",
1990 v2i64, v2i32, NEONvshllu>;
1992 // VSHLL : Vector Shift Left Long (with maximum shift count)
1993 def VSHLLi8 : N2VLSh<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll.i8",
1994 v8i16, v8i8, NEONvshlli>;
1995 def VSHLLi16 : N2VLSh<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll.i16",
1996 v4i32, v4i16, NEONvshlli>;
1997 def VSHLLi32 : N2VLSh<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll.i32",
1998 v2i64, v2i32, NEONvshlli>;
2000 // VSHRN : Vector Shift Right and Narrow
2001 def VSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 0, 1,
2002 IIC_VSHLiD, "vshrn.i16", v8i8, v8i16, NEONvshrn>;
2003 def VSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 0, 1,
2004 IIC_VSHLiD, "vshrn.i32", v4i16, v4i32, NEONvshrn>;
2005 def VSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 0, 1,
2006 IIC_VSHLiD, "vshrn.i64", v2i32, v2i64, NEONvshrn>;
2008 // VRSHL : Vector Rounding Shift
2009 defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2010 IIC_VSHLi4Q, "vrshl.s", int_arm_neon_vrshifts, 0>;
2011 defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2012 IIC_VSHLi4Q, "vrshl.u", int_arm_neon_vrshiftu, 0>;
2013 // VRSHR : Vector Rounding Shift Right
2014 defm VRSHRs : N2VSh_QHSD<0, 1, 0b0010, 1, IIC_VSHLi4D, "vrshr.s", NEONvrshrs>;
2015 defm VRSHRu : N2VSh_QHSD<1, 1, 0b0010, 1, IIC_VSHLi4D, "vrshr.u", NEONvrshru>;
2017 // VRSHRN : Vector Rounding Shift Right and Narrow
2018 def VRSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 1, 1,
2019 IIC_VSHLi4D, "vrshrn.i16", v8i8, v8i16, NEONvrshrn>;
2020 def VRSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 1, 1,
2021 IIC_VSHLi4D, "vrshrn.i32", v4i16, v4i32, NEONvrshrn>;
2022 def VRSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 1, 1,
2023 IIC_VSHLi4D, "vrshrn.i64", v2i32, v2i64, NEONvrshrn>;
2025 // VQSHL : Vector Saturating Shift
2026 defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2027 IIC_VSHLi4Q, "vqshl.s", int_arm_neon_vqshifts, 0>;
2028 defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2029 IIC_VSHLi4Q, "vqshl.u", int_arm_neon_vqshiftu, 0>;
2030 // VQSHL : Vector Saturating Shift Left (Immediate)
2031 defm VQSHLsi : N2VSh_QHSD<0, 1, 0b0111, 1, IIC_VSHLi4D, "vqshl.s", NEONvqshls>;
2032 defm VQSHLui : N2VSh_QHSD<1, 1, 0b0111, 1, IIC_VSHLi4D, "vqshl.u", NEONvqshlu>;
2033 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
2034 defm VQSHLsu : N2VSh_QHSD<1, 1, 0b0110, 1, IIC_VSHLi4D, "vqshlu.s", NEONvqshlsu>;
2036 // VQSHRN : Vector Saturating Shift Right and Narrow
2037 def VQSHRNs16 : N2VNSh<0, 1, 0b001000, 0b1001, 0, 0, 1,
2038 IIC_VSHLi4D, "vqshrn.s16", v8i8, v8i16, NEONvqshrns>;
2039 def VQSHRNs32 : N2VNSh<0, 1, 0b010000, 0b1001, 0, 0, 1,
2040 IIC_VSHLi4D, "vqshrn.s32", v4i16, v4i32, NEONvqshrns>;
2041 def VQSHRNs64 : N2VNSh<0, 1, 0b100000, 0b1001, 0, 0, 1,
2042 IIC_VSHLi4D, "vqshrn.s64", v2i32, v2i64, NEONvqshrns>;
2043 def VQSHRNu16 : N2VNSh<1, 1, 0b001000, 0b1001, 0, 0, 1,
2044 IIC_VSHLi4D, "vqshrn.u16", v8i8, v8i16, NEONvqshrnu>;
2045 def VQSHRNu32 : N2VNSh<1, 1, 0b010000, 0b1001, 0, 0, 1,
2046 IIC_VSHLi4D, "vqshrn.u32", v4i16, v4i32, NEONvqshrnu>;
2047 def VQSHRNu64 : N2VNSh<1, 1, 0b100000, 0b1001, 0, 0, 1,
2048 IIC_VSHLi4D, "vqshrn.u64", v2i32, v2i64, NEONvqshrnu>;
2050 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
2051 def VQSHRUN16 : N2VNSh<1, 1, 0b001000, 0b1000, 0, 0, 1,
2052 IIC_VSHLi4D, "vqshrun.s16", v8i8, v8i16, NEONvqshrnsu>;
2053 def VQSHRUN32 : N2VNSh<1, 1, 0b010000, 0b1000, 0, 0, 1,
2054 IIC_VSHLi4D, "vqshrun.s32", v4i16, v4i32, NEONvqshrnsu>;
2055 def VQSHRUN64 : N2VNSh<1, 1, 0b100000, 0b1000, 0, 0, 1,
2056 IIC_VSHLi4D, "vqshrun.s64", v2i32, v2i64, NEONvqshrnsu>;
2058 // VQRSHL : Vector Saturating Rounding Shift
2059 defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2060 IIC_VSHLi4Q, "vqrshl.s", int_arm_neon_vqrshifts, 0>;
2061 defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2062 IIC_VSHLi4Q, "vqrshl.u", int_arm_neon_vqrshiftu, 0>;
2064 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
2065 def VQRSHRNs16: N2VNSh<0, 1, 0b001000, 0b1001, 0, 1, 1,
2066 IIC_VSHLi4D, "vqrshrn.s16", v8i8, v8i16, NEONvqrshrns>;
2067 def VQRSHRNs32: N2VNSh<0, 1, 0b010000, 0b1001, 0, 1, 1,
2068 IIC_VSHLi4D, "vqrshrn.s32", v4i16, v4i32, NEONvqrshrns>;
2069 def VQRSHRNs64: N2VNSh<0, 1, 0b100000, 0b1001, 0, 1, 1,
2070 IIC_VSHLi4D, "vqrshrn.s64", v2i32, v2i64, NEONvqrshrns>;
2071 def VQRSHRNu16: N2VNSh<1, 1, 0b001000, 0b1001, 0, 1, 1,
2072 IIC_VSHLi4D, "vqrshrn.u16", v8i8, v8i16, NEONvqrshrnu>;
2073 def VQRSHRNu32: N2VNSh<1, 1, 0b010000, 0b1001, 0, 1, 1,
2074 IIC_VSHLi4D, "vqrshrn.u32", v4i16, v4i32, NEONvqrshrnu>;
2075 def VQRSHRNu64: N2VNSh<1, 1, 0b100000, 0b1001, 0, 1, 1,
2076 IIC_VSHLi4D, "vqrshrn.u64", v2i32, v2i64, NEONvqrshrnu>;
2078 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
2079 def VQRSHRUN16: N2VNSh<1, 1, 0b001000, 0b1000, 0, 1, 1,
2080 IIC_VSHLi4D, "vqrshrun.s16", v8i8, v8i16, NEONvqrshrnsu>;
2081 def VQRSHRUN32: N2VNSh<1, 1, 0b010000, 0b1000, 0, 1, 1,
2082 IIC_VSHLi4D, "vqrshrun.s32", v4i16, v4i32, NEONvqrshrnsu>;
2083 def VQRSHRUN64: N2VNSh<1, 1, 0b100000, 0b1000, 0, 1, 1,
2084 IIC_VSHLi4D, "vqrshrun.s64", v2i32, v2i64, NEONvqrshrnsu>;
2086 // VSRA : Vector Shift Right and Accumulate
2087 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra.s", NEONvshrs>;
2088 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra.u", NEONvshru>;
2089 // VRSRA : Vector Rounding Shift Right and Accumulate
2090 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra.s", NEONvrshrs>;
2091 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra.u", NEONvrshru>;
2093 // VSLI : Vector Shift Left and Insert
2094 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli.", NEONvsli>;
2095 // VSRI : Vector Shift Right and Insert
2096 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri.", NEONvsri>;
2098 // Vector Absolute and Saturating Absolute.
2100 // VABS : Vector Absolute Value
2101 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
2102 IIC_VUNAiD, IIC_VUNAiQ, "vabs.s",
2104 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2105 IIC_VUNAD, "vabs.f32",
2106 v2f32, v2f32, int_arm_neon_vabs>;
2107 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2108 IIC_VUNAQ, "vabs.f32",
2109 v4f32, v4f32, int_arm_neon_vabs>;
2111 // VQABS : Vector Saturating Absolute Value
2112 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
2113 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs.s",
2114 int_arm_neon_vqabs>;
2118 def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
2119 def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>;
2121 class VNEGD<bits<2> size, string OpcodeStr, ValueType Ty>
2122 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
2123 IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "",
2124 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>;
2125 class VNEGQ<bits<2> size, string OpcodeStr, ValueType Ty>
2126 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
2127 IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "",
2128 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>;
2130 // VNEG : Vector Negate
2131 def VNEGs8d : VNEGD<0b00, "vneg.s8", v8i8>;
2132 def VNEGs16d : VNEGD<0b01, "vneg.s16", v4i16>;
2133 def VNEGs32d : VNEGD<0b10, "vneg.s32", v2i32>;
2134 def VNEGs8q : VNEGQ<0b00, "vneg.s8", v16i8>;
2135 def VNEGs16q : VNEGQ<0b01, "vneg.s16", v8i16>;
2136 def VNEGs32q : VNEGQ<0b10, "vneg.s32", v4i32>;
2138 // VNEG : Vector Negate (floating-point)
2139 def VNEGf32d : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
2140 (outs DPR:$dst), (ins DPR:$src), IIC_VUNAD,
2141 "vneg.f32\t$dst, $src", "",
2142 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
2143 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
2144 (outs QPR:$dst), (ins QPR:$src), IIC_VUNAQ,
2145 "vneg.f32\t$dst, $src", "",
2146 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
2148 def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
2149 def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
2150 def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>;
2151 def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>;
2152 def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>;
2153 def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>;
2155 // VQNEG : Vector Saturating Negate
2156 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
2157 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg.s",
2158 int_arm_neon_vqneg>;
2160 // Vector Bit Counting Operations.
2162 // VCLS : Vector Count Leading Sign Bits
2163 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
2164 IIC_VCNTiD, IIC_VCNTiQ, "vcls.s",
2166 // VCLZ : Vector Count Leading Zeros
2167 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
2168 IIC_VCNTiD, IIC_VCNTiQ, "vclz.i",
2170 // VCNT : Vector Count One Bits
2171 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2172 IIC_VCNTiD, "vcnt.8",
2173 v8i8, v8i8, int_arm_neon_vcnt>;
2174 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2175 IIC_VCNTiQ, "vcnt.8",
2176 v16i8, v16i8, int_arm_neon_vcnt>;
2178 // Vector Move Operations.
2180 // VMOV : Vector Move (Register)
2182 def VMOVD : N3V<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
2183 IIC_VMOVD, "vmov\t$dst, $src", "", []>;
2184 def VMOVQ : N3V<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
2185 IIC_VMOVD, "vmov\t$dst, $src", "", []>;
2187 // VMOV : Vector Move (Immediate)
2189 // VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
2190 def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
2191 return ARM::getVMOVImm(N, 1, *CurDAG);
2193 def vmovImm8 : PatLeaf<(build_vector), [{
2194 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
2197 // VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
2198 def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
2199 return ARM::getVMOVImm(N, 2, *CurDAG);
2201 def vmovImm16 : PatLeaf<(build_vector), [{
2202 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
2203 }], VMOV_get_imm16>;
2205 // VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
2206 def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
2207 return ARM::getVMOVImm(N, 4, *CurDAG);
2209 def vmovImm32 : PatLeaf<(build_vector), [{
2210 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
2211 }], VMOV_get_imm32>;
2213 // VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
2214 def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
2215 return ARM::getVMOVImm(N, 8, *CurDAG);
2217 def vmovImm64 : PatLeaf<(build_vector), [{
2218 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
2219 }], VMOV_get_imm64>;
2221 // Note: Some of the cmode bits in the following VMOV instructions need to
2222 // be encoded based on the immed values.
2224 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
2225 (ins i8imm:$SIMM), IIC_VMOVImm,
2226 "vmov.i8\t$dst, $SIMM", "",
2227 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
2228 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
2229 (ins i8imm:$SIMM), IIC_VMOVImm,
2230 "vmov.i8\t$dst, $SIMM", "",
2231 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
2233 def VMOVv4i16 : N1ModImm<1, 0b000, 0b1000, 0, 0, 0, 1, (outs DPR:$dst),
2234 (ins i16imm:$SIMM), IIC_VMOVImm,
2235 "vmov.i16\t$dst, $SIMM", "",
2236 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
2237 def VMOVv8i16 : N1ModImm<1, 0b000, 0b1000, 0, 1, 0, 1, (outs QPR:$dst),
2238 (ins i16imm:$SIMM), IIC_VMOVImm,
2239 "vmov.i16\t$dst, $SIMM", "",
2240 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
2242 def VMOVv2i32 : N1ModImm<1, 0b000, 0b0000, 0, 0, 0, 1, (outs DPR:$dst),
2243 (ins i32imm:$SIMM), IIC_VMOVImm,
2244 "vmov.i32\t$dst, $SIMM", "",
2245 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
2246 def VMOVv4i32 : N1ModImm<1, 0b000, 0b0000, 0, 1, 0, 1, (outs QPR:$dst),
2247 (ins i32imm:$SIMM), IIC_VMOVImm,
2248 "vmov.i32\t$dst, $SIMM", "",
2249 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
2251 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
2252 (ins i64imm:$SIMM), IIC_VMOVImm,
2253 "vmov.i64\t$dst, $SIMM", "",
2254 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
2255 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
2256 (ins i64imm:$SIMM), IIC_VMOVImm,
2257 "vmov.i64\t$dst, $SIMM", "",
2258 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
2260 // VMOV : Vector Get Lane (move scalar to ARM core register)
2262 def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00,
2263 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2264 IIC_VMOVSI, "vmov", ".s8\t$dst, $src[$lane]",
2265 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
2267 def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01,
2268 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2269 IIC_VMOVSI, "vmov", ".s16\t$dst, $src[$lane]",
2270 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
2272 def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00,
2273 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2274 IIC_VMOVSI, "vmov", ".u8\t$dst, $src[$lane]",
2275 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
2277 def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01,
2278 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2279 IIC_VMOVSI, "vmov", ".u16\t$dst, $src[$lane]",
2280 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
2282 def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00,
2283 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2284 IIC_VMOVSI, "vmov", ".32\t$dst, $src[$lane]",
2285 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
2287 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
2288 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
2289 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2290 (DSubReg_i8_reg imm:$lane))),
2291 (SubReg_i8_lane imm:$lane))>;
2292 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
2293 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2294 (DSubReg_i16_reg imm:$lane))),
2295 (SubReg_i16_lane imm:$lane))>;
2296 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
2297 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2298 (DSubReg_i8_reg imm:$lane))),
2299 (SubReg_i8_lane imm:$lane))>;
2300 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
2301 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2302 (DSubReg_i16_reg imm:$lane))),
2303 (SubReg_i16_lane imm:$lane))>;
2304 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
2305 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
2306 (DSubReg_i32_reg imm:$lane))),
2307 (SubReg_i32_lane imm:$lane))>;
2308 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
2309 (EXTRACT_SUBREG (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2),
2310 (SSubReg_f32_reg imm:$src2))>;
2311 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
2312 (EXTRACT_SUBREG (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2),
2313 (SSubReg_f32_reg imm:$src2))>;
2314 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
2315 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2316 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
2317 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2320 // VMOV : Vector Set Lane (move ARM core register to scalar)
2322 let Constraints = "$src1 = $dst" in {
2323 def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst),
2324 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2325 IIC_VMOVISL, "vmov", ".8\t$dst[$lane], $src2",
2326 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
2327 GPR:$src2, imm:$lane))]>;
2328 def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst),
2329 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2330 IIC_VMOVISL, "vmov", ".16\t$dst[$lane], $src2",
2331 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
2332 GPR:$src2, imm:$lane))]>;
2333 def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst),
2334 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2335 IIC_VMOVISL, "vmov", ".32\t$dst[$lane], $src2",
2336 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
2337 GPR:$src2, imm:$lane))]>;
2339 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
2340 (v16i8 (INSERT_SUBREG QPR:$src1,
2341 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
2342 (DSubReg_i8_reg imm:$lane))),
2343 GPR:$src2, (SubReg_i8_lane imm:$lane)),
2344 (DSubReg_i8_reg imm:$lane)))>;
2345 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
2346 (v8i16 (INSERT_SUBREG QPR:$src1,
2347 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
2348 (DSubReg_i16_reg imm:$lane))),
2349 GPR:$src2, (SubReg_i16_lane imm:$lane)),
2350 (DSubReg_i16_reg imm:$lane)))>;
2351 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
2352 (v4i32 (INSERT_SUBREG QPR:$src1,
2353 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
2354 (DSubReg_i32_reg imm:$lane))),
2355 GPR:$src2, (SubReg_i32_lane imm:$lane)),
2356 (DSubReg_i32_reg imm:$lane)))>;
2358 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
2359 (INSERT_SUBREG (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2),
2360 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
2361 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
2362 (INSERT_SUBREG (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2),
2363 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
2365 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
2366 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
2367 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
2368 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
2370 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
2371 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
2372 def : Pat<(v2f64 (scalar_to_vector DPR:$src)),
2373 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, arm_dsubreg_0)>;
2374 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
2375 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
2377 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
2378 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2379 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
2380 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2381 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
2382 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2384 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
2385 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
2386 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2388 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
2389 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
2390 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2392 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
2393 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
2394 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2397 // VDUP : Vector Duplicate (from ARM core register to all elements)
2399 class VDUPD<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
2400 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
2401 IIC_VMOVIS, "vdup", !strconcat(asmSize, "\t$dst, $src"),
2402 [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
2403 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
2404 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
2405 IIC_VMOVIS, "vdup", !strconcat(asmSize, "\t$dst, $src"),
2406 [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
2408 def VDUP8d : VDUPD<0b11101100, 0b00, ".8", v8i8>;
2409 def VDUP16d : VDUPD<0b11101000, 0b01, ".16", v4i16>;
2410 def VDUP32d : VDUPD<0b11101000, 0b00, ".32", v2i32>;
2411 def VDUP8q : VDUPQ<0b11101110, 0b00, ".8", v16i8>;
2412 def VDUP16q : VDUPQ<0b11101010, 0b01, ".16", v8i16>;
2413 def VDUP32q : VDUPQ<0b11101010, 0b00, ".32", v4i32>;
2415 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
2416 IIC_VMOVIS, "vdup", ".32\t$dst, $src",
2417 [(set DPR:$dst, (v2f32 (NEONvdup
2418 (f32 (bitconvert GPR:$src)))))]>;
2419 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
2420 IIC_VMOVIS, "vdup", ".32\t$dst, $src",
2421 [(set QPR:$dst, (v4f32 (NEONvdup
2422 (f32 (bitconvert GPR:$src)))))]>;
2424 // VDUP : Vector Duplicate Lane (from scalar to all elements)
2426 class VDUPLND<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty>
2427 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
2428 (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
2429 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
2430 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
2432 class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr,
2433 ValueType ResTy, ValueType OpTy>
2434 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
2435 (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
2436 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
2437 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src), imm:$lane)))]>;
2439 def VDUPLN8d : VDUPLND<0b00, 0b01, "vdup.8", v8i8>;
2440 def VDUPLN16d : VDUPLND<0b00, 0b10, "vdup.16", v4i16>;
2441 def VDUPLN32d : VDUPLND<0b01, 0b00, "vdup.32", v2i32>;
2442 def VDUPLNfd : VDUPLND<0b01, 0b00, "vdup.32", v2f32>;
2443 def VDUPLN8q : VDUPLNQ<0b00, 0b01, "vdup.8", v16i8, v8i8>;
2444 def VDUPLN16q : VDUPLNQ<0b00, 0b10, "vdup.16", v8i16, v4i16>;
2445 def VDUPLN32q : VDUPLNQ<0b01, 0b00, "vdup.32", v4i32, v2i32>;
2446 def VDUPLNfq : VDUPLNQ<0b01, 0b00, "vdup.32", v4f32, v2f32>;
2448 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
2449 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
2450 (DSubReg_i8_reg imm:$lane))),
2451 (SubReg_i8_lane imm:$lane)))>;
2452 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
2453 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
2454 (DSubReg_i16_reg imm:$lane))),
2455 (SubReg_i16_lane imm:$lane)))>;
2456 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
2457 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
2458 (DSubReg_i32_reg imm:$lane))),
2459 (SubReg_i32_lane imm:$lane)))>;
2460 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
2461 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
2462 (DSubReg_i32_reg imm:$lane))),
2463 (SubReg_i32_lane imm:$lane)))>;
2465 def VDUPfdf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 0, 0,
2466 (outs DPR:$dst), (ins SPR:$src),
2467 IIC_VMOVD, "vdup.32\t$dst, ${src:lane}", "",
2468 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
2470 def VDUPfqf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 1, 0,
2471 (outs QPR:$dst), (ins SPR:$src),
2472 IIC_VMOVD, "vdup.32\t$dst, ${src:lane}", "",
2473 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
2475 def : Pat<(v2i64 (NEONvduplane (v2i64 QPR:$src), imm:$lane)),
2476 (INSERT_SUBREG QPR:$src,
2477 (i64 (EXTRACT_SUBREG QPR:$src, (DSubReg_f64_reg imm:$lane))),
2478 (DSubReg_f64_other_reg imm:$lane))>;
2479 def : Pat<(v2f64 (NEONvduplane (v2f64 QPR:$src), imm:$lane)),
2480 (INSERT_SUBREG QPR:$src,
2481 (f64 (EXTRACT_SUBREG QPR:$src, (DSubReg_f64_reg imm:$lane))),
2482 (DSubReg_f64_other_reg imm:$lane))>;
2484 // VMOVN : Vector Narrowing Move
2485 defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVD, "vmovn.i",
2486 int_arm_neon_vmovn>;
2487 // VQMOVN : Vector Saturating Narrowing Move
2488 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD, "vqmovn.s",
2489 int_arm_neon_vqmovns>;
2490 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD, "vqmovn.u",
2491 int_arm_neon_vqmovnu>;
2492 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD, "vqmovun.s",
2493 int_arm_neon_vqmovnsu>;
2494 // VMOVL : Vector Lengthening Move
2495 defm VMOVLs : N2VLInt_QHS<0,1,0b1010,0,0,1, "vmovl.s", int_arm_neon_vmovls>;
2496 defm VMOVLu : N2VLInt_QHS<1,1,0b1010,0,0,1, "vmovl.u", int_arm_neon_vmovlu>;
2498 // Vector Conversions.
2500 // VCVT : Vector Convert Between Floating-Point and Integers
2501 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
2502 v2i32, v2f32, fp_to_sint>;
2503 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
2504 v2i32, v2f32, fp_to_uint>;
2505 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
2506 v2f32, v2i32, sint_to_fp>;
2507 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
2508 v2f32, v2i32, uint_to_fp>;
2510 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
2511 v4i32, v4f32, fp_to_sint>;
2512 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
2513 v4i32, v4f32, fp_to_uint>;
2514 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
2515 v4f32, v4i32, sint_to_fp>;
2516 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
2517 v4f32, v4i32, uint_to_fp>;
2519 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
2520 // Note: Some of the opcode bits in the following VCVT instructions need to
2521 // be encoded based on the immed values.
2522 def VCVTf2xsd : N2VCvtD<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
2523 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
2524 def VCVTf2xud : N2VCvtD<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
2525 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
2526 def VCVTxs2fd : N2VCvtD<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
2527 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
2528 def VCVTxu2fd : N2VCvtD<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
2529 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
2531 def VCVTf2xsq : N2VCvtQ<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
2532 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
2533 def VCVTf2xuq : N2VCvtQ<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
2534 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
2535 def VCVTxs2fq : N2VCvtQ<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
2536 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
2537 def VCVTxu2fq : N2VCvtQ<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
2538 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
2542 // VREV64 : Vector Reverse elements within 64-bit doublewords
2544 class VREV64D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2545 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
2546 (ins DPR:$src), IIC_VMOVD,
2547 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2548 [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
2549 class VREV64Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2550 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
2551 (ins QPR:$src), IIC_VMOVD,
2552 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2553 [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
2555 def VREV64d8 : VREV64D<0b00, "vrev64.8", v8i8>;
2556 def VREV64d16 : VREV64D<0b01, "vrev64.16", v4i16>;
2557 def VREV64d32 : VREV64D<0b10, "vrev64.32", v2i32>;
2558 def VREV64df : VREV64D<0b10, "vrev64.32", v2f32>;
2560 def VREV64q8 : VREV64Q<0b00, "vrev64.8", v16i8>;
2561 def VREV64q16 : VREV64Q<0b01, "vrev64.16", v8i16>;
2562 def VREV64q32 : VREV64Q<0b10, "vrev64.32", v4i32>;
2563 def VREV64qf : VREV64Q<0b10, "vrev64.32", v4f32>;
2565 // VREV32 : Vector Reverse elements within 32-bit words
2567 class VREV32D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2568 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
2569 (ins DPR:$src), IIC_VMOVD,
2570 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2571 [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
2572 class VREV32Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2573 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
2574 (ins QPR:$src), IIC_VMOVD,
2575 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2576 [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
2578 def VREV32d8 : VREV32D<0b00, "vrev32.8", v8i8>;
2579 def VREV32d16 : VREV32D<0b01, "vrev32.16", v4i16>;
2581 def VREV32q8 : VREV32Q<0b00, "vrev32.8", v16i8>;
2582 def VREV32q16 : VREV32Q<0b01, "vrev32.16", v8i16>;
2584 // VREV16 : Vector Reverse elements within 16-bit halfwords
2586 class VREV16D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2587 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
2588 (ins DPR:$src), IIC_VMOVD,
2589 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2590 [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
2591 class VREV16Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2592 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
2593 (ins QPR:$src), IIC_VMOVD,
2594 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2595 [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
2597 def VREV16d8 : VREV16D<0b00, "vrev16.8", v8i8>;
2598 def VREV16q8 : VREV16Q<0b00, "vrev16.8", v16i8>;
2600 // Other Vector Shuffles.
2602 // VEXT : Vector Extract
2604 class VEXTd<string OpcodeStr, ValueType Ty>
2605 : N3V<0,1,0b11,0b0000,0,0, (outs DPR:$dst),
2606 (ins DPR:$lhs, DPR:$rhs, i32imm:$index), IIC_VEXTD,
2607 !strconcat(OpcodeStr, "\t$dst, $lhs, $rhs, $index"), "",
2608 [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
2609 (Ty DPR:$rhs), imm:$index)))]>;
2611 class VEXTq<string OpcodeStr, ValueType Ty>
2612 : N3V<0,1,0b11,0b0000,1,0, (outs QPR:$dst),
2613 (ins QPR:$lhs, QPR:$rhs, i32imm:$index), IIC_VEXTQ,
2614 !strconcat(OpcodeStr, "\t$dst, $lhs, $rhs, $index"), "",
2615 [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
2616 (Ty QPR:$rhs), imm:$index)))]>;
2618 def VEXTd8 : VEXTd<"vext.8", v8i8>;
2619 def VEXTd16 : VEXTd<"vext.16", v4i16>;
2620 def VEXTd32 : VEXTd<"vext.32", v2i32>;
2621 def VEXTdf : VEXTd<"vext.32", v2f32>;
2623 def VEXTq8 : VEXTq<"vext.8", v16i8>;
2624 def VEXTq16 : VEXTq<"vext.16", v8i16>;
2625 def VEXTq32 : VEXTq<"vext.32", v4i32>;
2626 def VEXTqf : VEXTq<"vext.32", v4f32>;
2628 // VTRN : Vector Transpose
2630 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn.8">;
2631 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn.16">;
2632 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn.32">;
2634 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn.8">;
2635 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn.16">;
2636 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn.32">;
2638 // VUZP : Vector Unzip (Deinterleave)
2640 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp.8">;
2641 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp.16">;
2642 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp.32">;
2644 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp.8">;
2645 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp.16">;
2646 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp.32">;
2648 // VZIP : Vector Zip (Interleave)
2650 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip.8">;
2651 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip.16">;
2652 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip.32">;
2654 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip.8">;
2655 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip.16">;
2656 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip.32">;
2658 // Vector Table Lookup and Table Extension.
2660 // VTBL : Vector Table Lookup
2662 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
2663 (ins DPR:$tbl1, DPR:$src), IIC_VTB1,
2664 "vtbl.8\t$dst, \\{$tbl1\\}, $src", "",
2665 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
2666 let hasExtraSrcRegAllocReq = 1 in {
2668 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
2669 (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTB2,
2670 "vtbl.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "",
2671 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl2
2672 DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
2674 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
2675 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTB3,
2676 "vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "",
2677 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl3
2678 DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
2680 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
2681 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTB4,
2682 "vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "",
2683 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl4 DPR:$tbl1, DPR:$tbl2,
2684 DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
2685 } // hasExtraSrcRegAllocReq = 1
2687 // VTBX : Vector Table Extension
2689 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
2690 (ins DPR:$orig, DPR:$tbl1, DPR:$src), IIC_VTBX1,
2691 "vtbx.8\t$dst, \\{$tbl1\\}, $src", "$orig = $dst",
2692 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
2693 DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
2694 let hasExtraSrcRegAllocReq = 1 in {
2696 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
2697 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTBX2,
2698 "vtbx.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "$orig = $dst",
2699 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx2
2700 DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
2702 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
2703 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTBX3,
2704 "vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "$orig = $dst",
2705 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx3 DPR:$orig, DPR:$tbl1,
2706 DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
2708 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
2709 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTBX4,
2710 "vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "$orig = $dst",
2711 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx4 DPR:$orig, DPR:$tbl1,
2712 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
2713 } // hasExtraSrcRegAllocReq = 1
2715 //===----------------------------------------------------------------------===//
2716 // NEON instructions for single-precision FP math
2717 //===----------------------------------------------------------------------===//
2719 // These need separate instructions because they must use DPR_VFP2 register
2720 // class which have SPR sub-registers.
2722 // Vector Add Operations used for single-precision FP
2723 let neverHasSideEffects = 1 in
2724 def VADDfd_sfp : N3VDs<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd,1>;
2725 def : N3VDsPat<fadd, VADDfd_sfp>;
2727 // Vector Sub Operations used for single-precision FP
2728 let neverHasSideEffects = 1 in
2729 def VSUBfd_sfp : N3VDs<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub,0>;
2730 def : N3VDsPat<fsub, VSUBfd_sfp>;
2732 // Vector Multiply Operations used for single-precision FP
2733 let neverHasSideEffects = 1 in
2734 def VMULfd_sfp : N3VDs<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul,1>;
2735 def : N3VDsPat<fmul, VMULfd_sfp>;
2737 // Vector Multiply-Accumulate/Subtract used for single-precision FP
2738 let neverHasSideEffects = 1 in
2739 def VMLAfd_sfp : N3VDMulOps<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla.f32", v2f32,fmul,fadd>;
2740 def : N3VDMulOpsPat<fmul, fadd, VMLAfd_sfp>;
2742 let neverHasSideEffects = 1 in
2743 def VMLSfd_sfp : N3VDMulOps<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls.f32", v2f32,fmul,fsub>;
2744 def : N3VDMulOpsPat<fmul, fsub, VMLSfd_sfp>;
2746 // Vector Absolute used for single-precision FP
2747 let neverHasSideEffects = 1 in
2748 def VABSfd_sfp : N2VDInts<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2749 IIC_VUNAD, "vabs.f32",
2750 v2f32, v2f32, int_arm_neon_vabs>;
2751 def : N2VDIntsPat<fabs, VABSfd_sfp>;
2753 // Vector Negate used for single-precision FP
2754 let neverHasSideEffects = 1 in
2755 def VNEGf32d_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
2756 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
2757 "vneg.f32\t$dst, $src", "", []>;
2758 def : N2VDIntsPat<fneg, VNEGf32d_sfp>;
2760 // Vector Convert between single-precision FP and integer
2761 let neverHasSideEffects = 1 in
2762 def VCVTf2sd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
2763 v2i32, v2f32, fp_to_sint>;
2764 def : N2VDsPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
2766 let neverHasSideEffects = 1 in
2767 def VCVTf2ud_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
2768 v2i32, v2f32, fp_to_uint>;
2769 def : N2VDsPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
2771 let neverHasSideEffects = 1 in
2772 def VCVTs2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
2773 v2f32, v2i32, sint_to_fp>;
2774 def : N2VDsPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
2776 let neverHasSideEffects = 1 in
2777 def VCVTu2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
2778 v2f32, v2i32, uint_to_fp>;
2779 def : N2VDsPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
2781 //===----------------------------------------------------------------------===//
2782 // Non-Instruction Patterns
2783 //===----------------------------------------------------------------------===//
2786 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
2787 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
2788 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
2789 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
2790 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
2791 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
2792 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
2793 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
2794 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
2795 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
2796 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
2797 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
2798 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
2799 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
2800 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
2801 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
2802 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
2803 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
2804 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
2805 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
2806 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
2807 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
2808 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
2809 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
2810 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
2811 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
2812 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
2813 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
2814 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
2815 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
2817 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
2818 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
2819 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
2820 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
2821 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
2822 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
2823 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
2824 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
2825 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
2826 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
2827 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
2828 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
2829 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
2830 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
2831 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
2832 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
2833 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
2834 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
2835 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
2836 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
2837 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
2838 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
2839 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
2840 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
2841 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
2842 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
2843 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
2844 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
2845 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
2846 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;