1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def NEONvduplaneq : SDNode<"ARMISD::VDUPLANEQ",
69 SDTypeProfile<1, 2, [SDTCisVT<2, i32>]>>;
71 def SDTARMVLD2 : SDTypeProfile<2, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
72 def SDTARMVLD3 : SDTypeProfile<3, 1, [SDTCisSameAs<0, 1>,
73 SDTCisSameAs<0, 2>, SDTCisPtrTy<3>]>;
74 def SDTARMVLD4 : SDTypeProfile<4, 1, [SDTCisSameAs<0, 1>,
76 SDTCisSameAs<0, 3>, SDTCisPtrTy<4>]>;
77 def NEONvld2d : SDNode<"ARMISD::VLD2D", SDTARMVLD2,
78 [SDNPHasChain, SDNPMayLoad]>;
79 def NEONvld3d : SDNode<"ARMISD::VLD3D", SDTARMVLD3,
80 [SDNPHasChain, SDNPMayLoad]>;
81 def NEONvld4d : SDNode<"ARMISD::VLD4D", SDTARMVLD4,
82 [SDNPHasChain, SDNPMayLoad]>;
84 def SDTARMVST2 : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>]>;
85 def SDTARMVST3 : SDTypeProfile<0, 4, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
87 def SDTARMVST4 : SDTypeProfile<0, 5, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
91 def NEONvst2d : SDNode<"ARMISD::VST2D", SDTARMVST2,
92 [SDNPHasChain, SDNPMayStore]>;
93 def NEONvst3d : SDNode<"ARMISD::VST3D", SDTARMVST3,
94 [SDNPHasChain, SDNPMayStore]>;
95 def NEONvst4d : SDNode<"ARMISD::VST4D", SDTARMVST4,
96 [SDNPHasChain, SDNPMayStore]>;
98 //===----------------------------------------------------------------------===//
99 // NEON operand definitions
100 //===----------------------------------------------------------------------===//
102 // addrmode_neonldstm := reg
104 /* TODO: Take advantage of vldm.
105 def addrmode_neonldstm : Operand<i32>,
106 ComplexPattern<i32, 2, "SelectAddrModeNeonLdStM", []> {
107 let PrintMethod = "printAddrNeonLdStMOperand";
108 let MIOperandInfo = (ops GPR, i32imm);
112 //===----------------------------------------------------------------------===//
113 // NEON load / store instructions
114 //===----------------------------------------------------------------------===//
116 /* TODO: Take advantage of vldm.
118 def VLDMD : NI<(outs),
119 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
121 "vldm${addr:submode} ${addr:base}, $dst1",
123 let Inst{27-25} = 0b110;
125 let Inst{11-9} = 0b101;
128 def VLDMS : NI<(outs),
129 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
131 "vldm${addr:submode} ${addr:base}, $dst1",
133 let Inst{27-25} = 0b110;
135 let Inst{11-9} = 0b101;
140 // Use vldmia to load a Q register as a D register pair.
141 def VLDRQ : NI<(outs QPR:$dst), (ins GPR:$addr),
143 "vldmia $addr, ${dst:dregpair}",
144 [(set QPR:$dst, (v2f64 (load GPR:$addr)))]> {
145 let Inst{27-25} = 0b110;
146 let Inst{24} = 0; // P bit
147 let Inst{23} = 1; // U bit
149 let Inst{11-9} = 0b101;
152 // Use vstmia to store a Q register as a D register pair.
153 def VSTRQ : NI<(outs), (ins QPR:$src, GPR:$addr),
155 "vstmia $addr, ${src:dregpair}",
156 [(store (v2f64 QPR:$src), GPR:$addr)]> {
157 let Inst{27-25} = 0b110;
158 let Inst{24} = 0; // P bit
159 let Inst{23} = 1; // U bit
161 let Inst{11-9} = 0b101;
165 // VLD1 : Vector Load (multiple single elements)
166 class VLD1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
167 : NLdSt<(outs DPR:$dst), (ins addrmode6:$addr),
169 !strconcat(OpcodeStr, "\t\\{$dst\\}, $addr"),
170 [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
171 class VLD1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
172 : NLdSt<(outs QPR:$dst), (ins addrmode6:$addr),
174 !strconcat(OpcodeStr, "\t${dst:dregpair}, $addr"),
175 [(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
177 def VLD1d8 : VLD1D<"vld1.8", v8i8, int_arm_neon_vld1i>;
178 def VLD1d16 : VLD1D<"vld1.16", v4i16, int_arm_neon_vld1i>;
179 def VLD1d32 : VLD1D<"vld1.32", v2i32, int_arm_neon_vld1i>;
180 def VLD1df : VLD1D<"vld1.32", v2f32, int_arm_neon_vld1f>;
181 def VLD1d64 : VLD1D<"vld1.64", v1i64, int_arm_neon_vld1i>;
183 def VLD1q8 : VLD1Q<"vld1.8", v16i8, int_arm_neon_vld1i>;
184 def VLD1q16 : VLD1Q<"vld1.16", v8i16, int_arm_neon_vld1i>;
185 def VLD1q32 : VLD1Q<"vld1.32", v4i32, int_arm_neon_vld1i>;
186 def VLD1qf : VLD1Q<"vld1.32", v4f32, int_arm_neon_vld1f>;
187 def VLD1q64 : VLD1Q<"vld1.64", v2i64, int_arm_neon_vld1i>;
189 // VLD2 : Vector Load (multiple 2-element structures)
190 class VLD2D<string OpcodeStr>
191 : NLdSt<(outs DPR:$dst1, DPR:$dst2), (ins addrmode6:$addr),
193 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2\\}, $addr"), []>;
195 def VLD2d8 : VLD2D<"vld2.8">;
196 def VLD2d16 : VLD2D<"vld2.16">;
197 def VLD2d32 : VLD2D<"vld2.32">;
199 // VLD3 : Vector Load (multiple 3-element structures)
200 class VLD3D<string OpcodeStr>
201 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3), (ins addrmode6:$addr),
203 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"), []>;
205 def VLD3d8 : VLD3D<"vld3.8">;
206 def VLD3d16 : VLD3D<"vld3.16">;
207 def VLD3d32 : VLD3D<"vld3.32">;
209 // VLD4 : Vector Load (multiple 4-element structures)
210 class VLD4D<string OpcodeStr>
211 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
212 (ins addrmode6:$addr),
214 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"), []>;
216 def VLD4d8 : VLD4D<"vld4.8">;
217 def VLD4d16 : VLD4D<"vld4.16">;
218 def VLD4d32 : VLD4D<"vld4.32">;
220 // VST1 : Vector Store (multiple single elements)
221 class VST1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
222 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src),
224 !strconcat(OpcodeStr, "\t\\{$src\\}, $addr"),
225 [(IntOp addrmode6:$addr, (Ty DPR:$src))]>;
226 class VST1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
227 : NLdSt<(outs), (ins addrmode6:$addr, QPR:$src),
229 !strconcat(OpcodeStr, "\t${src:dregpair}, $addr"),
230 [(IntOp addrmode6:$addr, (Ty QPR:$src))]>;
232 def VST1d8 : VST1D<"vst1.8", v8i8, int_arm_neon_vst1i>;
233 def VST1d16 : VST1D<"vst1.16", v4i16, int_arm_neon_vst1i>;
234 def VST1d32 : VST1D<"vst1.32", v2i32, int_arm_neon_vst1i>;
235 def VST1df : VST1D<"vst1.32", v2f32, int_arm_neon_vst1f>;
236 def VST1d64 : VST1D<"vst1.64", v1i64, int_arm_neon_vst1i>;
238 def VST1q8 : VST1Q<"vst1.8", v16i8, int_arm_neon_vst1i>;
239 def VST1q16 : VST1Q<"vst1.16", v8i16, int_arm_neon_vst1i>;
240 def VST1q32 : VST1Q<"vst1.32", v4i32, int_arm_neon_vst1i>;
241 def VST1qf : VST1Q<"vst1.32", v4f32, int_arm_neon_vst1f>;
242 def VST1q64 : VST1Q<"vst1.64", v2i64, int_arm_neon_vst1i>;
244 // VST2 : Vector Store (multiple 2-element structures)
245 class VST2D<string OpcodeStr>
246 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2), NoItinerary,
247 !strconcat(OpcodeStr, "\t\\{$src1,$src2\\}, $addr"), []>;
249 def VST2d8 : VST2D<"vst2.8">;
250 def VST2d16 : VST2D<"vst2.16">;
251 def VST2d32 : VST2D<"vst2.32">;
253 // VST3 : Vector Store (multiple 3-element structures)
254 class VST3D<string OpcodeStr>
255 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
257 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"), []>;
259 def VST3d8 : VST3D<"vst3.8">;
260 def VST3d16 : VST3D<"vst3.16">;
261 def VST3d32 : VST3D<"vst3.32">;
263 // VST4 : Vector Store (multiple 4-element structures)
264 class VST4D<string OpcodeStr>
265 : NLdSt<(outs), (ins addrmode6:$addr,
266 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), NoItinerary,
267 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"), []>;
269 def VST4d8 : VST4D<"vst4.8">;
270 def VST4d16 : VST4D<"vst4.16">;
271 def VST4d32 : VST4D<"vst4.32">;
274 //===----------------------------------------------------------------------===//
275 // NEON pattern fragments
276 //===----------------------------------------------------------------------===//
278 // Extract D sub-registers of Q registers.
279 // (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
280 def SubReg_i8_reg : SDNodeXForm<imm, [{
281 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
283 def SubReg_i16_reg : SDNodeXForm<imm, [{
284 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
286 def SubReg_i32_reg : SDNodeXForm<imm, [{
287 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
289 def SubReg_f64_reg : SDNodeXForm<imm, [{
290 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
293 // Translate lane numbers from Q registers to D subregs.
294 def SubReg_i8_lane : SDNodeXForm<imm, [{
295 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
297 def SubReg_i16_lane : SDNodeXForm<imm, [{
298 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
300 def SubReg_i32_lane : SDNodeXForm<imm, [{
301 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
304 //===----------------------------------------------------------------------===//
305 // Instruction Classes
306 //===----------------------------------------------------------------------===//
308 // Basic 2-register operations, both double- and quad-register.
309 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
310 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
311 ValueType ResTy, ValueType OpTy, SDNode OpNode>
312 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
313 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
314 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
315 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
316 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
317 ValueType ResTy, ValueType OpTy, SDNode OpNode>
318 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
319 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
320 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
322 // Basic 2-register intrinsics, both double- and quad-register.
323 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
324 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
325 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
326 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
327 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
328 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
329 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
330 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
331 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
332 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
333 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
334 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
336 // Basic 2-register operations, scalar single-precision
337 class N2VDInts<SDNode OpNode, NeonI Inst>
338 : NEONFPPat<(f32 (OpNode SPR:$a)),
339 (EXTRACT_SUBREG (COPY_TO_REGCLASS
340 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
341 SPR:$a, arm_ssubreg_0)),
345 // Narrow 2-register intrinsics.
346 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
347 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
348 string OpcodeStr, ValueType TyD, ValueType TyQ, Intrinsic IntOp>
349 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
350 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
351 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
353 // Long 2-register intrinsics. (This is currently only used for VMOVL and is
354 // derived from N2VImm instead of N2V because of the way the size is encoded.)
355 class N2VLInt<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
356 bit op6, bit op4, string OpcodeStr, ValueType TyQ, ValueType TyD,
358 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4, (outs QPR:$dst),
359 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
360 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
362 // Basic 3-register operations, both double- and quad-register.
363 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
364 string OpcodeStr, ValueType ResTy, ValueType OpTy,
365 SDNode OpNode, bit Commutable>
366 : N3V<op24, op23, op21_20, op11_8, 0, op4,
367 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
368 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
369 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
370 let isCommutable = Commutable;
372 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
373 string OpcodeStr, ValueType ResTy, ValueType OpTy,
374 SDNode OpNode, bit Commutable>
375 : N3V<op24, op23, op21_20, op11_8, 1, op4,
376 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
377 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
378 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
379 let isCommutable = Commutable;
382 // Basic 3-register operations, scalar single-precision
383 class N3VDs<SDNode OpNode, NeonI Inst>
384 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
385 (EXTRACT_SUBREG (COPY_TO_REGCLASS
386 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
387 SPR:$a, arm_ssubreg_0),
388 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
389 SPR:$b, arm_ssubreg_0)),
393 // Basic 3-register intrinsics, both double- and quad-register.
394 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
395 string OpcodeStr, ValueType ResTy, ValueType OpTy,
396 Intrinsic IntOp, bit Commutable>
397 : N3V<op24, op23, op21_20, op11_8, 0, op4,
398 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
399 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
400 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
401 let isCommutable = Commutable;
403 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
404 string OpcodeStr, ValueType ResTy, ValueType OpTy,
405 Intrinsic IntOp, bit Commutable>
406 : N3V<op24, op23, op21_20, op11_8, 1, op4,
407 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
408 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
409 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
410 let isCommutable = Commutable;
413 // Multiply-Add/Sub operations, both double- and quad-register.
414 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
415 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
416 : N3V<op24, op23, op21_20, op11_8, 0, op4,
417 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
418 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
419 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
420 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
421 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
422 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
423 : N3V<op24, op23, op21_20, op11_8, 1, op4,
424 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
425 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
426 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
427 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
429 // Multiply-Add/Sub operations, scalar single-precision
430 class N3VDMulOps<SDNode MulNode, SDNode OpNode, NeonI Inst>
431 : NEONFPPat<(f32 (OpNode SPR:$acc,
432 (f32 (MulNode SPR:$a, SPR:$b)))),
433 (EXTRACT_SUBREG (COPY_TO_REGCLASS
434 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
435 SPR:$acc, arm_ssubreg_0),
436 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
437 SPR:$a, arm_ssubreg_0),
438 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
439 SPR:$b, arm_ssubreg_0)),
443 // Neon 3-argument intrinsics, both double- and quad-register.
444 // The destination register is also used as the first source operand register.
445 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
446 string OpcodeStr, ValueType ResTy, ValueType OpTy,
448 : N3V<op24, op23, op21_20, op11_8, 0, op4,
449 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
450 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
451 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
452 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
453 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
454 string OpcodeStr, ValueType ResTy, ValueType OpTy,
456 : N3V<op24, op23, op21_20, op11_8, 1, op4,
457 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
458 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
459 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
460 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
462 // Neon Long 3-argument intrinsic. The destination register is
463 // a quad-register and is also used as the first source operand register.
464 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
465 string OpcodeStr, ValueType TyQ, ValueType TyD, Intrinsic IntOp>
466 : N3V<op24, op23, op21_20, op11_8, 0, op4,
467 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
468 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
470 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
472 // Narrowing 3-register intrinsics.
473 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
474 string OpcodeStr, ValueType TyD, ValueType TyQ,
475 Intrinsic IntOp, bit Commutable>
476 : N3V<op24, op23, op21_20, op11_8, 0, op4,
477 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
478 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
479 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
480 let isCommutable = Commutable;
483 // Long 3-register intrinsics.
484 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
485 string OpcodeStr, ValueType TyQ, ValueType TyD,
486 Intrinsic IntOp, bit Commutable>
487 : N3V<op24, op23, op21_20, op11_8, 0, op4,
488 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
489 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
490 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
491 let isCommutable = Commutable;
494 // Wide 3-register intrinsics.
495 class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
496 string OpcodeStr, ValueType TyQ, ValueType TyD,
497 Intrinsic IntOp, bit Commutable>
498 : N3V<op24, op23, op21_20, op11_8, 0, op4,
499 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), NoItinerary,
500 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
501 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
502 let isCommutable = Commutable;
505 // Pairwise long 2-register intrinsics, both double- and quad-register.
506 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
507 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
508 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
509 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
510 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
511 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
512 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
513 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
514 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
515 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
516 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
517 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
519 // Pairwise long 2-register accumulate intrinsics,
520 // both double- and quad-register.
521 // The destination register is also used as the first source operand register.
522 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
523 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
524 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
525 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
526 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
527 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
528 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
529 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
530 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
531 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
532 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
533 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
534 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
535 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
537 // Shift by immediate,
538 // both double- and quad-register.
539 class N2VDSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
540 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
541 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
542 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
543 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
544 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
545 class N2VQSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
546 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
547 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
548 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
549 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
550 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
552 // Long shift by immediate.
553 class N2VLSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
554 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
555 ValueType OpTy, SDNode OpNode>
556 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
557 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
558 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
559 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
560 (i32 imm:$SIMM))))]>;
562 // Narrow shift by immediate.
563 class N2VNSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
564 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
565 ValueType OpTy, SDNode OpNode>
566 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
567 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
568 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
569 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
570 (i32 imm:$SIMM))))]>;
572 // Shift right by immediate and accumulate,
573 // both double- and quad-register.
574 class N2VDShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
575 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
576 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
577 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
579 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
580 [(set DPR:$dst, (Ty (add DPR:$src1,
581 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
582 class N2VQShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
583 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
584 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
585 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
587 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
588 [(set QPR:$dst, (Ty (add QPR:$src1,
589 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
591 // Shift by immediate and insert,
592 // both double- and quad-register.
593 class N2VDShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
594 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
595 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
596 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
598 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
599 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
600 class N2VQShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
601 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
602 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
603 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
605 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
606 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
608 // Convert, with fractional bits immediate,
609 // both double- and quad-register.
610 class N2VCvtD<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
611 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
613 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
614 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
615 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
616 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
617 class N2VCvtQ<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
618 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
620 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
621 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
622 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
623 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
625 //===----------------------------------------------------------------------===//
627 //===----------------------------------------------------------------------===//
629 // Neon 3-register vector operations.
631 // First with only element sizes of 8, 16 and 32 bits:
632 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
633 string OpcodeStr, SDNode OpNode, bit Commutable = 0> {
634 // 64-bit vector types.
635 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
636 v8i8, v8i8, OpNode, Commutable>;
637 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
638 v4i16, v4i16, OpNode, Commutable>;
639 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
640 v2i32, v2i32, OpNode, Commutable>;
642 // 128-bit vector types.
643 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
644 v16i8, v16i8, OpNode, Commutable>;
645 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
646 v8i16, v8i16, OpNode, Commutable>;
647 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
648 v4i32, v4i32, OpNode, Commutable>;
651 // ....then also with element size 64 bits:
652 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
653 string OpcodeStr, SDNode OpNode, bit Commutable = 0>
654 : N3V_QHS<op24, op23, op11_8, op4, OpcodeStr, OpNode, Commutable> {
655 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
656 v1i64, v1i64, OpNode, Commutable>;
657 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
658 v2i64, v2i64, OpNode, Commutable>;
662 // Neon Narrowing 2-register vector intrinsics,
663 // source operand element sizes of 16, 32 and 64 bits:
664 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
665 bits<5> op11_7, bit op6, bit op4, string OpcodeStr,
667 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
668 !strconcat(OpcodeStr, "16"), v8i8, v8i16, IntOp>;
669 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
670 !strconcat(OpcodeStr, "32"), v4i16, v4i32, IntOp>;
671 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
672 !strconcat(OpcodeStr, "64"), v2i32, v2i64, IntOp>;
676 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
677 // source operand element sizes of 16, 32 and 64 bits:
678 multiclass N2VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
679 bit op4, string OpcodeStr, Intrinsic IntOp> {
680 def v8i16 : N2VLInt<op24, op23, 0b001000, op11_8, op7, op6, op4,
681 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
682 def v4i32 : N2VLInt<op24, op23, 0b010000, op11_8, op7, op6, op4,
683 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
684 def v2i64 : N2VLInt<op24, op23, 0b100000, op11_8, op7, op6, op4,
685 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
689 // Neon 3-register vector intrinsics.
691 // First with only element sizes of 16 and 32 bits:
692 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
693 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
694 // 64-bit vector types.
695 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
696 v4i16, v4i16, IntOp, Commutable>;
697 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
698 v2i32, v2i32, IntOp, Commutable>;
700 // 128-bit vector types.
701 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
702 v8i16, v8i16, IntOp, Commutable>;
703 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
704 v4i32, v4i32, IntOp, Commutable>;
707 // ....then also with element size of 8 bits:
708 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
709 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
710 : N3VInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
711 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
712 v8i8, v8i8, IntOp, Commutable>;
713 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
714 v16i8, v16i8, IntOp, Commutable>;
717 // ....then also with element size of 64 bits:
718 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
719 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
720 : N3VInt_QHS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
721 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
722 v1i64, v1i64, IntOp, Commutable>;
723 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
724 v2i64, v2i64, IntOp, Commutable>;
728 // Neon Narrowing 3-register vector intrinsics,
729 // source operand element sizes of 16, 32 and 64 bits:
730 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
731 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
732 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr,"16"),
733 v8i8, v8i16, IntOp, Commutable>;
734 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"32"),
735 v4i16, v4i32, IntOp, Commutable>;
736 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"64"),
737 v2i32, v2i64, IntOp, Commutable>;
741 // Neon Long 3-register vector intrinsics.
743 // First with only element sizes of 16 and 32 bits:
744 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
745 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
746 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
747 v4i32, v4i16, IntOp, Commutable>;
748 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
749 v2i64, v2i32, IntOp, Commutable>;
752 // ....then also with element size of 8 bits:
753 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
754 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
755 : N3VLInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
756 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
757 v8i16, v8i8, IntOp, Commutable>;
761 // Neon Wide 3-register vector intrinsics,
762 // source operand element sizes of 8, 16 and 32 bits:
763 multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
764 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
765 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
766 v8i16, v8i8, IntOp, Commutable>;
767 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
768 v4i32, v4i16, IntOp, Commutable>;
769 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
770 v2i64, v2i32, IntOp, Commutable>;
774 // Neon Multiply-Op vector operations,
775 // element sizes of 8, 16 and 32 bits:
776 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
777 string OpcodeStr, SDNode OpNode> {
778 // 64-bit vector types.
779 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4,
780 !strconcat(OpcodeStr, "8"), v8i8, mul, OpNode>;
781 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4,
782 !strconcat(OpcodeStr, "16"), v4i16, mul, OpNode>;
783 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4,
784 !strconcat(OpcodeStr, "32"), v2i32, mul, OpNode>;
786 // 128-bit vector types.
787 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4,
788 !strconcat(OpcodeStr, "8"), v16i8, mul, OpNode>;
789 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4,
790 !strconcat(OpcodeStr, "16"), v8i16, mul, OpNode>;
791 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4,
792 !strconcat(OpcodeStr, "32"), v4i32, mul, OpNode>;
796 // Neon 3-argument intrinsics,
797 // element sizes of 8, 16 and 32 bits:
798 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
799 string OpcodeStr, Intrinsic IntOp> {
800 // 64-bit vector types.
801 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4,
802 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
803 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4,
804 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
805 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4,
806 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
808 // 128-bit vector types.
809 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4,
810 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
811 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4,
812 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
813 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4,
814 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
818 // Neon Long 3-argument intrinsics.
820 // First with only element sizes of 16 and 32 bits:
821 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
822 string OpcodeStr, Intrinsic IntOp> {
823 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
824 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
825 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4,
826 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
829 // ....then also with element size of 8 bits:
830 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
831 string OpcodeStr, Intrinsic IntOp>
832 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp> {
833 def v8i16 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
834 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
838 // Neon 2-register vector intrinsics,
839 // element sizes of 8, 16 and 32 bits:
840 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
841 bits<5> op11_7, bit op4, string OpcodeStr,
843 // 64-bit vector types.
844 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
845 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
846 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
847 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
848 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
849 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
851 // 128-bit vector types.
852 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
853 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
854 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
855 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
856 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
857 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
861 // Neon Pairwise long 2-register intrinsics,
862 // element sizes of 8, 16 and 32 bits:
863 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
864 bits<5> op11_7, bit op4,
865 string OpcodeStr, Intrinsic IntOp> {
866 // 64-bit vector types.
867 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
868 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
869 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
870 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
871 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
872 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
874 // 128-bit vector types.
875 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
876 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
877 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
878 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
879 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
880 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
884 // Neon Pairwise long 2-register accumulate intrinsics,
885 // element sizes of 8, 16 and 32 bits:
886 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
887 bits<5> op11_7, bit op4,
888 string OpcodeStr, Intrinsic IntOp> {
889 // 64-bit vector types.
890 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
891 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
892 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
893 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
894 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
895 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
897 // 128-bit vector types.
898 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
899 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
900 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
901 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
902 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
903 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
907 // Neon 2-register vector shift by immediate,
908 // element sizes of 8, 16, 32 and 64 bits:
909 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
910 string OpcodeStr, SDNode OpNode> {
911 // 64-bit vector types.
912 def v8i8 : N2VDSh<op24, op23, 0b001000, op11_8, 0, op4,
913 !strconcat(OpcodeStr, "8"), v8i8, OpNode>;
914 def v4i16 : N2VDSh<op24, op23, 0b010000, op11_8, 0, op4,
915 !strconcat(OpcodeStr, "16"), v4i16, OpNode>;
916 def v2i32 : N2VDSh<op24, op23, 0b100000, op11_8, 0, op4,
917 !strconcat(OpcodeStr, "32"), v2i32, OpNode>;
918 def v1i64 : N2VDSh<op24, op23, 0b000000, op11_8, 1, op4,
919 !strconcat(OpcodeStr, "64"), v1i64, OpNode>;
921 // 128-bit vector types.
922 def v16i8 : N2VQSh<op24, op23, 0b001000, op11_8, 0, op4,
923 !strconcat(OpcodeStr, "8"), v16i8, OpNode>;
924 def v8i16 : N2VQSh<op24, op23, 0b010000, op11_8, 0, op4,
925 !strconcat(OpcodeStr, "16"), v8i16, OpNode>;
926 def v4i32 : N2VQSh<op24, op23, 0b100000, op11_8, 0, op4,
927 !strconcat(OpcodeStr, "32"), v4i32, OpNode>;
928 def v2i64 : N2VQSh<op24, op23, 0b000000, op11_8, 1, op4,
929 !strconcat(OpcodeStr, "64"), v2i64, OpNode>;
933 // Neon Shift-Accumulate vector operations,
934 // element sizes of 8, 16, 32 and 64 bits:
935 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
936 string OpcodeStr, SDNode ShOp> {
937 // 64-bit vector types.
938 def v8i8 : N2VDShAdd<op24, op23, 0b001000, op11_8, 0, op4,
939 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
940 def v4i16 : N2VDShAdd<op24, op23, 0b010000, op11_8, 0, op4,
941 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
942 def v2i32 : N2VDShAdd<op24, op23, 0b100000, op11_8, 0, op4,
943 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
944 def v1i64 : N2VDShAdd<op24, op23, 0b000000, op11_8, 1, op4,
945 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
947 // 128-bit vector types.
948 def v16i8 : N2VQShAdd<op24, op23, 0b001000, op11_8, 0, op4,
949 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
950 def v8i16 : N2VQShAdd<op24, op23, 0b010000, op11_8, 0, op4,
951 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
952 def v4i32 : N2VQShAdd<op24, op23, 0b100000, op11_8, 0, op4,
953 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
954 def v2i64 : N2VQShAdd<op24, op23, 0b000000, op11_8, 1, op4,
955 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
959 // Neon Shift-Insert vector operations,
960 // element sizes of 8, 16, 32 and 64 bits:
961 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
962 string OpcodeStr, SDNode ShOp> {
963 // 64-bit vector types.
964 def v8i8 : N2VDShIns<op24, op23, 0b001000, op11_8, 0, op4,
965 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
966 def v4i16 : N2VDShIns<op24, op23, 0b010000, op11_8, 0, op4,
967 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
968 def v2i32 : N2VDShIns<op24, op23, 0b100000, op11_8, 0, op4,
969 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
970 def v1i64 : N2VDShIns<op24, op23, 0b000000, op11_8, 1, op4,
971 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
973 // 128-bit vector types.
974 def v16i8 : N2VQShIns<op24, op23, 0b001000, op11_8, 0, op4,
975 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
976 def v8i16 : N2VQShIns<op24, op23, 0b010000, op11_8, 0, op4,
977 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
978 def v4i32 : N2VQShIns<op24, op23, 0b100000, op11_8, 0, op4,
979 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
980 def v2i64 : N2VQShIns<op24, op23, 0b000000, op11_8, 1, op4,
981 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
984 //===----------------------------------------------------------------------===//
985 // Instruction Definitions.
986 //===----------------------------------------------------------------------===//
988 // Vector Add Operations.
990 // VADD : Vector Add (integer and floating-point)
991 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, "vadd.i", add, 1>;
992 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd, 1>;
993 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, "vadd.f32", v4f32, v4f32, fadd, 1>;
994 // VADDL : Vector Add Long (Q = D + D)
995 defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, "vaddl.s", int_arm_neon_vaddls, 1>;
996 defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, "vaddl.u", int_arm_neon_vaddlu, 1>;
997 // VADDW : Vector Add Wide (Q = Q + D)
998 defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw.s", int_arm_neon_vaddws, 0>;
999 defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw.u", int_arm_neon_vaddwu, 0>;
1000 // VHADD : Vector Halving Add
1001 defm VHADDs : N3VInt_QHS<0,0,0b0000,0, "vhadd.s", int_arm_neon_vhadds, 1>;
1002 defm VHADDu : N3VInt_QHS<1,0,0b0000,0, "vhadd.u", int_arm_neon_vhaddu, 1>;
1003 // VRHADD : Vector Rounding Halving Add
1004 defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, "vrhadd.s", int_arm_neon_vrhadds, 1>;
1005 defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, "vrhadd.u", int_arm_neon_vrhaddu, 1>;
1006 // VQADD : Vector Saturating Add
1007 defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, "vqadd.s", int_arm_neon_vqadds, 1>;
1008 defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, "vqadd.u", int_arm_neon_vqaddu, 1>;
1009 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
1010 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn.i", int_arm_neon_vaddhn, 1>;
1011 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
1012 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn.i", int_arm_neon_vraddhn, 1>;
1014 // Vector Add Operations used for single-precision FP
1015 def : N3VDs<fadd, VADDfd>;
1017 // Vector Multiply Operations.
1019 // VMUL : Vector Multiply (integer, polynomial and floating-point)
1020 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, "vmul.i", mul, 1>;
1021 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v8i8, v8i8,
1022 int_arm_neon_vmulp, 1>;
1023 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v16i8, v16i8,
1024 int_arm_neon_vmulp, 1>;
1025 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul, 1>;
1026 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, "vmul.f32", v4f32, v4f32, fmul, 1>;
1027 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
1028 defm VQDMULH : N3VInt_HS<0,0,0b1011,0, "vqdmulh.s", int_arm_neon_vqdmulh, 1>;
1029 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
1030 defm VQRDMULH : N3VInt_HS<1,0,0b1011,0, "vqrdmulh.s", int_arm_neon_vqrdmulh, 1>;
1031 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
1032 defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, "vmull.s", int_arm_neon_vmulls, 1>;
1033 defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, "vmull.u", int_arm_neon_vmullu, 1>;
1034 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, "vmull.p8", v8i16, v8i8,
1035 int_arm_neon_vmullp, 1>;
1036 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
1037 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, "vqdmull.s", int_arm_neon_vqdmull, 1>;
1039 // Vector Multiply Operations used for single-precision FP
1040 def : N3VDs<fmul, VMULfd>;
1042 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
1044 // VMLA : Vector Multiply Accumulate (integer and floating-point)
1045 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmla.i", add>;
1046 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32, fmul, fadd>;
1047 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v4f32, fmul, fadd>;
1048 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
1049 defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal.s", int_arm_neon_vmlals>;
1050 defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal.u", int_arm_neon_vmlalu>;
1051 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
1052 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal.s", int_arm_neon_vqdmlal>;
1053 // VMLS : Vector Multiply Subtract (integer and floating-point)
1054 defm VMLS : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmls.i", sub>;
1055 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32, fmul, fsub>;
1056 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v4f32, fmul, fsub>;
1057 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
1058 defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl.s", int_arm_neon_vmlsls>;
1059 defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl.u", int_arm_neon_vmlslu>;
1060 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
1061 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl.s", int_arm_neon_vqdmlsl>;
1063 // Vector Multiply-Accumulate/Subtract used for single-precision FP
1064 def : N3VDMulOps<fmul, fadd, VMLAfd>;
1065 def : N3VDMulOps<fmul, fsub, VMLSfd>;
1067 // Vector Subtract Operations.
1069 // VSUB : Vector Subtract (integer and floating-point)
1070 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, "vsub.i", sub, 0>;
1071 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub, 0>;
1072 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, "vsub.f32", v4f32, v4f32, fsub, 0>;
1073 // VSUBL : Vector Subtract Long (Q = D - D)
1074 defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, "vsubl.s", int_arm_neon_vsubls, 1>;
1075 defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, "vsubl.u", int_arm_neon_vsublu, 1>;
1076 // VSUBW : Vector Subtract Wide (Q = Q - D)
1077 defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw.s", int_arm_neon_vsubws, 0>;
1078 defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw.u", int_arm_neon_vsubwu, 0>;
1079 // VHSUB : Vector Halving Subtract
1080 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, "vhsub.s", int_arm_neon_vhsubs, 0>;
1081 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, "vhsub.u", int_arm_neon_vhsubu, 0>;
1082 // VQSUB : Vector Saturing Subtract
1083 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, "vqsub.s", int_arm_neon_vqsubs, 0>;
1084 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, "vqsub.u", int_arm_neon_vqsubu, 0>;
1085 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
1086 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn.i", int_arm_neon_vsubhn, 0>;
1087 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
1088 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn.i", int_arm_neon_vrsubhn, 0>;
1090 // Vector Sub Operations used for single-precision FP
1091 def : N3VDs<fsub, VSUBfd>;
1093 // Vector Comparisons.
1095 // VCEQ : Vector Compare Equal
1096 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, "vceq.i", NEONvceq, 1>;
1097 def VCEQfd : N3VD<0,0,0b00,0b1110,0, "vceq.f32", v2i32, v2f32, NEONvceq, 1>;
1098 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, "vceq.f32", v4i32, v4f32, NEONvceq, 1>;
1099 // VCGE : Vector Compare Greater Than or Equal
1100 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, "vcge.s", NEONvcge, 0>;
1101 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, "vcge.u", NEONvcgeu, 0>;
1102 def VCGEfd : N3VD<1,0,0b00,0b1110,0, "vcge.f32", v2i32, v2f32, NEONvcge, 0>;
1103 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, "vcge.f32", v4i32, v4f32, NEONvcge, 0>;
1104 // VCGT : Vector Compare Greater Than
1105 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, "vcgt.s", NEONvcgt, 0>;
1106 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, "vcgt.u", NEONvcgtu, 0>;
1107 def VCGTfd : N3VD<1,0,0b10,0b1110,0, "vcgt.f32", v2i32, v2f32, NEONvcgt, 0>;
1108 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, "vcgt.f32", v4i32, v4f32, NEONvcgt, 0>;
1109 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
1110 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v2i32, v2f32,
1111 int_arm_neon_vacged, 0>;
1112 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v4i32, v4f32,
1113 int_arm_neon_vacgeq, 0>;
1114 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
1115 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v2i32, v2f32,
1116 int_arm_neon_vacgtd, 0>;
1117 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v4i32, v4f32,
1118 int_arm_neon_vacgtq, 0>;
1119 // VTST : Vector Test Bits
1120 defm VTST : N3V_QHS<0, 0, 0b1000, 1, "vtst.i", NEONvtst, 1>;
1122 // Vector Bitwise Operations.
1124 // VAND : Vector Bitwise AND
1125 def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, "vand", v2i32, v2i32, and, 1>;
1126 def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, "vand", v4i32, v4i32, and, 1>;
1128 // VEOR : Vector Bitwise Exclusive OR
1129 def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, "veor", v2i32, v2i32, xor, 1>;
1130 def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, "veor", v4i32, v4i32, xor, 1>;
1132 // VORR : Vector Bitwise OR
1133 def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, "vorr", v2i32, v2i32, or, 1>;
1134 def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, "vorr", v4i32, v4i32, or, 1>;
1136 // VBIC : Vector Bitwise Bit Clear (AND NOT)
1137 def VBICd : N3V<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1138 (ins DPR:$src1, DPR:$src2), NoItinerary,
1139 "vbic\t$dst, $src1, $src2", "",
1140 [(set DPR:$dst, (v2i32 (and DPR:$src1,(vnot DPR:$src2))))]>;
1141 def VBICq : N3V<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1142 (ins QPR:$src1, QPR:$src2), NoItinerary,
1143 "vbic\t$dst, $src1, $src2", "",
1144 [(set QPR:$dst, (v4i32 (and QPR:$src1,(vnot QPR:$src2))))]>;
1146 // VORN : Vector Bitwise OR NOT
1147 def VORNd : N3V<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
1148 (ins DPR:$src1, DPR:$src2), NoItinerary,
1149 "vorn\t$dst, $src1, $src2", "",
1150 [(set DPR:$dst, (v2i32 (or DPR:$src1, (vnot DPR:$src2))))]>;
1151 def VORNq : N3V<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
1152 (ins QPR:$src1, QPR:$src2), NoItinerary,
1153 "vorn\t$dst, $src1, $src2", "",
1154 [(set QPR:$dst, (v4i32 (or QPR:$src1, (vnot QPR:$src2))))]>;
1156 // VMVN : Vector Bitwise NOT
1157 def VMVNd : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
1158 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1159 "vmvn\t$dst, $src", "",
1160 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>;
1161 def VMVNq : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
1162 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1163 "vmvn\t$dst, $src", "",
1164 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>;
1165 def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>;
1166 def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>;
1168 // VBSL : Vector Bitwise Select
1169 def VBSLd : N3V<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1170 (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
1171 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1173 (v2i32 (or (and DPR:$src2, DPR:$src1),
1174 (and DPR:$src3, (vnot DPR:$src1)))))]>;
1175 def VBSLq : N3V<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1176 (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
1177 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1179 (v4i32 (or (and QPR:$src2, QPR:$src1),
1180 (and QPR:$src3, (vnot QPR:$src1)))))]>;
1182 // VBIF : Vector Bitwise Insert if False
1183 // like VBSL but with: "vbif\t$dst, $src3, $src1", "$src2 = $dst",
1184 // VBIT : Vector Bitwise Insert if True
1185 // like VBSL but with: "vbit\t$dst, $src2, $src1", "$src3 = $dst",
1186 // These are not yet implemented. The TwoAddress pass will not go looking
1187 // for equivalent operations with different register constraints; it just
1190 // Vector Absolute Differences.
1192 // VABD : Vector Absolute Difference
1193 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, "vabd.s", int_arm_neon_vabds, 0>;
1194 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, "vabd.u", int_arm_neon_vabdu, 0>;
1195 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v2f32, v2f32,
1196 int_arm_neon_vabdf, 0>;
1197 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v4f32, v4f32,
1198 int_arm_neon_vabdf, 0>;
1200 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
1201 defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, "vabdl.s", int_arm_neon_vabdls, 0>;
1202 defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, "vabdl.u", int_arm_neon_vabdlu, 0>;
1204 // VABA : Vector Absolute Difference and Accumulate
1205 defm VABAs : N3VInt3_QHS<0,1,0b0101,0, "vaba.s", int_arm_neon_vabas>;
1206 defm VABAu : N3VInt3_QHS<1,1,0b0101,0, "vaba.u", int_arm_neon_vabau>;
1208 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
1209 defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal.s", int_arm_neon_vabals>;
1210 defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal.u", int_arm_neon_vabalu>;
1212 // Vector Maximum and Minimum.
1214 // VMAX : Vector Maximum
1215 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, "vmax.s", int_arm_neon_vmaxs, 1>;
1216 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, "vmax.u", int_arm_neon_vmaxu, 1>;
1217 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v2f32, v2f32,
1218 int_arm_neon_vmaxf, 1>;
1219 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v4f32, v4f32,
1220 int_arm_neon_vmaxf, 1>;
1222 // VMIN : Vector Minimum
1223 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, "vmin.s", int_arm_neon_vmins, 1>;
1224 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, "vmin.u", int_arm_neon_vminu, 1>;
1225 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v2f32, v2f32,
1226 int_arm_neon_vminf, 1>;
1227 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v4f32, v4f32,
1228 int_arm_neon_vminf, 1>;
1230 // Vector Pairwise Operations.
1232 // VPADD : Vector Pairwise Add
1233 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, "vpadd.i8", v8i8, v8i8,
1234 int_arm_neon_vpaddi, 0>;
1235 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, "vpadd.i16", v4i16, v4i16,
1236 int_arm_neon_vpaddi, 0>;
1237 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, "vpadd.i32", v2i32, v2i32,
1238 int_arm_neon_vpaddi, 0>;
1239 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, "vpadd.f32", v2f32, v2f32,
1240 int_arm_neon_vpaddf, 0>;
1242 // VPADDL : Vector Pairwise Add Long
1243 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl.s",
1244 int_arm_neon_vpaddls>;
1245 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl.u",
1246 int_arm_neon_vpaddlu>;
1248 // VPADAL : Vector Pairwise Add and Accumulate Long
1249 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpadal.s",
1250 int_arm_neon_vpadals>;
1251 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpadal.u",
1252 int_arm_neon_vpadalu>;
1254 // VPMAX : Vector Pairwise Maximum
1255 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, "vpmax.s8", v8i8, v8i8,
1256 int_arm_neon_vpmaxs, 0>;
1257 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, "vpmax.s16", v4i16, v4i16,
1258 int_arm_neon_vpmaxs, 0>;
1259 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, "vpmax.s32", v2i32, v2i32,
1260 int_arm_neon_vpmaxs, 0>;
1261 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, "vpmax.u8", v8i8, v8i8,
1262 int_arm_neon_vpmaxu, 0>;
1263 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, "vpmax.u16", v4i16, v4i16,
1264 int_arm_neon_vpmaxu, 0>;
1265 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, "vpmax.u32", v2i32, v2i32,
1266 int_arm_neon_vpmaxu, 0>;
1267 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, "vpmax.f32", v2f32, v2f32,
1268 int_arm_neon_vpmaxf, 0>;
1270 // VPMIN : Vector Pairwise Minimum
1271 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, "vpmin.s8", v8i8, v8i8,
1272 int_arm_neon_vpmins, 0>;
1273 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, "vpmin.s16", v4i16, v4i16,
1274 int_arm_neon_vpmins, 0>;
1275 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, "vpmin.s32", v2i32, v2i32,
1276 int_arm_neon_vpmins, 0>;
1277 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, "vpmin.u8", v8i8, v8i8,
1278 int_arm_neon_vpminu, 0>;
1279 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, "vpmin.u16", v4i16, v4i16,
1280 int_arm_neon_vpminu, 0>;
1281 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, "vpmin.u32", v2i32, v2i32,
1282 int_arm_neon_vpminu, 0>;
1283 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, "vpmin.f32", v2f32, v2f32,
1284 int_arm_neon_vpminf, 0>;
1286 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
1288 // VRECPE : Vector Reciprocal Estimate
1289 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1290 v2i32, v2i32, int_arm_neon_vrecpe>;
1291 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1292 v4i32, v4i32, int_arm_neon_vrecpe>;
1293 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1294 v2f32, v2f32, int_arm_neon_vrecpef>;
1295 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1296 v4f32, v4f32, int_arm_neon_vrecpef>;
1298 // VRECPS : Vector Reciprocal Step
1299 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v2f32, v2f32,
1300 int_arm_neon_vrecps, 1>;
1301 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v4f32, v4f32,
1302 int_arm_neon_vrecps, 1>;
1304 // VRSQRTE : Vector Reciprocal Square Root Estimate
1305 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1306 v2i32, v2i32, int_arm_neon_vrsqrte>;
1307 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1308 v4i32, v4i32, int_arm_neon_vrsqrte>;
1309 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1310 v2f32, v2f32, int_arm_neon_vrsqrtef>;
1311 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1312 v4f32, v4f32, int_arm_neon_vrsqrtef>;
1314 // VRSQRTS : Vector Reciprocal Square Root Step
1315 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v2f32, v2f32,
1316 int_arm_neon_vrsqrts, 1>;
1317 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v4f32, v4f32,
1318 int_arm_neon_vrsqrts, 1>;
1322 // VSHL : Vector Shift
1323 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, "vshl.s", int_arm_neon_vshifts, 0>;
1324 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, "vshl.u", int_arm_neon_vshiftu, 0>;
1325 // VSHL : Vector Shift Left (Immediate)
1326 defm VSHLi : N2VSh_QHSD<0, 1, 0b0111, 1, "vshl.i", NEONvshl>;
1327 // VSHR : Vector Shift Right (Immediate)
1328 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, "vshr.s", NEONvshrs>;
1329 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, "vshr.u", NEONvshru>;
1331 // VSHLL : Vector Shift Left Long
1332 def VSHLLs8 : N2VLSh<0, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.s8",
1333 v8i16, v8i8, NEONvshlls>;
1334 def VSHLLs16 : N2VLSh<0, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.s16",
1335 v4i32, v4i16, NEONvshlls>;
1336 def VSHLLs32 : N2VLSh<0, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.s32",
1337 v2i64, v2i32, NEONvshlls>;
1338 def VSHLLu8 : N2VLSh<1, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.u8",
1339 v8i16, v8i8, NEONvshllu>;
1340 def VSHLLu16 : N2VLSh<1, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.u16",
1341 v4i32, v4i16, NEONvshllu>;
1342 def VSHLLu32 : N2VLSh<1, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.u32",
1343 v2i64, v2i32, NEONvshllu>;
1345 // VSHLL : Vector Shift Left Long (with maximum shift count)
1346 def VSHLLi8 : N2VLSh<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll.i8",
1347 v8i16, v8i8, NEONvshlli>;
1348 def VSHLLi16 : N2VLSh<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll.i16",
1349 v4i32, v4i16, NEONvshlli>;
1350 def VSHLLi32 : N2VLSh<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll.i32",
1351 v2i64, v2i32, NEONvshlli>;
1353 // VSHRN : Vector Shift Right and Narrow
1354 def VSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 0, 1, "vshrn.i16",
1355 v8i8, v8i16, NEONvshrn>;
1356 def VSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 0, 1, "vshrn.i32",
1357 v4i16, v4i32, NEONvshrn>;
1358 def VSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 0, 1, "vshrn.i64",
1359 v2i32, v2i64, NEONvshrn>;
1361 // VRSHL : Vector Rounding Shift
1362 defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, "vrshl.s", int_arm_neon_vrshifts, 0>;
1363 defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, "vrshl.u", int_arm_neon_vrshiftu, 0>;
1364 // VRSHR : Vector Rounding Shift Right
1365 defm VRSHRs : N2VSh_QHSD<0, 1, 0b0010, 1, "vrshr.s", NEONvrshrs>;
1366 defm VRSHRu : N2VSh_QHSD<1, 1, 0b0010, 1, "vrshr.u", NEONvrshru>;
1368 // VRSHRN : Vector Rounding Shift Right and Narrow
1369 def VRSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 1, 1, "vrshrn.i16",
1370 v8i8, v8i16, NEONvrshrn>;
1371 def VRSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 1, 1, "vrshrn.i32",
1372 v4i16, v4i32, NEONvrshrn>;
1373 def VRSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 1, 1, "vrshrn.i64",
1374 v2i32, v2i64, NEONvrshrn>;
1376 // VQSHL : Vector Saturating Shift
1377 defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, "vqshl.s", int_arm_neon_vqshifts, 0>;
1378 defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, "vqshl.u", int_arm_neon_vqshiftu, 0>;
1379 // VQSHL : Vector Saturating Shift Left (Immediate)
1380 defm VQSHLsi : N2VSh_QHSD<0, 1, 0b0111, 1, "vqshl.s", NEONvqshls>;
1381 defm VQSHLui : N2VSh_QHSD<1, 1, 0b0111, 1, "vqshl.u", NEONvqshlu>;
1382 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
1383 defm VQSHLsu : N2VSh_QHSD<1, 1, 0b0110, 1, "vqshlu.s", NEONvqshlsu>;
1385 // VQSHRN : Vector Saturating Shift Right and Narrow
1386 def VQSHRNs16 : N2VNSh<0, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.s16",
1387 v8i8, v8i16, NEONvqshrns>;
1388 def VQSHRNs32 : N2VNSh<0, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.s32",
1389 v4i16, v4i32, NEONvqshrns>;
1390 def VQSHRNs64 : N2VNSh<0, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.s64",
1391 v2i32, v2i64, NEONvqshrns>;
1392 def VQSHRNu16 : N2VNSh<1, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.u16",
1393 v8i8, v8i16, NEONvqshrnu>;
1394 def VQSHRNu32 : N2VNSh<1, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.u32",
1395 v4i16, v4i32, NEONvqshrnu>;
1396 def VQSHRNu64 : N2VNSh<1, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.u64",
1397 v2i32, v2i64, NEONvqshrnu>;
1399 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
1400 def VQSHRUN16 : N2VNSh<1, 1, 0b001000, 0b1000, 0, 0, 1, "vqshrun.s16",
1401 v8i8, v8i16, NEONvqshrnsu>;
1402 def VQSHRUN32 : N2VNSh<1, 1, 0b010000, 0b1000, 0, 0, 1, "vqshrun.s32",
1403 v4i16, v4i32, NEONvqshrnsu>;
1404 def VQSHRUN64 : N2VNSh<1, 1, 0b100000, 0b1000, 0, 0, 1, "vqshrun.s64",
1405 v2i32, v2i64, NEONvqshrnsu>;
1407 // VQRSHL : Vector Saturating Rounding Shift
1408 defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, "vqrshl.s",
1409 int_arm_neon_vqrshifts, 0>;
1410 defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, "vqrshl.u",
1411 int_arm_neon_vqrshiftu, 0>;
1413 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
1414 def VQRSHRNs16: N2VNSh<0, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.s16",
1415 v8i8, v8i16, NEONvqrshrns>;
1416 def VQRSHRNs32: N2VNSh<0, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.s32",
1417 v4i16, v4i32, NEONvqrshrns>;
1418 def VQRSHRNs64: N2VNSh<0, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.s64",
1419 v2i32, v2i64, NEONvqrshrns>;
1420 def VQRSHRNu16: N2VNSh<1, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.u16",
1421 v8i8, v8i16, NEONvqrshrnu>;
1422 def VQRSHRNu32: N2VNSh<1, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.u32",
1423 v4i16, v4i32, NEONvqrshrnu>;
1424 def VQRSHRNu64: N2VNSh<1, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.u64",
1425 v2i32, v2i64, NEONvqrshrnu>;
1427 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
1428 def VQRSHRUN16: N2VNSh<1, 1, 0b001000, 0b1000, 0, 1, 1, "vqrshrun.s16",
1429 v8i8, v8i16, NEONvqrshrnsu>;
1430 def VQRSHRUN32: N2VNSh<1, 1, 0b010000, 0b1000, 0, 1, 1, "vqrshrun.s32",
1431 v4i16, v4i32, NEONvqrshrnsu>;
1432 def VQRSHRUN64: N2VNSh<1, 1, 0b100000, 0b1000, 0, 1, 1, "vqrshrun.s64",
1433 v2i32, v2i64, NEONvqrshrnsu>;
1435 // VSRA : Vector Shift Right and Accumulate
1436 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra.s", NEONvshrs>;
1437 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra.u", NEONvshru>;
1438 // VRSRA : Vector Rounding Shift Right and Accumulate
1439 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra.s", NEONvrshrs>;
1440 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra.u", NEONvrshru>;
1442 // VSLI : Vector Shift Left and Insert
1443 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli.", NEONvsli>;
1444 // VSRI : Vector Shift Right and Insert
1445 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri.", NEONvsri>;
1447 // Vector Absolute and Saturating Absolute.
1449 // VABS : Vector Absolute Value
1450 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0, "vabs.s",
1452 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1453 v2f32, v2f32, int_arm_neon_vabsf>;
1454 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1455 v4f32, v4f32, int_arm_neon_vabsf>;
1456 def : N2VDInts<fabs, VABSfd>;
1458 // VQABS : Vector Saturating Absolute Value
1459 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0, "vqabs.s",
1460 int_arm_neon_vqabs>;
1464 def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
1465 def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>;
1467 class VNEGD<bits<2> size, string OpcodeStr, ValueType Ty>
1468 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
1470 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1471 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>;
1472 class VNEGQ<bits<2> size, string OpcodeStr, ValueType Ty>
1473 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
1475 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1476 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>;
1478 // VNEG : Vector Negate
1479 def VNEGs8d : VNEGD<0b00, "vneg.s8", v8i8>;
1480 def VNEGs16d : VNEGD<0b01, "vneg.s16", v4i16>;
1481 def VNEGs32d : VNEGD<0b10, "vneg.s32", v2i32>;
1482 def VNEGs8q : VNEGQ<0b00, "vneg.s8", v16i8>;
1483 def VNEGs16q : VNEGQ<0b01, "vneg.s16", v8i16>;
1484 def VNEGs32q : VNEGQ<0b10, "vneg.s32", v4i32>;
1486 // VNEG : Vector Negate (floating-point)
1487 def VNEGf32d : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
1488 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1489 "vneg.f32\t$dst, $src", "",
1490 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
1491 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
1492 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1493 "vneg.f32\t$dst, $src", "",
1494 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
1495 def : N2VDInts<fneg, VNEGf32d>;
1497 def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
1498 def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
1499 def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>;
1500 def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>;
1501 def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>;
1502 def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>;
1504 // VQNEG : Vector Saturating Negate
1505 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0, "vqneg.s",
1506 int_arm_neon_vqneg>;
1508 // Vector Bit Counting Operations.
1510 // VCLS : Vector Count Leading Sign Bits
1511 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0, "vcls.s",
1513 // VCLZ : Vector Count Leading Zeros
1514 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0, "vclz.i",
1516 // VCNT : Vector Count One Bits
1517 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1518 v8i8, v8i8, int_arm_neon_vcnt>;
1519 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1520 v16i8, v16i8, int_arm_neon_vcnt>;
1522 // Vector Move Operations.
1524 // VMOV : Vector Move (Register)
1526 def VMOVD : N3V<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
1527 NoItinerary, "vmov\t$dst, $src", "", []>;
1528 def VMOVQ : N3V<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
1529 NoItinerary, "vmov\t$dst, $src", "", []>;
1531 // VMOV : Vector Move (Immediate)
1533 // VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
1534 def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
1535 return ARM::getVMOVImm(N, 1, *CurDAG);
1537 def vmovImm8 : PatLeaf<(build_vector), [{
1538 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
1541 // VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
1542 def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
1543 return ARM::getVMOVImm(N, 2, *CurDAG);
1545 def vmovImm16 : PatLeaf<(build_vector), [{
1546 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
1547 }], VMOV_get_imm16>;
1549 // VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
1550 def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
1551 return ARM::getVMOVImm(N, 4, *CurDAG);
1553 def vmovImm32 : PatLeaf<(build_vector), [{
1554 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
1555 }], VMOV_get_imm32>;
1557 // VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
1558 def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
1559 return ARM::getVMOVImm(N, 8, *CurDAG);
1561 def vmovImm64 : PatLeaf<(build_vector), [{
1562 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
1563 }], VMOV_get_imm64>;
1565 // Note: Some of the cmode bits in the following VMOV instructions need to
1566 // be encoded based on the immed values.
1568 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
1569 (ins i8imm:$SIMM), NoItinerary,
1570 "vmov.i8\t$dst, $SIMM", "",
1571 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
1572 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
1573 (ins i8imm:$SIMM), NoItinerary,
1574 "vmov.i8\t$dst, $SIMM", "",
1575 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
1577 def VMOVv4i16 : N1ModImm<1, 0b000, 0b1000, 0, 0, 0, 1, (outs DPR:$dst),
1578 (ins i16imm:$SIMM), NoItinerary,
1579 "vmov.i16\t$dst, $SIMM", "",
1580 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
1581 def VMOVv8i16 : N1ModImm<1, 0b000, 0b1000, 0, 1, 0, 1, (outs QPR:$dst),
1582 (ins i16imm:$SIMM), NoItinerary,
1583 "vmov.i16\t$dst, $SIMM", "",
1584 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
1586 def VMOVv2i32 : N1ModImm<1, 0b000, 0b0000, 0, 0, 0, 1, (outs DPR:$dst),
1587 (ins i32imm:$SIMM), NoItinerary,
1588 "vmov.i32\t$dst, $SIMM", "",
1589 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
1590 def VMOVv4i32 : N1ModImm<1, 0b000, 0b0000, 0, 1, 0, 1, (outs QPR:$dst),
1591 (ins i32imm:$SIMM), NoItinerary,
1592 "vmov.i32\t$dst, $SIMM", "",
1593 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
1595 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
1596 (ins i64imm:$SIMM), NoItinerary,
1597 "vmov.i64\t$dst, $SIMM", "",
1598 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
1599 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
1600 (ins i64imm:$SIMM), NoItinerary,
1601 "vmov.i64\t$dst, $SIMM", "",
1602 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
1604 // VMOV : Vector Get Lane (move scalar to ARM core register)
1606 def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00,
1607 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1608 NoItinerary, "vmov", ".s8\t$dst, $src[$lane]",
1609 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
1611 def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01,
1612 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1613 NoItinerary, "vmov", ".s16\t$dst, $src[$lane]",
1614 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
1616 def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00,
1617 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1618 NoItinerary, "vmov", ".u8\t$dst, $src[$lane]",
1619 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
1621 def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01,
1622 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1623 NoItinerary, "vmov", ".u16\t$dst, $src[$lane]",
1624 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
1626 def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00,
1627 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1628 NoItinerary, "vmov", ".32\t$dst, $src[$lane]",
1629 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
1631 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
1632 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
1633 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1634 (SubReg_i8_reg imm:$lane))),
1635 (SubReg_i8_lane imm:$lane))>;
1636 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
1637 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1638 (SubReg_i16_reg imm:$lane))),
1639 (SubReg_i16_lane imm:$lane))>;
1640 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
1641 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1642 (SubReg_i8_reg imm:$lane))),
1643 (SubReg_i8_lane imm:$lane))>;
1644 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
1645 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1646 (SubReg_i16_reg imm:$lane))),
1647 (SubReg_i16_lane imm:$lane))>;
1648 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
1649 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
1650 (SubReg_i32_reg imm:$lane))),
1651 (SubReg_i32_lane imm:$lane))>;
1652 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
1653 // (EXTRACT_SUBREG QPR:$src1, (SubReg_f64_reg imm:$src2))>;
1654 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
1655 (EXTRACT_SUBREG QPR:$src1, (SubReg_f64_reg imm:$src2))>;
1658 // VMOV : Vector Set Lane (move ARM core register to scalar)
1660 let Constraints = "$src1 = $dst" in {
1661 def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst),
1662 (ins DPR:$src1, GPR:$src2, i32imm:$lane),
1663 NoItinerary, "vmov", ".8\t$dst[$lane], $src2",
1664 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
1665 GPR:$src2, imm:$lane))]>;
1666 def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst),
1667 (ins DPR:$src1, GPR:$src2, i32imm:$lane),
1668 NoItinerary, "vmov", ".16\t$dst[$lane], $src2",
1669 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
1670 GPR:$src2, imm:$lane))]>;
1671 def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst),
1672 (ins DPR:$src1, GPR:$src2, i32imm:$lane),
1673 NoItinerary, "vmov", ".32\t$dst[$lane], $src2",
1674 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
1675 GPR:$src2, imm:$lane))]>;
1677 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
1678 (v16i8 (INSERT_SUBREG QPR:$src1,
1679 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
1680 (SubReg_i8_reg imm:$lane))),
1681 GPR:$src2, (SubReg_i8_lane imm:$lane)),
1682 (SubReg_i8_reg imm:$lane)))>;
1683 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
1684 (v8i16 (INSERT_SUBREG QPR:$src1,
1685 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
1686 (SubReg_i16_reg imm:$lane))),
1687 GPR:$src2, (SubReg_i16_lane imm:$lane)),
1688 (SubReg_i16_reg imm:$lane)))>;
1689 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
1690 (v4i32 (INSERT_SUBREG QPR:$src1,
1691 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
1692 (SubReg_i32_reg imm:$lane))),
1693 GPR:$src2, (SubReg_i32_lane imm:$lane)),
1694 (SubReg_i32_reg imm:$lane)))>;
1696 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1697 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (SubReg_f64_reg imm:$src3))>;
1698 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1699 (INSERT_SUBREG QPR:$src1, DPR:$src2, (SubReg_f64_reg imm:$src3))>;
1701 // VDUP : Vector Duplicate (from ARM core register to all elements)
1703 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
1704 (vector_shuffle node:$lhs, node:$rhs), [{
1705 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1706 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
1709 class VDUPD<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1710 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
1711 NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"),
1712 [(set DPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>;
1713 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1714 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
1715 NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"),
1716 [(set QPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>;
1718 def VDUP8d : VDUPD<0b11101100, 0b00, ".8", v8i8>;
1719 def VDUP16d : VDUPD<0b11101000, 0b01, ".16", v4i16>;
1720 def VDUP32d : VDUPD<0b11101000, 0b00, ".32", v2i32>;
1721 def VDUP8q : VDUPQ<0b11101110, 0b00, ".8", v16i8>;
1722 def VDUP16q : VDUPQ<0b11101010, 0b01, ".16", v8i16>;
1723 def VDUP32q : VDUPQ<0b11101010, 0b00, ".32", v4i32>;
1725 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
1726 NoItinerary, "vdup", ".32\t$dst, $src",
1727 [(set DPR:$dst, (v2f32 (splat_lo
1729 (f32 (bitconvert GPR:$src))),
1731 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
1732 NoItinerary, "vdup", ".32\t$dst, $src",
1733 [(set QPR:$dst, (v4f32 (splat_lo
1735 (f32 (bitconvert GPR:$src))),
1738 // VDUP : Vector Duplicate Lane (from scalar to all elements)
1740 def SHUFFLE_get_splat_lane : SDNodeXForm<vector_shuffle, [{
1741 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1742 return CurDAG->getTargetConstant(SVOp->getSplatIndex(), MVT::i32);
1745 def splat_lane : PatFrag<(ops node:$lhs, node:$rhs),
1746 (vector_shuffle node:$lhs, node:$rhs), [{
1747 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1748 return SVOp->isSplat();
1749 }], SHUFFLE_get_splat_lane>;
1751 class VDUPLND<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty>
1752 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
1753 (outs DPR:$dst), (ins DPR:$src, i32imm:$lane), NoItinerary,
1754 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
1755 [(set DPR:$dst, (Ty (splat_lane:$lane DPR:$src, undef)))]>;
1757 // vector_shuffle requires that the source and destination types match, so
1758 // VDUP to a 128-bit result uses a target-specific VDUPLANEQ node.
1759 class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr,
1760 ValueType ResTy, ValueType OpTy>
1761 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
1762 (outs QPR:$dst), (ins DPR:$src, i32imm:$lane), NoItinerary,
1763 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
1764 [(set QPR:$dst, (ResTy (NEONvduplaneq (OpTy DPR:$src), imm:$lane)))]>;
1766 def VDUPLN8d : VDUPLND<0b00, 0b01, "vdup.8", v8i8>;
1767 def VDUPLN16d : VDUPLND<0b00, 0b10, "vdup.16", v4i16>;
1768 def VDUPLN32d : VDUPLND<0b01, 0b00, "vdup.32", v2i32>;
1769 def VDUPLNfd : VDUPLND<0b01, 0b00, "vdup.32", v2f32>;
1770 def VDUPLN8q : VDUPLNQ<0b00, 0b01, "vdup.8", v16i8, v8i8>;
1771 def VDUPLN16q : VDUPLNQ<0b00, 0b10, "vdup.16", v8i16, v4i16>;
1772 def VDUPLN32q : VDUPLNQ<0b01, 0b00, "vdup.32", v4i32, v2i32>;
1773 def VDUPLNfq : VDUPLNQ<0b01, 0b00, "vdup.32", v4f32, v2f32>;
1775 // VMOVN : Vector Narrowing Move
1776 defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, "vmovn.i",
1777 int_arm_neon_vmovn>;
1778 // VQMOVN : Vector Saturating Narrowing Move
1779 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, "vqmovn.s",
1780 int_arm_neon_vqmovns>;
1781 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, "vqmovn.u",
1782 int_arm_neon_vqmovnu>;
1783 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, "vqmovun.s",
1784 int_arm_neon_vqmovnsu>;
1785 // VMOVL : Vector Lengthening Move
1786 defm VMOVLs : N2VLInt_QHS<0,1,0b1010,0,0,1, "vmovl.s", int_arm_neon_vmovls>;
1787 defm VMOVLu : N2VLInt_QHS<1,1,0b1010,0,0,1, "vmovl.u", int_arm_neon_vmovlu>;
1789 // Vector Conversions.
1791 // VCVT : Vector Convert Between Floating-Point and Integers
1792 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1793 v2i32, v2f32, fp_to_sint>;
1794 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1795 v2i32, v2f32, fp_to_uint>;
1796 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1797 v2f32, v2i32, sint_to_fp>;
1798 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1799 v2f32, v2i32, uint_to_fp>;
1801 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1802 v4i32, v4f32, fp_to_sint>;
1803 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1804 v4i32, v4f32, fp_to_uint>;
1805 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1806 v4f32, v4i32, sint_to_fp>;
1807 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1808 v4f32, v4i32, uint_to_fp>;
1810 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
1811 // Note: Some of the opcode bits in the following VCVT instructions need to
1812 // be encoded based on the immed values.
1813 def VCVTf2xsd : N2VCvtD<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1814 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
1815 def VCVTf2xud : N2VCvtD<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1816 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
1817 def VCVTxs2fd : N2VCvtD<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1818 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
1819 def VCVTxu2fd : N2VCvtD<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1820 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
1822 def VCVTf2xsq : N2VCvtQ<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1823 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
1824 def VCVTf2xuq : N2VCvtQ<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1825 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
1826 def VCVTxs2fq : N2VCvtQ<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1827 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
1828 def VCVTxu2fq : N2VCvtQ<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1829 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
1831 // VREV : Vector Reverse
1833 def vrev64_shuffle : PatFrag<(ops node:$in),
1834 (vector_shuffle node:$in, undef), [{
1835 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1836 return ARM::isVREVMask(SVOp, 64);
1839 def vrev32_shuffle : PatFrag<(ops node:$in),
1840 (vector_shuffle node:$in, undef), [{
1841 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1842 return ARM::isVREVMask(SVOp, 32);
1845 def vrev16_shuffle : PatFrag<(ops node:$in),
1846 (vector_shuffle node:$in, undef), [{
1847 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1848 return ARM::isVREVMask(SVOp, 16);
1851 // VREV64 : Vector Reverse elements within 64-bit doublewords
1853 class VREV64D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1854 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
1855 (ins DPR:$src), NoItinerary,
1856 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1857 [(set DPR:$dst, (Ty (vrev64_shuffle (Ty DPR:$src))))]>;
1858 class VREV64Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1859 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
1860 (ins QPR:$src), NoItinerary,
1861 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1862 [(set QPR:$dst, (Ty (vrev64_shuffle (Ty QPR:$src))))]>;
1864 def VREV64d8 : VREV64D<0b00, "vrev64.8", v8i8>;
1865 def VREV64d16 : VREV64D<0b01, "vrev64.16", v4i16>;
1866 def VREV64d32 : VREV64D<0b10, "vrev64.32", v2i32>;
1867 def VREV64df : VREV64D<0b10, "vrev64.32", v2f32>;
1869 def VREV64q8 : VREV64Q<0b00, "vrev64.8", v16i8>;
1870 def VREV64q16 : VREV64Q<0b01, "vrev64.16", v8i16>;
1871 def VREV64q32 : VREV64Q<0b10, "vrev64.32", v4i32>;
1872 def VREV64qf : VREV64Q<0b10, "vrev64.32", v4f32>;
1874 // VREV32 : Vector Reverse elements within 32-bit words
1876 class VREV32D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1877 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
1878 (ins DPR:$src), NoItinerary,
1879 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1880 [(set DPR:$dst, (Ty (vrev32_shuffle (Ty DPR:$src))))]>;
1881 class VREV32Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1882 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
1883 (ins QPR:$src), NoItinerary,
1884 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1885 [(set QPR:$dst, (Ty (vrev32_shuffle (Ty QPR:$src))))]>;
1887 def VREV32d8 : VREV32D<0b00, "vrev32.8", v8i8>;
1888 def VREV32d16 : VREV32D<0b01, "vrev32.16", v4i16>;
1890 def VREV32q8 : VREV32Q<0b00, "vrev32.8", v16i8>;
1891 def VREV32q16 : VREV32Q<0b01, "vrev32.16", v8i16>;
1893 // VREV16 : Vector Reverse elements within 16-bit halfwords
1895 class VREV16D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1896 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
1897 (ins DPR:$src), NoItinerary,
1898 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1899 [(set DPR:$dst, (Ty (vrev16_shuffle (Ty DPR:$src))))]>;
1900 class VREV16Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1901 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
1902 (ins QPR:$src), NoItinerary,
1903 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1904 [(set QPR:$dst, (Ty (vrev16_shuffle (Ty QPR:$src))))]>;
1906 def VREV16d8 : VREV16D<0b00, "vrev16.8", v8i8>;
1907 def VREV16q8 : VREV16Q<0b00, "vrev16.8", v16i8>;
1909 //===----------------------------------------------------------------------===//
1910 // Non-Instruction Patterns
1911 //===----------------------------------------------------------------------===//
1914 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
1915 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
1916 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
1917 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
1918 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
1919 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
1920 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
1921 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
1922 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
1923 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
1924 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
1925 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
1926 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
1927 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
1928 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
1929 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
1930 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
1931 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
1932 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
1933 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
1934 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
1935 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
1936 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
1937 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
1938 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
1939 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
1940 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
1941 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
1942 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
1943 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
1945 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
1946 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
1947 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
1948 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
1949 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
1950 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
1951 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
1952 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
1953 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
1954 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
1955 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
1956 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
1957 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
1958 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
1959 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
1960 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
1961 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
1962 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
1963 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
1964 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
1965 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
1966 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
1967 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
1968 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
1969 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
1970 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
1971 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
1972 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
1973 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
1974 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
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