1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def NEONvduplaneq : SDNode<"ARMISD::VDUPLANEQ",
69 SDTypeProfile<1, 2, [SDTCisVT<2, i32>]>>;
71 def SDTARMVLD : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
72 def NEONvld2d : SDNode<"ARMISD::VLD2D", SDTARMVLD,
73 [SDNPHasChain, SDNPOutFlag, SDNPMayLoad]>;
74 def NEONvld3d : SDNode<"ARMISD::VLD3D", SDTARMVLD,
75 [SDNPHasChain, SDNPOutFlag, SDNPMayLoad]>;
76 def NEONvld4d : SDNode<"ARMISD::VLD4D", SDTARMVLD,
77 [SDNPHasChain, SDNPOutFlag, SDNPMayLoad]>;
79 //===----------------------------------------------------------------------===//
80 // NEON operand definitions
81 //===----------------------------------------------------------------------===//
83 // addrmode_neonldstm := reg
85 /* TODO: Take advantage of vldm.
86 def addrmode_neonldstm : Operand<i32>,
87 ComplexPattern<i32, 2, "SelectAddrModeNeonLdStM", []> {
88 let PrintMethod = "printAddrNeonLdStMOperand";
89 let MIOperandInfo = (ops GPR, i32imm);
93 //===----------------------------------------------------------------------===//
94 // NEON load / store instructions
95 //===----------------------------------------------------------------------===//
97 /* TODO: Take advantage of vldm.
99 def VLDMD : NI<(outs),
100 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
101 "vldm${addr:submode} ${addr:base}, $dst1",
103 let Inst{27-25} = 0b110;
105 let Inst{11-9} = 0b101;
108 def VLDMS : NI<(outs),
109 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
110 "vldm${addr:submode} ${addr:base}, $dst1",
112 let Inst{27-25} = 0b110;
114 let Inst{11-9} = 0b101;
119 // Use vldmia to load a Q register as a D register pair.
120 def VLDRQ : NI<(outs QPR:$dst), (ins GPR:$addr),
121 "vldmia $addr, ${dst:dregpair}",
122 [(set QPR:$dst, (v2f64 (load GPR:$addr)))]> {
123 let Inst{27-25} = 0b110;
124 let Inst{24} = 0; // P bit
125 let Inst{23} = 1; // U bit
127 let Inst{11-9} = 0b101;
130 // Use vstmia to store a Q register as a D register pair.
131 def VSTRQ : NI<(outs), (ins QPR:$src, GPR:$addr),
132 "vstmia $addr, ${src:dregpair}",
133 [(store (v2f64 QPR:$src), GPR:$addr)]> {
134 let Inst{27-25} = 0b110;
135 let Inst{24} = 0; // P bit
136 let Inst{23} = 1; // U bit
138 let Inst{11-9} = 0b101;
142 // VLD1 : Vector Load (multiple single elements)
143 class VLD1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
144 : NLdSt<(outs DPR:$dst), (ins addrmode6:$addr),
145 !strconcat(OpcodeStr, "\t\\{$dst\\}, $addr"),
146 [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
147 class VLD1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
148 : NLdSt<(outs QPR:$dst), (ins addrmode6:$addr),
149 !strconcat(OpcodeStr, "\t${dst:dregpair}, $addr"),
150 [(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
152 def VLD1d8 : VLD1D<"vld1.8", v8i8, int_arm_neon_vld1i>;
153 def VLD1d16 : VLD1D<"vld1.16", v4i16, int_arm_neon_vld1i>;
154 def VLD1d32 : VLD1D<"vld1.32", v2i32, int_arm_neon_vld1i>;
155 def VLD1df : VLD1D<"vld1.32", v2f32, int_arm_neon_vld1f>;
156 def VLD1d64 : VLD1D<"vld1.64", v1i64, int_arm_neon_vld1i>;
158 def VLD1q8 : VLD1Q<"vld1.8", v16i8, int_arm_neon_vld1i>;
159 def VLD1q16 : VLD1Q<"vld1.16", v8i16, int_arm_neon_vld1i>;
160 def VLD1q32 : VLD1Q<"vld1.32", v4i32, int_arm_neon_vld1i>;
161 def VLD1qf : VLD1Q<"vld1.32", v4f32, int_arm_neon_vld1f>;
162 def VLD1q64 : VLD1Q<"vld1.64", v2i64, int_arm_neon_vld1i>;
164 // VST1 : Vector Store (multiple single elements)
165 class VST1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
166 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src),
167 !strconcat(OpcodeStr, "\t\\{$src\\}, $addr"),
168 [(IntOp addrmode6:$addr, (Ty DPR:$src))]>;
169 class VST1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
170 : NLdSt<(outs), (ins addrmode6:$addr, QPR:$src),
171 !strconcat(OpcodeStr, "\t${src:dregpair}, $addr"),
172 [(IntOp addrmode6:$addr, (Ty QPR:$src))]>;
174 def VST1d8 : VST1D<"vst1.8", v8i8, int_arm_neon_vst1i>;
175 def VST1d16 : VST1D<"vst1.16", v4i16, int_arm_neon_vst1i>;
176 def VST1d32 : VST1D<"vst1.32", v2i32, int_arm_neon_vst1i>;
177 def VST1df : VST1D<"vst1.32", v2f32, int_arm_neon_vst1f>;
178 def VST1d64 : VST1D<"vst1.64", v1i64, int_arm_neon_vst1i>;
180 def VST1q8 : VST1Q<"vst1.8", v16i8, int_arm_neon_vst1i>;
181 def VST1q16 : VST1Q<"vst1.16", v8i16, int_arm_neon_vst1i>;
182 def VST1q32 : VST1Q<"vst1.32", v4i32, int_arm_neon_vst1i>;
183 def VST1qf : VST1Q<"vst1.32", v4f32, int_arm_neon_vst1f>;
184 def VST1q64 : VST1Q<"vst1.64", v2i64, int_arm_neon_vst1i>;
187 //===----------------------------------------------------------------------===//
188 // NEON pattern fragments
189 //===----------------------------------------------------------------------===//
191 // Extract D sub-registers of Q registers.
192 // (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
193 def SubReg_i8_reg : SDNodeXForm<imm, [{
194 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
196 def SubReg_i16_reg : SDNodeXForm<imm, [{
197 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
199 def SubReg_i32_reg : SDNodeXForm<imm, [{
200 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
202 def SubReg_f64_reg : SDNodeXForm<imm, [{
203 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
206 // Translate lane numbers from Q registers to D subregs.
207 def SubReg_i8_lane : SDNodeXForm<imm, [{
208 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
210 def SubReg_i16_lane : SDNodeXForm<imm, [{
211 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
213 def SubReg_i32_lane : SDNodeXForm<imm, [{
214 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
217 //===----------------------------------------------------------------------===//
218 // Instruction Classes
219 //===----------------------------------------------------------------------===//
221 // Basic 2-register operations, both double- and quad-register.
222 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
223 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
224 ValueType ResTy, ValueType OpTy, SDNode OpNode>
225 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
226 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
227 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
228 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
229 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
230 ValueType ResTy, ValueType OpTy, SDNode OpNode>
231 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
232 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
233 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
235 // Basic 2-register intrinsics, both double- and quad-register.
236 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
237 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
238 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
239 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
240 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
241 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
242 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
243 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
244 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
245 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
246 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
247 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
249 // Basic 2-register operations, scalar single-precision
250 class N2VDInts<SDNode OpNode, NeonI Inst>
251 : NEONFPPat<(f32 (OpNode SPR:$a)),
252 (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
255 // Narrow 2-register intrinsics.
256 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
257 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
258 string OpcodeStr, ValueType TyD, ValueType TyQ, Intrinsic IntOp>
259 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
260 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
261 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
263 // Long 2-register intrinsics. (This is currently only used for VMOVL and is
264 // derived from N2VImm instead of N2V because of the way the size is encoded.)
265 class N2VLInt<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
266 bit op6, bit op4, string OpcodeStr, ValueType TyQ, ValueType TyD,
268 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4, (outs QPR:$dst),
269 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
270 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
272 // Basic 3-register operations, both double- and quad-register.
273 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
274 string OpcodeStr, ValueType ResTy, ValueType OpTy,
275 SDNode OpNode, bit Commutable>
276 : N3V<op24, op23, op21_20, op11_8, 0, op4,
277 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2),
278 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
279 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
280 let isCommutable = Commutable;
282 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
283 string OpcodeStr, ValueType ResTy, ValueType OpTy,
284 SDNode OpNode, bit Commutable>
285 : N3V<op24, op23, op21_20, op11_8, 1, op4,
286 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2),
287 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
288 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
289 let isCommutable = Commutable;
292 // Basic 3-register operations, scalar single-precision
293 class N3VDs<SDNode OpNode, NeonI Inst>
294 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
295 (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
296 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
299 // Basic 3-register intrinsics, both double- and quad-register.
300 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
301 string OpcodeStr, ValueType ResTy, ValueType OpTy,
302 Intrinsic IntOp, bit Commutable>
303 : N3V<op24, op23, op21_20, op11_8, 0, op4,
304 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2),
305 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
306 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
307 let isCommutable = Commutable;
309 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
310 string OpcodeStr, ValueType ResTy, ValueType OpTy,
311 Intrinsic IntOp, bit Commutable>
312 : N3V<op24, op23, op21_20, op11_8, 1, op4,
313 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2),
314 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
315 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
316 let isCommutable = Commutable;
319 // Multiply-Add/Sub operations, both double- and quad-register.
320 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
321 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
322 : N3V<op24, op23, op21_20, op11_8, 0, op4,
323 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
324 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
325 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
326 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
327 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
328 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
329 : N3V<op24, op23, op21_20, op11_8, 1, op4,
330 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
331 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
332 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
333 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
335 // Multiply-Add/Sub operations, scalar single-precision
336 class N3VDMulOps<SDNode MulNode, SDNode OpNode, NeonI Inst>
337 : NEONFPPat<(f32 (OpNode SPR:$acc,
338 (f32 (MulNode SPR:$a, SPR:$b)))),
339 (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$acc, arm_ssubreg_0),
340 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
341 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
344 // Neon 3-argument intrinsics, both double- and quad-register.
345 // The destination register is also used as the first source operand register.
346 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
347 string OpcodeStr, ValueType ResTy, ValueType OpTy,
349 : N3V<op24, op23, op21_20, op11_8, 0, op4,
350 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
351 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
352 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
353 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
354 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
355 string OpcodeStr, ValueType ResTy, ValueType OpTy,
357 : N3V<op24, op23, op21_20, op11_8, 1, op4,
358 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
359 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
360 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
361 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
363 // Neon Long 3-argument intrinsic. The destination register is
364 // a quad-register and is also used as the first source operand register.
365 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
366 string OpcodeStr, ValueType TyQ, ValueType TyD, Intrinsic IntOp>
367 : N3V<op24, op23, op21_20, op11_8, 0, op4,
368 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3),
369 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
371 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
373 // Narrowing 3-register intrinsics.
374 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
375 string OpcodeStr, ValueType TyD, ValueType TyQ,
376 Intrinsic IntOp, bit Commutable>
377 : N3V<op24, op23, op21_20, op11_8, 0, op4,
378 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2),
379 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
380 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
381 let isCommutable = Commutable;
384 // Long 3-register intrinsics.
385 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
386 string OpcodeStr, ValueType TyQ, ValueType TyD,
387 Intrinsic IntOp, bit Commutable>
388 : N3V<op24, op23, op21_20, op11_8, 0, op4,
389 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2),
390 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
391 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
392 let isCommutable = Commutable;
395 // Wide 3-register intrinsics.
396 class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
397 string OpcodeStr, ValueType TyQ, ValueType TyD,
398 Intrinsic IntOp, bit Commutable>
399 : N3V<op24, op23, op21_20, op11_8, 0, op4,
400 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2),
401 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
402 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
403 let isCommutable = Commutable;
406 // Pairwise long 2-register intrinsics, both double- and quad-register.
407 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
408 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
409 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
410 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
411 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
412 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
413 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
414 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
415 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
416 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
417 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
418 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
420 // Pairwise long 2-register accumulate intrinsics,
421 // both double- and quad-register.
422 // The destination register is also used as the first source operand register.
423 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
424 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
425 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
426 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
427 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2),
428 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
429 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
430 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
431 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
432 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
433 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
434 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2),
435 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
436 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
438 // Shift by immediate,
439 // both double- and quad-register.
440 class N2VDSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
441 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
442 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
443 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM),
444 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
445 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
446 class N2VQSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
447 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
448 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
449 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM),
450 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
451 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
453 // Long shift by immediate.
454 class N2VLSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
455 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
456 ValueType OpTy, SDNode OpNode>
457 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
458 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM),
459 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
460 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
461 (i32 imm:$SIMM))))]>;
463 // Narrow shift by immediate.
464 class N2VNSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
465 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
466 ValueType OpTy, SDNode OpNode>
467 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
468 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM),
469 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
470 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
471 (i32 imm:$SIMM))))]>;
473 // Shift right by immediate and accumulate,
474 // both double- and quad-register.
475 class N2VDShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
476 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
477 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
478 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
479 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
480 [(set DPR:$dst, (Ty (add DPR:$src1,
481 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
482 class N2VQShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
483 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
484 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
485 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
486 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
487 [(set QPR:$dst, (Ty (add QPR:$src1,
488 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
490 // Shift by immediate and insert,
491 // both double- and quad-register.
492 class N2VDShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
493 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
494 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
495 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
496 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
497 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
498 class N2VQShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
499 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
500 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
501 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
502 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
503 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
505 // Convert, with fractional bits immediate,
506 // both double- and quad-register.
507 class N2VCvtD<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
508 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
510 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
511 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM),
512 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
513 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
514 class N2VCvtQ<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
515 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
517 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
518 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM),
519 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
520 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
522 //===----------------------------------------------------------------------===//
524 //===----------------------------------------------------------------------===//
526 // Neon 3-register vector operations.
528 // First with only element sizes of 8, 16 and 32 bits:
529 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
530 string OpcodeStr, SDNode OpNode, bit Commutable = 0> {
531 // 64-bit vector types.
532 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
533 v8i8, v8i8, OpNode, Commutable>;
534 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
535 v4i16, v4i16, OpNode, Commutable>;
536 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
537 v2i32, v2i32, OpNode, Commutable>;
539 // 128-bit vector types.
540 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
541 v16i8, v16i8, OpNode, Commutable>;
542 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
543 v8i16, v8i16, OpNode, Commutable>;
544 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
545 v4i32, v4i32, OpNode, Commutable>;
548 // ....then also with element size 64 bits:
549 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
550 string OpcodeStr, SDNode OpNode, bit Commutable = 0>
551 : N3V_QHS<op24, op23, op11_8, op4, OpcodeStr, OpNode, Commutable> {
552 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
553 v1i64, v1i64, OpNode, Commutable>;
554 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
555 v2i64, v2i64, OpNode, Commutable>;
559 // Neon Narrowing 2-register vector intrinsics,
560 // source operand element sizes of 16, 32 and 64 bits:
561 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
562 bits<5> op11_7, bit op6, bit op4, string OpcodeStr,
564 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
565 !strconcat(OpcodeStr, "16"), v8i8, v8i16, IntOp>;
566 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
567 !strconcat(OpcodeStr, "32"), v4i16, v4i32, IntOp>;
568 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
569 !strconcat(OpcodeStr, "64"), v2i32, v2i64, IntOp>;
573 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
574 // source operand element sizes of 16, 32 and 64 bits:
575 multiclass N2VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
576 bit op4, string OpcodeStr, Intrinsic IntOp> {
577 def v8i16 : N2VLInt<op24, op23, 0b001000, op11_8, op7, op6, op4,
578 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
579 def v4i32 : N2VLInt<op24, op23, 0b010000, op11_8, op7, op6, op4,
580 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
581 def v2i64 : N2VLInt<op24, op23, 0b100000, op11_8, op7, op6, op4,
582 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
586 // Neon 3-register vector intrinsics.
588 // First with only element sizes of 16 and 32 bits:
589 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
590 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
591 // 64-bit vector types.
592 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
593 v4i16, v4i16, IntOp, Commutable>;
594 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
595 v2i32, v2i32, IntOp, Commutable>;
597 // 128-bit vector types.
598 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
599 v8i16, v8i16, IntOp, Commutable>;
600 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
601 v4i32, v4i32, IntOp, Commutable>;
604 // ....then also with element size of 8 bits:
605 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
606 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
607 : N3VInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
608 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
609 v8i8, v8i8, IntOp, Commutable>;
610 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
611 v16i8, v16i8, IntOp, Commutable>;
614 // ....then also with element size of 64 bits:
615 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
616 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
617 : N3VInt_QHS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
618 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
619 v1i64, v1i64, IntOp, Commutable>;
620 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
621 v2i64, v2i64, IntOp, Commutable>;
625 // Neon Narrowing 3-register vector intrinsics,
626 // source operand element sizes of 16, 32 and 64 bits:
627 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
628 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
629 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr,"16"),
630 v8i8, v8i16, IntOp, Commutable>;
631 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"32"),
632 v4i16, v4i32, IntOp, Commutable>;
633 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"64"),
634 v2i32, v2i64, IntOp, Commutable>;
638 // Neon Long 3-register vector intrinsics.
640 // First with only element sizes of 16 and 32 bits:
641 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
642 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
643 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
644 v4i32, v4i16, IntOp, Commutable>;
645 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
646 v2i64, v2i32, IntOp, Commutable>;
649 // ....then also with element size of 8 bits:
650 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
651 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
652 : N3VLInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
653 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
654 v8i16, v8i8, IntOp, Commutable>;
658 // Neon Wide 3-register vector intrinsics,
659 // source operand element sizes of 8, 16 and 32 bits:
660 multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
661 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
662 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
663 v8i16, v8i8, IntOp, Commutable>;
664 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
665 v4i32, v4i16, IntOp, Commutable>;
666 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
667 v2i64, v2i32, IntOp, Commutable>;
671 // Neon Multiply-Op vector operations,
672 // element sizes of 8, 16 and 32 bits:
673 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
674 string OpcodeStr, SDNode OpNode> {
675 // 64-bit vector types.
676 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4,
677 !strconcat(OpcodeStr, "8"), v8i8, mul, OpNode>;
678 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4,
679 !strconcat(OpcodeStr, "16"), v4i16, mul, OpNode>;
680 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4,
681 !strconcat(OpcodeStr, "32"), v2i32, mul, OpNode>;
683 // 128-bit vector types.
684 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4,
685 !strconcat(OpcodeStr, "8"), v16i8, mul, OpNode>;
686 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4,
687 !strconcat(OpcodeStr, "16"), v8i16, mul, OpNode>;
688 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4,
689 !strconcat(OpcodeStr, "32"), v4i32, mul, OpNode>;
693 // Neon 3-argument intrinsics,
694 // element sizes of 8, 16 and 32 bits:
695 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
696 string OpcodeStr, Intrinsic IntOp> {
697 // 64-bit vector types.
698 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4,
699 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
700 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4,
701 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
702 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4,
703 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
705 // 128-bit vector types.
706 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4,
707 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
708 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4,
709 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
710 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4,
711 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
715 // Neon Long 3-argument intrinsics.
717 // First with only element sizes of 16 and 32 bits:
718 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
719 string OpcodeStr, Intrinsic IntOp> {
720 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
721 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
722 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4,
723 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
726 // ....then also with element size of 8 bits:
727 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
728 string OpcodeStr, Intrinsic IntOp>
729 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp> {
730 def v8i16 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
731 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
735 // Neon 2-register vector intrinsics,
736 // element sizes of 8, 16 and 32 bits:
737 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
738 bits<5> op11_7, bit op4, string OpcodeStr,
740 // 64-bit vector types.
741 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
742 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
743 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
744 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
745 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
746 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
748 // 128-bit vector types.
749 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
750 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
751 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
752 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
753 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
754 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
758 // Neon Pairwise long 2-register intrinsics,
759 // element sizes of 8, 16 and 32 bits:
760 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
761 bits<5> op11_7, bit op4,
762 string OpcodeStr, Intrinsic IntOp> {
763 // 64-bit vector types.
764 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
765 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
766 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
767 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
768 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
769 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
771 // 128-bit vector types.
772 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
773 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
774 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
775 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
776 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
777 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
781 // Neon Pairwise long 2-register accumulate intrinsics,
782 // element sizes of 8, 16 and 32 bits:
783 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
784 bits<5> op11_7, bit op4,
785 string OpcodeStr, Intrinsic IntOp> {
786 // 64-bit vector types.
787 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
788 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
789 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
790 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
791 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
792 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
794 // 128-bit vector types.
795 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
796 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
797 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
798 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
799 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
800 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
804 // Neon 2-register vector shift by immediate,
805 // element sizes of 8, 16, 32 and 64 bits:
806 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
807 string OpcodeStr, SDNode OpNode> {
808 // 64-bit vector types.
809 def v8i8 : N2VDSh<op24, op23, 0b001000, op11_8, 0, op4,
810 !strconcat(OpcodeStr, "8"), v8i8, OpNode>;
811 def v4i16 : N2VDSh<op24, op23, 0b010000, op11_8, 0, op4,
812 !strconcat(OpcodeStr, "16"), v4i16, OpNode>;
813 def v2i32 : N2VDSh<op24, op23, 0b100000, op11_8, 0, op4,
814 !strconcat(OpcodeStr, "32"), v2i32, OpNode>;
815 def v1i64 : N2VDSh<op24, op23, 0b000000, op11_8, 1, op4,
816 !strconcat(OpcodeStr, "64"), v1i64, OpNode>;
818 // 128-bit vector types.
819 def v16i8 : N2VQSh<op24, op23, 0b001000, op11_8, 0, op4,
820 !strconcat(OpcodeStr, "8"), v16i8, OpNode>;
821 def v8i16 : N2VQSh<op24, op23, 0b010000, op11_8, 0, op4,
822 !strconcat(OpcodeStr, "16"), v8i16, OpNode>;
823 def v4i32 : N2VQSh<op24, op23, 0b100000, op11_8, 0, op4,
824 !strconcat(OpcodeStr, "32"), v4i32, OpNode>;
825 def v2i64 : N2VQSh<op24, op23, 0b000000, op11_8, 1, op4,
826 !strconcat(OpcodeStr, "64"), v2i64, OpNode>;
830 // Neon Shift-Accumulate vector operations,
831 // element sizes of 8, 16, 32 and 64 bits:
832 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
833 string OpcodeStr, SDNode ShOp> {
834 // 64-bit vector types.
835 def v8i8 : N2VDShAdd<op24, op23, 0b001000, op11_8, 0, op4,
836 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
837 def v4i16 : N2VDShAdd<op24, op23, 0b010000, op11_8, 0, op4,
838 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
839 def v2i32 : N2VDShAdd<op24, op23, 0b100000, op11_8, 0, op4,
840 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
841 def v1i64 : N2VDShAdd<op24, op23, 0b000000, op11_8, 1, op4,
842 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
844 // 128-bit vector types.
845 def v16i8 : N2VQShAdd<op24, op23, 0b001000, op11_8, 0, op4,
846 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
847 def v8i16 : N2VQShAdd<op24, op23, 0b010000, op11_8, 0, op4,
848 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
849 def v4i32 : N2VQShAdd<op24, op23, 0b100000, op11_8, 0, op4,
850 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
851 def v2i64 : N2VQShAdd<op24, op23, 0b000000, op11_8, 1, op4,
852 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
856 // Neon Shift-Insert vector operations,
857 // element sizes of 8, 16, 32 and 64 bits:
858 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
859 string OpcodeStr, SDNode ShOp> {
860 // 64-bit vector types.
861 def v8i8 : N2VDShIns<op24, op23, 0b001000, op11_8, 0, op4,
862 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
863 def v4i16 : N2VDShIns<op24, op23, 0b010000, op11_8, 0, op4,
864 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
865 def v2i32 : N2VDShIns<op24, op23, 0b100000, op11_8, 0, op4,
866 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
867 def v1i64 : N2VDShIns<op24, op23, 0b000000, op11_8, 1, op4,
868 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
870 // 128-bit vector types.
871 def v16i8 : N2VQShIns<op24, op23, 0b001000, op11_8, 0, op4,
872 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
873 def v8i16 : N2VQShIns<op24, op23, 0b010000, op11_8, 0, op4,
874 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
875 def v4i32 : N2VQShIns<op24, op23, 0b100000, op11_8, 0, op4,
876 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
877 def v2i64 : N2VQShIns<op24, op23, 0b000000, op11_8, 1, op4,
878 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
881 //===----------------------------------------------------------------------===//
882 // Instruction Definitions.
883 //===----------------------------------------------------------------------===//
885 // Vector Add Operations.
887 // VADD : Vector Add (integer and floating-point)
888 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, "vadd.i", add, 1>;
889 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd, 1>;
890 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, "vadd.f32", v4f32, v4f32, fadd, 1>;
891 // VADDL : Vector Add Long (Q = D + D)
892 defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, "vaddl.s", int_arm_neon_vaddls, 1>;
893 defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, "vaddl.u", int_arm_neon_vaddlu, 1>;
894 // VADDW : Vector Add Wide (Q = Q + D)
895 defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw.s", int_arm_neon_vaddws, 0>;
896 defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw.u", int_arm_neon_vaddwu, 0>;
897 // VHADD : Vector Halving Add
898 defm VHADDs : N3VInt_QHS<0,0,0b0000,0, "vhadd.s", int_arm_neon_vhadds, 1>;
899 defm VHADDu : N3VInt_QHS<1,0,0b0000,0, "vhadd.u", int_arm_neon_vhaddu, 1>;
900 // VRHADD : Vector Rounding Halving Add
901 defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, "vrhadd.s", int_arm_neon_vrhadds, 1>;
902 defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, "vrhadd.u", int_arm_neon_vrhaddu, 1>;
903 // VQADD : Vector Saturating Add
904 defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, "vqadd.s", int_arm_neon_vqadds, 1>;
905 defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, "vqadd.u", int_arm_neon_vqaddu, 1>;
906 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
907 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn.i", int_arm_neon_vaddhn, 1>;
908 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
909 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn.i", int_arm_neon_vraddhn, 1>;
911 // Vector Add Operations used for single-precision FP
912 def : N3VDs<fadd, VADDfd>;
914 // Vector Multiply Operations.
916 // VMUL : Vector Multiply (integer, polynomial and floating-point)
917 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, "vmul.i", mul, 1>;
918 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v8i8, v8i8,
919 int_arm_neon_vmulp, 1>;
920 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v16i8, v16i8,
921 int_arm_neon_vmulp, 1>;
922 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul, 1>;
923 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, "vmul.f32", v4f32, v4f32, fmul, 1>;
924 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
925 defm VQDMULH : N3VInt_HS<0,0,0b1011,0, "vqdmulh.s", int_arm_neon_vqdmulh, 1>;
926 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
927 defm VQRDMULH : N3VInt_HS<1,0,0b1011,0, "vqrdmulh.s", int_arm_neon_vqrdmulh, 1>;
928 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
929 defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, "vmull.s", int_arm_neon_vmulls, 1>;
930 defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, "vmull.u", int_arm_neon_vmullu, 1>;
931 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, "vmull.p8", v8i16, v8i8,
932 int_arm_neon_vmullp, 1>;
933 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
934 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, "vqdmull.s", int_arm_neon_vqdmull, 1>;
936 // Vector Multiply Operations used for single-precision FP
937 def : N3VDs<fmul, VMULfd>;
939 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
941 // VMLA : Vector Multiply Accumulate (integer and floating-point)
942 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmla.i", add>;
943 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32, fmul, fadd>;
944 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v4f32, fmul, fadd>;
945 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
946 defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal.s", int_arm_neon_vmlals>;
947 defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal.u", int_arm_neon_vmlalu>;
948 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
949 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal.s", int_arm_neon_vqdmlal>;
950 // VMLS : Vector Multiply Subtract (integer and floating-point)
951 defm VMLS : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmls.i", sub>;
952 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32, fmul, fsub>;
953 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v4f32, fmul, fsub>;
954 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
955 defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl.s", int_arm_neon_vmlsls>;
956 defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl.u", int_arm_neon_vmlslu>;
957 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
958 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl.s", int_arm_neon_vqdmlsl>;
960 // Vector Multiply-Accumulate/Subtract used for single-precision FP
961 def : N3VDMulOps<fmul, fadd, VMLAfd>;
962 def : N3VDMulOps<fmul, fsub, VMLSfd>;
964 // Vector Subtract Operations.
966 // VSUB : Vector Subtract (integer and floating-point)
967 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, "vsub.i", sub, 0>;
968 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub, 0>;
969 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, "vsub.f32", v4f32, v4f32, fsub, 0>;
970 // VSUBL : Vector Subtract Long (Q = D - D)
971 defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, "vsubl.s", int_arm_neon_vsubls, 1>;
972 defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, "vsubl.u", int_arm_neon_vsublu, 1>;
973 // VSUBW : Vector Subtract Wide (Q = Q - D)
974 defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw.s", int_arm_neon_vsubws, 0>;
975 defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw.u", int_arm_neon_vsubwu, 0>;
976 // VHSUB : Vector Halving Subtract
977 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, "vhsub.s", int_arm_neon_vhsubs, 0>;
978 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, "vhsub.u", int_arm_neon_vhsubu, 0>;
979 // VQSUB : Vector Saturing Subtract
980 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, "vqsub.s", int_arm_neon_vqsubs, 0>;
981 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, "vqsub.u", int_arm_neon_vqsubu, 0>;
982 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
983 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn.i", int_arm_neon_vsubhn, 0>;
984 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
985 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn.i", int_arm_neon_vrsubhn, 0>;
987 // Vector Sub Operations used for single-precision FP
988 def : N3VDs<fsub, VSUBfd>;
990 // Vector Comparisons.
992 // VCEQ : Vector Compare Equal
993 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, "vceq.i", NEONvceq, 1>;
994 def VCEQfd : N3VD<0,0,0b00,0b1110,0, "vceq.f32", v2i32, v2f32, NEONvceq, 1>;
995 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, "vceq.f32", v4i32, v4f32, NEONvceq, 1>;
996 // VCGE : Vector Compare Greater Than or Equal
997 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, "vcge.s", NEONvcge, 0>;
998 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, "vcge.u", NEONvcgeu, 0>;
999 def VCGEfd : N3VD<1,0,0b00,0b1110,0, "vcge.f32", v2i32, v2f32, NEONvcge, 0>;
1000 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, "vcge.f32", v4i32, v4f32, NEONvcge, 0>;
1001 // VCGT : Vector Compare Greater Than
1002 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, "vcgt.s", NEONvcgt, 0>;
1003 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, "vcgt.u", NEONvcgtu, 0>;
1004 def VCGTfd : N3VD<1,0,0b10,0b1110,0, "vcgt.f32", v2i32, v2f32, NEONvcgt, 0>;
1005 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, "vcgt.f32", v4i32, v4f32, NEONvcgt, 0>;
1006 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
1007 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v2i32, v2f32,
1008 int_arm_neon_vacged, 0>;
1009 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v4i32, v4f32,
1010 int_arm_neon_vacgeq, 0>;
1011 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
1012 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v2i32, v2f32,
1013 int_arm_neon_vacgtd, 0>;
1014 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v4i32, v4f32,
1015 int_arm_neon_vacgtq, 0>;
1016 // VTST : Vector Test Bits
1017 defm VTST : N3V_QHS<0, 0, 0b1000, 1, "vtst.i", NEONvtst, 1>;
1019 // Vector Bitwise Operations.
1021 // VAND : Vector Bitwise AND
1022 def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, "vand", v2i32, v2i32, and, 1>;
1023 def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, "vand", v4i32, v4i32, and, 1>;
1025 // VEOR : Vector Bitwise Exclusive OR
1026 def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, "veor", v2i32, v2i32, xor, 1>;
1027 def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, "veor", v4i32, v4i32, xor, 1>;
1029 // VORR : Vector Bitwise OR
1030 def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, "vorr", v2i32, v2i32, or, 1>;
1031 def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, "vorr", v4i32, v4i32, or, 1>;
1033 // VBIC : Vector Bitwise Bit Clear (AND NOT)
1034 def VBICd : N3V<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1035 (ins DPR:$src1, DPR:$src2), "vbic\t$dst, $src1, $src2", "",
1036 [(set DPR:$dst, (v2i32 (and DPR:$src1,(vnot DPR:$src2))))]>;
1037 def VBICq : N3V<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1038 (ins QPR:$src1, QPR:$src2), "vbic\t$dst, $src1, $src2", "",
1039 [(set QPR:$dst, (v4i32 (and QPR:$src1,(vnot QPR:$src2))))]>;
1041 // VORN : Vector Bitwise OR NOT
1042 def VORNd : N3V<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
1043 (ins DPR:$src1, DPR:$src2), "vorn\t$dst, $src1, $src2", "",
1044 [(set DPR:$dst, (v2i32 (or DPR:$src1, (vnot DPR:$src2))))]>;
1045 def VORNq : N3V<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
1046 (ins QPR:$src1, QPR:$src2), "vorn\t$dst, $src1, $src2", "",
1047 [(set QPR:$dst, (v4i32 (or QPR:$src1, (vnot QPR:$src2))))]>;
1049 // VMVN : Vector Bitwise NOT
1050 def VMVNd : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
1051 (outs DPR:$dst), (ins DPR:$src), "vmvn\t$dst, $src", "",
1052 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>;
1053 def VMVNq : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
1054 (outs QPR:$dst), (ins QPR:$src), "vmvn\t$dst, $src", "",
1055 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>;
1056 def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>;
1057 def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>;
1059 // VBSL : Vector Bitwise Select
1060 def VBSLd : N3V<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1061 (ins DPR:$src1, DPR:$src2, DPR:$src3),
1062 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1064 (v2i32 (or (and DPR:$src2, DPR:$src1),
1065 (and DPR:$src3, (vnot DPR:$src1)))))]>;
1066 def VBSLq : N3V<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1067 (ins QPR:$src1, QPR:$src2, QPR:$src3),
1068 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1070 (v4i32 (or (and QPR:$src2, QPR:$src1),
1071 (and QPR:$src3, (vnot QPR:$src1)))))]>;
1073 // VBIF : Vector Bitwise Insert if False
1074 // like VBSL but with: "vbif\t$dst, $src3, $src1", "$src2 = $dst",
1075 // VBIT : Vector Bitwise Insert if True
1076 // like VBSL but with: "vbit\t$dst, $src2, $src1", "$src3 = $dst",
1077 // These are not yet implemented. The TwoAddress pass will not go looking
1078 // for equivalent operations with different register constraints; it just
1081 // Vector Absolute Differences.
1083 // VABD : Vector Absolute Difference
1084 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, "vabd.s", int_arm_neon_vabds, 0>;
1085 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, "vabd.u", int_arm_neon_vabdu, 0>;
1086 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v2f32, v2f32,
1087 int_arm_neon_vabdf, 0>;
1088 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v4f32, v4f32,
1089 int_arm_neon_vabdf, 0>;
1091 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
1092 defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, "vabdl.s", int_arm_neon_vabdls, 0>;
1093 defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, "vabdl.u", int_arm_neon_vabdlu, 0>;
1095 // VABA : Vector Absolute Difference and Accumulate
1096 defm VABAs : N3VInt3_QHS<0,1,0b0101,0, "vaba.s", int_arm_neon_vabas>;
1097 defm VABAu : N3VInt3_QHS<1,1,0b0101,0, "vaba.u", int_arm_neon_vabau>;
1099 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
1100 defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal.s", int_arm_neon_vabals>;
1101 defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal.u", int_arm_neon_vabalu>;
1103 // Vector Maximum and Minimum.
1105 // VMAX : Vector Maximum
1106 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, "vmax.s", int_arm_neon_vmaxs, 1>;
1107 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, "vmax.u", int_arm_neon_vmaxu, 1>;
1108 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v2f32, v2f32,
1109 int_arm_neon_vmaxf, 1>;
1110 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v4f32, v4f32,
1111 int_arm_neon_vmaxf, 1>;
1113 // VMIN : Vector Minimum
1114 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, "vmin.s", int_arm_neon_vmins, 1>;
1115 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, "vmin.u", int_arm_neon_vminu, 1>;
1116 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v2f32, v2f32,
1117 int_arm_neon_vminf, 1>;
1118 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v4f32, v4f32,
1119 int_arm_neon_vminf, 1>;
1121 // Vector Pairwise Operations.
1123 // VPADD : Vector Pairwise Add
1124 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, "vpadd.i8", v8i8, v8i8,
1125 int_arm_neon_vpaddi, 0>;
1126 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, "vpadd.i16", v4i16, v4i16,
1127 int_arm_neon_vpaddi, 0>;
1128 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, "vpadd.i32", v2i32, v2i32,
1129 int_arm_neon_vpaddi, 0>;
1130 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, "vpadd.f32", v2f32, v2f32,
1131 int_arm_neon_vpaddf, 0>;
1133 // VPADDL : Vector Pairwise Add Long
1134 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl.s",
1135 int_arm_neon_vpaddls>;
1136 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl.u",
1137 int_arm_neon_vpaddlu>;
1139 // VPADAL : Vector Pairwise Add and Accumulate Long
1140 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpadal.s",
1141 int_arm_neon_vpadals>;
1142 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpadal.u",
1143 int_arm_neon_vpadalu>;
1145 // VPMAX : Vector Pairwise Maximum
1146 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, "vpmax.s8", v8i8, v8i8,
1147 int_arm_neon_vpmaxs, 0>;
1148 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, "vpmax.s16", v4i16, v4i16,
1149 int_arm_neon_vpmaxs, 0>;
1150 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, "vpmax.s32", v2i32, v2i32,
1151 int_arm_neon_vpmaxs, 0>;
1152 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, "vpmax.u8", v8i8, v8i8,
1153 int_arm_neon_vpmaxu, 0>;
1154 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, "vpmax.u16", v4i16, v4i16,
1155 int_arm_neon_vpmaxu, 0>;
1156 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, "vpmax.u32", v2i32, v2i32,
1157 int_arm_neon_vpmaxu, 0>;
1158 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, "vpmax.f32", v2f32, v2f32,
1159 int_arm_neon_vpmaxf, 0>;
1161 // VPMIN : Vector Pairwise Minimum
1162 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, "vpmin.s8", v8i8, v8i8,
1163 int_arm_neon_vpmins, 0>;
1164 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, "vpmin.s16", v4i16, v4i16,
1165 int_arm_neon_vpmins, 0>;
1166 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, "vpmin.s32", v2i32, v2i32,
1167 int_arm_neon_vpmins, 0>;
1168 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, "vpmin.u8", v8i8, v8i8,
1169 int_arm_neon_vpminu, 0>;
1170 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, "vpmin.u16", v4i16, v4i16,
1171 int_arm_neon_vpminu, 0>;
1172 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, "vpmin.u32", v2i32, v2i32,
1173 int_arm_neon_vpminu, 0>;
1174 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, "vpmin.f32", v2f32, v2f32,
1175 int_arm_neon_vpminf, 0>;
1177 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
1179 // VRECPE : Vector Reciprocal Estimate
1180 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1181 v2i32, v2i32, int_arm_neon_vrecpe>;
1182 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1183 v4i32, v4i32, int_arm_neon_vrecpe>;
1184 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1185 v2f32, v2f32, int_arm_neon_vrecpef>;
1186 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1187 v4f32, v4f32, int_arm_neon_vrecpef>;
1189 // VRECPS : Vector Reciprocal Step
1190 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v2f32, v2f32,
1191 int_arm_neon_vrecps, 1>;
1192 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v4f32, v4f32,
1193 int_arm_neon_vrecps, 1>;
1195 // VRSQRTE : Vector Reciprocal Square Root Estimate
1196 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1197 v2i32, v2i32, int_arm_neon_vrsqrte>;
1198 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1199 v4i32, v4i32, int_arm_neon_vrsqrte>;
1200 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1201 v2f32, v2f32, int_arm_neon_vrsqrtef>;
1202 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1203 v4f32, v4f32, int_arm_neon_vrsqrtef>;
1205 // VRSQRTS : Vector Reciprocal Square Root Step
1206 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v2f32, v2f32,
1207 int_arm_neon_vrsqrts, 1>;
1208 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v4f32, v4f32,
1209 int_arm_neon_vrsqrts, 1>;
1213 // VSHL : Vector Shift
1214 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, "vshl.s", int_arm_neon_vshifts, 0>;
1215 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, "vshl.u", int_arm_neon_vshiftu, 0>;
1216 // VSHL : Vector Shift Left (Immediate)
1217 defm VSHLi : N2VSh_QHSD<0, 1, 0b0111, 1, "vshl.i", NEONvshl>;
1218 // VSHR : Vector Shift Right (Immediate)
1219 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, "vshr.s", NEONvshrs>;
1220 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, "vshr.u", NEONvshru>;
1222 // VSHLL : Vector Shift Left Long
1223 def VSHLLs8 : N2VLSh<0, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.s8",
1224 v8i16, v8i8, NEONvshlls>;
1225 def VSHLLs16 : N2VLSh<0, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.s16",
1226 v4i32, v4i16, NEONvshlls>;
1227 def VSHLLs32 : N2VLSh<0, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.s32",
1228 v2i64, v2i32, NEONvshlls>;
1229 def VSHLLu8 : N2VLSh<1, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.u8",
1230 v8i16, v8i8, NEONvshllu>;
1231 def VSHLLu16 : N2VLSh<1, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.u16",
1232 v4i32, v4i16, NEONvshllu>;
1233 def VSHLLu32 : N2VLSh<1, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.u32",
1234 v2i64, v2i32, NEONvshllu>;
1236 // VSHLL : Vector Shift Left Long (with maximum shift count)
1237 def VSHLLi8 : N2VLSh<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll.i8",
1238 v8i16, v8i8, NEONvshlli>;
1239 def VSHLLi16 : N2VLSh<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll.i16",
1240 v4i32, v4i16, NEONvshlli>;
1241 def VSHLLi32 : N2VLSh<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll.i32",
1242 v2i64, v2i32, NEONvshlli>;
1244 // VSHRN : Vector Shift Right and Narrow
1245 def VSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 0, 1, "vshrn.i16",
1246 v8i8, v8i16, NEONvshrn>;
1247 def VSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 0, 1, "vshrn.i32",
1248 v4i16, v4i32, NEONvshrn>;
1249 def VSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 0, 1, "vshrn.i64",
1250 v2i32, v2i64, NEONvshrn>;
1252 // VRSHL : Vector Rounding Shift
1253 defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, "vrshl.s", int_arm_neon_vrshifts, 0>;
1254 defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, "vrshl.u", int_arm_neon_vrshiftu, 0>;
1255 // VRSHR : Vector Rounding Shift Right
1256 defm VRSHRs : N2VSh_QHSD<0, 1, 0b0010, 1, "vrshr.s", NEONvrshrs>;
1257 defm VRSHRu : N2VSh_QHSD<1, 1, 0b0010, 1, "vrshr.u", NEONvrshru>;
1259 // VRSHRN : Vector Rounding Shift Right and Narrow
1260 def VRSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 1, 1, "vrshrn.i16",
1261 v8i8, v8i16, NEONvrshrn>;
1262 def VRSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 1, 1, "vrshrn.i32",
1263 v4i16, v4i32, NEONvrshrn>;
1264 def VRSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 1, 1, "vrshrn.i64",
1265 v2i32, v2i64, NEONvrshrn>;
1267 // VQSHL : Vector Saturating Shift
1268 defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, "vqshl.s", int_arm_neon_vqshifts, 0>;
1269 defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, "vqshl.u", int_arm_neon_vqshiftu, 0>;
1270 // VQSHL : Vector Saturating Shift Left (Immediate)
1271 defm VQSHLsi : N2VSh_QHSD<0, 1, 0b0111, 1, "vqshl.s", NEONvqshls>;
1272 defm VQSHLui : N2VSh_QHSD<1, 1, 0b0111, 1, "vqshl.u", NEONvqshlu>;
1273 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
1274 defm VQSHLsu : N2VSh_QHSD<1, 1, 0b0110, 1, "vqshlu.s", NEONvqshlsu>;
1276 // VQSHRN : Vector Saturating Shift Right and Narrow
1277 def VQSHRNs16 : N2VNSh<0, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.s16",
1278 v8i8, v8i16, NEONvqshrns>;
1279 def VQSHRNs32 : N2VNSh<0, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.s32",
1280 v4i16, v4i32, NEONvqshrns>;
1281 def VQSHRNs64 : N2VNSh<0, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.s64",
1282 v2i32, v2i64, NEONvqshrns>;
1283 def VQSHRNu16 : N2VNSh<1, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.u16",
1284 v8i8, v8i16, NEONvqshrnu>;
1285 def VQSHRNu32 : N2VNSh<1, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.u32",
1286 v4i16, v4i32, NEONvqshrnu>;
1287 def VQSHRNu64 : N2VNSh<1, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.u64",
1288 v2i32, v2i64, NEONvqshrnu>;
1290 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
1291 def VQSHRUN16 : N2VNSh<1, 1, 0b001000, 0b1000, 0, 0, 1, "vqshrun.s16",
1292 v8i8, v8i16, NEONvqshrnsu>;
1293 def VQSHRUN32 : N2VNSh<1, 1, 0b010000, 0b1000, 0, 0, 1, "vqshrun.s32",
1294 v4i16, v4i32, NEONvqshrnsu>;
1295 def VQSHRUN64 : N2VNSh<1, 1, 0b100000, 0b1000, 0, 0, 1, "vqshrun.s64",
1296 v2i32, v2i64, NEONvqshrnsu>;
1298 // VQRSHL : Vector Saturating Rounding Shift
1299 defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, "vqrshl.s",
1300 int_arm_neon_vqrshifts, 0>;
1301 defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, "vqrshl.u",
1302 int_arm_neon_vqrshiftu, 0>;
1304 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
1305 def VQRSHRNs16: N2VNSh<0, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.s16",
1306 v8i8, v8i16, NEONvqrshrns>;
1307 def VQRSHRNs32: N2VNSh<0, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.s32",
1308 v4i16, v4i32, NEONvqrshrns>;
1309 def VQRSHRNs64: N2VNSh<0, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.s64",
1310 v2i32, v2i64, NEONvqrshrns>;
1311 def VQRSHRNu16: N2VNSh<1, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.u16",
1312 v8i8, v8i16, NEONvqrshrnu>;
1313 def VQRSHRNu32: N2VNSh<1, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.u32",
1314 v4i16, v4i32, NEONvqrshrnu>;
1315 def VQRSHRNu64: N2VNSh<1, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.u64",
1316 v2i32, v2i64, NEONvqrshrnu>;
1318 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
1319 def VQRSHRUN16: N2VNSh<1, 1, 0b001000, 0b1000, 0, 1, 1, "vqrshrun.s16",
1320 v8i8, v8i16, NEONvqrshrnsu>;
1321 def VQRSHRUN32: N2VNSh<1, 1, 0b010000, 0b1000, 0, 1, 1, "vqrshrun.s32",
1322 v4i16, v4i32, NEONvqrshrnsu>;
1323 def VQRSHRUN64: N2VNSh<1, 1, 0b100000, 0b1000, 0, 1, 1, "vqrshrun.s64",
1324 v2i32, v2i64, NEONvqrshrnsu>;
1326 // VSRA : Vector Shift Right and Accumulate
1327 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra.s", NEONvshrs>;
1328 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra.u", NEONvshru>;
1329 // VRSRA : Vector Rounding Shift Right and Accumulate
1330 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra.s", NEONvrshrs>;
1331 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra.u", NEONvrshru>;
1333 // VSLI : Vector Shift Left and Insert
1334 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli.", NEONvsli>;
1335 // VSRI : Vector Shift Right and Insert
1336 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri.", NEONvsri>;
1338 // Vector Absolute and Saturating Absolute.
1340 // VABS : Vector Absolute Value
1341 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0, "vabs.s",
1343 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1344 v2f32, v2f32, int_arm_neon_vabsf>;
1345 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1346 v4f32, v4f32, int_arm_neon_vabsf>;
1347 def : N2VDInts<fabs, VABSfd>;
1349 // VQABS : Vector Saturating Absolute Value
1350 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0, "vqabs.s",
1351 int_arm_neon_vqabs>;
1355 def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
1356 def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>;
1358 class VNEGD<bits<2> size, string OpcodeStr, ValueType Ty>
1359 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
1360 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1361 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>;
1362 class VNEGQ<bits<2> size, string OpcodeStr, ValueType Ty>
1363 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
1364 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1365 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>;
1367 // VNEG : Vector Negate
1368 def VNEGs8d : VNEGD<0b00, "vneg.s8", v8i8>;
1369 def VNEGs16d : VNEGD<0b01, "vneg.s16", v4i16>;
1370 def VNEGs32d : VNEGD<0b10, "vneg.s32", v2i32>;
1371 def VNEGs8q : VNEGQ<0b00, "vneg.s8", v16i8>;
1372 def VNEGs16q : VNEGQ<0b01, "vneg.s16", v8i16>;
1373 def VNEGs32q : VNEGQ<0b10, "vneg.s32", v4i32>;
1375 // VNEG : Vector Negate (floating-point)
1376 def VNEGf32d : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
1377 (outs DPR:$dst), (ins DPR:$src), "vneg.f32\t$dst, $src", "",
1378 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
1379 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
1380 (outs QPR:$dst), (ins QPR:$src), "vneg.f32\t$dst, $src", "",
1381 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
1382 def : N2VDInts<fneg, VNEGf32d>;
1384 def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
1385 def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
1386 def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>;
1387 def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>;
1388 def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>;
1389 def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>;
1391 // VQNEG : Vector Saturating Negate
1392 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0, "vqneg.s",
1393 int_arm_neon_vqneg>;
1395 // Vector Bit Counting Operations.
1397 // VCLS : Vector Count Leading Sign Bits
1398 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0, "vcls.s",
1400 // VCLZ : Vector Count Leading Zeros
1401 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0, "vclz.i",
1403 // VCNT : Vector Count One Bits
1404 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1405 v8i8, v8i8, int_arm_neon_vcnt>;
1406 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1407 v16i8, v16i8, int_arm_neon_vcnt>;
1409 // Vector Move Operations.
1411 // VMOV : Vector Move (Register)
1413 def VMOVD : N3V<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
1414 "vmov\t$dst, $src", "", []>;
1415 def VMOVQ : N3V<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
1416 "vmov\t$dst, $src", "", []>;
1418 // VMOV : Vector Move (Immediate)
1420 // VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
1421 def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
1422 return ARM::getVMOVImm(N, 1, *CurDAG);
1424 def vmovImm8 : PatLeaf<(build_vector), [{
1425 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
1428 // VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
1429 def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
1430 return ARM::getVMOVImm(N, 2, *CurDAG);
1432 def vmovImm16 : PatLeaf<(build_vector), [{
1433 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
1434 }], VMOV_get_imm16>;
1436 // VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
1437 def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
1438 return ARM::getVMOVImm(N, 4, *CurDAG);
1440 def vmovImm32 : PatLeaf<(build_vector), [{
1441 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
1442 }], VMOV_get_imm32>;
1444 // VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
1445 def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
1446 return ARM::getVMOVImm(N, 8, *CurDAG);
1448 def vmovImm64 : PatLeaf<(build_vector), [{
1449 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
1450 }], VMOV_get_imm64>;
1452 // Note: Some of the cmode bits in the following VMOV instructions need to
1453 // be encoded based on the immed values.
1455 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
1456 (ins i8imm:$SIMM), "vmov.i8\t$dst, $SIMM", "",
1457 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
1458 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
1459 (ins i8imm:$SIMM), "vmov.i8\t$dst, $SIMM", "",
1460 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
1462 def VMOVv4i16 : N1ModImm<1, 0b000, 0b1000, 0, 0, 0, 1, (outs DPR:$dst),
1463 (ins i16imm:$SIMM), "vmov.i16\t$dst, $SIMM", "",
1464 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
1465 def VMOVv8i16 : N1ModImm<1, 0b000, 0b1000, 0, 1, 0, 1, (outs QPR:$dst),
1466 (ins i16imm:$SIMM), "vmov.i16\t$dst, $SIMM", "",
1467 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
1469 def VMOVv2i32 : N1ModImm<1, 0b000, 0b0000, 0, 0, 0, 1, (outs DPR:$dst),
1470 (ins i32imm:$SIMM), "vmov.i32\t$dst, $SIMM", "",
1471 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
1472 def VMOVv4i32 : N1ModImm<1, 0b000, 0b0000, 0, 1, 0, 1, (outs QPR:$dst),
1473 (ins i32imm:$SIMM), "vmov.i32\t$dst, $SIMM", "",
1474 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
1476 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
1477 (ins i64imm:$SIMM), "vmov.i64\t$dst, $SIMM", "",
1478 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
1479 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
1480 (ins i64imm:$SIMM), "vmov.i64\t$dst, $SIMM", "",
1481 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
1483 // VMOV : Vector Get Lane (move scalar to ARM core register)
1485 def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00,
1486 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1487 "vmov", ".s8\t$dst, $src[$lane]",
1488 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
1490 def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01,
1491 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1492 "vmov", ".s16\t$dst, $src[$lane]",
1493 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
1495 def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00,
1496 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1497 "vmov", ".u8\t$dst, $src[$lane]",
1498 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
1500 def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01,
1501 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1502 "vmov", ".u16\t$dst, $src[$lane]",
1503 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
1505 def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00,
1506 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1507 "vmov", ".32\t$dst, $src[$lane]",
1508 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
1510 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
1511 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
1512 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1513 (SubReg_i8_reg imm:$lane))),
1514 (SubReg_i8_lane imm:$lane))>;
1515 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
1516 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1517 (SubReg_i16_reg imm:$lane))),
1518 (SubReg_i16_lane imm:$lane))>;
1519 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
1520 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1521 (SubReg_i8_reg imm:$lane))),
1522 (SubReg_i8_lane imm:$lane))>;
1523 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
1524 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1525 (SubReg_i16_reg imm:$lane))),
1526 (SubReg_i16_lane imm:$lane))>;
1527 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
1528 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
1529 (SubReg_i32_reg imm:$lane))),
1530 (SubReg_i32_lane imm:$lane))>;
1531 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
1532 // (EXTRACT_SUBREG QPR:$src1, (SubReg_f64_reg imm:$src2))>;
1533 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
1534 (EXTRACT_SUBREG QPR:$src1, (SubReg_f64_reg imm:$src2))>;
1537 // VMOV : Vector Set Lane (move ARM core register to scalar)
1539 let Constraints = "$src1 = $dst" in {
1540 def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst),
1541 (ins DPR:$src1, GPR:$src2, i32imm:$lane),
1542 "vmov", ".8\t$dst[$lane], $src2",
1543 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
1544 GPR:$src2, imm:$lane))]>;
1545 def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst),
1546 (ins DPR:$src1, GPR:$src2, i32imm:$lane),
1547 "vmov", ".16\t$dst[$lane], $src2",
1548 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
1549 GPR:$src2, imm:$lane))]>;
1550 def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst),
1551 (ins DPR:$src1, GPR:$src2, i32imm:$lane),
1552 "vmov", ".32\t$dst[$lane], $src2",
1553 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
1554 GPR:$src2, imm:$lane))]>;
1556 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
1557 (v16i8 (INSERT_SUBREG QPR:$src1,
1558 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
1559 (SubReg_i8_reg imm:$lane))),
1560 GPR:$src2, (SubReg_i8_lane imm:$lane)),
1561 (SubReg_i8_reg imm:$lane)))>;
1562 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
1563 (v8i16 (INSERT_SUBREG QPR:$src1,
1564 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
1565 (SubReg_i16_reg imm:$lane))),
1566 GPR:$src2, (SubReg_i16_lane imm:$lane)),
1567 (SubReg_i16_reg imm:$lane)))>;
1568 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
1569 (v4i32 (INSERT_SUBREG QPR:$src1,
1570 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
1571 (SubReg_i32_reg imm:$lane))),
1572 GPR:$src2, (SubReg_i32_lane imm:$lane)),
1573 (SubReg_i32_reg imm:$lane)))>;
1575 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1576 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (SubReg_f64_reg imm:$src3))>;
1577 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1578 (INSERT_SUBREG QPR:$src1, DPR:$src2, (SubReg_f64_reg imm:$src3))>;
1580 // VDUP : Vector Duplicate (from ARM core register to all elements)
1582 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
1583 (vector_shuffle node:$lhs, node:$rhs), [{
1584 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1585 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
1588 class VDUPD<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1589 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
1590 "vdup", !strconcat(asmSize, "\t$dst, $src"),
1591 [(set DPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>;
1592 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1593 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
1594 "vdup", !strconcat(asmSize, "\t$dst, $src"),
1595 [(set QPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>;
1597 def VDUP8d : VDUPD<0b11101100, 0b00, ".8", v8i8>;
1598 def VDUP16d : VDUPD<0b11101000, 0b01, ".16", v4i16>;
1599 def VDUP32d : VDUPD<0b11101000, 0b00, ".32", v2i32>;
1600 def VDUP8q : VDUPQ<0b11101110, 0b00, ".8", v16i8>;
1601 def VDUP16q : VDUPQ<0b11101010, 0b01, ".16", v8i16>;
1602 def VDUP32q : VDUPQ<0b11101010, 0b00, ".32", v4i32>;
1604 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
1605 "vdup", ".32\t$dst, $src",
1606 [(set DPR:$dst, (v2f32 (splat_lo
1608 (f32 (bitconvert GPR:$src))),
1610 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
1611 "vdup", ".32\t$dst, $src",
1612 [(set QPR:$dst, (v4f32 (splat_lo
1614 (f32 (bitconvert GPR:$src))),
1617 // VDUP : Vector Duplicate Lane (from scalar to all elements)
1619 def SHUFFLE_get_splat_lane : SDNodeXForm<vector_shuffle, [{
1620 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1621 return CurDAG->getTargetConstant(SVOp->getSplatIndex(), MVT::i32);
1624 def splat_lane : PatFrag<(ops node:$lhs, node:$rhs),
1625 (vector_shuffle node:$lhs, node:$rhs), [{
1626 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1627 return SVOp->isSplat();
1628 }], SHUFFLE_get_splat_lane>;
1630 class VDUPLND<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty>
1631 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
1632 (outs DPR:$dst), (ins DPR:$src, i32imm:$lane),
1633 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
1634 [(set DPR:$dst, (Ty (splat_lane:$lane DPR:$src, undef)))]>;
1636 // vector_shuffle requires that the source and destination types match, so
1637 // VDUP to a 128-bit result uses a target-specific VDUPLANEQ node.
1638 class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr,
1639 ValueType ResTy, ValueType OpTy>
1640 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
1641 (outs QPR:$dst), (ins DPR:$src, i32imm:$lane),
1642 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
1643 [(set QPR:$dst, (ResTy (NEONvduplaneq (OpTy DPR:$src), imm:$lane)))]>;
1645 def VDUPLN8d : VDUPLND<0b00, 0b01, "vdup.8", v8i8>;
1646 def VDUPLN16d : VDUPLND<0b00, 0b10, "vdup.16", v4i16>;
1647 def VDUPLN32d : VDUPLND<0b01, 0b00, "vdup.32", v2i32>;
1648 def VDUPLNfd : VDUPLND<0b01, 0b00, "vdup.32", v2f32>;
1649 def VDUPLN8q : VDUPLNQ<0b00, 0b01, "vdup.8", v16i8, v8i8>;
1650 def VDUPLN16q : VDUPLNQ<0b00, 0b10, "vdup.16", v8i16, v4i16>;
1651 def VDUPLN32q : VDUPLNQ<0b01, 0b00, "vdup.32", v4i32, v2i32>;
1652 def VDUPLNfq : VDUPLNQ<0b01, 0b00, "vdup.32", v4f32, v2f32>;
1654 // VMOVN : Vector Narrowing Move
1655 defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, "vmovn.i",
1656 int_arm_neon_vmovn>;
1657 // VQMOVN : Vector Saturating Narrowing Move
1658 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, "vqmovn.s",
1659 int_arm_neon_vqmovns>;
1660 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, "vqmovn.u",
1661 int_arm_neon_vqmovnu>;
1662 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, "vqmovun.s",
1663 int_arm_neon_vqmovnsu>;
1664 // VMOVL : Vector Lengthening Move
1665 defm VMOVLs : N2VLInt_QHS<0,1,0b1010,0,0,1, "vmovl.s", int_arm_neon_vmovls>;
1666 defm VMOVLu : N2VLInt_QHS<1,1,0b1010,0,0,1, "vmovl.u", int_arm_neon_vmovlu>;
1668 // Vector Conversions.
1670 // VCVT : Vector Convert Between Floating-Point and Integers
1671 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1672 v2i32, v2f32, fp_to_sint>;
1673 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1674 v2i32, v2f32, fp_to_uint>;
1675 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1676 v2f32, v2i32, sint_to_fp>;
1677 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1678 v2f32, v2i32, uint_to_fp>;
1680 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1681 v4i32, v4f32, fp_to_sint>;
1682 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1683 v4i32, v4f32, fp_to_uint>;
1684 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1685 v4f32, v4i32, sint_to_fp>;
1686 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1687 v4f32, v4i32, uint_to_fp>;
1689 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
1690 // Note: Some of the opcode bits in the following VCVT instructions need to
1691 // be encoded based on the immed values.
1692 def VCVTf2xsd : N2VCvtD<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1693 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
1694 def VCVTf2xud : N2VCvtD<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1695 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
1696 def VCVTxs2fd : N2VCvtD<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1697 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
1698 def VCVTxu2fd : N2VCvtD<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1699 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
1701 def VCVTf2xsq : N2VCvtQ<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1702 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
1703 def VCVTf2xuq : N2VCvtQ<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1704 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
1705 def VCVTxs2fq : N2VCvtQ<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1706 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
1707 def VCVTxu2fq : N2VCvtQ<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1708 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
1710 // VREV : Vector Reverse
1712 def vrev64_shuffle : PatFrag<(ops node:$in),
1713 (vector_shuffle node:$in, undef), [{
1714 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1715 return ARM::isVREVMask(SVOp, 64);
1718 def vrev32_shuffle : PatFrag<(ops node:$in),
1719 (vector_shuffle node:$in, undef), [{
1720 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1721 return ARM::isVREVMask(SVOp, 32);
1724 def vrev16_shuffle : PatFrag<(ops node:$in),
1725 (vector_shuffle node:$in, undef), [{
1726 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1727 return ARM::isVREVMask(SVOp, 16);
1730 // VREV64 : Vector Reverse elements within 64-bit doublewords
1732 class VREV64D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1733 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
1734 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
1735 [(set DPR:$dst, (Ty (vrev64_shuffle (Ty DPR:$src))))]>;
1736 class VREV64Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1737 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
1738 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
1739 [(set QPR:$dst, (Ty (vrev64_shuffle (Ty QPR:$src))))]>;
1741 def VREV64d8 : VREV64D<0b00, "vrev64.8", v8i8>;
1742 def VREV64d16 : VREV64D<0b01, "vrev64.16", v4i16>;
1743 def VREV64d32 : VREV64D<0b10, "vrev64.32", v2i32>;
1744 def VREV64df : VREV64D<0b10, "vrev64.32", v2f32>;
1746 def VREV64q8 : VREV64Q<0b00, "vrev64.8", v16i8>;
1747 def VREV64q16 : VREV64Q<0b01, "vrev64.16", v8i16>;
1748 def VREV64q32 : VREV64Q<0b10, "vrev64.32", v4i32>;
1749 def VREV64qf : VREV64Q<0b10, "vrev64.32", v4f32>;
1751 // VREV32 : Vector Reverse elements within 32-bit words
1753 class VREV32D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1754 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
1755 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
1756 [(set DPR:$dst, (Ty (vrev32_shuffle (Ty DPR:$src))))]>;
1757 class VREV32Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1758 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
1759 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
1760 [(set QPR:$dst, (Ty (vrev32_shuffle (Ty QPR:$src))))]>;
1762 def VREV32d8 : VREV32D<0b00, "vrev32.8", v8i8>;
1763 def VREV32d16 : VREV32D<0b01, "vrev32.16", v4i16>;
1765 def VREV32q8 : VREV32Q<0b00, "vrev32.8", v16i8>;
1766 def VREV32q16 : VREV32Q<0b01, "vrev32.16", v8i16>;
1768 // VREV16 : Vector Reverse elements within 16-bit halfwords
1770 class VREV16D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1771 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
1772 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
1773 [(set DPR:$dst, (Ty (vrev16_shuffle (Ty DPR:$src))))]>;
1774 class VREV16Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1775 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
1776 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
1777 [(set QPR:$dst, (Ty (vrev16_shuffle (Ty QPR:$src))))]>;
1779 def VREV16d8 : VREV16D<0b00, "vrev16.8", v8i8>;
1780 def VREV16q8 : VREV16Q<0b00, "vrev16.8", v16i8>;
1782 //===----------------------------------------------------------------------===//
1783 // Non-Instruction Patterns
1784 //===----------------------------------------------------------------------===//
1787 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
1788 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
1789 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
1790 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
1791 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
1792 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
1793 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
1794 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
1795 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
1796 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
1797 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
1798 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
1799 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
1800 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
1801 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
1802 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
1803 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
1804 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
1805 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
1806 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
1807 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
1808 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
1809 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
1810 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
1811 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
1812 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
1813 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
1814 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
1815 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
1816 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
1818 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
1819 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
1820 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
1821 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
1822 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
1823 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
1824 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
1825 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
1826 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
1827 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
1828 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
1829 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
1830 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
1831 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
1832 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
1833 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
1834 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
1835 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
1836 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
1837 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
1838 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
1839 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
1840 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
1841 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
1842 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
1843 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
1844 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
1845 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
1846 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
1847 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
projects / oota-llvm.git / blob