1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
69 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
70 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
72 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
74 // VDUPLANE can produce a quad-register result from a double-register source,
75 // so the result is not constrained to match the source.
76 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
77 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
80 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
81 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
82 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
84 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
85 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
86 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
87 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
89 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
92 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
93 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
94 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
96 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
98 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
99 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
101 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
102 SDTCisSameAs<0, 2>]>;
103 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
104 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
106 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
107 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
108 unsigned EltBits = 0;
109 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
110 return (EltBits == 32 && EltVal == 0);
113 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
114 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
115 unsigned EltBits = 0;
116 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
117 return (EltBits == 8 && EltVal == 0xff);
120 //===----------------------------------------------------------------------===//
121 // NEON operand definitions
122 //===----------------------------------------------------------------------===//
124 def nModImm : Operand<i32> {
125 let PrintMethod = "printNEONModImmOperand";
128 //===----------------------------------------------------------------------===//
129 // NEON load / store instructions
130 //===----------------------------------------------------------------------===//
132 // Use VLDM to load a Q register as a D register pair.
133 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
135 : PseudoVFPLdStM<(outs QPR:$dst), (ins addrmode4:$addr), IIC_fpLoad_m, "",
136 [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]>;
138 // Use VSTM to store a Q register as a D register pair.
139 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
141 : PseudoVFPLdStM<(outs), (ins QPR:$src, addrmode4:$addr), IIC_fpStore_m, "",
142 [(store (v2f64 QPR:$src), addrmode4:$addr)]>;
144 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
146 // Classes for VLD* pseudo-instructions with multi-register operands.
147 // These are expanded to real instructions after register allocation.
148 class VLDQPseudo<InstrItinClass itin>
149 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
150 class VLDQWBPseudo<InstrItinClass itin>
151 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
152 (ins addrmode6:$addr, am6offset:$offset), itin,
154 class VLDQQPseudo<InstrItinClass itin>
155 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
156 class VLDQQWBPseudo<InstrItinClass itin>
157 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
158 (ins addrmode6:$addr, am6offset:$offset), itin,
160 class VLDQQQQWBPseudo<InstrItinClass itin>
161 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
162 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
163 "$addr.addr = $wb, $src = $dst">;
165 // VLD1 : Vector Load (multiple single elements)
166 class VLD1D<bits<4> op7_4, string Dt>
167 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd),
168 (ins addrmode6:$Rn), IIC_VLD1,
169 "vld1", Dt, "\\{$Vd\\}, $Rn", "", []> {
173 class VLD1Q<bits<4> op7_4, string Dt>
174 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2),
175 (ins addrmode6:$Rn), IIC_VLD1x2,
176 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
178 let Inst{5-4} = Rn{5-4};
181 def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
182 def VLD1d16 : VLD1D<{0,1,0,?}, "16">;
183 def VLD1d32 : VLD1D<{1,0,0,?}, "32">;
184 def VLD1d64 : VLD1D<{1,1,0,?}, "64">;
186 def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;
187 def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
188 def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
189 def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
191 def VLD1q8Pseudo : VLDQPseudo<IIC_VLD1x2>;
192 def VLD1q16Pseudo : VLDQPseudo<IIC_VLD1x2>;
193 def VLD1q32Pseudo : VLDQPseudo<IIC_VLD1x2>;
194 def VLD1q64Pseudo : VLDQPseudo<IIC_VLD1x2>;
196 // ...with address register writeback:
197 class VLD1DWB<bits<4> op7_4, string Dt>
198 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd, GPR:$wb),
199 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1u,
200 "vld1", Dt, "\\{$Vd\\}, $Rn$Rm",
201 "$Rn.addr = $wb", []> {
204 class VLD1QWB<bits<4> op7_4, string Dt>
205 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
206 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x2u,
207 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
208 "$Rn.addr = $wb", []> {
209 let Inst{5-4} = Rn{5-4};
212 def VLD1d8_UPD : VLD1DWB<{0,0,0,?}, "8">;
213 def VLD1d16_UPD : VLD1DWB<{0,1,0,?}, "16">;
214 def VLD1d32_UPD : VLD1DWB<{1,0,0,?}, "32">;
215 def VLD1d64_UPD : VLD1DWB<{1,1,0,?}, "64">;
217 def VLD1q8_UPD : VLD1QWB<{0,0,?,?}, "8">;
218 def VLD1q16_UPD : VLD1QWB<{0,1,?,?}, "16">;
219 def VLD1q32_UPD : VLD1QWB<{1,0,?,?}, "32">;
220 def VLD1q64_UPD : VLD1QWB<{1,1,?,?}, "64">;
222 def VLD1q8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
223 def VLD1q16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
224 def VLD1q32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
225 def VLD1q64Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
227 // ...with 3 registers (some of these are only for the disassembler):
228 class VLD1D3<bits<4> op7_4, string Dt>
229 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
230 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
231 "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
235 class VLD1D3WB<bits<4> op7_4, string Dt>
236 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
237 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x3u, "vld1", Dt,
238 "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
242 def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
243 def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;
244 def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;
245 def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;
247 def VLD1d8T_UPD : VLD1D3WB<{0,0,0,?}, "8">;
248 def VLD1d16T_UPD : VLD1D3WB<{0,1,0,?}, "16">;
249 def VLD1d32T_UPD : VLD1D3WB<{1,0,0,?}, "32">;
250 def VLD1d64T_UPD : VLD1D3WB<{1,1,0,?}, "64">;
252 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
253 def VLD1d64TPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x3u>;
255 // ...with 4 registers (some of these are only for the disassembler):
256 class VLD1D4<bits<4> op7_4, string Dt>
257 : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
258 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
259 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
261 let Inst{5-4} = Rn{5-4};
263 class VLD1D4WB<bits<4> op7_4, string Dt>
264 : NLdSt<0,0b10,0b0010,op7_4,
265 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
266 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4, "vld1", Dt,
267 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", "$Rn.addr = $wb",
269 let Inst{5-4} = Rn{5-4};
272 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
273 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;
274 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;
275 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;
277 def VLD1d8Q_UPD : VLD1D4WB<{0,0,?,?}, "8">;
278 def VLD1d16Q_UPD : VLD1D4WB<{0,1,?,?}, "16">;
279 def VLD1d32Q_UPD : VLD1D4WB<{1,0,?,?}, "32">;
280 def VLD1d64Q_UPD : VLD1D4WB<{1,1,?,?}, "64">;
282 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
283 def VLD1d64QPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x4u>;
285 // VLD2 : Vector Load (multiple 2-element structures)
286 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
287 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
288 (ins addrmode6:$Rn), IIC_VLD2,
289 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
291 let Inst{5-4} = Rn{5-4};
293 class VLD2Q<bits<4> op7_4, string Dt>
294 : NLdSt<0, 0b10, 0b0011, op7_4,
295 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
296 (ins addrmode6:$Rn), IIC_VLD2x2,
297 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
299 let Inst{5-4} = Rn{5-4};
302 def VLD2d8 : VLD2D<0b1000, {0,0,?,?}, "8">;
303 def VLD2d16 : VLD2D<0b1000, {0,1,?,?}, "16">;
304 def VLD2d32 : VLD2D<0b1000, {1,0,?,?}, "32">;
306 def VLD2q8 : VLD2Q<{0,0,?,?}, "8">;
307 def VLD2q16 : VLD2Q<{0,1,?,?}, "16">;
308 def VLD2q32 : VLD2Q<{1,0,?,?}, "32">;
310 def VLD2d8Pseudo : VLDQPseudo<IIC_VLD2>;
311 def VLD2d16Pseudo : VLDQPseudo<IIC_VLD2>;
312 def VLD2d32Pseudo : VLDQPseudo<IIC_VLD2>;
314 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
315 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
316 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
318 // ...with address register writeback:
319 class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
320 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
321 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2u,
322 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
323 "$Rn.addr = $wb", []> {
324 let Inst{5-4} = Rn{5-4};
326 class VLD2QWB<bits<4> op7_4, string Dt>
327 : NLdSt<0, 0b10, 0b0011, op7_4,
328 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
329 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2x2u,
330 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
331 "$Rn.addr = $wb", []> {
332 let Inst{5-4} = Rn{5-4};
335 def VLD2d8_UPD : VLD2DWB<0b1000, {0,0,?,?}, "8">;
336 def VLD2d16_UPD : VLD2DWB<0b1000, {0,1,?,?}, "16">;
337 def VLD2d32_UPD : VLD2DWB<0b1000, {1,0,?,?}, "32">;
339 def VLD2q8_UPD : VLD2QWB<{0,0,?,?}, "8">;
340 def VLD2q16_UPD : VLD2QWB<{0,1,?,?}, "16">;
341 def VLD2q32_UPD : VLD2QWB<{1,0,?,?}, "32">;
343 def VLD2d8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
344 def VLD2d16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
345 def VLD2d32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
347 def VLD2q8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
348 def VLD2q16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
349 def VLD2q32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
351 // ...with double-spaced registers (for disassembly only):
352 def VLD2b8 : VLD2D<0b1001, {0,0,?,?}, "8">;
353 def VLD2b16 : VLD2D<0b1001, {0,1,?,?}, "16">;
354 def VLD2b32 : VLD2D<0b1001, {1,0,?,?}, "32">;
355 def VLD2b8_UPD : VLD2DWB<0b1001, {0,0,?,?}, "8">;
356 def VLD2b16_UPD : VLD2DWB<0b1001, {0,1,?,?}, "16">;
357 def VLD2b32_UPD : VLD2DWB<0b1001, {1,0,?,?}, "32">;
359 // VLD3 : Vector Load (multiple 3-element structures)
360 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
361 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
362 (ins addrmode6:$Rn), IIC_VLD3,
363 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
368 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
369 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
370 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
372 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
373 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
374 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
376 // ...with address register writeback:
377 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
378 : NLdSt<0, 0b10, op11_8, op7_4,
379 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
380 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
381 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
382 "$Rn.addr = $wb", []> {
386 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
387 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
388 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
390 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
391 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
392 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
394 // ...with double-spaced registers (non-updating versions for disassembly only):
395 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
396 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
397 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
398 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
399 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
400 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
402 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
403 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
404 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
406 // ...alternate versions to be allocated odd register numbers:
407 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
408 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
409 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
411 // VLD4 : Vector Load (multiple 4-element structures)
412 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
413 : NLdSt<0, 0b10, op11_8, op7_4,
414 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
415 (ins addrmode6:$Rn), IIC_VLD4,
416 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
418 let Inst{5-4} = Rn{5-4};
421 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
422 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
423 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
425 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
426 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
427 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
429 // ...with address register writeback:
430 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
431 : NLdSt<0, 0b10, op11_8, op7_4,
432 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
433 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4,
434 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
435 "$Rn.addr = $wb", []> {
436 let Inst{5-4} = Rn{5-4};
439 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
440 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
441 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
443 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
444 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
445 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
447 // ...with double-spaced registers (non-updating versions for disassembly only):
448 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
449 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
450 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
451 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
452 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
453 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
455 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
456 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
457 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
459 // ...alternate versions to be allocated odd register numbers:
460 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
461 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
462 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
464 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
466 // Classes for VLD*LN pseudo-instructions with multi-register operands.
467 // These are expanded to real instructions after register allocation.
468 class VLDQLNPseudo<InstrItinClass itin>
469 : PseudoNLdSt<(outs QPR:$dst),
470 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
471 itin, "$src = $dst">;
472 class VLDQLNWBPseudo<InstrItinClass itin>
473 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
474 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
475 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
476 class VLDQQLNPseudo<InstrItinClass itin>
477 : PseudoNLdSt<(outs QQPR:$dst),
478 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
479 itin, "$src = $dst">;
480 class VLDQQLNWBPseudo<InstrItinClass itin>
481 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
482 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
483 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
484 class VLDQQQQLNPseudo<InstrItinClass itin>
485 : PseudoNLdSt<(outs QQQQPR:$dst),
486 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
487 itin, "$src = $dst">;
488 class VLDQQQQLNWBPseudo<InstrItinClass itin>
489 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
490 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
491 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
493 // VLD1LN : Vector Load (single element to one lane)
494 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
496 : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst),
497 (ins addrmode6:$addr, DPR:$src, nohash_imm:$lane),
498 IIC_VLD1ln, "vld1", Dt, "\\{$dst[$lane]\\}, $addr",
500 [(set DPR:$dst, (vector_insert (Ty DPR:$src),
501 (i32 (LoadOp addrmode6:$addr)),
503 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
504 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
505 (i32 (LoadOp addrmode6:$addr)),
509 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8>;
510 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16>;
511 def VLD1LNd32 : VLD1LN<0b1000, {?,0,?,?}, "32", v2i32, load>;
513 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
514 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
515 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
517 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
519 // ...with address register writeback:
520 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
521 : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst, GPR:$wb),
522 (ins addrmode6:$addr, am6offset:$offset,
523 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
524 "\\{$dst[$lane]\\}, $addr$offset",
525 "$src = $dst, $addr.addr = $wb", []>;
527 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8">;
528 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16">;
529 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32">;
531 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
532 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
533 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
535 // VLD2LN : Vector Load (single 2-element structure to one lane)
536 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
537 : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2),
538 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
539 IIC_VLD2ln, "vld2", Dt, "\\{$dst1[$lane], $dst2[$lane]\\}, $addr",
540 "$src1 = $dst1, $src2 = $dst2", []>;
542 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8">;
543 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16">;
544 def VLD2LNd32 : VLD2LN<0b1001, {?,0,?,?}, "32">;
546 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
547 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
548 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
550 // ...with double-spaced registers:
551 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16">;
552 def VLD2LNq32 : VLD2LN<0b1001, {?,1,?,?}, "32">;
554 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
555 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
557 // ...with address register writeback:
558 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
559 : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
560 (ins addrmode6:$addr, am6offset:$offset,
561 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
562 "\\{$dst1[$lane], $dst2[$lane]\\}, $addr$offset",
563 "$src1 = $dst1, $src2 = $dst2, $addr.addr = $wb", []>;
565 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8">;
566 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16">;
567 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,?,?}, "32">;
569 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
570 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
571 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
573 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16">;
574 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,?,?}, "32">;
576 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
577 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
579 // VLD3LN : Vector Load (single 3-element structure to one lane)
580 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
581 : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
582 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
583 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
584 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr",
585 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
587 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8">;
588 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16">;
589 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32">;
591 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
592 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
593 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
595 // ...with double-spaced registers:
596 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16">;
597 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32">;
599 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
600 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
602 // ...with address register writeback:
603 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
604 : NLdSt<1, 0b10, op11_8, op7_4,
605 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
606 (ins addrmode6:$addr, am6offset:$offset,
607 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
608 IIC_VLD3lnu, "vld3", Dt,
609 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr$offset",
610 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $addr.addr = $wb",
613 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8">;
614 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16">;
615 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32">;
617 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
618 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
619 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
621 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16">;
622 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32">;
624 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
625 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
627 // VLD4LN : Vector Load (single 4-element structure to one lane)
628 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
629 : NLdSt<1, 0b10, op11_8, op7_4,
630 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
631 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
632 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
633 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr",
634 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
636 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8">;
637 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16">;
638 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32">;
640 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
641 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
642 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
644 // ...with double-spaced registers:
645 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16">;
646 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32">;
648 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
649 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
651 // ...with address register writeback:
652 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
653 : NLdSt<1, 0b10, op11_8, op7_4,
654 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
655 (ins addrmode6:$addr, am6offset:$offset,
656 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
657 IIC_VLD4ln, "vld4", Dt,
658 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr$offset",
659 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $addr.addr = $wb",
662 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8">;
663 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16">;
664 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32">;
666 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
667 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
668 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
670 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16">;
671 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32">;
673 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
674 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
676 // VLD1DUP : Vector Load (single element to all lanes)
677 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
678 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
679 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
680 // FIXME: Not yet implemented.
681 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
683 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
685 // Classes for VST* pseudo-instructions with multi-register operands.
686 // These are expanded to real instructions after register allocation.
687 class VSTQPseudo<InstrItinClass itin>
688 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
689 class VSTQWBPseudo<InstrItinClass itin>
690 : PseudoNLdSt<(outs GPR:$wb),
691 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
693 class VSTQQPseudo<InstrItinClass itin>
694 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
695 class VSTQQWBPseudo<InstrItinClass itin>
696 : PseudoNLdSt<(outs GPR:$wb),
697 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
699 class VSTQQQQWBPseudo<InstrItinClass itin>
700 : PseudoNLdSt<(outs GPR:$wb),
701 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
704 // VST1 : Vector Store (multiple single elements)
705 class VST1D<bits<4> op7_4, string Dt>
706 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src),
707 IIC_VST1, "vst1", Dt, "\\{$src\\}, $addr", "", []>;
708 class VST1Q<bits<4> op7_4, string Dt>
709 : NLdSt<0,0b00,0b1010,op7_4, (outs),
710 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST1x2,
711 "vst1", Dt, "\\{$src1, $src2\\}, $addr", "", []>;
713 def VST1d8 : VST1D<0b0000, "8">;
714 def VST1d16 : VST1D<0b0100, "16">;
715 def VST1d32 : VST1D<0b1000, "32">;
716 def VST1d64 : VST1D<0b1100, "64">;
718 def VST1q8 : VST1Q<0b0000, "8">;
719 def VST1q16 : VST1Q<0b0100, "16">;
720 def VST1q32 : VST1Q<0b1000, "32">;
721 def VST1q64 : VST1Q<0b1100, "64">;
723 def VST1q8Pseudo : VSTQPseudo<IIC_VST1x2>;
724 def VST1q16Pseudo : VSTQPseudo<IIC_VST1x2>;
725 def VST1q32Pseudo : VSTQPseudo<IIC_VST1x2>;
726 def VST1q64Pseudo : VSTQPseudo<IIC_VST1x2>;
728 // ...with address register writeback:
729 class VST1DWB<bits<4> op7_4, string Dt>
730 : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
731 (ins addrmode6:$addr, am6offset:$offset, DPR:$src), IIC_VST1u,
732 "vst1", Dt, "\\{$src\\}, $addr$offset", "$addr.addr = $wb", []>;
733 class VST1QWB<bits<4> op7_4, string Dt>
734 : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),
735 (ins addrmode6:$addr, am6offset:$offset, DPR:$src1, DPR:$src2),
736 IIC_VST1x2u, "vst1", Dt, "\\{$src1, $src2\\}, $addr$offset",
737 "$addr.addr = $wb", []>;
739 def VST1d8_UPD : VST1DWB<0b0000, "8">;
740 def VST1d16_UPD : VST1DWB<0b0100, "16">;
741 def VST1d32_UPD : VST1DWB<0b1000, "32">;
742 def VST1d64_UPD : VST1DWB<0b1100, "64">;
744 def VST1q8_UPD : VST1QWB<0b0000, "8">;
745 def VST1q16_UPD : VST1QWB<0b0100, "16">;
746 def VST1q32_UPD : VST1QWB<0b1000, "32">;
747 def VST1q64_UPD : VST1QWB<0b1100, "64">;
749 def VST1q8Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
750 def VST1q16Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
751 def VST1q32Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
752 def VST1q64Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
754 // ...with 3 registers (some of these are only for the disassembler):
755 class VST1D3<bits<4> op7_4, string Dt>
756 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
757 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
758 IIC_VST1x3, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>;
759 class VST1D3WB<bits<4> op7_4, string Dt>
760 : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
761 (ins addrmode6:$addr, am6offset:$offset,
762 DPR:$src1, DPR:$src2, DPR:$src3),
763 IIC_VST1x3u, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr$offset",
764 "$addr.addr = $wb", []>;
766 def VST1d8T : VST1D3<0b0000, "8">;
767 def VST1d16T : VST1D3<0b0100, "16">;
768 def VST1d32T : VST1D3<0b1000, "32">;
769 def VST1d64T : VST1D3<0b1100, "64">;
771 def VST1d8T_UPD : VST1D3WB<0b0000, "8">;
772 def VST1d16T_UPD : VST1D3WB<0b0100, "16">;
773 def VST1d32T_UPD : VST1D3WB<0b1000, "32">;
774 def VST1d64T_UPD : VST1D3WB<0b1100, "64">;
776 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
777 def VST1d64TPseudo_UPD : VSTQQWBPseudo<IIC_VST1x3u>;
779 // ...with 4 registers (some of these are only for the disassembler):
780 class VST1D4<bits<4> op7_4, string Dt>
781 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
782 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
783 IIC_VST1x4, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr", "",
785 class VST1D4WB<bits<4> op7_4, string Dt>
786 : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
787 (ins addrmode6:$addr, am6offset:$offset,
788 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST1x4u,
789 "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
790 "$addr.addr = $wb", []>;
792 def VST1d8Q : VST1D4<0b0000, "8">;
793 def VST1d16Q : VST1D4<0b0100, "16">;
794 def VST1d32Q : VST1D4<0b1000, "32">;
795 def VST1d64Q : VST1D4<0b1100, "64">;
797 def VST1d8Q_UPD : VST1D4WB<0b0000, "8">;
798 def VST1d16Q_UPD : VST1D4WB<0b0100, "16">;
799 def VST1d32Q_UPD : VST1D4WB<0b1000, "32">;
800 def VST1d64Q_UPD : VST1D4WB<0b1100, "64">;
802 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
803 def VST1d64QPseudo_UPD : VSTQQWBPseudo<IIC_VST1x4u>;
805 // VST2 : Vector Store (multiple 2-element structures)
806 class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
807 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
808 (ins addrmode6:$addr, DPR:$src1, DPR:$src2),
809 IIC_VST2, "vst2", Dt, "\\{$src1, $src2\\}, $addr", "", []>;
810 class VST2Q<bits<4> op7_4, string Dt>
811 : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
812 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
813 IIC_VST2x2, "vst2", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
816 def VST2d8 : VST2D<0b1000, 0b0000, "8">;
817 def VST2d16 : VST2D<0b1000, 0b0100, "16">;
818 def VST2d32 : VST2D<0b1000, 0b1000, "32">;
820 def VST2q8 : VST2Q<0b0000, "8">;
821 def VST2q16 : VST2Q<0b0100, "16">;
822 def VST2q32 : VST2Q<0b1000, "32">;
824 def VST2d8Pseudo : VSTQPseudo<IIC_VST2>;
825 def VST2d16Pseudo : VSTQPseudo<IIC_VST2>;
826 def VST2d32Pseudo : VSTQPseudo<IIC_VST2>;
828 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
829 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
830 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
832 // ...with address register writeback:
833 class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
834 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
835 (ins addrmode6:$addr, am6offset:$offset, DPR:$src1, DPR:$src2),
836 IIC_VST2u, "vst2", Dt, "\\{$src1, $src2\\}, $addr$offset",
837 "$addr.addr = $wb", []>;
838 class VST2QWB<bits<4> op7_4, string Dt>
839 : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
840 (ins addrmode6:$addr, am6offset:$offset,
841 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST2x2u,
842 "vst2", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
843 "$addr.addr = $wb", []>;
845 def VST2d8_UPD : VST2DWB<0b1000, 0b0000, "8">;
846 def VST2d16_UPD : VST2DWB<0b1000, 0b0100, "16">;
847 def VST2d32_UPD : VST2DWB<0b1000, 0b1000, "32">;
849 def VST2q8_UPD : VST2QWB<0b0000, "8">;
850 def VST2q16_UPD : VST2QWB<0b0100, "16">;
851 def VST2q32_UPD : VST2QWB<0b1000, "32">;
853 def VST2d8Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
854 def VST2d16Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
855 def VST2d32Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
857 def VST2q8Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
858 def VST2q16Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
859 def VST2q32Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
861 // ...with double-spaced registers (for disassembly only):
862 def VST2b8 : VST2D<0b1001, 0b0000, "8">;
863 def VST2b16 : VST2D<0b1001, 0b0100, "16">;
864 def VST2b32 : VST2D<0b1001, 0b1000, "32">;
865 def VST2b8_UPD : VST2DWB<0b1001, 0b0000, "8">;
866 def VST2b16_UPD : VST2DWB<0b1001, 0b0100, "16">;
867 def VST2b32_UPD : VST2DWB<0b1001, 0b1000, "32">;
869 // VST3 : Vector Store (multiple 3-element structures)
870 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
871 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
872 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST3,
873 "vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>;
875 def VST3d8 : VST3D<0b0100, 0b0000, "8">;
876 def VST3d16 : VST3D<0b0100, 0b0100, "16">;
877 def VST3d32 : VST3D<0b0100, 0b1000, "32">;
879 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
880 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
881 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
883 // ...with address register writeback:
884 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
885 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
886 (ins addrmode6:$addr, am6offset:$offset,
887 DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST3u,
888 "vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr$offset",
889 "$addr.addr = $wb", []>;
891 def VST3d8_UPD : VST3DWB<0b0100, 0b0000, "8">;
892 def VST3d16_UPD : VST3DWB<0b0100, 0b0100, "16">;
893 def VST3d32_UPD : VST3DWB<0b0100, 0b1000, "32">;
895 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
896 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
897 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
899 // ...with double-spaced registers (non-updating versions for disassembly only):
900 def VST3q8 : VST3D<0b0101, 0b0000, "8">;
901 def VST3q16 : VST3D<0b0101, 0b0100, "16">;
902 def VST3q32 : VST3D<0b0101, 0b1000, "32">;
903 def VST3q8_UPD : VST3DWB<0b0101, 0b0000, "8">;
904 def VST3q16_UPD : VST3DWB<0b0101, 0b0100, "16">;
905 def VST3q32_UPD : VST3DWB<0b0101, 0b1000, "32">;
907 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
908 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
909 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
911 // ...alternate versions to be allocated odd register numbers:
912 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
913 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
914 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
916 // VST4 : Vector Store (multiple 4-element structures)
917 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
918 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
919 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
920 IIC_VST4, "vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
923 def VST4d8 : VST4D<0b0000, 0b0000, "8">;
924 def VST4d16 : VST4D<0b0000, 0b0100, "16">;
925 def VST4d32 : VST4D<0b0000, 0b1000, "32">;
927 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
928 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
929 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
931 // ...with address register writeback:
932 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
933 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
934 (ins addrmode6:$addr, am6offset:$offset,
935 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
936 "vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
937 "$addr.addr = $wb", []>;
939 def VST4d8_UPD : VST4DWB<0b0000, 0b0000, "8">;
940 def VST4d16_UPD : VST4DWB<0b0000, 0b0100, "16">;
941 def VST4d32_UPD : VST4DWB<0b0000, 0b1000, "32">;
943 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
944 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
945 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
947 // ...with double-spaced registers (non-updating versions for disassembly only):
948 def VST4q8 : VST4D<0b0001, 0b0000, "8">;
949 def VST4q16 : VST4D<0b0001, 0b0100, "16">;
950 def VST4q32 : VST4D<0b0001, 0b1000, "32">;
951 def VST4q8_UPD : VST4DWB<0b0001, 0b0000, "8">;
952 def VST4q16_UPD : VST4DWB<0b0001, 0b0100, "16">;
953 def VST4q32_UPD : VST4DWB<0b0001, 0b1000, "32">;
955 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
956 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
957 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
959 // ...alternate versions to be allocated odd register numbers:
960 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
961 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
962 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
964 // Classes for VST*LN pseudo-instructions with multi-register operands.
965 // These are expanded to real instructions after register allocation.
966 class VSTQLNPseudo<InstrItinClass itin>
967 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
969 class VSTQLNWBPseudo<InstrItinClass itin>
970 : PseudoNLdSt<(outs GPR:$wb),
971 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
972 nohash_imm:$lane), itin, "$addr.addr = $wb">;
973 class VSTQQLNPseudo<InstrItinClass itin>
974 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
976 class VSTQQLNWBPseudo<InstrItinClass itin>
977 : PseudoNLdSt<(outs GPR:$wb),
978 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
979 nohash_imm:$lane), itin, "$addr.addr = $wb">;
980 class VSTQQQQLNPseudo<InstrItinClass itin>
981 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
983 class VSTQQQQLNWBPseudo<InstrItinClass itin>
984 : PseudoNLdSt<(outs GPR:$wb),
985 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
986 nohash_imm:$lane), itin, "$addr.addr = $wb">;
988 // VST1LN : Vector Store (single element from one lane)
989 // FIXME: Not yet implemented.
991 // VST2LN : Vector Store (single 2-element structure from one lane)
992 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
993 : NLdSt<1, 0b00, op11_8, op7_4, (outs),
994 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
995 IIC_VST2ln, "vst2", Dt, "\\{$src1[$lane], $src2[$lane]\\}, $addr",
998 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8">;
999 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16">;
1000 def VST2LNd32 : VST2LN<0b1001, {?,0,?,?}, "32">;
1002 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1003 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1004 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1006 // ...with double-spaced registers:
1007 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16">;
1008 def VST2LNq32 : VST2LN<0b1001, {?,1,?,?}, "32">;
1010 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1011 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1013 // ...with address register writeback:
1014 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1015 : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1016 (ins addrmode6:$addr, am6offset:$offset,
1017 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
1018 "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset",
1019 "$addr.addr = $wb", []>;
1021 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8">;
1022 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16">;
1023 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,?,?}, "32">;
1025 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1026 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1027 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1029 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16">;
1030 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,?,?}, "32">;
1032 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1033 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1035 // VST3LN : Vector Store (single 3-element structure from one lane)
1036 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1037 : NLdSt<1, 0b00, op11_8, op7_4, (outs),
1038 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
1039 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
1040 "\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr", "", []>;
1042 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8">;
1043 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16">;
1044 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32">;
1046 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1047 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1048 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1050 // ...with double-spaced registers:
1051 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16">;
1052 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32">;
1054 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1055 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1057 // ...with address register writeback:
1058 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1059 : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1060 (ins addrmode6:$addr, am6offset:$offset,
1061 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1062 IIC_VST3lnu, "vst3", Dt,
1063 "\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr$offset",
1064 "$addr.addr = $wb", []>;
1066 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8">;
1067 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16">;
1068 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32">;
1070 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1071 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1072 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1074 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16">;
1075 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32">;
1077 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1078 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1080 // VST4LN : Vector Store (single 4-element structure from one lane)
1081 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1082 : NLdSt<1, 0b00, op11_8, op7_4, (outs),
1083 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
1084 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
1085 "\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr",
1088 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8">;
1089 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16">;
1090 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32">;
1092 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1093 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1094 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1096 // ...with double-spaced registers:
1097 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16">;
1098 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32">;
1100 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1101 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1103 // ...with address register writeback:
1104 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1105 : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1106 (ins addrmode6:$addr, am6offset:$offset,
1107 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1108 IIC_VST4lnu, "vst4", Dt,
1109 "\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr$offset",
1110 "$addr.addr = $wb", []>;
1112 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8">;
1113 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16">;
1114 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32">;
1116 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1117 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1118 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1120 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16">;
1121 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32">;
1123 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1124 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1126 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1129 //===----------------------------------------------------------------------===//
1130 // NEON pattern fragments
1131 //===----------------------------------------------------------------------===//
1133 // Extract D sub-registers of Q registers.
1134 def DSubReg_i8_reg : SDNodeXForm<imm, [{
1135 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1136 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
1138 def DSubReg_i16_reg : SDNodeXForm<imm, [{
1139 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1140 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
1142 def DSubReg_i32_reg : SDNodeXForm<imm, [{
1143 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1144 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
1146 def DSubReg_f64_reg : SDNodeXForm<imm, [{
1147 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1148 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
1151 // Extract S sub-registers of Q/D registers.
1152 def SSubReg_f32_reg : SDNodeXForm<imm, [{
1153 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
1154 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
1157 // Translate lane numbers from Q registers to D subregs.
1158 def SubReg_i8_lane : SDNodeXForm<imm, [{
1159 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
1161 def SubReg_i16_lane : SDNodeXForm<imm, [{
1162 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
1164 def SubReg_i32_lane : SDNodeXForm<imm, [{
1165 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
1168 //===----------------------------------------------------------------------===//
1169 // Instruction Classes
1170 //===----------------------------------------------------------------------===//
1172 // Basic 2-register operations: single-, double- and quad-register.
1173 class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1174 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1175 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1176 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
1177 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
1178 IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
1179 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1180 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1181 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1182 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1183 (ins DPR:$src), IIC_VUNAD, OpcodeStr, Dt,"$dst, $src", "",
1184 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
1185 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1186 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1187 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1188 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1189 (ins QPR:$src), IIC_VUNAQ, OpcodeStr, Dt,"$dst, $src", "",
1190 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
1192 // Basic 2-register intrinsics, both double- and quad-register.
1193 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1194 bits<2> op17_16, bits<5> op11_7, bit op4,
1195 InstrItinClass itin, string OpcodeStr, string Dt,
1196 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1197 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1198 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1199 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
1200 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1201 bits<2> op17_16, bits<5> op11_7, bit op4,
1202 InstrItinClass itin, string OpcodeStr, string Dt,
1203 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1204 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1205 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1206 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
1208 // Narrow 2-register operations.
1209 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1210 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1211 InstrItinClass itin, string OpcodeStr, string Dt,
1212 ValueType TyD, ValueType TyQ, SDNode OpNode>
1213 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
1214 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1215 [(set DPR:$dst, (TyD (OpNode (TyQ QPR:$src))))]>;
1217 // Narrow 2-register intrinsics.
1218 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1219 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1220 InstrItinClass itin, string OpcodeStr, string Dt,
1221 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
1222 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
1223 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1224 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
1226 // Long 2-register operations (currently only used for VMOVL).
1227 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1228 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1229 InstrItinClass itin, string OpcodeStr, string Dt,
1230 ValueType TyQ, ValueType TyD, SDNode OpNode>
1231 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$dst),
1232 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1233 [(set QPR:$dst, (TyQ (OpNode (TyD DPR:$src))))]>;
1235 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
1236 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
1237 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
1238 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
1239 OpcodeStr, Dt, "$dst1, $dst2",
1240 "$src1 = $dst1, $src2 = $dst2", []>;
1241 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
1242 InstrItinClass itin, string OpcodeStr, string Dt>
1243 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
1244 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$dst1, $dst2",
1245 "$src1 = $dst1, $src2 = $dst2", []>;
1247 // Basic 3-register operations: single-, double- and quad-register.
1248 class N3VS<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1249 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1250 SDNode OpNode, bit Commutable>
1251 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1252 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm,
1253 IIC_VBIND, OpcodeStr, Dt, "$dst, $src1, $src2", "", []> {
1254 let isCommutable = Commutable;
1257 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1258 InstrItinClass itin, string OpcodeStr, string Dt,
1259 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1260 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1261 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1262 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1263 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
1264 let isCommutable = Commutable;
1266 // Same as N3VD but no data type.
1267 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1268 InstrItinClass itin, string OpcodeStr,
1269 ValueType ResTy, ValueType OpTy,
1270 SDNode OpNode, bit Commutable>
1271 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
1272 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1273 OpcodeStr, "$dst, $src1, $src2", "",
1274 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]>{
1275 let isCommutable = Commutable;
1278 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
1279 InstrItinClass itin, string OpcodeStr, string Dt,
1280 ValueType Ty, SDNode ShOp>
1281 : N3V<0, 1, op21_20, op11_8, 1, 0,
1282 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1283 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1284 [(set (Ty DPR:$dst),
1285 (Ty (ShOp (Ty DPR:$src1),
1286 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),imm:$lane)))))]> {
1287 let isCommutable = 0;
1289 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
1290 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1291 : N3V<0, 1, op21_20, op11_8, 1, 0,
1292 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1293 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$dst, $src1, $src2[$lane]","",
1294 [(set (Ty DPR:$dst),
1295 (Ty (ShOp (Ty DPR:$src1),
1296 (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
1297 let isCommutable = 0;
1300 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1301 InstrItinClass itin, string OpcodeStr, string Dt,
1302 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1303 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1304 (outs QPR:$Qd), (ins QPR:$Qn, QPR:$Qm), N3RegFrm, itin,
1305 OpcodeStr, Dt, "$Qd, $Qn, $Qm", "",
1306 [(set QPR:$Qd, (ResTy (OpNode (OpTy QPR:$Qn), (OpTy QPR:$Qm))))]> {
1307 let isCommutable = Commutable;
1309 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1310 InstrItinClass itin, string OpcodeStr,
1311 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1312 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
1313 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, itin,
1314 OpcodeStr, "$dst, $src1, $src2", "",
1315 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]>{
1316 let isCommutable = Commutable;
1318 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
1319 InstrItinClass itin, string OpcodeStr, string Dt,
1320 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1321 : N3V<1, 1, op21_20, op11_8, 1, 0,
1322 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1323 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1324 [(set (ResTy QPR:$dst),
1325 (ResTy (ShOp (ResTy QPR:$src1),
1326 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1328 let isCommutable = 0;
1330 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
1331 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1332 : N3V<1, 1, op21_20, op11_8, 1, 0,
1333 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1334 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$dst, $src1, $src2[$lane]","",
1335 [(set (ResTy QPR:$dst),
1336 (ResTy (ShOp (ResTy QPR:$src1),
1337 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
1339 let isCommutable = 0;
1342 // Basic 3-register intrinsics, both double- and quad-register.
1343 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1344 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1345 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1346 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1347 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
1348 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1349 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
1350 let isCommutable = Commutable;
1352 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1353 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1354 : N3V<0, 1, op21_20, op11_8, 1, 0,
1355 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1356 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1357 [(set (Ty DPR:$dst),
1358 (Ty (IntOp (Ty DPR:$src1),
1359 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
1361 let isCommutable = 0;
1363 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1364 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1365 : N3V<0, 1, op21_20, op11_8, 1, 0,
1366 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1367 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1368 [(set (Ty DPR:$dst),
1369 (Ty (IntOp (Ty DPR:$src1),
1370 (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
1371 let isCommutable = 0;
1373 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1374 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1375 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1376 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1377 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
1378 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
1379 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
1380 let isCommutable = 0;
1383 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1384 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1385 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1386 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1387 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
1388 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1389 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
1390 let isCommutable = Commutable;
1392 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1393 string OpcodeStr, string Dt,
1394 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1395 : N3V<1, 1, op21_20, op11_8, 1, 0,
1396 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1397 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1398 [(set (ResTy QPR:$dst),
1399 (ResTy (IntOp (ResTy QPR:$src1),
1400 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1402 let isCommutable = 0;
1404 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1405 string OpcodeStr, string Dt,
1406 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1407 : N3V<1, 1, op21_20, op11_8, 1, 0,
1408 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1409 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1410 [(set (ResTy QPR:$dst),
1411 (ResTy (IntOp (ResTy QPR:$src1),
1412 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
1414 let isCommutable = 0;
1416 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1417 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1418 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1419 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1420 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
1421 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
1422 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
1423 let isCommutable = 0;
1426 // Multiply-Add/Sub operations: single-, double- and quad-register.
1427 class N3VSMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1428 InstrItinClass itin, string OpcodeStr, string Dt,
1429 ValueType Ty, SDNode MulOp, SDNode OpNode>
1430 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1431 (outs DPR_VFP2:$dst),
1432 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), N3RegFrm, itin,
1433 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst", []>;
1435 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1436 InstrItinClass itin, string OpcodeStr, string Dt,
1437 ValueType Ty, SDNode MulOp, SDNode OpNode>
1438 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1439 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1440 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1441 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
1442 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
1444 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1445 string OpcodeStr, string Dt,
1446 ValueType Ty, SDNode MulOp, SDNode ShOp>
1447 : N3V<0, 1, op21_20, op11_8, 1, 0,
1449 (ins DPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1451 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1452 [(set (Ty DPR:$dst),
1453 (Ty (ShOp (Ty DPR:$src1),
1454 (Ty (MulOp DPR:$src2,
1455 (Ty (NEONvduplane (Ty DPR_VFP2:$src3),
1457 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1458 string OpcodeStr, string Dt,
1459 ValueType Ty, SDNode MulOp, SDNode ShOp>
1460 : N3V<0, 1, op21_20, op11_8, 1, 0,
1462 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1464 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
1466 (Ty (ShOp (Ty DPR:$src1),
1468 (Ty (NEONvduplane (Ty DPR_8:$Vm),
1471 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1472 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
1473 SDNode MulOp, SDNode OpNode>
1474 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1475 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1476 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1477 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
1478 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
1479 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1480 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1481 SDNode MulOp, SDNode ShOp>
1482 : N3V<1, 1, op21_20, op11_8, 1, 0,
1484 (ins QPR:$src1, QPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1486 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1487 [(set (ResTy QPR:$dst),
1488 (ResTy (ShOp (ResTy QPR:$src1),
1489 (ResTy (MulOp QPR:$src2,
1490 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src3),
1492 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1493 string OpcodeStr, string Dt,
1494 ValueType ResTy, ValueType OpTy,
1495 SDNode MulOp, SDNode ShOp>
1496 : N3V<1, 1, op21_20, op11_8, 1, 0,
1498 (ins QPR:$src1, QPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1500 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1501 [(set (ResTy QPR:$dst),
1502 (ResTy (ShOp (ResTy QPR:$src1),
1503 (ResTy (MulOp QPR:$src2,
1504 (ResTy (NEONvduplane (OpTy DPR_8:$src3),
1507 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
1508 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1509 InstrItinClass itin, string OpcodeStr, string Dt,
1510 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
1511 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1512 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1513 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1514 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
1515 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
1516 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1517 InstrItinClass itin, string OpcodeStr, string Dt,
1518 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
1519 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1520 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1521 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1522 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
1523 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
1525 // Neon 3-argument intrinsics, both double- and quad-register.
1526 // The destination register is also used as the first source operand register.
1527 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1528 InstrItinClass itin, string OpcodeStr, string Dt,
1529 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1530 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1531 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1532 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1533 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
1534 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
1535 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1536 InstrItinClass itin, string OpcodeStr, string Dt,
1537 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1538 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1539 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), N3RegFrm, itin,
1540 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1541 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
1542 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
1544 // Long Multiply-Add/Sub operations.
1545 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1546 InstrItinClass itin, string OpcodeStr, string Dt,
1547 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
1548 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1549 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1550 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1551 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
1552 (TyQ (MulOp (TyD DPR:$Vn),
1553 (TyD DPR:$Vm)))))]>;
1554 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
1555 InstrItinClass itin, string OpcodeStr, string Dt,
1556 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
1557 : N3V<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$dst),
1558 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1560 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1562 (OpNode (TyQ QPR:$src1),
1563 (TyQ (MulOp (TyD DPR:$src2),
1564 (TyD (NEONvduplane (TyD DPR_VFP2:$src3),
1566 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1567 InstrItinClass itin, string OpcodeStr, string Dt,
1568 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
1569 : N3V<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$dst),
1570 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1572 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1574 (OpNode (TyQ QPR:$src1),
1575 (TyQ (MulOp (TyD DPR:$src2),
1576 (TyD (NEONvduplane (TyD DPR_8:$src3),
1579 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
1580 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1581 InstrItinClass itin, string OpcodeStr, string Dt,
1582 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
1584 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1585 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1586 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1587 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
1588 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
1589 (TyD DPR:$Vm)))))))]>;
1591 // Neon Long 3-argument intrinsic. The destination register is
1592 // a quad-register and is also used as the first source operand register.
1593 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1594 InstrItinClass itin, string OpcodeStr, string Dt,
1595 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
1596 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1597 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1598 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1600 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
1601 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1602 string OpcodeStr, string Dt,
1603 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1604 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1606 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1608 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1609 [(set (ResTy QPR:$dst),
1610 (ResTy (IntOp (ResTy QPR:$src1),
1612 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src3),
1614 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1615 InstrItinClass itin, string OpcodeStr, string Dt,
1616 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1617 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1619 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1621 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1622 [(set (ResTy QPR:$dst),
1623 (ResTy (IntOp (ResTy QPR:$src1),
1625 (OpTy (NEONvduplane (OpTy DPR_8:$src3),
1628 // Narrowing 3-register intrinsics.
1629 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1630 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
1631 Intrinsic IntOp, bit Commutable>
1632 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1633 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINi4D,
1634 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1635 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
1636 let isCommutable = Commutable;
1639 // Long 3-register operations.
1640 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1641 InstrItinClass itin, string OpcodeStr, string Dt,
1642 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
1643 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1644 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1645 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1646 [(set QPR:$dst, (TyQ (OpNode (TyD DPR:$src1), (TyD DPR:$src2))))]> {
1647 let isCommutable = Commutable;
1649 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
1650 InstrItinClass itin, string OpcodeStr, string Dt,
1651 ValueType TyQ, ValueType TyD, SDNode OpNode>
1652 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1653 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1654 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1656 (TyQ (OpNode (TyD DPR:$src1),
1657 (TyD (NEONvduplane (TyD DPR_VFP2:$src2),imm:$lane)))))]>;
1658 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1659 InstrItinClass itin, string OpcodeStr, string Dt,
1660 ValueType TyQ, ValueType TyD, SDNode OpNode>
1661 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1662 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1663 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1665 (TyQ (OpNode (TyD DPR:$src1),
1666 (TyD (NEONvduplane (TyD DPR_8:$src2), imm:$lane)))))]>;
1668 // Long 3-register operations with explicitly extended operands.
1669 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1670 InstrItinClass itin, string OpcodeStr, string Dt,
1671 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
1673 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1674 (outs QPR:$Qd), (ins DPR:$Dn, DPR:$Dm), N3RegFrm, itin,
1675 OpcodeStr, Dt, "$Qd, $Dn, $Dm", "",
1676 [(set QPR:$Qd, (OpNode (TyQ (ExtOp (TyD DPR:$Dn))),
1677 (TyQ (ExtOp (TyD DPR:$Dm)))))]> {
1678 let isCommutable = Commutable;
1681 // Long 3-register intrinsics with explicit extend (VABDL).
1682 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1683 InstrItinClass itin, string OpcodeStr, string Dt,
1684 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
1686 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1687 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1688 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1689 [(set QPR:$dst, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$src1),
1690 (TyD DPR:$src2))))))]> {
1691 let isCommutable = Commutable;
1694 // Long 3-register intrinsics.
1695 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1696 InstrItinClass itin, string OpcodeStr, string Dt,
1697 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
1698 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1699 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1700 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1701 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
1702 let isCommutable = Commutable;
1704 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1705 string OpcodeStr, string Dt,
1706 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1707 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1708 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1709 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1710 [(set (ResTy QPR:$dst),
1711 (ResTy (IntOp (OpTy DPR:$src1),
1712 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1714 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1715 InstrItinClass itin, string OpcodeStr, string Dt,
1716 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1717 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1718 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1719 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1720 [(set (ResTy QPR:$dst),
1721 (ResTy (IntOp (OpTy DPR:$src1),
1722 (OpTy (NEONvduplane (OpTy DPR_8:$src2),
1725 // Wide 3-register operations.
1726 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1727 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
1728 SDNode OpNode, SDNode ExtOp, bit Commutable>
1729 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1730 (outs QPR:$Qd), (ins QPR:$Qn, DPR:$Dm), N3RegFrm, IIC_VSUBiD,
1731 OpcodeStr, Dt, "$Qd, $Qn, $Dm", "",
1732 [(set QPR:$Qd, (OpNode (TyQ QPR:$Qn),
1733 (TyQ (ExtOp (TyD DPR:$Dm)))))]> {
1734 let isCommutable = Commutable;
1737 // Pairwise long 2-register intrinsics, both double- and quad-register.
1738 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1739 bits<2> op17_16, bits<5> op11_7, bit op4,
1740 string OpcodeStr, string Dt,
1741 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1742 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1743 (ins DPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
1744 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
1745 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1746 bits<2> op17_16, bits<5> op11_7, bit op4,
1747 string OpcodeStr, string Dt,
1748 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1749 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1750 (ins QPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
1751 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
1753 // Pairwise long 2-register accumulate intrinsics,
1754 // both double- and quad-register.
1755 // The destination register is also used as the first source operand register.
1756 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1757 bits<2> op17_16, bits<5> op11_7, bit op4,
1758 string OpcodeStr, string Dt,
1759 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1760 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
1761 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
1762 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
1763 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
1764 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1765 bits<2> op17_16, bits<5> op11_7, bit op4,
1766 string OpcodeStr, string Dt,
1767 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1768 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
1769 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
1770 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
1771 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
1773 // Shift by immediate,
1774 // both double- and quad-register.
1775 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1776 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1777 ValueType Ty, SDNode OpNode>
1778 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1779 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), f, itin,
1780 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1781 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
1782 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1783 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1784 ValueType Ty, SDNode OpNode>
1785 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1786 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), f, itin,
1787 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1788 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
1790 // Long shift by immediate.
1791 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1792 string OpcodeStr, string Dt,
1793 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1794 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1795 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), N2RegVShLFrm,
1796 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1797 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
1798 (i32 imm:$SIMM))))]>;
1800 // Narrow shift by immediate.
1801 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1802 InstrItinClass itin, string OpcodeStr, string Dt,
1803 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1804 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1805 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), N2RegVShRFrm, itin,
1806 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1807 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
1808 (i32 imm:$SIMM))))]>;
1810 // Shift right by immediate and accumulate,
1811 // both double- and quad-register.
1812 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1813 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1814 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
1815 (ins DPR:$src1, DPR:$Vm, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
1816 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
1817 [(set DPR:$Vd, (Ty (add DPR:$src1,
1818 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
1819 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1820 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1821 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
1822 (ins QPR:$src1, QPR:$Vm, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
1823 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
1824 [(set QPR:$Vd, (Ty (add QPR:$src1,
1825 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
1827 // Shift by immediate and insert,
1828 // both double- and quad-register.
1829 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1830 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
1831 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
1832 (ins DPR:$src1, DPR:$Vm, i32imm:$SIMM), f, IIC_VSHLiD,
1833 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
1834 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
1835 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1836 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
1837 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
1838 (ins QPR:$src1, QPR:$Vm, i32imm:$SIMM), f, IIC_VSHLiQ,
1839 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
1840 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
1842 // Convert, with fractional bits immediate,
1843 // both double- and quad-register.
1844 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1845 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1847 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1848 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
1849 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
1850 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
1851 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1852 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1854 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1855 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
1856 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
1857 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
1859 //===----------------------------------------------------------------------===//
1861 //===----------------------------------------------------------------------===//
1863 // Abbreviations used in multiclass suffixes:
1864 // Q = quarter int (8 bit) elements
1865 // H = half int (16 bit) elements
1866 // S = single int (32 bit) elements
1867 // D = double int (64 bit) elements
1869 // Neon 2-register vector operations -- for disassembly only.
1871 // First with only element sizes of 8, 16 and 32 bits:
1872 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1873 bits<5> op11_7, bit op4, string opc, string Dt,
1875 // 64-bit vector types.
1876 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
1877 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1878 opc, !strconcat(Dt, "8"), asm, "", []>;
1879 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
1880 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1881 opc, !strconcat(Dt, "16"), asm, "", []>;
1882 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
1883 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1884 opc, !strconcat(Dt, "32"), asm, "", []>;
1885 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
1886 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1887 opc, "f32", asm, "", []> {
1888 let Inst{10} = 1; // overwrite F = 1
1891 // 128-bit vector types.
1892 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
1893 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1894 opc, !strconcat(Dt, "8"), asm, "", []>;
1895 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
1896 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1897 opc, !strconcat(Dt, "16"), asm, "", []>;
1898 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
1899 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1900 opc, !strconcat(Dt, "32"), asm, "", []>;
1901 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
1902 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1903 opc, "f32", asm, "", []> {
1904 let Inst{10} = 1; // overwrite F = 1
1908 // Neon 3-register vector operations.
1910 // First with only element sizes of 8, 16 and 32 bits:
1911 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1912 InstrItinClass itinD16, InstrItinClass itinD32,
1913 InstrItinClass itinQ16, InstrItinClass itinQ32,
1914 string OpcodeStr, string Dt,
1915 SDNode OpNode, bit Commutable = 0> {
1916 // 64-bit vector types.
1917 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
1918 OpcodeStr, !strconcat(Dt, "8"),
1919 v8i8, v8i8, OpNode, Commutable>;
1920 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
1921 OpcodeStr, !strconcat(Dt, "16"),
1922 v4i16, v4i16, OpNode, Commutable>;
1923 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
1924 OpcodeStr, !strconcat(Dt, "32"),
1925 v2i32, v2i32, OpNode, Commutable>;
1927 // 128-bit vector types.
1928 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
1929 OpcodeStr, !strconcat(Dt, "8"),
1930 v16i8, v16i8, OpNode, Commutable>;
1931 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
1932 OpcodeStr, !strconcat(Dt, "16"),
1933 v8i16, v8i16, OpNode, Commutable>;
1934 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
1935 OpcodeStr, !strconcat(Dt, "32"),
1936 v4i32, v4i32, OpNode, Commutable>;
1939 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
1940 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1942 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
1944 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1945 v8i16, v4i16, ShOp>;
1946 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
1947 v4i32, v2i32, ShOp>;
1950 // ....then also with element size 64 bits:
1951 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1952 InstrItinClass itinD, InstrItinClass itinQ,
1953 string OpcodeStr, string Dt,
1954 SDNode OpNode, bit Commutable = 0>
1955 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
1956 OpcodeStr, Dt, OpNode, Commutable> {
1957 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
1958 OpcodeStr, !strconcat(Dt, "64"),
1959 v1i64, v1i64, OpNode, Commutable>;
1960 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
1961 OpcodeStr, !strconcat(Dt, "64"),
1962 v2i64, v2i64, OpNode, Commutable>;
1966 // Neon Narrowing 2-register vector operations,
1967 // source operand element sizes of 16, 32 and 64 bits:
1968 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1969 bits<5> op11_7, bit op6, bit op4,
1970 InstrItinClass itin, string OpcodeStr, string Dt,
1972 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
1973 itin, OpcodeStr, !strconcat(Dt, "16"),
1974 v8i8, v8i16, OpNode>;
1975 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
1976 itin, OpcodeStr, !strconcat(Dt, "32"),
1977 v4i16, v4i32, OpNode>;
1978 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
1979 itin, OpcodeStr, !strconcat(Dt, "64"),
1980 v2i32, v2i64, OpNode>;
1983 // Neon Narrowing 2-register vector intrinsics,
1984 // source operand element sizes of 16, 32 and 64 bits:
1985 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1986 bits<5> op11_7, bit op6, bit op4,
1987 InstrItinClass itin, string OpcodeStr, string Dt,
1989 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
1990 itin, OpcodeStr, !strconcat(Dt, "16"),
1991 v8i8, v8i16, IntOp>;
1992 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
1993 itin, OpcodeStr, !strconcat(Dt, "32"),
1994 v4i16, v4i32, IntOp>;
1995 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
1996 itin, OpcodeStr, !strconcat(Dt, "64"),
1997 v2i32, v2i64, IntOp>;
2001 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
2002 // source operand element sizes of 16, 32 and 64 bits:
2003 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
2004 string OpcodeStr, string Dt, SDNode OpNode> {
2005 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2006 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
2007 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2008 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2009 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2010 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2014 // Neon 3-register vector intrinsics.
2016 // First with only element sizes of 16 and 32 bits:
2017 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2018 InstrItinClass itinD16, InstrItinClass itinD32,
2019 InstrItinClass itinQ16, InstrItinClass itinQ32,
2020 string OpcodeStr, string Dt,
2021 Intrinsic IntOp, bit Commutable = 0> {
2022 // 64-bit vector types.
2023 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
2024 OpcodeStr, !strconcat(Dt, "16"),
2025 v4i16, v4i16, IntOp, Commutable>;
2026 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
2027 OpcodeStr, !strconcat(Dt, "32"),
2028 v2i32, v2i32, IntOp, Commutable>;
2030 // 128-bit vector types.
2031 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2032 OpcodeStr, !strconcat(Dt, "16"),
2033 v8i16, v8i16, IntOp, Commutable>;
2034 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2035 OpcodeStr, !strconcat(Dt, "32"),
2036 v4i32, v4i32, IntOp, Commutable>;
2038 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2039 InstrItinClass itinD16, InstrItinClass itinD32,
2040 InstrItinClass itinQ16, InstrItinClass itinQ32,
2041 string OpcodeStr, string Dt,
2043 // 64-bit vector types.
2044 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
2045 OpcodeStr, !strconcat(Dt, "16"),
2046 v4i16, v4i16, IntOp>;
2047 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
2048 OpcodeStr, !strconcat(Dt, "32"),
2049 v2i32, v2i32, IntOp>;
2051 // 128-bit vector types.
2052 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2053 OpcodeStr, !strconcat(Dt, "16"),
2054 v8i16, v8i16, IntOp>;
2055 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2056 OpcodeStr, !strconcat(Dt, "32"),
2057 v4i32, v4i32, IntOp>;
2060 multiclass N3VIntSL_HS<bits<4> op11_8,
2061 InstrItinClass itinD16, InstrItinClass itinD32,
2062 InstrItinClass itinQ16, InstrItinClass itinQ32,
2063 string OpcodeStr, string Dt, Intrinsic IntOp> {
2064 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
2065 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
2066 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
2067 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
2068 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
2069 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
2070 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
2071 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
2074 // ....then also with element size of 8 bits:
2075 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2076 InstrItinClass itinD16, InstrItinClass itinD32,
2077 InstrItinClass itinQ16, InstrItinClass itinQ32,
2078 string OpcodeStr, string Dt,
2079 Intrinsic IntOp, bit Commutable = 0>
2080 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2081 OpcodeStr, Dt, IntOp, Commutable> {
2082 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
2083 OpcodeStr, !strconcat(Dt, "8"),
2084 v8i8, v8i8, IntOp, Commutable>;
2085 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2086 OpcodeStr, !strconcat(Dt, "8"),
2087 v16i8, v16i8, IntOp, Commutable>;
2089 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2090 InstrItinClass itinD16, InstrItinClass itinD32,
2091 InstrItinClass itinQ16, InstrItinClass itinQ32,
2092 string OpcodeStr, string Dt,
2094 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2095 OpcodeStr, Dt, IntOp> {
2096 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
2097 OpcodeStr, !strconcat(Dt, "8"),
2099 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2100 OpcodeStr, !strconcat(Dt, "8"),
2101 v16i8, v16i8, IntOp>;
2105 // ....then also with element size of 64 bits:
2106 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2107 InstrItinClass itinD16, InstrItinClass itinD32,
2108 InstrItinClass itinQ16, InstrItinClass itinQ32,
2109 string OpcodeStr, string Dt,
2110 Intrinsic IntOp, bit Commutable = 0>
2111 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2112 OpcodeStr, Dt, IntOp, Commutable> {
2113 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
2114 OpcodeStr, !strconcat(Dt, "64"),
2115 v1i64, v1i64, IntOp, Commutable>;
2116 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2117 OpcodeStr, !strconcat(Dt, "64"),
2118 v2i64, v2i64, IntOp, Commutable>;
2120 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2121 InstrItinClass itinD16, InstrItinClass itinD32,
2122 InstrItinClass itinQ16, InstrItinClass itinQ32,
2123 string OpcodeStr, string Dt,
2125 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2126 OpcodeStr, Dt, IntOp> {
2127 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
2128 OpcodeStr, !strconcat(Dt, "64"),
2129 v1i64, v1i64, IntOp>;
2130 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2131 OpcodeStr, !strconcat(Dt, "64"),
2132 v2i64, v2i64, IntOp>;
2135 // Neon Narrowing 3-register vector intrinsics,
2136 // source operand element sizes of 16, 32 and 64 bits:
2137 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2138 string OpcodeStr, string Dt,
2139 Intrinsic IntOp, bit Commutable = 0> {
2140 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
2141 OpcodeStr, !strconcat(Dt, "16"),
2142 v8i8, v8i16, IntOp, Commutable>;
2143 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
2144 OpcodeStr, !strconcat(Dt, "32"),
2145 v4i16, v4i32, IntOp, Commutable>;
2146 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
2147 OpcodeStr, !strconcat(Dt, "64"),
2148 v2i32, v2i64, IntOp, Commutable>;
2152 // Neon Long 3-register vector operations.
2154 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2155 InstrItinClass itin16, InstrItinClass itin32,
2156 string OpcodeStr, string Dt,
2157 SDNode OpNode, bit Commutable = 0> {
2158 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
2159 OpcodeStr, !strconcat(Dt, "8"),
2160 v8i16, v8i8, OpNode, Commutable>;
2161 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
2162 OpcodeStr, !strconcat(Dt, "16"),
2163 v4i32, v4i16, OpNode, Commutable>;
2164 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
2165 OpcodeStr, !strconcat(Dt, "32"),
2166 v2i64, v2i32, OpNode, Commutable>;
2169 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
2170 InstrItinClass itin, string OpcodeStr, string Dt,
2172 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
2173 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2174 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
2175 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2178 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2179 InstrItinClass itin16, InstrItinClass itin32,
2180 string OpcodeStr, string Dt,
2181 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2182 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
2183 OpcodeStr, !strconcat(Dt, "8"),
2184 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2185 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
2186 OpcodeStr, !strconcat(Dt, "16"),
2187 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2188 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
2189 OpcodeStr, !strconcat(Dt, "32"),
2190 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2193 // Neon Long 3-register vector intrinsics.
2195 // First with only element sizes of 16 and 32 bits:
2196 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2197 InstrItinClass itin16, InstrItinClass itin32,
2198 string OpcodeStr, string Dt,
2199 Intrinsic IntOp, bit Commutable = 0> {
2200 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
2201 OpcodeStr, !strconcat(Dt, "16"),
2202 v4i32, v4i16, IntOp, Commutable>;
2203 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
2204 OpcodeStr, !strconcat(Dt, "32"),
2205 v2i64, v2i32, IntOp, Commutable>;
2208 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
2209 InstrItinClass itin, string OpcodeStr, string Dt,
2211 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
2212 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2213 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
2214 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2217 // ....then also with element size of 8 bits:
2218 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2219 InstrItinClass itin16, InstrItinClass itin32,
2220 string OpcodeStr, string Dt,
2221 Intrinsic IntOp, bit Commutable = 0>
2222 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
2223 IntOp, Commutable> {
2224 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
2225 OpcodeStr, !strconcat(Dt, "8"),
2226 v8i16, v8i8, IntOp, Commutable>;
2229 // ....with explicit extend (VABDL).
2230 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2231 InstrItinClass itin, string OpcodeStr, string Dt,
2232 Intrinsic IntOp, SDNode ExtOp, bit Commutable = 0> {
2233 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
2234 OpcodeStr, !strconcat(Dt, "8"),
2235 v8i16, v8i8, IntOp, ExtOp, Commutable>;
2236 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
2237 OpcodeStr, !strconcat(Dt, "16"),
2238 v4i32, v4i16, IntOp, ExtOp, Commutable>;
2239 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
2240 OpcodeStr, !strconcat(Dt, "32"),
2241 v2i64, v2i32, IntOp, ExtOp, Commutable>;
2245 // Neon Wide 3-register vector intrinsics,
2246 // source operand element sizes of 8, 16 and 32 bits:
2247 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2248 string OpcodeStr, string Dt,
2249 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2250 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
2251 OpcodeStr, !strconcat(Dt, "8"),
2252 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2253 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
2254 OpcodeStr, !strconcat(Dt, "16"),
2255 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2256 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
2257 OpcodeStr, !strconcat(Dt, "32"),
2258 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2262 // Neon Multiply-Op vector operations,
2263 // element sizes of 8, 16 and 32 bits:
2264 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2265 InstrItinClass itinD16, InstrItinClass itinD32,
2266 InstrItinClass itinQ16, InstrItinClass itinQ32,
2267 string OpcodeStr, string Dt, SDNode OpNode> {
2268 // 64-bit vector types.
2269 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
2270 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
2271 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
2272 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
2273 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
2274 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
2276 // 128-bit vector types.
2277 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
2278 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
2279 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
2280 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
2281 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
2282 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
2285 multiclass N3VMulOpSL_HS<bits<4> op11_8,
2286 InstrItinClass itinD16, InstrItinClass itinD32,
2287 InstrItinClass itinQ16, InstrItinClass itinQ32,
2288 string OpcodeStr, string Dt, SDNode ShOp> {
2289 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
2290 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
2291 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
2292 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
2293 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
2294 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
2296 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
2297 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
2301 // Neon Intrinsic-Op vector operations,
2302 // element sizes of 8, 16 and 32 bits:
2303 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2304 InstrItinClass itinD, InstrItinClass itinQ,
2305 string OpcodeStr, string Dt, Intrinsic IntOp,
2307 // 64-bit vector types.
2308 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
2309 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
2310 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
2311 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
2312 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
2313 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
2315 // 128-bit vector types.
2316 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
2317 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
2318 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
2319 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
2320 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
2321 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
2324 // Neon 3-argument intrinsics,
2325 // element sizes of 8, 16 and 32 bits:
2326 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2327 InstrItinClass itinD, InstrItinClass itinQ,
2328 string OpcodeStr, string Dt, Intrinsic IntOp> {
2329 // 64-bit vector types.
2330 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
2331 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2332 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
2333 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
2334 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
2335 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
2337 // 128-bit vector types.
2338 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
2339 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
2340 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
2341 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
2342 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
2343 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
2347 // Neon Long Multiply-Op vector operations,
2348 // element sizes of 8, 16 and 32 bits:
2349 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2350 InstrItinClass itin16, InstrItinClass itin32,
2351 string OpcodeStr, string Dt, SDNode MulOp,
2353 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
2354 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
2355 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
2356 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
2357 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
2358 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
2361 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
2362 string Dt, SDNode MulOp, SDNode OpNode> {
2363 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
2364 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
2365 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
2366 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
2370 // Neon Long 3-argument intrinsics.
2372 // First with only element sizes of 16 and 32 bits:
2373 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2374 InstrItinClass itin16, InstrItinClass itin32,
2375 string OpcodeStr, string Dt, Intrinsic IntOp> {
2376 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
2377 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2378 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
2379 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2382 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
2383 string OpcodeStr, string Dt, Intrinsic IntOp> {
2384 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
2385 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
2386 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
2387 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2390 // ....then also with element size of 8 bits:
2391 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2392 InstrItinClass itin16, InstrItinClass itin32,
2393 string OpcodeStr, string Dt, Intrinsic IntOp>
2394 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
2395 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
2396 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
2399 // ....with explicit extend (VABAL).
2400 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2401 InstrItinClass itin, string OpcodeStr, string Dt,
2402 Intrinsic IntOp, SDNode ExtOp, SDNode OpNode> {
2403 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
2404 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
2405 IntOp, ExtOp, OpNode>;
2406 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
2407 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
2408 IntOp, ExtOp, OpNode>;
2409 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
2410 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
2411 IntOp, ExtOp, OpNode>;
2415 // Neon 2-register vector intrinsics,
2416 // element sizes of 8, 16 and 32 bits:
2417 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2418 bits<5> op11_7, bit op4,
2419 InstrItinClass itinD, InstrItinClass itinQ,
2420 string OpcodeStr, string Dt, Intrinsic IntOp> {
2421 // 64-bit vector types.
2422 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2423 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2424 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2425 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
2426 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2427 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
2429 // 128-bit vector types.
2430 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2431 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
2432 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2433 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
2434 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2435 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
2439 // Neon Pairwise long 2-register intrinsics,
2440 // element sizes of 8, 16 and 32 bits:
2441 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2442 bits<5> op11_7, bit op4,
2443 string OpcodeStr, string Dt, Intrinsic IntOp> {
2444 // 64-bit vector types.
2445 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2446 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
2447 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2448 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
2449 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2450 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
2452 // 128-bit vector types.
2453 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2454 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
2455 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2456 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
2457 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2458 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
2462 // Neon Pairwise long 2-register accumulate intrinsics,
2463 // element sizes of 8, 16 and 32 bits:
2464 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2465 bits<5> op11_7, bit op4,
2466 string OpcodeStr, string Dt, Intrinsic IntOp> {
2467 // 64-bit vector types.
2468 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2469 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
2470 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2471 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
2472 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2473 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
2475 // 128-bit vector types.
2476 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2477 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
2478 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2479 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
2480 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2481 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
2485 // Neon 2-register vector shift by immediate,
2486 // with f of either N2RegVShLFrm or N2RegVShRFrm
2487 // element sizes of 8, 16, 32 and 64 bits:
2488 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2489 InstrItinClass itin, string OpcodeStr, string Dt,
2490 SDNode OpNode, Format f> {
2491 // 64-bit vector types.
2492 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2493 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
2494 let Inst{21-19} = 0b001; // imm6 = 001xxx
2496 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2497 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
2498 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2500 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2501 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
2502 let Inst{21} = 0b1; // imm6 = 1xxxxx
2504 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, f, itin,
2505 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
2508 // 128-bit vector types.
2509 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
2510 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
2511 let Inst{21-19} = 0b001; // imm6 = 001xxx
2513 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
2514 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
2515 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2517 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
2518 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
2519 let Inst{21} = 0b1; // imm6 = 1xxxxx
2521 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, f, itin,
2522 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
2526 // Neon Shift-Accumulate vector operations,
2527 // element sizes of 8, 16, 32 and 64 bits:
2528 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2529 string OpcodeStr, string Dt, SDNode ShOp> {
2530 // 64-bit vector types.
2531 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4,
2532 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
2533 let Inst{21-19} = 0b001; // imm6 = 001xxx
2535 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4,
2536 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
2537 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2539 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4,
2540 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
2541 let Inst{21} = 0b1; // imm6 = 1xxxxx
2543 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4,
2544 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
2547 // 128-bit vector types.
2548 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4,
2549 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
2550 let Inst{21-19} = 0b001; // imm6 = 001xxx
2552 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4,
2553 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
2554 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2556 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4,
2557 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
2558 let Inst{21} = 0b1; // imm6 = 1xxxxx
2560 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4,
2561 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
2566 // Neon Shift-Insert vector operations,
2567 // with f of either N2RegVShLFrm or N2RegVShRFrm
2568 // element sizes of 8, 16, 32 and 64 bits:
2569 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2570 string OpcodeStr, SDNode ShOp,
2572 // 64-bit vector types.
2573 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4,
2574 f, OpcodeStr, "8", v8i8, ShOp> {
2575 let Inst{21-19} = 0b001; // imm6 = 001xxx
2577 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4,
2578 f, OpcodeStr, "16", v4i16, ShOp> {
2579 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2581 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4,
2582 f, OpcodeStr, "32", v2i32, ShOp> {
2583 let Inst{21} = 0b1; // imm6 = 1xxxxx
2585 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4,
2586 f, OpcodeStr, "64", v1i64, ShOp>;
2589 // 128-bit vector types.
2590 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4,
2591 f, OpcodeStr, "8", v16i8, ShOp> {
2592 let Inst{21-19} = 0b001; // imm6 = 001xxx
2594 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4,
2595 f, OpcodeStr, "16", v8i16, ShOp> {
2596 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2598 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4,
2599 f, OpcodeStr, "32", v4i32, ShOp> {
2600 let Inst{21} = 0b1; // imm6 = 1xxxxx
2602 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4,
2603 f, OpcodeStr, "64", v2i64, ShOp>;
2607 // Neon Shift Long operations,
2608 // element sizes of 8, 16, 32 bits:
2609 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
2610 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
2611 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
2612 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
2613 let Inst{21-19} = 0b001; // imm6 = 001xxx
2615 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
2616 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
2617 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2619 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
2620 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
2621 let Inst{21} = 0b1; // imm6 = 1xxxxx
2625 // Neon Shift Narrow operations,
2626 // element sizes of 16, 32, 64 bits:
2627 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
2628 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
2630 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
2631 OpcodeStr, !strconcat(Dt, "16"), v8i8, v8i16, OpNode> {
2632 let Inst{21-19} = 0b001; // imm6 = 001xxx
2634 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
2635 OpcodeStr, !strconcat(Dt, "32"), v4i16, v4i32, OpNode> {
2636 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2638 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
2639 OpcodeStr, !strconcat(Dt, "64"), v2i32, v2i64, OpNode> {
2640 let Inst{21} = 0b1; // imm6 = 1xxxxx
2644 //===----------------------------------------------------------------------===//
2645 // Instruction Definitions.
2646 //===----------------------------------------------------------------------===//
2648 // Vector Add Operations.
2650 // VADD : Vector Add (integer and floating-point)
2651 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
2653 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
2654 v2f32, v2f32, fadd, 1>;
2655 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
2656 v4f32, v4f32, fadd, 1>;
2657 // VADDL : Vector Add Long (Q = D + D)
2658 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
2659 "vaddl", "s", add, sext, 1>;
2660 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
2661 "vaddl", "u", add, zext, 1>;
2662 // VADDW : Vector Add Wide (Q = Q + D)
2663 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
2664 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
2665 // VHADD : Vector Halving Add
2666 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
2667 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2668 "vhadd", "s", int_arm_neon_vhadds, 1>;
2669 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
2670 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2671 "vhadd", "u", int_arm_neon_vhaddu, 1>;
2672 // VRHADD : Vector Rounding Halving Add
2673 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
2674 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2675 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
2676 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
2677 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2678 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
2679 // VQADD : Vector Saturating Add
2680 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
2681 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2682 "vqadd", "s", int_arm_neon_vqadds, 1>;
2683 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
2684 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2685 "vqadd", "u", int_arm_neon_vqaddu, 1>;
2686 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
2687 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
2688 int_arm_neon_vaddhn, 1>;
2689 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
2690 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
2691 int_arm_neon_vraddhn, 1>;
2693 // Vector Multiply Operations.
2695 // VMUL : Vector Multiply (integer, polynomial and floating-point)
2696 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
2697 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
2698 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
2699 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
2700 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
2701 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
2702 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
2703 v2f32, v2f32, fmul, 1>;
2704 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
2705 v4f32, v4f32, fmul, 1>;
2706 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
2707 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
2708 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
2711 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
2712 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
2713 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
2714 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2715 (DSubReg_i16_reg imm:$lane))),
2716 (SubReg_i16_lane imm:$lane)))>;
2717 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
2718 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
2719 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
2720 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2721 (DSubReg_i32_reg imm:$lane))),
2722 (SubReg_i32_lane imm:$lane)))>;
2723 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
2724 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
2725 (v4f32 (VMULslfq (v4f32 QPR:$src1),
2726 (v2f32 (EXTRACT_SUBREG QPR:$src2,
2727 (DSubReg_i32_reg imm:$lane))),
2728 (SubReg_i32_lane imm:$lane)))>;
2730 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
2731 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
2732 IIC_VMULi16Q, IIC_VMULi32Q,
2733 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
2734 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
2735 IIC_VMULi16Q, IIC_VMULi32Q,
2736 "vqdmulh", "s", int_arm_neon_vqdmulh>;
2737 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
2738 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
2740 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
2741 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2742 (DSubReg_i16_reg imm:$lane))),
2743 (SubReg_i16_lane imm:$lane)))>;
2744 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
2745 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
2747 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
2748 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2749 (DSubReg_i32_reg imm:$lane))),
2750 (SubReg_i32_lane imm:$lane)))>;
2752 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
2753 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
2754 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
2755 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
2756 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
2757 IIC_VMULi16Q, IIC_VMULi32Q,
2758 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
2759 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
2760 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
2762 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
2763 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2764 (DSubReg_i16_reg imm:$lane))),
2765 (SubReg_i16_lane imm:$lane)))>;
2766 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
2767 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
2769 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
2770 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2771 (DSubReg_i32_reg imm:$lane))),
2772 (SubReg_i32_lane imm:$lane)))>;
2774 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
2775 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
2776 "vmull", "s", NEONvmulls, 1>;
2777 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
2778 "vmull", "u", NEONvmullu, 1>;
2779 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
2780 v8i16, v8i8, int_arm_neon_vmullp, 1>;
2781 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
2782 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
2784 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
2785 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
2786 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
2787 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
2788 "vqdmull", "s", int_arm_neon_vqdmull>;
2790 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
2792 // VMLA : Vector Multiply Accumulate (integer and floating-point)
2793 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
2794 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
2795 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
2797 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
2799 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
2800 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
2801 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
2803 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
2804 v4f32, v2f32, fmul, fadd>;
2806 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
2807 (mul (v8i16 QPR:$src2),
2808 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
2809 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
2810 (v4i16 (EXTRACT_SUBREG QPR:$src3,
2811 (DSubReg_i16_reg imm:$lane))),
2812 (SubReg_i16_lane imm:$lane)))>;
2814 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
2815 (mul (v4i32 QPR:$src2),
2816 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
2817 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
2818 (v2i32 (EXTRACT_SUBREG QPR:$src3,
2819 (DSubReg_i32_reg imm:$lane))),
2820 (SubReg_i32_lane imm:$lane)))>;
2822 def : Pat<(v4f32 (fadd (v4f32 QPR:$src1),
2823 (fmul (v4f32 QPR:$src2),
2824 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
2825 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
2827 (v2f32 (EXTRACT_SUBREG QPR:$src3,
2828 (DSubReg_i32_reg imm:$lane))),
2829 (SubReg_i32_lane imm:$lane)))>;
2831 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
2832 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
2833 "vmlal", "s", NEONvmulls, add>;
2834 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
2835 "vmlal", "u", NEONvmullu, add>;
2837 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
2838 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
2840 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
2841 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
2842 "vqdmlal", "s", int_arm_neon_vqdmlal>;
2843 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
2845 // VMLS : Vector Multiply Subtract (integer and floating-point)
2846 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
2847 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
2848 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
2850 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
2852 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
2853 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
2854 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
2856 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
2857 v4f32, v2f32, fmul, fsub>;
2859 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
2860 (mul (v8i16 QPR:$src2),
2861 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
2862 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
2863 (v4i16 (EXTRACT_SUBREG QPR:$src3,
2864 (DSubReg_i16_reg imm:$lane))),
2865 (SubReg_i16_lane imm:$lane)))>;
2867 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
2868 (mul (v4i32 QPR:$src2),
2869 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
2870 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
2871 (v2i32 (EXTRACT_SUBREG QPR:$src3,
2872 (DSubReg_i32_reg imm:$lane))),
2873 (SubReg_i32_lane imm:$lane)))>;
2875 def : Pat<(v4f32 (fsub (v4f32 QPR:$src1),
2876 (fmul (v4f32 QPR:$src2),
2877 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
2878 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
2879 (v2f32 (EXTRACT_SUBREG QPR:$src3,
2880 (DSubReg_i32_reg imm:$lane))),
2881 (SubReg_i32_lane imm:$lane)))>;
2883 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
2884 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
2885 "vmlsl", "s", NEONvmulls, sub>;
2886 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
2887 "vmlsl", "u", NEONvmullu, sub>;
2889 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
2890 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
2892 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
2893 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
2894 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
2895 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
2897 // Vector Subtract Operations.
2899 // VSUB : Vector Subtract (integer and floating-point)
2900 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
2901 "vsub", "i", sub, 0>;
2902 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
2903 v2f32, v2f32, fsub, 0>;
2904 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
2905 v4f32, v4f32, fsub, 0>;
2906 // VSUBL : Vector Subtract Long (Q = D - D)
2907 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
2908 "vsubl", "s", sub, sext, 0>;
2909 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
2910 "vsubl", "u", sub, zext, 0>;
2911 // VSUBW : Vector Subtract Wide (Q = Q - D)
2912 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
2913 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
2914 // VHSUB : Vector Halving Subtract
2915 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
2916 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2917 "vhsub", "s", int_arm_neon_vhsubs, 0>;
2918 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
2919 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2920 "vhsub", "u", int_arm_neon_vhsubu, 0>;
2921 // VQSUB : Vector Saturing Subtract
2922 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
2923 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2924 "vqsub", "s", int_arm_neon_vqsubs, 0>;
2925 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
2926 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2927 "vqsub", "u", int_arm_neon_vqsubu, 0>;
2928 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
2929 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
2930 int_arm_neon_vsubhn, 0>;
2931 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
2932 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
2933 int_arm_neon_vrsubhn, 0>;
2935 // Vector Comparisons.
2937 // VCEQ : Vector Compare Equal
2938 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2939 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
2940 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
2942 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
2944 // For disassembly only.
2945 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
2948 // VCGE : Vector Compare Greater Than or Equal
2949 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2950 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
2951 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2952 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
2953 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
2955 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
2957 // For disassembly only.
2958 // FIXME: This instruction's encoding MAY NOT BE correct.
2959 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
2961 // For disassembly only.
2962 // FIXME: This instruction's encoding MAY NOT BE correct.
2963 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
2966 // VCGT : Vector Compare Greater Than
2967 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2968 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
2969 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2970 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
2971 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
2973 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
2975 // For disassembly only.
2976 // FIXME: This instruction's encoding MAY NOT BE correct.
2977 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
2979 // For disassembly only.
2980 // FIXME: This instruction's encoding MAY NOT BE correct.
2981 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
2984 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
2985 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
2986 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
2987 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
2988 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
2989 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
2990 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
2991 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
2992 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
2993 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
2994 // VTST : Vector Test Bits
2995 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2996 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
2998 // Vector Bitwise Operations.
3000 def vnotd : PatFrag<(ops node:$in),
3001 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
3002 def vnotq : PatFrag<(ops node:$in),
3003 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
3006 // VAND : Vector Bitwise AND
3007 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
3008 v2i32, v2i32, and, 1>;
3009 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
3010 v4i32, v4i32, and, 1>;
3012 // VEOR : Vector Bitwise Exclusive OR
3013 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
3014 v2i32, v2i32, xor, 1>;
3015 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
3016 v4i32, v4i32, xor, 1>;
3018 // VORR : Vector Bitwise OR
3019 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
3020 v2i32, v2i32, or, 1>;
3021 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
3022 v4i32, v4i32, or, 1>;
3024 // VBIC : Vector Bitwise Bit Clear (AND NOT)
3025 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
3026 (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD,
3027 "vbic", "$dst, $src1, $src2", "",
3028 [(set DPR:$dst, (v2i32 (and DPR:$src1,
3029 (vnotd DPR:$src2))))]>;
3030 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
3031 (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINiQ,
3032 "vbic", "$dst, $src1, $src2", "",
3033 [(set QPR:$dst, (v4i32 (and QPR:$src1,
3034 (vnotq QPR:$src2))))]>;
3036 // VORN : Vector Bitwise OR NOT
3037 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
3038 (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD,
3039 "vorn", "$dst, $src1, $src2", "",
3040 [(set DPR:$dst, (v2i32 (or DPR:$src1,
3041 (vnotd DPR:$src2))))]>;
3042 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
3043 (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINiQ,
3044 "vorn", "$dst, $src1, $src2", "",
3045 [(set QPR:$dst, (v4i32 (or QPR:$src1,
3046 (vnotq QPR:$src2))))]>;
3048 // VMVN : Vector Bitwise NOT (Immediate)
3050 let isReMaterializable = 1 in {
3052 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$dst),
3053 (ins nModImm:$SIMM), IIC_VMOVImm,
3054 "vmvn", "i16", "$dst, $SIMM", "",
3055 [(set DPR:$dst, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
3056 let Inst{9} = SIMM{9};
3059 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$dst),
3060 (ins nModImm:$SIMM), IIC_VMOVImm,
3061 "vmvn", "i16", "$dst, $SIMM", "",
3062 [(set QPR:$dst, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
3063 let Inst{9} = SIMM{9};
3066 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$dst),
3067 (ins nModImm:$SIMM), IIC_VMOVImm,
3068 "vmvn", "i32", "$dst, $SIMM", "",
3069 [(set DPR:$dst, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
3070 let Inst{11-8} = SIMM{11-8};
3073 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$dst),
3074 (ins nModImm:$SIMM), IIC_VMOVImm,
3075 "vmvn", "i32", "$dst, $SIMM", "",
3076 [(set QPR:$dst, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
3077 let Inst{11-8} = SIMM{11-8};
3081 // VMVN : Vector Bitwise NOT
3082 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
3083 (outs DPR:$dst), (ins DPR:$src), IIC_VSUBiD,
3084 "vmvn", "$dst, $src", "",
3085 [(set DPR:$dst, (v2i32 (vnotd DPR:$src)))]>;
3086 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
3087 (outs QPR:$dst), (ins QPR:$src), IIC_VSUBiD,
3088 "vmvn", "$dst, $src", "",
3089 [(set QPR:$dst, (v4i32 (vnotq QPR:$src)))]>;
3090 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
3091 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
3093 // VBSL : Vector Bitwise Select
3094 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
3095 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3096 N3RegFrm, IIC_VCNTiD,
3097 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3099 (v2i32 (or (and DPR:$Vn, DPR:$src1),
3100 (and DPR:$Vm, (vnotd DPR:$src1)))))]>;
3101 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
3102 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3103 N3RegFrm, IIC_VCNTiQ,
3104 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3106 (v4i32 (or (and QPR:$Vn, QPR:$src1),
3107 (and QPR:$Vm, (vnotq QPR:$src1)))))]>;
3109 // VBIF : Vector Bitwise Insert if False
3110 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
3111 // FIXME: This instruction's encoding MAY NOT BE correct.
3112 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
3113 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3114 N3RegFrm, IIC_VBINiD,
3115 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3116 [/* For disassembly only; pattern left blank */]>;
3117 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
3118 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3119 N3RegFrm, IIC_VBINiQ,
3120 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3121 [/* For disassembly only; pattern left blank */]>;
3123 // VBIT : Vector Bitwise Insert if True
3124 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
3125 // FIXME: This instruction's encoding MAY NOT BE correct.
3126 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
3127 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3128 N3RegFrm, IIC_VBINiD,
3129 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3130 [/* For disassembly only; pattern left blank */]>;
3131 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
3132 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3133 N3RegFrm, IIC_VBINiQ,
3134 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3135 [/* For disassembly only; pattern left blank */]>;
3137 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
3138 // for equivalent operations with different register constraints; it just
3141 // Vector Absolute Differences.
3143 // VABD : Vector Absolute Difference
3144 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
3145 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3146 "vabd", "s", int_arm_neon_vabds, 1>;
3147 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
3148 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3149 "vabd", "u", int_arm_neon_vabdu, 1>;
3150 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
3151 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
3152 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
3153 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
3155 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
3156 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
3157 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
3158 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
3159 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
3161 // VABA : Vector Absolute Difference and Accumulate
3162 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3163 "vaba", "s", int_arm_neon_vabds, add>;
3164 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3165 "vaba", "u", int_arm_neon_vabdu, add>;
3167 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
3168 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
3169 "vabal", "s", int_arm_neon_vabds, zext, add>;
3170 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
3171 "vabal", "u", int_arm_neon_vabdu, zext, add>;
3173 // Vector Maximum and Minimum.
3175 // VMAX : Vector Maximum
3176 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
3177 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3178 "vmax", "s", int_arm_neon_vmaxs, 1>;
3179 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
3180 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3181 "vmax", "u", int_arm_neon_vmaxu, 1>;
3182 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
3184 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
3185 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
3187 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
3189 // VMIN : Vector Minimum
3190 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
3191 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3192 "vmin", "s", int_arm_neon_vmins, 1>;
3193 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
3194 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3195 "vmin", "u", int_arm_neon_vminu, 1>;
3196 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
3198 v2f32, v2f32, int_arm_neon_vmins, 1>;
3199 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
3201 v4f32, v4f32, int_arm_neon_vmins, 1>;
3203 // Vector Pairwise Operations.
3205 // VPADD : Vector Pairwise Add
3206 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3208 v8i8, v8i8, int_arm_neon_vpadd, 0>;
3209 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3211 v4i16, v4i16, int_arm_neon_vpadd, 0>;
3212 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3214 v2i32, v2i32, int_arm_neon_vpadd, 0>;
3215 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
3216 IIC_VPBIND, "vpadd", "f32",
3217 v2f32, v2f32, int_arm_neon_vpadd, 0>;
3219 // VPADDL : Vector Pairwise Add Long
3220 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
3221 int_arm_neon_vpaddls>;
3222 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
3223 int_arm_neon_vpaddlu>;
3225 // VPADAL : Vector Pairwise Add and Accumulate Long
3226 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
3227 int_arm_neon_vpadals>;
3228 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
3229 int_arm_neon_vpadalu>;
3231 // VPMAX : Vector Pairwise Maximum
3232 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3233 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
3234 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3235 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
3236 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3237 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
3238 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3239 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
3240 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3241 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
3242 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3243 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
3244 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
3245 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
3247 // VPMIN : Vector Pairwise Minimum
3248 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3249 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
3250 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3251 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
3252 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3253 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
3254 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3255 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
3256 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3257 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
3258 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3259 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
3260 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
3261 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
3263 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
3265 // VRECPE : Vector Reciprocal Estimate
3266 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
3267 IIC_VUNAD, "vrecpe", "u32",
3268 v2i32, v2i32, int_arm_neon_vrecpe>;
3269 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
3270 IIC_VUNAQ, "vrecpe", "u32",
3271 v4i32, v4i32, int_arm_neon_vrecpe>;
3272 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
3273 IIC_VUNAD, "vrecpe", "f32",
3274 v2f32, v2f32, int_arm_neon_vrecpe>;
3275 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
3276 IIC_VUNAQ, "vrecpe", "f32",
3277 v4f32, v4f32, int_arm_neon_vrecpe>;
3279 // VRECPS : Vector Reciprocal Step
3280 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
3281 IIC_VRECSD, "vrecps", "f32",
3282 v2f32, v2f32, int_arm_neon_vrecps, 1>;
3283 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
3284 IIC_VRECSQ, "vrecps", "f32",
3285 v4f32, v4f32, int_arm_neon_vrecps, 1>;
3287 // VRSQRTE : Vector Reciprocal Square Root Estimate
3288 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
3289 IIC_VUNAD, "vrsqrte", "u32",
3290 v2i32, v2i32, int_arm_neon_vrsqrte>;
3291 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
3292 IIC_VUNAQ, "vrsqrte", "u32",
3293 v4i32, v4i32, int_arm_neon_vrsqrte>;
3294 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
3295 IIC_VUNAD, "vrsqrte", "f32",
3296 v2f32, v2f32, int_arm_neon_vrsqrte>;
3297 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
3298 IIC_VUNAQ, "vrsqrte", "f32",
3299 v4f32, v4f32, int_arm_neon_vrsqrte>;
3301 // VRSQRTS : Vector Reciprocal Square Root Step
3302 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
3303 IIC_VRECSD, "vrsqrts", "f32",
3304 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
3305 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
3306 IIC_VRECSQ, "vrsqrts", "f32",
3307 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
3311 // VSHL : Vector Shift
3312 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
3313 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
3314 "vshl", "s", int_arm_neon_vshifts>;
3315 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
3316 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
3317 "vshl", "u", int_arm_neon_vshiftu>;
3318 // VSHL : Vector Shift Left (Immediate)
3319 defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl,
3321 // VSHR : Vector Shift Right (Immediate)
3322 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", NEONvshrs,
3324 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", NEONvshru,
3327 // VSHLL : Vector Shift Left Long
3328 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
3329 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
3331 // VSHLL : Vector Shift Left Long (with maximum shift count)
3332 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
3333 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
3334 ValueType OpTy, SDNode OpNode>
3335 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
3336 ResTy, OpTy, OpNode> {
3337 let Inst{21-16} = op21_16;
3339 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
3340 v8i16, v8i8, NEONvshlli>;
3341 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
3342 v4i32, v4i16, NEONvshlli>;
3343 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
3344 v2i64, v2i32, NEONvshlli>;
3346 // VSHRN : Vector Shift Right and Narrow
3347 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
3350 // VRSHL : Vector Rounding Shift
3351 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
3352 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3353 "vrshl", "s", int_arm_neon_vrshifts>;
3354 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
3355 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3356 "vrshl", "u", int_arm_neon_vrshiftu>;
3357 // VRSHR : Vector Rounding Shift Right
3358 defm VRSHRs : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs,
3360 defm VRSHRu : N2VSh_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", NEONvrshru,
3363 // VRSHRN : Vector Rounding Shift Right and Narrow
3364 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
3367 // VQSHL : Vector Saturating Shift
3368 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
3369 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3370 "vqshl", "s", int_arm_neon_vqshifts>;
3371 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
3372 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3373 "vqshl", "u", int_arm_neon_vqshiftu>;
3374 // VQSHL : Vector Saturating Shift Left (Immediate)
3375 defm VQSHLsi : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls,
3377 defm VQSHLui : N2VSh_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu,
3379 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
3380 defm VQSHLsu : N2VSh_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu,
3383 // VQSHRN : Vector Saturating Shift Right and Narrow
3384 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
3386 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
3389 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
3390 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
3393 // VQRSHL : Vector Saturating Rounding Shift
3394 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
3395 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3396 "vqrshl", "s", int_arm_neon_vqrshifts>;
3397 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
3398 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3399 "vqrshl", "u", int_arm_neon_vqrshiftu>;
3401 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
3402 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
3404 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
3407 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
3408 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
3411 // VSRA : Vector Shift Right and Accumulate
3412 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
3413 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
3414 // VRSRA : Vector Rounding Shift Right and Accumulate
3415 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
3416 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
3418 // VSLI : Vector Shift Left and Insert
3419 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli", NEONvsli, N2RegVShLFrm>;
3420 // VSRI : Vector Shift Right and Insert
3421 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri", NEONvsri, N2RegVShRFrm>;
3423 // Vector Absolute and Saturating Absolute.
3425 // VABS : Vector Absolute Value
3426 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
3427 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
3429 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
3430 IIC_VUNAD, "vabs", "f32",
3431 v2f32, v2f32, int_arm_neon_vabs>;
3432 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
3433 IIC_VUNAQ, "vabs", "f32",
3434 v4f32, v4f32, int_arm_neon_vabs>;
3436 // VQABS : Vector Saturating Absolute Value
3437 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
3438 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
3439 int_arm_neon_vqabs>;
3443 def vnegd : PatFrag<(ops node:$in),
3444 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
3445 def vnegq : PatFrag<(ops node:$in),
3446 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
3448 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
3449 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
3450 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
3451 [(set DPR:$dst, (Ty (vnegd DPR:$src)))]>;
3452 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
3453 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
3454 IIC_VSHLiQ, OpcodeStr, Dt, "$dst, $src", "",
3455 [(set QPR:$dst, (Ty (vnegq QPR:$src)))]>;
3457 // VNEG : Vector Negate (integer)
3458 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
3459 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
3460 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
3461 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
3462 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
3463 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
3465 // VNEG : Vector Negate (floating-point)
3466 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
3467 (outs DPR:$dst), (ins DPR:$src), IIC_VUNAD,
3468 "vneg", "f32", "$dst, $src", "",
3469 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
3470 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
3471 (outs QPR:$dst), (ins QPR:$src), IIC_VUNAQ,
3472 "vneg", "f32", "$dst, $src", "",
3473 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
3475 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
3476 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
3477 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
3478 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
3479 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
3480 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
3482 // VQNEG : Vector Saturating Negate
3483 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
3484 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
3485 int_arm_neon_vqneg>;
3487 // Vector Bit Counting Operations.
3489 // VCLS : Vector Count Leading Sign Bits
3490 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
3491 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
3493 // VCLZ : Vector Count Leading Zeros
3494 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
3495 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
3497 // VCNT : Vector Count One Bits
3498 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
3499 IIC_VCNTiD, "vcnt", "8",
3500 v8i8, v8i8, int_arm_neon_vcnt>;
3501 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
3502 IIC_VCNTiQ, "vcnt", "8",
3503 v16i8, v16i8, int_arm_neon_vcnt>;
3505 // Vector Swap -- for disassembly only.
3506 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
3507 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
3508 "vswp", "$dst, $src", "", []>;
3509 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
3510 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
3511 "vswp", "$dst, $src", "", []>;
3513 // Vector Move Operations.
3515 // VMOV : Vector Move (Register)
3517 let neverHasSideEffects = 1 in {
3518 def VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
3519 N3RegFrm, IIC_VMOV, "vmov", "$dst, $src", "", []>;
3520 def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
3521 N3RegFrm, IIC_VMOV, "vmov", "$dst, $src", "", []>;
3523 // Pseudo vector move instructions for QQ and QQQQ registers. This should
3524 // be expanded after register allocation is completed.
3525 def VMOVQQ : PseudoInst<(outs QQPR:$dst), (ins QQPR:$src),
3526 NoItinerary, "", []>;
3528 def VMOVQQQQ : PseudoInst<(outs QQQQPR:$dst), (ins QQQQPR:$src),
3529 NoItinerary, "", []>;
3530 } // neverHasSideEffects
3532 // VMOV : Vector Move (Immediate)
3534 let isReMaterializable = 1 in {
3535 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
3536 (ins nModImm:$SIMM), IIC_VMOVImm,
3537 "vmov", "i8", "$dst, $SIMM", "",
3538 [(set DPR:$dst, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
3539 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
3540 (ins nModImm:$SIMM), IIC_VMOVImm,
3541 "vmov", "i8", "$dst, $SIMM", "",
3542 [(set QPR:$dst, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
3544 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$dst),
3545 (ins nModImm:$SIMM), IIC_VMOVImm,
3546 "vmov", "i16", "$dst, $SIMM", "",
3547 [(set DPR:$dst, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
3548 let Inst{9} = SIMM{9};
3551 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$dst),
3552 (ins nModImm:$SIMM), IIC_VMOVImm,
3553 "vmov", "i16", "$dst, $SIMM", "",
3554 [(set QPR:$dst, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
3555 let Inst{9} = SIMM{9};
3558 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$dst),
3559 (ins nModImm:$SIMM), IIC_VMOVImm,
3560 "vmov", "i32", "$dst, $SIMM", "",
3561 [(set DPR:$dst, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
3562 let Inst{11-8} = SIMM{11-8};
3565 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$dst),
3566 (ins nModImm:$SIMM), IIC_VMOVImm,
3567 "vmov", "i32", "$dst, $SIMM", "",
3568 [(set QPR:$dst, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
3569 let Inst{11-8} = SIMM{11-8};
3572 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
3573 (ins nModImm:$SIMM), IIC_VMOVImm,
3574 "vmov", "i64", "$dst, $SIMM", "",
3575 [(set DPR:$dst, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
3576 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
3577 (ins nModImm:$SIMM), IIC_VMOVImm,
3578 "vmov", "i64", "$dst, $SIMM", "",
3579 [(set QPR:$dst, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
3580 } // isReMaterializable
3582 // VMOV : Vector Get Lane (move scalar to ARM core register)
3584 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
3585 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
3586 IIC_VMOVSI, "vmov", "s8", "$R, $V[$lane]",
3587 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
3589 let Inst{21} = lane{2};
3590 let Inst{6-5} = lane{1-0};
3592 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
3593 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
3594 IIC_VMOVSI, "vmov", "s16", "$R, $V[$lane]",
3595 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
3597 let Inst{21} = lane{1};
3598 let Inst{6} = lane{0};
3600 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
3601 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
3602 IIC_VMOVSI, "vmov", "u8", "$R, $V[$lane]",
3603 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
3605 let Inst{21} = lane{2};
3606 let Inst{6-5} = lane{1-0};
3608 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
3609 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
3610 IIC_VMOVSI, "vmov", "u16", "$R, $V[$lane]",
3611 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
3613 let Inst{21} = lane{1};
3614 let Inst{6} = lane{0};
3616 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
3617 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
3618 IIC_VMOVSI, "vmov", "32", "$R, $V[$lane]",
3619 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
3621 let Inst{21} = lane{0};
3623 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
3624 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
3625 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
3626 (DSubReg_i8_reg imm:$lane))),
3627 (SubReg_i8_lane imm:$lane))>;
3628 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
3629 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
3630 (DSubReg_i16_reg imm:$lane))),
3631 (SubReg_i16_lane imm:$lane))>;
3632 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
3633 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
3634 (DSubReg_i8_reg imm:$lane))),
3635 (SubReg_i8_lane imm:$lane))>;
3636 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
3637 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
3638 (DSubReg_i16_reg imm:$lane))),
3639 (SubReg_i16_lane imm:$lane))>;
3640 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
3641 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
3642 (DSubReg_i32_reg imm:$lane))),
3643 (SubReg_i32_lane imm:$lane))>;
3644 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
3645 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
3646 (SSubReg_f32_reg imm:$src2))>;
3647 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
3648 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
3649 (SSubReg_f32_reg imm:$src2))>;
3650 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
3651 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
3652 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
3653 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
3656 // VMOV : Vector Set Lane (move ARM core register to scalar)
3658 let Constraints = "$src1 = $V" in {
3659 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
3660 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
3661 IIC_VMOVISL, "vmov", "8", "$V[$lane], $R",
3662 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
3663 GPR:$R, imm:$lane))]> {
3664 let Inst{21} = lane{2};
3665 let Inst{6-5} = lane{1-0};
3667 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
3668 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
3669 IIC_VMOVISL, "vmov", "16", "$V[$lane], $R",
3670 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
3671 GPR:$R, imm:$lane))]> {
3672 let Inst{21} = lane{1};
3673 let Inst{6} = lane{0};
3675 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
3676 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
3677 IIC_VMOVISL, "vmov", "32", "$V[$lane], $R",
3678 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
3679 GPR:$R, imm:$lane))]> {
3680 let Inst{21} = lane{0};
3683 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
3684 (v16i8 (INSERT_SUBREG QPR:$src1,
3685 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
3686 (DSubReg_i8_reg imm:$lane))),
3687 GPR:$src2, (SubReg_i8_lane imm:$lane))),
3688 (DSubReg_i8_reg imm:$lane)))>;
3689 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
3690 (v8i16 (INSERT_SUBREG QPR:$src1,
3691 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
3692 (DSubReg_i16_reg imm:$lane))),
3693 GPR:$src2, (SubReg_i16_lane imm:$lane))),
3694 (DSubReg_i16_reg imm:$lane)))>;
3695 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
3696 (v4i32 (INSERT_SUBREG QPR:$src1,
3697 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
3698 (DSubReg_i32_reg imm:$lane))),
3699 GPR:$src2, (SubReg_i32_lane imm:$lane))),
3700 (DSubReg_i32_reg imm:$lane)))>;
3702 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
3703 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
3704 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
3705 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
3706 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
3707 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
3709 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
3710 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
3711 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
3712 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
3714 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
3715 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
3716 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
3717 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
3718 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
3719 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
3721 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
3722 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
3723 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
3724 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
3725 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
3726 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
3728 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
3729 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3730 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
3732 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
3733 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
3734 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
3736 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
3737 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3738 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
3741 // VDUP : Vector Duplicate (from ARM core register to all elements)
3743 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
3744 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
3745 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
3746 [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
3747 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
3748 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
3749 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
3750 [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
3752 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
3753 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
3754 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
3755 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
3756 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
3757 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
3759 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
3760 IIC_VMOVIS, "vdup", "32", "$dst, $src",
3761 [(set DPR:$dst, (v2f32 (NEONvdup
3762 (f32 (bitconvert GPR:$src)))))]>;
3763 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
3764 IIC_VMOVIS, "vdup", "32", "$dst, $src",
3765 [(set QPR:$dst, (v4f32 (NEONvdup
3766 (f32 (bitconvert GPR:$src)))))]>;
3768 // VDUP : Vector Duplicate Lane (from scalar to all elements)
3770 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
3772 : NVDupLane<op19_16, 0, (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3773 IIC_VMOVD, OpcodeStr, Dt, "$dst, $src[$lane]",
3774 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
3776 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
3777 ValueType ResTy, ValueType OpTy>
3778 : NVDupLane<op19_16, 1, (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3779 IIC_VMOVQ, OpcodeStr, Dt, "$dst, $src[$lane]",
3780 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src),
3783 // Inst{19-16} is partially specified depending on the element size.
3785 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8> {
3786 let Inst{19-17} = lane{2-0};
3788 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16> {
3789 let Inst{19-18} = lane{1-0};
3791 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32> {
3792 let Inst{19} = lane{0};
3794 def VDUPLNfd : VDUPLND<{?,1,0,0}, "vdup", "32", v2f32> {
3795 let Inst{19} = lane{0};
3797 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8> {
3798 let Inst{19-17} = lane{2-0};
3800 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16> {
3801 let Inst{19-18} = lane{1-0};
3803 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32> {
3804 let Inst{19} = lane{0};
3806 def VDUPLNfq : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4f32, v2f32> {
3807 let Inst{19} = lane{0};
3810 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
3811 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
3812 (DSubReg_i8_reg imm:$lane))),
3813 (SubReg_i8_lane imm:$lane)))>;
3814 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
3815 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
3816 (DSubReg_i16_reg imm:$lane))),
3817 (SubReg_i16_lane imm:$lane)))>;
3818 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
3819 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
3820 (DSubReg_i32_reg imm:$lane))),
3821 (SubReg_i32_lane imm:$lane)))>;
3822 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
3823 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
3824 (DSubReg_i32_reg imm:$lane))),
3825 (SubReg_i32_lane imm:$lane)))>;
3827 def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
3828 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
3829 def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
3830 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
3832 // VMOVN : Vector Narrowing Move
3833 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
3834 "vmovn", "i", trunc>;
3835 // VQMOVN : Vector Saturating Narrowing Move
3836 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
3837 "vqmovn", "s", int_arm_neon_vqmovns>;
3838 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
3839 "vqmovn", "u", int_arm_neon_vqmovnu>;
3840 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
3841 "vqmovun", "s", int_arm_neon_vqmovnsu>;
3842 // VMOVL : Vector Lengthening Move
3843 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
3844 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
3846 // Vector Conversions.
3848 // VCVT : Vector Convert Between Floating-Point and Integers
3849 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3850 v2i32, v2f32, fp_to_sint>;
3851 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3852 v2i32, v2f32, fp_to_uint>;
3853 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3854 v2f32, v2i32, sint_to_fp>;
3855 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3856 v2f32, v2i32, uint_to_fp>;
3858 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3859 v4i32, v4f32, fp_to_sint>;
3860 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3861 v4i32, v4f32, fp_to_uint>;
3862 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3863 v4f32, v4i32, sint_to_fp>;
3864 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3865 v4f32, v4i32, uint_to_fp>;
3867 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
3868 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
3869 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
3870 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
3871 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
3872 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
3873 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
3874 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
3875 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
3877 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
3878 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
3879 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
3880 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
3881 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
3882 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
3883 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
3884 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
3888 // VREV64 : Vector Reverse elements within 64-bit doublewords
3890 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3891 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
3892 (ins DPR:$src), IIC_VMOVD,
3893 OpcodeStr, Dt, "$dst, $src", "",
3894 [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
3895 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3896 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
3897 (ins QPR:$src), IIC_VMOVQ,
3898 OpcodeStr, Dt, "$dst, $src", "",
3899 [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
3901 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
3902 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
3903 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
3904 def VREV64df : VREV64D<0b10, "vrev64", "32", v2f32>;
3906 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
3907 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
3908 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
3909 def VREV64qf : VREV64Q<0b10, "vrev64", "32", v4f32>;
3911 // VREV32 : Vector Reverse elements within 32-bit words
3913 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3914 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
3915 (ins DPR:$src), IIC_VMOVD,
3916 OpcodeStr, Dt, "$dst, $src", "",
3917 [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
3918 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3919 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
3920 (ins QPR:$src), IIC_VMOVQ,
3921 OpcodeStr, Dt, "$dst, $src", "",
3922 [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
3924 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
3925 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
3927 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
3928 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
3930 // VREV16 : Vector Reverse elements within 16-bit halfwords
3932 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3933 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
3934 (ins DPR:$src), IIC_VMOVD,
3935 OpcodeStr, Dt, "$dst, $src", "",
3936 [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
3937 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3938 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
3939 (ins QPR:$src), IIC_VMOVQ,
3940 OpcodeStr, Dt, "$dst, $src", "",
3941 [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
3943 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
3944 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
3946 // Other Vector Shuffles.
3948 // VEXT : Vector Extract
3950 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
3951 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$dst),
3952 (ins DPR:$lhs, DPR:$rhs, i32imm:$index), NVExtFrm,
3953 IIC_VEXTD, OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
3954 [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
3955 (Ty DPR:$rhs), imm:$index)))]> {
3957 let Inst{11-8} = index{3-0};
3960 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
3961 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$dst),
3962 (ins QPR:$lhs, QPR:$rhs, i32imm:$index), NVExtFrm,
3963 IIC_VEXTQ, OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
3964 [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
3965 (Ty QPR:$rhs), imm:$index)))]> {
3967 let Inst{11-8} = index{3-0};
3970 def VEXTd8 : VEXTd<"vext", "8", v8i8>;
3971 def VEXTd16 : VEXTd<"vext", "16", v4i16>;
3972 def VEXTd32 : VEXTd<"vext", "32", v2i32>;
3973 def VEXTdf : VEXTd<"vext", "32", v2f32>;
3975 def VEXTq8 : VEXTq<"vext", "8", v16i8>;
3976 def VEXTq16 : VEXTq<"vext", "16", v8i16>;
3977 def VEXTq32 : VEXTq<"vext", "32", v4i32>;
3978 def VEXTqf : VEXTq<"vext", "32", v4f32>;
3980 // VTRN : Vector Transpose
3982 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
3983 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
3984 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
3986 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
3987 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
3988 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
3990 // VUZP : Vector Unzip (Deinterleave)
3992 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
3993 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
3994 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
3996 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
3997 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
3998 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
4000 // VZIP : Vector Zip (Interleave)
4002 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
4003 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
4004 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
4006 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
4007 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
4008 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
4010 // Vector Table Lookup and Table Extension.
4012 // VTBL : Vector Table Lookup
4014 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
4015 (ins DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
4016 "vtbl", "8", "$Vd, \\{$Vn\\}, $Vm", "",
4017 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 DPR:$Vn, DPR:$Vm)))]>;
4018 let hasExtraSrcRegAllocReq = 1 in {
4020 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
4021 (ins DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTB2,
4022 "vtbl", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "", []>;
4024 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
4025 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm), NVTBLFrm, IIC_VTB3,
4026 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm", "", []>;
4028 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
4029 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm),
4031 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm", "", []>;
4032 } // hasExtraSrcRegAllocReq = 1
4035 : PseudoNeonI<(outs DPR:$dst), (ins QPR:$tbl, DPR:$src), IIC_VTB2, "", []>;
4037 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
4039 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
4041 // VTBX : Vector Table Extension
4043 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
4044 (ins DPR:$orig, DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
4045 "vtbx", "8", "$Vd, \\{$Vn\\}, $Vm", "$orig = $Vd",
4046 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
4047 DPR:$orig, DPR:$Vn, DPR:$Vm)))]>;
4048 let hasExtraSrcRegAllocReq = 1 in {
4050 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
4051 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
4052 "vtbx", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "$orig = $Vd", []>;
4054 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
4055 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm),
4056 NVTBLFrm, IIC_VTBX3,
4057 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm",
4060 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd), (ins DPR:$orig, DPR:$Vn,
4061 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
4062 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm",
4064 } // hasExtraSrcRegAllocReq = 1
4067 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QPR:$tbl, DPR:$src),
4068 IIC_VTBX2, "$orig = $dst", []>;
4070 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4071 IIC_VTBX3, "$orig = $dst", []>;
4073 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4074 IIC_VTBX4, "$orig = $dst", []>;
4076 //===----------------------------------------------------------------------===//
4077 // NEON instructions for single-precision FP math
4078 //===----------------------------------------------------------------------===//
4080 class N2VSPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
4081 : NEONFPPat<(ResTy (OpNode SPR:$a)),
4082 (EXTRACT_SUBREG (OpTy (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)),
4086 class N3VSPat<SDNode OpNode, NeonI Inst>
4087 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
4088 (EXTRACT_SUBREG (v2f32
4089 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
4091 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
4095 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
4096 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
4097 (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
4099 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
4101 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
4105 // These need separate instructions because they must use DPR_VFP2 register
4106 // class which have SPR sub-registers.
4108 // Vector Add Operations used for single-precision FP
4109 let neverHasSideEffects = 1 in
4110 def VADDfd_sfp : N3VS<0,0,0b00,0b1101,0, "vadd", "f32", v2f32, v2f32, fadd, 1>;
4111 def : N3VSPat<fadd, VADDfd_sfp>;
4113 // Vector Sub Operations used for single-precision FP
4114 let neverHasSideEffects = 1 in
4115 def VSUBfd_sfp : N3VS<0,0,0b10,0b1101,0, "vsub", "f32", v2f32, v2f32, fsub, 0>;
4116 def : N3VSPat<fsub, VSUBfd_sfp>;
4118 // Vector Multiply Operations used for single-precision FP
4119 let neverHasSideEffects = 1 in
4120 def VMULfd_sfp : N3VS<1,0,0b00,0b1101,1, "vmul", "f32", v2f32, v2f32, fmul, 1>;
4121 def : N3VSPat<fmul, VMULfd_sfp>;
4123 // Vector Multiply-Accumulate/Subtract used for single-precision FP
4124 // vml[as].f32 can cause 4-8 cycle stalls in following ASIMD instructions, so
4125 // we want to avoid them for now. e.g., alternating vmla/vadd instructions.
4127 //let neverHasSideEffects = 1 in
4128 //def VMLAfd_sfp : N3VSMulOp<0,0,0b00,0b1101,1, IIC_VMACD, "vmla", "f32",
4129 // v2f32, fmul, fadd>;
4130 //def : N3VSMulOpPat<fmul, fadd, VMLAfd_sfp>;
4132 //let neverHasSideEffects = 1 in
4133 //def VMLSfd_sfp : N3VSMulOp<0,0,0b10,0b1101,1, IIC_VMACD, "vmls", "f32",
4134 // v2f32, fmul, fsub>;
4135 //def : N3VSMulOpPat<fmul, fsub, VMLSfd_sfp>;
4137 // Vector Absolute used for single-precision FP
4138 let neverHasSideEffects = 1 in
4139 def VABSfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01110, 0, 0,
4140 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
4141 "vabs", "f32", "$dst, $src", "", []>;
4142 def : N2VSPat<fabs, f32, v2f32, VABSfd_sfp>;
4144 // Vector Negate used for single-precision FP
4145 let neverHasSideEffects = 1 in
4146 def VNEGfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
4147 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
4148 "vneg", "f32", "$dst, $src", "", []>;
4149 def : N2VSPat<fneg, f32, v2f32, VNEGfd_sfp>;
4151 // Vector Maximum used for single-precision FP
4152 let neverHasSideEffects = 1 in
4153 def VMAXfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
4154 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm, IIC_VBIND,
4155 "vmax", "f32", "$dst, $src1, $src2", "", []>;
4156 def : N3VSPat<NEONfmax, VMAXfd_sfp>;
4158 // Vector Minimum used for single-precision FP
4159 let neverHasSideEffects = 1 in
4160 def VMINfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
4161 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm, IIC_VBIND,
4162 "vmin", "f32", "$dst, $src1, $src2", "", []>;
4163 def : N3VSPat<NEONfmin, VMINfd_sfp>;
4165 // Vector Convert between single-precision FP and integer
4166 let neverHasSideEffects = 1 in
4167 def VCVTf2sd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4168 v2i32, v2f32, fp_to_sint>;
4169 def : N2VSPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
4171 let neverHasSideEffects = 1 in
4172 def VCVTf2ud_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4173 v2i32, v2f32, fp_to_uint>;
4174 def : N2VSPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
4176 let neverHasSideEffects = 1 in
4177 def VCVTs2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4178 v2f32, v2i32, sint_to_fp>;
4179 def : N2VSPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
4181 let neverHasSideEffects = 1 in
4182 def VCVTu2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4183 v2f32, v2i32, uint_to_fp>;
4184 def : N2VSPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
4186 //===----------------------------------------------------------------------===//
4187 // Non-Instruction Patterns
4188 //===----------------------------------------------------------------------===//
4191 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
4192 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
4193 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
4194 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
4195 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
4196 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
4197 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
4198 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
4199 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
4200 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
4201 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
4202 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
4203 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
4204 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
4205 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
4206 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
4207 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
4208 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
4209 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
4210 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
4211 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
4212 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
4213 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
4214 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
4215 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
4216 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
4217 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
4218 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
4219 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
4220 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
4222 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
4223 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
4224 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
4225 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
4226 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
4227 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
4228 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
4229 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
4230 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
4231 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
4232 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
4233 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
4234 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
4235 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
4236 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
4237 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
4238 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
4239 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
4240 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
4241 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
4242 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
4243 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
4244 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
4245 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
4246 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
4247 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
4248 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
4249 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
4250 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
4251 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;