1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
70 // VDUPLANE can produce a quad-register result from a double-register source,
71 // so the result is not constrained to match the source.
72 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
73 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
76 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
77 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
78 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
80 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
81 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
82 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
83 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
85 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
88 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
89 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
90 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
92 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
94 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
95 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
97 //===----------------------------------------------------------------------===//
98 // NEON operand definitions
99 //===----------------------------------------------------------------------===//
101 def h8imm : Operand<i8> {
102 let PrintMethod = "printHex8ImmOperand";
104 def h16imm : Operand<i16> {
105 let PrintMethod = "printHex16ImmOperand";
107 def h32imm : Operand<i32> {
108 let PrintMethod = "printHex32ImmOperand";
110 def h64imm : Operand<i64> {
111 let PrintMethod = "printHex64ImmOperand";
114 //===----------------------------------------------------------------------===//
115 // NEON load / store instructions
116 //===----------------------------------------------------------------------===//
118 // Use vldmia to load a Q register as a D register pair.
119 def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr), IIC_fpLoadm,
120 "vldmia", "$addr, ${dst:dregpair}",
121 [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]> {
122 let Inst{27-25} = 0b110;
123 let Inst{24} = 0; // P bit
124 let Inst{23} = 1; // U bit
126 let Inst{11-8} = 0b1011;
129 // Use vstmia to store a Q register as a D register pair.
130 def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr), IIC_fpStorem,
131 "vstmia", "$addr, ${src:dregpair}",
132 [(store (v2f64 QPR:$src), addrmode4:$addr)]> {
133 let Inst{27-25} = 0b110;
134 let Inst{24} = 0; // P bit
135 let Inst{23} = 1; // U bit
137 let Inst{11-8} = 0b1011;
140 // VLD1 : Vector Load (multiple single elements)
141 class VLD1D<bits<4> op7_4, string Dt, ValueType Ty>
142 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst), (ins addrmode6:$addr), IIC_VLD1,
143 "vld1", Dt, "\\{$dst\\}, $addr", "",
144 [(set DPR:$dst, (Ty (int_arm_neon_vld1 addrmode6:$addr)))]>;
145 class VLD1Q<bits<4> op7_4, string Dt, ValueType Ty>
146 : NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst), (ins addrmode6:$addr), IIC_VLD1,
147 "vld1", Dt, "${dst:dregpair}, $addr", "",
148 [(set QPR:$dst, (Ty (int_arm_neon_vld1 addrmode6:$addr)))]>;
150 def VLD1d8 : VLD1D<0b0000, "8", v8i8>;
151 def VLD1d16 : VLD1D<0b0100, "16", v4i16>;
152 def VLD1d32 : VLD1D<0b1000, "32", v2i32>;
153 def VLD1df : VLD1D<0b1000, "32", v2f32>;
154 def VLD1d64 : VLD1D<0b1100, "64", v1i64>;
156 def VLD1q8 : VLD1Q<0b0000, "8", v16i8>;
157 def VLD1q16 : VLD1Q<0b0100, "16", v8i16>;
158 def VLD1q32 : VLD1Q<0b1000, "32", v4i32>;
159 def VLD1qf : VLD1Q<0b1000, "32", v4f32>;
160 def VLD1q64 : VLD1Q<0b1100, "64", v2i64>;
164 // ...with address register writeback:
165 class VLD1DWB<bits<4> op7_4, string Dt>
166 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst, GPR:$wb),
167 (ins addrmode6:$addr), IIC_VLD1,
168 "vld1", Dt, "\\{$dst\\}, $addr",
169 "$addr.addr = $wb", []>;
170 class VLD1QWB<bits<4> op7_4, string Dt>
171 : NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst, GPR:$wb),
172 (ins addrmode6:$addr), IIC_VLD1,
173 "vld1", Dt, "${dst:dregpair}, $addr",
174 "$addr.addr = $wb", []>;
176 def VLD1d8_UPD : VLD1DWB<0b0000, "8">;
177 def VLD1d16_UPD : VLD1DWB<0b0100, "16">;
178 def VLD1d32_UPD : VLD1DWB<0b1000, "32">;
179 def VLD1d64_UPD : VLD1DWB<0b1100, "64">;
181 def VLD1q8_UPD : VLD1QWB<0b0000, "8">;
182 def VLD1q16_UPD : VLD1QWB<0b0100, "16">;
183 def VLD1q32_UPD : VLD1QWB<0b1000, "32">;
184 def VLD1q64_UPD : VLD1QWB<0b1100, "64">;
187 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
189 // These (dreg triple/quadruple) are for disassembly only.
190 class VLD1D3<bits<4> op7_4, string Dt>
191 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
192 (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
193 "\\{$dst1, $dst2, $dst3\\}, $addr", "",
194 [/* For disassembly only; pattern left blank */]>;
195 class VLD1D4<bits<4> op7_4, string Dt>
196 : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
197 (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
198 "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "",
199 [/* For disassembly only; pattern left blank */]>;
201 def VLD1d8T : VLD1D3<0b0000, "8">;
202 def VLD1d16T : VLD1D3<0b0100, "16">;
203 def VLD1d32T : VLD1D3<0b1000, "32">;
204 // VLD1d64T : implemented as VLD3d64
206 def VLD1d8Q : VLD1D4<0b0000, "8">;
207 def VLD1d16Q : VLD1D4<0b0100, "16">;
208 def VLD1d32Q : VLD1D4<0b1000, "32">;
209 // VLD1d64Q : implemented as VLD4d64
211 // ...with address register writeback:
212 class VLD1D3WB<bits<4> op7_4, string Dt>
213 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
214 (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
215 "\\{$dst1, $dst2, $dst3\\}, $addr", "$addr.addr = $wb",
216 [/* For disassembly only; pattern left blank */]>;
217 class VLD1D4WB<bits<4> op7_4, string Dt>
218 : NLdSt<0,0b10,0b0010,op7_4,
219 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
220 (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
221 "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "$addr.addr = $wb",
222 [/* For disassembly only; pattern left blank */]>;
224 def VLD1d8T_UPD : VLD1D3WB<0b0000, "8">;
225 def VLD1d16T_UPD : VLD1D3WB<0b0100, "16">;
226 def VLD1d32T_UPD : VLD1D3WB<0b1000, "32">;
227 // VLD1d64T_UPD : implemented as VLD3d64_UPD
229 def VLD1d8Q_UPD : VLD1D4WB<0b0000, "8">;
230 def VLD1d16Q_UPD : VLD1D4WB<0b0100, "16">;
231 def VLD1d32Q_UPD : VLD1D4WB<0b1000, "32">;
232 // VLD1d64Q_UPD : implemented as VLD4d64_UPD
234 // VLD2 : Vector Load (multiple 2-element structures)
235 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
236 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2),
237 (ins addrmode6:$addr), IIC_VLD2,
238 "vld2", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>;
239 class VLD2Q<bits<4> op7_4, string Dt>
240 : NLdSt<0, 0b10, 0b0011, op7_4,
241 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
242 (ins addrmode6:$addr), IIC_VLD2,
243 "vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
245 def VLD2d8 : VLD2D<0b1000, 0b0000, "8">;
246 def VLD2d16 : VLD2D<0b1000, 0b0100, "16">;
247 def VLD2d32 : VLD2D<0b1000, 0b1000, "32">;
248 def VLD2d64 : NLdSt<0,0b10,0b1010,0b1100, (outs DPR:$dst1, DPR:$dst2),
249 (ins addrmode6:$addr), IIC_VLD1,
250 "vld1", "64", "\\{$dst1, $dst2\\}, $addr", "", []>;
252 def VLD2q8 : VLD2Q<0b0000, "8">;
253 def VLD2q16 : VLD2Q<0b0100, "16">;
254 def VLD2q32 : VLD2Q<0b1000, "32">;
256 // ...with address register writeback:
257 class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
258 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
259 (ins addrmode6:$addr), IIC_VLD2,
260 "vld2", Dt, "\\{$dst1, $dst2\\}, $addr",
261 "$addr.addr = $wb", []>;
262 class VLD2QWB<bits<4> op7_4, string Dt>
263 : NLdSt<0, 0b10, 0b0011, op7_4,
264 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
265 (ins addrmode6:$addr), IIC_VLD2,
266 "vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr",
267 "$addr.addr = $wb", []>;
269 def VLD2d8_UPD : VLD2DWB<0b1000, 0b0000, "8">;
270 def VLD2d16_UPD : VLD2DWB<0b1000, 0b0100, "16">;
271 def VLD2d32_UPD : VLD2DWB<0b1000, 0b1000, "32">;
272 def VLD2d64_UPD : NLdSt<0,0b10,0b1010,0b1100,
273 (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
274 (ins addrmode6:$addr), IIC_VLD1,
275 "vld1", "64", "\\{$dst1, $dst2\\}, $addr",
276 "$addr.addr = $wb", []>;
278 def VLD2q8_UPD : VLD2QWB<0b0000, "8">;
279 def VLD2q16_UPD : VLD2QWB<0b0100, "16">;
280 def VLD2q32_UPD : VLD2QWB<0b1000, "32">;
282 // ...with double-spaced registers (for disassembly only):
283 def VLD2b8 : VLD2D<0b1001, 0b0000, "8">;
284 def VLD2b16 : VLD2D<0b1001, 0b0100, "16">;
285 def VLD2b32 : VLD2D<0b1001, 0b1000, "32">;
286 def VLD2b8_UPD : VLD2DWB<0b1001, 0b0000, "8">;
287 def VLD2b16_UPD : VLD2DWB<0b1001, 0b0100, "16">;
288 def VLD2b32_UPD : VLD2DWB<0b1001, 0b1000, "32">;
290 // VLD3 : Vector Load (multiple 3-element structures)
291 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
292 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
293 (ins addrmode6:$addr), IIC_VLD3,
294 "vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
296 def VLD3d8 : VLD3D<0b0100, 0b0000, "8">;
297 def VLD3d16 : VLD3D<0b0100, 0b0100, "16">;
298 def VLD3d32 : VLD3D<0b0100, 0b1000, "32">;
299 def VLD3d64 : NLdSt<0,0b10,0b0110,0b1100,
300 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
301 (ins addrmode6:$addr), IIC_VLD1,
302 "vld1", "64", "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
304 // ...with address register writeback:
305 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
306 : NLdSt<0, 0b10, op11_8, op7_4,
307 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
308 (ins addrmode6:$addr), IIC_VLD3,
309 "vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr",
310 "$addr.addr = $wb", []>;
312 def VLD3d8_UPD : VLD3DWB<0b0100, 0b0000, "8">;
313 def VLD3d16_UPD : VLD3DWB<0b0100, 0b0100, "16">;
314 def VLD3d32_UPD : VLD3DWB<0b0100, 0b1000, "32">;
315 def VLD3d64_UPD : NLdSt<0,0b10,0b0110,0b1100,
316 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
317 (ins addrmode6:$addr), IIC_VLD1,
318 "vld1", "64", "\\{$dst1, $dst2, $dst3\\}, $addr",
319 "$addr.addr = $wb", []>;
321 // ...with double-spaced registers (non-updating versions for disassembly only):
322 def VLD3q8 : VLD3D<0b0101, 0b0000, "8">;
323 def VLD3q16 : VLD3D<0b0101, 0b0100, "16">;
324 def VLD3q32 : VLD3D<0b0101, 0b1000, "32">;
325 def VLD3q8_UPD : VLD3DWB<0b0101, 0b0000, "8">;
326 def VLD3q16_UPD : VLD3DWB<0b0101, 0b0100, "16">;
327 def VLD3q32_UPD : VLD3DWB<0b0101, 0b1000, "32">;
329 // ...alternate versions to be allocated odd register numbers:
330 def VLD3q8odd_UPD : VLD3DWB<0b0101, 0b0000, "8">;
331 def VLD3q16odd_UPD : VLD3DWB<0b0101, 0b0100, "16">;
332 def VLD3q32odd_UPD : VLD3DWB<0b0101, 0b1000, "32">;
334 // VLD4 : Vector Load (multiple 4-element structures)
335 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
336 : NLdSt<0, 0b10, op11_8, op7_4,
337 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
338 (ins addrmode6:$addr), IIC_VLD4,
339 "vld4", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
341 def VLD4d8 : VLD4D<0b0000, 0b0000, "8">;
342 def VLD4d16 : VLD4D<0b0000, 0b0100, "16">;
343 def VLD4d32 : VLD4D<0b0000, 0b1000, "32">;
344 def VLD4d64 : NLdSt<0,0b10,0b0010,0b1100,
345 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
346 (ins addrmode6:$addr), IIC_VLD1,
347 "vld1", "64", "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr",
350 // ...with address register writeback:
351 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
352 : NLdSt<0, 0b10, op11_8, op7_4,
353 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
354 (ins addrmode6:$addr), IIC_VLD4,
355 "vld4", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr",
356 "$addr.addr = $wb", []>;
358 def VLD4d8_UPD : VLD4DWB<0b0000, 0b0000, "8">;
359 def VLD4d16_UPD : VLD4DWB<0b0000, 0b0100, "16">;
360 def VLD4d32_UPD : VLD4DWB<0b0000, 0b1000, "32">;
361 def VLD4d64_UPD : NLdSt<0,0b10,0b0010,0b1100,
362 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4,
364 (ins addrmode6:$addr), IIC_VLD1,
366 "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr",
367 "$addr.addr = $wb", []>;
369 // ...with double-spaced registers (non-updating versions for disassembly only):
370 def VLD4q8 : VLD4D<0b0001, 0b0000, "8">;
371 def VLD4q16 : VLD4D<0b0001, 0b0100, "16">;
372 def VLD4q32 : VLD4D<0b0001, 0b1000, "32">;
373 def VLD4q8_UPD : VLD4DWB<0b0001, 0b0000, "8">;
374 def VLD4q16_UPD : VLD4DWB<0b0001, 0b0100, "16">;
375 def VLD4q32_UPD : VLD4DWB<0b0001, 0b1000, "32">;
377 // ...alternate versions to be allocated odd register numbers:
378 def VLD4q8odd_UPD : VLD4DWB<0b0001, 0b0000, "8">;
379 def VLD4q16odd_UPD : VLD4DWB<0b0001, 0b0100, "16">;
380 def VLD4q32odd_UPD : VLD4DWB<0b0001, 0b1000, "32">;
382 // VLD1LN : Vector Load (single element to one lane)
383 // FIXME: Not yet implemented.
385 // VLD2LN : Vector Load (single 2-element structure to one lane)
386 class VLD2LN<bits<4> op11_8, string Dt>
387 : NLdSt<1, 0b10, op11_8, {?,?,?,?}, (outs DPR:$dst1, DPR:$dst2),
388 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
389 IIC_VLD2, "vld2", Dt, "\\{$dst1[$lane], $dst2[$lane]\\}, $addr",
390 "$src1 = $dst1, $src2 = $dst2", []>;
392 def VLD2LNd8 : VLD2LN<0b0001, "8">;
393 def VLD2LNd16 : VLD2LN<0b0101, "16"> { let Inst{5} = 0; }
394 def VLD2LNd32 : VLD2LN<0b1001, "32"> { let Inst{6} = 0; }
396 // ...with double-spaced registers:
397 def VLD2LNq16 : VLD2LN<0b0101, "16"> { let Inst{5} = 1; }
398 def VLD2LNq32 : VLD2LN<0b1001, "32"> { let Inst{6} = 1; }
400 // ...alternate versions to be allocated odd register numbers:
401 def VLD2LNq16odd : VLD2LN<0b0101, "16"> { let Inst{5} = 1; }
402 def VLD2LNq32odd : VLD2LN<0b1001, "32"> { let Inst{6} = 1; }
404 // ...with address register writeback:
405 class VLD2LNWB<bits<4> op11_8, string Dt>
406 : NLdSt<1, 0b10, op11_8, {?,?,?,?}, (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
407 (ins addrmode6:$addr,
408 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2, "vld2", Dt,
409 "\\{$dst1[$lane], $dst2[$lane]\\}, $addr",
410 "$src1 = $dst1, $src2 = $dst2, $addr.addr = $wb", []>;
412 def VLD2LNd8_UPD : VLD2LNWB<0b0001, "8">;
413 def VLD2LNd16_UPD : VLD2LNWB<0b0101, "16"> { let Inst{5} = 0; }
414 def VLD2LNd32_UPD : VLD2LNWB<0b1001, "32"> { let Inst{6} = 0; }
416 def VLD2LNq16_UPD : VLD2LNWB<0b0101, "16"> { let Inst{5} = 1; }
417 def VLD2LNq32_UPD : VLD2LNWB<0b1001, "32"> { let Inst{6} = 1; }
419 // VLD3LN : Vector Load (single 3-element structure to one lane)
420 class VLD3LN<bits<4> op11_8, string Dt>
421 : NLdSt<1, 0b10, op11_8, {?,?,?,?}, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
422 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
423 nohash_imm:$lane), IIC_VLD3, "vld3", Dt,
424 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr",
425 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
427 def VLD3LNd8 : VLD3LN<0b0010, "8"> { let Inst{4} = 0; }
428 def VLD3LNd16 : VLD3LN<0b0110, "16"> { let Inst{5-4} = 0b00; }
429 def VLD3LNd32 : VLD3LN<0b1010, "32"> { let Inst{6-4} = 0b000; }
431 // ...with double-spaced registers:
432 def VLD3LNq16 : VLD3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
433 def VLD3LNq32 : VLD3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
435 // ...alternate versions to be allocated odd register numbers:
436 def VLD3LNq16odd : VLD3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
437 def VLD3LNq32odd : VLD3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
439 // ...with address register writeback:
440 class VLD3LNWB<bits<4> op11_8, string Dt>
441 : NLdSt<1, 0b10, op11_8, {?,?,?,?},
442 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
443 (ins addrmode6:$addr,
444 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
445 IIC_VLD3, "vld3", Dt,
446 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr",
447 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $addr.addr = $wb",
450 def VLD3LNd8_UPD : VLD3LNWB<0b0010, "8"> { let Inst{4} = 0; }
451 def VLD3LNd16_UPD : VLD3LNWB<0b0110, "16"> { let Inst{5-4} = 0b00; }
452 def VLD3LNd32_UPD : VLD3LNWB<0b1010, "32"> { let Inst{6-4} = 0b000; }
454 def VLD3LNq16_UPD : VLD3LNWB<0b0110, "16"> { let Inst{5-4} = 0b10; }
455 def VLD3LNq32_UPD : VLD3LNWB<0b1010, "32"> { let Inst{6-4} = 0b100; }
457 // VLD4LN : Vector Load (single 4-element structure to one lane)
458 class VLD4LN<bits<4> op11_8, string Dt>
459 : NLdSt<1, 0b10, op11_8, {?,?,?,?},
460 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
461 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
462 nohash_imm:$lane), IIC_VLD4, "vld4", Dt,
463 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr",
464 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
466 def VLD4LNd8 : VLD4LN<0b0011, "8">;
467 def VLD4LNd16 : VLD4LN<0b0111, "16"> { let Inst{5} = 0; }
468 def VLD4LNd32 : VLD4LN<0b1011, "32"> { let Inst{6} = 0; }
470 // ...with double-spaced registers:
471 def VLD4LNq16 : VLD4LN<0b0111, "16"> { let Inst{5} = 1; }
472 def VLD4LNq32 : VLD4LN<0b1011, "32"> { let Inst{6} = 1; }
474 // ...alternate versions to be allocated odd register numbers:
475 def VLD4LNq16odd : VLD4LN<0b0111, "16"> { let Inst{5} = 1; }
476 def VLD4LNq32odd : VLD4LN<0b1011, "32"> { let Inst{6} = 1; }
478 // ...with address register writeback:
479 class VLD4LNWB<bits<4> op11_8, string Dt>
480 : NLdSt<1, 0b10, op11_8, {?,?,?,?},
481 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
482 (ins addrmode6:$addr,
483 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
484 IIC_VLD4, "vld4", Dt,
485 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr",
486 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $addr.addr = $wb",
489 def VLD4LNd8_UPD : VLD4LNWB<0b0011, "8">;
490 def VLD4LNd16_UPD : VLD4LNWB<0b0111, "16"> { let Inst{5} = 0; }
491 def VLD4LNd32_UPD : VLD4LNWB<0b1011, "32"> { let Inst{6} = 0; }
493 def VLD4LNq16_UPD : VLD4LNWB<0b0111, "16"> { let Inst{5} = 1; }
494 def VLD4LNq32_UPD : VLD4LNWB<0b1011, "32"> { let Inst{6} = 1; }
496 // VLD1DUP : Vector Load (single element to all lanes)
497 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
498 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
499 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
500 // FIXME: Not yet implemented.
501 } // mayLoad = 1, hasExtraDefRegAllocReq = 1
503 // VST1 : Vector Store (multiple single elements)
504 class VST1D<bits<4> op7_4, string Dt, ValueType Ty>
505 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src), IIC_VST,
506 "vst1", Dt, "\\{$src\\}, $addr", "",
507 [(int_arm_neon_vst1 addrmode6:$addr, (Ty DPR:$src))]>;
508 class VST1Q<bits<4> op7_4, string Dt, ValueType Ty>
509 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$addr, QPR:$src), IIC_VST,
510 "vst1", Dt, "${src:dregpair}, $addr", "",
511 [(int_arm_neon_vst1 addrmode6:$addr, (Ty QPR:$src))]>;
513 let hasExtraSrcRegAllocReq = 1 in {
514 def VST1d8 : VST1D<0b0000, "8", v8i8>;
515 def VST1d16 : VST1D<0b0100, "16", v4i16>;
516 def VST1d32 : VST1D<0b1000, "32", v2i32>;
517 def VST1df : VST1D<0b1000, "32", v2f32>;
518 def VST1d64 : VST1D<0b1100, "64", v1i64>;
520 def VST1q8 : VST1Q<0b0000, "8", v16i8>;
521 def VST1q16 : VST1Q<0b0100, "16", v8i16>;
522 def VST1q32 : VST1Q<0b1000, "32", v4i32>;
523 def VST1qf : VST1Q<0b1000, "32", v4f32>;
524 def VST1q64 : VST1Q<0b1100, "64", v2i64>;
525 } // hasExtraSrcRegAllocReq
527 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
529 // ...with address register writeback:
530 class VST1DWB<bits<4> op7_4, string Dt>
531 : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
532 (ins addrmode6:$addr, DPR:$src), IIC_VST,
533 "vst1", Dt, "\\{$src\\}, $addr", "$addr.addr = $wb", []>;
534 class VST1QWB<bits<4> op7_4, string Dt>
535 : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),
536 (ins addrmode6:$addr, QPR:$src), IIC_VST,
537 "vst1", Dt, "${src:dregpair}, $addr", "$addr.addr = $wb", []>;
539 def VST1d8_UPD : VST1DWB<0b0000, "8">;
540 def VST1d16_UPD : VST1DWB<0b0100, "16">;
541 def VST1d32_UPD : VST1DWB<0b1000, "32">;
542 def VST1d64_UPD : VST1DWB<0b1100, "64">;
544 def VST1q8_UPD : VST1QWB<0b0000, "8">;
545 def VST1q16_UPD : VST1QWB<0b0100, "16">;
546 def VST1q32_UPD : VST1QWB<0b1000, "32">;
547 def VST1q64_UPD : VST1QWB<0b1100, "64">;
549 // These (dreg triple/quadruple) are for disassembly only.
550 class VST1D3<bits<4> op7_4, string Dt>
551 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
552 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
553 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr", "",
554 [/* For disassembly only; pattern left blank */]>;
555 class VST1D4<bits<4> op7_4, string Dt>
556 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
557 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
558 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr", "",
559 [/* For disassembly only; pattern left blank */]>;
561 def VST1d8T : VST1D3<0b0000, "8">;
562 def VST1d16T : VST1D3<0b0100, "16">;
563 def VST1d32T : VST1D3<0b1000, "32">;
564 // VST1d64T : implemented as VST3d64
566 def VST1d8Q : VST1D4<0b0000, "8">;
567 def VST1d16Q : VST1D4<0b0100, "16">;
568 def VST1d32Q : VST1D4<0b1000, "32">;
569 // VST1d64Q : implemented as VST4d64
571 // ...with address register writeback:
572 class VST1D3WB<bits<4> op7_4, string Dt>
573 : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
574 (ins addrmode6:$addr,
575 DPR:$src1, DPR:$src2, DPR:$src3),
576 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr",
578 [/* For disassembly only; pattern left blank */]>;
579 class VST1D4WB<bits<4> op7_4, string Dt>
580 : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
581 (ins addrmode6:$addr,
582 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
583 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
585 [/* For disassembly only; pattern left blank */]>;
587 def VST1d8T_UPD : VST1D3WB<0b0000, "8">;
588 def VST1d16T_UPD : VST1D3WB<0b0100, "16">;
589 def VST1d32T_UPD : VST1D3WB<0b1000, "32">;
590 // VST1d64T_UPD : implemented as VST3d64_UPD
592 def VST1d8Q_UPD : VST1D4WB<0b0000, "8">;
593 def VST1d16Q_UPD : VST1D4WB<0b0100, "16">;
594 def VST1d32Q_UPD : VST1D4WB<0b1000, "32">;
595 // VST1d64Q_UPD : implemented as VST4d64_UPD
597 // VST2 : Vector Store (multiple 2-element structures)
598 class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
599 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
600 (ins addrmode6:$addr, DPR:$src1, DPR:$src2),
601 IIC_VST, "vst2", Dt, "\\{$src1, $src2\\}, $addr", "", []>;
602 class VST2Q<bits<4> op7_4, string Dt>
603 : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
604 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
605 IIC_VST, "vst2", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
608 def VST2d8 : VST2D<0b1000, 0b0000, "8">;
609 def VST2d16 : VST2D<0b1000, 0b0100, "16">;
610 def VST2d32 : VST2D<0b1000, 0b1000, "32">;
611 def VST2d64 : NLdSt<0,0b00,0b1010,0b1100, (outs),
612 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
613 "vst1", "64", "\\{$src1, $src2\\}, $addr", "", []>;
615 def VST2q8 : VST2Q<0b0000, "8">;
616 def VST2q16 : VST2Q<0b0100, "16">;
617 def VST2q32 : VST2Q<0b1000, "32">;
619 // ...with address register writeback:
620 class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
621 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
622 (ins addrmode6:$addr, DPR:$src1, DPR:$src2),
623 IIC_VST, "vst2", Dt, "\\{$src1, $src2\\}, $addr",
624 "$addr.addr = $wb", []>;
625 class VST2QWB<bits<4> op7_4, string Dt>
626 : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
627 (ins addrmode6:$addr,
628 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
629 IIC_VST, "vst2", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
630 "$addr.addr = $wb", []>;
632 def VST2d8_UPD : VST2DWB<0b1000, 0b0000, "8">;
633 def VST2d16_UPD : VST2DWB<0b1000, 0b0100, "16">;
634 def VST2d32_UPD : VST2DWB<0b1000, 0b1000, "32">;
635 def VST2d64_UPD : NLdSt<0,0b00,0b1010,0b1100, (outs GPR:$wb),
636 (ins addrmode6:$addr,
637 DPR:$src1, DPR:$src2), IIC_VST,
638 "vst1", "64", "\\{$src1, $src2\\}, $addr",
639 "$addr.addr = $wb", []>;
641 def VST2q8_UPD : VST2QWB<0b0000, "8">;
642 def VST2q16_UPD : VST2QWB<0b0100, "16">;
643 def VST2q32_UPD : VST2QWB<0b1000, "32">;
645 // ...with double-spaced registers (for disassembly only):
646 def VST2b8 : VST2D<0b1001, 0b0000, "8">;
647 def VST2b16 : VST2D<0b1001, 0b0100, "16">;
648 def VST2b32 : VST2D<0b1001, 0b1000, "32">;
649 def VST2b8_UPD : VST2DWB<0b1001, 0b0000, "8">;
650 def VST2b16_UPD : VST2DWB<0b1001, 0b0100, "16">;
651 def VST2b32_UPD : VST2DWB<0b1001, 0b1000, "32">;
653 // VST3 : Vector Store (multiple 3-element structures)
654 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
655 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
656 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
657 "vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>;
659 def VST3d8 : VST3D<0b0100, 0b0000, "8">;
660 def VST3d16 : VST3D<0b0100, 0b0100, "16">;
661 def VST3d32 : VST3D<0b0100, 0b1000, "32">;
662 def VST3d64 : NLdSt<0,0b00,0b0110,0b1100, (outs),
663 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
665 "vst1", "64", "\\{$src1, $src2, $src3\\}, $addr", "", []>;
667 // ...with address register writeback:
668 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
669 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
670 (ins addrmode6:$addr,
671 DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
672 "vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr",
673 "$addr.addr = $wb", []>;
675 def VST3d8_UPD : VST3DWB<0b0100, 0b0000, "8">;
676 def VST3d16_UPD : VST3DWB<0b0100, 0b0100, "16">;
677 def VST3d32_UPD : VST3DWB<0b0100, 0b1000, "32">;
678 def VST3d64_UPD : NLdSt<0,0b00,0b0110,0b1100, (outs GPR:$wb),
679 (ins addrmode6:$addr,
680 DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
681 "vst1", "64", "\\{$src1, $src2, $src3\\}, $addr",
682 "$addr.addr = $wb", []>;
684 // ...with double-spaced registers (non-updating versions for disassembly only):
685 def VST3q8 : VST3D<0b0101, 0b0000, "8">;
686 def VST3q16 : VST3D<0b0101, 0b0100, "16">;
687 def VST3q32 : VST3D<0b0101, 0b1000, "32">;
688 def VST3q8_UPD : VST3DWB<0b0101, 0b0000, "8">;
689 def VST3q16_UPD : VST3DWB<0b0101, 0b0100, "16">;
690 def VST3q32_UPD : VST3DWB<0b0101, 0b1000, "32">;
692 // ...alternate versions to be allocated odd register numbers:
693 def VST3q8odd_UPD : VST3DWB<0b0101, 0b0000, "8">;
694 def VST3q16odd_UPD : VST3DWB<0b0101, 0b0100, "16">;
695 def VST3q32odd_UPD : VST3DWB<0b0101, 0b1000, "32">;
697 // VST4 : Vector Store (multiple 4-element structures)
698 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
699 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
700 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
701 IIC_VST, "vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
704 def VST4d8 : VST4D<0b0000, 0b0000, "8">;
705 def VST4d16 : VST4D<0b0000, 0b0100, "16">;
706 def VST4d32 : VST4D<0b0000, 0b1000, "32">;
707 def VST4d64 : NLdSt<0,0b00,0b0010,0b1100, (outs),
708 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
710 "vst1", "64", "\\{$src1, $src2, $src3, $src4\\}, $addr",
713 // ...with address register writeback:
714 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
715 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
716 (ins addrmode6:$addr,
717 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST,
718 "vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
719 "$addr.addr = $wb", []>;
721 def VST4d8_UPD : VST4DWB<0b0000, 0b0000, "8">;
722 def VST4d16_UPD : VST4DWB<0b0000, 0b0100, "16">;
723 def VST4d32_UPD : VST4DWB<0b0000, 0b1000, "32">;
724 def VST4d64_UPD : NLdSt<0,0b00,0b0010,0b1100, (outs GPR:$wb),
725 (ins addrmode6:$addr,
726 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST,
728 "\\{$src1, $src2, $src3, $src4\\}, $addr",
729 "$addr.addr = $wb", []>;
731 // ...with double-spaced registers (non-updating versions for disassembly only):
732 def VST4q8 : VST4D<0b0001, 0b0000, "8">;
733 def VST4q16 : VST4D<0b0001, 0b0100, "16">;
734 def VST4q32 : VST4D<0b0001, 0b1000, "32">;
735 def VST4q8_UPD : VST4DWB<0b0001, 0b0000, "8">;
736 def VST4q16_UPD : VST4DWB<0b0001, 0b0100, "16">;
737 def VST4q32_UPD : VST4DWB<0b0001, 0b1000, "32">;
739 // ...alternate versions to be allocated odd register numbers:
740 def VST4q8odd_UPD : VST4DWB<0b0001, 0b0000, "8">;
741 def VST4q16odd_UPD : VST4DWB<0b0001, 0b0100, "16">;
742 def VST4q32odd_UPD : VST4DWB<0b0001, 0b1000, "32">;
744 // VST1LN : Vector Store (single element from one lane)
745 // FIXME: Not yet implemented.
747 // VST2LN : Vector Store (single 2-element structure from one lane)
748 class VST2LN<bits<4> op11_8, string Dt>
749 : NLdSt<1, 0b00, op11_8, {?,?,?,?}, (outs),
750 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
751 IIC_VST, "vst2", Dt, "\\{$src1[$lane], $src2[$lane]\\}, $addr",
754 def VST2LNd8 : VST2LN<0b0001, "8">;
755 def VST2LNd16 : VST2LN<0b0101, "16"> { let Inst{5} = 0; }
756 def VST2LNd32 : VST2LN<0b1001, "32"> { let Inst{6} = 0; }
758 // ...with double-spaced registers:
759 def VST2LNq16 : VST2LN<0b0101, "16"> { let Inst{5} = 1; }
760 def VST2LNq32 : VST2LN<0b1001, "32"> { let Inst{6} = 1; }
762 // ...alternate versions to be allocated odd register numbers:
763 def VST2LNq16odd : VST2LN<0b0101, "16"> { let Inst{5} = 1; }
764 def VST2LNq32odd : VST2LN<0b1001, "32"> { let Inst{6} = 1; }
766 // ...with address register writeback:
767 class VST2LNWB<bits<4> op11_8, string Dt>
768 : NLdSt<1, 0b00, op11_8, {?,?,?,?}, (outs GPR:$wb),
769 (ins addrmode6:$addr,
770 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST, "vst2", Dt,
771 "\\{$src1[$lane], $src2[$lane]\\}, $addr",
772 "$addr.addr = $wb", []>;
774 def VST2LNd8_UPD : VST2LNWB<0b0001, "8">;
775 def VST2LNd16_UPD : VST2LNWB<0b0101, "16"> { let Inst{5} = 0; }
776 def VST2LNd32_UPD : VST2LNWB<0b1001, "32"> { let Inst{6} = 0; }
778 def VST2LNq16_UPD : VST2LNWB<0b0101, "16"> { let Inst{5} = 1; }
779 def VST2LNq32_UPD : VST2LNWB<0b1001, "32"> { let Inst{6} = 1; }
781 // VST3LN : Vector Store (single 3-element structure from one lane)
782 class VST3LN<bits<4> op11_8, string Dt>
783 : NLdSt<1, 0b00, op11_8, {?,?,?,?}, (outs),
784 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
785 nohash_imm:$lane), IIC_VST, "vst3", Dt,
786 "\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr", "", []>;
788 def VST3LNd8 : VST3LN<0b0010, "8"> { let Inst{4} = 0; }
789 def VST3LNd16 : VST3LN<0b0110, "16"> { let Inst{5-4} = 0b00; }
790 def VST3LNd32 : VST3LN<0b1010, "32"> { let Inst{6-4} = 0b000; }
792 // ...with double-spaced registers:
793 def VST3LNq16 : VST3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
794 def VST3LNq32 : VST3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
796 // ...alternate versions to be allocated odd register numbers:
797 def VST3LNq16odd : VST3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
798 def VST3LNq32odd : VST3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
800 // ...with address register writeback:
801 class VST3LNWB<bits<4> op11_8, string Dt>
802 : NLdSt<1, 0b00, op11_8, {?,?,?,?}, (outs GPR:$wb),
803 (ins addrmode6:$addr,
804 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
806 "\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr",
807 "$addr.addr = $wb", []>;
809 def VST3LNd8_UPD : VST3LNWB<0b0010, "8"> { let Inst{4} = 0; }
810 def VST3LNd16_UPD : VST3LNWB<0b0110, "16"> { let Inst{5-4} = 0b00; }
811 def VST3LNd32_UPD : VST3LNWB<0b1010, "32"> { let Inst{6-4} = 0b000; }
813 def VST3LNq16_UPD : VST3LNWB<0b0110, "16"> { let Inst{5-4} = 0b10; }
814 def VST3LNq32_UPD : VST3LNWB<0b1010, "32"> { let Inst{6-4} = 0b100; }
816 // VST4LN : Vector Store (single 4-element structure from one lane)
817 class VST4LN<bits<4> op11_8, string Dt>
818 : NLdSt<1, 0b00, op11_8, {?,?,?,?}, (outs),
819 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
820 nohash_imm:$lane), IIC_VST, "vst4", Dt,
821 "\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr",
824 def VST4LNd8 : VST4LN<0b0011, "8">;
825 def VST4LNd16 : VST4LN<0b0111, "16"> { let Inst{5} = 0; }
826 def VST4LNd32 : VST4LN<0b1011, "32"> { let Inst{6} = 0; }
828 // ...with double-spaced registers:
829 def VST4LNq16 : VST4LN<0b0111, "16"> { let Inst{5} = 1; }
830 def VST4LNq32 : VST4LN<0b1011, "32"> { let Inst{6} = 1; }
832 // ...alternate versions to be allocated odd register numbers:
833 def VST4LNq16odd : VST4LN<0b0111, "16"> { let Inst{5} = 1; }
834 def VST4LNq32odd : VST4LN<0b1011, "32"> { let Inst{6} = 1; }
836 // ...with address register writeback:
837 class VST4LNWB<bits<4> op11_8, string Dt>
838 : NLdSt<1, 0b00, op11_8, {?,?,?,?}, (outs GPR:$wb),
839 (ins addrmode6:$addr,
840 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
842 "\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr",
843 "$addr.addr = $wb", []>;
845 def VST4LNd8_UPD : VST4LNWB<0b0011, "8">;
846 def VST4LNd16_UPD : VST4LNWB<0b0111, "16"> { let Inst{5} = 0; }
847 def VST4LNd32_UPD : VST4LNWB<0b1011, "32"> { let Inst{6} = 0; }
849 def VST4LNq16_UPD : VST4LNWB<0b0111, "16"> { let Inst{5} = 1; }
850 def VST4LNq32_UPD : VST4LNWB<0b1011, "32"> { let Inst{6} = 1; }
852 } // mayStore = 1, hasExtraSrcRegAllocReq = 1
855 //===----------------------------------------------------------------------===//
856 // NEON pattern fragments
857 //===----------------------------------------------------------------------===//
859 // Extract D sub-registers of Q registers.
860 // (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
861 def DSubReg_i8_reg : SDNodeXForm<imm, [{
862 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
864 def DSubReg_i16_reg : SDNodeXForm<imm, [{
865 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
867 def DSubReg_i32_reg : SDNodeXForm<imm, [{
868 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
870 def DSubReg_f64_reg : SDNodeXForm<imm, [{
871 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
873 def DSubReg_f64_other_reg : SDNodeXForm<imm, [{
874 return CurDAG->getTargetConstant(5 + (1 - N->getZExtValue()), MVT::i32);
877 // Extract S sub-registers of Q/D registers.
878 // (arm_ssubreg_0 is 1; arm_ssubreg_1 is 2; etc.)
879 def SSubReg_f32_reg : SDNodeXForm<imm, [{
880 return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32);
883 // Translate lane numbers from Q registers to D subregs.
884 def SubReg_i8_lane : SDNodeXForm<imm, [{
885 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
887 def SubReg_i16_lane : SDNodeXForm<imm, [{
888 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
890 def SubReg_i32_lane : SDNodeXForm<imm, [{
891 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
894 //===----------------------------------------------------------------------===//
895 // Instruction Classes
896 //===----------------------------------------------------------------------===//
898 // Basic 2-register operations: single-, double- and quad-register.
899 class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
900 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
901 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
902 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
903 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
904 IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
905 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
906 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
907 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
908 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
909 (ins DPR:$src), IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "",
910 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
911 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
912 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
913 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
914 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
915 (ins QPR:$src), IIC_VUNAQ, OpcodeStr, Dt, "$dst, $src", "",
916 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
918 // Basic 2-register intrinsics, both double- and quad-register.
919 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
920 bits<2> op17_16, bits<5> op11_7, bit op4,
921 InstrItinClass itin, string OpcodeStr, string Dt,
922 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
923 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
924 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
925 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
926 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
927 bits<2> op17_16, bits<5> op11_7, bit op4,
928 InstrItinClass itin, string OpcodeStr, string Dt,
929 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
930 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
931 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
932 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
934 // Narrow 2-register intrinsics.
935 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
936 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
937 InstrItinClass itin, string OpcodeStr, string Dt,
938 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
939 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
940 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
941 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
943 // Long 2-register intrinsics (currently only used for VMOVL).
944 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
945 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
946 InstrItinClass itin, string OpcodeStr, string Dt,
947 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
948 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$dst),
949 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
950 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
952 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
953 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
954 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
955 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
956 OpcodeStr, Dt, "$dst1, $dst2",
957 "$src1 = $dst1, $src2 = $dst2", []>;
958 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
959 InstrItinClass itin, string OpcodeStr, string Dt>
960 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
961 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$dst1, $dst2",
962 "$src1 = $dst1, $src2 = $dst2", []>;
964 // Basic 3-register operations: single-, double- and quad-register.
965 class N3VS<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
966 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
967 SDNode OpNode, bit Commutable>
968 : N3V<op24, op23, op21_20, op11_8, 0, op4,
969 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), IIC_VBIND,
970 OpcodeStr, Dt, "$dst, $src1, $src2", "", []> {
971 let isCommutable = Commutable;
974 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
975 InstrItinClass itin, string OpcodeStr, string Dt,
976 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
977 : N3V<op24, op23, op21_20, op11_8, 0, op4,
978 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
979 OpcodeStr, Dt, "$dst, $src1, $src2", "",
980 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
981 let isCommutable = Commutable;
983 // Same as N3VD but no data type.
984 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
985 InstrItinClass itin, string OpcodeStr,
986 ValueType ResTy, ValueType OpTy,
987 SDNode OpNode, bit Commutable>
988 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
989 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
990 OpcodeStr, "$dst, $src1, $src2", "",
991 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]>{
992 let isCommutable = Commutable;
994 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
995 InstrItinClass itin, string OpcodeStr, string Dt,
996 ValueType Ty, SDNode ShOp>
997 : N3V<0, 1, op21_20, op11_8, 1, 0,
998 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
999 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1000 [(set (Ty DPR:$dst),
1001 (Ty (ShOp (Ty DPR:$src1),
1002 (Ty (NEONvduplane (Ty DPR_VFP2:$src2), imm:$lane)))))]>{
1003 let isCommutable = 0;
1005 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
1006 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1007 : N3V<0, 1, op21_20, op11_8, 1, 0,
1008 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1009 IIC_VMULi16D, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1010 [(set (Ty DPR:$dst),
1011 (Ty (ShOp (Ty DPR:$src1),
1012 (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
1013 let isCommutable = 0;
1016 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1017 InstrItinClass itin, string OpcodeStr, string Dt,
1018 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1019 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1020 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
1021 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1022 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
1023 let isCommutable = Commutable;
1025 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1026 InstrItinClass itin, string OpcodeStr,
1027 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1028 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
1029 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
1030 OpcodeStr, "$dst, $src1, $src2", "",
1031 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]>{
1032 let isCommutable = Commutable;
1034 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
1035 InstrItinClass itin, string OpcodeStr, string Dt,
1036 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1037 : N3V<1, 1, op21_20, op11_8, 1, 0,
1038 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1039 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1040 [(set (ResTy QPR:$dst),
1041 (ResTy (ShOp (ResTy QPR:$src1),
1042 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1044 let isCommutable = 0;
1046 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
1047 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1048 : N3V<1, 1, op21_20, op11_8, 1, 0,
1049 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1050 IIC_VMULi16Q, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1051 [(set (ResTy QPR:$dst),
1052 (ResTy (ShOp (ResTy QPR:$src1),
1053 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
1055 let isCommutable = 0;
1058 // Basic 3-register intrinsics, both double- and quad-register.
1059 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1060 InstrItinClass itin, string OpcodeStr, string Dt,
1061 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1062 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1063 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
1064 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1065 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
1066 let isCommutable = Commutable;
1068 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1069 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1070 : N3V<0, 1, op21_20, op11_8, 1, 0,
1071 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1072 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1073 [(set (Ty DPR:$dst),
1074 (Ty (IntOp (Ty DPR:$src1),
1075 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
1077 let isCommutable = 0;
1079 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1080 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1081 : N3V<0, 1, op21_20, op11_8, 1, 0,
1082 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1083 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1084 [(set (Ty DPR:$dst),
1085 (Ty (IntOp (Ty DPR:$src1),
1086 (Ty (NEONvduplane (Ty DPR_8:$src2),
1088 let isCommutable = 0;
1091 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1092 InstrItinClass itin, string OpcodeStr, string Dt,
1093 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1094 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1095 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
1096 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1097 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
1098 let isCommutable = Commutable;
1100 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1101 string OpcodeStr, string Dt,
1102 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1103 : N3V<1, 1, op21_20, op11_8, 1, 0,
1104 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1105 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1106 [(set (ResTy QPR:$dst),
1107 (ResTy (IntOp (ResTy QPR:$src1),
1108 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1110 let isCommutable = 0;
1112 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1113 string OpcodeStr, string Dt,
1114 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1115 : N3V<1, 1, op21_20, op11_8, 1, 0,
1116 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1117 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1118 [(set (ResTy QPR:$dst),
1119 (ResTy (IntOp (ResTy QPR:$src1),
1120 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
1122 let isCommutable = 0;
1125 // Multiply-Add/Sub operations: single-, double- and quad-register.
1126 class N3VSMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1127 InstrItinClass itin, string OpcodeStr, string Dt,
1128 ValueType Ty, SDNode MulOp, SDNode OpNode>
1129 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1130 (outs DPR_VFP2:$dst),
1131 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), itin,
1132 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst", []>;
1134 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1135 InstrItinClass itin, string OpcodeStr, string Dt,
1136 ValueType Ty, SDNode MulOp, SDNode OpNode>
1137 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1138 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin,
1139 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1140 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
1141 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
1142 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1143 string OpcodeStr, string Dt,
1144 ValueType Ty, SDNode MulOp, SDNode ShOp>
1145 : N3V<0, 1, op21_20, op11_8, 1, 0,
1147 (ins DPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
1148 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1149 [(set (Ty DPR:$dst),
1150 (Ty (ShOp (Ty DPR:$src1),
1151 (Ty (MulOp DPR:$src2,
1152 (Ty (NEONvduplane (Ty DPR_VFP2:$src3),
1154 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1155 string OpcodeStr, string Dt,
1156 ValueType Ty, SDNode MulOp, SDNode ShOp>
1157 : N3V<0, 1, op21_20, op11_8, 1, 0,
1159 (ins DPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
1160 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1161 [(set (Ty DPR:$dst),
1162 (Ty (ShOp (Ty DPR:$src1),
1163 (Ty (MulOp DPR:$src2,
1164 (Ty (NEONvduplane (Ty DPR_8:$src3),
1167 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1168 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
1169 SDNode MulOp, SDNode OpNode>
1170 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1171 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin,
1172 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1173 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
1174 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
1175 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1176 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1177 SDNode MulOp, SDNode ShOp>
1178 : N3V<1, 1, op21_20, op11_8, 1, 0,
1180 (ins QPR:$src1, QPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
1181 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1182 [(set (ResTy QPR:$dst),
1183 (ResTy (ShOp (ResTy QPR:$src1),
1184 (ResTy (MulOp QPR:$src2,
1185 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src3),
1187 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1188 string OpcodeStr, string Dt,
1189 ValueType ResTy, ValueType OpTy,
1190 SDNode MulOp, SDNode ShOp>
1191 : N3V<1, 1, op21_20, op11_8, 1, 0,
1193 (ins QPR:$src1, QPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
1194 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1195 [(set (ResTy QPR:$dst),
1196 (ResTy (ShOp (ResTy QPR:$src1),
1197 (ResTy (MulOp QPR:$src2,
1198 (ResTy (NEONvduplane (OpTy DPR_8:$src3),
1201 // Neon 3-argument intrinsics, both double- and quad-register.
1202 // The destination register is also used as the first source operand register.
1203 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1204 InstrItinClass itin, string OpcodeStr, string Dt,
1205 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1206 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1207 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin,
1208 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1209 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
1210 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
1211 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1212 InstrItinClass itin, string OpcodeStr, string Dt,
1213 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1214 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1215 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin,
1216 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1217 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
1218 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
1220 // Neon Long 3-argument intrinsic. The destination register is
1221 // a quad-register and is also used as the first source operand register.
1222 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1223 InstrItinClass itin, string OpcodeStr, string Dt,
1224 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
1225 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1226 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), itin,
1227 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1229 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
1230 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1231 string OpcodeStr, string Dt,
1232 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1233 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1235 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
1236 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1237 [(set (ResTy QPR:$dst),
1238 (ResTy (IntOp (ResTy QPR:$src1),
1240 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src3),
1242 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1243 InstrItinClass itin, string OpcodeStr, string Dt,
1244 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1245 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1247 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
1248 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1249 [(set (ResTy QPR:$dst),
1250 (ResTy (IntOp (ResTy QPR:$src1),
1252 (OpTy (NEONvduplane (OpTy DPR_8:$src3),
1255 // Narrowing 3-register intrinsics.
1256 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1257 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
1258 Intrinsic IntOp, bit Commutable>
1259 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1260 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VBINi4D,
1261 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1262 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
1263 let isCommutable = Commutable;
1266 // Long 3-register intrinsics.
1267 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1268 InstrItinClass itin, string OpcodeStr, string Dt,
1269 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
1270 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1271 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
1272 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1273 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
1274 let isCommutable = Commutable;
1276 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1277 string OpcodeStr, string Dt,
1278 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1279 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1280 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1281 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1282 [(set (ResTy QPR:$dst),
1283 (ResTy (IntOp (OpTy DPR:$src1),
1284 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1286 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1287 InstrItinClass itin, string OpcodeStr, string Dt,
1288 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1289 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1290 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1291 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1292 [(set (ResTy QPR:$dst),
1293 (ResTy (IntOp (OpTy DPR:$src1),
1294 (OpTy (NEONvduplane (OpTy DPR_8:$src2),
1297 // Wide 3-register intrinsics.
1298 class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1299 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
1300 Intrinsic IntOp, bit Commutable>
1301 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1302 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), IIC_VSUBiD,
1303 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1304 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
1305 let isCommutable = Commutable;
1308 // Pairwise long 2-register intrinsics, both double- and quad-register.
1309 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1310 bits<2> op17_16, bits<5> op11_7, bit op4,
1311 string OpcodeStr, string Dt,
1312 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1313 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1314 (ins DPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
1315 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
1316 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1317 bits<2> op17_16, bits<5> op11_7, bit op4,
1318 string OpcodeStr, string Dt,
1319 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1320 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1321 (ins QPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
1322 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
1324 // Pairwise long 2-register accumulate intrinsics,
1325 // both double- and quad-register.
1326 // The destination register is also used as the first source operand register.
1327 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1328 bits<2> op17_16, bits<5> op11_7, bit op4,
1329 string OpcodeStr, string Dt,
1330 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1331 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
1332 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), IIC_VPALiD,
1333 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
1334 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
1335 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1336 bits<2> op17_16, bits<5> op11_7, bit op4,
1337 string OpcodeStr, string Dt,
1338 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1339 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
1340 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VPALiQ,
1341 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
1342 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
1344 // Shift by immediate,
1345 // both double- and quad-register.
1346 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1347 InstrItinClass itin, string OpcodeStr, string Dt,
1348 ValueType Ty, SDNode OpNode>
1349 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1350 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), itin,
1351 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1352 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
1353 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1354 InstrItinClass itin, string OpcodeStr, string Dt,
1355 ValueType Ty, SDNode OpNode>
1356 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1357 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin,
1358 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1359 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
1361 // Long shift by immediate.
1362 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1363 string OpcodeStr, string Dt,
1364 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1365 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1366 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VSHLiD,
1367 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1368 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
1369 (i32 imm:$SIMM))))]>;
1371 // Narrow shift by immediate.
1372 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1373 InstrItinClass itin, string OpcodeStr, string Dt,
1374 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1375 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1376 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin,
1377 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1378 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
1379 (i32 imm:$SIMM))))]>;
1381 // Shift right by immediate and accumulate,
1382 // both double- and quad-register.
1383 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1384 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1385 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1386 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), IIC_VPALiD,
1387 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1388 [(set DPR:$dst, (Ty (add DPR:$src1,
1389 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
1390 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1391 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1392 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1393 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), IIC_VPALiD,
1394 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1395 [(set QPR:$dst, (Ty (add QPR:$src1,
1396 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
1398 // Shift by immediate and insert,
1399 // both double- and quad-register.
1400 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1401 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1402 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1403 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), IIC_VSHLiD,
1404 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1405 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
1406 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1407 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1408 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1409 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), IIC_VSHLiQ,
1410 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1411 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
1413 // Convert, with fractional bits immediate,
1414 // both double- and quad-register.
1415 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1416 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1418 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1419 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VUNAD,
1420 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1421 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
1422 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1423 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1425 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1426 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), IIC_VUNAQ,
1427 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1428 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
1430 //===----------------------------------------------------------------------===//
1432 //===----------------------------------------------------------------------===//
1434 // Abbreviations used in multiclass suffixes:
1435 // Q = quarter int (8 bit) elements
1436 // H = half int (16 bit) elements
1437 // S = single int (32 bit) elements
1438 // D = double int (64 bit) elements
1440 // Neon 2-register vector operations -- for disassembly only.
1442 // First with only element sizes of 8, 16 and 32 bits:
1443 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1444 bits<5> op11_7, bit op4, string opc, string Dt,
1446 // 64-bit vector types.
1447 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
1448 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1449 opc, !strconcat(Dt, "8"), asm, "", []>;
1450 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
1451 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1452 opc, !strconcat(Dt, "16"), asm, "", []>;
1453 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
1454 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1455 opc, !strconcat(Dt, "32"), asm, "", []>;
1456 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
1457 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1458 opc, "f32", asm, "", []> {
1459 let Inst{10} = 1; // overwrite F = 1
1462 // 128-bit vector types.
1463 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
1464 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1465 opc, !strconcat(Dt, "8"), asm, "", []>;
1466 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
1467 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1468 opc, !strconcat(Dt, "16"), asm, "", []>;
1469 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
1470 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1471 opc, !strconcat(Dt, "32"), asm, "", []>;
1472 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
1473 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1474 opc, "f32", asm, "", []> {
1475 let Inst{10} = 1; // overwrite F = 1
1479 // Neon 3-register vector operations.
1481 // First with only element sizes of 8, 16 and 32 bits:
1482 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1483 InstrItinClass itinD16, InstrItinClass itinD32,
1484 InstrItinClass itinQ16, InstrItinClass itinQ32,
1485 string OpcodeStr, string Dt,
1486 SDNode OpNode, bit Commutable = 0> {
1487 // 64-bit vector types.
1488 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
1489 OpcodeStr, !strconcat(Dt, "8"),
1490 v8i8, v8i8, OpNode, Commutable>;
1491 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
1492 OpcodeStr, !strconcat(Dt, "16"),
1493 v4i16, v4i16, OpNode, Commutable>;
1494 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
1495 OpcodeStr, !strconcat(Dt, "32"),
1496 v2i32, v2i32, OpNode, Commutable>;
1498 // 128-bit vector types.
1499 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
1500 OpcodeStr, !strconcat(Dt, "8"),
1501 v16i8, v16i8, OpNode, Commutable>;
1502 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
1503 OpcodeStr, !strconcat(Dt, "16"),
1504 v8i16, v8i16, OpNode, Commutable>;
1505 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
1506 OpcodeStr, !strconcat(Dt, "32"),
1507 v4i32, v4i32, OpNode, Commutable>;
1510 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
1511 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1513 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
1515 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1516 v8i16, v4i16, ShOp>;
1517 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
1518 v4i32, v2i32, ShOp>;
1521 // ....then also with element size 64 bits:
1522 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1523 InstrItinClass itinD, InstrItinClass itinQ,
1524 string OpcodeStr, string Dt,
1525 SDNode OpNode, bit Commutable = 0>
1526 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
1527 OpcodeStr, Dt, OpNode, Commutable> {
1528 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
1529 OpcodeStr, !strconcat(Dt, "64"),
1530 v1i64, v1i64, OpNode, Commutable>;
1531 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
1532 OpcodeStr, !strconcat(Dt, "64"),
1533 v2i64, v2i64, OpNode, Commutable>;
1537 // Neon Narrowing 2-register vector intrinsics,
1538 // source operand element sizes of 16, 32 and 64 bits:
1539 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1540 bits<5> op11_7, bit op6, bit op4,
1541 InstrItinClass itin, string OpcodeStr, string Dt,
1543 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
1544 itin, OpcodeStr, !strconcat(Dt, "16"),
1545 v8i8, v8i16, IntOp>;
1546 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
1547 itin, OpcodeStr, !strconcat(Dt, "32"),
1548 v4i16, v4i32, IntOp>;
1549 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
1550 itin, OpcodeStr, !strconcat(Dt, "64"),
1551 v2i32, v2i64, IntOp>;
1555 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
1556 // source operand element sizes of 16, 32 and 64 bits:
1557 multiclass N2VLInt_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
1558 string OpcodeStr, string Dt, Intrinsic IntOp> {
1559 def v8i16 : N2VLInt<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1560 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
1561 def v4i32 : N2VLInt<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1562 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1563 def v2i64 : N2VLInt<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1564 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1568 // Neon 3-register vector intrinsics.
1570 // First with only element sizes of 16 and 32 bits:
1571 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1572 InstrItinClass itinD16, InstrItinClass itinD32,
1573 InstrItinClass itinQ16, InstrItinClass itinQ32,
1574 string OpcodeStr, string Dt,
1575 Intrinsic IntOp, bit Commutable = 0> {
1576 // 64-bit vector types.
1577 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, itinD16,
1578 OpcodeStr, !strconcat(Dt, "16"),
1579 v4i16, v4i16, IntOp, Commutable>;
1580 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, itinD32,
1581 OpcodeStr, !strconcat(Dt, "32"),
1582 v2i32, v2i32, IntOp, Commutable>;
1584 // 128-bit vector types.
1585 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, itinQ16,
1586 OpcodeStr, !strconcat(Dt, "16"),
1587 v8i16, v8i16, IntOp, Commutable>;
1588 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, itinQ32,
1589 OpcodeStr, !strconcat(Dt, "32"),
1590 v4i32, v4i32, IntOp, Commutable>;
1593 multiclass N3VIntSL_HS<bits<4> op11_8,
1594 InstrItinClass itinD16, InstrItinClass itinD32,
1595 InstrItinClass itinQ16, InstrItinClass itinQ32,
1596 string OpcodeStr, string Dt, Intrinsic IntOp> {
1597 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
1598 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
1599 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
1600 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
1601 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
1602 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
1603 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
1604 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
1607 // ....then also with element size of 8 bits:
1608 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1609 InstrItinClass itinD16, InstrItinClass itinD32,
1610 InstrItinClass itinQ16, InstrItinClass itinQ32,
1611 string OpcodeStr, string Dt,
1612 Intrinsic IntOp, bit Commutable = 0>
1613 : N3VInt_HS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
1614 OpcodeStr, Dt, IntOp, Commutable> {
1615 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, itinD16,
1616 OpcodeStr, !strconcat(Dt, "8"),
1617 v8i8, v8i8, IntOp, Commutable>;
1618 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, itinQ16,
1619 OpcodeStr, !strconcat(Dt, "8"),
1620 v16i8, v16i8, IntOp, Commutable>;
1623 // ....then also with element size of 64 bits:
1624 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1625 InstrItinClass itinD16, InstrItinClass itinD32,
1626 InstrItinClass itinQ16, InstrItinClass itinQ32,
1627 string OpcodeStr, string Dt,
1628 Intrinsic IntOp, bit Commutable = 0>
1629 : N3VInt_QHS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
1630 OpcodeStr, Dt, IntOp, Commutable> {
1631 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, itinD32,
1632 OpcodeStr, !strconcat(Dt, "64"),
1633 v1i64, v1i64, IntOp, Commutable>;
1634 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, itinQ32,
1635 OpcodeStr, !strconcat(Dt, "64"),
1636 v2i64, v2i64, IntOp, Commutable>;
1640 // Neon Narrowing 3-register vector intrinsics,
1641 // source operand element sizes of 16, 32 and 64 bits:
1642 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1643 string OpcodeStr, string Dt,
1644 Intrinsic IntOp, bit Commutable = 0> {
1645 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
1646 OpcodeStr, !strconcat(Dt, "16"),
1647 v8i8, v8i16, IntOp, Commutable>;
1648 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
1649 OpcodeStr, !strconcat(Dt, "32"),
1650 v4i16, v4i32, IntOp, Commutable>;
1651 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
1652 OpcodeStr, !strconcat(Dt, "64"),
1653 v2i32, v2i64, IntOp, Commutable>;
1657 // Neon Long 3-register vector intrinsics.
1659 // First with only element sizes of 16 and 32 bits:
1660 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1661 InstrItinClass itin, string OpcodeStr, string Dt,
1662 Intrinsic IntOp, bit Commutable = 0> {
1663 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin,
1664 OpcodeStr, !strconcat(Dt, "16"),
1665 v4i32, v4i16, IntOp, Commutable>;
1666 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin,
1667 OpcodeStr, !strconcat(Dt, "32"),
1668 v2i64, v2i32, IntOp, Commutable>;
1671 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
1672 InstrItinClass itin, string OpcodeStr, string Dt,
1674 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
1675 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1676 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
1677 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1680 // ....then also with element size of 8 bits:
1681 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1682 InstrItinClass itin, string OpcodeStr, string Dt,
1683 Intrinsic IntOp, bit Commutable = 0>
1684 : N3VLInt_HS<op24, op23, op11_8, op4, itin, OpcodeStr, Dt,
1685 IntOp, Commutable> {
1686 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin,
1687 OpcodeStr, !strconcat(Dt, "8"),
1688 v8i16, v8i8, IntOp, Commutable>;
1692 // Neon Wide 3-register vector intrinsics,
1693 // source operand element sizes of 8, 16 and 32 bits:
1694 multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1695 string OpcodeStr, string Dt,
1696 Intrinsic IntOp, bit Commutable = 0> {
1697 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4,
1698 OpcodeStr, !strconcat(Dt, "8"),
1699 v8i16, v8i8, IntOp, Commutable>;
1700 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4,
1701 OpcodeStr, !strconcat(Dt, "16"),
1702 v4i32, v4i16, IntOp, Commutable>;
1703 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4,
1704 OpcodeStr, !strconcat(Dt, "32"),
1705 v2i64, v2i32, IntOp, Commutable>;
1709 // Neon Multiply-Op vector operations,
1710 // element sizes of 8, 16 and 32 bits:
1711 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1712 InstrItinClass itinD16, InstrItinClass itinD32,
1713 InstrItinClass itinQ16, InstrItinClass itinQ32,
1714 string OpcodeStr, string Dt, SDNode OpNode> {
1715 // 64-bit vector types.
1716 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
1717 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
1718 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
1719 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
1720 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
1721 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
1723 // 128-bit vector types.
1724 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
1725 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
1726 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
1727 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
1728 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
1729 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
1732 multiclass N3VMulOpSL_HS<bits<4> op11_8,
1733 InstrItinClass itinD16, InstrItinClass itinD32,
1734 InstrItinClass itinQ16, InstrItinClass itinQ32,
1735 string OpcodeStr, string Dt, SDNode ShOp> {
1736 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
1737 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
1738 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
1739 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
1740 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
1741 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
1743 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
1744 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
1748 // Neon 3-argument intrinsics,
1749 // element sizes of 8, 16 and 32 bits:
1750 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1751 string OpcodeStr, string Dt, Intrinsic IntOp> {
1752 // 64-bit vector types.
1753 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16D,
1754 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
1755 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
1756 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
1757 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32D,
1758 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
1760 // 128-bit vector types.
1761 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16Q,
1762 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
1763 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16Q,
1764 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
1765 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32Q,
1766 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
1770 // Neon Long 3-argument intrinsics.
1772 // First with only element sizes of 16 and 32 bits:
1773 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1774 string OpcodeStr, string Dt, Intrinsic IntOp> {
1775 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
1776 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1777 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi16D,
1778 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1781 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
1782 string OpcodeStr, string Dt, Intrinsic IntOp> {
1783 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
1784 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
1785 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
1786 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1789 // ....then also with element size of 8 bits:
1790 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1791 string OpcodeStr, string Dt, Intrinsic IntOp>
1792 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, Dt, IntOp> {
1793 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16D,
1794 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
1798 // Neon 2-register vector intrinsics,
1799 // element sizes of 8, 16 and 32 bits:
1800 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1801 bits<5> op11_7, bit op4,
1802 InstrItinClass itinD, InstrItinClass itinQ,
1803 string OpcodeStr, string Dt, Intrinsic IntOp> {
1804 // 64-bit vector types.
1805 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1806 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
1807 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1808 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
1809 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1810 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
1812 // 128-bit vector types.
1813 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1814 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
1815 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1816 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
1817 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1818 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
1822 // Neon Pairwise long 2-register intrinsics,
1823 // element sizes of 8, 16 and 32 bits:
1824 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1825 bits<5> op11_7, bit op4,
1826 string OpcodeStr, string Dt, Intrinsic IntOp> {
1827 // 64-bit vector types.
1828 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1829 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
1830 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1831 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
1832 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1833 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
1835 // 128-bit vector types.
1836 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1837 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
1838 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1839 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
1840 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1841 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
1845 // Neon Pairwise long 2-register accumulate intrinsics,
1846 // element sizes of 8, 16 and 32 bits:
1847 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1848 bits<5> op11_7, bit op4,
1849 string OpcodeStr, string Dt, Intrinsic IntOp> {
1850 // 64-bit vector types.
1851 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1852 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
1853 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1854 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
1855 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1856 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
1858 // 128-bit vector types.
1859 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1860 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
1861 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1862 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
1863 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1864 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
1868 // Neon 2-register vector shift by immediate,
1869 // element sizes of 8, 16, 32 and 64 bits:
1870 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1871 InstrItinClass itin, string OpcodeStr, string Dt,
1873 // 64-bit vector types.
1874 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
1875 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
1876 let Inst{21-19} = 0b001; // imm6 = 001xxx
1878 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
1879 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
1880 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1882 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
1883 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
1884 let Inst{21} = 0b1; // imm6 = 1xxxxx
1886 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, itin,
1887 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
1890 // 128-bit vector types.
1891 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
1892 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
1893 let Inst{21-19} = 0b001; // imm6 = 001xxx
1895 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
1896 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
1897 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1899 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
1900 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
1901 let Inst{21} = 0b1; // imm6 = 1xxxxx
1903 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, itin,
1904 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
1909 // Neon Shift-Accumulate vector operations,
1910 // element sizes of 8, 16, 32 and 64 bits:
1911 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1912 string OpcodeStr, string Dt, SDNode ShOp> {
1913 // 64-bit vector types.
1914 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1915 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
1916 let Inst{21-19} = 0b001; // imm6 = 001xxx
1918 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1919 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
1920 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1922 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1923 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
1924 let Inst{21} = 0b1; // imm6 = 1xxxxx
1926 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4,
1927 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
1930 // 128-bit vector types.
1931 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1932 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
1933 let Inst{21-19} = 0b001; // imm6 = 001xxx
1935 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1936 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
1937 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1939 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1940 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
1941 let Inst{21} = 0b1; // imm6 = 1xxxxx
1943 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4,
1944 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
1949 // Neon Shift-Insert vector operations,
1950 // element sizes of 8, 16, 32 and 64 bits:
1951 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1952 string OpcodeStr, SDNode ShOp> {
1953 // 64-bit vector types.
1954 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4,
1955 OpcodeStr, "8", v8i8, ShOp> {
1956 let Inst{21-19} = 0b001; // imm6 = 001xxx
1958 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4,
1959 OpcodeStr, "16", v4i16, ShOp> {
1960 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1962 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4,
1963 OpcodeStr, "32", v2i32, ShOp> {
1964 let Inst{21} = 0b1; // imm6 = 1xxxxx
1966 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4,
1967 OpcodeStr, "64", v1i64, ShOp>;
1970 // 128-bit vector types.
1971 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4,
1972 OpcodeStr, "8", v16i8, ShOp> {
1973 let Inst{21-19} = 0b001; // imm6 = 001xxx
1975 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4,
1976 OpcodeStr, "16", v8i16, ShOp> {
1977 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1979 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4,
1980 OpcodeStr, "32", v4i32, ShOp> {
1981 let Inst{21} = 0b1; // imm6 = 1xxxxx
1983 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4,
1984 OpcodeStr, "64", v2i64, ShOp>;
1988 // Neon Shift Long operations,
1989 // element sizes of 8, 16, 32 bits:
1990 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
1991 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
1992 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1993 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
1994 let Inst{21-19} = 0b001; // imm6 = 001xxx
1996 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1997 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
1998 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2000 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
2001 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
2002 let Inst{21} = 0b1; // imm6 = 1xxxxx
2006 // Neon Shift Narrow operations,
2007 // element sizes of 16, 32, 64 bits:
2008 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
2009 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
2011 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
2012 OpcodeStr, !strconcat(Dt, "16"), v8i8, v8i16, OpNode> {
2013 let Inst{21-19} = 0b001; // imm6 = 001xxx
2015 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
2016 OpcodeStr, !strconcat(Dt, "32"), v4i16, v4i32, OpNode> {
2017 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2019 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
2020 OpcodeStr, !strconcat(Dt, "64"), v2i32, v2i64, OpNode> {
2021 let Inst{21} = 0b1; // imm6 = 1xxxxx
2025 //===----------------------------------------------------------------------===//
2026 // Instruction Definitions.
2027 //===----------------------------------------------------------------------===//
2029 // Vector Add Operations.
2031 // VADD : Vector Add (integer and floating-point)
2032 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
2034 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
2035 v2f32, v2f32, fadd, 1>;
2036 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
2037 v4f32, v4f32, fadd, 1>;
2038 // VADDL : Vector Add Long (Q = D + D)
2039 defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, IIC_VSHLiD, "vaddl", "s",
2040 int_arm_neon_vaddls, 1>;
2041 defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, IIC_VSHLiD, "vaddl", "u",
2042 int_arm_neon_vaddlu, 1>;
2043 // VADDW : Vector Add Wide (Q = Q + D)
2044 defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw", "s", int_arm_neon_vaddws, 0>;
2045 defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw", "u", int_arm_neon_vaddwu, 0>;
2046 // VHADD : Vector Halving Add
2047 defm VHADDs : N3VInt_QHS<0,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2048 IIC_VBINi4Q, "vhadd", "s", int_arm_neon_vhadds, 1>;
2049 defm VHADDu : N3VInt_QHS<1,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2050 IIC_VBINi4Q, "vhadd", "u", int_arm_neon_vhaddu, 1>;
2051 // VRHADD : Vector Rounding Halving Add
2052 defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2053 IIC_VBINi4Q, "vrhadd", "s", int_arm_neon_vrhadds, 1>;
2054 defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2055 IIC_VBINi4Q, "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
2056 // VQADD : Vector Saturating Add
2057 defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2058 IIC_VBINi4Q, "vqadd", "s", int_arm_neon_vqadds, 1>;
2059 defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2060 IIC_VBINi4Q, "vqadd", "u", int_arm_neon_vqaddu, 1>;
2061 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
2062 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
2063 int_arm_neon_vaddhn, 1>;
2064 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
2065 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
2066 int_arm_neon_vraddhn, 1>;
2068 // Vector Multiply Operations.
2070 // VMUL : Vector Multiply (integer, polynomial and floating-point)
2071 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
2072 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
2073 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16D, "vmul", "p8",
2074 v8i8, v8i8, int_arm_neon_vmulp, 1>;
2075 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16Q, "vmul", "p8",
2076 v16i8, v16i8, int_arm_neon_vmulp, 1>;
2077 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VBIND, "vmul", "f32",
2078 v2f32, v2f32, fmul, 1>;
2079 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VBINQ, "vmul", "f32",
2080 v4f32, v4f32, fmul, 1>;
2081 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
2082 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
2083 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
2086 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
2087 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
2088 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
2089 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2090 (DSubReg_i16_reg imm:$lane))),
2091 (SubReg_i16_lane imm:$lane)))>;
2092 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
2093 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
2094 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
2095 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2096 (DSubReg_i32_reg imm:$lane))),
2097 (SubReg_i32_lane imm:$lane)))>;
2098 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
2099 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
2100 (v4f32 (VMULslfq (v4f32 QPR:$src1),
2101 (v2f32 (EXTRACT_SUBREG QPR:$src2,
2102 (DSubReg_i32_reg imm:$lane))),
2103 (SubReg_i32_lane imm:$lane)))>;
2105 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
2106 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
2107 IIC_VMULi16Q, IIC_VMULi32Q,
2108 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
2109 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
2110 IIC_VMULi16Q, IIC_VMULi32Q,
2111 "vqdmulh", "s", int_arm_neon_vqdmulh>;
2112 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
2113 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
2115 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
2116 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2117 (DSubReg_i16_reg imm:$lane))),
2118 (SubReg_i16_lane imm:$lane)))>;
2119 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
2120 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
2122 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
2123 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2124 (DSubReg_i32_reg imm:$lane))),
2125 (SubReg_i32_lane imm:$lane)))>;
2127 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
2128 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
2129 IIC_VMULi16Q, IIC_VMULi32Q,
2130 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
2131 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
2132 IIC_VMULi16Q, IIC_VMULi32Q,
2133 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
2134 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
2135 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
2137 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
2138 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2139 (DSubReg_i16_reg imm:$lane))),
2140 (SubReg_i16_lane imm:$lane)))>;
2141 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
2142 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
2144 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
2145 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2146 (DSubReg_i32_reg imm:$lane))),
2147 (SubReg_i32_lane imm:$lane)))>;
2149 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
2150 defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, IIC_VMULi16D, "vmull", "s",
2151 int_arm_neon_vmulls, 1>;
2152 defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, IIC_VMULi16D, "vmull", "u",
2153 int_arm_neon_vmullu, 1>;
2154 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
2155 v8i16, v8i8, int_arm_neon_vmullp, 1>;
2156 defm VMULLsls : N3VLIntSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s",
2157 int_arm_neon_vmulls>;
2158 defm VMULLslu : N3VLIntSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u",
2159 int_arm_neon_vmullu>;
2161 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
2162 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, "vqdmull", "s",
2163 int_arm_neon_vqdmull, 1>;
2164 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D, "vqdmull", "s",
2165 int_arm_neon_vqdmull>;
2167 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
2169 // VMLA : Vector Multiply Accumulate (integer and floating-point)
2170 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
2171 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
2172 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
2174 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
2176 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
2177 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
2178 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
2180 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
2181 v4f32, v2f32, fmul, fadd>;
2183 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
2184 (mul (v8i16 QPR:$src2),
2185 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
2186 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
2187 (v4i16 (EXTRACT_SUBREG QPR:$src3,
2188 (DSubReg_i16_reg imm:$lane))),
2189 (SubReg_i16_lane imm:$lane)))>;
2191 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
2192 (mul (v4i32 QPR:$src2),
2193 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
2194 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
2195 (v2i32 (EXTRACT_SUBREG QPR:$src3,
2196 (DSubReg_i32_reg imm:$lane))),
2197 (SubReg_i32_lane imm:$lane)))>;
2199 def : Pat<(v4f32 (fadd (v4f32 QPR:$src1),
2200 (fmul (v4f32 QPR:$src2),
2201 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
2202 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
2204 (v2f32 (EXTRACT_SUBREG QPR:$src3,
2205 (DSubReg_i32_reg imm:$lane))),
2206 (SubReg_i32_lane imm:$lane)))>;
2208 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
2209 defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal", "s", int_arm_neon_vmlals>;
2210 defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal", "u", int_arm_neon_vmlalu>;
2212 defm VMLALsls : N3VLInt3SL_HS<0, 0b0010, "vmlal", "s", int_arm_neon_vmlals>;
2213 defm VMLALslu : N3VLInt3SL_HS<1, 0b0010, "vmlal", "u", int_arm_neon_vmlalu>;
2215 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
2216 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal", "s",
2217 int_arm_neon_vqdmlal>;
2218 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
2220 // VMLS : Vector Multiply Subtract (integer and floating-point)
2221 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
2222 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
2223 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
2225 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
2227 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
2228 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
2229 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
2231 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
2232 v4f32, v2f32, fmul, fsub>;
2234 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
2235 (mul (v8i16 QPR:$src2),
2236 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
2237 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
2238 (v4i16 (EXTRACT_SUBREG QPR:$src3,
2239 (DSubReg_i16_reg imm:$lane))),
2240 (SubReg_i16_lane imm:$lane)))>;
2242 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
2243 (mul (v4i32 QPR:$src2),
2244 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
2245 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
2246 (v2i32 (EXTRACT_SUBREG QPR:$src3,
2247 (DSubReg_i32_reg imm:$lane))),
2248 (SubReg_i32_lane imm:$lane)))>;
2250 def : Pat<(v4f32 (fsub (v4f32 QPR:$src1),
2251 (fmul (v4f32 QPR:$src2),
2252 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
2253 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
2254 (v2f32 (EXTRACT_SUBREG QPR:$src3,
2255 (DSubReg_i32_reg imm:$lane))),
2256 (SubReg_i32_lane imm:$lane)))>;
2258 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
2259 defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl", "s", int_arm_neon_vmlsls>;
2260 defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl", "u", int_arm_neon_vmlslu>;
2262 defm VMLSLsls : N3VLInt3SL_HS<0, 0b0110, "vmlsl", "s", int_arm_neon_vmlsls>;
2263 defm VMLSLslu : N3VLInt3SL_HS<1, 0b0110, "vmlsl", "u", int_arm_neon_vmlslu>;
2265 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
2266 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl", "s",
2267 int_arm_neon_vqdmlsl>;
2268 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
2270 // Vector Subtract Operations.
2272 // VSUB : Vector Subtract (integer and floating-point)
2273 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
2274 "vsub", "i", sub, 0>;
2275 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
2276 v2f32, v2f32, fsub, 0>;
2277 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
2278 v4f32, v4f32, fsub, 0>;
2279 // VSUBL : Vector Subtract Long (Q = D - D)
2280 defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, IIC_VSHLiD, "vsubl", "s",
2281 int_arm_neon_vsubls, 1>;
2282 defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, IIC_VSHLiD, "vsubl", "u",
2283 int_arm_neon_vsublu, 1>;
2284 // VSUBW : Vector Subtract Wide (Q = Q - D)
2285 defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw", "s", int_arm_neon_vsubws, 0>;
2286 defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw", "u", int_arm_neon_vsubwu, 0>;
2287 // VHSUB : Vector Halving Subtract
2288 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D,
2289 IIC_VBINi4Q, IIC_VBINi4Q,
2290 "vhsub", "s", int_arm_neon_vhsubs, 0>;
2291 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D,
2292 IIC_VBINi4Q, IIC_VBINi4Q,
2293 "vhsub", "u", int_arm_neon_vhsubu, 0>;
2294 // VQSUB : Vector Saturing Subtract
2295 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D,
2296 IIC_VBINi4Q, IIC_VBINi4Q,
2297 "vqsub", "s", int_arm_neon_vqsubs, 0>;
2298 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D,
2299 IIC_VBINi4Q, IIC_VBINi4Q,
2300 "vqsub", "u", int_arm_neon_vqsubu, 0>;
2301 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
2302 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
2303 int_arm_neon_vsubhn, 0>;
2304 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
2305 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
2306 int_arm_neon_vrsubhn, 0>;
2308 // Vector Comparisons.
2310 // VCEQ : Vector Compare Equal
2311 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2312 IIC_VBINi4Q, "vceq", "i", NEONvceq, 1>;
2313 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
2315 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
2317 // For disassembly only.
2318 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
2321 // VCGE : Vector Compare Greater Than or Equal
2322 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2323 IIC_VBINi4Q, "vcge", "s", NEONvcge, 0>;
2324 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2325 IIC_VBINi4Q, "vcge", "u", NEONvcgeu, 0>;
2326 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32",
2327 v2i32, v2f32, NEONvcge, 0>;
2328 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
2330 // For disassembly only.
2331 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
2333 // For disassembly only.
2334 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
2337 // VCGT : Vector Compare Greater Than
2338 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2339 IIC_VBINi4Q, "vcgt", "s", NEONvcgt, 0>;
2340 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2341 IIC_VBINi4Q, "vcgt", "u", NEONvcgtu, 0>;
2342 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
2344 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
2346 // For disassembly only.
2347 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
2349 // For disassembly only.
2350 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
2353 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
2354 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, IIC_VBIND, "vacge", "f32",
2355 v2i32, v2f32, int_arm_neon_vacged, 0>;
2356 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, IIC_VBINQ, "vacge", "f32",
2357 v4i32, v4f32, int_arm_neon_vacgeq, 0>;
2358 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
2359 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, IIC_VBIND, "vacgt", "f32",
2360 v2i32, v2f32, int_arm_neon_vacgtd, 0>;
2361 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, IIC_VBINQ, "vacgt", "f32",
2362 v4i32, v4f32, int_arm_neon_vacgtq, 0>;
2363 // VTST : Vector Test Bits
2364 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2365 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
2367 // Vector Bitwise Operations.
2369 // VAND : Vector Bitwise AND
2370 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
2371 v2i32, v2i32, and, 1>;
2372 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
2373 v4i32, v4i32, and, 1>;
2375 // VEOR : Vector Bitwise Exclusive OR
2376 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
2377 v2i32, v2i32, xor, 1>;
2378 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
2379 v4i32, v4i32, xor, 1>;
2381 // VORR : Vector Bitwise OR
2382 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
2383 v2i32, v2i32, or, 1>;
2384 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
2385 v4i32, v4i32, or, 1>;
2387 // VBIC : Vector Bitwise Bit Clear (AND NOT)
2388 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2389 (ins DPR:$src1, DPR:$src2), IIC_VBINiD,
2390 "vbic", "$dst, $src1, $src2", "",
2391 [(set DPR:$dst, (v2i32 (and DPR:$src1,
2392 (vnot_conv DPR:$src2))))]>;
2393 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2394 (ins QPR:$src1, QPR:$src2), IIC_VBINiQ,
2395 "vbic", "$dst, $src1, $src2", "",
2396 [(set QPR:$dst, (v4i32 (and QPR:$src1,
2397 (vnot_conv QPR:$src2))))]>;
2399 // VORN : Vector Bitwise OR NOT
2400 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
2401 (ins DPR:$src1, DPR:$src2), IIC_VBINiD,
2402 "vorn", "$dst, $src1, $src2", "",
2403 [(set DPR:$dst, (v2i32 (or DPR:$src1,
2404 (vnot_conv DPR:$src2))))]>;
2405 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
2406 (ins QPR:$src1, QPR:$src2), IIC_VBINiQ,
2407 "vorn", "$dst, $src1, $src2", "",
2408 [(set QPR:$dst, (v4i32 (or QPR:$src1,
2409 (vnot_conv QPR:$src2))))]>;
2411 // VMVN : Vector Bitwise NOT
2412 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
2413 (outs DPR:$dst), (ins DPR:$src), IIC_VSHLiD,
2414 "vmvn", "$dst, $src", "",
2415 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>;
2416 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
2417 (outs QPR:$dst), (ins QPR:$src), IIC_VSHLiD,
2418 "vmvn", "$dst, $src", "",
2419 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>;
2420 def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>;
2421 def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>;
2423 // VBSL : Vector Bitwise Select
2424 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2425 (ins DPR:$src1, DPR:$src2, DPR:$src3), IIC_VCNTiD,
2426 "vbsl", "$dst, $src2, $src3", "$src1 = $dst",
2428 (v2i32 (or (and DPR:$src2, DPR:$src1),
2429 (and DPR:$src3, (vnot_conv DPR:$src1)))))]>;
2430 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2431 (ins QPR:$src1, QPR:$src2, QPR:$src3), IIC_VCNTiQ,
2432 "vbsl", "$dst, $src2, $src3", "$src1 = $dst",
2434 (v4i32 (or (and QPR:$src2, QPR:$src1),
2435 (and QPR:$src3, (vnot_conv QPR:$src1)))))]>;
2437 // VBIF : Vector Bitwise Insert if False
2438 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
2439 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
2440 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
2441 IIC_VBINiD, "vbif", "$dst, $src2, $src3", "$src1 = $dst",
2442 [/* For disassembly only; pattern left blank */]>;
2443 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
2444 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
2445 IIC_VBINiQ, "vbif", "$dst, $src2, $src3", "$src1 = $dst",
2446 [/* For disassembly only; pattern left blank */]>;
2448 // VBIT : Vector Bitwise Insert if True
2449 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
2450 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
2451 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
2452 IIC_VBINiD, "vbit", "$dst, $src2, $src3", "$src1 = $dst",
2453 [/* For disassembly only; pattern left blank */]>;
2454 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
2455 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
2456 IIC_VBINiQ, "vbit", "$dst, $src2, $src3", "$src1 = $dst",
2457 [/* For disassembly only; pattern left blank */]>;
2459 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
2460 // for equivalent operations with different register constraints; it just
2463 // Vector Absolute Differences.
2465 // VABD : Vector Absolute Difference
2466 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D,
2467 IIC_VBINi4Q, IIC_VBINi4Q,
2468 "vabd", "s", int_arm_neon_vabds, 0>;
2469 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D,
2470 IIC_VBINi4Q, IIC_VBINi4Q,
2471 "vabd", "u", int_arm_neon_vabdu, 0>;
2472 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, IIC_VBIND,
2473 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 0>;
2474 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, IIC_VBINQ,
2475 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 0>;
2477 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
2478 defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, IIC_VBINi4Q,
2479 "vabdl", "s", int_arm_neon_vabdls, 0>;
2480 defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, IIC_VBINi4Q,
2481 "vabdl", "u", int_arm_neon_vabdlu, 0>;
2483 // VABA : Vector Absolute Difference and Accumulate
2484 defm VABAs : N3VInt3_QHS<0,0,0b0111,1, "vaba", "s", int_arm_neon_vabas>;
2485 defm VABAu : N3VInt3_QHS<1,0,0b0111,1, "vaba", "u", int_arm_neon_vabau>;
2487 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
2488 defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal", "s", int_arm_neon_vabals>;
2489 defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal", "u", int_arm_neon_vabalu>;
2491 // Vector Maximum and Minimum.
2493 // VMAX : Vector Maximum
2494 defm VMAXs : N3VInt_QHS<0,0,0b0110,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2495 IIC_VBINi4Q, "vmax", "s", int_arm_neon_vmaxs, 1>;
2496 defm VMAXu : N3VInt_QHS<1,0,0b0110,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2497 IIC_VBINi4Q, "vmax", "u", int_arm_neon_vmaxu, 1>;
2498 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, IIC_VBIND, "vmax", "f32",
2499 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
2500 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, IIC_VBINQ, "vmax", "f32",
2501 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
2503 // VMIN : Vector Minimum
2504 defm VMINs : N3VInt_QHS<0,0,0b0110,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2505 IIC_VBINi4Q, "vmin", "s", int_arm_neon_vmins, 1>;
2506 defm VMINu : N3VInt_QHS<1,0,0b0110,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2507 IIC_VBINi4Q, "vmin", "u", int_arm_neon_vminu, 1>;
2508 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, IIC_VBIND, "vmin", "f32",
2509 v2f32, v2f32, int_arm_neon_vmins, 1>;
2510 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, IIC_VBINQ, "vmin", "f32",
2511 v4f32, v4f32, int_arm_neon_vmins, 1>;
2513 // Vector Pairwise Operations.
2515 // VPADD : Vector Pairwise Add
2516 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, IIC_VBINiD, "vpadd", "i8",
2517 v8i8, v8i8, int_arm_neon_vpadd, 0>;
2518 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, IIC_VBINiD, "vpadd", "i16",
2519 v4i16, v4i16, int_arm_neon_vpadd, 0>;
2520 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, IIC_VBINiD, "vpadd", "i32",
2521 v2i32, v2i32, int_arm_neon_vpadd, 0>;
2522 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, IIC_VBIND, "vpadd", "f32",
2523 v2f32, v2f32, int_arm_neon_vpadd, 0>;
2525 // VPADDL : Vector Pairwise Add Long
2526 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
2527 int_arm_neon_vpaddls>;
2528 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
2529 int_arm_neon_vpaddlu>;
2531 // VPADAL : Vector Pairwise Add and Accumulate Long
2532 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
2533 int_arm_neon_vpadals>;
2534 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
2535 int_arm_neon_vpadalu>;
2537 // VPMAX : Vector Pairwise Maximum
2538 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax", "s8",
2539 v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
2540 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax", "s16",
2541 v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
2542 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax", "s32",
2543 v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
2544 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax", "u8",
2545 v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
2546 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax", "u16",
2547 v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
2548 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax", "u32",
2549 v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
2550 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, IIC_VBINi4D, "vpmax", "f32",
2551 v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
2553 // VPMIN : Vector Pairwise Minimum
2554 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin", "s8",
2555 v8i8, v8i8, int_arm_neon_vpmins, 0>;
2556 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin", "s16",
2557 v4i16, v4i16, int_arm_neon_vpmins, 0>;
2558 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin", "s32",
2559 v2i32, v2i32, int_arm_neon_vpmins, 0>;
2560 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin", "u8",
2561 v8i8, v8i8, int_arm_neon_vpminu, 0>;
2562 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin", "u16",
2563 v4i16, v4i16, int_arm_neon_vpminu, 0>;
2564 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin", "u32",
2565 v2i32, v2i32, int_arm_neon_vpminu, 0>;
2566 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, IIC_VBINi4D, "vpmin", "f32",
2567 v2f32, v2f32, int_arm_neon_vpmins, 0>;
2569 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
2571 // VRECPE : Vector Reciprocal Estimate
2572 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
2573 IIC_VUNAD, "vrecpe", "u32",
2574 v2i32, v2i32, int_arm_neon_vrecpe>;
2575 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
2576 IIC_VUNAQ, "vrecpe", "u32",
2577 v4i32, v4i32, int_arm_neon_vrecpe>;
2578 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
2579 IIC_VUNAD, "vrecpe", "f32",
2580 v2f32, v2f32, int_arm_neon_vrecpe>;
2581 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
2582 IIC_VUNAQ, "vrecpe", "f32",
2583 v4f32, v4f32, int_arm_neon_vrecpe>;
2585 // VRECPS : Vector Reciprocal Step
2586 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1,
2587 IIC_VRECSD, "vrecps", "f32",
2588 v2f32, v2f32, int_arm_neon_vrecps, 1>;
2589 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1,
2590 IIC_VRECSQ, "vrecps", "f32",
2591 v4f32, v4f32, int_arm_neon_vrecps, 1>;
2593 // VRSQRTE : Vector Reciprocal Square Root Estimate
2594 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
2595 IIC_VUNAD, "vrsqrte", "u32",
2596 v2i32, v2i32, int_arm_neon_vrsqrte>;
2597 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
2598 IIC_VUNAQ, "vrsqrte", "u32",
2599 v4i32, v4i32, int_arm_neon_vrsqrte>;
2600 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
2601 IIC_VUNAD, "vrsqrte", "f32",
2602 v2f32, v2f32, int_arm_neon_vrsqrte>;
2603 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
2604 IIC_VUNAQ, "vrsqrte", "f32",
2605 v4f32, v4f32, int_arm_neon_vrsqrte>;
2607 // VRSQRTS : Vector Reciprocal Square Root Step
2608 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1,
2609 IIC_VRECSD, "vrsqrts", "f32",
2610 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
2611 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1,
2612 IIC_VRECSQ, "vrsqrts", "f32",
2613 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
2617 // VSHL : Vector Shift
2618 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
2619 IIC_VSHLiQ, "vshl", "s", int_arm_neon_vshifts, 0>;
2620 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
2621 IIC_VSHLiQ, "vshl", "u", int_arm_neon_vshiftu, 0>;
2622 // VSHL : Vector Shift Left (Immediate)
2623 defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
2624 // VSHR : Vector Shift Right (Immediate)
2625 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", NEONvshrs>;
2626 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", NEONvshru>;
2628 // VSHLL : Vector Shift Left Long
2629 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
2630 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
2632 // VSHLL : Vector Shift Left Long (with maximum shift count)
2633 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
2634 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
2635 ValueType OpTy, SDNode OpNode>
2636 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
2637 ResTy, OpTy, OpNode> {
2638 let Inst{21-16} = op21_16;
2640 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
2641 v8i16, v8i8, NEONvshlli>;
2642 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
2643 v4i32, v4i16, NEONvshlli>;
2644 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
2645 v2i64, v2i32, NEONvshlli>;
2647 // VSHRN : Vector Shift Right and Narrow
2648 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
2651 // VRSHL : Vector Rounding Shift
2652 defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2653 IIC_VSHLi4Q, "vrshl", "s", int_arm_neon_vrshifts,0>;
2654 defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2655 IIC_VSHLi4Q, "vrshl", "u", int_arm_neon_vrshiftu,0>;
2656 // VRSHR : Vector Rounding Shift Right
2657 defm VRSHRs : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs>;
2658 defm VRSHRu : N2VSh_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", NEONvrshru>;
2660 // VRSHRN : Vector Rounding Shift Right and Narrow
2661 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
2664 // VQSHL : Vector Saturating Shift
2665 defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2666 IIC_VSHLi4Q, "vqshl", "s", int_arm_neon_vqshifts,0>;
2667 defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2668 IIC_VSHLi4Q, "vqshl", "u", int_arm_neon_vqshiftu,0>;
2669 // VQSHL : Vector Saturating Shift Left (Immediate)
2670 defm VQSHLsi : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s", NEONvqshls>;
2671 defm VQSHLui : N2VSh_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u", NEONvqshlu>;
2672 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
2673 defm VQSHLsu : N2VSh_QHSD<1,1,0b0110,1, IIC_VSHLi4D, "vqshlu","s",NEONvqshlsu>;
2675 // VQSHRN : Vector Saturating Shift Right and Narrow
2676 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
2678 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
2681 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
2682 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
2685 // VQRSHL : Vector Saturating Rounding Shift
2686 defm VQRSHLs : N3VInt_QHSD<0,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2687 IIC_VSHLi4Q, "vqrshl", "s",
2688 int_arm_neon_vqrshifts, 0>;
2689 defm VQRSHLu : N3VInt_QHSD<1,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2690 IIC_VSHLi4Q, "vqrshl", "u",
2691 int_arm_neon_vqrshiftu, 0>;
2693 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
2694 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
2696 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
2699 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
2700 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
2703 // VSRA : Vector Shift Right and Accumulate
2704 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
2705 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
2706 // VRSRA : Vector Rounding Shift Right and Accumulate
2707 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
2708 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
2710 // VSLI : Vector Shift Left and Insert
2711 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli", NEONvsli>;
2712 // VSRI : Vector Shift Right and Insert
2713 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri", NEONvsri>;
2715 // Vector Absolute and Saturating Absolute.
2717 // VABS : Vector Absolute Value
2718 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
2719 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
2721 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2722 IIC_VUNAD, "vabs", "f32",
2723 v2f32, v2f32, int_arm_neon_vabs>;
2724 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2725 IIC_VUNAQ, "vabs", "f32",
2726 v4f32, v4f32, int_arm_neon_vabs>;
2728 // VQABS : Vector Saturating Absolute Value
2729 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
2730 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
2731 int_arm_neon_vqabs>;
2735 def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
2736 def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>;
2738 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
2739 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
2740 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
2741 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>;
2742 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
2743 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
2744 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
2745 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>;
2747 // VNEG : Vector Negate
2748 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
2749 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
2750 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
2751 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
2752 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
2753 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
2755 // VNEG : Vector Negate (floating-point)
2756 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
2757 (outs DPR:$dst), (ins DPR:$src), IIC_VUNAD,
2758 "vneg", "f32", "$dst, $src", "",
2759 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
2760 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
2761 (outs QPR:$dst), (ins QPR:$src), IIC_VUNAQ,
2762 "vneg", "f32", "$dst, $src", "",
2763 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
2765 def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
2766 def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
2767 def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>;
2768 def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>;
2769 def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>;
2770 def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>;
2772 // VQNEG : Vector Saturating Negate
2773 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
2774 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
2775 int_arm_neon_vqneg>;
2777 // Vector Bit Counting Operations.
2779 // VCLS : Vector Count Leading Sign Bits
2780 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
2781 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
2783 // VCLZ : Vector Count Leading Zeros
2784 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
2785 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
2787 // VCNT : Vector Count One Bits
2788 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2789 IIC_VCNTiD, "vcnt", "8",
2790 v8i8, v8i8, int_arm_neon_vcnt>;
2791 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2792 IIC_VCNTiQ, "vcnt", "8",
2793 v16i8, v16i8, int_arm_neon_vcnt>;
2795 // Vector Swap -- for disassembly only.
2796 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
2797 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
2798 "vswp", "$dst, $src", "", []>;
2799 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
2800 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
2801 "vswp", "$dst, $src", "", []>;
2803 // Vector Move Operations.
2805 // VMOV : Vector Move (Register)
2807 def VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
2808 IIC_VMOVD, "vmov", "$dst, $src", "", []>;
2809 def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
2810 IIC_VMOVD, "vmov", "$dst, $src", "", []>;
2812 // VMOV : Vector Move (Immediate)
2814 // VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
2815 def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
2816 return ARM::getVMOVImm(N, 1, *CurDAG);
2818 def vmovImm8 : PatLeaf<(build_vector), [{
2819 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
2822 // VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
2823 def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
2824 return ARM::getVMOVImm(N, 2, *CurDAG);
2826 def vmovImm16 : PatLeaf<(build_vector), [{
2827 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
2828 }], VMOV_get_imm16>;
2830 // VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
2831 def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
2832 return ARM::getVMOVImm(N, 4, *CurDAG);
2834 def vmovImm32 : PatLeaf<(build_vector), [{
2835 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
2836 }], VMOV_get_imm32>;
2838 // VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
2839 def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
2840 return ARM::getVMOVImm(N, 8, *CurDAG);
2842 def vmovImm64 : PatLeaf<(build_vector), [{
2843 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
2844 }], VMOV_get_imm64>;
2846 // Note: Some of the cmode bits in the following VMOV instructions need to
2847 // be encoded based on the immed values.
2849 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
2850 (ins h8imm:$SIMM), IIC_VMOVImm,
2851 "vmov", "i8", "$dst, $SIMM", "",
2852 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
2853 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
2854 (ins h8imm:$SIMM), IIC_VMOVImm,
2855 "vmov", "i8", "$dst, $SIMM", "",
2856 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
2858 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,?}, 0, 0, {?}, 1, (outs DPR:$dst),
2859 (ins h16imm:$SIMM), IIC_VMOVImm,
2860 "vmov", "i16", "$dst, $SIMM", "",
2861 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
2862 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,?}, 0, 1, {?}, 1, (outs QPR:$dst),
2863 (ins h16imm:$SIMM), IIC_VMOVImm,
2864 "vmov", "i16", "$dst, $SIMM", "",
2865 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
2867 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, {?}, 1, (outs DPR:$dst),
2868 (ins h32imm:$SIMM), IIC_VMOVImm,
2869 "vmov", "i32", "$dst, $SIMM", "",
2870 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
2871 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, {?}, 1, (outs QPR:$dst),
2872 (ins h32imm:$SIMM), IIC_VMOVImm,
2873 "vmov", "i32", "$dst, $SIMM", "",
2874 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
2876 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
2877 (ins h64imm:$SIMM), IIC_VMOVImm,
2878 "vmov", "i64", "$dst, $SIMM", "",
2879 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
2880 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
2881 (ins h64imm:$SIMM), IIC_VMOVImm,
2882 "vmov", "i64", "$dst, $SIMM", "",
2883 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
2885 // VMOV : Vector Get Lane (move scalar to ARM core register)
2887 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
2888 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2889 IIC_VMOVSI, "vmov", "s8", "$dst, $src[$lane]",
2890 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
2892 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
2893 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2894 IIC_VMOVSI, "vmov", "s16", "$dst, $src[$lane]",
2895 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
2897 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
2898 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2899 IIC_VMOVSI, "vmov", "u8", "$dst, $src[$lane]",
2900 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
2902 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
2903 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2904 IIC_VMOVSI, "vmov", "u16", "$dst, $src[$lane]",
2905 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
2907 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
2908 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2909 IIC_VMOVSI, "vmov", "32", "$dst, $src[$lane]",
2910 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
2912 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
2913 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
2914 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2915 (DSubReg_i8_reg imm:$lane))),
2916 (SubReg_i8_lane imm:$lane))>;
2917 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
2918 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2919 (DSubReg_i16_reg imm:$lane))),
2920 (SubReg_i16_lane imm:$lane))>;
2921 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
2922 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2923 (DSubReg_i8_reg imm:$lane))),
2924 (SubReg_i8_lane imm:$lane))>;
2925 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
2926 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2927 (DSubReg_i16_reg imm:$lane))),
2928 (SubReg_i16_lane imm:$lane))>;
2929 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
2930 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
2931 (DSubReg_i32_reg imm:$lane))),
2932 (SubReg_i32_lane imm:$lane))>;
2933 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
2934 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
2935 (SSubReg_f32_reg imm:$src2))>;
2936 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
2937 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
2938 (SSubReg_f32_reg imm:$src2))>;
2939 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
2940 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2941 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
2942 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2945 // VMOV : Vector Set Lane (move ARM core register to scalar)
2947 let Constraints = "$src1 = $dst" in {
2948 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$dst),
2949 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2950 IIC_VMOVISL, "vmov", "8", "$dst[$lane], $src2",
2951 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
2952 GPR:$src2, imm:$lane))]>;
2953 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$dst),
2954 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2955 IIC_VMOVISL, "vmov", "16", "$dst[$lane], $src2",
2956 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
2957 GPR:$src2, imm:$lane))]>;
2958 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$dst),
2959 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2960 IIC_VMOVISL, "vmov", "32", "$dst[$lane], $src2",
2961 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
2962 GPR:$src2, imm:$lane))]>;
2964 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
2965 (v16i8 (INSERT_SUBREG QPR:$src1,
2966 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
2967 (DSubReg_i8_reg imm:$lane))),
2968 GPR:$src2, (SubReg_i8_lane imm:$lane))),
2969 (DSubReg_i8_reg imm:$lane)))>;
2970 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
2971 (v8i16 (INSERT_SUBREG QPR:$src1,
2972 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
2973 (DSubReg_i16_reg imm:$lane))),
2974 GPR:$src2, (SubReg_i16_lane imm:$lane))),
2975 (DSubReg_i16_reg imm:$lane)))>;
2976 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
2977 (v4i32 (INSERT_SUBREG QPR:$src1,
2978 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
2979 (DSubReg_i32_reg imm:$lane))),
2980 GPR:$src2, (SubReg_i32_lane imm:$lane))),
2981 (DSubReg_i32_reg imm:$lane)))>;
2983 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
2984 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
2985 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
2986 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
2987 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
2988 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
2990 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
2991 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
2992 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
2993 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
2995 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
2996 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
2997 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
2998 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, arm_dsubreg_0)>;
2999 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
3000 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
3002 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
3003 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
3004 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
3005 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
3006 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
3007 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
3009 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
3010 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3011 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
3013 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
3014 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
3015 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
3017 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
3018 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3019 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
3022 // VDUP : Vector Duplicate (from ARM core register to all elements)
3024 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
3025 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
3026 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
3027 [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
3028 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
3029 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
3030 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
3031 [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
3033 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
3034 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
3035 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
3036 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
3037 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
3038 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
3040 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
3041 IIC_VMOVIS, "vdup", "32", "$dst, $src",
3042 [(set DPR:$dst, (v2f32 (NEONvdup
3043 (f32 (bitconvert GPR:$src)))))]>;
3044 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
3045 IIC_VMOVIS, "vdup", "32", "$dst, $src",
3046 [(set QPR:$dst, (v4f32 (NEONvdup
3047 (f32 (bitconvert GPR:$src)))))]>;
3049 // VDUP : Vector Duplicate Lane (from scalar to all elements)
3051 class VDUPLND<bits<2> op19_18, bits<2> op17_16,
3052 string OpcodeStr, string Dt, ValueType Ty>
3053 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
3054 (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
3055 OpcodeStr, Dt, "$dst, $src[$lane]", "",
3056 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
3058 class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, string Dt,
3059 ValueType ResTy, ValueType OpTy>
3060 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
3061 (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
3062 OpcodeStr, Dt, "$dst, $src[$lane]", "",
3063 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src), imm:$lane)))]>;
3065 // Inst{19-16} is partially specified depending on the element size.
3067 def VDUPLN8d : VDUPLND<{?,?}, {?,1}, "vdup", "8", v8i8>;
3068 def VDUPLN16d : VDUPLND<{?,?}, {1,0}, "vdup", "16", v4i16>;
3069 def VDUPLN32d : VDUPLND<{?,1}, {0,0}, "vdup", "32", v2i32>;
3070 def VDUPLNfd : VDUPLND<{?,1}, {0,0}, "vdup", "32", v2f32>;
3071 def VDUPLN8q : VDUPLNQ<{?,?}, {?,1}, "vdup", "8", v16i8, v8i8>;
3072 def VDUPLN16q : VDUPLNQ<{?,?}, {1,0}, "vdup", "16", v8i16, v4i16>;
3073 def VDUPLN32q : VDUPLNQ<{?,1}, {0,0}, "vdup", "32", v4i32, v2i32>;
3074 def VDUPLNfq : VDUPLNQ<{?,1}, {0,0}, "vdup", "32", v4f32, v2f32>;
3076 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
3077 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
3078 (DSubReg_i8_reg imm:$lane))),
3079 (SubReg_i8_lane imm:$lane)))>;
3080 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
3081 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
3082 (DSubReg_i16_reg imm:$lane))),
3083 (SubReg_i16_lane imm:$lane)))>;
3084 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
3085 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
3086 (DSubReg_i32_reg imm:$lane))),
3087 (SubReg_i32_lane imm:$lane)))>;
3088 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
3089 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
3090 (DSubReg_i32_reg imm:$lane))),
3091 (SubReg_i32_lane imm:$lane)))>;
3093 def VDUPfdf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 0, 0,
3094 (outs DPR:$dst), (ins SPR:$src),
3095 IIC_VMOVD, "vdup", "32", "$dst, ${src:lane}", "",
3096 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
3098 def VDUPfqf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 1, 0,
3099 (outs QPR:$dst), (ins SPR:$src),
3100 IIC_VMOVD, "vdup", "32", "$dst, ${src:lane}", "",
3101 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
3103 def : Pat<(v2i64 (NEONvduplane (v2i64 QPR:$src), imm:$lane)),
3104 (INSERT_SUBREG QPR:$src,
3105 (i64 (EXTRACT_SUBREG QPR:$src,
3106 (DSubReg_f64_reg imm:$lane))),
3107 (DSubReg_f64_other_reg imm:$lane))>;
3108 def : Pat<(v2f64 (NEONvduplane (v2f64 QPR:$src), imm:$lane)),
3109 (INSERT_SUBREG QPR:$src,
3110 (f64 (EXTRACT_SUBREG QPR:$src,
3111 (DSubReg_f64_reg imm:$lane))),
3112 (DSubReg_f64_other_reg imm:$lane))>;
3114 // VMOVN : Vector Narrowing Move
3115 defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVD,
3116 "vmovn", "i", int_arm_neon_vmovn>;
3117 // VQMOVN : Vector Saturating Narrowing Move
3118 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
3119 "vqmovn", "s", int_arm_neon_vqmovns>;
3120 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
3121 "vqmovn", "u", int_arm_neon_vqmovnu>;
3122 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
3123 "vqmovun", "s", int_arm_neon_vqmovnsu>;
3124 // VMOVL : Vector Lengthening Move
3125 defm VMOVLs : N2VLInt_QHS<0b01,0b10100,0,1, "vmovl", "s",
3126 int_arm_neon_vmovls>;
3127 defm VMOVLu : N2VLInt_QHS<0b11,0b10100,0,1, "vmovl", "u",
3128 int_arm_neon_vmovlu>;
3130 // Vector Conversions.
3132 // VCVT : Vector Convert Between Floating-Point and Integers
3133 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3134 v2i32, v2f32, fp_to_sint>;
3135 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3136 v2i32, v2f32, fp_to_uint>;
3137 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3138 v2f32, v2i32, sint_to_fp>;
3139 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3140 v2f32, v2i32, uint_to_fp>;
3142 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3143 v4i32, v4f32, fp_to_sint>;
3144 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3145 v4i32, v4f32, fp_to_uint>;
3146 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3147 v4f32, v4i32, sint_to_fp>;
3148 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3149 v4f32, v4i32, uint_to_fp>;
3151 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
3152 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
3153 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
3154 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
3155 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
3156 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
3157 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
3158 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
3159 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
3161 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
3162 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
3163 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
3164 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
3165 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
3166 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
3167 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
3168 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
3172 // VREV64 : Vector Reverse elements within 64-bit doublewords
3174 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3175 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
3176 (ins DPR:$src), IIC_VMOVD,
3177 OpcodeStr, Dt, "$dst, $src", "",
3178 [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
3179 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3180 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
3181 (ins QPR:$src), IIC_VMOVD,
3182 OpcodeStr, Dt, "$dst, $src", "",
3183 [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
3185 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
3186 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
3187 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
3188 def VREV64df : VREV64D<0b10, "vrev64", "32", v2f32>;
3190 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
3191 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
3192 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
3193 def VREV64qf : VREV64Q<0b10, "vrev64", "32", v4f32>;
3195 // VREV32 : Vector Reverse elements within 32-bit words
3197 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3198 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
3199 (ins DPR:$src), IIC_VMOVD,
3200 OpcodeStr, Dt, "$dst, $src", "",
3201 [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
3202 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3203 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
3204 (ins QPR:$src), IIC_VMOVD,
3205 OpcodeStr, Dt, "$dst, $src", "",
3206 [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
3208 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
3209 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
3211 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
3212 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
3214 // VREV16 : Vector Reverse elements within 16-bit halfwords
3216 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3217 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
3218 (ins DPR:$src), IIC_VMOVD,
3219 OpcodeStr, Dt, "$dst, $src", "",
3220 [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
3221 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3222 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
3223 (ins QPR:$src), IIC_VMOVD,
3224 OpcodeStr, Dt, "$dst, $src", "",
3225 [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
3227 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
3228 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
3230 // Other Vector Shuffles.
3232 // VEXT : Vector Extract
3234 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
3235 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$dst),
3236 (ins DPR:$lhs, DPR:$rhs, i32imm:$index), IIC_VEXTD,
3237 OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
3238 [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
3239 (Ty DPR:$rhs), imm:$index)))]>;
3241 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
3242 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$dst),
3243 (ins QPR:$lhs, QPR:$rhs, i32imm:$index), IIC_VEXTQ,
3244 OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
3245 [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
3246 (Ty QPR:$rhs), imm:$index)))]>;
3248 def VEXTd8 : VEXTd<"vext", "8", v8i8>;
3249 def VEXTd16 : VEXTd<"vext", "16", v4i16>;
3250 def VEXTd32 : VEXTd<"vext", "32", v2i32>;
3251 def VEXTdf : VEXTd<"vext", "32", v2f32>;
3253 def VEXTq8 : VEXTq<"vext", "8", v16i8>;
3254 def VEXTq16 : VEXTq<"vext", "16", v8i16>;
3255 def VEXTq32 : VEXTq<"vext", "32", v4i32>;
3256 def VEXTqf : VEXTq<"vext", "32", v4f32>;
3258 // VTRN : Vector Transpose
3260 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
3261 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
3262 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
3264 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
3265 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
3266 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
3268 // VUZP : Vector Unzip (Deinterleave)
3270 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
3271 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
3272 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
3274 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
3275 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
3276 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
3278 // VZIP : Vector Zip (Interleave)
3280 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
3281 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
3282 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
3284 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
3285 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
3286 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
3288 // Vector Table Lookup and Table Extension.
3290 // VTBL : Vector Table Lookup
3292 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
3293 (ins DPR:$tbl1, DPR:$src), IIC_VTB1,
3294 "vtbl", "8", "$dst, \\{$tbl1\\}, $src", "",
3295 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
3296 let hasExtraSrcRegAllocReq = 1 in {
3298 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
3299 (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTB2,
3300 "vtbl", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "",
3301 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl2
3302 DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
3304 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
3305 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTB3,
3306 "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src", "",
3307 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl3
3308 DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
3310 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
3311 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTB4,
3312 "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src", "",
3313 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl4 DPR:$tbl1, DPR:$tbl2,
3314 DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
3315 } // hasExtraSrcRegAllocReq = 1
3317 // VTBX : Vector Table Extension
3319 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
3320 (ins DPR:$orig, DPR:$tbl1, DPR:$src), IIC_VTBX1,
3321 "vtbx", "8", "$dst, \\{$tbl1\\}, $src", "$orig = $dst",
3322 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
3323 DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
3324 let hasExtraSrcRegAllocReq = 1 in {
3326 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
3327 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTBX2,
3328 "vtbx", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "$orig = $dst",
3329 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx2
3330 DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
3332 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
3333 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTBX3,
3334 "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src", "$orig = $dst",
3335 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx3 DPR:$orig, DPR:$tbl1,
3336 DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
3338 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
3339 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTBX4,
3340 "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src",
3342 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx4 DPR:$orig, DPR:$tbl1,
3343 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
3344 } // hasExtraSrcRegAllocReq = 1
3346 //===----------------------------------------------------------------------===//
3347 // NEON instructions for single-precision FP math
3348 //===----------------------------------------------------------------------===//
3350 class N2VSPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
3351 : NEONFPPat<(ResTy (OpNode SPR:$a)),
3352 (EXTRACT_SUBREG (OpTy (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)),
3353 SPR:$a, arm_ssubreg_0))),
3356 class N3VSPat<SDNode OpNode, NeonI Inst>
3357 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
3358 (EXTRACT_SUBREG (v2f32
3359 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3360 SPR:$a, arm_ssubreg_0),
3361 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3362 SPR:$b, arm_ssubreg_0))),
3365 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
3366 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
3367 (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3368 SPR:$acc, arm_ssubreg_0),
3369 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3370 SPR:$a, arm_ssubreg_0),
3371 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3372 SPR:$b, arm_ssubreg_0)),
3375 // These need separate instructions because they must use DPR_VFP2 register
3376 // class which have SPR sub-registers.
3378 // Vector Add Operations used for single-precision FP
3379 let neverHasSideEffects = 1 in
3380 def VADDfd_sfp : N3VS<0,0,0b00,0b1101,0, "vadd", "f32", v2f32, v2f32, fadd, 1>;
3381 def : N3VSPat<fadd, VADDfd_sfp>;
3383 // Vector Sub Operations used for single-precision FP
3384 let neverHasSideEffects = 1 in
3385 def VSUBfd_sfp : N3VS<0,0,0b10,0b1101,0, "vsub", "f32", v2f32, v2f32, fsub, 0>;
3386 def : N3VSPat<fsub, VSUBfd_sfp>;
3388 // Vector Multiply Operations used for single-precision FP
3389 let neverHasSideEffects = 1 in
3390 def VMULfd_sfp : N3VS<1,0,0b00,0b1101,1, "vmul", "f32", v2f32, v2f32, fmul, 1>;
3391 def : N3VSPat<fmul, VMULfd_sfp>;
3393 // Vector Multiply-Accumulate/Subtract used for single-precision FP
3394 // vml[as].f32 can cause 4-8 cycle stalls in following ASIMD instructions, so
3395 // we want to avoid them for now. e.g., alternating vmla/vadd instructions.
3397 //let neverHasSideEffects = 1 in
3398 //def VMLAfd_sfp : N3VSMulOp<0,0,0b00,0b1101,1, IIC_VMACD, "vmla", "f32",
3399 // v2f32, fmul, fadd>;
3400 //def : N3VSMulOpPat<fmul, fadd, VMLAfd_sfp>;
3402 //let neverHasSideEffects = 1 in
3403 //def VMLSfd_sfp : N3VSMulOp<0,0,0b10,0b1101,1, IIC_VMACD, "vmls", "f32",
3404 // v2f32, fmul, fsub>;
3405 //def : N3VSMulOpPat<fmul, fsub, VMLSfd_sfp>;
3407 // Vector Absolute used for single-precision FP
3408 let neverHasSideEffects = 1 in
3409 def VABSfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01110, 0, 0,
3410 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
3411 "vabs", "f32", "$dst, $src", "", []>;
3412 def : N2VSPat<fabs, f32, v2f32, VABSfd_sfp>;
3414 // Vector Negate used for single-precision FP
3415 let neverHasSideEffects = 1 in
3416 def VNEGfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
3417 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
3418 "vneg", "f32", "$dst, $src", "", []>;
3419 def : N2VSPat<fneg, f32, v2f32, VNEGfd_sfp>;
3421 // Vector Maximum used for single-precision FP
3422 let neverHasSideEffects = 1 in
3423 def VMAXfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
3424 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), IIC_VBIND,
3425 "vmax", "f32", "$dst, $src1, $src2", "", []>;
3426 def : N3VSPat<NEONfmax, VMAXfd_sfp>;
3428 // Vector Minimum used for single-precision FP
3429 let neverHasSideEffects = 1 in
3430 def VMINfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
3431 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), IIC_VBIND,
3432 "vmin", "f32", "$dst, $src1, $src2", "", []>;
3433 def : N3VSPat<NEONfmin, VMINfd_sfp>;
3435 // Vector Convert between single-precision FP and integer
3436 let neverHasSideEffects = 1 in
3437 def VCVTf2sd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3438 v2i32, v2f32, fp_to_sint>;
3439 def : N2VSPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
3441 let neverHasSideEffects = 1 in
3442 def VCVTf2ud_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3443 v2i32, v2f32, fp_to_uint>;
3444 def : N2VSPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
3446 let neverHasSideEffects = 1 in
3447 def VCVTs2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3448 v2f32, v2i32, sint_to_fp>;
3449 def : N2VSPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
3451 let neverHasSideEffects = 1 in
3452 def VCVTu2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3453 v2f32, v2i32, uint_to_fp>;
3454 def : N2VSPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
3456 //===----------------------------------------------------------------------===//
3457 // Non-Instruction Patterns
3458 //===----------------------------------------------------------------------===//
3461 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
3462 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
3463 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
3464 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
3465 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
3466 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
3467 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
3468 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
3469 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
3470 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
3471 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
3472 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
3473 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
3474 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
3475 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
3476 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
3477 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
3478 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
3479 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
3480 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
3481 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
3482 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
3483 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
3484 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
3485 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
3486 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
3487 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
3488 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
3489 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
3490 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
3492 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
3493 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
3494 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
3495 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
3496 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
3497 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
3498 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
3499 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
3500 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
3501 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
3502 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
3503 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
3504 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
3505 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
3506 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
3507 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
3508 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
3509 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
3510 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
3511 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
3512 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
3513 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
3514 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
3515 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
3516 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
3517 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
3518 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
3519 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
3520 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
3521 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;