1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
70 // VDUPLANE can produce a quad-register result from a double-register source,
71 // so the result is not constrained to match the source.
72 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
73 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
76 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
77 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
78 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
80 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
81 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
82 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
83 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
85 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
88 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
89 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
90 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
92 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
94 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
95 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
97 //===----------------------------------------------------------------------===//
98 // NEON operand definitions
99 //===----------------------------------------------------------------------===//
101 // addrmode_neonldstm := reg
103 /* TODO: Take advantage of vldm.
104 def addrmode_neonldstm : Operand<i32>,
105 ComplexPattern<i32, 2, "SelectAddrModeNeonLdStM", []> {
106 let PrintMethod = "printAddrNeonLdStMOperand";
107 let MIOperandInfo = (ops GPR, i32imm);
111 def h8imm : Operand<i8> {
112 let PrintMethod = "printHex8ImmOperand";
114 def h16imm : Operand<i16> {
115 let PrintMethod = "printHex16ImmOperand";
117 def h32imm : Operand<i32> {
118 let PrintMethod = "printHex32ImmOperand";
120 def h64imm : Operand<i64> {
121 let PrintMethod = "printHex64ImmOperand";
124 //===----------------------------------------------------------------------===//
125 // NEON load / store instructions
126 //===----------------------------------------------------------------------===//
128 /* TODO: Take advantage of vldm.
129 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
130 def VLDMD : NI<(outs),
131 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
132 IIC_fpLoadm, "vldm", "${addr:submode} ${addr:base}, $dst1", []> {
133 let Inst{27-25} = 0b110;
135 let Inst{11-9} = 0b101;
138 def VLDMS : NI<(outs),
139 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
140 IIC_fpLoadm, "vldm", "${addr:submode} ${addr:base}, $dst1", []> {
141 let Inst{27-25} = 0b110;
143 let Inst{11-9} = 0b101;
148 // Use vldmia to load a Q register as a D register pair.
149 def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr), IIC_fpLoadm,
150 "vldmia", "$addr, ${dst:dregpair}",
151 [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]> {
152 let Inst{27-25} = 0b110;
153 let Inst{24} = 0; // P bit
154 let Inst{23} = 1; // U bit
156 let Inst{11-8} = 0b1011;
159 // Use vstmia to store a Q register as a D register pair.
160 def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr), IIC_fpStorem,
161 "vstmia", "$addr, ${src:dregpair}",
162 [(store (v2f64 QPR:$src), addrmode4:$addr)]> {
163 let Inst{27-25} = 0b110;
164 let Inst{24} = 0; // P bit
165 let Inst{23} = 1; // U bit
167 let Inst{11-8} = 0b1011;
170 // VLD1 : Vector Load (multiple single elements)
171 class VLD1D<bits<4> op7_4, string OpcodeStr, string Dt,
172 ValueType Ty, Intrinsic IntOp>
173 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst), (ins addrmode6:$addr), IIC_VLD1,
174 OpcodeStr, Dt, "\\{$dst\\}, $addr", "",
175 [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
176 class VLD1Q<bits<4> op7_4, string OpcodeStr, string Dt,
177 ValueType Ty, Intrinsic IntOp>
178 : NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst), (ins addrmode6:$addr), IIC_VLD1,
179 OpcodeStr, Dt, "${dst:dregpair}, $addr", "",
180 [(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
182 def VLD1d8 : VLD1D<0b0000, "vld1", "8", v8i8, int_arm_neon_vld1>;
183 def VLD1d16 : VLD1D<0b0100, "vld1", "16", v4i16, int_arm_neon_vld1>;
184 def VLD1d32 : VLD1D<0b1000, "vld1", "32", v2i32, int_arm_neon_vld1>;
185 def VLD1df : VLD1D<0b1000, "vld1", "32", v2f32, int_arm_neon_vld1>;
186 def VLD1d64 : VLD1D<0b1100, "vld1", "64", v1i64, int_arm_neon_vld1>;
188 def VLD1q8 : VLD1Q<0b0000, "vld1", "8", v16i8, int_arm_neon_vld1>;
189 def VLD1q16 : VLD1Q<0b0100, "vld1", "16", v8i16, int_arm_neon_vld1>;
190 def VLD1q32 : VLD1Q<0b1000, "vld1", "32", v4i32, int_arm_neon_vld1>;
191 def VLD1qf : VLD1Q<0b1000, "vld1", "32", v4f32, int_arm_neon_vld1>;
192 def VLD1q64 : VLD1Q<0b1100, "vld1", "64", v2i64, int_arm_neon_vld1>;
194 // These (dreg triple/quadruple) are for disassembly only.
195 class VLD1D3<bits<4> op7_4, string OpcodeStr, string Dt>
196 : NLdSt<0, 0b10, 0b0110, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
197 (ins addrmode6:$addr), IIC_VLD1, OpcodeStr, Dt,
198 "\\{$dst1, $dst2, $dst3\\}, $addr", "",
199 [/* For disassembly only; pattern left blank */]>;
200 class VLD1D4<bits<4> op7_4, string OpcodeStr, string Dt>
201 : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
202 (ins addrmode6:$addr), IIC_VLD1, OpcodeStr, Dt,
203 "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "",
204 [/* For disassembly only; pattern left blank */]>;
206 def VLD1d8T : VLD1D3<0b0000, "vld1", "8">;
207 def VLD1d16T : VLD1D3<0b0100, "vld1", "16">;
208 def VLD1d32T : VLD1D3<0b1000, "vld1", "32">;
209 //def VLD1d64T : VLD1D3<0b1100, "vld1", "64">;
211 def VLD1d8Q : VLD1D4<0b0000, "vld1", "8">;
212 def VLD1d16Q : VLD1D4<0b0100, "vld1", "16">;
213 def VLD1d32Q : VLD1D4<0b1000, "vld1", "32">;
214 //def VLD1d64Q : VLD1D4<0b1100, "vld1", "64">;
217 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
219 // VLD2 : Vector Load (multiple 2-element structures)
220 class VLD2D<bits<4> op7_4, string OpcodeStr, string Dt>
221 : NLdSt<0,0b10,0b1000,op7_4, (outs DPR:$dst1, DPR:$dst2),
222 (ins addrmode6:$addr), IIC_VLD2,
223 OpcodeStr, Dt, "\\{$dst1, $dst2\\}, $addr", "", []>;
224 class VLD2Q<bits<4> op7_4, string OpcodeStr, string Dt>
225 : NLdSt<0,0b10,0b0011,op7_4,
226 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
227 (ins addrmode6:$addr), IIC_VLD2,
228 OpcodeStr, Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr",
231 def VLD2d8 : VLD2D<0b0000, "vld2", "8">;
232 def VLD2d16 : VLD2D<0b0100, "vld2", "16">;
233 def VLD2d32 : VLD2D<0b1000, "vld2", "32">;
234 def VLD2d64 : NLdSt<0,0b10,0b1010,0b1100, (outs DPR:$dst1, DPR:$dst2),
235 (ins addrmode6:$addr), IIC_VLD1,
236 "vld1", "64", "\\{$dst1, $dst2\\}, $addr", "", []>;
238 def VLD2q8 : VLD2Q<0b0000, "vld2", "8">;
239 def VLD2q16 : VLD2Q<0b0100, "vld2", "16">;
240 def VLD2q32 : VLD2Q<0b1000, "vld2", "32">;
242 // These (double-spaced dreg pair) are for disassembly only.
243 class VLD2Ddbl<bits<4> op7_4, string OpcodeStr, string Dt>
244 : NLdSt<0,0b10,0b1001,op7_4, (outs DPR:$dst1, DPR:$dst2),
245 (ins addrmode6:$addr), IIC_VLD2,
246 OpcodeStr, Dt, "\\{$dst1, $dst2\\}, $addr", "", []>;
248 def VLD2d8D : VLD2Ddbl<0b0000, "vld2", "8">;
249 def VLD2d16D : VLD2Ddbl<0b0100, "vld2", "16">;
250 def VLD2d32D : VLD2Ddbl<0b1000, "vld2", "32">;
252 // VLD3 : Vector Load (multiple 3-element structures)
253 class VLD3D<bits<4> op7_4, string OpcodeStr, string Dt>
254 : NLdSt<0,0b10,0b0100,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
255 (ins addrmode6:$addr), IIC_VLD3,
256 OpcodeStr, Dt, "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
257 class VLD3WB<bits<4> op7_4, string OpcodeStr, string Dt>
258 : NLdSt<0,0b10,0b0101,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
259 (ins addrmode6:$addr), IIC_VLD3,
260 OpcodeStr, Dt, "\\{$dst1, $dst2, $dst3\\}, $addr",
261 "$addr.addr = $wb", []>;
263 def VLD3d8 : VLD3D<0b0000, "vld3", "8">;
264 def VLD3d16 : VLD3D<0b0100, "vld3", "16">;
265 def VLD3d32 : VLD3D<0b1000, "vld3", "32">;
266 def VLD3d64 : NLdSt<0,0b10,0b0110,0b1100,
267 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
268 (ins addrmode6:$addr), IIC_VLD1,
269 "vld1", "64", "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
271 // vld3 to double-spaced even registers.
272 def VLD3q8a : VLD3WB<0b0000, "vld3", "8">;
273 def VLD3q16a : VLD3WB<0b0100, "vld3", "16">;
274 def VLD3q32a : VLD3WB<0b1000, "vld3", "32">;
276 // vld3 to double-spaced odd registers.
277 def VLD3q8b : VLD3WB<0b0000, "vld3", "8">;
278 def VLD3q16b : VLD3WB<0b0100, "vld3", "16">;
279 def VLD3q32b : VLD3WB<0b1000, "vld3", "32">;
281 // VLD4 : Vector Load (multiple 4-element structures)
282 class VLD4D<bits<4> op7_4, string OpcodeStr, string Dt>
283 : NLdSt<0,0b10,0b0000,op7_4,
284 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
285 (ins addrmode6:$addr), IIC_VLD4,
286 OpcodeStr, Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr",
288 class VLD4WB<bits<4> op7_4, string OpcodeStr, string Dt>
289 : NLdSt<0,0b10,0b0001,op7_4,
290 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
291 (ins addrmode6:$addr), IIC_VLD4,
292 OpcodeStr, Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr",
293 "$addr.addr = $wb", []>;
295 def VLD4d8 : VLD4D<0b0000, "vld4", "8">;
296 def VLD4d16 : VLD4D<0b0100, "vld4", "16">;
297 def VLD4d32 : VLD4D<0b1000, "vld4", "32">;
298 def VLD4d64 : NLdSt<0,0b10,0b0010,0b1100,
299 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
300 (ins addrmode6:$addr), IIC_VLD1,
301 "vld1", "64", "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr",
304 // vld4 to double-spaced even registers.
305 def VLD4q8a : VLD4WB<0b0000, "vld4", "8">;
306 def VLD4q16a : VLD4WB<0b0100, "vld4", "16">;
307 def VLD4q32a : VLD4WB<0b1000, "vld4", "32">;
309 // vld4 to double-spaced odd registers.
310 def VLD4q8b : VLD4WB<0b0000, "vld4", "8">;
311 def VLD4q16b : VLD4WB<0b0100, "vld4", "16">;
312 def VLD4q32b : VLD4WB<0b1000, "vld4", "32">;
314 // VLD1LN : Vector Load (single element to one lane)
315 // FIXME: Not yet implemented.
317 // VLD2LN : Vector Load (single 2-element structure to one lane)
318 class VLD2LN<bits<4> op11_8, string OpcodeStr, string Dt>
319 : NLdSt<1,0b10,op11_8,{?,?,?,?}, (outs DPR:$dst1, DPR:$dst2),
320 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
321 IIC_VLD2, OpcodeStr, Dt, "\\{$dst1[$lane], $dst2[$lane]\\}, $addr",
322 "$src1 = $dst1, $src2 = $dst2", []>;
324 // vld2 to single-spaced registers.
325 def VLD2LNd8 : VLD2LN<0b0001, "vld2", "8">;
326 def VLD2LNd16 : VLD2LN<0b0101, "vld2", "16"> { let Inst{5} = 0; }
327 def VLD2LNd32 : VLD2LN<0b1001, "vld2", "32"> { let Inst{6} = 0; }
329 // vld2 to double-spaced even registers.
330 def VLD2LNq16a: VLD2LN<0b0101, "vld2", "16"> { let Inst{5} = 1; }
331 def VLD2LNq32a: VLD2LN<0b1001, "vld2", "32"> { let Inst{6} = 1; }
333 // vld2 to double-spaced odd registers.
334 def VLD2LNq16b: VLD2LN<0b0101, "vld2", "16"> { let Inst{5} = 1; }
335 def VLD2LNq32b: VLD2LN<0b1001, "vld2", "32"> { let Inst{6} = 1; }
337 // VLD3LN : Vector Load (single 3-element structure to one lane)
338 class VLD3LN<bits<4> op11_8, string OpcodeStr, string Dt>
339 : NLdSt<1,0b10,op11_8,{?,?,?,?}, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
340 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
341 nohash_imm:$lane), IIC_VLD3, OpcodeStr, Dt,
342 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr",
343 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
345 // vld3 to single-spaced registers.
346 def VLD3LNd8 : VLD3LN<0b0010, "vld3", "8"> { let Inst{4} = 0; }
347 def VLD3LNd16 : VLD3LN<0b0110, "vld3", "16"> { let Inst{5-4} = 0b00; }
348 def VLD3LNd32 : VLD3LN<0b1010, "vld3", "32"> { let Inst{6-4} = 0b000; }
350 // vld3 to double-spaced even registers.
351 def VLD3LNq16a: VLD3LN<0b0110, "vld3", "16"> { let Inst{5-4} = 0b10; }
352 def VLD3LNq32a: VLD3LN<0b1010, "vld3", "32"> { let Inst{6-4} = 0b100; }
354 // vld3 to double-spaced odd registers.
355 def VLD3LNq16b: VLD3LN<0b0110, "vld3", "16"> { let Inst{5-4} = 0b10; }
356 def VLD3LNq32b: VLD3LN<0b1010, "vld3", "32"> { let Inst{6-4} = 0b100; }
358 // VLD4LN : Vector Load (single 4-element structure to one lane)
359 class VLD4LN<bits<4> op11_8, string OpcodeStr, string Dt>
360 : NLdSt<1,0b10,op11_8,{?,?,?,?},
361 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
362 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
363 nohash_imm:$lane), IIC_VLD4, OpcodeStr, Dt,
364 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr",
365 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
367 // vld4 to single-spaced registers.
368 def VLD4LNd8 : VLD4LN<0b0011, "vld4", "8">;
369 def VLD4LNd16 : VLD4LN<0b0111, "vld4", "16"> { let Inst{5} = 0; }
370 def VLD4LNd32 : VLD4LN<0b1011, "vld4", "32"> { let Inst{6} = 0; }
372 // vld4 to double-spaced even registers.
373 def VLD4LNq16a: VLD4LN<0b0111, "vld4", "16"> { let Inst{5} = 1; }
374 def VLD4LNq32a: VLD4LN<0b1011, "vld4", "32"> { let Inst{6} = 1; }
376 // vld4 to double-spaced odd registers.
377 def VLD4LNq16b: VLD4LN<0b0111, "vld4", "16"> { let Inst{5} = 1; }
378 def VLD4LNq32b: VLD4LN<0b1011, "vld4", "32"> { let Inst{6} = 1; }
380 // VLD1DUP : Vector Load (single element to all lanes)
381 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
382 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
383 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
384 // FIXME: Not yet implemented.
385 } // mayLoad = 1, hasExtraDefRegAllocReq = 1
387 // VST1 : Vector Store (multiple single elements)
388 class VST1D<bits<4> op7_4, string OpcodeStr, string Dt,
389 ValueType Ty, Intrinsic IntOp>
390 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src), IIC_VST,
391 OpcodeStr, Dt, "\\{$src\\}, $addr", "",
392 [(IntOp addrmode6:$addr, (Ty DPR:$src))]>;
393 class VST1Q<bits<4> op7_4, string OpcodeStr, string Dt,
394 ValueType Ty, Intrinsic IntOp>
395 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$addr, QPR:$src), IIC_VST,
396 OpcodeStr, Dt, "${src:dregpair}, $addr", "",
397 [(IntOp addrmode6:$addr, (Ty QPR:$src))]>;
399 let hasExtraSrcRegAllocReq = 1 in {
400 def VST1d8 : VST1D<0b0000, "vst1", "8", v8i8, int_arm_neon_vst1>;
401 def VST1d16 : VST1D<0b0100, "vst1", "16", v4i16, int_arm_neon_vst1>;
402 def VST1d32 : VST1D<0b1000, "vst1", "32", v2i32, int_arm_neon_vst1>;
403 def VST1df : VST1D<0b1000, "vst1", "32", v2f32, int_arm_neon_vst1>;
404 def VST1d64 : VST1D<0b1100, "vst1", "64", v1i64, int_arm_neon_vst1>;
406 def VST1q8 : VST1Q<0b0000, "vst1", "8", v16i8, int_arm_neon_vst1>;
407 def VST1q16 : VST1Q<0b0100, "vst1", "16", v8i16, int_arm_neon_vst1>;
408 def VST1q32 : VST1Q<0b1000, "vst1", "32", v4i32, int_arm_neon_vst1>;
409 def VST1qf : VST1Q<0b1000, "vst1", "32", v4f32, int_arm_neon_vst1>;
410 def VST1q64 : VST1Q<0b1100, "vst1", "64", v2i64, int_arm_neon_vst1>;
411 } // hasExtraSrcRegAllocReq
413 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
415 // VST2 : Vector Store (multiple 2-element structures)
416 class VST2D<bits<4> op7_4, string OpcodeStr, string Dt>
417 : NLdSt<0,0b00,0b1000,op7_4, (outs),
418 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
419 OpcodeStr, Dt, "\\{$src1, $src2\\}, $addr", "", []>;
420 class VST2Q<bits<4> op7_4, string OpcodeStr, string Dt>
421 : NLdSt<0,0b00,0b0011,op7_4, (outs),
422 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
423 IIC_VST, OpcodeStr, Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
426 def VST2d8 : VST2D<0b0000, "vst2", "8">;
427 def VST2d16 : VST2D<0b0100, "vst2", "16">;
428 def VST2d32 : VST2D<0b1000, "vst2", "32">;
429 def VST2d64 : NLdSt<0,0b00,0b1010,0b1100, (outs),
430 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
431 "vst1", "64", "\\{$src1, $src2\\}, $addr", "", []>;
433 def VST2q8 : VST2Q<0b0000, "vst2", "8">;
434 def VST2q16 : VST2Q<0b0100, "vst2", "16">;
435 def VST2q32 : VST2Q<0b1000, "vst2", "32">;
437 // VST3 : Vector Store (multiple 3-element structures)
438 class VST3D<bits<4> op7_4, string OpcodeStr, string Dt>
439 : NLdSt<0,0b00,0b0100,op7_4, (outs),
440 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
441 OpcodeStr, Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>;
442 class VST3WB<bits<4> op7_4, string OpcodeStr, string Dt>
443 : NLdSt<0,0b00,0b0101,op7_4, (outs GPR:$wb),
444 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
445 OpcodeStr, Dt, "\\{$src1, $src2, $src3\\}, $addr",
446 "$addr.addr = $wb", []>;
448 def VST3d8 : VST3D<0b0000, "vst3", "8">;
449 def VST3d16 : VST3D<0b0100, "vst3", "16">;
450 def VST3d32 : VST3D<0b1000, "vst3", "32">;
451 def VST3d64 : NLdSt<0,0b00,0b0110,0b1100, (outs),
452 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
454 "vst1", "64", "\\{$src1, $src2, $src3\\}, $addr", "", []>;
456 // vst3 to double-spaced even registers.
457 def VST3q8a : VST3WB<0b0000, "vst3", "8">;
458 def VST3q16a : VST3WB<0b0100, "vst3", "16">;
459 def VST3q32a : VST3WB<0b1000, "vst3", "32">;
461 // vst3 to double-spaced odd registers.
462 def VST3q8b : VST3WB<0b0000, "vst3", "8">;
463 def VST3q16b : VST3WB<0b0100, "vst3", "16">;
464 def VST3q32b : VST3WB<0b1000, "vst3", "32">;
466 // VST4 : Vector Store (multiple 4-element structures)
467 class VST4D<bits<4> op7_4, string OpcodeStr, string Dt>
468 : NLdSt<0,0b00,0b0000,op7_4, (outs),
469 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
470 IIC_VST, OpcodeStr, Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
472 class VST4WB<bits<4> op7_4, string OpcodeStr, string Dt>
473 : NLdSt<0,0b00,0b0001,op7_4, (outs GPR:$wb),
474 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
475 IIC_VST, OpcodeStr, Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
476 "$addr.addr = $wb", []>;
478 def VST4d8 : VST4D<0b0000, "vst4", "8">;
479 def VST4d16 : VST4D<0b0100, "vst4", "16">;
480 def VST4d32 : VST4D<0b1000, "vst4", "32">;
481 def VST4d64 : NLdSt<0,0b00,0b0010,0b1100, (outs),
482 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
484 "vst1", "64", "\\{$src1, $src2, $src3, $src4\\}, $addr",
487 // vst4 to double-spaced even registers.
488 def VST4q8a : VST4WB<0b0000, "vst4", "8">;
489 def VST4q16a : VST4WB<0b0100, "vst4", "16">;
490 def VST4q32a : VST4WB<0b1000, "vst4", "32">;
492 // vst4 to double-spaced odd registers.
493 def VST4q8b : VST4WB<0b0000, "vst4", "8">;
494 def VST4q16b : VST4WB<0b0100, "vst4", "16">;
495 def VST4q32b : VST4WB<0b1000, "vst4", "32">;
497 // VST1LN : Vector Store (single element from one lane)
498 // FIXME: Not yet implemented.
500 // VST2LN : Vector Store (single 2-element structure from one lane)
501 class VST2LN<bits<4> op11_8, string OpcodeStr, string Dt>
502 : NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs),
503 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
504 IIC_VST, OpcodeStr, Dt, "\\{$src1[$lane], $src2[$lane]\\}, $addr",
507 // vst2 to single-spaced registers.
508 def VST2LNd8 : VST2LN<0b0001, "vst2", "8">;
509 def VST2LNd16 : VST2LN<0b0101, "vst2", "16"> { let Inst{5} = 0; }
510 def VST2LNd32 : VST2LN<0b1001, "vst2", "32"> { let Inst{6} = 0; }
512 // vst2 to double-spaced even registers.
513 def VST2LNq16a: VST2LN<0b0101, "vst2", "16"> { let Inst{5} = 1; }
514 def VST2LNq32a: VST2LN<0b1001, "vst2", "32"> { let Inst{6} = 1; }
516 // vst2 to double-spaced odd registers.
517 def VST2LNq16b: VST2LN<0b0101, "vst2", "16"> { let Inst{5} = 1; }
518 def VST2LNq32b: VST2LN<0b1001, "vst2", "32"> { let Inst{6} = 1; }
520 // VST3LN : Vector Store (single 3-element structure from one lane)
521 class VST3LN<bits<4> op11_8, string OpcodeStr, string Dt>
522 : NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs),
523 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
524 nohash_imm:$lane), IIC_VST, OpcodeStr, Dt,
525 "\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr", "", []>;
527 // vst3 to single-spaced registers.
528 def VST3LNd8 : VST3LN<0b0010, "vst3", "8"> { let Inst{4} = 0; }
529 def VST3LNd16 : VST3LN<0b0110, "vst3", "16"> { let Inst{5-4} = 0b00; }
530 def VST3LNd32 : VST3LN<0b1010, "vst3", "32"> { let Inst{6-4} = 0b000; }
532 // vst3 to double-spaced even registers.
533 def VST3LNq16a: VST3LN<0b0110, "vst3", "16"> { let Inst{5-4} = 0b10; }
534 def VST3LNq32a: VST3LN<0b1010, "vst3", "32"> { let Inst{6-4} = 0b100; }
536 // vst3 to double-spaced odd registers.
537 def VST3LNq16b: VST3LN<0b0110, "vst3", "16"> { let Inst{5-4} = 0b10; }
538 def VST3LNq32b: VST3LN<0b1010, "vst3", "32"> { let Inst{6-4} = 0b100; }
540 // VST4LN : Vector Store (single 4-element structure from one lane)
541 class VST4LN<bits<4> op11_8, string OpcodeStr, string Dt>
542 : NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs),
543 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
544 nohash_imm:$lane), IIC_VST, OpcodeStr, Dt,
545 "\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr",
548 // vst4 to single-spaced registers.
549 def VST4LNd8 : VST4LN<0b0011, "vst4", "8">;
550 def VST4LNd16 : VST4LN<0b0111, "vst4", "16"> { let Inst{5} = 0; }
551 def VST4LNd32 : VST4LN<0b1011, "vst4", "32"> { let Inst{6} = 0; }
553 // vst4 to double-spaced even registers.
554 def VST4LNq16a: VST4LN<0b0111, "vst4", "16"> { let Inst{5} = 1; }
555 def VST4LNq32a: VST4LN<0b1011, "vst4", "32"> { let Inst{6} = 1; }
557 // vst4 to double-spaced odd registers.
558 def VST4LNq16b: VST4LN<0b0111, "vst4", "16"> { let Inst{5} = 1; }
559 def VST4LNq32b: VST4LN<0b1011, "vst4", "32"> { let Inst{6} = 1; }
561 } // mayStore = 1, hasExtraSrcRegAllocReq = 1
564 //===----------------------------------------------------------------------===//
565 // NEON pattern fragments
566 //===----------------------------------------------------------------------===//
568 // Extract D sub-registers of Q registers.
569 // (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
570 def DSubReg_i8_reg : SDNodeXForm<imm, [{
571 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
573 def DSubReg_i16_reg : SDNodeXForm<imm, [{
574 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
576 def DSubReg_i32_reg : SDNodeXForm<imm, [{
577 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
579 def DSubReg_f64_reg : SDNodeXForm<imm, [{
580 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
582 def DSubReg_f64_other_reg : SDNodeXForm<imm, [{
583 return CurDAG->getTargetConstant(5 + (1 - N->getZExtValue()), MVT::i32);
586 // Extract S sub-registers of Q/D registers.
587 // (arm_ssubreg_0 is 1; arm_ssubreg_1 is 2; etc.)
588 def SSubReg_f32_reg : SDNodeXForm<imm, [{
589 return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32);
592 // Translate lane numbers from Q registers to D subregs.
593 def SubReg_i8_lane : SDNodeXForm<imm, [{
594 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
596 def SubReg_i16_lane : SDNodeXForm<imm, [{
597 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
599 def SubReg_i32_lane : SDNodeXForm<imm, [{
600 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
603 //===----------------------------------------------------------------------===//
604 // Instruction Classes
605 //===----------------------------------------------------------------------===//
607 // Basic 2-register operations: single-, double- and quad-register.
608 class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
609 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
610 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
611 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
612 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
613 IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
614 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
615 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
616 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
617 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
618 (ins DPR:$src), IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "",
619 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
620 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
621 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
622 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
623 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
624 (ins QPR:$src), IIC_VUNAQ, OpcodeStr, Dt, "$dst, $src", "",
625 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
627 // Basic 2-register intrinsics, both double- and quad-register.
628 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
629 bits<2> op17_16, bits<5> op11_7, bit op4,
630 InstrItinClass itin, string OpcodeStr, string Dt,
631 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
632 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
633 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
634 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
635 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
636 bits<2> op17_16, bits<5> op11_7, bit op4,
637 InstrItinClass itin, string OpcodeStr, string Dt,
638 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
639 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
640 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
641 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
643 // Narrow 2-register intrinsics.
644 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
645 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
646 InstrItinClass itin, string OpcodeStr, string Dt,
647 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
648 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
649 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
650 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
652 // Long 2-register intrinsics (currently only used for VMOVL).
653 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
654 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
655 InstrItinClass itin, string OpcodeStr, string Dt,
656 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
657 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$dst),
658 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
659 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
661 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
662 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
663 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
664 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
665 OpcodeStr, Dt, "$dst1, $dst2",
666 "$src1 = $dst1, $src2 = $dst2", []>;
667 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
668 InstrItinClass itin, string OpcodeStr, string Dt>
669 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
670 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$dst1, $dst2",
671 "$src1 = $dst1, $src2 = $dst2", []>;
673 // Basic 3-register operations: single-, double- and quad-register.
674 class N3VS<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
675 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
676 SDNode OpNode, bit Commutable>
677 : N3V<op24, op23, op21_20, op11_8, 0, op4,
678 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), IIC_VBIND,
679 OpcodeStr, Dt, "$dst, $src1, $src2", "", []> {
680 let isCommutable = Commutable;
683 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
684 InstrItinClass itin, string OpcodeStr, string Dt,
685 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
686 : N3V<op24, op23, op21_20, op11_8, 0, op4,
687 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
688 OpcodeStr, Dt, "$dst, $src1, $src2", "",
689 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
690 let isCommutable = Commutable;
692 // Same as N3VD but no data type.
693 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
694 InstrItinClass itin, string OpcodeStr,
695 ValueType ResTy, ValueType OpTy,
696 SDNode OpNode, bit Commutable>
697 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
698 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
699 OpcodeStr, "$dst, $src1, $src2", "",
700 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]>{
701 let isCommutable = Commutable;
703 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
704 InstrItinClass itin, string OpcodeStr, string Dt,
705 ValueType Ty, SDNode ShOp>
706 : N3V<0, 1, op21_20, op11_8, 1, 0,
707 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
708 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
710 (Ty (ShOp (Ty DPR:$src1),
711 (Ty (NEONvduplane (Ty DPR_VFP2:$src2), imm:$lane)))))]>{
712 let isCommutable = 0;
714 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
715 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
716 : N3V<0, 1, op21_20, op11_8, 1, 0,
717 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
718 IIC_VMULi16D, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
720 (Ty (ShOp (Ty DPR:$src1),
721 (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
722 let isCommutable = 0;
725 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
726 InstrItinClass itin, string OpcodeStr, string Dt,
727 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
728 : N3V<op24, op23, op21_20, op11_8, 1, op4,
729 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
730 OpcodeStr, Dt, "$dst, $src1, $src2", "",
731 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
732 let isCommutable = Commutable;
734 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
735 InstrItinClass itin, string OpcodeStr,
736 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
737 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
738 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
739 OpcodeStr, "$dst, $src1, $src2", "",
740 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]>{
741 let isCommutable = Commutable;
743 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
744 InstrItinClass itin, string OpcodeStr, string Dt,
745 ValueType ResTy, ValueType OpTy, SDNode ShOp>
746 : N3V<1, 1, op21_20, op11_8, 1, 0,
747 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
748 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
749 [(set (ResTy QPR:$dst),
750 (ResTy (ShOp (ResTy QPR:$src1),
751 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
753 let isCommutable = 0;
755 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
756 ValueType ResTy, ValueType OpTy, SDNode ShOp>
757 : N3V<1, 1, op21_20, op11_8, 1, 0,
758 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
759 IIC_VMULi16Q, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
760 [(set (ResTy QPR:$dst),
761 (ResTy (ShOp (ResTy QPR:$src1),
762 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
764 let isCommutable = 0;
767 // Basic 3-register intrinsics, both double- and quad-register.
768 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
769 InstrItinClass itin, string OpcodeStr, string Dt,
770 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
771 : N3V<op24, op23, op21_20, op11_8, 0, op4,
772 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
773 OpcodeStr, Dt, "$dst, $src1, $src2", "",
774 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
775 let isCommutable = Commutable;
777 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
778 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
779 : N3V<0, 1, op21_20, op11_8, 1, 0,
780 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
781 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
783 (Ty (IntOp (Ty DPR:$src1),
784 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
786 let isCommutable = 0;
788 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
789 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
790 : N3V<0, 1, op21_20, op11_8, 1, 0,
791 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
792 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
794 (Ty (IntOp (Ty DPR:$src1),
795 (Ty (NEONvduplane (Ty DPR_8:$src2),
797 let isCommutable = 0;
800 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
801 InstrItinClass itin, string OpcodeStr, string Dt,
802 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
803 : N3V<op24, op23, op21_20, op11_8, 1, op4,
804 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
805 OpcodeStr, Dt, "$dst, $src1, $src2", "",
806 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
807 let isCommutable = Commutable;
809 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
810 string OpcodeStr, string Dt,
811 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
812 : N3V<1, 1, op21_20, op11_8, 1, 0,
813 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
814 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
815 [(set (ResTy QPR:$dst),
816 (ResTy (IntOp (ResTy QPR:$src1),
817 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
819 let isCommutable = 0;
821 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
822 string OpcodeStr, string Dt,
823 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
824 : N3V<1, 1, op21_20, op11_8, 1, 0,
825 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
826 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
827 [(set (ResTy QPR:$dst),
828 (ResTy (IntOp (ResTy QPR:$src1),
829 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
831 let isCommutable = 0;
834 // Multiply-Add/Sub operations: single-, double- and quad-register.
835 class N3VSMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
836 InstrItinClass itin, string OpcodeStr, string Dt,
837 ValueType Ty, SDNode MulOp, SDNode OpNode>
838 : N3V<op24, op23, op21_20, op11_8, 0, op4,
839 (outs DPR_VFP2:$dst),
840 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), itin,
841 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst", []>;
843 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
844 InstrItinClass itin, string OpcodeStr, string Dt,
845 ValueType Ty, SDNode MulOp, SDNode OpNode>
846 : N3V<op24, op23, op21_20, op11_8, 0, op4,
847 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin,
848 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
849 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
850 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
851 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
852 string OpcodeStr, string Dt,
853 ValueType Ty, SDNode MulOp, SDNode ShOp>
854 : N3V<0, 1, op21_20, op11_8, 1, 0,
856 (ins DPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
857 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
859 (Ty (ShOp (Ty DPR:$src1),
860 (Ty (MulOp DPR:$src2,
861 (Ty (NEONvduplane (Ty DPR_VFP2:$src3),
863 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
864 string OpcodeStr, string Dt,
865 ValueType Ty, SDNode MulOp, SDNode ShOp>
866 : N3V<0, 1, op21_20, op11_8, 1, 0,
868 (ins DPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
869 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
871 (Ty (ShOp (Ty DPR:$src1),
872 (Ty (MulOp DPR:$src2,
873 (Ty (NEONvduplane (Ty DPR_8:$src3),
876 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
877 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
878 SDNode MulOp, SDNode OpNode>
879 : N3V<op24, op23, op21_20, op11_8, 1, op4,
880 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin,
881 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
882 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
883 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
884 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
885 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
886 SDNode MulOp, SDNode ShOp>
887 : N3V<1, 1, op21_20, op11_8, 1, 0,
889 (ins QPR:$src1, QPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
890 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
891 [(set (ResTy QPR:$dst),
892 (ResTy (ShOp (ResTy QPR:$src1),
893 (ResTy (MulOp QPR:$src2,
894 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src3),
896 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
897 string OpcodeStr, string Dt,
898 ValueType ResTy, ValueType OpTy,
899 SDNode MulOp, SDNode ShOp>
900 : N3V<1, 1, op21_20, op11_8, 1, 0,
902 (ins QPR:$src1, QPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
903 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
904 [(set (ResTy QPR:$dst),
905 (ResTy (ShOp (ResTy QPR:$src1),
906 (ResTy (MulOp QPR:$src2,
907 (ResTy (NEONvduplane (OpTy DPR_8:$src3),
910 // Neon 3-argument intrinsics, both double- and quad-register.
911 // The destination register is also used as the first source operand register.
912 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
913 InstrItinClass itin, string OpcodeStr, string Dt,
914 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
915 : N3V<op24, op23, op21_20, op11_8, 0, op4,
916 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin,
917 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
918 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
919 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
920 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
921 InstrItinClass itin, string OpcodeStr, string Dt,
922 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
923 : N3V<op24, op23, op21_20, op11_8, 1, op4,
924 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin,
925 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
926 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
927 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
929 // Neon Long 3-argument intrinsic. The destination register is
930 // a quad-register and is also used as the first source operand register.
931 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
932 InstrItinClass itin, string OpcodeStr, string Dt,
933 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
934 : N3V<op24, op23, op21_20, op11_8, 0, op4,
935 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), itin,
936 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
938 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
939 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
940 string OpcodeStr, string Dt,
941 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
942 : N3V<op24, 1, op21_20, op11_8, 1, 0,
944 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
945 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
946 [(set (ResTy QPR:$dst),
947 (ResTy (IntOp (ResTy QPR:$src1),
949 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src3),
951 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
952 InstrItinClass itin, string OpcodeStr, string Dt,
953 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
954 : N3V<op24, 1, op21_20, op11_8, 1, 0,
956 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
957 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
958 [(set (ResTy QPR:$dst),
959 (ResTy (IntOp (ResTy QPR:$src1),
961 (OpTy (NEONvduplane (OpTy DPR_8:$src3),
964 // Narrowing 3-register intrinsics.
965 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
966 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
967 Intrinsic IntOp, bit Commutable>
968 : N3V<op24, op23, op21_20, op11_8, 0, op4,
969 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VBINi4D,
970 OpcodeStr, Dt, "$dst, $src1, $src2", "",
971 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
972 let isCommutable = Commutable;
975 // Long 3-register intrinsics.
976 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
977 InstrItinClass itin, string OpcodeStr, string Dt,
978 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
979 : N3V<op24, op23, op21_20, op11_8, 0, op4,
980 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
981 OpcodeStr, Dt, "$dst, $src1, $src2", "",
982 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
983 let isCommutable = Commutable;
985 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
986 string OpcodeStr, string Dt,
987 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
988 : N3V<op24, 1, op21_20, op11_8, 1, 0,
989 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
990 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
991 [(set (ResTy QPR:$dst),
992 (ResTy (IntOp (OpTy DPR:$src1),
993 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src2),
995 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
996 InstrItinClass itin, string OpcodeStr, string Dt,
997 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
998 : N3V<op24, 1, op21_20, op11_8, 1, 0,
999 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1000 itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1001 [(set (ResTy QPR:$dst),
1002 (ResTy (IntOp (OpTy DPR:$src1),
1003 (OpTy (NEONvduplane (OpTy DPR_8:$src2),
1006 // Wide 3-register intrinsics.
1007 class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1008 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
1009 Intrinsic IntOp, bit Commutable>
1010 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1011 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), IIC_VSUBiD,
1012 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1013 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
1014 let isCommutable = Commutable;
1017 // Pairwise long 2-register intrinsics, both double- and quad-register.
1018 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1019 bits<2> op17_16, bits<5> op11_7, bit op4,
1020 string OpcodeStr, string Dt,
1021 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1022 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1023 (ins DPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
1024 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
1025 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1026 bits<2> op17_16, bits<5> op11_7, bit op4,
1027 string OpcodeStr, string Dt,
1028 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1029 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1030 (ins QPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
1031 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
1033 // Pairwise long 2-register accumulate intrinsics,
1034 // both double- and quad-register.
1035 // The destination register is also used as the first source operand register.
1036 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1037 bits<2> op17_16, bits<5> op11_7, bit op4,
1038 string OpcodeStr, string Dt,
1039 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1040 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
1041 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), IIC_VPALiD,
1042 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
1043 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
1044 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1045 bits<2> op17_16, bits<5> op11_7, bit op4,
1046 string OpcodeStr, string Dt,
1047 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1048 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
1049 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VPALiQ,
1050 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
1051 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
1053 // Shift by immediate,
1054 // both double- and quad-register.
1055 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1056 InstrItinClass itin, string OpcodeStr, string Dt,
1057 ValueType Ty, SDNode OpNode>
1058 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1059 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), itin,
1060 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1061 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
1062 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1063 InstrItinClass itin, string OpcodeStr, string Dt,
1064 ValueType Ty, SDNode OpNode>
1065 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1066 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin,
1067 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1068 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
1070 // Long shift by immediate.
1071 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1072 string OpcodeStr, string Dt,
1073 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1074 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1075 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VSHLiD,
1076 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1077 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
1078 (i32 imm:$SIMM))))]>;
1080 // Narrow shift by immediate.
1081 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1082 InstrItinClass itin, string OpcodeStr, string Dt,
1083 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1084 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1085 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin,
1086 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1087 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
1088 (i32 imm:$SIMM))))]>;
1090 // Shift right by immediate and accumulate,
1091 // both double- and quad-register.
1092 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1093 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1094 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1095 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), IIC_VPALiD,
1096 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1097 [(set DPR:$dst, (Ty (add DPR:$src1,
1098 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
1099 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1100 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1101 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1102 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), IIC_VPALiD,
1103 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1104 [(set QPR:$dst, (Ty (add QPR:$src1,
1105 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
1107 // Shift by immediate and insert,
1108 // both double- and quad-register.
1109 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1110 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1111 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1112 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), IIC_VSHLiD,
1113 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1114 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
1115 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1116 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1117 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1118 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), IIC_VSHLiQ,
1119 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1120 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
1122 // Convert, with fractional bits immediate,
1123 // both double- and quad-register.
1124 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1125 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1127 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1128 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VUNAD,
1129 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1130 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
1131 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1132 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1134 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1135 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), IIC_VUNAQ,
1136 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1137 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
1139 //===----------------------------------------------------------------------===//
1141 //===----------------------------------------------------------------------===//
1143 // Abbreviations used in multiclass suffixes:
1144 // Q = quarter int (8 bit) elements
1145 // H = half int (16 bit) elements
1146 // S = single int (32 bit) elements
1147 // D = double int (64 bit) elements
1149 // Neon 2-register vector operations -- for disassembly only.
1151 // First with only element sizes of 8, 16 and 32 bits:
1152 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1153 bits<5> op11_7, bit op4, string opc, string Dt,
1155 // 64-bit vector types.
1156 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
1157 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1158 opc, !strconcat(Dt, "8"), asm, "", []>;
1159 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
1160 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1161 opc, !strconcat(Dt, "16"), asm, "", []>;
1162 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
1163 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1164 opc, !strconcat(Dt, "32"), asm, "", []>;
1165 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
1166 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1167 opc, "f32", asm, "", []> {
1168 let Inst{10} = 1; // overwrite F = 1
1171 // 128-bit vector types.
1172 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
1173 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1174 opc, !strconcat(Dt, "8"), asm, "", []>;
1175 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
1176 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1177 opc, !strconcat(Dt, "16"), asm, "", []>;
1178 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
1179 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1180 opc, !strconcat(Dt, "32"), asm, "", []>;
1181 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
1182 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1183 opc, "f32", asm, "", []> {
1184 let Inst{10} = 1; // overwrite F = 1
1188 // Neon 3-register vector operations.
1190 // First with only element sizes of 8, 16 and 32 bits:
1191 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1192 InstrItinClass itinD16, InstrItinClass itinD32,
1193 InstrItinClass itinQ16, InstrItinClass itinQ32,
1194 string OpcodeStr, string Dt,
1195 SDNode OpNode, bit Commutable = 0> {
1196 // 64-bit vector types.
1197 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
1198 OpcodeStr, !strconcat(Dt, "8"),
1199 v8i8, v8i8, OpNode, Commutable>;
1200 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
1201 OpcodeStr, !strconcat(Dt, "16"),
1202 v4i16, v4i16, OpNode, Commutable>;
1203 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
1204 OpcodeStr, !strconcat(Dt, "32"),
1205 v2i32, v2i32, OpNode, Commutable>;
1207 // 128-bit vector types.
1208 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
1209 OpcodeStr, !strconcat(Dt, "8"),
1210 v16i8, v16i8, OpNode, Commutable>;
1211 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
1212 OpcodeStr, !strconcat(Dt, "16"),
1213 v8i16, v8i16, OpNode, Commutable>;
1214 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
1215 OpcodeStr, !strconcat(Dt, "32"),
1216 v4i32, v4i32, OpNode, Commutable>;
1219 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
1220 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1222 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
1224 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1225 v8i16, v4i16, ShOp>;
1226 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
1227 v4i32, v2i32, ShOp>;
1230 // ....then also with element size 64 bits:
1231 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1232 InstrItinClass itinD, InstrItinClass itinQ,
1233 string OpcodeStr, string Dt,
1234 SDNode OpNode, bit Commutable = 0>
1235 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
1236 OpcodeStr, Dt, OpNode, Commutable> {
1237 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
1238 OpcodeStr, !strconcat(Dt, "64"),
1239 v1i64, v1i64, OpNode, Commutable>;
1240 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
1241 OpcodeStr, !strconcat(Dt, "64"),
1242 v2i64, v2i64, OpNode, Commutable>;
1246 // Neon Narrowing 2-register vector intrinsics,
1247 // source operand element sizes of 16, 32 and 64 bits:
1248 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1249 bits<5> op11_7, bit op6, bit op4,
1250 InstrItinClass itin, string OpcodeStr, string Dt,
1252 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
1253 itin, OpcodeStr, !strconcat(Dt, "16"),
1254 v8i8, v8i16, IntOp>;
1255 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
1256 itin, OpcodeStr, !strconcat(Dt, "32"),
1257 v4i16, v4i32, IntOp>;
1258 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
1259 itin, OpcodeStr, !strconcat(Dt, "64"),
1260 v2i32, v2i64, IntOp>;
1264 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
1265 // source operand element sizes of 16, 32 and 64 bits:
1266 multiclass N2VLInt_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
1267 string OpcodeStr, string Dt, Intrinsic IntOp> {
1268 def v8i16 : N2VLInt<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1269 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
1270 def v4i32 : N2VLInt<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1271 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1272 def v2i64 : N2VLInt<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1273 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1277 // Neon 3-register vector intrinsics.
1279 // First with only element sizes of 16 and 32 bits:
1280 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1281 InstrItinClass itinD16, InstrItinClass itinD32,
1282 InstrItinClass itinQ16, InstrItinClass itinQ32,
1283 string OpcodeStr, string Dt,
1284 Intrinsic IntOp, bit Commutable = 0> {
1285 // 64-bit vector types.
1286 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, itinD16,
1287 OpcodeStr, !strconcat(Dt, "16"),
1288 v4i16, v4i16, IntOp, Commutable>;
1289 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, itinD32,
1290 OpcodeStr, !strconcat(Dt, "32"),
1291 v2i32, v2i32, IntOp, Commutable>;
1293 // 128-bit vector types.
1294 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, itinQ16,
1295 OpcodeStr, !strconcat(Dt, "16"),
1296 v8i16, v8i16, IntOp, Commutable>;
1297 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, itinQ32,
1298 OpcodeStr, !strconcat(Dt, "32"),
1299 v4i32, v4i32, IntOp, Commutable>;
1302 multiclass N3VIntSL_HS<bits<4> op11_8,
1303 InstrItinClass itinD16, InstrItinClass itinD32,
1304 InstrItinClass itinQ16, InstrItinClass itinQ32,
1305 string OpcodeStr, string Dt, Intrinsic IntOp> {
1306 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
1307 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
1308 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
1309 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
1310 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
1311 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
1312 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
1313 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
1316 // ....then also with element size of 8 bits:
1317 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1318 InstrItinClass itinD16, InstrItinClass itinD32,
1319 InstrItinClass itinQ16, InstrItinClass itinQ32,
1320 string OpcodeStr, string Dt,
1321 Intrinsic IntOp, bit Commutable = 0>
1322 : N3VInt_HS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
1323 OpcodeStr, Dt, IntOp, Commutable> {
1324 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, itinD16,
1325 OpcodeStr, !strconcat(Dt, "8"),
1326 v8i8, v8i8, IntOp, Commutable>;
1327 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, itinQ16,
1328 OpcodeStr, !strconcat(Dt, "8"),
1329 v16i8, v16i8, IntOp, Commutable>;
1332 // ....then also with element size of 64 bits:
1333 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1334 InstrItinClass itinD16, InstrItinClass itinD32,
1335 InstrItinClass itinQ16, InstrItinClass itinQ32,
1336 string OpcodeStr, string Dt,
1337 Intrinsic IntOp, bit Commutable = 0>
1338 : N3VInt_QHS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
1339 OpcodeStr, Dt, IntOp, Commutable> {
1340 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, itinD32,
1341 OpcodeStr, !strconcat(Dt, "64"),
1342 v1i64, v1i64, IntOp, Commutable>;
1343 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, itinQ32,
1344 OpcodeStr, !strconcat(Dt, "64"),
1345 v2i64, v2i64, IntOp, Commutable>;
1349 // Neon Narrowing 3-register vector intrinsics,
1350 // source operand element sizes of 16, 32 and 64 bits:
1351 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1352 string OpcodeStr, string Dt,
1353 Intrinsic IntOp, bit Commutable = 0> {
1354 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
1355 OpcodeStr, !strconcat(Dt, "16"),
1356 v8i8, v8i16, IntOp, Commutable>;
1357 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
1358 OpcodeStr, !strconcat(Dt, "32"),
1359 v4i16, v4i32, IntOp, Commutable>;
1360 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
1361 OpcodeStr, !strconcat(Dt, "64"),
1362 v2i32, v2i64, IntOp, Commutable>;
1366 // Neon Long 3-register vector intrinsics.
1368 // First with only element sizes of 16 and 32 bits:
1369 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1370 InstrItinClass itin, string OpcodeStr, string Dt,
1371 Intrinsic IntOp, bit Commutable = 0> {
1372 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin,
1373 OpcodeStr, !strconcat(Dt, "16"),
1374 v4i32, v4i16, IntOp, Commutable>;
1375 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin,
1376 OpcodeStr, !strconcat(Dt, "32"),
1377 v2i64, v2i32, IntOp, Commutable>;
1380 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
1381 InstrItinClass itin, string OpcodeStr, string Dt,
1383 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
1384 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1385 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
1386 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1389 // ....then also with element size of 8 bits:
1390 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1391 InstrItinClass itin, string OpcodeStr, string Dt,
1392 Intrinsic IntOp, bit Commutable = 0>
1393 : N3VLInt_HS<op24, op23, op11_8, op4, itin, OpcodeStr, Dt,
1394 IntOp, Commutable> {
1395 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin,
1396 OpcodeStr, !strconcat(Dt, "8"),
1397 v8i16, v8i8, IntOp, Commutable>;
1401 // Neon Wide 3-register vector intrinsics,
1402 // source operand element sizes of 8, 16 and 32 bits:
1403 multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1404 string OpcodeStr, string Dt,
1405 Intrinsic IntOp, bit Commutable = 0> {
1406 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4,
1407 OpcodeStr, !strconcat(Dt, "8"),
1408 v8i16, v8i8, IntOp, Commutable>;
1409 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4,
1410 OpcodeStr, !strconcat(Dt, "16"),
1411 v4i32, v4i16, IntOp, Commutable>;
1412 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4,
1413 OpcodeStr, !strconcat(Dt, "32"),
1414 v2i64, v2i32, IntOp, Commutable>;
1418 // Neon Multiply-Op vector operations,
1419 // element sizes of 8, 16 and 32 bits:
1420 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1421 InstrItinClass itinD16, InstrItinClass itinD32,
1422 InstrItinClass itinQ16, InstrItinClass itinQ32,
1423 string OpcodeStr, string Dt, SDNode OpNode> {
1424 // 64-bit vector types.
1425 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
1426 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
1427 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
1428 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
1429 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
1430 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
1432 // 128-bit vector types.
1433 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
1434 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
1435 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
1436 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
1437 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
1438 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
1441 multiclass N3VMulOpSL_HS<bits<4> op11_8,
1442 InstrItinClass itinD16, InstrItinClass itinD32,
1443 InstrItinClass itinQ16, InstrItinClass itinQ32,
1444 string OpcodeStr, string Dt, SDNode ShOp> {
1445 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
1446 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
1447 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
1448 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
1449 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
1450 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
1452 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
1453 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
1457 // Neon 3-argument intrinsics,
1458 // element sizes of 8, 16 and 32 bits:
1459 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1460 string OpcodeStr, string Dt, Intrinsic IntOp> {
1461 // 64-bit vector types.
1462 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16D,
1463 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
1464 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
1465 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
1466 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32D,
1467 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
1469 // 128-bit vector types.
1470 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16Q,
1471 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
1472 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16Q,
1473 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
1474 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32Q,
1475 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
1479 // Neon Long 3-argument intrinsics.
1481 // First with only element sizes of 16 and 32 bits:
1482 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1483 string OpcodeStr, string Dt, Intrinsic IntOp> {
1484 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
1485 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1486 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi16D,
1487 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1490 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
1491 string OpcodeStr, string Dt, Intrinsic IntOp> {
1492 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
1493 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
1494 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
1495 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1498 // ....then also with element size of 8 bits:
1499 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1500 string OpcodeStr, string Dt, Intrinsic IntOp>
1501 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, Dt, IntOp> {
1502 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16D,
1503 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
1507 // Neon 2-register vector intrinsics,
1508 // element sizes of 8, 16 and 32 bits:
1509 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1510 bits<5> op11_7, bit op4,
1511 InstrItinClass itinD, InstrItinClass itinQ,
1512 string OpcodeStr, string Dt, Intrinsic IntOp> {
1513 // 64-bit vector types.
1514 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1515 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
1516 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1517 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
1518 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1519 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
1521 // 128-bit vector types.
1522 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1523 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
1524 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1525 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
1526 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1527 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
1531 // Neon Pairwise long 2-register intrinsics,
1532 // element sizes of 8, 16 and 32 bits:
1533 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1534 bits<5> op11_7, bit op4,
1535 string OpcodeStr, string Dt, Intrinsic IntOp> {
1536 // 64-bit vector types.
1537 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1538 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
1539 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1540 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
1541 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1542 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
1544 // 128-bit vector types.
1545 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1546 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
1547 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1548 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
1549 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1550 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
1554 // Neon Pairwise long 2-register accumulate intrinsics,
1555 // element sizes of 8, 16 and 32 bits:
1556 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1557 bits<5> op11_7, bit op4,
1558 string OpcodeStr, string Dt, Intrinsic IntOp> {
1559 // 64-bit vector types.
1560 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1561 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
1562 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1563 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
1564 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1565 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
1567 // 128-bit vector types.
1568 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1569 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
1570 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1571 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
1572 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1573 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
1577 // Neon 2-register vector shift by immediate,
1578 // element sizes of 8, 16, 32 and 64 bits:
1579 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1580 InstrItinClass itin, string OpcodeStr, string Dt,
1582 // 64-bit vector types.
1583 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
1584 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
1585 let Inst{21-19} = 0b001; // imm6 = 001xxx
1587 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
1588 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
1589 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1591 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
1592 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
1593 let Inst{21} = 0b1; // imm6 = 1xxxxx
1595 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, itin,
1596 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
1599 // 128-bit vector types.
1600 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
1601 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
1602 let Inst{21-19} = 0b001; // imm6 = 001xxx
1604 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
1605 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
1606 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1608 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
1609 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
1610 let Inst{21} = 0b1; // imm6 = 1xxxxx
1612 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, itin,
1613 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
1618 // Neon Shift-Accumulate vector operations,
1619 // element sizes of 8, 16, 32 and 64 bits:
1620 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1621 string OpcodeStr, string Dt, SDNode ShOp> {
1622 // 64-bit vector types.
1623 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1624 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
1625 let Inst{21-19} = 0b001; // imm6 = 001xxx
1627 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1628 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
1629 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1631 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1632 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
1633 let Inst{21} = 0b1; // imm6 = 1xxxxx
1635 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4,
1636 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
1639 // 128-bit vector types.
1640 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1641 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
1642 let Inst{21-19} = 0b001; // imm6 = 001xxx
1644 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1645 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
1646 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1648 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1649 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
1650 let Inst{21} = 0b1; // imm6 = 1xxxxx
1652 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4,
1653 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
1658 // Neon Shift-Insert vector operations,
1659 // element sizes of 8, 16, 32 and 64 bits:
1660 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1661 string OpcodeStr, SDNode ShOp> {
1662 // 64-bit vector types.
1663 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4,
1664 OpcodeStr, "8", v8i8, ShOp> {
1665 let Inst{21-19} = 0b001; // imm6 = 001xxx
1667 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4,
1668 OpcodeStr, "16", v4i16, ShOp> {
1669 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1671 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4,
1672 OpcodeStr, "32", v2i32, ShOp> {
1673 let Inst{21} = 0b1; // imm6 = 1xxxxx
1675 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4,
1676 OpcodeStr, "64", v1i64, ShOp>;
1679 // 128-bit vector types.
1680 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4,
1681 OpcodeStr, "8", v16i8, ShOp> {
1682 let Inst{21-19} = 0b001; // imm6 = 001xxx
1684 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4,
1685 OpcodeStr, "16", v8i16, ShOp> {
1686 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1688 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4,
1689 OpcodeStr, "32", v4i32, ShOp> {
1690 let Inst{21} = 0b1; // imm6 = 1xxxxx
1692 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4,
1693 OpcodeStr, "64", v2i64, ShOp>;
1697 // Neon Shift Long operations,
1698 // element sizes of 8, 16, 32 bits:
1699 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
1700 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
1701 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1702 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
1703 let Inst{21-19} = 0b001; // imm6 = 001xxx
1705 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1706 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
1707 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1709 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1710 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
1711 let Inst{21} = 0b1; // imm6 = 1xxxxx
1715 // Neon Shift Narrow operations,
1716 // element sizes of 16, 32, 64 bits:
1717 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
1718 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
1720 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1721 OpcodeStr, !strconcat(Dt, "16"), v8i8, v8i16, OpNode> {
1722 let Inst{21-19} = 0b001; // imm6 = 001xxx
1724 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1725 OpcodeStr, !strconcat(Dt, "32"), v4i16, v4i32, OpNode> {
1726 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1728 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1729 OpcodeStr, !strconcat(Dt, "64"), v2i32, v2i64, OpNode> {
1730 let Inst{21} = 0b1; // imm6 = 1xxxxx
1734 //===----------------------------------------------------------------------===//
1735 // Instruction Definitions.
1736 //===----------------------------------------------------------------------===//
1738 // Vector Add Operations.
1740 // VADD : Vector Add (integer and floating-point)
1741 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
1743 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
1744 v2f32, v2f32, fadd, 1>;
1745 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
1746 v4f32, v4f32, fadd, 1>;
1747 // VADDL : Vector Add Long (Q = D + D)
1748 defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, IIC_VSHLiD, "vaddl", "s",
1749 int_arm_neon_vaddls, 1>;
1750 defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, IIC_VSHLiD, "vaddl", "u",
1751 int_arm_neon_vaddlu, 1>;
1752 // VADDW : Vector Add Wide (Q = Q + D)
1753 defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw", "s", int_arm_neon_vaddws, 0>;
1754 defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw", "u", int_arm_neon_vaddwu, 0>;
1755 // VHADD : Vector Halving Add
1756 defm VHADDs : N3VInt_QHS<0,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1757 IIC_VBINi4Q, "vhadd", "s", int_arm_neon_vhadds, 1>;
1758 defm VHADDu : N3VInt_QHS<1,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1759 IIC_VBINi4Q, "vhadd", "u", int_arm_neon_vhaddu, 1>;
1760 // VRHADD : Vector Rounding Halving Add
1761 defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1762 IIC_VBINi4Q, "vrhadd", "s", int_arm_neon_vrhadds, 1>;
1763 defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1764 IIC_VBINi4Q, "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
1765 // VQADD : Vector Saturating Add
1766 defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1767 IIC_VBINi4Q, "vqadd", "s", int_arm_neon_vqadds, 1>;
1768 defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1769 IIC_VBINi4Q, "vqadd", "u", int_arm_neon_vqaddu, 1>;
1770 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
1771 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
1772 int_arm_neon_vaddhn, 1>;
1773 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
1774 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
1775 int_arm_neon_vraddhn, 1>;
1777 // Vector Multiply Operations.
1779 // VMUL : Vector Multiply (integer, polynomial and floating-point)
1780 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
1781 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
1782 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16D, "vmul", "p8",
1783 v8i8, v8i8, int_arm_neon_vmulp, 1>;
1784 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16Q, "vmul", "p8",
1785 v16i8, v16i8, int_arm_neon_vmulp, 1>;
1786 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VBIND, "vmul", "f32",
1787 v2f32, v2f32, fmul, 1>;
1788 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VBINQ, "vmul", "f32",
1789 v4f32, v4f32, fmul, 1>;
1790 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
1791 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
1792 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
1795 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
1796 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
1797 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
1798 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1799 (DSubReg_i16_reg imm:$lane))),
1800 (SubReg_i16_lane imm:$lane)))>;
1801 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
1802 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
1803 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
1804 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1805 (DSubReg_i32_reg imm:$lane))),
1806 (SubReg_i32_lane imm:$lane)))>;
1807 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
1808 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
1809 (v4f32 (VMULslfq (v4f32 QPR:$src1),
1810 (v2f32 (EXTRACT_SUBREG QPR:$src2,
1811 (DSubReg_i32_reg imm:$lane))),
1812 (SubReg_i32_lane imm:$lane)))>;
1814 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
1815 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
1816 IIC_VMULi16Q, IIC_VMULi32Q,
1817 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
1818 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
1819 IIC_VMULi16Q, IIC_VMULi32Q,
1820 "vqdmulh", "s", int_arm_neon_vqdmulh>;
1821 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
1822 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
1824 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
1825 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1826 (DSubReg_i16_reg imm:$lane))),
1827 (SubReg_i16_lane imm:$lane)))>;
1828 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
1829 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
1831 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
1832 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1833 (DSubReg_i32_reg imm:$lane))),
1834 (SubReg_i32_lane imm:$lane)))>;
1836 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
1837 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
1838 IIC_VMULi16Q, IIC_VMULi32Q,
1839 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
1840 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
1841 IIC_VMULi16Q, IIC_VMULi32Q,
1842 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
1843 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
1844 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
1846 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
1847 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1848 (DSubReg_i16_reg imm:$lane))),
1849 (SubReg_i16_lane imm:$lane)))>;
1850 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
1851 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
1853 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
1854 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1855 (DSubReg_i32_reg imm:$lane))),
1856 (SubReg_i32_lane imm:$lane)))>;
1858 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
1859 defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, IIC_VMULi16D, "vmull", "s",
1860 int_arm_neon_vmulls, 1>;
1861 defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, IIC_VMULi16D, "vmull", "u",
1862 int_arm_neon_vmullu, 1>;
1863 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
1864 v8i16, v8i8, int_arm_neon_vmullp, 1>;
1865 defm VMULLsls : N3VLIntSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s",
1866 int_arm_neon_vmulls>;
1867 defm VMULLslu : N3VLIntSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u",
1868 int_arm_neon_vmullu>;
1870 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
1871 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, "vqdmull", "s",
1872 int_arm_neon_vqdmull, 1>;
1873 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D, "vqdmull", "s",
1874 int_arm_neon_vqdmull>;
1876 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
1878 // VMLA : Vector Multiply Accumulate (integer and floating-point)
1879 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
1880 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
1881 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
1883 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
1885 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
1886 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
1887 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
1889 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
1890 v4f32, v2f32, fmul, fadd>;
1892 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
1893 (mul (v8i16 QPR:$src2),
1894 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
1895 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
1896 (v4i16 (EXTRACT_SUBREG QPR:$src3,
1897 (DSubReg_i16_reg imm:$lane))),
1898 (SubReg_i16_lane imm:$lane)))>;
1900 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
1901 (mul (v4i32 QPR:$src2),
1902 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
1903 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
1904 (v2i32 (EXTRACT_SUBREG QPR:$src3,
1905 (DSubReg_i32_reg imm:$lane))),
1906 (SubReg_i32_lane imm:$lane)))>;
1908 def : Pat<(v4f32 (fadd (v4f32 QPR:$src1),
1909 (fmul (v4f32 QPR:$src2),
1910 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
1911 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
1913 (v2f32 (EXTRACT_SUBREG QPR:$src3,
1914 (DSubReg_i32_reg imm:$lane))),
1915 (SubReg_i32_lane imm:$lane)))>;
1917 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
1918 defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal", "s", int_arm_neon_vmlals>;
1919 defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal", "u", int_arm_neon_vmlalu>;
1921 defm VMLALsls : N3VLInt3SL_HS<0, 0b0010, "vmlal", "s", int_arm_neon_vmlals>;
1922 defm VMLALslu : N3VLInt3SL_HS<1, 0b0010, "vmlal", "u", int_arm_neon_vmlalu>;
1924 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
1925 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal", "s",
1926 int_arm_neon_vqdmlal>;
1927 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
1929 // VMLS : Vector Multiply Subtract (integer and floating-point)
1930 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
1931 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
1932 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
1934 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
1936 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
1937 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
1938 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
1940 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
1941 v4f32, v2f32, fmul, fsub>;
1943 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
1944 (mul (v8i16 QPR:$src2),
1945 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
1946 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
1947 (v4i16 (EXTRACT_SUBREG QPR:$src3,
1948 (DSubReg_i16_reg imm:$lane))),
1949 (SubReg_i16_lane imm:$lane)))>;
1951 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
1952 (mul (v4i32 QPR:$src2),
1953 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
1954 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
1955 (v2i32 (EXTRACT_SUBREG QPR:$src3,
1956 (DSubReg_i32_reg imm:$lane))),
1957 (SubReg_i32_lane imm:$lane)))>;
1959 def : Pat<(v4f32 (fsub (v4f32 QPR:$src1),
1960 (fmul (v4f32 QPR:$src2),
1961 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
1962 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
1963 (v2f32 (EXTRACT_SUBREG QPR:$src3,
1964 (DSubReg_i32_reg imm:$lane))),
1965 (SubReg_i32_lane imm:$lane)))>;
1967 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
1968 defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl", "s", int_arm_neon_vmlsls>;
1969 defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl", "u", int_arm_neon_vmlslu>;
1971 defm VMLSLsls : N3VLInt3SL_HS<0, 0b0110, "vmlsl", "s", int_arm_neon_vmlsls>;
1972 defm VMLSLslu : N3VLInt3SL_HS<1, 0b0110, "vmlsl", "u", int_arm_neon_vmlslu>;
1974 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
1975 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl", "s",
1976 int_arm_neon_vqdmlsl>;
1977 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
1979 // Vector Subtract Operations.
1981 // VSUB : Vector Subtract (integer and floating-point)
1982 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
1983 "vsub", "i", sub, 0>;
1984 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
1985 v2f32, v2f32, fsub, 0>;
1986 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
1987 v4f32, v4f32, fsub, 0>;
1988 // VSUBL : Vector Subtract Long (Q = D - D)
1989 defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, IIC_VSHLiD, "vsubl", "s",
1990 int_arm_neon_vsubls, 1>;
1991 defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, IIC_VSHLiD, "vsubl", "u",
1992 int_arm_neon_vsublu, 1>;
1993 // VSUBW : Vector Subtract Wide (Q = Q - D)
1994 defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw", "s", int_arm_neon_vsubws, 0>;
1995 defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw", "u", int_arm_neon_vsubwu, 0>;
1996 // VHSUB : Vector Halving Subtract
1997 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D,
1998 IIC_VBINi4Q, IIC_VBINi4Q,
1999 "vhsub", "s", int_arm_neon_vhsubs, 0>;
2000 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D,
2001 IIC_VBINi4Q, IIC_VBINi4Q,
2002 "vhsub", "u", int_arm_neon_vhsubu, 0>;
2003 // VQSUB : Vector Saturing Subtract
2004 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D,
2005 IIC_VBINi4Q, IIC_VBINi4Q,
2006 "vqsub", "s", int_arm_neon_vqsubs, 0>;
2007 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D,
2008 IIC_VBINi4Q, IIC_VBINi4Q,
2009 "vqsub", "u", int_arm_neon_vqsubu, 0>;
2010 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
2011 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
2012 int_arm_neon_vsubhn, 0>;
2013 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
2014 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
2015 int_arm_neon_vrsubhn, 0>;
2017 // Vector Comparisons.
2019 // VCEQ : Vector Compare Equal
2020 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2021 IIC_VBINi4Q, "vceq", "i", NEONvceq, 1>;
2022 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
2024 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
2026 // For disassembly only.
2027 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
2030 // VCGE : Vector Compare Greater Than or Equal
2031 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2032 IIC_VBINi4Q, "vcge", "s", NEONvcge, 0>;
2033 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2034 IIC_VBINi4Q, "vcge", "u", NEONvcgeu, 0>;
2035 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32",
2036 v2i32, v2f32, NEONvcge, 0>;
2037 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
2039 // For disassembly only.
2040 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
2042 // For disassembly only.
2043 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
2046 // VCGT : Vector Compare Greater Than
2047 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2048 IIC_VBINi4Q, "vcgt", "s", NEONvcgt, 0>;
2049 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2050 IIC_VBINi4Q, "vcgt", "u", NEONvcgtu, 0>;
2051 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
2053 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
2055 // For disassembly only.
2056 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
2058 // For disassembly only.
2059 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
2062 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
2063 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, IIC_VBIND, "vacge", "f32",
2064 v2i32, v2f32, int_arm_neon_vacged, 0>;
2065 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, IIC_VBINQ, "vacge", "f32",
2066 v4i32, v4f32, int_arm_neon_vacgeq, 0>;
2067 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
2068 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, IIC_VBIND, "vacgt", "f32",
2069 v2i32, v2f32, int_arm_neon_vacgtd, 0>;
2070 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, IIC_VBINQ, "vacgt", "f32",
2071 v4i32, v4f32, int_arm_neon_vacgtq, 0>;
2072 // VTST : Vector Test Bits
2073 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2074 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
2076 // Vector Bitwise Operations.
2078 // VAND : Vector Bitwise AND
2079 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
2080 v2i32, v2i32, and, 1>;
2081 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
2082 v4i32, v4i32, and, 1>;
2084 // VEOR : Vector Bitwise Exclusive OR
2085 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
2086 v2i32, v2i32, xor, 1>;
2087 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
2088 v4i32, v4i32, xor, 1>;
2090 // VORR : Vector Bitwise OR
2091 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
2092 v2i32, v2i32, or, 1>;
2093 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
2094 v4i32, v4i32, or, 1>;
2096 // VBIC : Vector Bitwise Bit Clear (AND NOT)
2097 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2098 (ins DPR:$src1, DPR:$src2), IIC_VBINiD,
2099 "vbic", "$dst, $src1, $src2", "",
2100 [(set DPR:$dst, (v2i32 (and DPR:$src1,
2101 (vnot_conv DPR:$src2))))]>;
2102 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2103 (ins QPR:$src1, QPR:$src2), IIC_VBINiQ,
2104 "vbic", "$dst, $src1, $src2", "",
2105 [(set QPR:$dst, (v4i32 (and QPR:$src1,
2106 (vnot_conv QPR:$src2))))]>;
2108 // VORN : Vector Bitwise OR NOT
2109 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
2110 (ins DPR:$src1, DPR:$src2), IIC_VBINiD,
2111 "vorn", "$dst, $src1, $src2", "",
2112 [(set DPR:$dst, (v2i32 (or DPR:$src1,
2113 (vnot_conv DPR:$src2))))]>;
2114 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
2115 (ins QPR:$src1, QPR:$src2), IIC_VBINiQ,
2116 "vorn", "$dst, $src1, $src2", "",
2117 [(set QPR:$dst, (v4i32 (or QPR:$src1,
2118 (vnot_conv QPR:$src2))))]>;
2120 // VMVN : Vector Bitwise NOT
2121 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
2122 (outs DPR:$dst), (ins DPR:$src), IIC_VSHLiD,
2123 "vmvn", "$dst, $src", "",
2124 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>;
2125 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
2126 (outs QPR:$dst), (ins QPR:$src), IIC_VSHLiD,
2127 "vmvn", "$dst, $src", "",
2128 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>;
2129 def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>;
2130 def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>;
2132 // VBSL : Vector Bitwise Select
2133 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2134 (ins DPR:$src1, DPR:$src2, DPR:$src3), IIC_VCNTiD,
2135 "vbsl", "$dst, $src2, $src3", "$src1 = $dst",
2137 (v2i32 (or (and DPR:$src2, DPR:$src1),
2138 (and DPR:$src3, (vnot_conv DPR:$src1)))))]>;
2139 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2140 (ins QPR:$src1, QPR:$src2, QPR:$src3), IIC_VCNTiQ,
2141 "vbsl", "$dst, $src2, $src3", "$src1 = $dst",
2143 (v4i32 (or (and QPR:$src2, QPR:$src1),
2144 (and QPR:$src3, (vnot_conv QPR:$src1)))))]>;
2146 // VBIF : Vector Bitwise Insert if False
2147 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
2148 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
2149 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
2150 IIC_VBINiD, "vbif", "$dst, $src2, $src3", "$src1 = $dst",
2151 [/* For disassembly only; pattern left blank */]>;
2152 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
2153 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
2154 IIC_VBINiQ, "vbif", "$dst, $src2, $src3", "$src1 = $dst",
2155 [/* For disassembly only; pattern left blank */]>;
2157 // VBIT : Vector Bitwise Insert if True
2158 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
2159 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
2160 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
2161 IIC_VBINiD, "vbit", "$dst, $src2, $src3", "$src1 = $dst",
2162 [/* For disassembly only; pattern left blank */]>;
2163 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
2164 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
2165 IIC_VBINiQ, "vbit", "$dst, $src2, $src3", "$src1 = $dst",
2166 [/* For disassembly only; pattern left blank */]>;
2168 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
2169 // for equivalent operations with different register constraints; it just
2172 // Vector Absolute Differences.
2174 // VABD : Vector Absolute Difference
2175 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D,
2176 IIC_VBINi4Q, IIC_VBINi4Q,
2177 "vabd", "s", int_arm_neon_vabds, 0>;
2178 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D,
2179 IIC_VBINi4Q, IIC_VBINi4Q,
2180 "vabd", "u", int_arm_neon_vabdu, 0>;
2181 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, IIC_VBIND,
2182 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 0>;
2183 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, IIC_VBINQ,
2184 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 0>;
2186 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
2187 defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, IIC_VBINi4Q,
2188 "vabdl", "s", int_arm_neon_vabdls, 0>;
2189 defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, IIC_VBINi4Q,
2190 "vabdl", "u", int_arm_neon_vabdlu, 0>;
2192 // VABA : Vector Absolute Difference and Accumulate
2193 defm VABAs : N3VInt3_QHS<0,0,0b0111,1, "vaba", "s", int_arm_neon_vabas>;
2194 defm VABAu : N3VInt3_QHS<1,0,0b0111,1, "vaba", "u", int_arm_neon_vabau>;
2196 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
2197 defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal", "s", int_arm_neon_vabals>;
2198 defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal", "u", int_arm_neon_vabalu>;
2200 // Vector Maximum and Minimum.
2202 // VMAX : Vector Maximum
2203 defm VMAXs : N3VInt_QHS<0,0,0b0110,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2204 IIC_VBINi4Q, "vmax", "s", int_arm_neon_vmaxs, 1>;
2205 defm VMAXu : N3VInt_QHS<1,0,0b0110,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2206 IIC_VBINi4Q, "vmax", "u", int_arm_neon_vmaxu, 1>;
2207 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, IIC_VBIND, "vmax", "f32",
2208 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
2209 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, IIC_VBINQ, "vmax", "f32",
2210 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
2212 // VMIN : Vector Minimum
2213 defm VMINs : N3VInt_QHS<0,0,0b0110,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2214 IIC_VBINi4Q, "vmin", "s", int_arm_neon_vmins, 1>;
2215 defm VMINu : N3VInt_QHS<1,0,0b0110,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2216 IIC_VBINi4Q, "vmin", "u", int_arm_neon_vminu, 1>;
2217 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, IIC_VBIND, "vmin", "f32",
2218 v2f32, v2f32, int_arm_neon_vmins, 1>;
2219 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, IIC_VBINQ, "vmin", "f32",
2220 v4f32, v4f32, int_arm_neon_vmins, 1>;
2222 // Vector Pairwise Operations.
2224 // VPADD : Vector Pairwise Add
2225 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, IIC_VBINiD, "vpadd", "i8",
2226 v8i8, v8i8, int_arm_neon_vpadd, 0>;
2227 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, IIC_VBINiD, "vpadd", "i16",
2228 v4i16, v4i16, int_arm_neon_vpadd, 0>;
2229 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, IIC_VBINiD, "vpadd", "i32",
2230 v2i32, v2i32, int_arm_neon_vpadd, 0>;
2231 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, IIC_VBIND, "vpadd", "f32",
2232 v2f32, v2f32, int_arm_neon_vpadd, 0>;
2234 // VPADDL : Vector Pairwise Add Long
2235 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
2236 int_arm_neon_vpaddls>;
2237 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
2238 int_arm_neon_vpaddlu>;
2240 // VPADAL : Vector Pairwise Add and Accumulate Long
2241 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
2242 int_arm_neon_vpadals>;
2243 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
2244 int_arm_neon_vpadalu>;
2246 // VPMAX : Vector Pairwise Maximum
2247 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax", "s8",
2248 v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
2249 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax", "s16",
2250 v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
2251 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax", "s32",
2252 v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
2253 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax", "u8",
2254 v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
2255 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax", "u16",
2256 v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
2257 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax", "u32",
2258 v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
2259 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, IIC_VBINi4D, "vpmax", "f32",
2260 v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
2262 // VPMIN : Vector Pairwise Minimum
2263 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin", "s8",
2264 v8i8, v8i8, int_arm_neon_vpmins, 0>;
2265 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin", "s16",
2266 v4i16, v4i16, int_arm_neon_vpmins, 0>;
2267 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin", "s32",
2268 v2i32, v2i32, int_arm_neon_vpmins, 0>;
2269 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin", "u8",
2270 v8i8, v8i8, int_arm_neon_vpminu, 0>;
2271 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin", "u16",
2272 v4i16, v4i16, int_arm_neon_vpminu, 0>;
2273 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin", "u32",
2274 v2i32, v2i32, int_arm_neon_vpminu, 0>;
2275 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, IIC_VBINi4D, "vpmin", "f32",
2276 v2f32, v2f32, int_arm_neon_vpmins, 0>;
2278 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
2280 // VRECPE : Vector Reciprocal Estimate
2281 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
2282 IIC_VUNAD, "vrecpe", "u32",
2283 v2i32, v2i32, int_arm_neon_vrecpe>;
2284 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
2285 IIC_VUNAQ, "vrecpe", "u32",
2286 v4i32, v4i32, int_arm_neon_vrecpe>;
2287 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
2288 IIC_VUNAD, "vrecpe", "f32",
2289 v2f32, v2f32, int_arm_neon_vrecpe>;
2290 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
2291 IIC_VUNAQ, "vrecpe", "f32",
2292 v4f32, v4f32, int_arm_neon_vrecpe>;
2294 // VRECPS : Vector Reciprocal Step
2295 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1,
2296 IIC_VRECSD, "vrecps", "f32",
2297 v2f32, v2f32, int_arm_neon_vrecps, 1>;
2298 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1,
2299 IIC_VRECSQ, "vrecps", "f32",
2300 v4f32, v4f32, int_arm_neon_vrecps, 1>;
2302 // VRSQRTE : Vector Reciprocal Square Root Estimate
2303 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
2304 IIC_VUNAD, "vrsqrte", "u32",
2305 v2i32, v2i32, int_arm_neon_vrsqrte>;
2306 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
2307 IIC_VUNAQ, "vrsqrte", "u32",
2308 v4i32, v4i32, int_arm_neon_vrsqrte>;
2309 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
2310 IIC_VUNAD, "vrsqrte", "f32",
2311 v2f32, v2f32, int_arm_neon_vrsqrte>;
2312 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
2313 IIC_VUNAQ, "vrsqrte", "f32",
2314 v4f32, v4f32, int_arm_neon_vrsqrte>;
2316 // VRSQRTS : Vector Reciprocal Square Root Step
2317 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1,
2318 IIC_VRECSD, "vrsqrts", "f32",
2319 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
2320 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1,
2321 IIC_VRECSQ, "vrsqrts", "f32",
2322 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
2326 // VSHL : Vector Shift
2327 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
2328 IIC_VSHLiQ, "vshl", "s", int_arm_neon_vshifts, 0>;
2329 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
2330 IIC_VSHLiQ, "vshl", "u", int_arm_neon_vshiftu, 0>;
2331 // VSHL : Vector Shift Left (Immediate)
2332 defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
2333 // VSHR : Vector Shift Right (Immediate)
2334 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", NEONvshrs>;
2335 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", NEONvshru>;
2337 // VSHLL : Vector Shift Left Long
2338 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
2339 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
2341 // VSHLL : Vector Shift Left Long (with maximum shift count)
2342 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
2343 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
2344 ValueType OpTy, SDNode OpNode>
2345 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
2346 ResTy, OpTy, OpNode> {
2347 let Inst{21-16} = op21_16;
2349 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
2350 v8i16, v8i8, NEONvshlli>;
2351 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
2352 v4i32, v4i16, NEONvshlli>;
2353 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
2354 v2i64, v2i32, NEONvshlli>;
2356 // VSHRN : Vector Shift Right and Narrow
2357 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
2360 // VRSHL : Vector Rounding Shift
2361 defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2362 IIC_VSHLi4Q, "vrshl", "s", int_arm_neon_vrshifts,0>;
2363 defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2364 IIC_VSHLi4Q, "vrshl", "u", int_arm_neon_vrshiftu,0>;
2365 // VRSHR : Vector Rounding Shift Right
2366 defm VRSHRs : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs>;
2367 defm VRSHRu : N2VSh_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", NEONvrshru>;
2369 // VRSHRN : Vector Rounding Shift Right and Narrow
2370 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
2373 // VQSHL : Vector Saturating Shift
2374 defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2375 IIC_VSHLi4Q, "vqshl", "s", int_arm_neon_vqshifts,0>;
2376 defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2377 IIC_VSHLi4Q, "vqshl", "u", int_arm_neon_vqshiftu,0>;
2378 // VQSHL : Vector Saturating Shift Left (Immediate)
2379 defm VQSHLsi : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s", NEONvqshls>;
2380 defm VQSHLui : N2VSh_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u", NEONvqshlu>;
2381 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
2382 defm VQSHLsu : N2VSh_QHSD<1,1,0b0110,1, IIC_VSHLi4D, "vqshlu","s",NEONvqshlsu>;
2384 // VQSHRN : Vector Saturating Shift Right and Narrow
2385 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
2387 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
2390 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
2391 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
2394 // VQRSHL : Vector Saturating Rounding Shift
2395 defm VQRSHLs : N3VInt_QHSD<0,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2396 IIC_VSHLi4Q, "vqrshl", "s",
2397 int_arm_neon_vqrshifts, 0>;
2398 defm VQRSHLu : N3VInt_QHSD<1,0,0b0101,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2399 IIC_VSHLi4Q, "vqrshl", "u",
2400 int_arm_neon_vqrshiftu, 0>;
2402 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
2403 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
2405 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
2408 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
2409 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
2412 // VSRA : Vector Shift Right and Accumulate
2413 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
2414 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
2415 // VRSRA : Vector Rounding Shift Right and Accumulate
2416 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
2417 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
2419 // VSLI : Vector Shift Left and Insert
2420 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli", NEONvsli>;
2421 // VSRI : Vector Shift Right and Insert
2422 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri", NEONvsri>;
2424 // Vector Absolute and Saturating Absolute.
2426 // VABS : Vector Absolute Value
2427 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
2428 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
2430 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2431 IIC_VUNAD, "vabs", "f32",
2432 v2f32, v2f32, int_arm_neon_vabs>;
2433 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2434 IIC_VUNAQ, "vabs", "f32",
2435 v4f32, v4f32, int_arm_neon_vabs>;
2437 // VQABS : Vector Saturating Absolute Value
2438 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
2439 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
2440 int_arm_neon_vqabs>;
2444 def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
2445 def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>;
2447 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
2448 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
2449 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
2450 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>;
2451 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
2452 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
2453 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
2454 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>;
2456 // VNEG : Vector Negate
2457 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
2458 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
2459 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
2460 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
2461 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
2462 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
2464 // VNEG : Vector Negate (floating-point)
2465 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
2466 (outs DPR:$dst), (ins DPR:$src), IIC_VUNAD,
2467 "vneg", "f32", "$dst, $src", "",
2468 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
2469 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
2470 (outs QPR:$dst), (ins QPR:$src), IIC_VUNAQ,
2471 "vneg", "f32", "$dst, $src", "",
2472 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
2474 def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
2475 def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
2476 def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>;
2477 def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>;
2478 def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>;
2479 def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>;
2481 // VQNEG : Vector Saturating Negate
2482 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
2483 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
2484 int_arm_neon_vqneg>;
2486 // Vector Bit Counting Operations.
2488 // VCLS : Vector Count Leading Sign Bits
2489 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
2490 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
2492 // VCLZ : Vector Count Leading Zeros
2493 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
2494 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
2496 // VCNT : Vector Count One Bits
2497 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2498 IIC_VCNTiD, "vcnt", "8",
2499 v8i8, v8i8, int_arm_neon_vcnt>;
2500 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2501 IIC_VCNTiQ, "vcnt", "8",
2502 v16i8, v16i8, int_arm_neon_vcnt>;
2504 // Vector Move Operations.
2506 // VMOV : Vector Move (Register)
2508 def VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
2509 IIC_VMOVD, "vmov", "$dst, $src", "", []>;
2510 def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
2511 IIC_VMOVD, "vmov", "$dst, $src", "", []>;
2513 // VMOV : Vector Move (Immediate)
2515 // VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
2516 def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
2517 return ARM::getVMOVImm(N, 1, *CurDAG);
2519 def vmovImm8 : PatLeaf<(build_vector), [{
2520 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
2523 // VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
2524 def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
2525 return ARM::getVMOVImm(N, 2, *CurDAG);
2527 def vmovImm16 : PatLeaf<(build_vector), [{
2528 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
2529 }], VMOV_get_imm16>;
2531 // VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
2532 def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
2533 return ARM::getVMOVImm(N, 4, *CurDAG);
2535 def vmovImm32 : PatLeaf<(build_vector), [{
2536 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
2537 }], VMOV_get_imm32>;
2539 // VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
2540 def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
2541 return ARM::getVMOVImm(N, 8, *CurDAG);
2543 def vmovImm64 : PatLeaf<(build_vector), [{
2544 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
2545 }], VMOV_get_imm64>;
2547 // Note: Some of the cmode bits in the following VMOV instructions need to
2548 // be encoded based on the immed values.
2550 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
2551 (ins h8imm:$SIMM), IIC_VMOVImm,
2552 "vmov", "i8", "$dst, $SIMM", "",
2553 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
2554 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
2555 (ins h8imm:$SIMM), IIC_VMOVImm,
2556 "vmov", "i8", "$dst, $SIMM", "",
2557 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
2559 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,?}, 0, 0, {?}, 1, (outs DPR:$dst),
2560 (ins h16imm:$SIMM), IIC_VMOVImm,
2561 "vmov", "i16", "$dst, $SIMM", "",
2562 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
2563 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,?}, 0, 1, {?}, 1, (outs QPR:$dst),
2564 (ins h16imm:$SIMM), IIC_VMOVImm,
2565 "vmov", "i16", "$dst, $SIMM", "",
2566 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
2568 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, {?}, 1, (outs DPR:$dst),
2569 (ins h32imm:$SIMM), IIC_VMOVImm,
2570 "vmov", "i32", "$dst, $SIMM", "",
2571 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
2572 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, {?}, 1, (outs QPR:$dst),
2573 (ins h32imm:$SIMM), IIC_VMOVImm,
2574 "vmov", "i32", "$dst, $SIMM", "",
2575 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
2577 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
2578 (ins h64imm:$SIMM), IIC_VMOVImm,
2579 "vmov", "i64", "$dst, $SIMM", "",
2580 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
2581 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
2582 (ins h64imm:$SIMM), IIC_VMOVImm,
2583 "vmov", "i64", "$dst, $SIMM", "",
2584 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
2586 // VMOV : Vector Get Lane (move scalar to ARM core register)
2588 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
2589 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2590 IIC_VMOVSI, "vmov", "s8", "$dst, $src[$lane]",
2591 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
2593 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
2594 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2595 IIC_VMOVSI, "vmov", "s16", "$dst, $src[$lane]",
2596 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
2598 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
2599 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2600 IIC_VMOVSI, "vmov", "u8", "$dst, $src[$lane]",
2601 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
2603 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
2604 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2605 IIC_VMOVSI, "vmov", "u16", "$dst, $src[$lane]",
2606 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
2608 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
2609 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2610 IIC_VMOVSI, "vmov", "32", "$dst, $src[$lane]",
2611 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
2613 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
2614 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
2615 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2616 (DSubReg_i8_reg imm:$lane))),
2617 (SubReg_i8_lane imm:$lane))>;
2618 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
2619 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2620 (DSubReg_i16_reg imm:$lane))),
2621 (SubReg_i16_lane imm:$lane))>;
2622 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
2623 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2624 (DSubReg_i8_reg imm:$lane))),
2625 (SubReg_i8_lane imm:$lane))>;
2626 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
2627 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2628 (DSubReg_i16_reg imm:$lane))),
2629 (SubReg_i16_lane imm:$lane))>;
2630 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
2631 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
2632 (DSubReg_i32_reg imm:$lane))),
2633 (SubReg_i32_lane imm:$lane))>;
2634 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
2635 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
2636 (SSubReg_f32_reg imm:$src2))>;
2637 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
2638 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
2639 (SSubReg_f32_reg imm:$src2))>;
2640 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
2641 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2642 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
2643 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2646 // VMOV : Vector Set Lane (move ARM core register to scalar)
2648 let Constraints = "$src1 = $dst" in {
2649 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$dst),
2650 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2651 IIC_VMOVISL, "vmov", "8", "$dst[$lane], $src2",
2652 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
2653 GPR:$src2, imm:$lane))]>;
2654 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$dst),
2655 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2656 IIC_VMOVISL, "vmov", "16", "$dst[$lane], $src2",
2657 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
2658 GPR:$src2, imm:$lane))]>;
2659 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$dst),
2660 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2661 IIC_VMOVISL, "vmov", "32", "$dst[$lane], $src2",
2662 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
2663 GPR:$src2, imm:$lane))]>;
2665 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
2666 (v16i8 (INSERT_SUBREG QPR:$src1,
2667 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
2668 (DSubReg_i8_reg imm:$lane))),
2669 GPR:$src2, (SubReg_i8_lane imm:$lane)),
2670 (DSubReg_i8_reg imm:$lane)))>;
2671 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
2672 (v8i16 (INSERT_SUBREG QPR:$src1,
2673 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
2674 (DSubReg_i16_reg imm:$lane))),
2675 GPR:$src2, (SubReg_i16_lane imm:$lane)),
2676 (DSubReg_i16_reg imm:$lane)))>;
2677 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
2678 (v4i32 (INSERT_SUBREG QPR:$src1,
2679 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
2680 (DSubReg_i32_reg imm:$lane))),
2681 GPR:$src2, (SubReg_i32_lane imm:$lane)),
2682 (DSubReg_i32_reg imm:$lane)))>;
2684 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
2685 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
2686 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
2687 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
2688 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
2689 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
2691 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
2692 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
2693 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
2694 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
2696 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
2697 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
2698 def : Pat<(v2f64 (scalar_to_vector DPR:$src)),
2699 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, arm_dsubreg_0)>;
2700 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
2701 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
2703 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
2704 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2705 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
2706 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2707 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
2708 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2710 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
2711 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
2712 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2714 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
2715 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
2716 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2718 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
2719 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
2720 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2723 // VDUP : Vector Duplicate (from ARM core register to all elements)
2725 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
2726 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
2727 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
2728 [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
2729 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
2730 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
2731 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
2732 [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
2734 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
2735 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
2736 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
2737 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
2738 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
2739 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
2741 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
2742 IIC_VMOVIS, "vdup", "32", "$dst, $src",
2743 [(set DPR:$dst, (v2f32 (NEONvdup
2744 (f32 (bitconvert GPR:$src)))))]>;
2745 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
2746 IIC_VMOVIS, "vdup", "32", "$dst, $src",
2747 [(set QPR:$dst, (v4f32 (NEONvdup
2748 (f32 (bitconvert GPR:$src)))))]>;
2750 // VDUP : Vector Duplicate Lane (from scalar to all elements)
2752 class VDUPLND<bits<2> op19_18, bits<2> op17_16,
2753 string OpcodeStr, string Dt, ValueType Ty>
2754 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
2755 (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
2756 OpcodeStr, Dt, "$dst, $src[$lane]", "",
2757 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
2759 class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, string Dt,
2760 ValueType ResTy, ValueType OpTy>
2761 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
2762 (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
2763 OpcodeStr, Dt, "$dst, $src[$lane]", "",
2764 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src), imm:$lane)))]>;
2766 // Inst{19-16} is partially specified depending on the element size.
2768 def VDUPLN8d : VDUPLND<{?,?}, {?,1}, "vdup", "8", v8i8>;
2769 def VDUPLN16d : VDUPLND<{?,?}, {1,0}, "vdup", "16", v4i16>;
2770 def VDUPLN32d : VDUPLND<{?,1}, {0,0}, "vdup", "32", v2i32>;
2771 def VDUPLNfd : VDUPLND<{?,1}, {0,0}, "vdup", "32", v2f32>;
2772 def VDUPLN8q : VDUPLNQ<{?,?}, {?,1}, "vdup", "8", v16i8, v8i8>;
2773 def VDUPLN16q : VDUPLNQ<{?,?}, {1,0}, "vdup", "16", v8i16, v4i16>;
2774 def VDUPLN32q : VDUPLNQ<{?,1}, {0,0}, "vdup", "32", v4i32, v2i32>;
2775 def VDUPLNfq : VDUPLNQ<{?,1}, {0,0}, "vdup", "32", v4f32, v2f32>;
2777 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
2778 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
2779 (DSubReg_i8_reg imm:$lane))),
2780 (SubReg_i8_lane imm:$lane)))>;
2781 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
2782 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
2783 (DSubReg_i16_reg imm:$lane))),
2784 (SubReg_i16_lane imm:$lane)))>;
2785 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
2786 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
2787 (DSubReg_i32_reg imm:$lane))),
2788 (SubReg_i32_lane imm:$lane)))>;
2789 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
2790 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
2791 (DSubReg_i32_reg imm:$lane))),
2792 (SubReg_i32_lane imm:$lane)))>;
2794 def VDUPfdf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 0, 0,
2795 (outs DPR:$dst), (ins SPR:$src),
2796 IIC_VMOVD, "vdup", "32", "$dst, ${src:lane}", "",
2797 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
2799 def VDUPfqf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 1, 0,
2800 (outs QPR:$dst), (ins SPR:$src),
2801 IIC_VMOVD, "vdup", "32", "$dst, ${src:lane}", "",
2802 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
2804 def : Pat<(v2i64 (NEONvduplane (v2i64 QPR:$src), imm:$lane)),
2805 (INSERT_SUBREG QPR:$src,
2806 (i64 (EXTRACT_SUBREG QPR:$src,
2807 (DSubReg_f64_reg imm:$lane))),
2808 (DSubReg_f64_other_reg imm:$lane))>;
2809 def : Pat<(v2f64 (NEONvduplane (v2f64 QPR:$src), imm:$lane)),
2810 (INSERT_SUBREG QPR:$src,
2811 (f64 (EXTRACT_SUBREG QPR:$src,
2812 (DSubReg_f64_reg imm:$lane))),
2813 (DSubReg_f64_other_reg imm:$lane))>;
2815 // VMOVN : Vector Narrowing Move
2816 defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVD,
2817 "vmovn", "i", int_arm_neon_vmovn>;
2818 // VQMOVN : Vector Saturating Narrowing Move
2819 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
2820 "vqmovn", "s", int_arm_neon_vqmovns>;
2821 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
2822 "vqmovn", "u", int_arm_neon_vqmovnu>;
2823 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
2824 "vqmovun", "s", int_arm_neon_vqmovnsu>;
2825 // VMOVL : Vector Lengthening Move
2826 defm VMOVLs : N2VLInt_QHS<0b01,0b10100,0,1, "vmovl", "s",
2827 int_arm_neon_vmovls>;
2828 defm VMOVLu : N2VLInt_QHS<0b11,0b10100,0,1, "vmovl", "u",
2829 int_arm_neon_vmovlu>;
2831 // Vector Conversions.
2833 // VCVT : Vector Convert Between Floating-Point and Integers
2834 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
2835 v2i32, v2f32, fp_to_sint>;
2836 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
2837 v2i32, v2f32, fp_to_uint>;
2838 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
2839 v2f32, v2i32, sint_to_fp>;
2840 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
2841 v2f32, v2i32, uint_to_fp>;
2843 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
2844 v4i32, v4f32, fp_to_sint>;
2845 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
2846 v4i32, v4f32, fp_to_uint>;
2847 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
2848 v4f32, v4i32, sint_to_fp>;
2849 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
2850 v4f32, v4i32, uint_to_fp>;
2852 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
2853 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
2854 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
2855 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
2856 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
2857 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
2858 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
2859 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
2860 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
2862 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
2863 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
2864 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
2865 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
2866 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
2867 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
2868 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
2869 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
2873 // VREV64 : Vector Reverse elements within 64-bit doublewords
2875 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
2876 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
2877 (ins DPR:$src), IIC_VMOVD,
2878 OpcodeStr, Dt, "$dst, $src", "",
2879 [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
2880 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
2881 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
2882 (ins QPR:$src), IIC_VMOVD,
2883 OpcodeStr, Dt, "$dst, $src", "",
2884 [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
2886 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
2887 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
2888 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
2889 def VREV64df : VREV64D<0b10, "vrev64", "32", v2f32>;
2891 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
2892 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
2893 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
2894 def VREV64qf : VREV64Q<0b10, "vrev64", "32", v4f32>;
2896 // VREV32 : Vector Reverse elements within 32-bit words
2898 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
2899 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
2900 (ins DPR:$src), IIC_VMOVD,
2901 OpcodeStr, Dt, "$dst, $src", "",
2902 [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
2903 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
2904 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
2905 (ins QPR:$src), IIC_VMOVD,
2906 OpcodeStr, Dt, "$dst, $src", "",
2907 [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
2909 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
2910 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
2912 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
2913 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
2915 // VREV16 : Vector Reverse elements within 16-bit halfwords
2917 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
2918 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
2919 (ins DPR:$src), IIC_VMOVD,
2920 OpcodeStr, Dt, "$dst, $src", "",
2921 [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
2922 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
2923 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
2924 (ins QPR:$src), IIC_VMOVD,
2925 OpcodeStr, Dt, "$dst, $src", "",
2926 [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
2928 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
2929 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
2931 // Other Vector Shuffles.
2933 // VEXT : Vector Extract
2935 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
2936 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$dst),
2937 (ins DPR:$lhs, DPR:$rhs, i32imm:$index), IIC_VEXTD,
2938 OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
2939 [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
2940 (Ty DPR:$rhs), imm:$index)))]>;
2942 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
2943 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$dst),
2944 (ins QPR:$lhs, QPR:$rhs, i32imm:$index), IIC_VEXTQ,
2945 OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
2946 [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
2947 (Ty QPR:$rhs), imm:$index)))]>;
2949 def VEXTd8 : VEXTd<"vext", "8", v8i8>;
2950 def VEXTd16 : VEXTd<"vext", "16", v4i16>;
2951 def VEXTd32 : VEXTd<"vext", "32", v2i32>;
2952 def VEXTdf : VEXTd<"vext", "32", v2f32>;
2954 def VEXTq8 : VEXTq<"vext", "8", v16i8>;
2955 def VEXTq16 : VEXTq<"vext", "16", v8i16>;
2956 def VEXTq32 : VEXTq<"vext", "32", v4i32>;
2957 def VEXTqf : VEXTq<"vext", "32", v4f32>;
2959 // VTRN : Vector Transpose
2961 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
2962 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
2963 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
2965 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
2966 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
2967 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
2969 // VUZP : Vector Unzip (Deinterleave)
2971 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
2972 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
2973 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
2975 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
2976 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
2977 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
2979 // VZIP : Vector Zip (Interleave)
2981 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
2982 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
2983 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
2985 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
2986 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
2987 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
2989 // Vector Table Lookup and Table Extension.
2991 // VTBL : Vector Table Lookup
2993 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
2994 (ins DPR:$tbl1, DPR:$src), IIC_VTB1,
2995 "vtbl", "8", "$dst, \\{$tbl1\\}, $src", "",
2996 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
2997 let hasExtraSrcRegAllocReq = 1 in {
2999 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
3000 (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTB2,
3001 "vtbl", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "",
3002 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl2
3003 DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
3005 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
3006 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTB3,
3007 "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src", "",
3008 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl3
3009 DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
3011 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
3012 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTB4,
3013 "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src", "",
3014 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl4 DPR:$tbl1, DPR:$tbl2,
3015 DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
3016 } // hasExtraSrcRegAllocReq = 1
3018 // VTBX : Vector Table Extension
3020 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
3021 (ins DPR:$orig, DPR:$tbl1, DPR:$src), IIC_VTBX1,
3022 "vtbx", "8", "$dst, \\{$tbl1\\}, $src", "$orig = $dst",
3023 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
3024 DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
3025 let hasExtraSrcRegAllocReq = 1 in {
3027 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
3028 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTBX2,
3029 "vtbx", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "$orig = $dst",
3030 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx2
3031 DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
3033 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
3034 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTBX3,
3035 "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src", "$orig = $dst",
3036 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx3 DPR:$orig, DPR:$tbl1,
3037 DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
3039 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
3040 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTBX4,
3041 "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src",
3043 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx4 DPR:$orig, DPR:$tbl1,
3044 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
3045 } // hasExtraSrcRegAllocReq = 1
3047 //===----------------------------------------------------------------------===//
3048 // NEON instructions for single-precision FP math
3049 //===----------------------------------------------------------------------===//
3051 class N2VSPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
3052 : NEONFPPat<(ResTy (OpNode SPR:$a)),
3053 (EXTRACT_SUBREG (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)),
3054 SPR:$a, arm_ssubreg_0)),
3057 class N3VSPat<SDNode OpNode, NeonI Inst>
3058 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
3059 (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3060 SPR:$a, arm_ssubreg_0),
3061 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3062 SPR:$b, arm_ssubreg_0)),
3065 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
3066 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
3067 (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3068 SPR:$acc, arm_ssubreg_0),
3069 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3070 SPR:$a, arm_ssubreg_0),
3071 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3072 SPR:$b, arm_ssubreg_0)),
3075 // These need separate instructions because they must use DPR_VFP2 register
3076 // class which have SPR sub-registers.
3078 // Vector Add Operations used for single-precision FP
3079 let neverHasSideEffects = 1 in
3080 def VADDfd_sfp : N3VS<0,0,0b00,0b1101,0, "vadd", "f32", v2f32, v2f32, fadd, 1>;
3081 def : N3VSPat<fadd, VADDfd_sfp>;
3083 // Vector Sub Operations used for single-precision FP
3084 let neverHasSideEffects = 1 in
3085 def VSUBfd_sfp : N3VS<0,0,0b10,0b1101,0, "vsub", "f32", v2f32, v2f32, fsub, 0>;
3086 def : N3VSPat<fsub, VSUBfd_sfp>;
3088 // Vector Multiply Operations used for single-precision FP
3089 let neverHasSideEffects = 1 in
3090 def VMULfd_sfp : N3VS<1,0,0b00,0b1101,1, "vmul", "f32", v2f32, v2f32, fmul, 1>;
3091 def : N3VSPat<fmul, VMULfd_sfp>;
3093 // Vector Multiply-Accumulate/Subtract used for single-precision FP
3094 // vml[as].f32 can cause 4-8 cycle stalls in following ASIMD instructions, so
3095 // we want to avoid them for now. e.g., alternating vmla/vadd instructions.
3097 //let neverHasSideEffects = 1 in
3098 //def VMLAfd_sfp : N3VSMulOp<0,0,0b00,0b1101,1, IIC_VMACD, "vmla", "f32",
3099 // v2f32, fmul, fadd>;
3100 //def : N3VSMulOpPat<fmul, fadd, VMLAfd_sfp>;
3102 //let neverHasSideEffects = 1 in
3103 //def VMLSfd_sfp : N3VSMulOp<0,0,0b10,0b1101,1, IIC_VMACD, "vmls", "f32",
3104 // v2f32, fmul, fsub>;
3105 //def : N3VSMulOpPat<fmul, fsub, VMLSfd_sfp>;
3107 // Vector Absolute used for single-precision FP
3108 let neverHasSideEffects = 1 in
3109 def VABSfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01110, 0, 0,
3110 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
3111 "vabs", "f32", "$dst, $src", "", []>;
3112 def : N2VSPat<fabs, f32, v2f32, VABSfd_sfp>;
3114 // Vector Negate used for single-precision FP
3115 let neverHasSideEffects = 1 in
3116 def VNEGfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
3117 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
3118 "vneg", "f32", "$dst, $src", "", []>;
3119 def : N2VSPat<fneg, f32, v2f32, VNEGfd_sfp>;
3121 // Vector Maximum used for single-precision FP
3122 let neverHasSideEffects = 1 in
3123 def VMAXfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
3124 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), IIC_VBIND,
3125 "vmax", "f32", "$dst, $src1, $src2", "", []>;
3126 def : N3VSPat<NEONfmax, VMAXfd_sfp>;
3128 // Vector Minimum used for single-precision FP
3129 let neverHasSideEffects = 1 in
3130 def VMINfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
3131 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), IIC_VBIND,
3132 "vmin", "f32", "$dst, $src1, $src2", "", []>;
3133 def : N3VSPat<NEONfmin, VMINfd_sfp>;
3135 // Vector Convert between single-precision FP and integer
3136 let neverHasSideEffects = 1 in
3137 def VCVTf2sd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3138 v2i32, v2f32, fp_to_sint>;
3139 def : N2VSPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
3141 let neverHasSideEffects = 1 in
3142 def VCVTf2ud_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3143 v2i32, v2f32, fp_to_uint>;
3144 def : N2VSPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
3146 let neverHasSideEffects = 1 in
3147 def VCVTs2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3148 v2f32, v2i32, sint_to_fp>;
3149 def : N2VSPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
3151 let neverHasSideEffects = 1 in
3152 def VCVTu2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3153 v2f32, v2i32, uint_to_fp>;
3154 def : N2VSPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
3156 //===----------------------------------------------------------------------===//
3157 // Non-Instruction Patterns
3158 //===----------------------------------------------------------------------===//
3161 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
3162 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
3163 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
3164 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
3165 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
3166 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
3167 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
3168 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
3169 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
3170 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
3171 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
3172 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
3173 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
3174 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
3175 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
3176 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
3177 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
3178 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
3179 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
3180 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
3181 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
3182 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
3183 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
3184 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
3185 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
3186 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
3187 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
3188 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
3189 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
3190 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
3192 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
3193 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
3194 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
3195 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
3196 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
3197 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
3198 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
3199 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
3200 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
3201 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
3202 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
3203 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
3204 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
3205 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
3206 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
3207 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
3208 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
3209 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
3210 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
3211 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
3212 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
3213 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
3214 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
3215 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
3216 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
3217 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
3218 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
3219 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
3220 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
3221 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;