1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
70 // VDUPLANE can produce a quad-register result from a double-register source,
71 // so the result is not constrained to match the source.
72 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
73 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
76 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
77 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
78 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
80 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
81 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
82 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
83 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
85 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
86 SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>]>;
87 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
88 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
89 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
91 //===----------------------------------------------------------------------===//
92 // NEON operand definitions
93 //===----------------------------------------------------------------------===//
95 // addrmode_neonldstm := reg
97 /* TODO: Take advantage of vldm.
98 def addrmode_neonldstm : Operand<i32>,
99 ComplexPattern<i32, 2, "SelectAddrModeNeonLdStM", []> {
100 let PrintMethod = "printAddrNeonLdStMOperand";
101 let MIOperandInfo = (ops GPR, i32imm);
105 def h8imm : Operand<i8> {
106 let PrintMethod = "printHex8ImmOperand";
108 def h16imm : Operand<i16> {
109 let PrintMethod = "printHex16ImmOperand";
111 def h32imm : Operand<i32> {
112 let PrintMethod = "printHex32ImmOperand";
114 def h64imm : Operand<i64> {
115 let PrintMethod = "printHex64ImmOperand";
118 //===----------------------------------------------------------------------===//
119 // NEON load / store instructions
120 //===----------------------------------------------------------------------===//
122 /* TODO: Take advantage of vldm.
123 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
124 def VLDMD : NI<(outs),
125 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
127 "vldm", "${addr:submode} ${addr:base}, $dst1",
129 let Inst{27-25} = 0b110;
131 let Inst{11-9} = 0b101;
134 def VLDMS : NI<(outs),
135 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
137 "vldm", "${addr:submode} ${addr:base}, $dst1",
139 let Inst{27-25} = 0b110;
141 let Inst{11-9} = 0b101;
146 // Use vldmia to load a Q register as a D register pair.
147 def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr),
149 "vldmia", "\t$addr, ${dst:dregpair}",
150 [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]> {
151 let Inst{27-25} = 0b110;
152 let Inst{24} = 0; // P bit
153 let Inst{23} = 1; // U bit
155 let Inst{11-9} = 0b101;
158 // Use vstmia to store a Q register as a D register pair.
159 def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr),
161 "vstmia", "\t$addr, ${src:dregpair}",
162 [(store (v2f64 QPR:$src), addrmode4:$addr)]> {
163 let Inst{27-25} = 0b110;
164 let Inst{24} = 0; // P bit
165 let Inst{23} = 1; // U bit
167 let Inst{11-9} = 0b101;
170 // VLD1 : Vector Load (multiple single elements)
171 class VLD1D<bits<4> op7_4, string OpcodeStr, ValueType Ty, Intrinsic IntOp>
172 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst), (ins addrmode6:$addr), IIC_VLD1,
173 OpcodeStr, "\t\\{$dst\\}, $addr", "",
174 [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
175 class VLD1Q<bits<4> op7_4, string OpcodeStr, ValueType Ty, Intrinsic IntOp>
176 : NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst), (ins addrmode6:$addr), IIC_VLD1,
177 OpcodeStr, "\t${dst:dregpair}, $addr", "",
178 [(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
180 def VLD1d8 : VLD1D<0b0000, "vld1.8", v8i8, int_arm_neon_vld1>;
181 def VLD1d16 : VLD1D<0b0100, "vld1.16", v4i16, int_arm_neon_vld1>;
182 def VLD1d32 : VLD1D<0b1000, "vld1.32", v2i32, int_arm_neon_vld1>;
183 def VLD1df : VLD1D<0b1000, "vld1.32", v2f32, int_arm_neon_vld1>;
184 def VLD1d64 : VLD1D<0b1100, "vld1.64", v1i64, int_arm_neon_vld1>;
186 def VLD1q8 : VLD1Q<0b0000, "vld1.8", v16i8, int_arm_neon_vld1>;
187 def VLD1q16 : VLD1Q<0b0100, "vld1.16", v8i16, int_arm_neon_vld1>;
188 def VLD1q32 : VLD1Q<0b1000, "vld1.32", v4i32, int_arm_neon_vld1>;
189 def VLD1qf : VLD1Q<0b1000, "vld1.32", v4f32, int_arm_neon_vld1>;
190 def VLD1q64 : VLD1Q<0b1100, "vld1.64", v2i64, int_arm_neon_vld1>;
192 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
194 // VLD2 : Vector Load (multiple 2-element structures)
195 class VLD2D<bits<4> op7_4, string OpcodeStr>
196 : NLdSt<0,0b10,0b1000,op7_4, (outs DPR:$dst1, DPR:$dst2),
197 (ins addrmode6:$addr), IIC_VLD2,
198 OpcodeStr, "\t\\{$dst1,$dst2\\}, $addr", "", []>;
199 class VLD2Q<bits<4> op7_4, string OpcodeStr>
200 : NLdSt<0,0b10,0b0011,op7_4,
201 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
202 (ins addrmode6:$addr), IIC_VLD2,
203 OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr",
206 def VLD2d8 : VLD2D<0b0000, "vld2.8">;
207 def VLD2d16 : VLD2D<0b0100, "vld2.16">;
208 def VLD2d32 : VLD2D<0b1000, "vld2.32">;
209 def VLD2d64 : NLdSt<0,0b10,0b1010,0b1100, (outs DPR:$dst1, DPR:$dst2),
210 (ins addrmode6:$addr), IIC_VLD1,
211 "vld1.64", "\t\\{$dst1,$dst2\\}, $addr", "", []>;
213 def VLD2q8 : VLD2Q<0b0000, "vld2.8">;
214 def VLD2q16 : VLD2Q<0b0100, "vld2.16">;
215 def VLD2q32 : VLD2Q<0b1000, "vld2.32">;
217 // VLD3 : Vector Load (multiple 3-element structures)
218 class VLD3D<bits<4> op7_4, string OpcodeStr>
219 : NLdSt<0,0b10,0b0100,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
220 (ins addrmode6:$addr), IIC_VLD3,
221 OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr", "", []>;
222 class VLD3WB<bits<4> op7_4, string OpcodeStr>
223 : NLdSt<0,0b10,0b0101,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
224 (ins addrmode6:$addr), IIC_VLD3,
225 OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr",
226 "$addr.addr = $wb", []>;
228 def VLD3d8 : VLD3D<0b0000, "vld3.8">;
229 def VLD3d16 : VLD3D<0b0100, "vld3.16">;
230 def VLD3d32 : VLD3D<0b1000, "vld3.32">;
231 def VLD3d64 : NLdSt<0,0b10,0b0110,0b1100,
232 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
233 (ins addrmode6:$addr), IIC_VLD1,
234 "vld1.64", "\t\\{$dst1,$dst2,$dst3\\}, $addr", "", []>;
236 // vld3 to double-spaced even registers.
237 def VLD3q8a : VLD3WB<0b0000, "vld3.8">;
238 def VLD3q16a : VLD3WB<0b0100, "vld3.16">;
239 def VLD3q32a : VLD3WB<0b1000, "vld3.32">;
241 // vld3 to double-spaced odd registers.
242 def VLD3q8b : VLD3WB<0b0000, "vld3.8">;
243 def VLD3q16b : VLD3WB<0b0100, "vld3.16">;
244 def VLD3q32b : VLD3WB<0b1000, "vld3.32">;
246 // VLD4 : Vector Load (multiple 4-element structures)
247 class VLD4D<bits<4> op7_4, string OpcodeStr>
248 : NLdSt<0,0b10,0b0000,op7_4,
249 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
250 (ins addrmode6:$addr), IIC_VLD4,
251 OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr",
253 class VLD4WB<bits<4> op7_4, string OpcodeStr>
254 : NLdSt<0,0b10,0b0001,op7_4,
255 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
256 (ins addrmode6:$addr), IIC_VLD4,
257 OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr",
258 "$addr.addr = $wb", []>;
260 def VLD4d8 : VLD4D<0b0000, "vld4.8">;
261 def VLD4d16 : VLD4D<0b0100, "vld4.16">;
262 def VLD4d32 : VLD4D<0b1000, "vld4.32">;
263 def VLD4d64 : NLdSt<0,0b10,0b0010,0b1100,
264 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
265 (ins addrmode6:$addr), IIC_VLD1,
266 "vld1.64", "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr", "", []>;
268 // vld4 to double-spaced even registers.
269 def VLD4q8a : VLD4WB<0b0000, "vld4.8">;
270 def VLD4q16a : VLD4WB<0b0100, "vld4.16">;
271 def VLD4q32a : VLD4WB<0b1000, "vld4.32">;
273 // vld4 to double-spaced odd registers.
274 def VLD4q8b : VLD4WB<0b0000, "vld4.8">;
275 def VLD4q16b : VLD4WB<0b0100, "vld4.16">;
276 def VLD4q32b : VLD4WB<0b1000, "vld4.32">;
278 // VLD1LN : Vector Load (single element to one lane)
279 // FIXME: Not yet implemented.
281 // VLD2LN : Vector Load (single 2-element structure to one lane)
282 class VLD2LN<bits<4> op11_8, string OpcodeStr>
283 : NLdSt<1,0b10,op11_8,{?,?,?,?}, (outs DPR:$dst1, DPR:$dst2),
284 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
286 OpcodeStr, "\t\\{$dst1[$lane],$dst2[$lane]\\}, $addr",
287 "$src1 = $dst1, $src2 = $dst2", []>;
289 // vld2 to single-spaced registers.
290 def VLD2LNd8 : VLD2LN<0b0001, "vld2.8">;
291 def VLD2LNd16 : VLD2LN<0b0101, "vld2.16"> {
294 def VLD2LNd32 : VLD2LN<0b1001, "vld2.32"> {
298 // vld2 to double-spaced even registers.
299 def VLD2LNq16a: VLD2LN<0b0101, "vld2.16"> {
302 def VLD2LNq32a: VLD2LN<0b1001, "vld2.32"> {
306 // vld2 to double-spaced odd registers.
307 def VLD2LNq16b: VLD2LN<0b0101, "vld2.16"> {
310 def VLD2LNq32b: VLD2LN<0b1001, "vld2.32"> {
314 // VLD3LN : Vector Load (single 3-element structure to one lane)
315 class VLD3LN<bits<4> op11_8, string OpcodeStr>
316 : NLdSt<1,0b10,op11_8,{?,?,?,?}, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
317 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
318 nohash_imm:$lane), IIC_VLD3,
320 "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane]\\}, $addr",
321 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
323 // vld3 to single-spaced registers.
324 def VLD3LNd8 : VLD3LN<0b0010, "vld3.8"> {
327 def VLD3LNd16 : VLD3LN<0b0110, "vld3.16"> {
328 let Inst{5-4} = 0b00;
330 def VLD3LNd32 : VLD3LN<0b1010, "vld3.32"> {
331 let Inst{6-4} = 0b000;
334 // vld3 to double-spaced even registers.
335 def VLD3LNq16a: VLD3LN<0b0110, "vld3.16"> {
336 let Inst{5-4} = 0b10;
338 def VLD3LNq32a: VLD3LN<0b1010, "vld3.32"> {
339 let Inst{6-4} = 0b100;
342 // vld3 to double-spaced odd registers.
343 def VLD3LNq16b: VLD3LN<0b0110, "vld3.16"> {
344 let Inst{5-4} = 0b10;
346 def VLD3LNq32b: VLD3LN<0b1010, "vld3.32"> {
347 let Inst{6-4} = 0b100;
350 // VLD4LN : Vector Load (single 4-element structure to one lane)
351 class VLD4LN<bits<4> op11_8, string OpcodeStr>
352 : NLdSt<1,0b10,op11_8,{?,?,?,?},
353 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
354 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
355 nohash_imm:$lane), IIC_VLD4,
357 "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane],$dst4[$lane]\\}, $addr",
358 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
360 // vld4 to single-spaced registers.
361 def VLD4LNd8 : VLD4LN<0b0011, "vld4.8">;
362 def VLD4LNd16 : VLD4LN<0b0111, "vld4.16"> {
365 def VLD4LNd32 : VLD4LN<0b1011, "vld4.32"> {
369 // vld4 to double-spaced even registers.
370 def VLD4LNq16a: VLD4LN<0b0111, "vld4.16"> {
373 def VLD4LNq32a: VLD4LN<0b1011, "vld4.32"> {
377 // vld4 to double-spaced odd registers.
378 def VLD4LNq16b: VLD4LN<0b0111, "vld4.16"> {
381 def VLD4LNq32b: VLD4LN<0b1011, "vld4.32"> {
385 // VLD1DUP : Vector Load (single element to all lanes)
386 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
387 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
388 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
389 // FIXME: Not yet implemented.
390 } // mayLoad = 1, hasExtraDefRegAllocReq = 1
392 // VST1 : Vector Store (multiple single elements)
393 class VST1D<bits<4> op7_4, string OpcodeStr, ValueType Ty, Intrinsic IntOp>
394 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src), IIC_VST,
395 OpcodeStr, "\t\\{$src\\}, $addr", "",
396 [(IntOp addrmode6:$addr, (Ty DPR:$src))]>;
397 class VST1Q<bits<4> op7_4, string OpcodeStr, ValueType Ty, Intrinsic IntOp>
398 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$addr, QPR:$src), IIC_VST,
399 OpcodeStr, "\t${src:dregpair}, $addr", "",
400 [(IntOp addrmode6:$addr, (Ty QPR:$src))]>;
402 let hasExtraSrcRegAllocReq = 1 in {
403 def VST1d8 : VST1D<0b0000, "vst1.8", v8i8, int_arm_neon_vst1>;
404 def VST1d16 : VST1D<0b0100, "vst1.16", v4i16, int_arm_neon_vst1>;
405 def VST1d32 : VST1D<0b1000, "vst1.32", v2i32, int_arm_neon_vst1>;
406 def VST1df : VST1D<0b1000, "vst1.32", v2f32, int_arm_neon_vst1>;
407 def VST1d64 : VST1D<0b1100, "vst1.64", v1i64, int_arm_neon_vst1>;
409 def VST1q8 : VST1Q<0b0000, "vst1.8", v16i8, int_arm_neon_vst1>;
410 def VST1q16 : VST1Q<0b0100, "vst1.16", v8i16, int_arm_neon_vst1>;
411 def VST1q32 : VST1Q<0b1000, "vst1.32", v4i32, int_arm_neon_vst1>;
412 def VST1qf : VST1Q<0b1000, "vst1.32", v4f32, int_arm_neon_vst1>;
413 def VST1q64 : VST1Q<0b1100, "vst1.64", v2i64, int_arm_neon_vst1>;
414 } // hasExtraSrcRegAllocReq
416 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
418 // VST2 : Vector Store (multiple 2-element structures)
419 class VST2D<bits<4> op7_4, string OpcodeStr>
420 : NLdSt<0,0b00,0b1000,op7_4, (outs),
421 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
422 OpcodeStr, "\t\\{$src1,$src2\\}, $addr", "", []>;
423 class VST2Q<bits<4> op7_4, string OpcodeStr>
424 : NLdSt<0,0b00,0b0011,op7_4, (outs),
425 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
427 OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr",
430 def VST2d8 : VST2D<0b0000, "vst2.8">;
431 def VST2d16 : VST2D<0b0100, "vst2.16">;
432 def VST2d32 : VST2D<0b1000, "vst2.32">;
433 def VST2d64 : NLdSt<0,0b00,0b1010,0b1100, (outs),
434 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
435 "vst1.64", "\t\\{$src1,$src2\\}, $addr", "", []>;
437 def VST2q8 : VST2Q<0b0000, "vst2.8">;
438 def VST2q16 : VST2Q<0b0100, "vst2.16">;
439 def VST2q32 : VST2Q<0b1000, "vst2.32">;
441 // VST3 : Vector Store (multiple 3-element structures)
442 class VST3D<bits<4> op7_4, string OpcodeStr>
443 : NLdSt<0,0b00,0b0100,op7_4, (outs),
444 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
445 OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr", "", []>;
446 class VST3WB<bits<4> op7_4, string OpcodeStr>
447 : NLdSt<0,0b00,0b0101,op7_4, (outs GPR:$wb),
448 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
449 OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr",
450 "$addr.addr = $wb", []>;
452 def VST3d8 : VST3D<0b0000, "vst3.8">;
453 def VST3d16 : VST3D<0b0100, "vst3.16">;
454 def VST3d32 : VST3D<0b1000, "vst3.32">;
455 def VST3d64 : NLdSt<0,0b00,0b0110,0b1100, (outs),
456 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
458 "vst1.64", "\t\\{$src1,$src2,$src3\\}, $addr", "", []>;
460 // vst3 to double-spaced even registers.
461 def VST3q8a : VST3WB<0b0000, "vst3.8">;
462 def VST3q16a : VST3WB<0b0100, "vst3.16">;
463 def VST3q32a : VST3WB<0b1000, "vst3.32">;
465 // vst3 to double-spaced odd registers.
466 def VST3q8b : VST3WB<0b0000, "vst3.8">;
467 def VST3q16b : VST3WB<0b0100, "vst3.16">;
468 def VST3q32b : VST3WB<0b1000, "vst3.32">;
470 // VST4 : Vector Store (multiple 4-element structures)
471 class VST4D<bits<4> op7_4, string OpcodeStr>
472 : NLdSt<0,0b00,0b0000,op7_4, (outs),
473 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
475 OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr",
477 class VST4WB<bits<4> op7_4, string OpcodeStr>
478 : NLdSt<0,0b00,0b0001,op7_4, (outs GPR:$wb),
479 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
481 OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr",
482 "$addr.addr = $wb", []>;
484 def VST4d8 : VST4D<0b0000, "vst4.8">;
485 def VST4d16 : VST4D<0b0100, "vst4.16">;
486 def VST4d32 : VST4D<0b1000, "vst4.32">;
487 def VST4d64 : NLdSt<0,0b00,0b0010,0b1100, (outs),
488 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
490 "vst1.64", "\t\\{$src1,$src2,$src3,$src4\\}, $addr", "", []>;
492 // vst4 to double-spaced even registers.
493 def VST4q8a : VST4WB<0b0000, "vst4.8">;
494 def VST4q16a : VST4WB<0b0100, "vst4.16">;
495 def VST4q32a : VST4WB<0b1000, "vst4.32">;
497 // vst4 to double-spaced odd registers.
498 def VST4q8b : VST4WB<0b0000, "vst4.8">;
499 def VST4q16b : VST4WB<0b0100, "vst4.16">;
500 def VST4q32b : VST4WB<0b1000, "vst4.32">;
502 // VST1LN : Vector Store (single element from one lane)
503 // FIXME: Not yet implemented.
505 // VST2LN : Vector Store (single 2-element structure from one lane)
506 class VST2LN<bits<4> op11_8, string OpcodeStr>
507 : NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs),
508 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
510 OpcodeStr, "\t\\{$src1[$lane],$src2[$lane]\\}, $addr",
513 // vst2 to single-spaced registers.
514 def VST2LNd8 : VST2LN<0b0001, "vst2.8">;
515 def VST2LNd16 : VST2LN<0b0101, "vst2.16"> {
518 def VST2LNd32 : VST2LN<0b1001, "vst2.32"> {
522 // vst2 to double-spaced even registers.
523 def VST2LNq16a: VST2LN<0b0101, "vst2.16"> {
526 def VST2LNq32a: VST2LN<0b1001, "vst2.32"> {
530 // vst2 to double-spaced odd registers.
531 def VST2LNq16b: VST2LN<0b0101, "vst2.16"> {
534 def VST2LNq32b: VST2LN<0b1001, "vst2.32"> {
538 // VST3LN : Vector Store (single 3-element structure from one lane)
539 class VST3LN<bits<4> op11_8, string OpcodeStr>
540 : NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs),
541 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
542 nohash_imm:$lane), IIC_VST,
544 "\t\\{$src1[$lane],$src2[$lane],$src3[$lane]\\}, $addr", "", []>;
546 // vst3 to single-spaced registers.
547 def VST3LNd8 : VST3LN<0b0010, "vst3.8"> {
550 def VST3LNd16 : VST3LN<0b0110, "vst3.16"> {
551 let Inst{5-4} = 0b00;
553 def VST3LNd32 : VST3LN<0b1010, "vst3.32"> {
554 let Inst{6-4} = 0b000;
557 // vst3 to double-spaced even registers.
558 def VST3LNq16a: VST3LN<0b0110, "vst3.16"> {
559 let Inst{5-4} = 0b10;
561 def VST3LNq32a: VST3LN<0b1010, "vst3.32"> {
562 let Inst{6-4} = 0b100;
565 // vst3 to double-spaced odd registers.
566 def VST3LNq16b: VST3LN<0b0110, "vst3.16"> {
567 let Inst{5-4} = 0b10;
569 def VST3LNq32b: VST3LN<0b1010, "vst3.32"> {
570 let Inst{6-4} = 0b100;
573 // VST4LN : Vector Store (single 4-element structure from one lane)
574 class VST4LN<bits<4> op11_8, string OpcodeStr>
575 : NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs),
576 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
577 nohash_imm:$lane), IIC_VST,
579 "\t\\{$src1[$lane],$src2[$lane],$src3[$lane],$src4[$lane]\\}, $addr",
582 // vst4 to single-spaced registers.
583 def VST4LNd8 : VST4LN<0b0011, "vst4.8">;
584 def VST4LNd16 : VST4LN<0b0111, "vst4.16"> {
587 def VST4LNd32 : VST4LN<0b1011, "vst4.32"> {
591 // vst4 to double-spaced even registers.
592 def VST4LNq16a: VST4LN<0b0111, "vst4.16"> {
595 def VST4LNq32a: VST4LN<0b1011, "vst4.32"> {
599 // vst4 to double-spaced odd registers.
600 def VST4LNq16b: VST4LN<0b0111, "vst4.16"> {
603 def VST4LNq32b: VST4LN<0b1011, "vst4.32"> {
607 } // mayStore = 1, hasExtraSrcRegAllocReq = 1
610 //===----------------------------------------------------------------------===//
611 // NEON pattern fragments
612 //===----------------------------------------------------------------------===//
614 // Extract D sub-registers of Q registers.
615 // (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
616 def DSubReg_i8_reg : SDNodeXForm<imm, [{
617 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
619 def DSubReg_i16_reg : SDNodeXForm<imm, [{
620 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
622 def DSubReg_i32_reg : SDNodeXForm<imm, [{
623 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
625 def DSubReg_f64_reg : SDNodeXForm<imm, [{
626 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
628 def DSubReg_f64_other_reg : SDNodeXForm<imm, [{
629 return CurDAG->getTargetConstant(5 + (1 - N->getZExtValue()), MVT::i32);
632 // Extract S sub-registers of Q/D registers.
633 // (arm_ssubreg_0 is 1; arm_ssubreg_1 is 2; etc.)
634 def SSubReg_f32_reg : SDNodeXForm<imm, [{
635 return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32);
638 // Translate lane numbers from Q registers to D subregs.
639 def SubReg_i8_lane : SDNodeXForm<imm, [{
640 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
642 def SubReg_i16_lane : SDNodeXForm<imm, [{
643 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
645 def SubReg_i32_lane : SDNodeXForm<imm, [{
646 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
649 //===----------------------------------------------------------------------===//
650 // Instruction Classes
651 //===----------------------------------------------------------------------===//
653 // Basic 2-register operations, both double- and quad-register.
654 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
655 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
656 ValueType ResTy, ValueType OpTy, SDNode OpNode>
657 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
658 (ins DPR:$src), IIC_VUNAD, OpcodeStr, "\t$dst, $src", "",
659 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
660 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
661 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
662 ValueType ResTy, ValueType OpTy, SDNode OpNode>
663 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
664 (ins QPR:$src), IIC_VUNAQ, OpcodeStr, "\t$dst, $src", "",
665 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
667 // Basic 2-register operations, scalar single-precision.
668 class N2VDs<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
669 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
670 ValueType ResTy, ValueType OpTy, SDNode OpNode>
671 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
672 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
673 IIC_VUNAD, OpcodeStr, "\t$dst, $src", "", []>;
675 class N2VDsPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
676 : NEONFPPat<(ResTy (OpNode SPR:$a)),
678 (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
681 // Basic 2-register intrinsics, both double- and quad-register.
682 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
683 bits<2> op17_16, bits<5> op11_7, bit op4,
684 InstrItinClass itin, string OpcodeStr,
685 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
686 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
687 (ins DPR:$src), itin, OpcodeStr, "\t$dst, $src", "",
688 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
689 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
690 bits<2> op17_16, bits<5> op11_7, bit op4,
691 InstrItinClass itin, string OpcodeStr,
692 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
693 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
694 (ins QPR:$src), itin, OpcodeStr, "\t$dst, $src", "",
695 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
697 // Basic 2-register intrinsics, scalar single-precision
698 class N2VDInts<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
699 bits<2> op17_16, bits<5> op11_7, bit op4,
700 InstrItinClass itin, string OpcodeStr,
701 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
702 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
703 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), itin,
704 OpcodeStr, "\t$dst, $src", "", []>;
706 class N2VDIntsPat<SDNode OpNode, NeonI Inst>
707 : NEONFPPat<(f32 (OpNode SPR:$a)),
709 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
712 // Narrow 2-register intrinsics.
713 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
714 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
715 InstrItinClass itin, string OpcodeStr,
716 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
717 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
718 (ins QPR:$src), itin, OpcodeStr, "\t$dst, $src", "",
719 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
721 // Long 2-register intrinsics (currently only used for VMOVL).
722 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
723 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
724 InstrItinClass itin, string OpcodeStr,
725 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
726 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$dst),
727 (ins DPR:$src), itin, OpcodeStr, "\t$dst, $src", "",
728 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
730 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
731 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr>
732 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
733 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
734 OpcodeStr, "\t$dst1, $dst2",
735 "$src1 = $dst1, $src2 = $dst2", []>;
736 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
737 InstrItinClass itin, string OpcodeStr>
738 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
739 (ins QPR:$src1, QPR:$src2), itin,
740 OpcodeStr, "\t$dst1, $dst2",
741 "$src1 = $dst1, $src2 = $dst2", []>;
743 // Basic 3-register operations, both double- and quad-register.
744 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
745 InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy,
746 SDNode OpNode, bit Commutable>
747 : N3V<op24, op23, op21_20, op11_8, 0, op4,
748 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
749 OpcodeStr, "\t$dst, $src1, $src2", "",
750 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
751 let isCommutable = Commutable;
753 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
754 InstrItinClass itin, string OpcodeStr, ValueType Ty, SDNode ShOp>
755 : N3V<0, 1, op21_20, op11_8, 1, 0,
756 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
757 itin, OpcodeStr, "\t$dst, $src1, $src2[$lane]", "",
759 (Ty (ShOp (Ty DPR:$src1),
760 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
762 let isCommutable = 0;
764 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
765 string OpcodeStr, ValueType Ty, SDNode ShOp>
766 : N3V<0, 1, op21_20, op11_8, 1, 0,
767 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
769 OpcodeStr, "\t$dst, $src1, $src2[$lane]", "",
771 (Ty (ShOp (Ty DPR:$src1),
772 (Ty (NEONvduplane (Ty DPR_8:$src2),
774 let isCommutable = 0;
777 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
778 InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy,
779 SDNode OpNode, bit Commutable>
780 : N3V<op24, op23, op21_20, op11_8, 1, op4,
781 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
782 OpcodeStr, "\t$dst, $src1, $src2", "",
783 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
784 let isCommutable = Commutable;
786 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
787 InstrItinClass itin, string OpcodeStr,
788 ValueType ResTy, ValueType OpTy, SDNode ShOp>
789 : N3V<1, 1, op21_20, op11_8, 1, 0,
790 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
791 itin, OpcodeStr, "\t$dst, $src1, $src2[$lane]", "",
792 [(set (ResTy QPR:$dst),
793 (ResTy (ShOp (ResTy QPR:$src1),
794 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
796 let isCommutable = 0;
798 class N3VQSL16<bits<2> op21_20, bits<4> op11_8,
799 string OpcodeStr, ValueType ResTy, ValueType OpTy, SDNode ShOp>
800 : N3V<1, 1, op21_20, op11_8, 1, 0,
801 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
803 OpcodeStr, "\t$dst, $src1, $src2[$lane]", "",
804 [(set (ResTy QPR:$dst),
805 (ResTy (ShOp (ResTy QPR:$src1),
806 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
808 let isCommutable = 0;
811 // Basic 3-register operations, scalar single-precision
812 class N3VDs<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
813 string OpcodeStr, ValueType ResTy, ValueType OpTy,
814 SDNode OpNode, bit Commutable>
815 : N3V<op24, op23, op21_20, op11_8, 0, op4,
816 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), IIC_VBIND,
817 OpcodeStr, "\t$dst, $src1, $src2", "", []> {
818 let isCommutable = Commutable;
820 class N3VDsPat<SDNode OpNode, NeonI Inst>
821 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
823 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
824 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
827 // Basic 3-register intrinsics, both double- and quad-register.
828 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
829 InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy,
830 Intrinsic IntOp, bit Commutable>
831 : N3V<op24, op23, op21_20, op11_8, 0, op4,
832 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
833 OpcodeStr, "\t$dst, $src1, $src2", "",
834 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
835 let isCommutable = Commutable;
837 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
838 string OpcodeStr, ValueType Ty, Intrinsic IntOp>
839 : N3V<0, 1, op21_20, op11_8, 1, 0,
840 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
841 itin, OpcodeStr, "\t$dst, $src1, $src2[$lane]", "",
843 (Ty (IntOp (Ty DPR:$src1),
844 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
846 let isCommutable = 0;
848 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
849 string OpcodeStr, ValueType Ty, Intrinsic IntOp>
850 : N3V<0, 1, op21_20, op11_8, 1, 0,
851 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
852 itin, OpcodeStr, "\t$dst, $src1, $src2[$lane]", "",
854 (Ty (IntOp (Ty DPR:$src1),
855 (Ty (NEONvduplane (Ty DPR_8:$src2),
857 let isCommutable = 0;
860 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
861 InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy,
862 Intrinsic IntOp, bit Commutable>
863 : N3V<op24, op23, op21_20, op11_8, 1, op4,
864 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
865 OpcodeStr, "\t$dst, $src1, $src2", "",
866 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
867 let isCommutable = Commutable;
869 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
870 string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
871 : N3V<1, 1, op21_20, op11_8, 1, 0,
872 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
873 itin, OpcodeStr, "\t$dst, $src1, $src2[$lane]", "",
874 [(set (ResTy QPR:$dst),
875 (ResTy (IntOp (ResTy QPR:$src1),
876 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
878 let isCommutable = 0;
880 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
881 string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
882 : N3V<1, 1, op21_20, op11_8, 1, 0,
883 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
884 itin, OpcodeStr, "\t$dst, $src1, $src2[$lane]", "",
885 [(set (ResTy QPR:$dst),
886 (ResTy (IntOp (ResTy QPR:$src1),
887 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
889 let isCommutable = 0;
892 // Multiply-Add/Sub operations, both double- and quad-register.
893 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
894 InstrItinClass itin, string OpcodeStr,
895 ValueType Ty, SDNode MulOp, SDNode OpNode>
896 : N3V<op24, op23, op21_20, op11_8, 0, op4,
897 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin,
898 OpcodeStr, "\t$dst, $src2, $src3", "$src1 = $dst",
899 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
900 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
901 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
902 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode ShOp>
903 : N3V<0, 1, op21_20, op11_8, 1, 0,
905 (ins DPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
906 OpcodeStr, "\t$dst, $src2, $src3[$lane]", "$src1 = $dst",
908 (Ty (ShOp (Ty DPR:$src1),
909 (Ty (MulOp DPR:$src2,
910 (Ty (NEONvduplane (Ty DPR_VFP2:$src3),
912 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
913 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode ShOp>
914 : N3V<0, 1, op21_20, op11_8, 1, 0,
916 (ins DPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
917 OpcodeStr, "\t$dst, $src2, $src3[$lane]", "$src1 = $dst",
919 (Ty (ShOp (Ty DPR:$src1),
920 (Ty (MulOp DPR:$src2,
921 (Ty (NEONvduplane (Ty DPR_8:$src3),
924 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
925 InstrItinClass itin, string OpcodeStr, ValueType Ty,
926 SDNode MulOp, SDNode OpNode>
927 : N3V<op24, op23, op21_20, op11_8, 1, op4,
928 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin,
929 OpcodeStr, "\t$dst, $src2, $src3", "$src1 = $dst",
930 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
931 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
932 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
933 string OpcodeStr, ValueType ResTy, ValueType OpTy,
934 SDNode MulOp, SDNode ShOp>
935 : N3V<1, 1, op21_20, op11_8, 1, 0,
937 (ins QPR:$src1, QPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
938 OpcodeStr, "\t$dst, $src2, $src3[$lane]", "$src1 = $dst",
939 [(set (ResTy QPR:$dst),
940 (ResTy (ShOp (ResTy QPR:$src1),
941 (ResTy (MulOp QPR:$src2,
942 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src3),
944 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
945 string OpcodeStr, ValueType ResTy, ValueType OpTy,
946 SDNode MulOp, SDNode ShOp>
947 : N3V<1, 1, op21_20, op11_8, 1, 0,
949 (ins QPR:$src1, QPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
950 OpcodeStr, "\t$dst, $src2, $src3[$lane]", "$src1 = $dst",
951 [(set (ResTy QPR:$dst),
952 (ResTy (ShOp (ResTy QPR:$src1),
953 (ResTy (MulOp QPR:$src2,
954 (ResTy (NEONvduplane (OpTy DPR_8:$src3),
957 // Multiply-Add/Sub operations, scalar single-precision
958 class N3VDMulOps<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
959 InstrItinClass itin, string OpcodeStr,
960 ValueType Ty, SDNode MulOp, SDNode OpNode>
961 : N3V<op24, op23, op21_20, op11_8, 0, op4,
962 (outs DPR_VFP2:$dst),
963 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), itin,
964 OpcodeStr, "\t$dst, $src2, $src3", "$src1 = $dst", []>;
966 class N3VDMulOpsPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
967 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
969 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$acc, arm_ssubreg_0),
970 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
971 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
974 // Neon 3-argument intrinsics, both double- and quad-register.
975 // The destination register is also used as the first source operand register.
976 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
977 InstrItinClass itin, string OpcodeStr,
978 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
979 : N3V<op24, op23, op21_20, op11_8, 0, op4,
980 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin,
981 OpcodeStr, "\t$dst, $src2, $src3", "$src1 = $dst",
982 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
983 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
984 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
985 InstrItinClass itin, string OpcodeStr,
986 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
987 : N3V<op24, op23, op21_20, op11_8, 1, op4,
988 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin,
989 OpcodeStr, "\t$dst, $src2, $src3", "$src1 = $dst",
990 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
991 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
993 // Neon Long 3-argument intrinsic. The destination register is
994 // a quad-register and is also used as the first source operand register.
995 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
996 InstrItinClass itin, string OpcodeStr,
997 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
998 : N3V<op24, op23, op21_20, op11_8, 0, op4,
999 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), itin,
1000 OpcodeStr, "\t$dst, $src2, $src3", "$src1 = $dst",
1002 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
1003 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1004 string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1005 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1007 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
1008 OpcodeStr, "\t$dst, $src2, $src3[$lane]", "$src1 = $dst",
1009 [(set (ResTy QPR:$dst),
1010 (ResTy (IntOp (ResTy QPR:$src1),
1012 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src3),
1014 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1015 string OpcodeStr, ValueType ResTy, ValueType OpTy,
1017 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1019 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
1020 OpcodeStr, "\t$dst, $src2, $src3[$lane]", "$src1 = $dst",
1021 [(set (ResTy QPR:$dst),
1022 (ResTy (IntOp (ResTy QPR:$src1),
1024 (OpTy (NEONvduplane (OpTy DPR_8:$src3),
1028 // Narrowing 3-register intrinsics.
1029 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1030 string OpcodeStr, ValueType TyD, ValueType TyQ,
1031 Intrinsic IntOp, bit Commutable>
1032 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1033 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VBINi4D,
1034 OpcodeStr, "\t$dst, $src1, $src2", "",
1035 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
1036 let isCommutable = Commutable;
1039 // Long 3-register intrinsics.
1040 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1041 InstrItinClass itin, string OpcodeStr, ValueType TyQ, ValueType TyD,
1042 Intrinsic IntOp, bit Commutable>
1043 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1044 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
1045 OpcodeStr, "\t$dst, $src1, $src2", "",
1046 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
1047 let isCommutable = Commutable;
1049 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1050 string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1051 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1052 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1053 itin, OpcodeStr, "\t$dst, $src1, $src2[$lane]", "",
1054 [(set (ResTy QPR:$dst),
1055 (ResTy (IntOp (OpTy DPR:$src1),
1056 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1058 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1059 string OpcodeStr, ValueType ResTy, ValueType OpTy,
1061 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1062 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1063 itin, OpcodeStr, "\t$dst, $src1, $src2[$lane]", "",
1064 [(set (ResTy QPR:$dst),
1065 (ResTy (IntOp (OpTy DPR:$src1),
1066 (OpTy (NEONvduplane (OpTy DPR_8:$src2),
1069 // Wide 3-register intrinsics.
1070 class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1071 string OpcodeStr, ValueType TyQ, ValueType TyD,
1072 Intrinsic IntOp, bit Commutable>
1073 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1074 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), IIC_VSUBiD,
1075 OpcodeStr, "\t$dst, $src1, $src2", "",
1076 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
1077 let isCommutable = Commutable;
1080 // Pairwise long 2-register intrinsics, both double- and quad-register.
1081 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1082 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1083 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1084 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1085 (ins DPR:$src), IIC_VSHLiD, OpcodeStr, "\t$dst, $src", "",
1086 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
1087 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1088 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1089 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1090 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1091 (ins QPR:$src), IIC_VSHLiD, OpcodeStr, "\t$dst, $src", "",
1092 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
1094 // Pairwise long 2-register accumulate intrinsics,
1095 // both double- and quad-register.
1096 // The destination register is also used as the first source operand register.
1097 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1098 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1099 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1100 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
1101 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), IIC_VPALiD,
1102 OpcodeStr, "\t$dst, $src2", "$src1 = $dst",
1103 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
1104 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1105 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1106 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1107 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
1108 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VPALiQ,
1109 OpcodeStr, "\t$dst, $src2", "$src1 = $dst",
1110 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
1112 // Shift by immediate,
1113 // both double- and quad-register.
1114 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1115 InstrItinClass itin, string OpcodeStr, ValueType Ty, SDNode OpNode>
1116 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1117 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), itin,
1118 OpcodeStr, "\t$dst, $src, $SIMM", "",
1119 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
1120 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1121 InstrItinClass itin, string OpcodeStr, ValueType Ty, SDNode OpNode>
1122 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1123 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin,
1124 OpcodeStr, "\t$dst, $src, $SIMM", "",
1125 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
1127 // Long shift by immediate.
1128 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1129 string OpcodeStr, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1130 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1131 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VSHLiD,
1132 OpcodeStr, "\t$dst, $src, $SIMM", "",
1133 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
1134 (i32 imm:$SIMM))))]>;
1136 // Narrow shift by immediate.
1137 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1138 InstrItinClass itin, string OpcodeStr,
1139 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1140 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1141 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin,
1142 OpcodeStr, "\t$dst, $src, $SIMM", "",
1143 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
1144 (i32 imm:$SIMM))))]>;
1146 // Shift right by immediate and accumulate,
1147 // both double- and quad-register.
1148 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1149 string OpcodeStr, ValueType Ty, SDNode ShOp>
1150 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1151 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), IIC_VPALiD,
1152 OpcodeStr, "\t$dst, $src2, $SIMM", "$src1 = $dst",
1153 [(set DPR:$dst, (Ty (add DPR:$src1,
1154 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
1155 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1156 string OpcodeStr, ValueType Ty, SDNode ShOp>
1157 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1158 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), IIC_VPALiD,
1159 OpcodeStr, "\t$dst, $src2, $SIMM", "$src1 = $dst",
1160 [(set QPR:$dst, (Ty (add QPR:$src1,
1161 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
1163 // Shift by immediate and insert,
1164 // both double- and quad-register.
1165 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1166 string OpcodeStr, ValueType Ty, SDNode ShOp>
1167 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1168 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), IIC_VSHLiD,
1169 OpcodeStr, "\t$dst, $src2, $SIMM", "$src1 = $dst",
1170 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
1171 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1172 string OpcodeStr, ValueType Ty, SDNode ShOp>
1173 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1174 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), IIC_VSHLiQ,
1175 OpcodeStr, "\t$dst, $src2, $SIMM", "$src1 = $dst",
1176 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
1178 // Convert, with fractional bits immediate,
1179 // both double- and quad-register.
1180 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1181 string OpcodeStr, ValueType ResTy, ValueType OpTy,
1183 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1184 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VUNAD,
1185 OpcodeStr, "\t$dst, $src, $SIMM", "",
1186 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
1187 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1188 string OpcodeStr, ValueType ResTy, ValueType OpTy,
1190 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1191 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), IIC_VUNAQ,
1192 OpcodeStr, "\t$dst, $src, $SIMM", "",
1193 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
1195 //===----------------------------------------------------------------------===//
1197 //===----------------------------------------------------------------------===//
1199 // Abbreviations used in multiclass suffixes:
1200 // Q = quarter int (8 bit) elements
1201 // H = half int (16 bit) elements
1202 // S = single int (32 bit) elements
1203 // D = double int (64 bit) elements
1205 // Neon 3-register vector operations.
1207 // First with only element sizes of 8, 16 and 32 bits:
1208 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1209 InstrItinClass itinD16, InstrItinClass itinD32,
1210 InstrItinClass itinQ16, InstrItinClass itinQ32,
1211 string OpcodeStr, SDNode OpNode, bit Commutable = 0> {
1212 // 64-bit vector types.
1213 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
1214 !strconcat(OpcodeStr, "8"), v8i8, v8i8, OpNode, Commutable>;
1215 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
1216 !strconcat(OpcodeStr, "16"), v4i16, v4i16, OpNode, Commutable>;
1217 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
1218 !strconcat(OpcodeStr, "32"), v2i32, v2i32, OpNode, Commutable>;
1220 // 128-bit vector types.
1221 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
1222 !strconcat(OpcodeStr, "8"), v16i8, v16i8, OpNode, Commutable>;
1223 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
1224 !strconcat(OpcodeStr, "16"), v8i16, v8i16, OpNode, Commutable>;
1225 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
1226 !strconcat(OpcodeStr, "32"), v4i32, v4i32, OpNode, Commutable>;
1229 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, SDNode ShOp> {
1230 def v4i16 : N3VDSL16<0b01, op11_8, !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
1231 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, !strconcat(OpcodeStr, "32"),
1233 def v8i16 : N3VQSL16<0b01, op11_8, !strconcat(OpcodeStr, "16"),
1234 v8i16, v4i16, ShOp>;
1235 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, !strconcat(OpcodeStr, "32"),
1236 v4i32, v2i32, ShOp>;
1239 // ....then also with element size 64 bits:
1240 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1241 InstrItinClass itinD, InstrItinClass itinQ,
1242 string OpcodeStr, SDNode OpNode, bit Commutable = 0>
1243 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
1244 OpcodeStr, OpNode, Commutable> {
1245 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
1246 !strconcat(OpcodeStr, "64"), v1i64, v1i64, OpNode, Commutable>;
1247 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
1248 !strconcat(OpcodeStr, "64"), v2i64, v2i64, OpNode, Commutable>;
1252 // Neon Narrowing 2-register vector intrinsics,
1253 // source operand element sizes of 16, 32 and 64 bits:
1254 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1255 bits<5> op11_7, bit op6, bit op4,
1256 InstrItinClass itin, string OpcodeStr,
1258 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
1259 itin, !strconcat(OpcodeStr, "16"), v8i8, v8i16, IntOp>;
1260 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
1261 itin, !strconcat(OpcodeStr, "32"), v4i16, v4i32, IntOp>;
1262 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
1263 itin, !strconcat(OpcodeStr, "64"), v2i32, v2i64, IntOp>;
1267 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
1268 // source operand element sizes of 16, 32 and 64 bits:
1269 multiclass N2VLInt_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
1270 string OpcodeStr, Intrinsic IntOp> {
1271 def v8i16 : N2VLInt<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1272 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
1273 def v4i32 : N2VLInt<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1274 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
1275 def v2i64 : N2VLInt<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1276 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
1280 // Neon 3-register vector intrinsics.
1282 // First with only element sizes of 16 and 32 bits:
1283 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1284 InstrItinClass itinD16, InstrItinClass itinD32,
1285 InstrItinClass itinQ16, InstrItinClass itinQ32,
1286 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
1287 // 64-bit vector types.
1288 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, itinD16,
1289 !strconcat(OpcodeStr,"16"),
1290 v4i16, v4i16, IntOp, Commutable>;
1291 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, itinD32,
1292 !strconcat(OpcodeStr,"32"),
1293 v2i32, v2i32, IntOp, Commutable>;
1295 // 128-bit vector types.
1296 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, itinQ16,
1297 !strconcat(OpcodeStr,"16"),
1298 v8i16, v8i16, IntOp, Commutable>;
1299 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, itinQ32,
1300 !strconcat(OpcodeStr,"32"),
1301 v4i32, v4i32, IntOp, Commutable>;
1304 multiclass N3VIntSL_HS<bits<4> op11_8,
1305 InstrItinClass itinD16, InstrItinClass itinD32,
1306 InstrItinClass itinQ16, InstrItinClass itinQ32,
1307 string OpcodeStr, Intrinsic IntOp> {
1308 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
1309 !strconcat(OpcodeStr, "16"), v4i16, IntOp>;
1310 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
1311 !strconcat(OpcodeStr, "32"), v2i32, IntOp>;
1312 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
1313 !strconcat(OpcodeStr, "16"), v8i16, v4i16, IntOp>;
1314 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
1315 !strconcat(OpcodeStr, "32"), v4i32, v2i32, IntOp>;
1318 // ....then also with element size of 8 bits:
1319 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1320 InstrItinClass itinD16, InstrItinClass itinD32,
1321 InstrItinClass itinQ16, InstrItinClass itinQ32,
1322 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
1323 : N3VInt_HS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
1324 OpcodeStr, IntOp, Commutable> {
1325 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, itinD16,
1326 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp, Commutable>;
1327 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, itinQ16,
1328 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp, Commutable>;
1331 // ....then also with element size of 64 bits:
1332 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1333 InstrItinClass itinD16, InstrItinClass itinD32,
1334 InstrItinClass itinQ16, InstrItinClass itinQ32,
1335 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
1336 : N3VInt_QHS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
1337 OpcodeStr, IntOp, Commutable> {
1338 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, itinD32,
1339 !strconcat(OpcodeStr,"64"), v1i64, v1i64, IntOp, Commutable>;
1340 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, itinQ32,
1341 !strconcat(OpcodeStr,"64"), v2i64, v2i64, IntOp, Commutable>;
1345 // Neon Narrowing 3-register vector intrinsics,
1346 // source operand element sizes of 16, 32 and 64 bits:
1347 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1348 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
1349 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr,"16"),
1350 v8i8, v8i16, IntOp, Commutable>;
1351 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"32"),
1352 v4i16, v4i32, IntOp, Commutable>;
1353 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"64"),
1354 v2i32, v2i64, IntOp, Commutable>;
1358 // Neon Long 3-register vector intrinsics.
1360 // First with only element sizes of 16 and 32 bits:
1361 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1362 InstrItinClass itin, string OpcodeStr,
1363 Intrinsic IntOp, bit Commutable = 0> {
1364 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin,
1365 !strconcat(OpcodeStr,"16"), v4i32, v4i16, IntOp, Commutable>;
1366 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin,
1367 !strconcat(OpcodeStr,"32"), v2i64, v2i32, IntOp, Commutable>;
1370 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
1371 InstrItinClass itin, string OpcodeStr, Intrinsic IntOp> {
1372 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
1373 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
1374 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
1375 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
1378 // ....then also with element size of 8 bits:
1379 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1380 InstrItinClass itin, string OpcodeStr,
1381 Intrinsic IntOp, bit Commutable = 0>
1382 : N3VLInt_HS<op24, op23, op11_8, op4, itin, OpcodeStr, IntOp, Commutable> {
1383 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin,
1384 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp, Commutable>;
1388 // Neon Wide 3-register vector intrinsics,
1389 // source operand element sizes of 8, 16 and 32 bits:
1390 multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1391 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
1392 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
1393 v8i16, v8i8, IntOp, Commutable>;
1394 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
1395 v4i32, v4i16, IntOp, Commutable>;
1396 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
1397 v2i64, v2i32, IntOp, Commutable>;
1401 // Neon Multiply-Op vector operations,
1402 // element sizes of 8, 16 and 32 bits:
1403 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1404 InstrItinClass itinD16, InstrItinClass itinD32,
1405 InstrItinClass itinQ16, InstrItinClass itinQ32,
1406 string OpcodeStr, SDNode OpNode> {
1407 // 64-bit vector types.
1408 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
1409 !strconcat(OpcodeStr, "8"), v8i8, mul, OpNode>;
1410 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
1411 !strconcat(OpcodeStr, "16"), v4i16, mul, OpNode>;
1412 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
1413 !strconcat(OpcodeStr, "32"), v2i32, mul, OpNode>;
1415 // 128-bit vector types.
1416 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
1417 !strconcat(OpcodeStr, "8"), v16i8, mul, OpNode>;
1418 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
1419 !strconcat(OpcodeStr, "16"), v8i16, mul, OpNode>;
1420 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
1421 !strconcat(OpcodeStr, "32"), v4i32, mul, OpNode>;
1424 multiclass N3VMulOpSL_HS<bits<4> op11_8,
1425 InstrItinClass itinD16, InstrItinClass itinD32,
1426 InstrItinClass itinQ16, InstrItinClass itinQ32,
1427 string OpcodeStr, SDNode ShOp> {
1428 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
1429 !strconcat(OpcodeStr, "16"), v4i16, mul, ShOp>;
1430 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
1431 !strconcat(OpcodeStr, "32"), v2i32, mul, ShOp>;
1432 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
1433 !strconcat(OpcodeStr, "16"), v8i16, v4i16, mul, ShOp>;
1434 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
1435 !strconcat(OpcodeStr, "32"), v4i32, v2i32, mul, ShOp>;
1438 // Neon 3-argument intrinsics,
1439 // element sizes of 8, 16 and 32 bits:
1440 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1441 string OpcodeStr, Intrinsic IntOp> {
1442 // 64-bit vector types.
1443 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16D,
1444 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
1445 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
1446 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
1447 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32D,
1448 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
1450 // 128-bit vector types.
1451 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16Q,
1452 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
1453 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16Q,
1454 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
1455 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32Q,
1456 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
1460 // Neon Long 3-argument intrinsics.
1462 // First with only element sizes of 16 and 32 bits:
1463 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1464 string OpcodeStr, Intrinsic IntOp> {
1465 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
1466 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
1467 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi16D,
1468 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
1471 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
1472 string OpcodeStr, Intrinsic IntOp> {
1473 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
1474 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
1475 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
1476 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
1479 // ....then also with element size of 8 bits:
1480 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1481 string OpcodeStr, Intrinsic IntOp>
1482 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp> {
1483 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16D,
1484 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
1488 // Neon 2-register vector intrinsics,
1489 // element sizes of 8, 16 and 32 bits:
1490 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1491 bits<5> op11_7, bit op4,
1492 InstrItinClass itinD, InstrItinClass itinQ,
1493 string OpcodeStr, Intrinsic IntOp> {
1494 // 64-bit vector types.
1495 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1496 itinD, !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
1497 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1498 itinD, !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
1499 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1500 itinD, !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
1502 // 128-bit vector types.
1503 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1504 itinQ, !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
1505 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1506 itinQ, !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
1507 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1508 itinQ, !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
1512 // Neon Pairwise long 2-register intrinsics,
1513 // element sizes of 8, 16 and 32 bits:
1514 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1515 bits<5> op11_7, bit op4,
1516 string OpcodeStr, Intrinsic IntOp> {
1517 // 64-bit vector types.
1518 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1519 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
1520 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1521 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
1522 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1523 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
1525 // 128-bit vector types.
1526 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1527 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
1528 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1529 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
1530 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1531 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
1535 // Neon Pairwise long 2-register accumulate intrinsics,
1536 // element sizes of 8, 16 and 32 bits:
1537 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1538 bits<5> op11_7, bit op4,
1539 string OpcodeStr, Intrinsic IntOp> {
1540 // 64-bit vector types.
1541 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1542 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
1543 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1544 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
1545 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1546 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
1548 // 128-bit vector types.
1549 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1550 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
1551 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1552 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
1553 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1554 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
1558 // Neon 2-register vector shift by immediate,
1559 // element sizes of 8, 16, 32 and 64 bits:
1560 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1561 InstrItinClass itin, string OpcodeStr, SDNode OpNode> {
1562 // 64-bit vector types.
1563 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
1564 !strconcat(OpcodeStr, "8"), v8i8, OpNode> {
1565 let Inst{21-19} = 0b001; // imm6 = 001xxx
1567 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
1568 !strconcat(OpcodeStr, "16"), v4i16, OpNode> {
1569 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1571 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
1572 !strconcat(OpcodeStr, "32"), v2i32, OpNode> {
1573 let Inst{21} = 0b1; // imm6 = 1xxxxx
1575 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, itin,
1576 !strconcat(OpcodeStr, "64"), v1i64, OpNode>;
1579 // 128-bit vector types.
1580 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
1581 !strconcat(OpcodeStr, "8"), v16i8, OpNode> {
1582 let Inst{21-19} = 0b001; // imm6 = 001xxx
1584 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
1585 !strconcat(OpcodeStr, "16"), v8i16, OpNode> {
1586 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1588 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
1589 !strconcat(OpcodeStr, "32"), v4i32, OpNode> {
1590 let Inst{21} = 0b1; // imm6 = 1xxxxx
1592 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, itin,
1593 !strconcat(OpcodeStr, "64"), v2i64, OpNode>;
1598 // Neon Shift-Accumulate vector operations,
1599 // element sizes of 8, 16, 32 and 64 bits:
1600 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1601 string OpcodeStr, SDNode ShOp> {
1602 // 64-bit vector types.
1603 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1604 !strconcat(OpcodeStr, "8"), v8i8, ShOp> {
1605 let Inst{21-19} = 0b001; // imm6 = 001xxx
1607 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1608 !strconcat(OpcodeStr, "16"), v4i16, ShOp> {
1609 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1611 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1612 !strconcat(OpcodeStr, "32"), v2i32, ShOp> {
1613 let Inst{21} = 0b1; // imm6 = 1xxxxx
1615 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4,
1616 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
1619 // 128-bit vector types.
1620 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1621 !strconcat(OpcodeStr, "8"), v16i8, ShOp> {
1622 let Inst{21-19} = 0b001; // imm6 = 001xxx
1624 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1625 !strconcat(OpcodeStr, "16"), v8i16, ShOp> {
1626 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1628 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1629 !strconcat(OpcodeStr, "32"), v4i32, ShOp> {
1630 let Inst{21} = 0b1; // imm6 = 1xxxxx
1632 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4,
1633 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
1638 // Neon Shift-Insert vector operations,
1639 // element sizes of 8, 16, 32 and 64 bits:
1640 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1641 string OpcodeStr, SDNode ShOp> {
1642 // 64-bit vector types.
1643 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4,
1644 !strconcat(OpcodeStr, "8"), v8i8, ShOp> {
1645 let Inst{21-19} = 0b001; // imm6 = 001xxx
1647 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4,
1648 !strconcat(OpcodeStr, "16"), v4i16, ShOp> {
1649 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1651 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4,
1652 !strconcat(OpcodeStr, "32"), v2i32, ShOp> {
1653 let Inst{21} = 0b1; // imm6 = 1xxxxx
1655 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4,
1656 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
1659 // 128-bit vector types.
1660 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4,
1661 !strconcat(OpcodeStr, "8"), v16i8, ShOp> {
1662 let Inst{21-19} = 0b001; // imm6 = 001xxx
1664 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4,
1665 !strconcat(OpcodeStr, "16"), v8i16, ShOp> {
1666 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1668 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4,
1669 !strconcat(OpcodeStr, "32"), v4i32, ShOp> {
1670 let Inst{21} = 0b1; // imm6 = 1xxxxx
1672 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4,
1673 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
1677 // Neon Shift Long operations,
1678 // element sizes of 8, 16, 32 bits:
1679 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
1680 bit op4, string OpcodeStr, SDNode OpNode> {
1681 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1682 !strconcat(OpcodeStr, "8"), v8i16, v8i8, OpNode> {
1683 let Inst{21-19} = 0b001; // imm6 = 001xxx
1685 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1686 !strconcat(OpcodeStr, "16"), v4i32, v4i16, OpNode> {
1687 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1689 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1690 !strconcat(OpcodeStr, "32"), v2i64, v2i32, OpNode> {
1691 let Inst{21} = 0b1; // imm6 = 1xxxxx
1695 // Neon Shift Narrow operations,
1696 // element sizes of 16, 32, 64 bits:
1697 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
1698 bit op4, InstrItinClass itin, string OpcodeStr,
1700 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1701 !strconcat(OpcodeStr, "16"), v8i8, v8i16, OpNode> {
1702 let Inst{21-19} = 0b001; // imm6 = 001xxx
1704 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1705 !strconcat(OpcodeStr, "32"), v4i16, v4i32, OpNode> {
1706 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1708 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1709 !strconcat(OpcodeStr, "64"), v2i32, v2i64, OpNode> {
1710 let Inst{21} = 0b1; // imm6 = 1xxxxx
1714 //===----------------------------------------------------------------------===//
1715 // Instruction Definitions.
1716 //===----------------------------------------------------------------------===//
1718 // Vector Add Operations.
1720 // VADD : Vector Add (integer and floating-point)
1721 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd.i",
1723 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd.f32",
1724 v2f32, v2f32, fadd, 1>;
1725 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd.f32",
1726 v4f32, v4f32, fadd, 1>;
1727 // VADDL : Vector Add Long (Q = D + D)
1728 defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, IIC_VSHLiD, "vaddl.s",
1729 int_arm_neon_vaddls, 1>;
1730 defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, IIC_VSHLiD, "vaddl.u",
1731 int_arm_neon_vaddlu, 1>;
1732 // VADDW : Vector Add Wide (Q = Q + D)
1733 defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw.s", int_arm_neon_vaddws, 0>;
1734 defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw.u", int_arm_neon_vaddwu, 0>;
1735 // VHADD : Vector Halving Add
1736 defm VHADDs : N3VInt_QHS<0,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1737 IIC_VBINi4Q, "vhadd.s", int_arm_neon_vhadds, 1>;
1738 defm VHADDu : N3VInt_QHS<1,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1739 IIC_VBINi4Q, "vhadd.u", int_arm_neon_vhaddu, 1>;
1740 // VRHADD : Vector Rounding Halving Add
1741 defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1742 IIC_VBINi4Q, "vrhadd.s", int_arm_neon_vrhadds, 1>;
1743 defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1744 IIC_VBINi4Q, "vrhadd.u", int_arm_neon_vrhaddu, 1>;
1745 // VQADD : Vector Saturating Add
1746 defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1747 IIC_VBINi4Q, "vqadd.s", int_arm_neon_vqadds, 1>;
1748 defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1749 IIC_VBINi4Q, "vqadd.u", int_arm_neon_vqaddu, 1>;
1750 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
1751 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn.i", int_arm_neon_vaddhn, 1>;
1752 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
1753 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn.i", int_arm_neon_vraddhn, 1>;
1755 // Vector Multiply Operations.
1757 // VMUL : Vector Multiply (integer, polynomial and floating-point)
1758 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
1759 IIC_VMULi16Q, IIC_VMULi32Q, "vmul.i", mul, 1>;
1760 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16D, "vmul.p8",
1761 v8i8, v8i8, int_arm_neon_vmulp, 1>;
1762 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16Q, "vmul.p8",
1763 v16i8, v16i8, int_arm_neon_vmulp, 1>;
1764 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VBIND, "vmul.f32",
1765 v2f32, v2f32, fmul, 1>;
1766 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VBINQ, "vmul.f32",
1767 v4f32, v4f32, fmul, 1>;
1768 defm VMULsl : N3VSL_HS<0b1000, "vmul.i", mul>;
1769 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul.f32", v2f32, fmul>;
1770 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul.f32", v4f32, v2f32, fmul>;
1771 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
1772 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
1773 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
1774 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1775 (DSubReg_i16_reg imm:$lane))),
1776 (SubReg_i16_lane imm:$lane)))>;
1777 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
1778 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
1779 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
1780 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1781 (DSubReg_i32_reg imm:$lane))),
1782 (SubReg_i32_lane imm:$lane)))>;
1783 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
1784 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
1785 (v4f32 (VMULslfq (v4f32 QPR:$src1),
1786 (v2f32 (EXTRACT_SUBREG QPR:$src2,
1787 (DSubReg_i32_reg imm:$lane))),
1788 (SubReg_i32_lane imm:$lane)))>;
1790 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
1791 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
1792 IIC_VMULi16Q, IIC_VMULi32Q,
1793 "vqdmulh.s", int_arm_neon_vqdmulh, 1>;
1794 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
1795 IIC_VMULi16Q, IIC_VMULi32Q,
1796 "vqdmulh.s", int_arm_neon_vqdmulh>;
1797 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
1798 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
1800 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
1801 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1802 (DSubReg_i16_reg imm:$lane))),
1803 (SubReg_i16_lane imm:$lane)))>;
1804 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
1805 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
1807 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
1808 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1809 (DSubReg_i32_reg imm:$lane))),
1810 (SubReg_i32_lane imm:$lane)))>;
1812 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
1813 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
1814 IIC_VMULi16Q, IIC_VMULi32Q,
1815 "vqrdmulh.s", int_arm_neon_vqrdmulh, 1>;
1816 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
1817 IIC_VMULi16Q, IIC_VMULi32Q,
1818 "vqrdmulh.s", int_arm_neon_vqrdmulh>;
1819 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
1820 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
1822 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
1823 (v4i16 (EXTRACT_SUBREG QPR:$src2,
1824 (DSubReg_i16_reg imm:$lane))),
1825 (SubReg_i16_lane imm:$lane)))>;
1826 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
1827 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
1829 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
1830 (v2i32 (EXTRACT_SUBREG QPR:$src2,
1831 (DSubReg_i32_reg imm:$lane))),
1832 (SubReg_i32_lane imm:$lane)))>;
1834 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
1835 defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, IIC_VMULi16D, "vmull.s",
1836 int_arm_neon_vmulls, 1>;
1837 defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, IIC_VMULi16D, "vmull.u",
1838 int_arm_neon_vmullu, 1>;
1839 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull.p8",
1840 v8i16, v8i8, int_arm_neon_vmullp, 1>;
1841 defm VMULLsls : N3VLIntSL_HS<0, 0b1010, IIC_VMULi16D, "vmull.s",
1842 int_arm_neon_vmulls>;
1843 defm VMULLslu : N3VLIntSL_HS<1, 0b1010, IIC_VMULi16D, "vmull.u",
1844 int_arm_neon_vmullu>;
1846 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
1847 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, "vqdmull.s",
1848 int_arm_neon_vqdmull, 1>;
1849 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D, "vqdmull.s",
1850 int_arm_neon_vqdmull>;
1852 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
1854 // VMLA : Vector Multiply Accumulate (integer and floating-point)
1855 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
1856 IIC_VMACi16Q, IIC_VMACi32Q, "vmla.i", add>;
1857 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla.f32",
1859 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla.f32",
1861 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
1862 IIC_VMACi16Q, IIC_VMACi32Q, "vmla.i", add>;
1863 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla.f32",
1865 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla.f32",
1866 v4f32, v2f32, fmul, fadd>;
1868 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
1869 (mul (v8i16 QPR:$src2),
1870 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
1871 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1),
1873 (v4i16 (EXTRACT_SUBREG QPR:$src3,
1874 (DSubReg_i16_reg imm:$lane))),
1875 (SubReg_i16_lane imm:$lane)))>;
1877 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
1878 (mul (v4i32 QPR:$src2),
1879 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
1880 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1),
1882 (v2i32 (EXTRACT_SUBREG QPR:$src3,
1883 (DSubReg_i32_reg imm:$lane))),
1884 (SubReg_i32_lane imm:$lane)))>;
1886 def : Pat<(v4f32 (fadd (v4f32 QPR:$src1),
1887 (fmul (v4f32 QPR:$src2),
1888 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
1889 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
1891 (v2f32 (EXTRACT_SUBREG QPR:$src3,
1892 (DSubReg_i32_reg imm:$lane))),
1893 (SubReg_i32_lane imm:$lane)))>;
1895 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
1896 defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal.s", int_arm_neon_vmlals>;
1897 defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal.u", int_arm_neon_vmlalu>;
1899 defm VMLALsls : N3VLInt3SL_HS<0, 0b0010, "vmlal.s", int_arm_neon_vmlals>;
1900 defm VMLALslu : N3VLInt3SL_HS<1, 0b0010, "vmlal.u", int_arm_neon_vmlalu>;
1902 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
1903 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal.s", int_arm_neon_vqdmlal>;
1904 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal.s", int_arm_neon_vqdmlal>;
1906 // VMLS : Vector Multiply Subtract (integer and floating-point)
1907 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
1908 IIC_VMACi16Q, IIC_VMACi32Q, "vmls.i", sub>;
1909 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls.f32",
1911 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls.f32",
1913 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
1914 IIC_VMACi16Q, IIC_VMACi32Q, "vmls.i", sub>;
1915 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls.f32",
1917 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls.f32",
1918 v4f32, v2f32, fmul, fsub>;
1920 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
1921 (mul (v8i16 QPR:$src2),
1922 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
1923 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1),
1925 (v4i16 (EXTRACT_SUBREG QPR:$src3,
1926 (DSubReg_i16_reg imm:$lane))),
1927 (SubReg_i16_lane imm:$lane)))>;
1929 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
1930 (mul (v4i32 QPR:$src2),
1931 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
1932 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1),
1934 (v2i32 (EXTRACT_SUBREG QPR:$src3,
1935 (DSubReg_i32_reg imm:$lane))),
1936 (SubReg_i32_lane imm:$lane)))>;
1938 def : Pat<(v4f32 (fsub (v4f32 QPR:$src1),
1939 (fmul (v4f32 QPR:$src2),
1940 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
1941 (v4f32 (VMLSslfq (v4f32 QPR:$src1),
1943 (v2f32 (EXTRACT_SUBREG QPR:$src3,
1944 (DSubReg_i32_reg imm:$lane))),
1945 (SubReg_i32_lane imm:$lane)))>;
1947 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
1948 defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl.s", int_arm_neon_vmlsls>;
1949 defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl.u", int_arm_neon_vmlslu>;
1951 defm VMLSLsls : N3VLInt3SL_HS<0, 0b0110, "vmlsl.s", int_arm_neon_vmlsls>;
1952 defm VMLSLslu : N3VLInt3SL_HS<1, 0b0110, "vmlsl.u", int_arm_neon_vmlslu>;
1954 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
1955 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl.s", int_arm_neon_vqdmlsl>;
1956 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl.s", int_arm_neon_vqdmlsl>;
1958 // Vector Subtract Operations.
1960 // VSUB : Vector Subtract (integer and floating-point)
1961 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
1963 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub.f32",
1964 v2f32, v2f32, fsub, 0>;
1965 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub.f32",
1966 v4f32, v4f32, fsub, 0>;
1967 // VSUBL : Vector Subtract Long (Q = D - D)
1968 defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, IIC_VSHLiD, "vsubl.s",
1969 int_arm_neon_vsubls, 1>;
1970 defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, IIC_VSHLiD, "vsubl.u",
1971 int_arm_neon_vsublu, 1>;
1972 // VSUBW : Vector Subtract Wide (Q = Q - D)
1973 defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw.s", int_arm_neon_vsubws, 0>;
1974 defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw.u", int_arm_neon_vsubwu, 0>;
1975 // VHSUB : Vector Halving Subtract
1976 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D,
1977 IIC_VBINi4Q, IIC_VBINi4Q,
1978 "vhsub.s", int_arm_neon_vhsubs, 0>;
1979 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D,
1980 IIC_VBINi4Q, IIC_VBINi4Q,
1981 "vhsub.u", int_arm_neon_vhsubu, 0>;
1982 // VQSUB : Vector Saturing Subtract
1983 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D,
1984 IIC_VBINi4Q, IIC_VBINi4Q,
1985 "vqsub.s", int_arm_neon_vqsubs, 0>;
1986 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D,
1987 IIC_VBINi4Q, IIC_VBINi4Q,
1988 "vqsub.u", int_arm_neon_vqsubu, 0>;
1989 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
1990 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn.i", int_arm_neon_vsubhn, 0>;
1991 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
1992 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn.i", int_arm_neon_vrsubhn, 0>;
1994 // Vector Comparisons.
1996 // VCEQ : Vector Compare Equal
1997 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
1998 IIC_VBINi4Q, "vceq.i", NEONvceq, 1>;
1999 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq.f32", v2i32, v2f32,
2001 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq.f32", v4i32, v4f32,
2003 // VCGE : Vector Compare Greater Than or Equal
2004 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2005 IIC_VBINi4Q, "vcge.s", NEONvcge, 0>;
2006 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2007 IIC_VBINi4Q, "vcge.u", NEONvcgeu, 0>;
2008 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge.f32",
2009 v2i32, v2f32, NEONvcge, 0>;
2010 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge.f32", v4i32, v4f32,
2012 // VCGT : Vector Compare Greater Than
2013 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2014 IIC_VBINi4Q, "vcgt.s", NEONvcgt, 0>;
2015 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2016 IIC_VBINi4Q, "vcgt.u", NEONvcgtu, 0>;
2017 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt.f32", v2i32, v2f32,
2019 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt.f32", v4i32, v4f32,
2021 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
2022 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, IIC_VBIND, "vacge.f32",
2023 v2i32, v2f32, int_arm_neon_vacged, 0>;
2024 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, IIC_VBINQ, "vacge.f32",
2025 v4i32, v4f32, int_arm_neon_vacgeq, 0>;
2026 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
2027 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, IIC_VBIND, "vacgt.f32",
2028 v2i32, v2f32, int_arm_neon_vacgtd, 0>;
2029 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, IIC_VBINQ, "vacgt.f32",
2030 v4i32, v4f32, int_arm_neon_vacgtq, 0>;
2031 // VTST : Vector Test Bits
2032 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2033 IIC_VBINi4Q, "vtst.i", NEONvtst, 1>;
2035 // Vector Bitwise Operations.
2037 // VAND : Vector Bitwise AND
2038 def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
2039 v2i32, v2i32, and, 1>;
2040 def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
2041 v4i32, v4i32, and, 1>;
2043 // VEOR : Vector Bitwise Exclusive OR
2044 def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
2045 v2i32, v2i32, xor, 1>;
2046 def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
2047 v4i32, v4i32, xor, 1>;
2049 // VORR : Vector Bitwise OR
2050 def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
2051 v2i32, v2i32, or, 1>;
2052 def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
2053 v4i32, v4i32, or, 1>;
2055 // VBIC : Vector Bitwise Bit Clear (AND NOT)
2056 def VBICd : N3V<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2057 (ins DPR:$src1, DPR:$src2), IIC_VBINiD,
2058 "vbic", "\t$dst, $src1, $src2", "",
2059 [(set DPR:$dst, (v2i32 (and DPR:$src1,
2060 (vnot_conv DPR:$src2))))]>;
2061 def VBICq : N3V<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2062 (ins QPR:$src1, QPR:$src2), IIC_VBINiQ,
2063 "vbic", "\t$dst, $src1, $src2", "",
2064 [(set QPR:$dst, (v4i32 (and QPR:$src1,
2065 (vnot_conv QPR:$src2))))]>;
2067 // VORN : Vector Bitwise OR NOT
2068 def VORNd : N3V<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
2069 (ins DPR:$src1, DPR:$src2), IIC_VBINiD,
2070 "vorn", "\t$dst, $src1, $src2", "",
2071 [(set DPR:$dst, (v2i32 (or DPR:$src1,
2072 (vnot_conv DPR:$src2))))]>;
2073 def VORNq : N3V<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
2074 (ins QPR:$src1, QPR:$src2), IIC_VBINiQ,
2075 "vorn", "\t$dst, $src1, $src2", "",
2076 [(set QPR:$dst, (v4i32 (or QPR:$src1,
2077 (vnot_conv QPR:$src2))))]>;
2079 // VMVN : Vector Bitwise NOT
2080 def VMVNd : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
2081 (outs DPR:$dst), (ins DPR:$src), IIC_VSHLiD,
2082 "vmvn", "\t$dst, $src", "",
2083 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>;
2084 def VMVNq : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
2085 (outs QPR:$dst), (ins QPR:$src), IIC_VSHLiD,
2086 "vmvn", "\t$dst, $src", "",
2087 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>;
2088 def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>;
2089 def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>;
2091 // VBSL : Vector Bitwise Select
2092 def VBSLd : N3V<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2093 (ins DPR:$src1, DPR:$src2, DPR:$src3), IIC_VCNTiD,
2094 "vbsl", "\t$dst, $src2, $src3", "$src1 = $dst",
2096 (v2i32 (or (and DPR:$src2, DPR:$src1),
2097 (and DPR:$src3, (vnot_conv DPR:$src1)))))]>;
2098 def VBSLq : N3V<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2099 (ins QPR:$src1, QPR:$src2, QPR:$src3), IIC_VCNTiQ,
2100 "vbsl", "\t$dst, $src2, $src3", "$src1 = $dst",
2102 (v4i32 (or (and QPR:$src2, QPR:$src1),
2103 (and QPR:$src3, (vnot_conv QPR:$src1)))))]>;
2105 // VBIF : Vector Bitwise Insert if False
2106 // like VBSL but with: "vbif\t$dst, $src3, $src1", "$src2 = $dst",
2107 // VBIT : Vector Bitwise Insert if True
2108 // like VBSL but with: "vbit\t$dst, $src2, $src1", "$src3 = $dst",
2109 // These are not yet implemented. The TwoAddress pass will not go looking
2110 // for equivalent operations with different register constraints; it just
2113 // Vector Absolute Differences.
2115 // VABD : Vector Absolute Difference
2116 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D,
2117 IIC_VBINi4Q, IIC_VBINi4Q,
2118 "vabd.s", int_arm_neon_vabds, 0>;
2119 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D,
2120 IIC_VBINi4Q, IIC_VBINi4Q,
2121 "vabd.u", int_arm_neon_vabdu, 0>;
2122 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, IIC_VBIND,
2123 "vabd.f32", v2f32, v2f32, int_arm_neon_vabds, 0>;
2124 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, IIC_VBINQ,
2125 "vabd.f32", v4f32, v4f32, int_arm_neon_vabds, 0>;
2127 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
2128 defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, IIC_VBINi4Q,
2129 "vabdl.s", int_arm_neon_vabdls, 0>;
2130 defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, IIC_VBINi4Q,
2131 "vabdl.u", int_arm_neon_vabdlu, 0>;
2133 // VABA : Vector Absolute Difference and Accumulate
2134 defm VABAs : N3VInt3_QHS<0,0,0b0111,1, "vaba.s", int_arm_neon_vabas>;
2135 defm VABAu : N3VInt3_QHS<1,0,0b0111,1, "vaba.u", int_arm_neon_vabau>;
2137 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
2138 defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal.s", int_arm_neon_vabals>;
2139 defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal.u", int_arm_neon_vabalu>;
2141 // Vector Maximum and Minimum.
2143 // VMAX : Vector Maximum
2144 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2145 IIC_VBINi4Q, "vmax.s", int_arm_neon_vmaxs, 1>;
2146 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2147 IIC_VBINi4Q, "vmax.u", int_arm_neon_vmaxu, 1>;
2148 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, IIC_VBIND, "vmax.f32", v2f32, v2f32,
2149 int_arm_neon_vmaxs, 1>;
2150 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, IIC_VBINQ, "vmax.f32", v4f32, v4f32,
2151 int_arm_neon_vmaxs, 1>;
2153 // VMIN : Vector Minimum
2154 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2155 IIC_VBINi4Q, "vmin.s", int_arm_neon_vmins, 1>;
2156 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2157 IIC_VBINi4Q, "vmin.u", int_arm_neon_vminu, 1>;
2158 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, IIC_VBIND, "vmin.f32", v2f32, v2f32,
2159 int_arm_neon_vmins, 1>;
2160 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, IIC_VBINQ, "vmin.f32", v4f32, v4f32,
2161 int_arm_neon_vmins, 1>;
2163 // Vector Pairwise Operations.
2165 // VPADD : Vector Pairwise Add
2166 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, IIC_VBINiD, "vpadd.i8", v8i8, v8i8,
2167 int_arm_neon_vpadd, 0>;
2168 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, IIC_VBINiD, "vpadd.i16", v4i16, v4i16,
2169 int_arm_neon_vpadd, 0>;
2170 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, IIC_VBINiD, "vpadd.i32", v2i32, v2i32,
2171 int_arm_neon_vpadd, 0>;
2172 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, IIC_VBIND, "vpadd.f32", v2f32, v2f32,
2173 int_arm_neon_vpadd, 0>;
2175 // VPADDL : Vector Pairwise Add Long
2176 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl.s",
2177 int_arm_neon_vpaddls>;
2178 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl.u",
2179 int_arm_neon_vpaddlu>;
2181 // VPADAL : Vector Pairwise Add and Accumulate Long
2182 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal.s",
2183 int_arm_neon_vpadals>;
2184 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal.u",
2185 int_arm_neon_vpadalu>;
2187 // VPMAX : Vector Pairwise Maximum
2188 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax.s8", v8i8, v8i8,
2189 int_arm_neon_vpmaxs, 0>;
2190 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax.s16", v4i16, v4i16,
2191 int_arm_neon_vpmaxs, 0>;
2192 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax.s32", v2i32, v2i32,
2193 int_arm_neon_vpmaxs, 0>;
2194 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax.u8", v8i8, v8i8,
2195 int_arm_neon_vpmaxu, 0>;
2196 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax.u16", v4i16, v4i16,
2197 int_arm_neon_vpmaxu, 0>;
2198 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax.u32", v2i32, v2i32,
2199 int_arm_neon_vpmaxu, 0>;
2200 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, IIC_VBINi4D, "vpmax.f32", v2f32, v2f32,
2201 int_arm_neon_vpmaxs, 0>;
2203 // VPMIN : Vector Pairwise Minimum
2204 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin.s8", v8i8, v8i8,
2205 int_arm_neon_vpmins, 0>;
2206 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin.s16", v4i16, v4i16,
2207 int_arm_neon_vpmins, 0>;
2208 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin.s32", v2i32, v2i32,
2209 int_arm_neon_vpmins, 0>;
2210 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin.u8", v8i8, v8i8,
2211 int_arm_neon_vpminu, 0>;
2212 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin.u16", v4i16, v4i16,
2213 int_arm_neon_vpminu, 0>;
2214 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin.u32", v2i32, v2i32,
2215 int_arm_neon_vpminu, 0>;
2216 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, IIC_VBINi4D, "vpmin.f32", v2f32, v2f32,
2217 int_arm_neon_vpmins, 0>;
2219 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
2221 // VRECPE : Vector Reciprocal Estimate
2222 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
2223 IIC_VUNAD, "vrecpe.u32",
2224 v2i32, v2i32, int_arm_neon_vrecpe>;
2225 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
2226 IIC_VUNAQ, "vrecpe.u32",
2227 v4i32, v4i32, int_arm_neon_vrecpe>;
2228 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
2229 IIC_VUNAD, "vrecpe.f32",
2230 v2f32, v2f32, int_arm_neon_vrecpe>;
2231 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
2232 IIC_VUNAQ, "vrecpe.f32",
2233 v4f32, v4f32, int_arm_neon_vrecpe>;
2235 // VRECPS : Vector Reciprocal Step
2236 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, IIC_VRECSD, "vrecps.f32", v2f32, v2f32,
2237 int_arm_neon_vrecps, 1>;
2238 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, IIC_VRECSQ, "vrecps.f32", v4f32, v4f32,
2239 int_arm_neon_vrecps, 1>;
2241 // VRSQRTE : Vector Reciprocal Square Root Estimate
2242 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
2243 IIC_VUNAD, "vrsqrte.u32",
2244 v2i32, v2i32, int_arm_neon_vrsqrte>;
2245 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
2246 IIC_VUNAQ, "vrsqrte.u32",
2247 v4i32, v4i32, int_arm_neon_vrsqrte>;
2248 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
2249 IIC_VUNAD, "vrsqrte.f32",
2250 v2f32, v2f32, int_arm_neon_vrsqrte>;
2251 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
2252 IIC_VUNAQ, "vrsqrte.f32",
2253 v4f32, v4f32, int_arm_neon_vrsqrte>;
2255 // VRSQRTS : Vector Reciprocal Square Root Step
2256 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, IIC_VRECSD, "vrsqrts.f32", v2f32, v2f32,
2257 int_arm_neon_vrsqrts, 1>;
2258 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, IIC_VRECSQ, "vrsqrts.f32", v4f32, v4f32,
2259 int_arm_neon_vrsqrts, 1>;
2263 // VSHL : Vector Shift
2264 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
2265 IIC_VSHLiQ, "vshl.s", int_arm_neon_vshifts, 0>;
2266 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
2267 IIC_VSHLiQ, "vshl.u", int_arm_neon_vshiftu, 0>;
2268 // VSHL : Vector Shift Left (Immediate)
2269 defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl.i", NEONvshl>;
2270 // VSHR : Vector Shift Right (Immediate)
2271 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr.s", NEONvshrs>;
2272 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr.u", NEONvshru>;
2274 // VSHLL : Vector Shift Left Long
2275 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll.s", NEONvshlls>;
2276 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll.u", NEONvshllu>;
2278 // VSHLL : Vector Shift Left Long (with maximum shift count)
2279 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
2280 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
2281 ValueType OpTy, SDNode OpNode>
2282 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, ResTy, OpTy, OpNode> {
2283 let Inst{21-16} = op21_16;
2285 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll.i8",
2286 v8i16, v8i8, NEONvshlli>;
2287 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll.i16",
2288 v4i32, v4i16, NEONvshlli>;
2289 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll.i32",
2290 v2i64, v2i32, NEONvshlli>;
2292 // VSHRN : Vector Shift Right and Narrow
2293 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn.i", NEONvshrn>;
2295 // VRSHL : Vector Rounding Shift
2296 defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2297 IIC_VSHLi4Q, "vrshl.s", int_arm_neon_vrshifts, 0>;
2298 defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2299 IIC_VSHLi4Q, "vrshl.u", int_arm_neon_vrshiftu, 0>;
2300 // VRSHR : Vector Rounding Shift Right
2301 defm VRSHRs : N2VSh_QHSD<0, 1, 0b0010, 1, IIC_VSHLi4D, "vrshr.s", NEONvrshrs>;
2302 defm VRSHRu : N2VSh_QHSD<1, 1, 0b0010, 1, IIC_VSHLi4D, "vrshr.u", NEONvrshru>;
2304 // VRSHRN : Vector Rounding Shift Right and Narrow
2305 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn.i",
2308 // VQSHL : Vector Saturating Shift
2309 defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2310 IIC_VSHLi4Q, "vqshl.s", int_arm_neon_vqshifts, 0>;
2311 defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2312 IIC_VSHLi4Q, "vqshl.u", int_arm_neon_vqshiftu, 0>;
2313 // VQSHL : Vector Saturating Shift Left (Immediate)
2314 defm VQSHLsi : N2VSh_QHSD<0, 1, 0b0111, 1, IIC_VSHLi4D, "vqshl.s", NEONvqshls>;
2315 defm VQSHLui : N2VSh_QHSD<1, 1, 0b0111, 1, IIC_VSHLi4D, "vqshl.u", NEONvqshlu>;
2316 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
2317 defm VQSHLsu : N2VSh_QHSD<1, 1, 0b0110, 1, IIC_VSHLi4D, "vqshlu.s", NEONvqshlsu>;
2319 // VQSHRN : Vector Saturating Shift Right and Narrow
2320 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn.s",
2322 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn.u",
2325 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
2326 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun.s",
2329 // VQRSHL : Vector Saturating Rounding Shift
2330 defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2331 IIC_VSHLi4Q, "vqrshl.s", int_arm_neon_vqrshifts, 0>;
2332 defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
2333 IIC_VSHLi4Q, "vqrshl.u", int_arm_neon_vqrshiftu, 0>;
2335 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
2336 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn.s",
2338 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn.u",
2341 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
2342 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun.s",
2345 // VSRA : Vector Shift Right and Accumulate
2346 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra.s", NEONvshrs>;
2347 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra.u", NEONvshru>;
2348 // VRSRA : Vector Rounding Shift Right and Accumulate
2349 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra.s", NEONvrshrs>;
2350 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra.u", NEONvrshru>;
2352 // VSLI : Vector Shift Left and Insert
2353 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli.", NEONvsli>;
2354 // VSRI : Vector Shift Right and Insert
2355 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri.", NEONvsri>;
2357 // Vector Absolute and Saturating Absolute.
2359 // VABS : Vector Absolute Value
2360 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
2361 IIC_VUNAiD, IIC_VUNAiQ, "vabs.s",
2363 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2364 IIC_VUNAD, "vabs.f32",
2365 v2f32, v2f32, int_arm_neon_vabs>;
2366 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2367 IIC_VUNAQ, "vabs.f32",
2368 v4f32, v4f32, int_arm_neon_vabs>;
2370 // VQABS : Vector Saturating Absolute Value
2371 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
2372 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs.s",
2373 int_arm_neon_vqabs>;
2377 def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
2378 def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>;
2380 class VNEGD<bits<2> size, string OpcodeStr, ValueType Ty>
2381 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
2382 IIC_VSHLiD, OpcodeStr, "\t$dst, $src", "",
2383 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>;
2384 class VNEGQ<bits<2> size, string OpcodeStr, ValueType Ty>
2385 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
2386 IIC_VSHLiD, OpcodeStr, "\t$dst, $src", "",
2387 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>;
2389 // VNEG : Vector Negate
2390 def VNEGs8d : VNEGD<0b00, "vneg.s8", v8i8>;
2391 def VNEGs16d : VNEGD<0b01, "vneg.s16", v4i16>;
2392 def VNEGs32d : VNEGD<0b10, "vneg.s32", v2i32>;
2393 def VNEGs8q : VNEGQ<0b00, "vneg.s8", v16i8>;
2394 def VNEGs16q : VNEGQ<0b01, "vneg.s16", v8i16>;
2395 def VNEGs32q : VNEGQ<0b10, "vneg.s32", v4i32>;
2397 // VNEG : Vector Negate (floating-point)
2398 def VNEGf32d : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
2399 (outs DPR:$dst), (ins DPR:$src), IIC_VUNAD,
2400 "vneg.f32", "\t$dst, $src", "",
2401 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
2402 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
2403 (outs QPR:$dst), (ins QPR:$src), IIC_VUNAQ,
2404 "vneg.f32", "\t$dst, $src", "",
2405 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
2407 def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
2408 def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
2409 def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>;
2410 def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>;
2411 def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>;
2412 def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>;
2414 // VQNEG : Vector Saturating Negate
2415 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
2416 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg.s",
2417 int_arm_neon_vqneg>;
2419 // Vector Bit Counting Operations.
2421 // VCLS : Vector Count Leading Sign Bits
2422 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
2423 IIC_VCNTiD, IIC_VCNTiQ, "vcls.s",
2425 // VCLZ : Vector Count Leading Zeros
2426 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
2427 IIC_VCNTiD, IIC_VCNTiQ, "vclz.i",
2429 // VCNT : Vector Count One Bits
2430 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2431 IIC_VCNTiD, "vcnt.8",
2432 v8i8, v8i8, int_arm_neon_vcnt>;
2433 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2434 IIC_VCNTiQ, "vcnt.8",
2435 v16i8, v16i8, int_arm_neon_vcnt>;
2437 // Vector Move Operations.
2439 // VMOV : Vector Move (Register)
2441 def VMOVDneon: N3V<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
2442 IIC_VMOVD, "vmov", "\t$dst, $src", "", []>;
2443 def VMOVQ : N3V<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
2444 IIC_VMOVD, "vmov", "\t$dst, $src", "", []>;
2446 // VMOV : Vector Move (Immediate)
2448 // VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
2449 def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
2450 return ARM::getVMOVImm(N, 1, *CurDAG);
2452 def vmovImm8 : PatLeaf<(build_vector), [{
2453 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
2456 // VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
2457 def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
2458 return ARM::getVMOVImm(N, 2, *CurDAG);
2460 def vmovImm16 : PatLeaf<(build_vector), [{
2461 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
2462 }], VMOV_get_imm16>;
2464 // VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
2465 def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
2466 return ARM::getVMOVImm(N, 4, *CurDAG);
2468 def vmovImm32 : PatLeaf<(build_vector), [{
2469 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
2470 }], VMOV_get_imm32>;
2472 // VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
2473 def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
2474 return ARM::getVMOVImm(N, 8, *CurDAG);
2476 def vmovImm64 : PatLeaf<(build_vector), [{
2477 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
2478 }], VMOV_get_imm64>;
2480 // Note: Some of the cmode bits in the following VMOV instructions need to
2481 // be encoded based on the immed values.
2483 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
2484 (ins h8imm:$SIMM), IIC_VMOVImm,
2485 "vmov.i8", "\t$dst, $SIMM", "",
2486 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
2487 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
2488 (ins h8imm:$SIMM), IIC_VMOVImm,
2489 "vmov.i8", "\t$dst, $SIMM", "",
2490 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
2492 def VMOVv4i16 : N1ModImm<1, 0b000, 0b1000, 0, 0, 0, 1, (outs DPR:$dst),
2493 (ins h16imm:$SIMM), IIC_VMOVImm,
2494 "vmov.i16", "\t$dst, $SIMM", "",
2495 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
2496 def VMOVv8i16 : N1ModImm<1, 0b000, 0b1000, 0, 1, 0, 1, (outs QPR:$dst),
2497 (ins h16imm:$SIMM), IIC_VMOVImm,
2498 "vmov.i16", "\t$dst, $SIMM", "",
2499 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
2501 def VMOVv2i32 : N1ModImm<1, 0b000, 0b0000, 0, 0, 0, 1, (outs DPR:$dst),
2502 (ins h32imm:$SIMM), IIC_VMOVImm,
2503 "vmov.i32", "\t$dst, $SIMM", "",
2504 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
2505 def VMOVv4i32 : N1ModImm<1, 0b000, 0b0000, 0, 1, 0, 1, (outs QPR:$dst),
2506 (ins h32imm:$SIMM), IIC_VMOVImm,
2507 "vmov.i32", "\t$dst, $SIMM", "",
2508 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
2510 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
2511 (ins h64imm:$SIMM), IIC_VMOVImm,
2512 "vmov.i64", "\t$dst, $SIMM", "",
2513 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
2514 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
2515 (ins h64imm:$SIMM), IIC_VMOVImm,
2516 "vmov.i64", "\t$dst, $SIMM", "",
2517 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
2519 // VMOV : Vector Get Lane (move scalar to ARM core register)
2521 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
2522 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2523 IIC_VMOVSI, "vmov", ".s8\t$dst, $src[$lane]",
2524 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
2526 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
2527 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2528 IIC_VMOVSI, "vmov", ".s16\t$dst, $src[$lane]",
2529 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
2531 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
2532 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2533 IIC_VMOVSI, "vmov", ".u8\t$dst, $src[$lane]",
2534 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
2536 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
2537 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2538 IIC_VMOVSI, "vmov", ".u16\t$dst, $src[$lane]",
2539 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
2541 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
2542 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2543 IIC_VMOVSI, "vmov", ".32\t$dst, $src[$lane]",
2544 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
2546 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
2547 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
2548 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2549 (DSubReg_i8_reg imm:$lane))),
2550 (SubReg_i8_lane imm:$lane))>;
2551 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
2552 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2553 (DSubReg_i16_reg imm:$lane))),
2554 (SubReg_i16_lane imm:$lane))>;
2555 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
2556 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2557 (DSubReg_i8_reg imm:$lane))),
2558 (SubReg_i8_lane imm:$lane))>;
2559 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
2560 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2561 (DSubReg_i16_reg imm:$lane))),
2562 (SubReg_i16_lane imm:$lane))>;
2563 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
2564 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
2565 (DSubReg_i32_reg imm:$lane))),
2566 (SubReg_i32_lane imm:$lane))>;
2567 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
2568 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1), DPR_VFP2)),
2569 (SSubReg_f32_reg imm:$src2))>;
2570 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
2571 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1), QPR_VFP2)),
2572 (SSubReg_f32_reg imm:$src2))>;
2573 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
2574 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2575 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
2576 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2579 // VMOV : Vector Set Lane (move ARM core register to scalar)
2581 let Constraints = "$src1 = $dst" in {
2582 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$dst),
2583 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2584 IIC_VMOVISL, "vmov", ".8\t$dst[$lane], $src2",
2585 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
2586 GPR:$src2, imm:$lane))]>;
2587 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$dst),
2588 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2589 IIC_VMOVISL, "vmov", ".16\t$dst[$lane], $src2",
2590 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
2591 GPR:$src2, imm:$lane))]>;
2592 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$dst),
2593 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2594 IIC_VMOVISL, "vmov", ".32\t$dst[$lane], $src2",
2595 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
2596 GPR:$src2, imm:$lane))]>;
2598 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
2599 (v16i8 (INSERT_SUBREG QPR:$src1,
2600 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
2601 (DSubReg_i8_reg imm:$lane))),
2602 GPR:$src2, (SubReg_i8_lane imm:$lane)),
2603 (DSubReg_i8_reg imm:$lane)))>;
2604 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
2605 (v8i16 (INSERT_SUBREG QPR:$src1,
2606 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
2607 (DSubReg_i16_reg imm:$lane))),
2608 GPR:$src2, (SubReg_i16_lane imm:$lane)),
2609 (DSubReg_i16_reg imm:$lane)))>;
2610 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
2611 (v4i32 (INSERT_SUBREG QPR:$src1,
2612 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
2613 (DSubReg_i32_reg imm:$lane))),
2614 GPR:$src2, (SubReg_i32_lane imm:$lane)),
2615 (DSubReg_i32_reg imm:$lane)))>;
2617 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
2618 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
2619 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
2620 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
2621 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
2622 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
2624 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
2625 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
2626 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
2627 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
2629 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
2630 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
2631 def : Pat<(v2f64 (scalar_to_vector DPR:$src)),
2632 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, arm_dsubreg_0)>;
2633 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
2634 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
2636 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
2637 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2638 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
2639 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2640 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
2641 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
2643 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
2644 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
2645 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2647 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
2648 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
2649 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2651 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
2652 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
2653 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
2656 // VDUP : Vector Duplicate (from ARM core register to all elements)
2658 class VDUPD<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
2659 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
2660 IIC_VMOVIS, "vdup", !strconcat(asmSize, "\t$dst, $src"),
2661 [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
2662 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
2663 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
2664 IIC_VMOVIS, "vdup", !strconcat(asmSize, "\t$dst, $src"),
2665 [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
2667 def VDUP8d : VDUPD<0b11101100, 0b00, ".8", v8i8>;
2668 def VDUP16d : VDUPD<0b11101000, 0b01, ".16", v4i16>;
2669 def VDUP32d : VDUPD<0b11101000, 0b00, ".32", v2i32>;
2670 def VDUP8q : VDUPQ<0b11101110, 0b00, ".8", v16i8>;
2671 def VDUP16q : VDUPQ<0b11101010, 0b01, ".16", v8i16>;
2672 def VDUP32q : VDUPQ<0b11101010, 0b00, ".32", v4i32>;
2674 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
2675 IIC_VMOVIS, "vdup", ".32\t$dst, $src",
2676 [(set DPR:$dst, (v2f32 (NEONvdup
2677 (f32 (bitconvert GPR:$src)))))]>;
2678 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
2679 IIC_VMOVIS, "vdup", ".32\t$dst, $src",
2680 [(set QPR:$dst, (v4f32 (NEONvdup
2681 (f32 (bitconvert GPR:$src)))))]>;
2683 // VDUP : Vector Duplicate Lane (from scalar to all elements)
2685 class VDUPLND<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty>
2686 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
2687 (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
2688 OpcodeStr, "\t$dst, $src[$lane]", "",
2689 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
2691 class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr,
2692 ValueType ResTy, ValueType OpTy>
2693 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
2694 (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
2695 OpcodeStr, "\t$dst, $src[$lane]", "",
2696 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src), imm:$lane)))]>;
2698 // Inst{19-16} is partially specified depending on the element size.
2700 def VDUPLN8d : VDUPLND<{?,?}, {?,1}, "vdup.8", v8i8>;
2701 def VDUPLN16d : VDUPLND<{?,?}, {1,0}, "vdup.16", v4i16>;
2702 def VDUPLN32d : VDUPLND<{?,1}, {0,0}, "vdup.32", v2i32>;
2703 def VDUPLNfd : VDUPLND<{?,1}, {0,0}, "vdup.32", v2f32>;
2704 def VDUPLN8q : VDUPLNQ<{?,?}, {?,1}, "vdup.8", v16i8, v8i8>;
2705 def VDUPLN16q : VDUPLNQ<{?,?}, {1,0}, "vdup.16", v8i16, v4i16>;
2706 def VDUPLN32q : VDUPLNQ<{?,1}, {0,0}, "vdup.32", v4i32, v2i32>;
2707 def VDUPLNfq : VDUPLNQ<{?,1}, {0,0}, "vdup.32", v4f32, v2f32>;
2709 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
2710 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
2711 (DSubReg_i8_reg imm:$lane))),
2712 (SubReg_i8_lane imm:$lane)))>;
2713 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
2714 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
2715 (DSubReg_i16_reg imm:$lane))),
2716 (SubReg_i16_lane imm:$lane)))>;
2717 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
2718 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
2719 (DSubReg_i32_reg imm:$lane))),
2720 (SubReg_i32_lane imm:$lane)))>;
2721 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
2722 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
2723 (DSubReg_i32_reg imm:$lane))),
2724 (SubReg_i32_lane imm:$lane)))>;
2726 def VDUPfdf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 0, 0,
2727 (outs DPR:$dst), (ins SPR:$src),
2728 IIC_VMOVD, "vdup.32", "\t$dst, ${src:lane}", "",
2729 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
2731 def VDUPfqf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 1, 0,
2732 (outs QPR:$dst), (ins SPR:$src),
2733 IIC_VMOVD, "vdup.32", "\t$dst, ${src:lane}", "",
2734 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
2736 def : Pat<(v2i64 (NEONvduplane (v2i64 QPR:$src), imm:$lane)),
2737 (INSERT_SUBREG QPR:$src,
2738 (i64 (EXTRACT_SUBREG QPR:$src, (DSubReg_f64_reg imm:$lane))),
2739 (DSubReg_f64_other_reg imm:$lane))>;
2740 def : Pat<(v2f64 (NEONvduplane (v2f64 QPR:$src), imm:$lane)),
2741 (INSERT_SUBREG QPR:$src,
2742 (f64 (EXTRACT_SUBREG QPR:$src, (DSubReg_f64_reg imm:$lane))),
2743 (DSubReg_f64_other_reg imm:$lane))>;
2745 // VMOVN : Vector Narrowing Move
2746 defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVD, "vmovn.i",
2747 int_arm_neon_vmovn>;
2748 // VQMOVN : Vector Saturating Narrowing Move
2749 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD, "vqmovn.s",
2750 int_arm_neon_vqmovns>;
2751 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD, "vqmovn.u",
2752 int_arm_neon_vqmovnu>;
2753 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD, "vqmovun.s",
2754 int_arm_neon_vqmovnsu>;
2755 // VMOVL : Vector Lengthening Move
2756 defm VMOVLs : N2VLInt_QHS<0b01,0b10100,0,1, "vmovl.s", int_arm_neon_vmovls>;
2757 defm VMOVLu : N2VLInt_QHS<0b11,0b10100,0,1, "vmovl.u", int_arm_neon_vmovlu>;
2759 // Vector Conversions.
2761 // VCVT : Vector Convert Between Floating-Point and Integers
2762 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
2763 v2i32, v2f32, fp_to_sint>;
2764 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
2765 v2i32, v2f32, fp_to_uint>;
2766 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
2767 v2f32, v2i32, sint_to_fp>;
2768 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
2769 v2f32, v2i32, uint_to_fp>;
2771 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
2772 v4i32, v4f32, fp_to_sint>;
2773 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
2774 v4i32, v4f32, fp_to_uint>;
2775 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
2776 v4f32, v4i32, sint_to_fp>;
2777 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
2778 v4f32, v4i32, uint_to_fp>;
2780 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
2781 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt.s32.f32",
2782 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
2783 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt.u32.f32",
2784 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
2785 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt.f32.s32",
2786 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
2787 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt.f32.u32",
2788 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
2790 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt.s32.f32",
2791 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
2792 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt.u32.f32",
2793 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
2794 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt.f32.s32",
2795 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
2796 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt.f32.u32",
2797 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
2801 // VREV64 : Vector Reverse elements within 64-bit doublewords
2803 class VREV64D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2804 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
2805 (ins DPR:$src), IIC_VMOVD,
2806 OpcodeStr, "\t$dst, $src", "",
2807 [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
2808 class VREV64Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2809 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
2810 (ins QPR:$src), IIC_VMOVD,
2811 OpcodeStr, "\t$dst, $src", "",
2812 [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
2814 def VREV64d8 : VREV64D<0b00, "vrev64.8", v8i8>;
2815 def VREV64d16 : VREV64D<0b01, "vrev64.16", v4i16>;
2816 def VREV64d32 : VREV64D<0b10, "vrev64.32", v2i32>;
2817 def VREV64df : VREV64D<0b10, "vrev64.32", v2f32>;
2819 def VREV64q8 : VREV64Q<0b00, "vrev64.8", v16i8>;
2820 def VREV64q16 : VREV64Q<0b01, "vrev64.16", v8i16>;
2821 def VREV64q32 : VREV64Q<0b10, "vrev64.32", v4i32>;
2822 def VREV64qf : VREV64Q<0b10, "vrev64.32", v4f32>;
2824 // VREV32 : Vector Reverse elements within 32-bit words
2826 class VREV32D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2827 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
2828 (ins DPR:$src), IIC_VMOVD,
2829 OpcodeStr, "\t$dst, $src", "",
2830 [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
2831 class VREV32Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2832 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
2833 (ins QPR:$src), IIC_VMOVD,
2834 OpcodeStr, "\t$dst, $src", "",
2835 [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
2837 def VREV32d8 : VREV32D<0b00, "vrev32.8", v8i8>;
2838 def VREV32d16 : VREV32D<0b01, "vrev32.16", v4i16>;
2840 def VREV32q8 : VREV32Q<0b00, "vrev32.8", v16i8>;
2841 def VREV32q16 : VREV32Q<0b01, "vrev32.16", v8i16>;
2843 // VREV16 : Vector Reverse elements within 16-bit halfwords
2845 class VREV16D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2846 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
2847 (ins DPR:$src), IIC_VMOVD,
2848 OpcodeStr, "\t$dst, $src", "",
2849 [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
2850 class VREV16Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2851 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
2852 (ins QPR:$src), IIC_VMOVD,
2853 OpcodeStr, "\t$dst, $src", "",
2854 [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
2856 def VREV16d8 : VREV16D<0b00, "vrev16.8", v8i8>;
2857 def VREV16q8 : VREV16Q<0b00, "vrev16.8", v16i8>;
2859 // Other Vector Shuffles.
2861 // VEXT : Vector Extract
2863 class VEXTd<string OpcodeStr, ValueType Ty>
2864 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$dst),
2865 (ins DPR:$lhs, DPR:$rhs, i32imm:$index), IIC_VEXTD,
2866 OpcodeStr, "\t$dst, $lhs, $rhs, $index", "",
2867 [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
2868 (Ty DPR:$rhs), imm:$index)))]>;
2870 class VEXTq<string OpcodeStr, ValueType Ty>
2871 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$dst),
2872 (ins QPR:$lhs, QPR:$rhs, i32imm:$index), IIC_VEXTQ,
2873 OpcodeStr, "\t$dst, $lhs, $rhs, $index", "",
2874 [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
2875 (Ty QPR:$rhs), imm:$index)))]>;
2877 def VEXTd8 : VEXTd<"vext.8", v8i8>;
2878 def VEXTd16 : VEXTd<"vext.16", v4i16>;
2879 def VEXTd32 : VEXTd<"vext.32", v2i32>;
2880 def VEXTdf : VEXTd<"vext.32", v2f32>;
2882 def VEXTq8 : VEXTq<"vext.8", v16i8>;
2883 def VEXTq16 : VEXTq<"vext.16", v8i16>;
2884 def VEXTq32 : VEXTq<"vext.32", v4i32>;
2885 def VEXTqf : VEXTq<"vext.32", v4f32>;
2887 // VTRN : Vector Transpose
2889 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn.8">;
2890 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn.16">;
2891 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn.32">;
2893 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn.8">;
2894 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn.16">;
2895 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn.32">;
2897 // VUZP : Vector Unzip (Deinterleave)
2899 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp.8">;
2900 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp.16">;
2901 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp.32">;
2903 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp.8">;
2904 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp.16">;
2905 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp.32">;
2907 // VZIP : Vector Zip (Interleave)
2909 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip.8">;
2910 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip.16">;
2911 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip.32">;
2913 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip.8">;
2914 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip.16">;
2915 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip.32">;
2917 // Vector Table Lookup and Table Extension.
2919 // VTBL : Vector Table Lookup
2921 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
2922 (ins DPR:$tbl1, DPR:$src), IIC_VTB1,
2923 "vtbl.8", "\t$dst, \\{$tbl1\\}, $src", "",
2924 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
2925 let hasExtraSrcRegAllocReq = 1 in {
2927 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
2928 (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTB2,
2929 "vtbl.8", "\t$dst, \\{$tbl1,$tbl2\\}, $src", "",
2930 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl2
2931 DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
2933 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
2934 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTB3,
2935 "vtbl.8", "\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "",
2936 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl3
2937 DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
2939 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
2940 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTB4,
2941 "vtbl.8", "\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "",
2942 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl4 DPR:$tbl1, DPR:$tbl2,
2943 DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
2944 } // hasExtraSrcRegAllocReq = 1
2946 // VTBX : Vector Table Extension
2948 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
2949 (ins DPR:$orig, DPR:$tbl1, DPR:$src), IIC_VTBX1,
2950 "vtbx.8", "\t$dst, \\{$tbl1\\}, $src", "$orig = $dst",
2951 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
2952 DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
2953 let hasExtraSrcRegAllocReq = 1 in {
2955 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
2956 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTBX2,
2957 "vtbx.8", "\t$dst, \\{$tbl1,$tbl2\\}, $src", "$orig = $dst",
2958 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx2
2959 DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
2961 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
2962 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTBX3,
2963 "vtbx.8", "\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "$orig = $dst",
2964 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx3 DPR:$orig, DPR:$tbl1,
2965 DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
2967 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
2968 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTBX4,
2969 "vtbx.8", "\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "$orig = $dst",
2970 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx4 DPR:$orig, DPR:$tbl1,
2971 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
2972 } // hasExtraSrcRegAllocReq = 1
2974 //===----------------------------------------------------------------------===//
2975 // NEON instructions for single-precision FP math
2976 //===----------------------------------------------------------------------===//
2978 // These need separate instructions because they must use DPR_VFP2 register
2979 // class which have SPR sub-registers.
2981 // Vector Add Operations used for single-precision FP
2982 let neverHasSideEffects = 1 in
2983 def VADDfd_sfp : N3VDs<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd,1>;
2984 def : N3VDsPat<fadd, VADDfd_sfp>;
2986 // Vector Sub Operations used for single-precision FP
2987 let neverHasSideEffects = 1 in
2988 def VSUBfd_sfp : N3VDs<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub,0>;
2989 def : N3VDsPat<fsub, VSUBfd_sfp>;
2991 // Vector Multiply Operations used for single-precision FP
2992 let neverHasSideEffects = 1 in
2993 def VMULfd_sfp : N3VDs<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul,1>;
2994 def : N3VDsPat<fmul, VMULfd_sfp>;
2996 // Vector Multiply-Accumulate/Subtract used for single-precision FP
2997 // vml[as].f32 can cause 4-8 cycle stalls in following ASIMD instructions, so
2998 // we want to avoid them for now. e.g., alternating vmla/vadd instructions.
3000 //let neverHasSideEffects = 1 in
3001 //def VMLAfd_sfp : N3VDMulOps<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla.f32", v2f32,fmul,fadd>;
3002 //def : N3VDMulOpsPat<fmul, fadd, VMLAfd_sfp>;
3004 //let neverHasSideEffects = 1 in
3005 //def VMLSfd_sfp : N3VDMulOps<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls.f32", v2f32,fmul,fsub>;
3006 //def : N3VDMulOpsPat<fmul, fsub, VMLSfd_sfp>;
3008 // Vector Absolute used for single-precision FP
3009 let neverHasSideEffects = 1 in
3010 def VABSfd_sfp : N2VDInts<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
3011 IIC_VUNAD, "vabs.f32",
3012 v2f32, v2f32, int_arm_neon_vabs>;
3013 def : N2VDIntsPat<fabs, VABSfd_sfp>;
3015 // Vector Negate used for single-precision FP
3016 let neverHasSideEffects = 1 in
3017 def VNEGf32d_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
3018 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
3019 "vneg.f32", "\t$dst, $src", "", []>;
3020 def : N2VDIntsPat<fneg, VNEGf32d_sfp>;
3022 // Vector Convert between single-precision FP and integer
3023 let neverHasSideEffects = 1 in
3024 def VCVTf2sd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
3025 v2i32, v2f32, fp_to_sint>;
3026 def : N2VDsPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
3028 let neverHasSideEffects = 1 in
3029 def VCVTf2ud_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
3030 v2i32, v2f32, fp_to_uint>;
3031 def : N2VDsPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
3033 let neverHasSideEffects = 1 in
3034 def VCVTs2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
3035 v2f32, v2i32, sint_to_fp>;
3036 def : N2VDsPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
3038 let neverHasSideEffects = 1 in
3039 def VCVTu2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
3040 v2f32, v2i32, uint_to_fp>;
3041 def : N2VDsPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
3043 //===----------------------------------------------------------------------===//
3044 // Non-Instruction Patterns
3045 //===----------------------------------------------------------------------===//
3048 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
3049 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
3050 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
3051 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
3052 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
3053 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
3054 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
3055 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
3056 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
3057 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
3058 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
3059 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
3060 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
3061 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
3062 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
3063 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
3064 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
3065 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
3066 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
3067 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
3068 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
3069 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
3070 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
3071 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
3072 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
3073 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
3074 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
3075 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
3076 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
3077 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
3079 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
3080 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
3081 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
3082 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
3083 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
3084 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
3085 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
3086 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
3087 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
3088 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
3089 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
3090 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
3091 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
3092 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
3093 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
3094 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
3095 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
3096 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
3097 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
3098 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
3099 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
3100 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
3101 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
3102 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
3103 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
3104 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
3105 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
3106 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
3107 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
3108 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;