1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // NEON-specific Operands.
17 //===----------------------------------------------------------------------===//
18 def nModImm : Operand<i32> {
19 let PrintMethod = "printNEONModImmOperand";
22 def nImmSplatI8AsmOperand : AsmOperandClass { let Name = "NEONi8splat"; }
23 def nImmSplatI8 : Operand<i32> {
24 let PrintMethod = "printNEONModImmOperand";
25 let ParserMatchClass = nImmSplatI8AsmOperand;
27 def nImmSplatI16AsmOperand : AsmOperandClass { let Name = "NEONi16splat"; }
28 def nImmSplatI16 : Operand<i32> {
29 let PrintMethod = "printNEONModImmOperand";
30 let ParserMatchClass = nImmSplatI16AsmOperand;
32 def nImmSplatI32AsmOperand : AsmOperandClass { let Name = "NEONi32splat"; }
33 def nImmSplatI32 : Operand<i32> {
34 let PrintMethod = "printNEONModImmOperand";
35 let ParserMatchClass = nImmSplatI32AsmOperand;
37 def nImmVMOVI32AsmOperand : AsmOperandClass { let Name = "NEONi32vmov"; }
38 def nImmVMOVI32 : Operand<i32> {
39 let PrintMethod = "printNEONModImmOperand";
40 let ParserMatchClass = nImmVMOVI32AsmOperand;
42 def nImmVMOVF32 : Operand<i32> {
43 let PrintMethod = "printFPImmOperand";
44 let ParserMatchClass = FPImmOperand;
46 def nImmSplatI64AsmOperand : AsmOperandClass { let Name = "NEONi64splat"; }
47 def nImmSplatI64 : Operand<i32> {
48 let PrintMethod = "printNEONModImmOperand";
49 let ParserMatchClass = nImmSplatI64AsmOperand;
52 def VectorIndex8Operand : AsmOperandClass { let Name = "VectorIndex8"; }
53 def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; }
54 def VectorIndex32Operand : AsmOperandClass { let Name = "VectorIndex32"; }
55 def VectorIndex8 : Operand<i32>, ImmLeaf<i32, [{
56 return ((uint64_t)Imm) < 8;
58 let ParserMatchClass = VectorIndex8Operand;
59 let PrintMethod = "printVectorIndex";
60 let MIOperandInfo = (ops i32imm);
62 def VectorIndex16 : Operand<i32>, ImmLeaf<i32, [{
63 return ((uint64_t)Imm) < 4;
65 let ParserMatchClass = VectorIndex16Operand;
66 let PrintMethod = "printVectorIndex";
67 let MIOperandInfo = (ops i32imm);
69 def VectorIndex32 : Operand<i32>, ImmLeaf<i32, [{
70 return ((uint64_t)Imm) < 2;
72 let ParserMatchClass = VectorIndex32Operand;
73 let PrintMethod = "printVectorIndex";
74 let MIOperandInfo = (ops i32imm);
77 // Register list of one D register.
78 def VecListOneDAsmOperand : AsmOperandClass {
79 let Name = "VecListOneD";
80 let ParserMethod = "parseVectorList";
81 let RenderMethod = "addVecListOperands";
83 def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> {
84 let ParserMatchClass = VecListOneDAsmOperand;
86 // Register list of two sequential D registers.
87 def VecListTwoDAsmOperand : AsmOperandClass {
88 let Name = "VecListTwoD";
89 let ParserMethod = "parseVectorList";
90 let RenderMethod = "addVecListOperands";
92 def VecListTwoD : RegisterOperand<DPR, "printVectorListTwo"> {
93 let ParserMatchClass = VecListTwoDAsmOperand;
95 // Register list of three sequential D registers.
96 def VecListThreeDAsmOperand : AsmOperandClass {
97 let Name = "VecListThreeD";
98 let ParserMethod = "parseVectorList";
99 let RenderMethod = "addVecListOperands";
101 def VecListThreeD : RegisterOperand<DPR, "printVectorListThree"> {
102 let ParserMatchClass = VecListThreeDAsmOperand;
104 // Register list of four sequential D registers.
105 def VecListFourDAsmOperand : AsmOperandClass {
106 let Name = "VecListFourD";
107 let ParserMethod = "parseVectorList";
108 let RenderMethod = "addVecListOperands";
110 def VecListFourD : RegisterOperand<DPR, "printVectorListFour"> {
111 let ParserMatchClass = VecListFourDAsmOperand;
113 // Register list of two D registers spaced by 2 (two sequential Q registers).
114 def VecListTwoQAsmOperand : AsmOperandClass {
115 let Name = "VecListTwoQ";
116 let ParserMethod = "parseVectorList";
117 let RenderMethod = "addVecListOperands";
119 def VecListTwoQ : RegisterOperand<DPR, "printVectorListTwoSpaced"> {
120 let ParserMatchClass = VecListTwoQAsmOperand;
123 // Register list of one D register, with "all lanes" subscripting.
124 def VecListOneDAllLanesAsmOperand : AsmOperandClass {
125 let Name = "VecListOneDAllLanes";
126 let ParserMethod = "parseVectorList";
127 let RenderMethod = "addVecListOperands";
129 def VecListOneDAllLanes : RegisterOperand<DPR, "printVectorListOneAllLanes"> {
130 let ParserMatchClass = VecListOneDAllLanesAsmOperand;
132 // Register list of two D registers, with "all lanes" subscripting.
133 def VecListTwoDAllLanesAsmOperand : AsmOperandClass {
134 let Name = "VecListTwoDAllLanes";
135 let ParserMethod = "parseVectorList";
136 let RenderMethod = "addVecListOperands";
138 def VecListTwoDAllLanes : RegisterOperand<DPR, "printVectorListTwoAllLanes"> {
139 let ParserMatchClass = VecListTwoDAllLanesAsmOperand;
142 // Register list of one D register, with byte lane subscripting.
143 def VecListOneDByteIndexAsmOperand : AsmOperandClass {
144 let Name = "VecListOneDByteIndexed";
145 let ParserMethod = "parseVectorList";
146 let RenderMethod = "addVecListIndexedOperands";
148 def VecListOneDByteIndexed : Operand<i32> {
149 let ParserMatchClass = VecListOneDByteIndexAsmOperand;
150 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
152 // ...with half-word lane subscripting.
153 def VecListOneDHWordIndexAsmOperand : AsmOperandClass {
154 let Name = "VecListOneDHWordIndexed";
155 let ParserMethod = "parseVectorList";
156 let RenderMethod = "addVecListIndexedOperands";
158 def VecListOneDHWordIndexed : Operand<i32> {
159 let ParserMatchClass = VecListOneDHWordIndexAsmOperand;
160 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
162 // ...with word lane subscripting.
163 def VecListOneDWordIndexAsmOperand : AsmOperandClass {
164 let Name = "VecListOneDWordIndexed";
165 let ParserMethod = "parseVectorList";
166 let RenderMethod = "addVecListIndexedOperands";
168 def VecListOneDWordIndexed : Operand<i32> {
169 let ParserMatchClass = VecListOneDWordIndexAsmOperand;
170 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
172 // Register list of two D registers, with byte lane subscripting.
173 def VecListTwoDByteIndexAsmOperand : AsmOperandClass {
174 let Name = "VecListTwoDByteIndexed";
175 let ParserMethod = "parseVectorList";
176 let RenderMethod = "addVecListIndexedOperands";
178 def VecListTwoDByteIndexed : Operand<i32> {
179 let ParserMatchClass = VecListTwoDByteIndexAsmOperand;
180 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
182 // ...with half-word lane subscripting.
183 def VecListTwoDHWordIndexAsmOperand : AsmOperandClass {
184 let Name = "VecListTwoDHWordIndexed";
185 let ParserMethod = "parseVectorList";
186 let RenderMethod = "addVecListIndexedOperands";
188 def VecListTwoDHWordIndexed : Operand<i32> {
189 let ParserMatchClass = VecListTwoDHWordIndexAsmOperand;
190 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
192 // ...with word lane subscripting.
193 def VecListTwoDWordIndexAsmOperand : AsmOperandClass {
194 let Name = "VecListTwoDWordIndexed";
195 let ParserMethod = "parseVectorList";
196 let RenderMethod = "addVecListIndexedOperands";
198 def VecListTwoDWordIndexed : Operand<i32> {
199 let ParserMatchClass = VecListTwoDWordIndexAsmOperand;
200 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
203 //===----------------------------------------------------------------------===//
204 // NEON-specific DAG Nodes.
205 //===----------------------------------------------------------------------===//
207 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
208 def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
210 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
211 def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
212 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
213 def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
214 def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
215 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
216 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
217 def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
218 def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
219 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
220 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
222 // Types for vector shift by immediates. The "SHX" version is for long and
223 // narrow operations where the source and destination vectors have different
224 // types. The "SHINS" version is for shift and insert operations.
225 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
227 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
229 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
230 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
232 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
233 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
234 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
235 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
236 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
237 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
238 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
240 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
241 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
242 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
244 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
245 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
246 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
247 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
248 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
249 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
251 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
252 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
253 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
255 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
256 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
258 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
260 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
261 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
263 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
264 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
265 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
266 def NEONvmovFPImm : SDNode<"ARMISD::VMOVFPIMM", SDTARMVMOVIMM>;
268 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
270 def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
271 def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
273 def NEONvbsl : SDNode<"ARMISD::VBSL",
274 SDTypeProfile<1, 3, [SDTCisVec<0>,
277 SDTCisSameAs<0, 3>]>>;
279 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
281 // VDUPLANE can produce a quad-register result from a double-register source,
282 // so the result is not constrained to match the source.
283 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
284 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
287 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
288 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
289 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
291 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
292 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
293 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
294 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
296 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
298 SDTCisSameAs<0, 3>]>;
299 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
300 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
301 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
303 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
304 SDTCisSameAs<1, 2>]>;
305 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
306 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
308 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
309 SDTCisSameAs<0, 2>]>;
310 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
311 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
313 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
314 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
315 unsigned EltBits = 0;
316 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
317 return (EltBits == 32 && EltVal == 0);
320 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
321 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
322 unsigned EltBits = 0;
323 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
324 return (EltBits == 8 && EltVal == 0xff);
327 //===----------------------------------------------------------------------===//
328 // NEON load / store instructions
329 //===----------------------------------------------------------------------===//
331 // Use VLDM to load a Q register as a D register pair.
332 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
334 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
336 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
338 // Use VSTM to store a Q register as a D register pair.
339 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
341 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
343 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
345 // Classes for VLD* pseudo-instructions with multi-register operands.
346 // These are expanded to real instructions after register allocation.
347 class VLDQPseudo<InstrItinClass itin>
348 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
349 class VLDQWBPseudo<InstrItinClass itin>
350 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
351 (ins addrmode6:$addr, am6offset:$offset), itin,
353 class VLDQWBfixedPseudo<InstrItinClass itin>
354 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
355 (ins addrmode6:$addr), itin,
357 class VLDQWBregisterPseudo<InstrItinClass itin>
358 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
359 (ins addrmode6:$addr, rGPR:$offset), itin,
362 class VLDQQPseudo<InstrItinClass itin>
363 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
364 class VLDQQWBPseudo<InstrItinClass itin>
365 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
366 (ins addrmode6:$addr, am6offset:$offset), itin,
368 class VLDQQWBfixedPseudo<InstrItinClass itin>
369 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
370 (ins addrmode6:$addr), itin,
372 class VLDQQWBregisterPseudo<InstrItinClass itin>
373 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
374 (ins addrmode6:$addr, rGPR:$offset), itin,
378 class VLDQQQQPseudo<InstrItinClass itin>
379 : PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src),itin,
381 class VLDQQQQWBPseudo<InstrItinClass itin>
382 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
383 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
384 "$addr.addr = $wb, $src = $dst">;
386 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
388 // VLD1 : Vector Load (multiple single elements)
389 class VLD1D<bits<4> op7_4, string Dt>
390 : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd),
391 (ins addrmode6:$Rn), IIC_VLD1,
392 "vld1", Dt, "$Vd, $Rn", "", []> {
395 let DecoderMethod = "DecodeVLDInstruction";
397 class VLD1Q<bits<4> op7_4, string Dt>
398 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd),
399 (ins addrmode6:$Rn), IIC_VLD1x2,
400 "vld1", Dt, "$Vd, $Rn", "", []> {
402 let Inst{5-4} = Rn{5-4};
403 let DecoderMethod = "DecodeVLDInstruction";
406 def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
407 def VLD1d16 : VLD1D<{0,1,0,?}, "16">;
408 def VLD1d32 : VLD1D<{1,0,0,?}, "32">;
409 def VLD1d64 : VLD1D<{1,1,0,?}, "64">;
411 def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;
412 def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
413 def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
414 def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
416 def VLD1q8Pseudo : VLDQPseudo<IIC_VLD1x2>;
417 def VLD1q16Pseudo : VLDQPseudo<IIC_VLD1x2>;
418 def VLD1q32Pseudo : VLDQPseudo<IIC_VLD1x2>;
419 def VLD1q64Pseudo : VLDQPseudo<IIC_VLD1x2>;
421 // ...with address register writeback:
422 multiclass VLD1DWB<bits<4> op7_4, string Dt> {
423 def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
424 (ins addrmode6:$Rn), IIC_VLD1u,
425 "vld1", Dt, "$Vd, $Rn!",
426 "$Rn.addr = $wb", []> {
427 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
429 let DecoderMethod = "DecodeVLDInstruction";
430 let AsmMatchConverter = "cvtVLDwbFixed";
432 def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
433 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1u,
434 "vld1", Dt, "$Vd, $Rn, $Rm",
435 "$Rn.addr = $wb", []> {
437 let DecoderMethod = "DecodeVLDInstruction";
438 let AsmMatchConverter = "cvtVLDwbRegister";
441 multiclass VLD1QWB<bits<4> op7_4, string Dt> {
442 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd, GPR:$wb),
443 (ins addrmode6:$Rn), IIC_VLD1x2u,
444 "vld1", Dt, "$Vd, $Rn!",
445 "$Rn.addr = $wb", []> {
446 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
447 let Inst{5-4} = Rn{5-4};
448 let DecoderMethod = "DecodeVLDInstruction";
449 let AsmMatchConverter = "cvtVLDwbFixed";
451 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd, GPR:$wb),
452 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
453 "vld1", Dt, "$Vd, $Rn, $Rm",
454 "$Rn.addr = $wb", []> {
455 let Inst{5-4} = Rn{5-4};
456 let DecoderMethod = "DecodeVLDInstruction";
457 let AsmMatchConverter = "cvtVLDwbRegister";
461 defm VLD1d8wb : VLD1DWB<{0,0,0,?}, "8">;
462 defm VLD1d16wb : VLD1DWB<{0,1,0,?}, "16">;
463 defm VLD1d32wb : VLD1DWB<{1,0,0,?}, "32">;
464 defm VLD1d64wb : VLD1DWB<{1,1,0,?}, "64">;
465 defm VLD1q8wb : VLD1QWB<{0,0,?,?}, "8">;
466 defm VLD1q16wb : VLD1QWB<{0,1,?,?}, "16">;
467 defm VLD1q32wb : VLD1QWB<{1,0,?,?}, "32">;
468 defm VLD1q64wb : VLD1QWB<{1,1,?,?}, "64">;
470 def VLD1q8PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
471 def VLD1q16PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
472 def VLD1q32PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
473 def VLD1q64PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
474 def VLD1q8PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
475 def VLD1q16PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
476 def VLD1q32PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
477 def VLD1q64PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
479 // ...with 3 registers
480 class VLD1D3<bits<4> op7_4, string Dt>
481 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd),
482 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
483 "$Vd, $Rn", "", []> {
486 let DecoderMethod = "DecodeVLDInstruction";
488 multiclass VLD1D3WB<bits<4> op7_4, string Dt> {
489 def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
490 (ins addrmode6:$Rn), IIC_VLD1x2u,
491 "vld1", Dt, "$Vd, $Rn!",
492 "$Rn.addr = $wb", []> {
493 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
495 let DecoderMethod = "DecodeVLDInstruction";
496 let AsmMatchConverter = "cvtVLDwbFixed";
498 def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
499 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
500 "vld1", Dt, "$Vd, $Rn, $Rm",
501 "$Rn.addr = $wb", []> {
503 let DecoderMethod = "DecodeVLDInstruction";
504 let AsmMatchConverter = "cvtVLDwbRegister";
508 def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
509 def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;
510 def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;
511 def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;
513 defm VLD1d8Twb : VLD1D3WB<{0,0,0,?}, "8">;
514 defm VLD1d16Twb : VLD1D3WB<{0,1,0,?}, "16">;
515 defm VLD1d32Twb : VLD1D3WB<{1,0,0,?}, "32">;
516 defm VLD1d64Twb : VLD1D3WB<{1,1,0,?}, "64">;
518 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
520 // ...with 4 registers
521 class VLD1D4<bits<4> op7_4, string Dt>
522 : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd),
523 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
524 "$Vd, $Rn", "", []> {
526 let Inst{5-4} = Rn{5-4};
527 let DecoderMethod = "DecodeVLDInstruction";
529 multiclass VLD1D4WB<bits<4> op7_4, string Dt> {
530 def _fixed : NLdSt<0,0b10,0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb),
531 (ins addrmode6:$Rn), IIC_VLD1x2u,
532 "vld1", Dt, "$Vd, $Rn!",
533 "$Rn.addr = $wb", []> {
534 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
535 let Inst{5-4} = Rn{5-4};
536 let DecoderMethod = "DecodeVLDInstruction";
537 let AsmMatchConverter = "cvtVLDwbFixed";
539 def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb),
540 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
541 "vld1", Dt, "$Vd, $Rn, $Rm",
542 "$Rn.addr = $wb", []> {
543 let Inst{5-4} = Rn{5-4};
544 let DecoderMethod = "DecodeVLDInstruction";
545 let AsmMatchConverter = "cvtVLDwbRegister";
549 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
550 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;
551 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;
552 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;
554 defm VLD1d8Qwb : VLD1D4WB<{0,0,?,?}, "8">;
555 defm VLD1d16Qwb : VLD1D4WB<{0,1,?,?}, "16">;
556 defm VLD1d32Qwb : VLD1D4WB<{1,0,?,?}, "32">;
557 defm VLD1d64Qwb : VLD1D4WB<{1,1,?,?}, "64">;
559 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
561 // VLD2 : Vector Load (multiple 2-element structures)
562 class VLD2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
564 : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd),
565 (ins addrmode6:$Rn), itin,
566 "vld2", Dt, "$Vd, $Rn", "", []> {
568 let Inst{5-4} = Rn{5-4};
569 let DecoderMethod = "DecodeVLDInstruction";
572 def VLD2d8 : VLD2<0b1000, {0,0,?,?}, "8", VecListTwoD, IIC_VLD2>;
573 def VLD2d16 : VLD2<0b1000, {0,1,?,?}, "16", VecListTwoD, IIC_VLD2>;
574 def VLD2d32 : VLD2<0b1000, {1,0,?,?}, "32", VecListTwoD, IIC_VLD2>;
576 def VLD2q8 : VLD2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2>;
577 def VLD2q16 : VLD2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2>;
578 def VLD2q32 : VLD2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2>;
580 def VLD2d8Pseudo : VLDQPseudo<IIC_VLD2>;
581 def VLD2d16Pseudo : VLDQPseudo<IIC_VLD2>;
582 def VLD2d32Pseudo : VLDQPseudo<IIC_VLD2>;
584 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
585 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
586 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
588 // ...with address register writeback:
589 multiclass VLD2WB<bits<4> op11_8, bits<4> op7_4, string Dt,
590 RegisterOperand VdTy, InstrItinClass itin> {
591 def _fixed : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
592 (ins addrmode6:$Rn), itin,
593 "vld2", Dt, "$Vd, $Rn!",
594 "$Rn.addr = $wb", []> {
595 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
596 let Inst{5-4} = Rn{5-4};
597 let DecoderMethod = "DecodeVLDInstruction";
598 let AsmMatchConverter = "cvtVLDwbFixed";
600 def _register : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
601 (ins addrmode6:$Rn, rGPR:$Rm), itin,
602 "vld2", Dt, "$Vd, $Rn, $Rm",
603 "$Rn.addr = $wb", []> {
604 let Inst{5-4} = Rn{5-4};
605 let DecoderMethod = "DecodeVLDInstruction";
606 let AsmMatchConverter = "cvtVLDwbRegister";
610 defm VLD2d8wb : VLD2WB<0b1000, {0,0,?,?}, "8", VecListTwoD, IIC_VLD2u>;
611 defm VLD2d16wb : VLD2WB<0b1000, {0,1,?,?}, "16", VecListTwoD, IIC_VLD2u>;
612 defm VLD2d32wb : VLD2WB<0b1000, {1,0,?,?}, "32", VecListTwoD, IIC_VLD2u>;
614 defm VLD2q8wb : VLD2WB<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2u>;
615 defm VLD2q16wb : VLD2WB<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2u>;
616 defm VLD2q32wb : VLD2WB<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2u>;
618 def VLD2d8PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD2u>;
619 def VLD2d16PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD2u>;
620 def VLD2d32PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD2u>;
621 def VLD2d8PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD2u>;
622 def VLD2d16PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD2u>;
623 def VLD2d32PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD2u>;
625 def VLD2q8PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
626 def VLD2q16PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
627 def VLD2q32PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
628 def VLD2q8PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
629 def VLD2q16PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
630 def VLD2q32PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
632 // ...with double-spaced registers
633 def VLD2b8 : VLD2<0b1001, {0,0,?,?}, "8", VecListTwoQ, IIC_VLD2>;
634 def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListTwoQ, IIC_VLD2>;
635 def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListTwoQ, IIC_VLD2>;
636 defm VLD2b8wb : VLD2WB<0b1001, {0,0,?,?}, "8", VecListTwoQ, IIC_VLD2u>;
637 defm VLD2b16wb : VLD2WB<0b1001, {0,1,?,?}, "16", VecListTwoQ, IIC_VLD2u>;
638 defm VLD2b32wb : VLD2WB<0b1001, {1,0,?,?}, "32", VecListTwoQ, IIC_VLD2u>;
640 // VLD3 : Vector Load (multiple 3-element structures)
641 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
642 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
643 (ins addrmode6:$Rn), IIC_VLD3,
644 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
647 let DecoderMethod = "DecodeVLDInstruction";
650 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
651 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
652 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
654 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
655 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
656 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
658 // ...with address register writeback:
659 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
660 : NLdSt<0, 0b10, op11_8, op7_4,
661 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
662 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
663 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
664 "$Rn.addr = $wb", []> {
666 let DecoderMethod = "DecodeVLDInstruction";
669 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
670 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
671 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
673 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
674 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
675 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
677 // ...with double-spaced registers:
678 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
679 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
680 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
681 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
682 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
683 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
685 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
686 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
687 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
689 // ...alternate versions to be allocated odd register numbers:
690 def VLD3q8oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
691 def VLD3q16oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
692 def VLD3q32oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
694 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
695 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
696 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
698 // VLD4 : Vector Load (multiple 4-element structures)
699 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
700 : NLdSt<0, 0b10, op11_8, op7_4,
701 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
702 (ins addrmode6:$Rn), IIC_VLD4,
703 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
705 let Inst{5-4} = Rn{5-4};
706 let DecoderMethod = "DecodeVLDInstruction";
709 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
710 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
711 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
713 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
714 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
715 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
717 // ...with address register writeback:
718 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
719 : NLdSt<0, 0b10, op11_8, op7_4,
720 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
721 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u,
722 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
723 "$Rn.addr = $wb", []> {
724 let Inst{5-4} = Rn{5-4};
725 let DecoderMethod = "DecodeVLDInstruction";
728 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
729 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
730 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
732 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
733 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
734 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
736 // ...with double-spaced registers:
737 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
738 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
739 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
740 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
741 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
742 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
744 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
745 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
746 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
748 // ...alternate versions to be allocated odd register numbers:
749 def VLD4q8oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
750 def VLD4q16oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
751 def VLD4q32oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
753 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
754 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
755 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
757 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
759 // Classes for VLD*LN pseudo-instructions with multi-register operands.
760 // These are expanded to real instructions after register allocation.
761 class VLDQLNPseudo<InstrItinClass itin>
762 : PseudoNLdSt<(outs QPR:$dst),
763 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
764 itin, "$src = $dst">;
765 class VLDQLNWBPseudo<InstrItinClass itin>
766 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
767 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
768 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
769 class VLDQQLNPseudo<InstrItinClass itin>
770 : PseudoNLdSt<(outs QQPR:$dst),
771 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
772 itin, "$src = $dst">;
773 class VLDQQLNWBPseudo<InstrItinClass itin>
774 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
775 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
776 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
777 class VLDQQQQLNPseudo<InstrItinClass itin>
778 : PseudoNLdSt<(outs QQQQPR:$dst),
779 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
780 itin, "$src = $dst">;
781 class VLDQQQQLNWBPseudo<InstrItinClass itin>
782 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
783 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
784 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
786 // VLD1LN : Vector Load (single element to one lane)
787 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
789 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
790 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
791 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
793 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
794 (i32 (LoadOp addrmode6:$Rn)),
797 let DecoderMethod = "DecodeVLD1LN";
799 class VLD1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
801 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
802 (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane),
803 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
805 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
806 (i32 (LoadOp addrmode6oneL32:$Rn)),
809 let DecoderMethod = "DecodeVLD1LN";
811 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
812 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
813 (i32 (LoadOp addrmode6:$addr)),
817 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
818 let Inst{7-5} = lane{2-0};
820 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
821 let Inst{7-6} = lane{1-0};
824 def VLD1LNd32 : VLD1LN32<0b1000, {?,0,?,?}, "32", v2i32, load> {
825 let Inst{7} = lane{0};
830 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
831 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
832 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
834 def : Pat<(vector_insert (v2f32 DPR:$src),
835 (f32 (load addrmode6:$addr)), imm:$lane),
836 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
837 def : Pat<(vector_insert (v4f32 QPR:$src),
838 (f32 (load addrmode6:$addr)), imm:$lane),
839 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
841 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
843 // ...with address register writeback:
844 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
845 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
846 (ins addrmode6:$Rn, am6offset:$Rm,
847 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
848 "\\{$Vd[$lane]\\}, $Rn$Rm",
849 "$src = $Vd, $Rn.addr = $wb", []> {
850 let DecoderMethod = "DecodeVLD1LN";
853 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
854 let Inst{7-5} = lane{2-0};
856 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
857 let Inst{7-6} = lane{1-0};
860 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
861 let Inst{7} = lane{0};
866 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
867 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
868 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
870 // VLD2LN : Vector Load (single 2-element structure to one lane)
871 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
872 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
873 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
874 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
875 "$src1 = $Vd, $src2 = $dst2", []> {
878 let DecoderMethod = "DecodeVLD2LN";
881 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
882 let Inst{7-5} = lane{2-0};
884 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
885 let Inst{7-6} = lane{1-0};
887 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
888 let Inst{7} = lane{0};
891 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
892 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
893 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
895 // ...with double-spaced registers:
896 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
897 let Inst{7-6} = lane{1-0};
899 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
900 let Inst{7} = lane{0};
903 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
904 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
906 // ...with address register writeback:
907 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
908 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
909 (ins addrmode6:$Rn, am6offset:$Rm,
910 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
911 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
912 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
914 let DecoderMethod = "DecodeVLD2LN";
917 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
918 let Inst{7-5} = lane{2-0};
920 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
921 let Inst{7-6} = lane{1-0};
923 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
924 let Inst{7} = lane{0};
927 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
928 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
929 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
931 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
932 let Inst{7-6} = lane{1-0};
934 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
935 let Inst{7} = lane{0};
938 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
939 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
941 // VLD3LN : Vector Load (single 3-element structure to one lane)
942 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
943 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
944 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
945 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
946 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
947 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
949 let DecoderMethod = "DecodeVLD3LN";
952 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
953 let Inst{7-5} = lane{2-0};
955 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
956 let Inst{7-6} = lane{1-0};
958 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
959 let Inst{7} = lane{0};
962 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
963 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
964 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
966 // ...with double-spaced registers:
967 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
968 let Inst{7-6} = lane{1-0};
970 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
971 let Inst{7} = lane{0};
974 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
975 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
977 // ...with address register writeback:
978 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
979 : NLdStLn<1, 0b10, op11_8, op7_4,
980 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
981 (ins addrmode6:$Rn, am6offset:$Rm,
982 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
983 IIC_VLD3lnu, "vld3", Dt,
984 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
985 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
987 let DecoderMethod = "DecodeVLD3LN";
990 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
991 let Inst{7-5} = lane{2-0};
993 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
994 let Inst{7-6} = lane{1-0};
996 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
997 let Inst{7} = lane{0};
1000 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1001 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1002 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1004 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
1005 let Inst{7-6} = lane{1-0};
1007 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
1008 let Inst{7} = lane{0};
1011 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
1012 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
1014 // VLD4LN : Vector Load (single 4-element structure to one lane)
1015 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1016 : NLdStLn<1, 0b10, op11_8, op7_4,
1017 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1018 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
1019 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
1020 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
1021 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
1023 let Inst{4} = Rn{4};
1024 let DecoderMethod = "DecodeVLD4LN";
1027 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
1028 let Inst{7-5} = lane{2-0};
1030 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
1031 let Inst{7-6} = lane{1-0};
1033 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
1034 let Inst{7} = lane{0};
1035 let Inst{5} = Rn{5};
1038 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1039 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1040 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1042 // ...with double-spaced registers:
1043 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
1044 let Inst{7-6} = lane{1-0};
1046 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
1047 let Inst{7} = lane{0};
1048 let Inst{5} = Rn{5};
1051 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
1052 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
1054 // ...with address register writeback:
1055 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1056 : NLdStLn<1, 0b10, op11_8, op7_4,
1057 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1058 (ins addrmode6:$Rn, am6offset:$Rm,
1059 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1060 IIC_VLD4lnu, "vld4", Dt,
1061 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
1062 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
1064 let Inst{4} = Rn{4};
1065 let DecoderMethod = "DecodeVLD4LN" ;
1068 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
1069 let Inst{7-5} = lane{2-0};
1071 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
1072 let Inst{7-6} = lane{1-0};
1074 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
1075 let Inst{7} = lane{0};
1076 let Inst{5} = Rn{5};
1079 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1080 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1081 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1083 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
1084 let Inst{7-6} = lane{1-0};
1086 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
1087 let Inst{7} = lane{0};
1088 let Inst{5} = Rn{5};
1091 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
1092 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
1094 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1096 // VLD1DUP : Vector Load (single element to all lanes)
1097 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
1098 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd),
1099 (ins addrmode6dup:$Rn),
1100 IIC_VLD1dup, "vld1", Dt, "$Vd, $Rn", "",
1101 [(set VecListOneDAllLanes:$Vd,
1102 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
1104 let Inst{4} = Rn{4};
1105 let DecoderMethod = "DecodeVLD1DupInstruction";
1107 class VLD1QDUPPseudo<ValueType Ty, PatFrag LoadOp> : VLDQPseudo<IIC_VLD1dup> {
1108 let Pattern = [(set QPR:$dst,
1109 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$addr)))))];
1112 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
1113 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;
1114 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;
1116 def VLD1DUPq8Pseudo : VLD1QDUPPseudo<v16i8, extloadi8>;
1117 def VLD1DUPq16Pseudo : VLD1QDUPPseudo<v8i16, extloadi16>;
1118 def VLD1DUPq32Pseudo : VLD1QDUPPseudo<v4i32, load>;
1120 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1121 (VLD1DUPd32 addrmode6:$addr)>;
1122 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1123 (VLD1DUPq32Pseudo addrmode6:$addr)>;
1125 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1127 class VLD1QDUP<bits<4> op7_4, string Dt>
1128 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListTwoDAllLanes:$Vd),
1129 (ins addrmode6dup:$Rn), IIC_VLD1dup,
1130 "vld1", Dt, "$Vd, $Rn", "", []> {
1132 let Inst{4} = Rn{4};
1133 let DecoderMethod = "DecodeVLD1DupInstruction";
1136 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8">;
1137 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16">;
1138 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32">;
1140 // ...with address register writeback:
1141 multiclass VLD1DUPWB<bits<4> op7_4, string Dt> {
1142 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1143 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1144 (ins addrmode6dup:$Rn), IIC_VLD1dupu,
1145 "vld1", Dt, "$Vd, $Rn!",
1146 "$Rn.addr = $wb", []> {
1147 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1148 let Inst{4} = Rn{4};
1149 let DecoderMethod = "DecodeVLD1DupInstruction";
1150 let AsmMatchConverter = "cvtVLDwbFixed";
1152 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1153 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1154 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1155 "vld1", Dt, "$Vd, $Rn, $Rm",
1156 "$Rn.addr = $wb", []> {
1157 let Inst{4} = Rn{4};
1158 let DecoderMethod = "DecodeVLD1DupInstruction";
1159 let AsmMatchConverter = "cvtVLDwbRegister";
1162 multiclass VLD1QDUPWB<bits<4> op7_4, string Dt> {
1163 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1164 (outs VecListTwoDAllLanes:$Vd, GPR:$wb),
1165 (ins addrmode6dup:$Rn), IIC_VLD1dupu,
1166 "vld1", Dt, "$Vd, $Rn!",
1167 "$Rn.addr = $wb", []> {
1168 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1169 let Inst{4} = Rn{4};
1170 let DecoderMethod = "DecodeVLD1DupInstruction";
1171 let AsmMatchConverter = "cvtVLDwbFixed";
1173 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1174 (outs VecListTwoDAllLanes:$Vd, GPR:$wb),
1175 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1176 "vld1", Dt, "$Vd, $Rn, $Rm",
1177 "$Rn.addr = $wb", []> {
1178 let Inst{4} = Rn{4};
1179 let DecoderMethod = "DecodeVLD1DupInstruction";
1180 let AsmMatchConverter = "cvtVLDwbRegister";
1184 defm VLD1DUPd8wb : VLD1DUPWB<{0,0,0,0}, "8">;
1185 defm VLD1DUPd16wb : VLD1DUPWB<{0,1,0,?}, "16">;
1186 defm VLD1DUPd32wb : VLD1DUPWB<{1,0,0,?}, "32">;
1188 defm VLD1DUPq8wb : VLD1QDUPWB<{0,0,1,0}, "8">;
1189 defm VLD1DUPq16wb : VLD1QDUPWB<{0,1,1,?}, "16">;
1190 defm VLD1DUPq32wb : VLD1QDUPWB<{1,0,1,?}, "32">;
1192 def VLD1DUPq8PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1dupu>;
1193 def VLD1DUPq16PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1dupu>;
1194 def VLD1DUPq32PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1dupu>;
1195 def VLD1DUPq8PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1dupu>;
1196 def VLD1DUPq16PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1dupu>;
1197 def VLD1DUPq32PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1dupu>;
1199 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
1200 class VLD2DUP<bits<4> op7_4, string Dt>
1201 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2),
1202 (ins addrmode6dup:$Rn), IIC_VLD2dup,
1203 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
1205 let Inst{4} = Rn{4};
1206 let DecoderMethod = "DecodeVLD2DupInstruction";
1209 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8">;
1210 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16">;
1211 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32">;
1213 def VLD2DUPd8Pseudo : VLDQPseudo<IIC_VLD2dup>;
1214 def VLD2DUPd16Pseudo : VLDQPseudo<IIC_VLD2dup>;
1215 def VLD2DUPd32Pseudo : VLDQPseudo<IIC_VLD2dup>;
1217 // ...with double-spaced registers (not used for codegen):
1218 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8">;
1219 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16">;
1220 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32">;
1222 // ...with address register writeback:
1223 class VLD2DUPWB<bits<4> op7_4, string Dt>
1224 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
1225 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD2dupu,
1226 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
1227 let Inst{4} = Rn{4};
1228 let DecoderMethod = "DecodeVLD2DupInstruction";
1231 def VLD2DUPd8_UPD : VLD2DUPWB<{0,0,0,0}, "8">;
1232 def VLD2DUPd16_UPD : VLD2DUPWB<{0,1,0,?}, "16">;
1233 def VLD2DUPd32_UPD : VLD2DUPWB<{1,0,0,?}, "32">;
1235 def VLD2DUPd8x2_UPD : VLD2DUPWB<{0,0,1,0}, "8">;
1236 def VLD2DUPd16x2_UPD : VLD2DUPWB<{0,1,1,?}, "16">;
1237 def VLD2DUPd32x2_UPD : VLD2DUPWB<{1,0,1,?}, "32">;
1239 def VLD2DUPd8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
1240 def VLD2DUPd16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
1241 def VLD2DUPd32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
1243 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
1244 class VLD3DUP<bits<4> op7_4, string Dt>
1245 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1246 (ins addrmode6dup:$Rn), IIC_VLD3dup,
1247 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
1250 let DecoderMethod = "DecodeVLD3DupInstruction";
1253 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
1254 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
1255 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
1257 def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1258 def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1259 def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1261 // ...with double-spaced registers (not used for codegen):
1262 def VLD3DUPd8x2 : VLD3DUP<{0,0,1,?}, "8">;
1263 def VLD3DUPd16x2 : VLD3DUP<{0,1,1,?}, "16">;
1264 def VLD3DUPd32x2 : VLD3DUP<{1,0,1,?}, "32">;
1266 // ...with address register writeback:
1267 class VLD3DUPWB<bits<4> op7_4, string Dt>
1268 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1269 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu,
1270 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
1271 "$Rn.addr = $wb", []> {
1273 let DecoderMethod = "DecodeVLD3DupInstruction";
1276 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;
1277 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">;
1278 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">;
1280 def VLD3DUPd8x2_UPD : VLD3DUPWB<{0,0,1,0}, "8">;
1281 def VLD3DUPd16x2_UPD : VLD3DUPWB<{0,1,1,?}, "16">;
1282 def VLD3DUPd32x2_UPD : VLD3DUPWB<{1,0,1,?}, "32">;
1284 def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1285 def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1286 def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1288 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1289 class VLD4DUP<bits<4> op7_4, string Dt>
1290 : NLdSt<1, 0b10, 0b1111, op7_4,
1291 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1292 (ins addrmode6dup:$Rn), IIC_VLD4dup,
1293 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
1295 let Inst{4} = Rn{4};
1296 let DecoderMethod = "DecodeVLD4DupInstruction";
1299 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1300 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1301 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1303 def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1304 def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1305 def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1307 // ...with double-spaced registers (not used for codegen):
1308 def VLD4DUPd8x2 : VLD4DUP<{0,0,1,?}, "8">;
1309 def VLD4DUPd16x2 : VLD4DUP<{0,1,1,?}, "16">;
1310 def VLD4DUPd32x2 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1312 // ...with address register writeback:
1313 class VLD4DUPWB<bits<4> op7_4, string Dt>
1314 : NLdSt<1, 0b10, 0b1111, op7_4,
1315 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1316 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
1317 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
1318 "$Rn.addr = $wb", []> {
1319 let Inst{4} = Rn{4};
1320 let DecoderMethod = "DecodeVLD4DupInstruction";
1323 def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">;
1324 def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">;
1325 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1327 def VLD4DUPd8x2_UPD : VLD4DUPWB<{0,0,1,0}, "8">;
1328 def VLD4DUPd16x2_UPD : VLD4DUPWB<{0,1,1,?}, "16">;
1329 def VLD4DUPd32x2_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1331 def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1332 def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1333 def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1335 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1337 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1339 // Classes for VST* pseudo-instructions with multi-register operands.
1340 // These are expanded to real instructions after register allocation.
1341 class VSTQPseudo<InstrItinClass itin>
1342 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1343 class VSTQWBPseudo<InstrItinClass itin>
1344 : PseudoNLdSt<(outs GPR:$wb),
1345 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1346 "$addr.addr = $wb">;
1347 class VSTQWBfixedPseudo<InstrItinClass itin>
1348 : PseudoNLdSt<(outs GPR:$wb),
1349 (ins addrmode6:$addr, QPR:$src), itin,
1350 "$addr.addr = $wb">;
1351 class VSTQWBregisterPseudo<InstrItinClass itin>
1352 : PseudoNLdSt<(outs GPR:$wb),
1353 (ins addrmode6:$addr, rGPR:$offset, QPR:$src), itin,
1354 "$addr.addr = $wb">;
1355 class VSTQQPseudo<InstrItinClass itin>
1356 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
1357 class VSTQQWBPseudo<InstrItinClass itin>
1358 : PseudoNLdSt<(outs GPR:$wb),
1359 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
1360 "$addr.addr = $wb">;
1361 class VSTQQQQPseudo<InstrItinClass itin>
1362 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src), itin, "">;
1363 class VSTQQQQWBPseudo<InstrItinClass itin>
1364 : PseudoNLdSt<(outs GPR:$wb),
1365 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
1366 "$addr.addr = $wb">;
1368 // VST1 : Vector Store (multiple single elements)
1369 class VST1D<bits<4> op7_4, string Dt>
1370 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, VecListOneD:$Vd),
1371 IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []> {
1373 let Inst{4} = Rn{4};
1374 let DecoderMethod = "DecodeVSTInstruction";
1376 class VST1Q<bits<4> op7_4, string Dt>
1377 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$Rn, VecListTwoD:$Vd),
1378 IIC_VST1x2, "vst1", Dt, "$Vd, $Rn", "", []> {
1380 let Inst{5-4} = Rn{5-4};
1381 let DecoderMethod = "DecodeVSTInstruction";
1384 def VST1d8 : VST1D<{0,0,0,?}, "8">;
1385 def VST1d16 : VST1D<{0,1,0,?}, "16">;
1386 def VST1d32 : VST1D<{1,0,0,?}, "32">;
1387 def VST1d64 : VST1D<{1,1,0,?}, "64">;
1389 def VST1q8 : VST1Q<{0,0,?,?}, "8">;
1390 def VST1q16 : VST1Q<{0,1,?,?}, "16">;
1391 def VST1q32 : VST1Q<{1,0,?,?}, "32">;
1392 def VST1q64 : VST1Q<{1,1,?,?}, "64">;
1394 def VST1q8Pseudo : VSTQPseudo<IIC_VST1x2>;
1395 def VST1q16Pseudo : VSTQPseudo<IIC_VST1x2>;
1396 def VST1q32Pseudo : VSTQPseudo<IIC_VST1x2>;
1397 def VST1q64Pseudo : VSTQPseudo<IIC_VST1x2>;
1399 // ...with address register writeback:
1400 multiclass VST1DWB<bits<4> op7_4, string Dt> {
1401 def _fixed : NLdSt<0,0b00, 0b0111,op7_4, (outs GPR:$wb),
1402 (ins addrmode6:$Rn, VecListOneD:$Vd), IIC_VLD1u,
1403 "vst1", Dt, "$Vd, $Rn!",
1404 "$Rn.addr = $wb", []> {
1405 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1406 let Inst{4} = Rn{4};
1407 let DecoderMethod = "DecodeVSTInstruction";
1408 let AsmMatchConverter = "cvtVSTwbFixed";
1410 def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb),
1411 (ins addrmode6:$Rn, rGPR:$Rm, VecListOneD:$Vd),
1413 "vst1", Dt, "$Vd, $Rn, $Rm",
1414 "$Rn.addr = $wb", []> {
1415 let Inst{4} = Rn{4};
1416 let DecoderMethod = "DecodeVSTInstruction";
1417 let AsmMatchConverter = "cvtVSTwbRegister";
1420 multiclass VST1QWB<bits<4> op7_4, string Dt> {
1421 def _fixed : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1422 (ins addrmode6:$Rn, VecListTwoD:$Vd), IIC_VLD1x2u,
1423 "vst1", Dt, "$Vd, $Rn!",
1424 "$Rn.addr = $wb", []> {
1425 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1426 let Inst{5-4} = Rn{5-4};
1427 let DecoderMethod = "DecodeVSTInstruction";
1428 let AsmMatchConverter = "cvtVSTwbFixed";
1430 def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1431 (ins addrmode6:$Rn, rGPR:$Rm, VecListTwoD:$Vd),
1433 "vst1", Dt, "$Vd, $Rn, $Rm",
1434 "$Rn.addr = $wb", []> {
1435 let Inst{5-4} = Rn{5-4};
1436 let DecoderMethod = "DecodeVSTInstruction";
1437 let AsmMatchConverter = "cvtVSTwbRegister";
1441 defm VST1d8wb : VST1DWB<{0,0,0,?}, "8">;
1442 defm VST1d16wb : VST1DWB<{0,1,0,?}, "16">;
1443 defm VST1d32wb : VST1DWB<{1,0,0,?}, "32">;
1444 defm VST1d64wb : VST1DWB<{1,1,0,?}, "64">;
1446 defm VST1q8wb : VST1QWB<{0,0,?,?}, "8">;
1447 defm VST1q16wb : VST1QWB<{0,1,?,?}, "16">;
1448 defm VST1q32wb : VST1QWB<{1,0,?,?}, "32">;
1449 defm VST1q64wb : VST1QWB<{1,1,?,?}, "64">;
1451 def VST1q8PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST1x2u>;
1452 def VST1q16PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST1x2u>;
1453 def VST1q32PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST1x2u>;
1454 def VST1q64PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST1x2u>;
1455 def VST1q8PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>;
1456 def VST1q16PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>;
1457 def VST1q32PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>;
1458 def VST1q64PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>;
1460 // ...with 3 registers
1461 class VST1D3<bits<4> op7_4, string Dt>
1462 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1463 (ins addrmode6:$Rn, VecListThreeD:$Vd),
1464 IIC_VST1x3, "vst1", Dt, "$Vd, $Rn", "", []> {
1466 let Inst{4} = Rn{4};
1467 let DecoderMethod = "DecodeVSTInstruction";
1469 multiclass VST1D3WB<bits<4> op7_4, string Dt> {
1470 def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1471 (ins addrmode6:$Rn, VecListThreeD:$Vd), IIC_VLD1x3u,
1472 "vst1", Dt, "$Vd, $Rn!",
1473 "$Rn.addr = $wb", []> {
1474 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1475 let Inst{5-4} = Rn{5-4};
1476 let DecoderMethod = "DecodeVSTInstruction";
1477 let AsmMatchConverter = "cvtVSTwbFixed";
1479 def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1480 (ins addrmode6:$Rn, rGPR:$Rm, VecListThreeD:$Vd),
1482 "vst1", Dt, "$Vd, $Rn, $Rm",
1483 "$Rn.addr = $wb", []> {
1484 let Inst{5-4} = Rn{5-4};
1485 let DecoderMethod = "DecodeVSTInstruction";
1486 let AsmMatchConverter = "cvtVSTwbRegister";
1490 def VST1d8T : VST1D3<{0,0,0,?}, "8">;
1491 def VST1d16T : VST1D3<{0,1,0,?}, "16">;
1492 def VST1d32T : VST1D3<{1,0,0,?}, "32">;
1493 def VST1d64T : VST1D3<{1,1,0,?}, "64">;
1495 defm VST1d8Twb : VST1D3WB<{0,0,0,?}, "8">;
1496 defm VST1d16Twb : VST1D3WB<{0,1,0,?}, "16">;
1497 defm VST1d32Twb : VST1D3WB<{1,0,0,?}, "32">;
1498 defm VST1d64Twb : VST1D3WB<{1,1,0,?}, "64">;
1500 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
1501 def VST1d64TPseudoWB_fixed : VSTQQWBPseudo<IIC_VST1x3u>;
1502 def VST1d64TPseudoWB_register : VSTQQWBPseudo<IIC_VST1x3u>;
1504 // ...with 4 registers
1505 class VST1D4<bits<4> op7_4, string Dt>
1506 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1507 (ins addrmode6:$Rn, VecListFourD:$Vd),
1508 IIC_VST1x4, "vst1", Dt, "$Vd, $Rn", "",
1511 let Inst{5-4} = Rn{5-4};
1512 let DecoderMethod = "DecodeVSTInstruction";
1514 multiclass VST1D4WB<bits<4> op7_4, string Dt> {
1515 def _fixed : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1516 (ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1x4u,
1517 "vst1", Dt, "$Vd, $Rn!",
1518 "$Rn.addr = $wb", []> {
1519 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1520 let Inst{5-4} = Rn{5-4};
1521 let DecoderMethod = "DecodeVSTInstruction";
1522 let AsmMatchConverter = "cvtVSTwbFixed";
1524 def _register : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1525 (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1527 "vst1", Dt, "$Vd, $Rn, $Rm",
1528 "$Rn.addr = $wb", []> {
1529 let Inst{5-4} = Rn{5-4};
1530 let DecoderMethod = "DecodeVSTInstruction";
1531 let AsmMatchConverter = "cvtVSTwbRegister";
1535 def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
1536 def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
1537 def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
1538 def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
1540 defm VST1d8Qwb : VST1D4WB<{0,0,?,?}, "8">;
1541 defm VST1d16Qwb : VST1D4WB<{0,1,?,?}, "16">;
1542 defm VST1d32Qwb : VST1D4WB<{1,0,?,?}, "32">;
1543 defm VST1d64Qwb : VST1D4WB<{1,1,?,?}, "64">;
1545 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
1546 def VST1d64QPseudoWB_fixed : VSTQQWBPseudo<IIC_VST1x4u>;
1547 def VST1d64QPseudoWB_register : VSTQQWBPseudo<IIC_VST1x4u>;
1549 // VST2 : Vector Store (multiple 2-element structures)
1550 class VST2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
1551 InstrItinClass itin>
1552 : NLdSt<0, 0b00, op11_8, op7_4, (outs), (ins addrmode6:$Rn, VdTy:$Vd),
1553 itin, "vst2", Dt, "$Vd, $Rn", "", []> {
1555 let Inst{5-4} = Rn{5-4};
1556 let DecoderMethod = "DecodeVSTInstruction";
1559 def VST2d8 : VST2<0b1000, {0,0,?,?}, "8", VecListTwoD, IIC_VST2>;
1560 def VST2d16 : VST2<0b1000, {0,1,?,?}, "16", VecListTwoD, IIC_VST2>;
1561 def VST2d32 : VST2<0b1000, {1,0,?,?}, "32", VecListTwoD, IIC_VST2>;
1563 def VST2q8 : VST2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VST2x2>;
1564 def VST2q16 : VST2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VST2x2>;
1565 def VST2q32 : VST2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VST2x2>;
1567 def VST2d8Pseudo : VSTQPseudo<IIC_VST2>;
1568 def VST2d16Pseudo : VSTQPseudo<IIC_VST2>;
1569 def VST2d32Pseudo : VSTQPseudo<IIC_VST2>;
1571 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
1572 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
1573 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
1575 // ...with address register writeback:
1576 multiclass VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt,
1577 RegisterOperand VdTy> {
1578 def _fixed : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1579 (ins addrmode6:$Rn, VdTy:$Vd), IIC_VLD1u,
1580 "vst2", Dt, "$Vd, $Rn!",
1581 "$Rn.addr = $wb", []> {
1582 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1583 let Inst{5-4} = Rn{5-4};
1584 let DecoderMethod = "DecodeVSTInstruction";
1585 let AsmMatchConverter = "cvtVSTwbFixed";
1587 def _register : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1588 (ins addrmode6:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u,
1589 "vst2", Dt, "$Vd, $Rn, $Rm",
1590 "$Rn.addr = $wb", []> {
1591 let Inst{5-4} = Rn{5-4};
1592 let DecoderMethod = "DecodeVSTInstruction";
1593 let AsmMatchConverter = "cvtVSTwbRegister";
1596 multiclass VST2QWB<bits<4> op7_4, string Dt> {
1597 def _fixed : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1598 (ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1u,
1599 "vst2", Dt, "$Vd, $Rn!",
1600 "$Rn.addr = $wb", []> {
1601 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1602 let Inst{5-4} = Rn{5-4};
1603 let DecoderMethod = "DecodeVSTInstruction";
1604 let AsmMatchConverter = "cvtVSTwbFixed";
1606 def _register : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1607 (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1609 "vst2", Dt, "$Vd, $Rn, $Rm",
1610 "$Rn.addr = $wb", []> {
1611 let Inst{5-4} = Rn{5-4};
1612 let DecoderMethod = "DecodeVSTInstruction";
1613 let AsmMatchConverter = "cvtVSTwbRegister";
1617 defm VST2d8wb : VST2DWB<0b1000, {0,0,?,?}, "8", VecListTwoD>;
1618 defm VST2d16wb : VST2DWB<0b1000, {0,1,?,?}, "16", VecListTwoD>;
1619 defm VST2d32wb : VST2DWB<0b1000, {1,0,?,?}, "32", VecListTwoD>;
1621 defm VST2q8wb : VST2QWB<{0,0,?,?}, "8">;
1622 defm VST2q16wb : VST2QWB<{0,1,?,?}, "16">;
1623 defm VST2q32wb : VST2QWB<{1,0,?,?}, "32">;
1625 def VST2d8PseudoWB_fixed : VSTQWBPseudo<IIC_VST2u>;
1626 def VST2d16PseudoWB_fixed : VSTQWBPseudo<IIC_VST2u>;
1627 def VST2d32PseudoWB_fixed : VSTQWBPseudo<IIC_VST2u>;
1628 def VST2d8PseudoWB_register : VSTQWBPseudo<IIC_VST2u>;
1629 def VST2d16PseudoWB_register : VSTQWBPseudo<IIC_VST2u>;
1630 def VST2d32PseudoWB_register : VSTQWBPseudo<IIC_VST2u>;
1632 def VST2q8PseudoWB_fixed : VSTQQWBPseudo<IIC_VST2x2u>;
1633 def VST2q16PseudoWB_fixed : VSTQQWBPseudo<IIC_VST2x2u>;
1634 def VST2q32PseudoWB_fixed : VSTQQWBPseudo<IIC_VST2x2u>;
1635 def VST2q8PseudoWB_register : VSTQQWBPseudo<IIC_VST2x2u>;
1636 def VST2q16PseudoWB_register : VSTQQWBPseudo<IIC_VST2x2u>;
1637 def VST2q32PseudoWB_register : VSTQQWBPseudo<IIC_VST2x2u>;
1639 // ...with double-spaced registers
1640 def VST2b8 : VST2<0b1001, {0,0,?,?}, "8", VecListTwoQ, IIC_VST2>;
1641 def VST2b16 : VST2<0b1001, {0,1,?,?}, "16", VecListTwoQ, IIC_VST2>;
1642 def VST2b32 : VST2<0b1001, {1,0,?,?}, "32", VecListTwoQ, IIC_VST2>;
1643 defm VST2b8wb : VST2DWB<0b1001, {0,0,?,?}, "8", VecListTwoQ>;
1644 defm VST2b16wb : VST2DWB<0b1001, {0,1,?,?}, "16", VecListTwoQ>;
1645 defm VST2b32wb : VST2DWB<0b1001, {1,0,?,?}, "32", VecListTwoQ>;
1647 // VST3 : Vector Store (multiple 3-element structures)
1648 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1649 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1650 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1651 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1653 let Inst{4} = Rn{4};
1654 let DecoderMethod = "DecodeVSTInstruction";
1657 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1658 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1659 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
1661 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1662 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1663 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
1665 // ...with address register writeback:
1666 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1667 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1668 (ins addrmode6:$Rn, am6offset:$Rm,
1669 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1670 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1671 "$Rn.addr = $wb", []> {
1672 let Inst{4} = Rn{4};
1673 let DecoderMethod = "DecodeVSTInstruction";
1676 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1677 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1678 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
1680 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1681 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1682 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1684 // ...with double-spaced registers:
1685 def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1686 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1687 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1688 def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1689 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1690 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
1692 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1693 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1694 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1696 // ...alternate versions to be allocated odd register numbers:
1697 def VST3q8oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1698 def VST3q16oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1699 def VST3q32oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1701 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1702 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1703 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1705 // VST4 : Vector Store (multiple 4-element structures)
1706 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1707 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1708 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1709 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1712 let Inst{5-4} = Rn{5-4};
1713 let DecoderMethod = "DecodeVSTInstruction";
1716 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1717 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1718 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
1720 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1721 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1722 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
1724 // ...with address register writeback:
1725 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1726 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1727 (ins addrmode6:$Rn, am6offset:$Rm,
1728 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1729 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1730 "$Rn.addr = $wb", []> {
1731 let Inst{5-4} = Rn{5-4};
1732 let DecoderMethod = "DecodeVSTInstruction";
1735 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
1736 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
1737 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
1739 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1740 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1741 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1743 // ...with double-spaced registers:
1744 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
1745 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
1746 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
1747 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
1748 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
1749 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
1751 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1752 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1753 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1755 // ...alternate versions to be allocated odd register numbers:
1756 def VST4q8oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1757 def VST4q16oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1758 def VST4q32oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1760 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1761 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1762 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1764 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1766 // Classes for VST*LN pseudo-instructions with multi-register operands.
1767 // These are expanded to real instructions after register allocation.
1768 class VSTQLNPseudo<InstrItinClass itin>
1769 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1771 class VSTQLNWBPseudo<InstrItinClass itin>
1772 : PseudoNLdSt<(outs GPR:$wb),
1773 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1774 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1775 class VSTQQLNPseudo<InstrItinClass itin>
1776 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1778 class VSTQQLNWBPseudo<InstrItinClass itin>
1779 : PseudoNLdSt<(outs GPR:$wb),
1780 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1781 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1782 class VSTQQQQLNPseudo<InstrItinClass itin>
1783 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1785 class VSTQQQQLNWBPseudo<InstrItinClass itin>
1786 : PseudoNLdSt<(outs GPR:$wb),
1787 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1788 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1790 // VST1LN : Vector Store (single element from one lane)
1791 class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1792 PatFrag StoreOp, SDNode ExtractOp>
1793 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1794 (ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane),
1795 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1796 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6:$Rn)]> {
1798 let DecoderMethod = "DecodeVST1LN";
1800 class VST1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1801 PatFrag StoreOp, SDNode ExtractOp>
1802 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1803 (ins addrmode6oneL32:$Rn, DPR:$Vd, nohash_imm:$lane),
1804 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1805 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6oneL32:$Rn)]>{
1807 let DecoderMethod = "DecodeVST1LN";
1809 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1810 : VSTQLNPseudo<IIC_VST1ln> {
1811 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1815 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
1817 let Inst{7-5} = lane{2-0};
1819 def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
1821 let Inst{7-6} = lane{1-0};
1822 let Inst{4} = Rn{5};
1825 def VST1LNd32 : VST1LN32<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt> {
1826 let Inst{7} = lane{0};
1827 let Inst{5-4} = Rn{5-4};
1830 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
1831 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
1832 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
1834 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
1835 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1836 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
1837 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1839 // ...with address register writeback:
1840 class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1841 PatFrag StoreOp, SDNode ExtractOp>
1842 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1843 (ins addrmode6:$Rn, am6offset:$Rm,
1844 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
1845 "\\{$Vd[$lane]\\}, $Rn$Rm",
1847 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
1848 addrmode6:$Rn, am6offset:$Rm))]> {
1849 let DecoderMethod = "DecodeVST1LN";
1851 class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1852 : VSTQLNWBPseudo<IIC_VST1lnu> {
1853 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1854 addrmode6:$addr, am6offset:$offset))];
1857 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8,
1859 let Inst{7-5} = lane{2-0};
1861 def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16", v4i16, post_truncsti16,
1863 let Inst{7-6} = lane{1-0};
1864 let Inst{4} = Rn{5};
1866 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32", v2i32, post_store,
1868 let Inst{7} = lane{0};
1869 let Inst{5-4} = Rn{5-4};
1872 def VST1LNq8Pseudo_UPD : VST1QLNWBPseudo<v16i8, post_truncsti8, NEONvgetlaneu>;
1873 def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,NEONvgetlaneu>;
1874 def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
1876 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1878 // VST2LN : Vector Store (single 2-element structure from one lane)
1879 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1880 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1881 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
1882 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
1885 let Inst{4} = Rn{4};
1886 let DecoderMethod = "DecodeVST2LN";
1889 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
1890 let Inst{7-5} = lane{2-0};
1892 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
1893 let Inst{7-6} = lane{1-0};
1895 def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
1896 let Inst{7} = lane{0};
1899 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1900 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1901 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1903 // ...with double-spaced registers:
1904 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
1905 let Inst{7-6} = lane{1-0};
1906 let Inst{4} = Rn{4};
1908 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
1909 let Inst{7} = lane{0};
1910 let Inst{4} = Rn{4};
1913 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1914 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1916 // ...with address register writeback:
1917 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1918 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1919 (ins addrmode6:$Rn, am6offset:$Rm,
1920 DPR:$Vd, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
1921 "\\{$Vd[$lane], $src2[$lane]\\}, $Rn$Rm",
1922 "$Rn.addr = $wb", []> {
1923 let Inst{4} = Rn{4};
1924 let DecoderMethod = "DecodeVST2LN";
1927 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
1928 let Inst{7-5} = lane{2-0};
1930 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
1931 let Inst{7-6} = lane{1-0};
1933 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
1934 let Inst{7} = lane{0};
1937 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1938 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1939 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1941 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
1942 let Inst{7-6} = lane{1-0};
1944 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
1945 let Inst{7} = lane{0};
1948 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1949 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1951 // VST3LN : Vector Store (single 3-element structure from one lane)
1952 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1953 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1954 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
1955 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
1956 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
1958 let DecoderMethod = "DecodeVST3LN";
1961 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
1962 let Inst{7-5} = lane{2-0};
1964 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
1965 let Inst{7-6} = lane{1-0};
1967 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
1968 let Inst{7} = lane{0};
1971 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1972 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1973 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1975 // ...with double-spaced registers:
1976 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
1977 let Inst{7-6} = lane{1-0};
1979 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
1980 let Inst{7} = lane{0};
1983 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1984 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1986 // ...with address register writeback:
1987 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1988 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1989 (ins addrmode6:$Rn, am6offset:$Rm,
1990 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1991 IIC_VST3lnu, "vst3", Dt,
1992 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
1993 "$Rn.addr = $wb", []> {
1994 let DecoderMethod = "DecodeVST3LN";
1997 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
1998 let Inst{7-5} = lane{2-0};
2000 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
2001 let Inst{7-6} = lane{1-0};
2003 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
2004 let Inst{7} = lane{0};
2007 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2008 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2009 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2011 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
2012 let Inst{7-6} = lane{1-0};
2014 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
2015 let Inst{7} = lane{0};
2018 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
2019 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
2021 // VST4LN : Vector Store (single 4-element structure from one lane)
2022 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2023 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2024 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
2025 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
2026 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
2029 let Inst{4} = Rn{4};
2030 let DecoderMethod = "DecodeVST4LN";
2033 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
2034 let Inst{7-5} = lane{2-0};
2036 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
2037 let Inst{7-6} = lane{1-0};
2039 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
2040 let Inst{7} = lane{0};
2041 let Inst{5} = Rn{5};
2044 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2045 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2046 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2048 // ...with double-spaced registers:
2049 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
2050 let Inst{7-6} = lane{1-0};
2052 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
2053 let Inst{7} = lane{0};
2054 let Inst{5} = Rn{5};
2057 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
2058 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
2060 // ...with address register writeback:
2061 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2062 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2063 (ins addrmode6:$Rn, am6offset:$Rm,
2064 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
2065 IIC_VST4lnu, "vst4", Dt,
2066 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
2067 "$Rn.addr = $wb", []> {
2068 let Inst{4} = Rn{4};
2069 let DecoderMethod = "DecodeVST4LN";
2072 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
2073 let Inst{7-5} = lane{2-0};
2075 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
2076 let Inst{7-6} = lane{1-0};
2078 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
2079 let Inst{7} = lane{0};
2080 let Inst{5} = Rn{5};
2083 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2084 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2085 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2087 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
2088 let Inst{7-6} = lane{1-0};
2090 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
2091 let Inst{7} = lane{0};
2092 let Inst{5} = Rn{5};
2095 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
2096 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
2098 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2101 //===----------------------------------------------------------------------===//
2102 // NEON pattern fragments
2103 //===----------------------------------------------------------------------===//
2105 // Extract D sub-registers of Q registers.
2106 def DSubReg_i8_reg : SDNodeXForm<imm, [{
2107 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2108 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
2110 def DSubReg_i16_reg : SDNodeXForm<imm, [{
2111 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2112 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
2114 def DSubReg_i32_reg : SDNodeXForm<imm, [{
2115 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2116 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
2118 def DSubReg_f64_reg : SDNodeXForm<imm, [{
2119 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2120 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
2123 // Extract S sub-registers of Q/D registers.
2124 def SSubReg_f32_reg : SDNodeXForm<imm, [{
2125 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
2126 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
2129 // Translate lane numbers from Q registers to D subregs.
2130 def SubReg_i8_lane : SDNodeXForm<imm, [{
2131 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
2133 def SubReg_i16_lane : SDNodeXForm<imm, [{
2134 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
2136 def SubReg_i32_lane : SDNodeXForm<imm, [{
2137 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
2140 //===----------------------------------------------------------------------===//
2141 // Instruction Classes
2142 //===----------------------------------------------------------------------===//
2144 // Basic 2-register operations: double- and quad-register.
2145 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2146 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
2147 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2148 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2149 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
2150 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
2151 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2152 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
2153 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2154 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2155 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
2156 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
2158 // Basic 2-register intrinsics, both double- and quad-register.
2159 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2160 bits<2> op17_16, bits<5> op11_7, bit op4,
2161 InstrItinClass itin, string OpcodeStr, string Dt,
2162 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2163 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2164 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2165 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2166 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2167 bits<2> op17_16, bits<5> op11_7, bit op4,
2168 InstrItinClass itin, string OpcodeStr, string Dt,
2169 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2170 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2171 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2172 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2174 // Narrow 2-register operations.
2175 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2176 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2177 InstrItinClass itin, string OpcodeStr, string Dt,
2178 ValueType TyD, ValueType TyQ, SDNode OpNode>
2179 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2180 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2181 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
2183 // Narrow 2-register intrinsics.
2184 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2185 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2186 InstrItinClass itin, string OpcodeStr, string Dt,
2187 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
2188 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2189 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2190 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
2192 // Long 2-register operations (currently only used for VMOVL).
2193 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2194 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2195 InstrItinClass itin, string OpcodeStr, string Dt,
2196 ValueType TyQ, ValueType TyD, SDNode OpNode>
2197 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2198 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2199 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
2201 // Long 2-register intrinsics.
2202 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2203 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2204 InstrItinClass itin, string OpcodeStr, string Dt,
2205 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
2206 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2207 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2208 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
2210 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
2211 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
2212 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
2213 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
2214 OpcodeStr, Dt, "$Vd, $Vm",
2215 "$src1 = $Vd, $src2 = $Vm", []>;
2216 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
2217 InstrItinClass itin, string OpcodeStr, string Dt>
2218 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
2219 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
2220 "$src1 = $Vd, $src2 = $Vm", []>;
2222 // Basic 3-register operations: double- and quad-register.
2223 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2224 InstrItinClass itin, string OpcodeStr, string Dt,
2225 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2226 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2227 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2228 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2229 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2230 let isCommutable = Commutable;
2232 // Same as N3VD but no data type.
2233 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2234 InstrItinClass itin, string OpcodeStr,
2235 ValueType ResTy, ValueType OpTy,
2236 SDNode OpNode, bit Commutable>
2237 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
2238 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2239 OpcodeStr, "$Vd, $Vn, $Vm", "",
2240 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
2241 let isCommutable = Commutable;
2244 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
2245 InstrItinClass itin, string OpcodeStr, string Dt,
2246 ValueType Ty, SDNode ShOp>
2247 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2248 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2249 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2251 (Ty (ShOp (Ty DPR:$Vn),
2252 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
2253 let isCommutable = 0;
2255 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
2256 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2257 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2258 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2259 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane","",
2261 (Ty (ShOp (Ty DPR:$Vn),
2262 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2263 let isCommutable = 0;
2266 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2267 InstrItinClass itin, string OpcodeStr, string Dt,
2268 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2269 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2270 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2271 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2272 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2273 let isCommutable = Commutable;
2275 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2276 InstrItinClass itin, string OpcodeStr,
2277 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2278 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
2279 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2280 OpcodeStr, "$Vd, $Vn, $Vm", "",
2281 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
2282 let isCommutable = Commutable;
2284 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
2285 InstrItinClass itin, string OpcodeStr, string Dt,
2286 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2287 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2288 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2289 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2290 [(set (ResTy QPR:$Vd),
2291 (ResTy (ShOp (ResTy QPR:$Vn),
2292 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2294 let isCommutable = 0;
2296 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
2297 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2298 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2299 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2300 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane", "",
2301 [(set (ResTy QPR:$Vd),
2302 (ResTy (ShOp (ResTy QPR:$Vn),
2303 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2305 let isCommutable = 0;
2308 // Basic 3-register intrinsics, both double- and quad-register.
2309 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2310 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2311 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
2312 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2313 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
2314 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2315 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2316 let isCommutable = Commutable;
2318 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2319 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
2320 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2321 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2322 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2324 (Ty (IntOp (Ty DPR:$Vn),
2325 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2327 let isCommutable = 0;
2329 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2330 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
2331 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2332 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2333 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2335 (Ty (IntOp (Ty DPR:$Vn),
2336 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2337 let isCommutable = 0;
2339 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2340 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2341 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2342 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2343 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
2344 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2345 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
2346 let isCommutable = 0;
2349 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2350 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2351 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
2352 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2353 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
2354 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2355 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2356 let isCommutable = Commutable;
2358 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2359 string OpcodeStr, string Dt,
2360 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2361 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2362 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2363 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2364 [(set (ResTy QPR:$Vd),
2365 (ResTy (IntOp (ResTy QPR:$Vn),
2366 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2368 let isCommutable = 0;
2370 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2371 string OpcodeStr, string Dt,
2372 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2373 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2374 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2375 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2376 [(set (ResTy QPR:$Vd),
2377 (ResTy (IntOp (ResTy QPR:$Vn),
2378 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2380 let isCommutable = 0;
2382 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2383 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2384 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2385 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2386 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
2387 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2388 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
2389 let isCommutable = 0;
2392 // Multiply-Add/Sub operations: double- and quad-register.
2393 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2394 InstrItinClass itin, string OpcodeStr, string Dt,
2395 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode>
2396 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2397 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2398 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2399 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2400 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
2402 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2403 string OpcodeStr, string Dt,
2404 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
2405 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2407 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2409 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2411 (Ty (ShOp (Ty DPR:$src1),
2413 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2415 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2416 string OpcodeStr, string Dt,
2417 ValueType Ty, SDNode MulOp, SDNode ShOp>
2418 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2420 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2422 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2424 (Ty (ShOp (Ty DPR:$src1),
2426 (Ty (NEONvduplane (Ty DPR_8:$Vm),
2429 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2430 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
2431 SDPatternOperator MulOp, SDPatternOperator OpNode>
2432 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2433 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2434 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2435 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2436 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
2437 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2438 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2439 SDPatternOperator MulOp, SDPatternOperator ShOp>
2440 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2442 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2444 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2445 [(set (ResTy QPR:$Vd),
2446 (ResTy (ShOp (ResTy QPR:$src1),
2447 (ResTy (MulOp QPR:$Vn,
2448 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2450 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2451 string OpcodeStr, string Dt,
2452 ValueType ResTy, ValueType OpTy,
2453 SDNode MulOp, SDNode ShOp>
2454 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2456 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2458 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2459 [(set (ResTy QPR:$Vd),
2460 (ResTy (ShOp (ResTy QPR:$src1),
2461 (ResTy (MulOp QPR:$Vn,
2462 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2465 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
2466 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2467 InstrItinClass itin, string OpcodeStr, string Dt,
2468 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2469 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2470 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2471 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2472 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2473 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
2474 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2475 InstrItinClass itin, string OpcodeStr, string Dt,
2476 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2477 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2478 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2479 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2480 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2481 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2483 // Neon 3-argument intrinsics, both double- and quad-register.
2484 // The destination register is also used as the first source operand register.
2485 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2486 InstrItinClass itin, string OpcodeStr, string Dt,
2487 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2488 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2489 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2490 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2491 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2492 (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2493 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2494 InstrItinClass itin, string OpcodeStr, string Dt,
2495 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2496 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2497 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2498 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2499 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2500 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2502 // Long Multiply-Add/Sub operations.
2503 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2504 InstrItinClass itin, string OpcodeStr, string Dt,
2505 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2506 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2507 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2508 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2509 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2510 (TyQ (MulOp (TyD DPR:$Vn),
2511 (TyD DPR:$Vm)))))]>;
2512 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2513 InstrItinClass itin, string OpcodeStr, string Dt,
2514 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2515 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2516 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2518 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2520 (OpNode (TyQ QPR:$src1),
2521 (TyQ (MulOp (TyD DPR:$Vn),
2522 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),
2524 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2525 InstrItinClass itin, string OpcodeStr, string Dt,
2526 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2527 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2528 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2530 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2532 (OpNode (TyQ QPR:$src1),
2533 (TyQ (MulOp (TyD DPR:$Vn),
2534 (TyD (NEONvduplane (TyD DPR_8:$Vm),
2537 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
2538 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2539 InstrItinClass itin, string OpcodeStr, string Dt,
2540 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2542 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2543 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2544 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2545 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2546 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2547 (TyD DPR:$Vm)))))))]>;
2549 // Neon Long 3-argument intrinsic. The destination register is
2550 // a quad-register and is also used as the first source operand register.
2551 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2552 InstrItinClass itin, string OpcodeStr, string Dt,
2553 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
2554 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2555 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2556 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2558 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2559 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2560 string OpcodeStr, string Dt,
2561 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2562 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2564 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2566 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2567 [(set (ResTy QPR:$Vd),
2568 (ResTy (IntOp (ResTy QPR:$src1),
2570 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2572 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2573 InstrItinClass itin, string OpcodeStr, string Dt,
2574 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2575 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2577 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2579 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2580 [(set (ResTy QPR:$Vd),
2581 (ResTy (IntOp (ResTy QPR:$src1),
2583 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2586 // Narrowing 3-register intrinsics.
2587 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2588 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
2589 Intrinsic IntOp, bit Commutable>
2590 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2591 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2592 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2593 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2594 let isCommutable = Commutable;
2597 // Long 3-register operations.
2598 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2599 InstrItinClass itin, string OpcodeStr, string Dt,
2600 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
2601 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2602 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2603 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2604 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2605 let isCommutable = Commutable;
2607 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2608 InstrItinClass itin, string OpcodeStr, string Dt,
2609 ValueType TyQ, ValueType TyD, SDNode OpNode>
2610 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2611 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2612 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2614 (TyQ (OpNode (TyD DPR:$Vn),
2615 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
2616 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2617 InstrItinClass itin, string OpcodeStr, string Dt,
2618 ValueType TyQ, ValueType TyD, SDNode OpNode>
2619 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2620 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2621 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2623 (TyQ (OpNode (TyD DPR:$Vn),
2624 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
2626 // Long 3-register operations with explicitly extended operands.
2627 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2628 InstrItinClass itin, string OpcodeStr, string Dt,
2629 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
2631 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2632 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2633 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2634 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
2635 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2636 let isCommutable = Commutable;
2639 // Long 3-register intrinsics with explicit extend (VABDL).
2640 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2641 InstrItinClass itin, string OpcodeStr, string Dt,
2642 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2644 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2645 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2646 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2647 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2648 (TyD DPR:$Vm))))))]> {
2649 let isCommutable = Commutable;
2652 // Long 3-register intrinsics.
2653 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2654 InstrItinClass itin, string OpcodeStr, string Dt,
2655 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
2656 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2657 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2658 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2659 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2660 let isCommutable = Commutable;
2662 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2663 string OpcodeStr, string Dt,
2664 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2665 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2666 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2667 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2668 [(set (ResTy QPR:$Vd),
2669 (ResTy (IntOp (OpTy DPR:$Vn),
2670 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2672 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2673 InstrItinClass itin, string OpcodeStr, string Dt,
2674 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2675 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2676 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2677 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2678 [(set (ResTy QPR:$Vd),
2679 (ResTy (IntOp (OpTy DPR:$Vn),
2680 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2683 // Wide 3-register operations.
2684 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2685 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
2686 SDNode OpNode, SDNode ExtOp, bit Commutable>
2687 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2688 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
2689 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2690 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
2691 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2692 let isCommutable = Commutable;
2695 // Pairwise long 2-register intrinsics, both double- and quad-register.
2696 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2697 bits<2> op17_16, bits<5> op11_7, bit op4,
2698 string OpcodeStr, string Dt,
2699 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2700 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2701 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2702 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2703 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2704 bits<2> op17_16, bits<5> op11_7, bit op4,
2705 string OpcodeStr, string Dt,
2706 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2707 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2708 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2709 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2711 // Pairwise long 2-register accumulate intrinsics,
2712 // both double- and quad-register.
2713 // The destination register is also used as the first source operand register.
2714 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2715 bits<2> op17_16, bits<5> op11_7, bit op4,
2716 string OpcodeStr, string Dt,
2717 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2718 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
2719 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
2720 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2721 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
2722 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2723 bits<2> op17_16, bits<5> op11_7, bit op4,
2724 string OpcodeStr, string Dt,
2725 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2726 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
2727 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
2728 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2729 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
2731 // Shift by immediate,
2732 // both double- and quad-register.
2733 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2734 Format f, InstrItinClass itin, Operand ImmTy,
2735 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2736 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2737 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
2738 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2739 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
2740 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2741 Format f, InstrItinClass itin, Operand ImmTy,
2742 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2743 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2744 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
2745 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2746 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
2748 // Long shift by immediate.
2749 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2750 string OpcodeStr, string Dt,
2751 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode>
2752 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2753 (outs QPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), N2RegVShLFrm,
2754 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2755 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm),
2756 (i32 imm:$SIMM))))]>;
2758 // Narrow shift by immediate.
2759 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2760 InstrItinClass itin, string OpcodeStr, string Dt,
2761 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode>
2762 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2763 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
2764 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2765 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
2766 (i32 imm:$SIMM))))]>;
2768 // Shift right by immediate and accumulate,
2769 // both double- and quad-register.
2770 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2771 Operand ImmTy, string OpcodeStr, string Dt,
2772 ValueType Ty, SDNode ShOp>
2773 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2774 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2775 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2776 [(set DPR:$Vd, (Ty (add DPR:$src1,
2777 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
2778 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2779 Operand ImmTy, string OpcodeStr, string Dt,
2780 ValueType Ty, SDNode ShOp>
2781 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2782 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2783 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2784 [(set QPR:$Vd, (Ty (add QPR:$src1,
2785 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
2787 // Shift by immediate and insert,
2788 // both double- and quad-register.
2789 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2790 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2791 ValueType Ty,SDNode ShOp>
2792 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2793 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiD,
2794 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2795 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
2796 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2797 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2798 ValueType Ty,SDNode ShOp>
2799 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2800 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiQ,
2801 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2802 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
2804 // Convert, with fractional bits immediate,
2805 // both double- and quad-register.
2806 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2807 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2809 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2810 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2811 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2812 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
2813 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2814 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2816 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2817 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2818 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2819 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
2821 //===----------------------------------------------------------------------===//
2823 //===----------------------------------------------------------------------===//
2825 // Abbreviations used in multiclass suffixes:
2826 // Q = quarter int (8 bit) elements
2827 // H = half int (16 bit) elements
2828 // S = single int (32 bit) elements
2829 // D = double int (64 bit) elements
2831 // Neon 2-register vector operations and intrinsics.
2833 // Neon 2-register comparisons.
2834 // source operand element sizes of 8, 16 and 32 bits:
2835 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2836 bits<5> op11_7, bit op4, string opc, string Dt,
2837 string asm, SDNode OpNode> {
2838 // 64-bit vector types.
2839 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
2840 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2841 opc, !strconcat(Dt, "8"), asm, "",
2842 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
2843 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
2844 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2845 opc, !strconcat(Dt, "16"), asm, "",
2846 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>;
2847 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2848 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2849 opc, !strconcat(Dt, "32"), asm, "",
2850 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>;
2851 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2852 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2853 opc, "f32", asm, "",
2854 [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> {
2855 let Inst{10} = 1; // overwrite F = 1
2858 // 128-bit vector types.
2859 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
2860 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2861 opc, !strconcat(Dt, "8"), asm, "",
2862 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
2863 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
2864 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2865 opc, !strconcat(Dt, "16"), asm, "",
2866 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
2867 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2868 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2869 opc, !strconcat(Dt, "32"), asm, "",
2870 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
2871 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2872 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2873 opc, "f32", asm, "",
2874 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
2875 let Inst{10} = 1; // overwrite F = 1
2880 // Neon 2-register vector intrinsics,
2881 // element sizes of 8, 16 and 32 bits:
2882 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2883 bits<5> op11_7, bit op4,
2884 InstrItinClass itinD, InstrItinClass itinQ,
2885 string OpcodeStr, string Dt, Intrinsic IntOp> {
2886 // 64-bit vector types.
2887 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2888 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2889 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2890 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
2891 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2892 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
2894 // 128-bit vector types.
2895 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2896 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
2897 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2898 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
2899 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2900 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
2904 // Neon Narrowing 2-register vector operations,
2905 // source operand element sizes of 16, 32 and 64 bits:
2906 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2907 bits<5> op11_7, bit op6, bit op4,
2908 InstrItinClass itin, string OpcodeStr, string Dt,
2910 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2911 itin, OpcodeStr, !strconcat(Dt, "16"),
2912 v8i8, v8i16, OpNode>;
2913 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2914 itin, OpcodeStr, !strconcat(Dt, "32"),
2915 v4i16, v4i32, OpNode>;
2916 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2917 itin, OpcodeStr, !strconcat(Dt, "64"),
2918 v2i32, v2i64, OpNode>;
2921 // Neon Narrowing 2-register vector intrinsics,
2922 // source operand element sizes of 16, 32 and 64 bits:
2923 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2924 bits<5> op11_7, bit op6, bit op4,
2925 InstrItinClass itin, string OpcodeStr, string Dt,
2927 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2928 itin, OpcodeStr, !strconcat(Dt, "16"),
2929 v8i8, v8i16, IntOp>;
2930 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2931 itin, OpcodeStr, !strconcat(Dt, "32"),
2932 v4i16, v4i32, IntOp>;
2933 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2934 itin, OpcodeStr, !strconcat(Dt, "64"),
2935 v2i32, v2i64, IntOp>;
2939 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
2940 // source operand element sizes of 16, 32 and 64 bits:
2941 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
2942 string OpcodeStr, string Dt, SDNode OpNode> {
2943 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2944 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
2945 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2946 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2947 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2948 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2952 // Neon 3-register vector operations.
2954 // First with only element sizes of 8, 16 and 32 bits:
2955 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2956 InstrItinClass itinD16, InstrItinClass itinD32,
2957 InstrItinClass itinQ16, InstrItinClass itinQ32,
2958 string OpcodeStr, string Dt,
2959 SDNode OpNode, bit Commutable = 0> {
2960 // 64-bit vector types.
2961 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
2962 OpcodeStr, !strconcat(Dt, "8"),
2963 v8i8, v8i8, OpNode, Commutable>;
2964 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
2965 OpcodeStr, !strconcat(Dt, "16"),
2966 v4i16, v4i16, OpNode, Commutable>;
2967 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
2968 OpcodeStr, !strconcat(Dt, "32"),
2969 v2i32, v2i32, OpNode, Commutable>;
2971 // 128-bit vector types.
2972 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
2973 OpcodeStr, !strconcat(Dt, "8"),
2974 v16i8, v16i8, OpNode, Commutable>;
2975 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
2976 OpcodeStr, !strconcat(Dt, "16"),
2977 v8i16, v8i16, OpNode, Commutable>;
2978 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
2979 OpcodeStr, !strconcat(Dt, "32"),
2980 v4i32, v4i32, OpNode, Commutable>;
2983 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, SDNode ShOp> {
2984 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, "i16", v4i16, ShOp>;
2985 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, "i32", v2i32, ShOp>;
2986 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, "i16", v8i16, v4i16, ShOp>;
2987 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, "i32",
2988 v4i32, v2i32, ShOp>;
2991 // ....then also with element size 64 bits:
2992 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2993 InstrItinClass itinD, InstrItinClass itinQ,
2994 string OpcodeStr, string Dt,
2995 SDNode OpNode, bit Commutable = 0>
2996 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
2997 OpcodeStr, Dt, OpNode, Commutable> {
2998 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
2999 OpcodeStr, !strconcat(Dt, "64"),
3000 v1i64, v1i64, OpNode, Commutable>;
3001 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
3002 OpcodeStr, !strconcat(Dt, "64"),
3003 v2i64, v2i64, OpNode, Commutable>;
3007 // Neon 3-register vector intrinsics.
3009 // First with only element sizes of 16 and 32 bits:
3010 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3011 InstrItinClass itinD16, InstrItinClass itinD32,
3012 InstrItinClass itinQ16, InstrItinClass itinQ32,
3013 string OpcodeStr, string Dt,
3014 Intrinsic IntOp, bit Commutable = 0> {
3015 // 64-bit vector types.
3016 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
3017 OpcodeStr, !strconcat(Dt, "16"),
3018 v4i16, v4i16, IntOp, Commutable>;
3019 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
3020 OpcodeStr, !strconcat(Dt, "32"),
3021 v2i32, v2i32, IntOp, Commutable>;
3023 // 128-bit vector types.
3024 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3025 OpcodeStr, !strconcat(Dt, "16"),
3026 v8i16, v8i16, IntOp, Commutable>;
3027 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3028 OpcodeStr, !strconcat(Dt, "32"),
3029 v4i32, v4i32, IntOp, Commutable>;
3031 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3032 InstrItinClass itinD16, InstrItinClass itinD32,
3033 InstrItinClass itinQ16, InstrItinClass itinQ32,
3034 string OpcodeStr, string Dt,
3036 // 64-bit vector types.
3037 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
3038 OpcodeStr, !strconcat(Dt, "16"),
3039 v4i16, v4i16, IntOp>;
3040 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
3041 OpcodeStr, !strconcat(Dt, "32"),
3042 v2i32, v2i32, IntOp>;
3044 // 128-bit vector types.
3045 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3046 OpcodeStr, !strconcat(Dt, "16"),
3047 v8i16, v8i16, IntOp>;
3048 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3049 OpcodeStr, !strconcat(Dt, "32"),
3050 v4i32, v4i32, IntOp>;
3053 multiclass N3VIntSL_HS<bits<4> op11_8,
3054 InstrItinClass itinD16, InstrItinClass itinD32,
3055 InstrItinClass itinQ16, InstrItinClass itinQ32,
3056 string OpcodeStr, string Dt, Intrinsic IntOp> {
3057 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
3058 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
3059 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
3060 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
3061 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
3062 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
3063 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
3064 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
3067 // ....then also with element size of 8 bits:
3068 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3069 InstrItinClass itinD16, InstrItinClass itinD32,
3070 InstrItinClass itinQ16, InstrItinClass itinQ32,
3071 string OpcodeStr, string Dt,
3072 Intrinsic IntOp, bit Commutable = 0>
3073 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3074 OpcodeStr, Dt, IntOp, Commutable> {
3075 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
3076 OpcodeStr, !strconcat(Dt, "8"),
3077 v8i8, v8i8, IntOp, Commutable>;
3078 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
3079 OpcodeStr, !strconcat(Dt, "8"),
3080 v16i8, v16i8, IntOp, Commutable>;
3082 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3083 InstrItinClass itinD16, InstrItinClass itinD32,
3084 InstrItinClass itinQ16, InstrItinClass itinQ32,
3085 string OpcodeStr, string Dt,
3087 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3088 OpcodeStr, Dt, IntOp> {
3089 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
3090 OpcodeStr, !strconcat(Dt, "8"),
3092 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
3093 OpcodeStr, !strconcat(Dt, "8"),
3094 v16i8, v16i8, IntOp>;
3098 // ....then also with element size of 64 bits:
3099 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3100 InstrItinClass itinD16, InstrItinClass itinD32,
3101 InstrItinClass itinQ16, InstrItinClass itinQ32,
3102 string OpcodeStr, string Dt,
3103 Intrinsic IntOp, bit Commutable = 0>
3104 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3105 OpcodeStr, Dt, IntOp, Commutable> {
3106 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
3107 OpcodeStr, !strconcat(Dt, "64"),
3108 v1i64, v1i64, IntOp, Commutable>;
3109 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3110 OpcodeStr, !strconcat(Dt, "64"),
3111 v2i64, v2i64, IntOp, Commutable>;
3113 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3114 InstrItinClass itinD16, InstrItinClass itinD32,
3115 InstrItinClass itinQ16, InstrItinClass itinQ32,
3116 string OpcodeStr, string Dt,
3118 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3119 OpcodeStr, Dt, IntOp> {
3120 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
3121 OpcodeStr, !strconcat(Dt, "64"),
3122 v1i64, v1i64, IntOp>;
3123 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3124 OpcodeStr, !strconcat(Dt, "64"),
3125 v2i64, v2i64, IntOp>;
3128 // Neon Narrowing 3-register vector intrinsics,
3129 // source operand element sizes of 16, 32 and 64 bits:
3130 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3131 string OpcodeStr, string Dt,
3132 Intrinsic IntOp, bit Commutable = 0> {
3133 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
3134 OpcodeStr, !strconcat(Dt, "16"),
3135 v8i8, v8i16, IntOp, Commutable>;
3136 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
3137 OpcodeStr, !strconcat(Dt, "32"),
3138 v4i16, v4i32, IntOp, Commutable>;
3139 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
3140 OpcodeStr, !strconcat(Dt, "64"),
3141 v2i32, v2i64, IntOp, Commutable>;
3145 // Neon Long 3-register vector operations.
3147 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3148 InstrItinClass itin16, InstrItinClass itin32,
3149 string OpcodeStr, string Dt,
3150 SDNode OpNode, bit Commutable = 0> {
3151 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
3152 OpcodeStr, !strconcat(Dt, "8"),
3153 v8i16, v8i8, OpNode, Commutable>;
3154 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
3155 OpcodeStr, !strconcat(Dt, "16"),
3156 v4i32, v4i16, OpNode, Commutable>;
3157 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
3158 OpcodeStr, !strconcat(Dt, "32"),
3159 v2i64, v2i32, OpNode, Commutable>;
3162 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
3163 InstrItinClass itin, string OpcodeStr, string Dt,
3165 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
3166 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
3167 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
3168 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
3171 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3172 InstrItinClass itin16, InstrItinClass itin32,
3173 string OpcodeStr, string Dt,
3174 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3175 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
3176 OpcodeStr, !strconcat(Dt, "8"),
3177 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3178 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
3179 OpcodeStr, !strconcat(Dt, "16"),
3180 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3181 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
3182 OpcodeStr, !strconcat(Dt, "32"),
3183 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3186 // Neon Long 3-register vector intrinsics.
3188 // First with only element sizes of 16 and 32 bits:
3189 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3190 InstrItinClass itin16, InstrItinClass itin32,
3191 string OpcodeStr, string Dt,
3192 Intrinsic IntOp, bit Commutable = 0> {
3193 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
3194 OpcodeStr, !strconcat(Dt, "16"),
3195 v4i32, v4i16, IntOp, Commutable>;
3196 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
3197 OpcodeStr, !strconcat(Dt, "32"),
3198 v2i64, v2i32, IntOp, Commutable>;
3201 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
3202 InstrItinClass itin, string OpcodeStr, string Dt,
3204 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
3205 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3206 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
3207 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3210 // ....then also with element size of 8 bits:
3211 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3212 InstrItinClass itin16, InstrItinClass itin32,
3213 string OpcodeStr, string Dt,
3214 Intrinsic IntOp, bit Commutable = 0>
3215 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
3216 IntOp, Commutable> {
3217 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
3218 OpcodeStr, !strconcat(Dt, "8"),
3219 v8i16, v8i8, IntOp, Commutable>;
3222 // ....with explicit extend (VABDL).
3223 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3224 InstrItinClass itin, string OpcodeStr, string Dt,
3225 Intrinsic IntOp, SDNode ExtOp, bit Commutable = 0> {
3226 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
3227 OpcodeStr, !strconcat(Dt, "8"),
3228 v8i16, v8i8, IntOp, ExtOp, Commutable>;
3229 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
3230 OpcodeStr, !strconcat(Dt, "16"),
3231 v4i32, v4i16, IntOp, ExtOp, Commutable>;
3232 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
3233 OpcodeStr, !strconcat(Dt, "32"),
3234 v2i64, v2i32, IntOp, ExtOp, Commutable>;
3238 // Neon Wide 3-register vector intrinsics,
3239 // source operand element sizes of 8, 16 and 32 bits:
3240 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3241 string OpcodeStr, string Dt,
3242 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3243 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
3244 OpcodeStr, !strconcat(Dt, "8"),
3245 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3246 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
3247 OpcodeStr, !strconcat(Dt, "16"),
3248 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3249 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
3250 OpcodeStr, !strconcat(Dt, "32"),
3251 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3255 // Neon Multiply-Op vector operations,
3256 // element sizes of 8, 16 and 32 bits:
3257 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3258 InstrItinClass itinD16, InstrItinClass itinD32,
3259 InstrItinClass itinQ16, InstrItinClass itinQ32,
3260 string OpcodeStr, string Dt, SDNode OpNode> {
3261 // 64-bit vector types.
3262 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
3263 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
3264 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
3265 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
3266 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
3267 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
3269 // 128-bit vector types.
3270 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
3271 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
3272 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
3273 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
3274 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
3275 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
3278 multiclass N3VMulOpSL_HS<bits<4> op11_8,
3279 InstrItinClass itinD16, InstrItinClass itinD32,
3280 InstrItinClass itinQ16, InstrItinClass itinQ32,
3281 string OpcodeStr, string Dt, SDNode ShOp> {
3282 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
3283 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
3284 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
3285 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
3286 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
3287 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
3289 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
3290 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
3294 // Neon Intrinsic-Op vector operations,
3295 // element sizes of 8, 16 and 32 bits:
3296 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3297 InstrItinClass itinD, InstrItinClass itinQ,
3298 string OpcodeStr, string Dt, Intrinsic IntOp,
3300 // 64-bit vector types.
3301 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
3302 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
3303 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
3304 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
3305 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
3306 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
3308 // 128-bit vector types.
3309 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
3310 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
3311 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
3312 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
3313 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
3314 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
3317 // Neon 3-argument intrinsics,
3318 // element sizes of 8, 16 and 32 bits:
3319 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3320 InstrItinClass itinD, InstrItinClass itinQ,
3321 string OpcodeStr, string Dt, Intrinsic IntOp> {
3322 // 64-bit vector types.
3323 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
3324 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
3325 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
3326 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
3327 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
3328 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
3330 // 128-bit vector types.
3331 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
3332 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
3333 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
3334 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
3335 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
3336 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
3340 // Neon Long Multiply-Op vector operations,
3341 // element sizes of 8, 16 and 32 bits:
3342 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3343 InstrItinClass itin16, InstrItinClass itin32,
3344 string OpcodeStr, string Dt, SDNode MulOp,
3346 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
3347 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
3348 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
3349 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
3350 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
3351 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3354 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
3355 string Dt, SDNode MulOp, SDNode OpNode> {
3356 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
3357 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
3358 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
3359 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3363 // Neon Long 3-argument intrinsics.
3365 // First with only element sizes of 16 and 32 bits:
3366 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3367 InstrItinClass itin16, InstrItinClass itin32,
3368 string OpcodeStr, string Dt, Intrinsic IntOp> {
3369 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
3370 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3371 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
3372 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3375 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
3376 string OpcodeStr, string Dt, Intrinsic IntOp> {
3377 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
3378 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
3379 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
3380 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3383 // ....then also with element size of 8 bits:
3384 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3385 InstrItinClass itin16, InstrItinClass itin32,
3386 string OpcodeStr, string Dt, Intrinsic IntOp>
3387 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
3388 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
3389 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
3392 // ....with explicit extend (VABAL).
3393 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3394 InstrItinClass itin, string OpcodeStr, string Dt,
3395 Intrinsic IntOp, SDNode ExtOp, SDNode OpNode> {
3396 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
3397 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
3398 IntOp, ExtOp, OpNode>;
3399 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
3400 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
3401 IntOp, ExtOp, OpNode>;
3402 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
3403 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
3404 IntOp, ExtOp, OpNode>;
3408 // Neon Pairwise long 2-register intrinsics,
3409 // element sizes of 8, 16 and 32 bits:
3410 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3411 bits<5> op11_7, bit op4,
3412 string OpcodeStr, string Dt, Intrinsic IntOp> {
3413 // 64-bit vector types.
3414 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3415 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3416 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3417 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3418 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3419 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3421 // 128-bit vector types.
3422 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3423 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3424 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3425 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3426 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3427 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3431 // Neon Pairwise long 2-register accumulate intrinsics,
3432 // element sizes of 8, 16 and 32 bits:
3433 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3434 bits<5> op11_7, bit op4,
3435 string OpcodeStr, string Dt, Intrinsic IntOp> {
3436 // 64-bit vector types.
3437 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3438 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3439 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3440 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3441 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3442 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3444 // 128-bit vector types.
3445 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3446 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3447 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3448 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3449 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3450 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3454 // Neon 2-register vector shift by immediate,
3455 // with f of either N2RegVShLFrm or N2RegVShRFrm
3456 // element sizes of 8, 16, 32 and 64 bits:
3457 multiclass N2VShL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3458 InstrItinClass itin, string OpcodeStr, string Dt,
3460 // 64-bit vector types.
3461 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3462 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3463 let Inst{21-19} = 0b001; // imm6 = 001xxx
3465 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3466 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3467 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3469 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3470 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3471 let Inst{21} = 0b1; // imm6 = 1xxxxx
3473 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3474 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3477 // 128-bit vector types.
3478 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3479 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3480 let Inst{21-19} = 0b001; // imm6 = 001xxx
3482 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3483 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3484 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3486 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3487 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3488 let Inst{21} = 0b1; // imm6 = 1xxxxx
3490 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3491 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3494 multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3495 InstrItinClass itin, string OpcodeStr, string Dt,
3497 // 64-bit vector types.
3498 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3499 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3500 let Inst{21-19} = 0b001; // imm6 = 001xxx
3502 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3503 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3504 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3506 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3507 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3508 let Inst{21} = 0b1; // imm6 = 1xxxxx
3510 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3511 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3514 // 128-bit vector types.
3515 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3516 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3517 let Inst{21-19} = 0b001; // imm6 = 001xxx
3519 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3520 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3521 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3523 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3524 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3525 let Inst{21} = 0b1; // imm6 = 1xxxxx
3527 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3528 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3532 // Neon Shift-Accumulate vector operations,
3533 // element sizes of 8, 16, 32 and 64 bits:
3534 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3535 string OpcodeStr, string Dt, SDNode ShOp> {
3536 // 64-bit vector types.
3537 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3538 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
3539 let Inst{21-19} = 0b001; // imm6 = 001xxx
3541 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3542 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
3543 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3545 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3546 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
3547 let Inst{21} = 0b1; // imm6 = 1xxxxx
3549 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3550 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
3553 // 128-bit vector types.
3554 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3555 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
3556 let Inst{21-19} = 0b001; // imm6 = 001xxx
3558 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3559 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
3560 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3562 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3563 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
3564 let Inst{21} = 0b1; // imm6 = 1xxxxx
3566 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3567 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
3571 // Neon Shift-Insert vector operations,
3572 // with f of either N2RegVShLFrm or N2RegVShRFrm
3573 // element sizes of 8, 16, 32 and 64 bits:
3574 multiclass N2VShInsL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3576 // 64-bit vector types.
3577 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3578 N2RegVShLFrm, OpcodeStr, "8", v8i8, NEONvsli> {
3579 let Inst{21-19} = 0b001; // imm6 = 001xxx
3581 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3582 N2RegVShLFrm, OpcodeStr, "16", v4i16, NEONvsli> {
3583 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3585 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3586 N2RegVShLFrm, OpcodeStr, "32", v2i32, NEONvsli> {
3587 let Inst{21} = 0b1; // imm6 = 1xxxxx
3589 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, i32imm,
3590 N2RegVShLFrm, OpcodeStr, "64", v1i64, NEONvsli>;
3593 // 128-bit vector types.
3594 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3595 N2RegVShLFrm, OpcodeStr, "8", v16i8, NEONvsli> {
3596 let Inst{21-19} = 0b001; // imm6 = 001xxx
3598 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3599 N2RegVShLFrm, OpcodeStr, "16", v8i16, NEONvsli> {
3600 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3602 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3603 N2RegVShLFrm, OpcodeStr, "32", v4i32, NEONvsli> {
3604 let Inst{21} = 0b1; // imm6 = 1xxxxx
3606 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, i32imm,
3607 N2RegVShLFrm, OpcodeStr, "64", v2i64, NEONvsli>;
3610 multiclass N2VShInsR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3612 // 64-bit vector types.
3613 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3614 N2RegVShRFrm, OpcodeStr, "8", v8i8, NEONvsri> {
3615 let Inst{21-19} = 0b001; // imm6 = 001xxx
3617 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3618 N2RegVShRFrm, OpcodeStr, "16", v4i16, NEONvsri> {
3619 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3621 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3622 N2RegVShRFrm, OpcodeStr, "32", v2i32, NEONvsri> {
3623 let Inst{21} = 0b1; // imm6 = 1xxxxx
3625 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3626 N2RegVShRFrm, OpcodeStr, "64", v1i64, NEONvsri>;
3629 // 128-bit vector types.
3630 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3631 N2RegVShRFrm, OpcodeStr, "8", v16i8, NEONvsri> {
3632 let Inst{21-19} = 0b001; // imm6 = 001xxx
3634 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3635 N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsri> {
3636 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3638 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3639 N2RegVShRFrm, OpcodeStr, "32", v4i32, NEONvsri> {
3640 let Inst{21} = 0b1; // imm6 = 1xxxxx
3642 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3643 N2RegVShRFrm, OpcodeStr, "64", v2i64, NEONvsri>;
3647 // Neon Shift Long operations,
3648 // element sizes of 8, 16, 32 bits:
3649 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3650 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
3651 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3652 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, imm1_7, OpNode> {
3653 let Inst{21-19} = 0b001; // imm6 = 001xxx
3655 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3656 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, imm1_15, OpNode> {
3657 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3659 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3660 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, imm1_31, OpNode> {
3661 let Inst{21} = 0b1; // imm6 = 1xxxxx
3665 // Neon Shift Narrow operations,
3666 // element sizes of 16, 32, 64 bits:
3667 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3668 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
3670 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3671 OpcodeStr, !strconcat(Dt, "16"),
3672 v8i8, v8i16, shr_imm8, OpNode> {
3673 let Inst{21-19} = 0b001; // imm6 = 001xxx
3675 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3676 OpcodeStr, !strconcat(Dt, "32"),
3677 v4i16, v4i32, shr_imm16, OpNode> {
3678 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3680 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3681 OpcodeStr, !strconcat(Dt, "64"),
3682 v2i32, v2i64, shr_imm32, OpNode> {
3683 let Inst{21} = 0b1; // imm6 = 1xxxxx
3687 //===----------------------------------------------------------------------===//
3688 // Instruction Definitions.
3689 //===----------------------------------------------------------------------===//
3691 // Vector Add Operations.
3693 // VADD : Vector Add (integer and floating-point)
3694 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
3696 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
3697 v2f32, v2f32, fadd, 1>;
3698 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
3699 v4f32, v4f32, fadd, 1>;
3700 // VADDL : Vector Add Long (Q = D + D)
3701 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3702 "vaddl", "s", add, sext, 1>;
3703 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3704 "vaddl", "u", add, zext, 1>;
3705 // VADDW : Vector Add Wide (Q = Q + D)
3706 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
3707 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
3708 // VHADD : Vector Halving Add
3709 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
3710 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3711 "vhadd", "s", int_arm_neon_vhadds, 1>;
3712 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
3713 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3714 "vhadd", "u", int_arm_neon_vhaddu, 1>;
3715 // VRHADD : Vector Rounding Halving Add
3716 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
3717 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3718 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
3719 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
3720 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3721 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
3722 // VQADD : Vector Saturating Add
3723 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
3724 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3725 "vqadd", "s", int_arm_neon_vqadds, 1>;
3726 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
3727 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3728 "vqadd", "u", int_arm_neon_vqaddu, 1>;
3729 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
3730 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
3731 int_arm_neon_vaddhn, 1>;
3732 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
3733 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
3734 int_arm_neon_vraddhn, 1>;
3736 // Vector Multiply Operations.
3738 // VMUL : Vector Multiply (integer, polynomial and floating-point)
3739 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
3740 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
3741 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
3742 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
3743 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
3744 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
3745 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
3746 v2f32, v2f32, fmul, 1>;
3747 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
3748 v4f32, v4f32, fmul, 1>;
3749 defm VMULsl : N3VSL_HS<0b1000, "vmul", mul>;
3750 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
3751 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
3754 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
3755 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
3756 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
3757 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3758 (DSubReg_i16_reg imm:$lane))),
3759 (SubReg_i16_lane imm:$lane)))>;
3760 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
3761 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
3762 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
3763 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3764 (DSubReg_i32_reg imm:$lane))),
3765 (SubReg_i32_lane imm:$lane)))>;
3766 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
3767 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
3768 (v4f32 (VMULslfq (v4f32 QPR:$src1),
3769 (v2f32 (EXTRACT_SUBREG QPR:$src2,
3770 (DSubReg_i32_reg imm:$lane))),
3771 (SubReg_i32_lane imm:$lane)))>;
3773 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
3774 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
3775 IIC_VMULi16Q, IIC_VMULi32Q,
3776 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
3777 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
3778 IIC_VMULi16Q, IIC_VMULi32Q,
3779 "vqdmulh", "s", int_arm_neon_vqdmulh>;
3780 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
3781 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3783 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
3784 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3785 (DSubReg_i16_reg imm:$lane))),
3786 (SubReg_i16_lane imm:$lane)))>;
3787 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
3788 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3790 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
3791 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3792 (DSubReg_i32_reg imm:$lane))),
3793 (SubReg_i32_lane imm:$lane)))>;
3795 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
3796 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
3797 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
3798 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
3799 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
3800 IIC_VMULi16Q, IIC_VMULi32Q,
3801 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
3802 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
3803 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3805 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
3806 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3807 (DSubReg_i16_reg imm:$lane))),
3808 (SubReg_i16_lane imm:$lane)))>;
3809 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
3810 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3812 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
3813 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3814 (DSubReg_i32_reg imm:$lane))),
3815 (SubReg_i32_lane imm:$lane)))>;
3817 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
3818 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3819 "vmull", "s", NEONvmulls, 1>;
3820 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3821 "vmull", "u", NEONvmullu, 1>;
3822 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
3823 v8i16, v8i8, int_arm_neon_vmullp, 1>;
3824 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
3825 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
3827 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
3828 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
3829 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
3830 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
3831 "vqdmull", "s", int_arm_neon_vqdmull>;
3833 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
3835 // VMLA : Vector Multiply Accumulate (integer and floating-point)
3836 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3837 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3838 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
3839 v2f32, fmul_su, fadd_mlx>,
3840 Requires<[HasNEON, UseFPVMLx]>;
3841 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
3842 v4f32, fmul_su, fadd_mlx>,
3843 Requires<[HasNEON, UseFPVMLx]>;
3844 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
3845 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3846 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
3847 v2f32, fmul_su, fadd_mlx>,
3848 Requires<[HasNEON, UseFPVMLx]>;
3849 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
3850 v4f32, v2f32, fmul_su, fadd_mlx>,
3851 Requires<[HasNEON, UseFPVMLx]>;
3853 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
3854 (mul (v8i16 QPR:$src2),
3855 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3856 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3857 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3858 (DSubReg_i16_reg imm:$lane))),
3859 (SubReg_i16_lane imm:$lane)))>;
3861 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
3862 (mul (v4i32 QPR:$src2),
3863 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3864 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3865 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3866 (DSubReg_i32_reg imm:$lane))),
3867 (SubReg_i32_lane imm:$lane)))>;
3869 def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1),
3870 (fmul_su (v4f32 QPR:$src2),
3871 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3872 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
3874 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3875 (DSubReg_i32_reg imm:$lane))),
3876 (SubReg_i32_lane imm:$lane)))>,
3877 Requires<[HasNEON, UseFPVMLx]>;
3879 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
3880 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3881 "vmlal", "s", NEONvmulls, add>;
3882 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3883 "vmlal", "u", NEONvmullu, add>;
3885 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
3886 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
3888 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
3889 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3890 "vqdmlal", "s", int_arm_neon_vqdmlal>;
3891 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
3893 // VMLS : Vector Multiply Subtract (integer and floating-point)
3894 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3895 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3896 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
3897 v2f32, fmul_su, fsub_mlx>,
3898 Requires<[HasNEON, UseFPVMLx]>;
3899 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
3900 v4f32, fmul_su, fsub_mlx>,
3901 Requires<[HasNEON, UseFPVMLx]>;
3902 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
3903 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3904 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
3905 v2f32, fmul_su, fsub_mlx>,
3906 Requires<[HasNEON, UseFPVMLx]>;
3907 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
3908 v4f32, v2f32, fmul_su, fsub_mlx>,
3909 Requires<[HasNEON, UseFPVMLx]>;
3911 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
3912 (mul (v8i16 QPR:$src2),
3913 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3914 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3915 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3916 (DSubReg_i16_reg imm:$lane))),
3917 (SubReg_i16_lane imm:$lane)))>;
3919 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
3920 (mul (v4i32 QPR:$src2),
3921 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3922 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3923 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3924 (DSubReg_i32_reg imm:$lane))),
3925 (SubReg_i32_lane imm:$lane)))>;
3927 def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1),
3928 (fmul_su (v4f32 QPR:$src2),
3929 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3930 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
3931 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3932 (DSubReg_i32_reg imm:$lane))),
3933 (SubReg_i32_lane imm:$lane)))>,
3934 Requires<[HasNEON, UseFPVMLx]>;
3936 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
3937 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3938 "vmlsl", "s", NEONvmulls, sub>;
3939 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3940 "vmlsl", "u", NEONvmullu, sub>;
3942 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
3943 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
3945 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
3946 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
3947 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3948 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3950 // Vector Subtract Operations.
3952 // VSUB : Vector Subtract (integer and floating-point)
3953 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
3954 "vsub", "i", sub, 0>;
3955 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
3956 v2f32, v2f32, fsub, 0>;
3957 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
3958 v4f32, v4f32, fsub, 0>;
3959 // VSUBL : Vector Subtract Long (Q = D - D)
3960 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3961 "vsubl", "s", sub, sext, 0>;
3962 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3963 "vsubl", "u", sub, zext, 0>;
3964 // VSUBW : Vector Subtract Wide (Q = Q - D)
3965 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
3966 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
3967 // VHSUB : Vector Halving Subtract
3968 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
3969 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3970 "vhsub", "s", int_arm_neon_vhsubs, 0>;
3971 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
3972 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3973 "vhsub", "u", int_arm_neon_vhsubu, 0>;
3974 // VQSUB : Vector Saturing Subtract
3975 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
3976 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3977 "vqsub", "s", int_arm_neon_vqsubs, 0>;
3978 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
3979 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3980 "vqsub", "u", int_arm_neon_vqsubu, 0>;
3981 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
3982 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
3983 int_arm_neon_vsubhn, 0>;
3984 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
3985 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
3986 int_arm_neon_vrsubhn, 0>;
3988 // Vector Comparisons.
3990 // VCEQ : Vector Compare Equal
3991 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3992 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
3993 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
3995 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
3998 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
3999 "$Vd, $Vm, #0", NEONvceqz>;
4001 // VCGE : Vector Compare Greater Than or Equal
4002 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4003 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
4004 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4005 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
4006 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
4008 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
4011 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
4012 "$Vd, $Vm, #0", NEONvcgez>;
4013 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
4014 "$Vd, $Vm, #0", NEONvclez>;
4016 // VCGT : Vector Compare Greater Than
4017 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4018 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
4019 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4020 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
4021 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
4023 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
4026 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
4027 "$Vd, $Vm, #0", NEONvcgtz>;
4028 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
4029 "$Vd, $Vm, #0", NEONvcltz>;
4031 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
4032 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
4033 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
4034 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
4035 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
4036 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
4037 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
4038 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
4039 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
4040 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
4041 // VTST : Vector Test Bits
4042 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
4043 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
4045 // Vector Bitwise Operations.
4047 def vnotd : PatFrag<(ops node:$in),
4048 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
4049 def vnotq : PatFrag<(ops node:$in),
4050 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
4053 // VAND : Vector Bitwise AND
4054 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
4055 v2i32, v2i32, and, 1>;
4056 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
4057 v4i32, v4i32, and, 1>;
4059 // VEOR : Vector Bitwise Exclusive OR
4060 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
4061 v2i32, v2i32, xor, 1>;
4062 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
4063 v4i32, v4i32, xor, 1>;
4065 // VORR : Vector Bitwise OR
4066 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
4067 v2i32, v2i32, or, 1>;
4068 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
4069 v4i32, v4i32, or, 1>;
4071 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
4072 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4074 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4076 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4077 let Inst{9} = SIMM{9};
4080 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
4081 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4083 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4085 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4086 let Inst{10-9} = SIMM{10-9};
4089 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
4090 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4092 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4094 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4095 let Inst{9} = SIMM{9};
4098 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
4099 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4101 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4103 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4104 let Inst{10-9} = SIMM{10-9};
4108 // VBIC : Vector Bitwise Bit Clear (AND NOT)
4109 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4110 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
4111 "vbic", "$Vd, $Vn, $Vm", "",
4112 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
4113 (vnotd DPR:$Vm))))]>;
4114 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4115 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4116 "vbic", "$Vd, $Vn, $Vm", "",
4117 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
4118 (vnotq QPR:$Vm))))]>;
4120 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
4121 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4123 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4125 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4126 let Inst{9} = SIMM{9};
4129 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
4130 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4132 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4134 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4135 let Inst{10-9} = SIMM{10-9};
4138 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
4139 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4141 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4143 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4144 let Inst{9} = SIMM{9};
4147 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
4148 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4150 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4152 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4153 let Inst{10-9} = SIMM{10-9};
4156 // VORN : Vector Bitwise OR NOT
4157 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
4158 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
4159 "vorn", "$Vd, $Vn, $Vm", "",
4160 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
4161 (vnotd DPR:$Vm))))]>;
4162 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
4163 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4164 "vorn", "$Vd, $Vn, $Vm", "",
4165 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
4166 (vnotq QPR:$Vm))))]>;
4168 // VMVN : Vector Bitwise NOT (Immediate)
4170 let isReMaterializable = 1 in {
4172 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
4173 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4174 "vmvn", "i16", "$Vd, $SIMM", "",
4175 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
4176 let Inst{9} = SIMM{9};
4179 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
4180 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4181 "vmvn", "i16", "$Vd, $SIMM", "",
4182 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
4183 let Inst{9} = SIMM{9};
4186 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
4187 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4188 "vmvn", "i32", "$Vd, $SIMM", "",
4189 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
4190 let Inst{11-8} = SIMM{11-8};
4193 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
4194 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4195 "vmvn", "i32", "$Vd, $SIMM", "",
4196 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
4197 let Inst{11-8} = SIMM{11-8};
4201 // VMVN : Vector Bitwise NOT
4202 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
4203 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
4204 "vmvn", "$Vd, $Vm", "",
4205 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
4206 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
4207 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
4208 "vmvn", "$Vd, $Vm", "",
4209 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
4210 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
4211 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
4213 // VBSL : Vector Bitwise Select
4214 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4215 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4216 N3RegFrm, IIC_VCNTiD,
4217 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4219 (v2i32 (NEONvbsl DPR:$src1, DPR:$Vn, DPR:$Vm)))]>;
4221 def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
4222 (and DPR:$Vm, (vnotd DPR:$Vd)))),
4223 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>;
4225 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4226 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4227 N3RegFrm, IIC_VCNTiQ,
4228 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4230 (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>;
4232 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
4233 (and QPR:$Vm, (vnotq QPR:$Vd)))),
4234 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
4236 // VBIF : Vector Bitwise Insert if False
4237 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
4238 // FIXME: This instruction's encoding MAY NOT BE correct.
4239 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
4240 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4241 N3RegFrm, IIC_VBINiD,
4242 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4244 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
4245 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4246 N3RegFrm, IIC_VBINiQ,
4247 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4250 // VBIT : Vector Bitwise Insert if True
4251 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
4252 // FIXME: This instruction's encoding MAY NOT BE correct.
4253 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
4254 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4255 N3RegFrm, IIC_VBINiD,
4256 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4258 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
4259 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4260 N3RegFrm, IIC_VBINiQ,
4261 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4264 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
4265 // for equivalent operations with different register constraints; it just
4268 // Vector Absolute Differences.
4270 // VABD : Vector Absolute Difference
4271 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
4272 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4273 "vabd", "s", int_arm_neon_vabds, 1>;
4274 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
4275 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4276 "vabd", "u", int_arm_neon_vabdu, 1>;
4277 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
4278 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
4279 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
4280 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
4282 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
4283 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
4284 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
4285 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
4286 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
4288 // VABA : Vector Absolute Difference and Accumulate
4289 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4290 "vaba", "s", int_arm_neon_vabds, add>;
4291 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4292 "vaba", "u", int_arm_neon_vabdu, add>;
4294 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
4295 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
4296 "vabal", "s", int_arm_neon_vabds, zext, add>;
4297 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
4298 "vabal", "u", int_arm_neon_vabdu, zext, add>;
4300 // Vector Maximum and Minimum.
4302 // VMAX : Vector Maximum
4303 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
4304 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4305 "vmax", "s", int_arm_neon_vmaxs, 1>;
4306 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
4307 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4308 "vmax", "u", int_arm_neon_vmaxu, 1>;
4309 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
4311 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
4312 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4314 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
4316 // VMIN : Vector Minimum
4317 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
4318 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4319 "vmin", "s", int_arm_neon_vmins, 1>;
4320 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
4321 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4322 "vmin", "u", int_arm_neon_vminu, 1>;
4323 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
4325 v2f32, v2f32, int_arm_neon_vmins, 1>;
4326 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4328 v4f32, v4f32, int_arm_neon_vmins, 1>;
4330 // Vector Pairwise Operations.
4332 // VPADD : Vector Pairwise Add
4333 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4335 v8i8, v8i8, int_arm_neon_vpadd, 0>;
4336 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4338 v4i16, v4i16, int_arm_neon_vpadd, 0>;
4339 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4341 v2i32, v2i32, int_arm_neon_vpadd, 0>;
4342 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
4343 IIC_VPBIND, "vpadd", "f32",
4344 v2f32, v2f32, int_arm_neon_vpadd, 0>;
4346 // VPADDL : Vector Pairwise Add Long
4347 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
4348 int_arm_neon_vpaddls>;
4349 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
4350 int_arm_neon_vpaddlu>;
4352 // VPADAL : Vector Pairwise Add and Accumulate Long
4353 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
4354 int_arm_neon_vpadals>;
4355 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
4356 int_arm_neon_vpadalu>;
4358 // VPMAX : Vector Pairwise Maximum
4359 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4360 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
4361 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4362 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
4363 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4364 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
4365 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4366 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
4367 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4368 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
4369 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4370 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
4371 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
4372 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
4374 // VPMIN : Vector Pairwise Minimum
4375 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4376 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
4377 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4378 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
4379 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4380 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
4381 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4382 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
4383 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4384 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
4385 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4386 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
4387 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
4388 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
4390 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
4392 // VRECPE : Vector Reciprocal Estimate
4393 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4394 IIC_VUNAD, "vrecpe", "u32",
4395 v2i32, v2i32, int_arm_neon_vrecpe>;
4396 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4397 IIC_VUNAQ, "vrecpe", "u32",
4398 v4i32, v4i32, int_arm_neon_vrecpe>;
4399 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4400 IIC_VUNAD, "vrecpe", "f32",
4401 v2f32, v2f32, int_arm_neon_vrecpe>;
4402 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4403 IIC_VUNAQ, "vrecpe", "f32",
4404 v4f32, v4f32, int_arm_neon_vrecpe>;
4406 // VRECPS : Vector Reciprocal Step
4407 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4408 IIC_VRECSD, "vrecps", "f32",
4409 v2f32, v2f32, int_arm_neon_vrecps, 1>;
4410 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4411 IIC_VRECSQ, "vrecps", "f32",
4412 v4f32, v4f32, int_arm_neon_vrecps, 1>;
4414 // VRSQRTE : Vector Reciprocal Square Root Estimate
4415 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4416 IIC_VUNAD, "vrsqrte", "u32",
4417 v2i32, v2i32, int_arm_neon_vrsqrte>;
4418 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4419 IIC_VUNAQ, "vrsqrte", "u32",
4420 v4i32, v4i32, int_arm_neon_vrsqrte>;
4421 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4422 IIC_VUNAD, "vrsqrte", "f32",
4423 v2f32, v2f32, int_arm_neon_vrsqrte>;
4424 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4425 IIC_VUNAQ, "vrsqrte", "f32",
4426 v4f32, v4f32, int_arm_neon_vrsqrte>;
4428 // VRSQRTS : Vector Reciprocal Square Root Step
4429 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4430 IIC_VRECSD, "vrsqrts", "f32",
4431 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
4432 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4433 IIC_VRECSQ, "vrsqrts", "f32",
4434 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
4438 // VSHL : Vector Shift
4439 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
4440 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4441 "vshl", "s", int_arm_neon_vshifts>;
4442 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
4443 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4444 "vshl", "u", int_arm_neon_vshiftu>;
4446 // VSHL : Vector Shift Left (Immediate)
4447 defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
4449 // VSHR : Vector Shift Right (Immediate)
4450 defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s",NEONvshrs>;
4451 defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u",NEONvshru>;
4453 // VSHLL : Vector Shift Left Long
4454 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
4455 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
4457 // VSHLL : Vector Shift Left Long (with maximum shift count)
4458 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
4459 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
4460 ValueType OpTy, Operand ImmTy, SDNode OpNode>
4461 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
4462 ResTy, OpTy, ImmTy, OpNode> {
4463 let Inst{21-16} = op21_16;
4464 let DecoderMethod = "DecodeVSHLMaxInstruction";
4466 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
4467 v8i16, v8i8, imm8, NEONvshlli>;
4468 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
4469 v4i32, v4i16, imm16, NEONvshlli>;
4470 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
4471 v2i64, v2i32, imm32, NEONvshlli>;
4473 // VSHRN : Vector Shift Right and Narrow
4474 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
4477 // VRSHL : Vector Rounding Shift
4478 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
4479 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4480 "vrshl", "s", int_arm_neon_vrshifts>;
4481 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
4482 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4483 "vrshl", "u", int_arm_neon_vrshiftu>;
4484 // VRSHR : Vector Rounding Shift Right
4485 defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s",NEONvrshrs>;
4486 defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u",NEONvrshru>;
4488 // VRSHRN : Vector Rounding Shift Right and Narrow
4489 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
4492 // VQSHL : Vector Saturating Shift
4493 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
4494 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4495 "vqshl", "s", int_arm_neon_vqshifts>;
4496 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
4497 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4498 "vqshl", "u", int_arm_neon_vqshiftu>;
4499 // VQSHL : Vector Saturating Shift Left (Immediate)
4500 defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls>;
4501 defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu>;
4503 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
4504 defm VQSHLsu : N2VShL_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu>;
4506 // VQSHRN : Vector Saturating Shift Right and Narrow
4507 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
4509 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
4512 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
4513 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
4516 // VQRSHL : Vector Saturating Rounding Shift
4517 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
4518 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4519 "vqrshl", "s", int_arm_neon_vqrshifts>;
4520 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
4521 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4522 "vqrshl", "u", int_arm_neon_vqrshiftu>;
4524 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
4525 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
4527 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
4530 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
4531 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
4534 // VSRA : Vector Shift Right and Accumulate
4535 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
4536 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
4537 // VRSRA : Vector Rounding Shift Right and Accumulate
4538 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
4539 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
4541 // VSLI : Vector Shift Left and Insert
4542 defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">;
4544 // VSRI : Vector Shift Right and Insert
4545 defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;
4547 // Vector Absolute and Saturating Absolute.
4549 // VABS : Vector Absolute Value
4550 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
4551 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
4553 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4554 IIC_VUNAD, "vabs", "f32",
4555 v2f32, v2f32, int_arm_neon_vabs>;
4556 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4557 IIC_VUNAQ, "vabs", "f32",
4558 v4f32, v4f32, int_arm_neon_vabs>;
4560 // VQABS : Vector Saturating Absolute Value
4561 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
4562 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
4563 int_arm_neon_vqabs>;
4567 def vnegd : PatFrag<(ops node:$in),
4568 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
4569 def vnegq : PatFrag<(ops node:$in),
4570 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
4572 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4573 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
4574 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
4575 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
4576 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4577 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
4578 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
4579 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
4581 // VNEG : Vector Negate (integer)
4582 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
4583 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
4584 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
4585 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
4586 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
4587 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
4589 // VNEG : Vector Negate (floating-point)
4590 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
4591 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
4592 "vneg", "f32", "$Vd, $Vm", "",
4593 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
4594 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
4595 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
4596 "vneg", "f32", "$Vd, $Vm", "",
4597 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
4599 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
4600 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
4601 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
4602 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
4603 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
4604 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
4606 // VQNEG : Vector Saturating Negate
4607 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
4608 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
4609 int_arm_neon_vqneg>;
4611 // Vector Bit Counting Operations.
4613 // VCLS : Vector Count Leading Sign Bits
4614 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
4615 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
4617 // VCLZ : Vector Count Leading Zeros
4618 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
4619 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
4621 // VCNT : Vector Count One Bits
4622 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4623 IIC_VCNTiD, "vcnt", "8",
4624 v8i8, v8i8, int_arm_neon_vcnt>;
4625 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4626 IIC_VCNTiQ, "vcnt", "8",
4627 v16i8, v16i8, int_arm_neon_vcnt>;
4630 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
4631 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
4632 "vswp", "$Vd, $Vm", "", []>;
4633 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
4634 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
4635 "vswp", "$Vd, $Vm", "", []>;
4637 // Vector Move Operations.
4639 // VMOV : Vector Move (Register)
4640 def : InstAlias<"vmov${p} $Vd, $Vm",
4641 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
4642 def : InstAlias<"vmov${p} $Vd, $Vm",
4643 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
4645 // VMOV : Vector Move (Immediate)
4647 let isReMaterializable = 1 in {
4648 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
4649 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
4650 "vmov", "i8", "$Vd, $SIMM", "",
4651 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
4652 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
4653 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
4654 "vmov", "i8", "$Vd, $SIMM", "",
4655 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
4657 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
4658 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4659 "vmov", "i16", "$Vd, $SIMM", "",
4660 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
4661 let Inst{9} = SIMM{9};
4664 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
4665 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4666 "vmov", "i16", "$Vd, $SIMM", "",
4667 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
4668 let Inst{9} = SIMM{9};
4671 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
4672 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4673 "vmov", "i32", "$Vd, $SIMM", "",
4674 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
4675 let Inst{11-8} = SIMM{11-8};
4678 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
4679 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4680 "vmov", "i32", "$Vd, $SIMM", "",
4681 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
4682 let Inst{11-8} = SIMM{11-8};
4685 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
4686 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
4687 "vmov", "i64", "$Vd, $SIMM", "",
4688 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
4689 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
4690 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
4691 "vmov", "i64", "$Vd, $SIMM", "",
4692 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
4694 def VMOVv2f32 : N1ModImm<1, 0b000, 0b1111, 0, 0, 0, 1, (outs DPR:$Vd),
4695 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
4696 "vmov", "f32", "$Vd, $SIMM", "",
4697 [(set DPR:$Vd, (v2f32 (NEONvmovFPImm timm:$SIMM)))]>;
4698 def VMOVv4f32 : N1ModImm<1, 0b000, 0b1111, 0, 1, 0, 1, (outs QPR:$Vd),
4699 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
4700 "vmov", "f32", "$Vd, $SIMM", "",
4701 [(set QPR:$Vd, (v4f32 (NEONvmovFPImm timm:$SIMM)))]>;
4702 } // isReMaterializable
4704 // VMOV : Vector Get Lane (move scalar to ARM core register)
4706 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
4707 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
4708 IIC_VMOVSI, "vmov", "s8", "$R, $V$lane",
4709 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
4711 let Inst{21} = lane{2};
4712 let Inst{6-5} = lane{1-0};
4714 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
4715 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
4716 IIC_VMOVSI, "vmov", "s16", "$R, $V$lane",
4717 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
4719 let Inst{21} = lane{1};
4720 let Inst{6} = lane{0};
4722 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
4723 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
4724 IIC_VMOVSI, "vmov", "u8", "$R, $V$lane",
4725 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
4727 let Inst{21} = lane{2};
4728 let Inst{6-5} = lane{1-0};
4730 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
4731 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
4732 IIC_VMOVSI, "vmov", "u16", "$R, $V$lane",
4733 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
4735 let Inst{21} = lane{1};
4736 let Inst{6} = lane{0};
4738 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
4739 (outs GPR:$R), (ins DPR:$V, VectorIndex32:$lane),
4740 IIC_VMOVSI, "vmov", "32", "$R, $V$lane",
4741 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
4743 let Inst{21} = lane{0};
4745 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
4746 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
4747 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4748 (DSubReg_i8_reg imm:$lane))),
4749 (SubReg_i8_lane imm:$lane))>;
4750 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
4751 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4752 (DSubReg_i16_reg imm:$lane))),
4753 (SubReg_i16_lane imm:$lane))>;
4754 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
4755 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4756 (DSubReg_i8_reg imm:$lane))),
4757 (SubReg_i8_lane imm:$lane))>;
4758 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
4759 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4760 (DSubReg_i16_reg imm:$lane))),
4761 (SubReg_i16_lane imm:$lane))>;
4762 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
4763 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
4764 (DSubReg_i32_reg imm:$lane))),
4765 (SubReg_i32_lane imm:$lane))>;
4766 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
4767 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
4768 (SSubReg_f32_reg imm:$src2))>;
4769 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
4770 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
4771 (SSubReg_f32_reg imm:$src2))>;
4772 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
4773 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4774 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
4775 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4778 // VMOV : Vector Set Lane (move ARM core register to scalar)
4780 let Constraints = "$src1 = $V" in {
4781 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
4782 (ins DPR:$src1, GPR:$R, VectorIndex8:$lane),
4783 IIC_VMOVISL, "vmov", "8", "$V$lane, $R",
4784 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
4785 GPR:$R, imm:$lane))]> {
4786 let Inst{21} = lane{2};
4787 let Inst{6-5} = lane{1-0};
4789 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
4790 (ins DPR:$src1, GPR:$R, VectorIndex16:$lane),
4791 IIC_VMOVISL, "vmov", "16", "$V$lane, $R",
4792 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
4793 GPR:$R, imm:$lane))]> {
4794 let Inst{21} = lane{1};
4795 let Inst{6} = lane{0};
4797 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
4798 (ins DPR:$src1, GPR:$R, VectorIndex32:$lane),
4799 IIC_VMOVISL, "vmov", "32", "$V$lane, $R",
4800 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
4801 GPR:$R, imm:$lane))]> {
4802 let Inst{21} = lane{0};
4805 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
4806 (v16i8 (INSERT_SUBREG QPR:$src1,
4807 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
4808 (DSubReg_i8_reg imm:$lane))),
4809 GPR:$src2, (SubReg_i8_lane imm:$lane))),
4810 (DSubReg_i8_reg imm:$lane)))>;
4811 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
4812 (v8i16 (INSERT_SUBREG QPR:$src1,
4813 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
4814 (DSubReg_i16_reg imm:$lane))),
4815 GPR:$src2, (SubReg_i16_lane imm:$lane))),
4816 (DSubReg_i16_reg imm:$lane)))>;
4817 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
4818 (v4i32 (INSERT_SUBREG QPR:$src1,
4819 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
4820 (DSubReg_i32_reg imm:$lane))),
4821 GPR:$src2, (SubReg_i32_lane imm:$lane))),
4822 (DSubReg_i32_reg imm:$lane)))>;
4824 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
4825 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
4826 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4827 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
4828 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
4829 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4831 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4832 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4833 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4834 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4836 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
4837 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4838 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
4839 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
4840 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
4841 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4843 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
4844 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4845 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
4846 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4847 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
4848 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4850 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
4851 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4852 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4854 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
4855 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
4856 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4858 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
4859 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4860 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4863 // VDUP : Vector Duplicate (from ARM core register to all elements)
4865 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4866 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
4867 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4868 [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4869 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4870 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
4871 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4872 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4874 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
4875 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
4876 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
4877 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
4878 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
4879 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
4881 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32d GPR:$R)>;
4882 def : Pat<(v4f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32q GPR:$R)>;
4884 // VDUP : Vector Duplicate Lane (from scalar to all elements)
4886 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
4887 ValueType Ty, Operand IdxTy>
4888 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
4889 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm$lane",
4890 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
4892 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
4893 ValueType ResTy, ValueType OpTy, Operand IdxTy>
4894 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
4895 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm$lane",
4896 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
4897 VectorIndex32:$lane)))]>;
4899 // Inst{19-16} is partially specified depending on the element size.
4901 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8, VectorIndex8> {
4903 let Inst{19-17} = lane{2-0};
4905 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16, VectorIndex16> {
4907 let Inst{19-18} = lane{1-0};
4909 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32, VectorIndex32> {
4911 let Inst{19} = lane{0};
4913 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8, VectorIndex8> {
4915 let Inst{19-17} = lane{2-0};
4917 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16, VectorIndex16> {
4919 let Inst{19-18} = lane{1-0};
4921 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32, VectorIndex32> {
4923 let Inst{19} = lane{0};
4926 def : Pat<(v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
4927 (VDUPLN32d DPR:$Vm, imm:$lane)>;
4929 def : Pat<(v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
4930 (VDUPLN32q DPR:$Vm, imm:$lane)>;
4932 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
4933 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
4934 (DSubReg_i8_reg imm:$lane))),
4935 (SubReg_i8_lane imm:$lane)))>;
4936 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
4937 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
4938 (DSubReg_i16_reg imm:$lane))),
4939 (SubReg_i16_lane imm:$lane)))>;
4940 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
4941 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
4942 (DSubReg_i32_reg imm:$lane))),
4943 (SubReg_i32_lane imm:$lane)))>;
4944 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
4945 (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src,
4946 (DSubReg_i32_reg imm:$lane))),
4947 (SubReg_i32_lane imm:$lane)))>;
4949 def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4950 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
4951 def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4952 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
4954 // VMOVN : Vector Narrowing Move
4955 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
4956 "vmovn", "i", trunc>;
4957 // VQMOVN : Vector Saturating Narrowing Move
4958 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
4959 "vqmovn", "s", int_arm_neon_vqmovns>;
4960 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
4961 "vqmovn", "u", int_arm_neon_vqmovnu>;
4962 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
4963 "vqmovun", "s", int_arm_neon_vqmovnsu>;
4964 // VMOVL : Vector Lengthening Move
4965 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
4966 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
4968 // Vector Conversions.
4970 // VCVT : Vector Convert Between Floating-Point and Integers
4971 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4972 v2i32, v2f32, fp_to_sint>;
4973 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4974 v2i32, v2f32, fp_to_uint>;
4975 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4976 v2f32, v2i32, sint_to_fp>;
4977 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4978 v2f32, v2i32, uint_to_fp>;
4980 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4981 v4i32, v4f32, fp_to_sint>;
4982 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4983 v4i32, v4f32, fp_to_uint>;
4984 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4985 v4f32, v4i32, sint_to_fp>;
4986 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4987 v4f32, v4i32, uint_to_fp>;
4989 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
4990 let DecoderMethod = "DecodeVCVTD" in {
4991 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4992 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
4993 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4994 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
4995 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4996 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
4997 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4998 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
5001 let DecoderMethod = "DecodeVCVTQ" in {
5002 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
5003 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
5004 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
5005 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
5006 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
5007 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
5008 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
5009 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
5012 // VCVT : Vector Convert Between Half-Precision and Single-Precision.
5013 def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
5014 IIC_VUNAQ, "vcvt", "f16.f32",
5015 v4i16, v4f32, int_arm_neon_vcvtfp2hf>,
5016 Requires<[HasNEON, HasFP16]>;
5017 def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
5018 IIC_VUNAQ, "vcvt", "f32.f16",
5019 v4f32, v4i16, int_arm_neon_vcvthf2fp>,
5020 Requires<[HasNEON, HasFP16]>;
5024 // VREV64 : Vector Reverse elements within 64-bit doublewords
5026 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5027 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
5028 (ins DPR:$Vm), IIC_VMOVD,
5029 OpcodeStr, Dt, "$Vd, $Vm", "",
5030 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
5031 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5032 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
5033 (ins QPR:$Vm), IIC_VMOVQ,
5034 OpcodeStr, Dt, "$Vd, $Vm", "",
5035 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
5037 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
5038 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
5039 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
5040 def : Pat<(v2f32 (NEONvrev64 (v2f32 DPR:$Vm))), (VREV64d32 DPR:$Vm)>;
5042 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
5043 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
5044 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
5045 def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>;
5047 // VREV32 : Vector Reverse elements within 32-bit words
5049 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5050 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
5051 (ins DPR:$Vm), IIC_VMOVD,
5052 OpcodeStr, Dt, "$Vd, $Vm", "",
5053 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
5054 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5055 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
5056 (ins QPR:$Vm), IIC_VMOVQ,
5057 OpcodeStr, Dt, "$Vd, $Vm", "",
5058 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
5060 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
5061 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
5063 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
5064 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
5066 // VREV16 : Vector Reverse elements within 16-bit halfwords
5068 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5069 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
5070 (ins DPR:$Vm), IIC_VMOVD,
5071 OpcodeStr, Dt, "$Vd, $Vm", "",
5072 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
5073 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5074 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
5075 (ins QPR:$Vm), IIC_VMOVQ,
5076 OpcodeStr, Dt, "$Vd, $Vm", "",
5077 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
5079 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
5080 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
5082 // Other Vector Shuffles.
5084 // Aligned extractions: really just dropping registers
5086 class AlignedVEXTq<ValueType DestTy, ValueType SrcTy, SDNodeXForm LaneCVT>
5087 : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))),
5088 (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>;
5090 def : AlignedVEXTq<v8i8, v16i8, DSubReg_i8_reg>;
5092 def : AlignedVEXTq<v4i16, v8i16, DSubReg_i16_reg>;
5094 def : AlignedVEXTq<v2i32, v4i32, DSubReg_i32_reg>;
5096 def : AlignedVEXTq<v1i64, v2i64, DSubReg_f64_reg>;
5098 def : AlignedVEXTq<v2f32, v4f32, DSubReg_i32_reg>;
5101 // VEXT : Vector Extract
5103 class VEXTd<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
5104 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
5105 (ins DPR:$Vn, DPR:$Vm, immTy:$index), NVExtFrm,
5106 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
5107 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
5108 (Ty DPR:$Vm), imm:$index)))]> {
5110 let Inst{11-8} = index{3-0};
5113 class VEXTq<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
5114 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
5115 (ins QPR:$Vn, QPR:$Vm, imm0_15:$index), NVExtFrm,
5116 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
5117 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
5118 (Ty QPR:$Vm), imm:$index)))]> {
5120 let Inst{11-8} = index{3-0};
5123 def VEXTd8 : VEXTd<"vext", "8", v8i8, imm0_7> {
5124 let Inst{11-8} = index{3-0};
5126 def VEXTd16 : VEXTd<"vext", "16", v4i16, imm0_3> {
5127 let Inst{11-9} = index{2-0};
5130 def VEXTd32 : VEXTd<"vext", "32", v2i32, imm0_1> {
5131 let Inst{11-10} = index{1-0};
5132 let Inst{9-8} = 0b00;
5134 def : Pat<(v2f32 (NEONvext (v2f32 DPR:$Vn),
5137 (VEXTd32 DPR:$Vn, DPR:$Vm, imm:$index)>;
5139 def VEXTq8 : VEXTq<"vext", "8", v16i8, imm0_15> {
5140 let Inst{11-8} = index{3-0};
5142 def VEXTq16 : VEXTq<"vext", "16", v8i16, imm0_7> {
5143 let Inst{11-9} = index{2-0};
5146 def VEXTq32 : VEXTq<"vext", "32", v4i32, imm0_3> {
5147 let Inst{11-10} = index{1-0};
5148 let Inst{9-8} = 0b00;
5150 def VEXTq64 : VEXTq<"vext", "64", v2i64, imm0_1> {
5151 let Inst{11} = index{0};
5152 let Inst{10-8} = 0b000;
5154 def : Pat<(v4f32 (NEONvext (v4f32 QPR:$Vn),
5157 (VEXTq32 QPR:$Vn, QPR:$Vm, imm:$index)>;
5159 // VTRN : Vector Transpose
5161 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
5162 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
5163 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
5165 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
5166 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
5167 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
5169 // VUZP : Vector Unzip (Deinterleave)
5171 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
5172 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
5173 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
5175 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
5176 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
5177 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
5179 // VZIP : Vector Zip (Interleave)
5181 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
5182 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
5183 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
5185 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
5186 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
5187 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
5189 // Vector Table Lookup and Table Extension.
5191 // VTBL : Vector Table Lookup
5192 let DecoderMethod = "DecodeTBLInstruction" in {
5194 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
5195 (ins VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
5196 "vtbl", "8", "$Vd, $Vn, $Vm", "",
5197 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 VecListOneD:$Vn, DPR:$Vm)))]>;
5198 let hasExtraSrcRegAllocReq = 1 in {
5200 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
5201 (ins VecListTwoD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB2,
5202 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5204 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
5205 (ins VecListThreeD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB3,
5206 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5208 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
5209 (ins VecListFourD:$Vn, DPR:$Vm),
5211 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5212 } // hasExtraSrcRegAllocReq = 1
5215 : PseudoNeonI<(outs DPR:$dst), (ins QPR:$tbl, DPR:$src), IIC_VTB2, "", []>;
5217 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
5219 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
5221 // VTBX : Vector Table Extension
5223 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
5224 (ins DPR:$orig, VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
5225 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd",
5226 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
5227 DPR:$orig, VecListOneD:$Vn, DPR:$Vm)))]>;
5228 let hasExtraSrcRegAllocReq = 1 in {
5230 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
5231 (ins DPR:$orig, VecListTwoD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
5232 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd", []>;
5234 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
5235 (ins DPR:$orig, VecListThreeD:$Vn, DPR:$Vm),
5236 NVTBLFrm, IIC_VTBX3,
5237 "vtbx", "8", "$Vd, $Vn, $Vm",
5240 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd),
5241 (ins DPR:$orig, VecListFourD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
5242 "vtbx", "8", "$Vd, $Vn, $Vm",
5244 } // hasExtraSrcRegAllocReq = 1
5247 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QPR:$tbl, DPR:$src),
5248 IIC_VTBX2, "$orig = $dst", []>;
5250 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
5251 IIC_VTBX3, "$orig = $dst", []>;
5253 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
5254 IIC_VTBX4, "$orig = $dst", []>;
5255 } // DecoderMethod = "DecodeTBLInstruction"
5257 //===----------------------------------------------------------------------===//
5258 // NEON instructions for single-precision FP math
5259 //===----------------------------------------------------------------------===//
5261 class N2VSPat<SDNode OpNode, NeonI Inst>
5262 : NEONFPPat<(f32 (OpNode SPR:$a)),
5264 (v2f32 (COPY_TO_REGCLASS (Inst
5266 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5267 SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>;
5269 class N3VSPat<SDNode OpNode, NeonI Inst>
5270 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
5272 (v2f32 (COPY_TO_REGCLASS (Inst
5274 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5277 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5278 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
5280 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
5281 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
5283 (v2f32 (COPY_TO_REGCLASS (Inst
5285 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5288 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5291 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5292 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
5294 def : N3VSPat<fadd, VADDfd>;
5295 def : N3VSPat<fsub, VSUBfd>;
5296 def : N3VSPat<fmul, VMULfd>;
5297 def : N3VSMulOpPat<fmul, fadd, VMLAfd>,
5298 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
5299 def : N3VSMulOpPat<fmul, fsub, VMLSfd>,
5300 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
5301 def : N2VSPat<fabs, VABSfd>;
5302 def : N2VSPat<fneg, VNEGfd>;
5303 def : N3VSPat<NEONfmax, VMAXfd>;
5304 def : N3VSPat<NEONfmin, VMINfd>;
5305 def : N2VSPat<arm_ftosi, VCVTf2sd>;
5306 def : N2VSPat<arm_ftoui, VCVTf2ud>;
5307 def : N2VSPat<arm_sitof, VCVTs2fd>;
5308 def : N2VSPat<arm_uitof, VCVTu2fd>;
5310 //===----------------------------------------------------------------------===//
5311 // Non-Instruction Patterns
5312 //===----------------------------------------------------------------------===//
5315 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
5316 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
5317 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
5318 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
5319 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
5320 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
5321 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
5322 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
5323 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
5324 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
5325 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
5326 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
5327 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
5328 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
5329 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
5330 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
5331 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
5332 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
5333 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
5334 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
5335 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
5336 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
5337 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
5338 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
5339 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
5340 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
5341 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
5342 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
5343 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
5344 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
5346 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
5347 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
5348 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
5349 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
5350 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
5351 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
5352 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
5353 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
5354 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
5355 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
5356 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
5357 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
5358 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
5359 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
5360 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
5361 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
5362 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
5363 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
5364 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
5365 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
5366 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
5367 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
5368 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
5369 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
5370 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
5371 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
5372 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
5373 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
5374 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
5375 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
5378 //===----------------------------------------------------------------------===//
5379 // Assembler aliases
5382 def : VFP2InstAlias<"fmdhr${p} $Dd, $Rn",
5383 (VSETLNi32 DPR:$Dd, GPR:$Rn, 1, pred:$p)>;
5384 def : VFP2InstAlias<"fmdlr${p} $Dd, $Rn",
5385 (VSETLNi32 DPR:$Dd, GPR:$Rn, 0, pred:$p)>;
5388 // VADD two-operand aliases.
5389 def : NEONInstAlias<"vadd${p}.i8 $Vdn, $Vm",
5390 (VADDv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5391 def : NEONInstAlias<"vadd${p}.i16 $Vdn, $Vm",
5392 (VADDv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5393 def : NEONInstAlias<"vadd${p}.i32 $Vdn, $Vm",
5394 (VADDv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5395 def : NEONInstAlias<"vadd${p}.i64 $Vdn, $Vm",
5396 (VADDv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5398 def : NEONInstAlias<"vadd${p}.i8 $Vdn, $Vm",
5399 (VADDv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5400 def : NEONInstAlias<"vadd${p}.i16 $Vdn, $Vm",
5401 (VADDv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5402 def : NEONInstAlias<"vadd${p}.i32 $Vdn, $Vm",
5403 (VADDv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5404 def : NEONInstAlias<"vadd${p}.i64 $Vdn, $Vm",
5405 (VADDv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5407 def : NEONInstAlias<"vadd${p}.f32 $Vdn, $Vm",
5408 (VADDfd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5409 def : NEONInstAlias<"vadd${p}.f32 $Vdn, $Vm",
5410 (VADDfq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5412 // VSUB two-operand aliases.
5413 def : NEONInstAlias<"vsub${p}.i8 $Vdn, $Vm",
5414 (VSUBv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5415 def : NEONInstAlias<"vsub${p}.i16 $Vdn, $Vm",
5416 (VSUBv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5417 def : NEONInstAlias<"vsub${p}.i32 $Vdn, $Vm",
5418 (VSUBv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5419 def : NEONInstAlias<"vsub${p}.i64 $Vdn, $Vm",
5420 (VSUBv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5422 def : NEONInstAlias<"vsub${p}.i8 $Vdn, $Vm",
5423 (VSUBv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5424 def : NEONInstAlias<"vsub${p}.i16 $Vdn, $Vm",
5425 (VSUBv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5426 def : NEONInstAlias<"vsub${p}.i32 $Vdn, $Vm",
5427 (VSUBv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5428 def : NEONInstAlias<"vsub${p}.i64 $Vdn, $Vm",
5429 (VSUBv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5431 def : NEONInstAlias<"vsub${p}.f32 $Vdn, $Vm",
5432 (VSUBfd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5433 def : NEONInstAlias<"vsub${p}.f32 $Vdn, $Vm",
5434 (VSUBfq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5436 // VADDW two-operand aliases.
5437 def : NEONInstAlias<"vaddw${p}.s8 $Vdn, $Vm",
5438 (VADDWsv8i16 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
5439 def : NEONInstAlias<"vaddw${p}.s16 $Vdn, $Vm",
5440 (VADDWsv4i32 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
5441 def : NEONInstAlias<"vaddw${p}.s32 $Vdn, $Vm",
5442 (VADDWsv2i64 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
5443 def : NEONInstAlias<"vaddw${p}.u8 $Vdn, $Vm",
5444 (VADDWuv8i16 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
5445 def : NEONInstAlias<"vaddw${p}.u16 $Vdn, $Vm",
5446 (VADDWuv4i32 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
5447 def : NEONInstAlias<"vaddw${p}.u32 $Vdn, $Vm",
5448 (VADDWuv2i64 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
5450 // VAND/VBIC/VEOR/VORR accept but do not require a type suffix.
5451 defm : VFPDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
5452 (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
5453 defm : VFPDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
5454 (VANDq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
5455 defm : VFPDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
5456 (VBICd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
5457 defm : VFPDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
5458 (VBICq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
5459 defm : VFPDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
5460 (VEORd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
5461 defm : VFPDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
5462 (VEORq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
5463 defm : VFPDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
5464 (VORRd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
5465 defm : VFPDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
5466 (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
5467 // ... two-operand aliases
5468 def : NEONInstAlias<"vand${p} $Vdn, $Vm",
5469 (VANDd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5470 def : NEONInstAlias<"vand${p} $Vdn, $Vm",
5471 (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5472 def : NEONInstAlias<"vbic${p} $Vdn, $Vm",
5473 (VBICd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5474 def : NEONInstAlias<"vbic${p} $Vdn, $Vm",
5475 (VBICq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5476 def : NEONInstAlias<"veor${p} $Vdn, $Vm",
5477 (VEORd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5478 def : NEONInstAlias<"veor${p} $Vdn, $Vm",
5479 (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5480 def : NEONInstAlias<"vorr${p} $Vdn, $Vm",
5481 (VORRd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5482 def : NEONInstAlias<"vorr${p} $Vdn, $Vm",
5483 (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5485 defm : VFPDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",
5486 (VANDd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5487 defm : VFPDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",
5488 (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5489 defm : VFPDTAnyInstAlias<"veor${p}", "$Vdn, $Vm",
5490 (VEORd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5491 defm : VFPDTAnyInstAlias<"veor${p}", "$Vdn, $Vm",
5492 (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5493 defm : VFPDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
5494 (VORRd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5495 defm : VFPDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
5496 (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5498 // VMUL two-operand aliases.
5499 def : NEONInstAlias<"vmul${p}.p8 $Qdn, $Qm",
5500 (VMULpq QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>;
5501 def : NEONInstAlias<"vmul${p}.i8 $Qdn, $Qm",
5502 (VMULv16i8 QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>;
5503 def : NEONInstAlias<"vmul${p}.i16 $Qdn, $Qm",
5504 (VMULv8i16 QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>;
5505 def : NEONInstAlias<"vmul${p}.i32 $Qdn, $Qm",
5506 (VMULv4i32 QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>;
5508 def : NEONInstAlias<"vmul${p}.p8 $Ddn, $Dm",
5509 (VMULpd DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>;
5510 def : NEONInstAlias<"vmul${p}.i8 $Ddn, $Dm",
5511 (VMULv8i8 DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>;
5512 def : NEONInstAlias<"vmul${p}.i16 $Ddn, $Dm",
5513 (VMULv4i16 DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>;
5514 def : NEONInstAlias<"vmul${p}.i32 $Ddn, $Dm",
5515 (VMULv2i32 DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>;
5517 def : NEONInstAlias<"vmul${p}.f32 $Qdn, $Qm",
5518 (VMULfq QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>;
5519 def : NEONInstAlias<"vmul${p}.f32 $Ddn, $Dm",
5520 (VMULfd DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>;
5522 def : NEONInstAlias<"vmul${p}.i16 $Ddn, $Dm$lane",
5523 (VMULslv4i16 DPR:$Ddn, DPR:$Ddn, DPR_8:$Dm,
5524 VectorIndex16:$lane, pred:$p)>;
5525 def : NEONInstAlias<"vmul${p}.i16 $Qdn, $Dm$lane",
5526 (VMULslv8i16 QPR:$Qdn, QPR:$Qdn, DPR_8:$Dm,
5527 VectorIndex16:$lane, pred:$p)>;
5529 def : NEONInstAlias<"vmul${p}.i32 $Ddn, $Dm$lane",
5530 (VMULslv2i32 DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm,
5531 VectorIndex32:$lane, pred:$p)>;
5532 def : NEONInstAlias<"vmul${p}.i32 $Qdn, $Dm$lane",
5533 (VMULslv4i32 QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm,
5534 VectorIndex32:$lane, pred:$p)>;
5536 def : NEONInstAlias<"vmul${p}.f32 $Ddn, $Dm$lane",
5537 (VMULslfd DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm,
5538 VectorIndex32:$lane, pred:$p)>;
5539 def : NEONInstAlias<"vmul${p}.f32 $Qdn, $Dm$lane",
5540 (VMULslfq QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm,
5541 VectorIndex32:$lane, pred:$p)>;
5543 // VQADD (register) two-operand aliases.
5544 def : NEONInstAlias<"vqadd${p}.s8 $Vdn, $Vm",
5545 (VQADDsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5546 def : NEONInstAlias<"vqadd${p}.s16 $Vdn, $Vm",
5547 (VQADDsv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5548 def : NEONInstAlias<"vqadd${p}.s32 $Vdn, $Vm",
5549 (VQADDsv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5550 def : NEONInstAlias<"vqadd${p}.s64 $Vdn, $Vm",
5551 (VQADDsv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5552 def : NEONInstAlias<"vqadd${p}.u8 $Vdn, $Vm",
5553 (VQADDuv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5554 def : NEONInstAlias<"vqadd${p}.u16 $Vdn, $Vm",
5555 (VQADDuv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5556 def : NEONInstAlias<"vqadd${p}.u32 $Vdn, $Vm",
5557 (VQADDuv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5558 def : NEONInstAlias<"vqadd${p}.u64 $Vdn, $Vm",
5559 (VQADDuv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5561 def : NEONInstAlias<"vqadd${p}.s8 $Vdn, $Vm",
5562 (VQADDsv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5563 def : NEONInstAlias<"vqadd${p}.s16 $Vdn, $Vm",
5564 (VQADDsv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5565 def : NEONInstAlias<"vqadd${p}.s32 $Vdn, $Vm",
5566 (VQADDsv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5567 def : NEONInstAlias<"vqadd${p}.s64 $Vdn, $Vm",
5568 (VQADDsv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5569 def : NEONInstAlias<"vqadd${p}.u8 $Vdn, $Vm",
5570 (VQADDuv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5571 def : NEONInstAlias<"vqadd${p}.u16 $Vdn, $Vm",
5572 (VQADDuv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5573 def : NEONInstAlias<"vqadd${p}.u32 $Vdn, $Vm",
5574 (VQADDuv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5575 def : NEONInstAlias<"vqadd${p}.u64 $Vdn, $Vm",
5576 (VQADDuv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5578 // VSHL (immediate) two-operand aliases.
5579 def : NEONInstAlias<"vshl${p}.i8 $Vdn, $imm",
5580 (VSHLiv8i8 DPR:$Vdn, DPR:$Vdn, imm0_7:$imm, pred:$p)>;
5581 def : NEONInstAlias<"vshl${p}.i16 $Vdn, $imm",
5582 (VSHLiv4i16 DPR:$Vdn, DPR:$Vdn, imm0_15:$imm, pred:$p)>;
5583 def : NEONInstAlias<"vshl${p}.i32 $Vdn, $imm",
5584 (VSHLiv2i32 DPR:$Vdn, DPR:$Vdn, imm0_31:$imm, pred:$p)>;
5585 def : NEONInstAlias<"vshl${p}.i64 $Vdn, $imm",
5586 (VSHLiv1i64 DPR:$Vdn, DPR:$Vdn, imm0_63:$imm, pred:$p)>;
5588 def : NEONInstAlias<"vshl${p}.i8 $Vdn, $imm",
5589 (VSHLiv16i8 QPR:$Vdn, QPR:$Vdn, imm0_7:$imm, pred:$p)>;
5590 def : NEONInstAlias<"vshl${p}.i16 $Vdn, $imm",
5591 (VSHLiv8i16 QPR:$Vdn, QPR:$Vdn, imm0_15:$imm, pred:$p)>;
5592 def : NEONInstAlias<"vshl${p}.i32 $Vdn, $imm",
5593 (VSHLiv4i32 QPR:$Vdn, QPR:$Vdn, imm0_31:$imm, pred:$p)>;
5594 def : NEONInstAlias<"vshl${p}.i64 $Vdn, $imm",
5595 (VSHLiv2i64 QPR:$Vdn, QPR:$Vdn, imm0_63:$imm, pred:$p)>;
5597 // VSHL (register) two-operand aliases.
5598 def : NEONInstAlias<"vshl${p}.s8 $Vdn, $Vm",
5599 (VSHLsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5600 def : NEONInstAlias<"vshl${p}.s16 $Vdn, $Vm",
5601 (VSHLsv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5602 def : NEONInstAlias<"vshl${p}.s32 $Vdn, $Vm",
5603 (VSHLsv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5604 def : NEONInstAlias<"vshl${p}.s64 $Vdn, $Vm",
5605 (VSHLsv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5606 def : NEONInstAlias<"vshl${p}.u8 $Vdn, $Vm",
5607 (VSHLuv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5608 def : NEONInstAlias<"vshl${p}.u16 $Vdn, $Vm",
5609 (VSHLuv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5610 def : NEONInstAlias<"vshl${p}.u32 $Vdn, $Vm",
5611 (VSHLuv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5612 def : NEONInstAlias<"vshl${p}.u64 $Vdn, $Vm",
5613 (VSHLuv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5615 def : NEONInstAlias<"vshl${p}.s8 $Vdn, $Vm",
5616 (VSHLsv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5617 def : NEONInstAlias<"vshl${p}.s16 $Vdn, $Vm",
5618 (VSHLsv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5619 def : NEONInstAlias<"vshl${p}.s32 $Vdn, $Vm",
5620 (VSHLsv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5621 def : NEONInstAlias<"vshl${p}.s64 $Vdn, $Vm",
5622 (VSHLsv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5623 def : NEONInstAlias<"vshl${p}.u8 $Vdn, $Vm",
5624 (VSHLuv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5625 def : NEONInstAlias<"vshl${p}.u16 $Vdn, $Vm",
5626 (VSHLuv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5627 def : NEONInstAlias<"vshl${p}.u32 $Vdn, $Vm",
5628 (VSHLuv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5629 def : NEONInstAlias<"vshl${p}.u64 $Vdn, $Vm",
5630 (VSHLuv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5632 // VSHL (immediate) two-operand aliases.
5633 def : NEONInstAlias<"vshr${p}.s8 $Vdn, $imm",
5634 (VSHRsv8i8 DPR:$Vdn, DPR:$Vdn, shr_imm8:$imm, pred:$p)>;
5635 def : NEONInstAlias<"vshr${p}.s16 $Vdn, $imm",
5636 (VSHRsv4i16 DPR:$Vdn, DPR:$Vdn, shr_imm16:$imm, pred:$p)>;
5637 def : NEONInstAlias<"vshr${p}.s32 $Vdn, $imm",
5638 (VSHRsv2i32 DPR:$Vdn, DPR:$Vdn, shr_imm32:$imm, pred:$p)>;
5639 def : NEONInstAlias<"vshr${p}.s64 $Vdn, $imm",
5640 (VSHRsv1i64 DPR:$Vdn, DPR:$Vdn, shr_imm64:$imm, pred:$p)>;
5642 def : NEONInstAlias<"vshr${p}.s8 $Vdn, $imm",
5643 (VSHRsv16i8 QPR:$Vdn, QPR:$Vdn, shr_imm8:$imm, pred:$p)>;
5644 def : NEONInstAlias<"vshr${p}.s16 $Vdn, $imm",
5645 (VSHRsv8i16 QPR:$Vdn, QPR:$Vdn, shr_imm16:$imm, pred:$p)>;
5646 def : NEONInstAlias<"vshr${p}.s32 $Vdn, $imm",
5647 (VSHRsv4i32 QPR:$Vdn, QPR:$Vdn, shr_imm32:$imm, pred:$p)>;
5648 def : NEONInstAlias<"vshr${p}.s64 $Vdn, $imm",
5649 (VSHRsv2i64 QPR:$Vdn, QPR:$Vdn, shr_imm64:$imm, pred:$p)>;
5651 def : NEONInstAlias<"vshr${p}.u8 $Vdn, $imm",
5652 (VSHRuv8i8 DPR:$Vdn, DPR:$Vdn, shr_imm8:$imm, pred:$p)>;
5653 def : NEONInstAlias<"vshr${p}.u16 $Vdn, $imm",
5654 (VSHRuv4i16 DPR:$Vdn, DPR:$Vdn, shr_imm16:$imm, pred:$p)>;
5655 def : NEONInstAlias<"vshr${p}.u32 $Vdn, $imm",
5656 (VSHRuv2i32 DPR:$Vdn, DPR:$Vdn, shr_imm32:$imm, pred:$p)>;
5657 def : NEONInstAlias<"vshr${p}.u64 $Vdn, $imm",
5658 (VSHRuv1i64 DPR:$Vdn, DPR:$Vdn, shr_imm64:$imm, pred:$p)>;
5660 def : NEONInstAlias<"vshr${p}.u8 $Vdn, $imm",
5661 (VSHRuv16i8 QPR:$Vdn, QPR:$Vdn, shr_imm8:$imm, pred:$p)>;
5662 def : NEONInstAlias<"vshr${p}.u16 $Vdn, $imm",
5663 (VSHRuv8i16 QPR:$Vdn, QPR:$Vdn, shr_imm16:$imm, pred:$p)>;
5664 def : NEONInstAlias<"vshr${p}.u32 $Vdn, $imm",
5665 (VSHRuv4i32 QPR:$Vdn, QPR:$Vdn, shr_imm32:$imm, pred:$p)>;
5666 def : NEONInstAlias<"vshr${p}.u64 $Vdn, $imm",
5667 (VSHRuv2i64 QPR:$Vdn, QPR:$Vdn, shr_imm64:$imm, pred:$p)>;
5669 // VLD1 single-lane pseudo-instructions. These need special handling for
5670 // the lane index that an InstAlias can't handle, so we use these instead.
5671 defm VLD1LNdAsm : NEONDT8AsmPseudoInst<"vld1${p}", "$list, $addr",
5672 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5673 defm VLD1LNdAsm : NEONDT16AsmPseudoInst<"vld1${p}", "$list, $addr",
5674 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5675 defm VLD1LNdAsm : NEONDT32AsmPseudoInst<"vld1${p}", "$list, $addr",
5676 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5678 defm VLD1LNdWB_fixed_Asm : NEONDT8AsmPseudoInst<"vld1${p}", "$list, $addr!",
5679 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5680 defm VLD1LNdWB_fixed_Asm : NEONDT16AsmPseudoInst<"vld1${p}", "$list, $addr!",
5681 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5682 defm VLD1LNdWB_fixed_Asm : NEONDT32AsmPseudoInst<"vld1${p}", "$list, $addr!",
5683 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5684 defm VLD1LNdWB_register_Asm :
5685 NEONDT8AsmPseudoInst<"vld1${p}", "$list, $addr, $Rm",
5686 (ins VecListOneDByteIndexed:$list, addrmode6:$addr,
5687 rGPR:$Rm, pred:$p)>;
5688 defm VLD1LNdWB_register_Asm :
5689 NEONDT16AsmPseudoInst<"vld1${p}", "$list, $addr, $Rm",
5690 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr,
5691 rGPR:$Rm, pred:$p)>;
5692 defm VLD1LNdWB_register_Asm :
5693 NEONDT32AsmPseudoInst<"vld1${p}", "$list, $addr, $Rm",
5694 (ins VecListOneDWordIndexed:$list, addrmode6:$addr,
5695 rGPR:$Rm, pred:$p)>;
5698 // VST1 single-lane pseudo-instructions. These need special handling for
5699 // the lane index that an InstAlias can't handle, so we use these instead.
5700 defm VST1LNdAsm : NEONDT8AsmPseudoInst<"vst1${p}", "$list, $addr",
5701 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5702 defm VST1LNdAsm : NEONDT16AsmPseudoInst<"vst1${p}", "$list, $addr",
5703 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5704 defm VST1LNdAsm : NEONDT32AsmPseudoInst<"vst1${p}", "$list, $addr",
5705 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5707 defm VST1LNdWB_fixed_Asm : NEONDT8AsmPseudoInst<"vst1${p}", "$list, $addr!",
5708 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5709 defm VST1LNdWB_fixed_Asm : NEONDT16AsmPseudoInst<"vst1${p}", "$list, $addr!",
5710 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5711 defm VST1LNdWB_fixed_Asm : NEONDT32AsmPseudoInst<"vst1${p}", "$list, $addr!",
5712 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5713 defm VST1LNdWB_register_Asm :
5714 NEONDT8AsmPseudoInst<"vst1${p}", "$list, $addr, $Rm",
5715 (ins VecListOneDByteIndexed:$list, addrmode6:$addr,
5716 rGPR:$Rm, pred:$p)>;
5717 defm VST1LNdWB_register_Asm :
5718 NEONDT16AsmPseudoInst<"vst1${p}", "$list, $addr, $Rm",
5719 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr,
5720 rGPR:$Rm, pred:$p)>;
5721 defm VST1LNdWB_register_Asm :
5722 NEONDT32AsmPseudoInst<"vst1${p}", "$list, $addr, $Rm",
5723 (ins VecListOneDWordIndexed:$list, addrmode6:$addr,
5724 rGPR:$Rm, pred:$p)>;
5726 // VLD2 single-lane pseudo-instructions. These need special handling for
5727 // the lane index that an InstAlias can't handle, so we use these instead.
5728 defm VLD2LNdAsm : NEONDT8AsmPseudoInst<"vld2${p}", "$list, $addr",
5729 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5730 defm VLD2LNdAsm : NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr",
5731 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5732 defm VLD2LNdAsm : NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr",
5733 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5735 defm VLD2LNdWB_fixed_Asm : NEONDT8AsmPseudoInst<"vld2${p}", "$list, $addr!",
5736 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5737 defm VLD2LNdWB_fixed_Asm : NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr!",
5738 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5739 defm VLD2LNdWB_fixed_Asm : NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr!",
5740 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5741 defm VLD2LNdWB_register_Asm :
5742 NEONDT8AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm",
5743 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr,
5744 rGPR:$Rm, pred:$p)>;
5745 defm VLD2LNdWB_register_Asm :
5746 NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm",
5747 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr,
5748 rGPR:$Rm, pred:$p)>;
5749 defm VLD2LNdWB_register_Asm :
5750 NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm",
5751 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr,
5752 rGPR:$Rm, pred:$p)>;
5755 // VST2 single-lane pseudo-instructions. These need special handling for
5756 // the lane index that an InstAlias can't handle, so we use these instead.
5757 defm VST2LNdAsm : NEONDT8AsmPseudoInst<"vst2${p}", "$list, $addr",
5758 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5759 defm VST2LNdAsm : NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr",
5760 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5761 defm VST2LNdAsm : NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr",
5762 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5764 defm VST2LNdWB_fixed_Asm : NEONDT8AsmPseudoInst<"vst2${p}", "$list, $addr!",
5765 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5766 defm VST2LNdWB_fixed_Asm : NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr!",
5767 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5768 defm VST2LNdWB_fixed_Asm : NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr!",
5769 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5770 defm VST2LNdWB_register_Asm :
5771 NEONDT8AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm",
5772 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr,
5773 rGPR:$Rm, pred:$p)>;
5774 defm VST2LNdWB_register_Asm :
5775 NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm",
5776 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr,
5777 rGPR:$Rm, pred:$p)>;
5778 defm VST2LNdWB_register_Asm :
5779 NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm",
5780 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr,
5781 rGPR:$Rm, pred:$p)>;
5783 // VMOV takes an optional datatype suffix
5784 defm : VFPDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
5785 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
5786 defm : VFPDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
5787 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
5789 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
5790 // D-register versions.
5791 def : NEONInstAlias<"vcle${p}.s8 $Dd, $Dn, $Dm",
5792 (VCGEsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5793 def : NEONInstAlias<"vcle${p}.s16 $Dd, $Dn, $Dm",
5794 (VCGEsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5795 def : NEONInstAlias<"vcle${p}.s32 $Dd, $Dn, $Dm",
5796 (VCGEsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5797 def : NEONInstAlias<"vcle${p}.u8 $Dd, $Dn, $Dm",
5798 (VCGEuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5799 def : NEONInstAlias<"vcle${p}.u16 $Dd, $Dn, $Dm",
5800 (VCGEuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5801 def : NEONInstAlias<"vcle${p}.u32 $Dd, $Dn, $Dm",
5802 (VCGEuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5803 def : NEONInstAlias<"vcle${p}.f32 $Dd, $Dn, $Dm",
5804 (VCGEfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5805 // Q-register versions.
5806 def : NEONInstAlias<"vcle${p}.s8 $Qd, $Qn, $Qm",
5807 (VCGEsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5808 def : NEONInstAlias<"vcle${p}.s16 $Qd, $Qn, $Qm",
5809 (VCGEsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5810 def : NEONInstAlias<"vcle${p}.s32 $Qd, $Qn, $Qm",
5811 (VCGEsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5812 def : NEONInstAlias<"vcle${p}.u8 $Qd, $Qn, $Qm",
5813 (VCGEuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5814 def : NEONInstAlias<"vcle${p}.u16 $Qd, $Qn, $Qm",
5815 (VCGEuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5816 def : NEONInstAlias<"vcle${p}.u32 $Qd, $Qn, $Qm",
5817 (VCGEuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5818 def : NEONInstAlias<"vcle${p}.f32 $Qd, $Qn, $Qm",
5819 (VCGEfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5821 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
5822 // D-register versions.
5823 def : NEONInstAlias<"vclt${p}.s8 $Dd, $Dn, $Dm",
5824 (VCGTsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5825 def : NEONInstAlias<"vclt${p}.s16 $Dd, $Dn, $Dm",
5826 (VCGTsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5827 def : NEONInstAlias<"vclt${p}.s32 $Dd, $Dn, $Dm",
5828 (VCGTsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5829 def : NEONInstAlias<"vclt${p}.u8 $Dd, $Dn, $Dm",
5830 (VCGTuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5831 def : NEONInstAlias<"vclt${p}.u16 $Dd, $Dn, $Dm",
5832 (VCGTuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5833 def : NEONInstAlias<"vclt${p}.u32 $Dd, $Dn, $Dm",
5834 (VCGTuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5835 def : NEONInstAlias<"vclt${p}.f32 $Dd, $Dn, $Dm",
5836 (VCGTfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5837 // Q-register versions.
5838 def : NEONInstAlias<"vclt${p}.s8 $Qd, $Qn, $Qm",
5839 (VCGTsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5840 def : NEONInstAlias<"vclt${p}.s16 $Qd, $Qn, $Qm",
5841 (VCGTsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5842 def : NEONInstAlias<"vclt${p}.s32 $Qd, $Qn, $Qm",
5843 (VCGTsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5844 def : NEONInstAlias<"vclt${p}.u8 $Qd, $Qn, $Qm",
5845 (VCGTuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5846 def : NEONInstAlias<"vclt${p}.u16 $Qd, $Qn, $Qm",
5847 (VCGTuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5848 def : NEONInstAlias<"vclt${p}.u32 $Qd, $Qn, $Qm",
5849 (VCGTuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5850 def : NEONInstAlias<"vclt${p}.f32 $Qd, $Qn, $Qm",
5851 (VCGTfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5853 // Two-operand variants for VEXT
5854 def : NEONInstAlias<"vext${p}.8 $Vdn, $Vm, $imm",
5855 (VEXTd8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_7:$imm, pred:$p)>;
5856 def : NEONInstAlias<"vext${p}.16 $Vdn, $Vm, $imm",
5857 (VEXTd16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_3:$imm, pred:$p)>;
5858 def : NEONInstAlias<"vext${p}.32 $Vdn, $Vm, $imm",
5859 (VEXTd32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_1:$imm, pred:$p)>;
5861 def : NEONInstAlias<"vext${p}.8 $Vdn, $Vm, $imm",
5862 (VEXTq8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_15:$imm, pred:$p)>;
5863 def : NEONInstAlias<"vext${p}.16 $Vdn, $Vm, $imm",
5864 (VEXTq16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_7:$imm, pred:$p)>;
5865 def : NEONInstAlias<"vext${p}.32 $Vdn, $Vm, $imm",
5866 (VEXTq32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_3:$imm, pred:$p)>;
5867 def : NEONInstAlias<"vext${p}.64 $Vdn, $Vm, $imm",
5868 (VEXTq64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_1:$imm, pred:$p)>;
5870 // Two-operand variants for VQDMULH
5871 def : NEONInstAlias<"vqdmulh${p}.s16 $Vdn, $Vm",
5872 (VQDMULHv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5873 def : NEONInstAlias<"vqdmulh${p}.s32 $Vdn, $Vm",
5874 (VQDMULHv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5876 def : NEONInstAlias<"vqdmulh${p}.s16 $Vdn, $Vm",
5877 (VQDMULHv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5878 def : NEONInstAlias<"vqdmulh${p}.s32 $Vdn, $Vm",
5879 (VQDMULHv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5881 // 'gas' compatibility aliases for quad-word instructions. Strictly speaking,
5882 // these should restrict to just the Q register variants, but the register
5883 // classes are enough to match correctly regardless, so we keep it simple
5884 // and just use MnemonicAlias.
5885 def : NEONMnemonicAlias<"vbicq", "vbic">;
5886 def : NEONMnemonicAlias<"vandq", "vand">;
5887 def : NEONMnemonicAlias<"veorq", "veor">;
5888 def : NEONMnemonicAlias<"vorrq", "vorr">;
5890 def : NEONMnemonicAlias<"vmovq", "vmov">;
5891 def : NEONMnemonicAlias<"vmvnq", "vmvn">;
5892 // Explicit versions for floating point so that the FPImm variants get
5893 // handled early. The parser gets confused otherwise.
5894 def : NEONMnemonicAlias<"vmovq.f32", "vmov.f32">;
5895 def : NEONMnemonicAlias<"vmovq.f64", "vmov.f64">;
5897 def : NEONMnemonicAlias<"vaddq", "vadd">;
5898 def : NEONMnemonicAlias<"vsubq", "vsub">;
5900 def : NEONMnemonicAlias<"vminq", "vmin">;
5901 def : NEONMnemonicAlias<"vmaxq", "vmax">;
5903 def : NEONMnemonicAlias<"vmulq", "vmul">;
5905 def : NEONMnemonicAlias<"vabsq", "vabs">;
5907 def : NEONMnemonicAlias<"vshlq", "vshl">;
5908 def : NEONMnemonicAlias<"vshrq", "vshr">;
5910 def : NEONMnemonicAlias<"vcvtq", "vcvt">;
5912 def : NEONMnemonicAlias<"vcleq", "vcle">;
5913 def : NEONMnemonicAlias<"vceqq", "vceq">;