1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
70 // VDUPLANE can produce a quad-register result from a double-register source,
71 // so the result is not constrained to match the source.
72 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
73 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
76 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
77 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
78 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
80 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
81 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
82 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
83 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
85 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
88 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
89 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
90 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
92 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
94 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
95 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
97 //===----------------------------------------------------------------------===//
98 // NEON operand definitions
99 //===----------------------------------------------------------------------===//
101 def h8imm : Operand<i8> {
102 let PrintMethod = "printHex8ImmOperand";
104 def h16imm : Operand<i16> {
105 let PrintMethod = "printHex16ImmOperand";
107 def h32imm : Operand<i32> {
108 let PrintMethod = "printHex32ImmOperand";
110 def h64imm : Operand<i64> {
111 let PrintMethod = "printHex64ImmOperand";
114 //===----------------------------------------------------------------------===//
115 // NEON load / store instructions
116 //===----------------------------------------------------------------------===//
119 // Use vldmia to load a Q register as a D register pair.
120 // This is equivalent to VLDMD except that it has a Q register operand
121 // instead of a pair of D registers.
123 : AXDI5<(outs QPR:$dst), (ins addrmode5:$addr, pred:$p),
124 IndexModeNone, IIC_fpLoadm,
125 "vldm${addr:submode}${p}\t${addr:base}, ${dst:dregpair}", "", []>;
127 : AXDI5<(outs QPR:$dst, GPR:$wb), (ins addrmode5:$addr, pred:$p),
128 IndexModeUpd, IIC_fpLoadm,
129 "vldm${addr:submode}${p}\t${addr:base}!, ${dst:dregpair}",
130 "$addr.base = $wb", []>;
132 // Use vld1 to load a Q register as a D register pair.
133 // This alternative to VLDMQ allows an alignment to be specified.
134 // This is equivalent to VLD1q64 except that it has a Q register operand.
136 : NLdSt<0,0b10,0b1010,0b1100, (outs QPR:$dst), (ins addrmode6:$addr),
137 IIC_VLD1, "vld1", "64", "${dst:dregpair}, $addr", "", []>;
139 : NLdSt<0,0b10,0b1010,0b1100, (outs QPR:$dst, GPR:$wb),
140 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1, "vld1", "64",
141 "${dst:dregpair}, $addr$offset", "$addr.addr = $wb", []>;
144 let mayStore = 1 in {
145 // Use vstmia to store a Q register as a D register pair.
146 // This is equivalent to VSTMD except that it has a Q register operand
147 // instead of a pair of D registers.
149 : AXDI5<(outs), (ins QPR:$src, addrmode5:$addr, pred:$p),
150 IndexModeNone, IIC_fpStorem,
151 "vstm${addr:submode}${p}\t${addr:base}, ${src:dregpair}", "", []>;
153 : AXDI5<(outs GPR:$wb), (ins QPR:$src, addrmode5:$addr, pred:$p),
154 IndexModeUpd, IIC_fpStorem,
155 "vstm${addr:submode}${p}\t${addr:base}!, ${src:dregpair}",
156 "$addr.base = $wb", []>;
158 // Use vst1 to store a Q register as a D register pair.
159 // This alternative to VSTMQ allows an alignment to be specified.
160 // This is equivalent to VST1q64 except that it has a Q register operand.
162 : NLdSt<0,0b00,0b1010,0b1100, (outs), (ins addrmode6:$addr, QPR:$src),
163 IIC_VST, "vst1", "64", "${src:dregpair}, $addr", "", []>;
165 : NLdSt<0,0b00,0b1010,0b1100, (outs GPR:$wb),
166 (ins addrmode6:$addr, am6offset:$offset, QPR:$src),
167 IIC_VST, "vst1", "64", "{$src:dregpair}, $addr$offset",
168 "$addr.addr = $wb", []>;
171 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
173 // VLD1 : Vector Load (multiple single elements)
174 class VLD1D<bits<4> op7_4, string Dt>
175 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst),
176 (ins addrmode6:$addr), IIC_VLD1,
177 "vld1", Dt, "\\{$dst\\}, $addr", "", []>;
178 class VLD1Q<bits<4> op7_4, string Dt>
179 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$dst1, DPR:$dst2),
180 (ins addrmode6:$addr), IIC_VLD1,
181 "vld1", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>;
183 def VLD1d8 : VLD1D<0b0000, "8">;
184 def VLD1d16 : VLD1D<0b0100, "16">;
185 def VLD1d32 : VLD1D<0b1000, "32">;
186 def VLD1d64 : VLD1D<0b1100, "64">;
188 def VLD1q8 : VLD1Q<0b0000, "8">;
189 def VLD1q16 : VLD1Q<0b0100, "16">;
190 def VLD1q32 : VLD1Q<0b1000, "32">;
191 def VLD1q64 : VLD1Q<0b1100, "64">;
193 // ...with address register writeback:
194 class VLD1DWB<bits<4> op7_4, string Dt>
195 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst, GPR:$wb),
196 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1,
197 "vld1", Dt, "\\{$dst\\}, $addr$offset",
198 "$addr.addr = $wb", []>;
199 class VLD1QWB<bits<4> op7_4, string Dt>
200 : NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst, GPR:$wb),
201 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1,
202 "vld1", Dt, "${dst:dregpair}, $addr$offset",
203 "$addr.addr = $wb", []>;
205 def VLD1d8_UPD : VLD1DWB<0b0000, "8">;
206 def VLD1d16_UPD : VLD1DWB<0b0100, "16">;
207 def VLD1d32_UPD : VLD1DWB<0b1000, "32">;
208 def VLD1d64_UPD : VLD1DWB<0b1100, "64">;
210 def VLD1q8_UPD : VLD1QWB<0b0000, "8">;
211 def VLD1q16_UPD : VLD1QWB<0b0100, "16">;
212 def VLD1q32_UPD : VLD1QWB<0b1000, "32">;
213 def VLD1q64_UPD : VLD1QWB<0b1100, "64">;
215 // ...with 3 registers (some of these are only for the disassembler):
216 class VLD1D3<bits<4> op7_4, string Dt>
217 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
218 (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
219 "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
220 class VLD1D3WB<bits<4> op7_4, string Dt>
221 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
222 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1, "vld1", Dt,
223 "\\{$dst1, $dst2, $dst3\\}, $addr$offset", "$addr.addr = $wb", []>;
225 def VLD1d8T : VLD1D3<0b0000, "8">;
226 def VLD1d16T : VLD1D3<0b0100, "16">;
227 def VLD1d32T : VLD1D3<0b1000, "32">;
228 def VLD1d64T : VLD1D3<0b1100, "64">;
230 def VLD1d8T_UPD : VLD1D3WB<0b0000, "8">;
231 def VLD1d16T_UPD : VLD1D3WB<0b0100, "16">;
232 def VLD1d32T_UPD : VLD1D3WB<0b1000, "32">;
233 def VLD1d64T_UPD : VLD1D3WB<0b1100, "64">;
235 // ...with 4 registers (some of these are only for the disassembler):
236 class VLD1D4<bits<4> op7_4, string Dt>
237 : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
238 (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
239 "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
240 class VLD1D4WB<bits<4> op7_4, string Dt>
241 : NLdSt<0,0b10,0b0010,op7_4,
242 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
243 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1, "vld1", Dt,
244 "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset", "$addr.addr = $wb",
247 def VLD1d8Q : VLD1D4<0b0000, "8">;
248 def VLD1d16Q : VLD1D4<0b0100, "16">;
249 def VLD1d32Q : VLD1D4<0b1000, "32">;
250 def VLD1d64Q : VLD1D4<0b1100, "64">;
252 def VLD1d8Q_UPD : VLD1D4WB<0b0000, "8">;
253 def VLD1d16Q_UPD : VLD1D4WB<0b0100, "16">;
254 def VLD1d32Q_UPD : VLD1D4WB<0b1000, "32">;
255 def VLD1d64Q_UPD : VLD1D4WB<0b1100, "64">;
257 // VLD2 : Vector Load (multiple 2-element structures)
258 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
259 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2),
260 (ins addrmode6:$addr), IIC_VLD2,
261 "vld2", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>;
262 class VLD2Q<bits<4> op7_4, string Dt>
263 : NLdSt<0, 0b10, 0b0011, op7_4,
264 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
265 (ins addrmode6:$addr), IIC_VLD2,
266 "vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
268 def VLD2d8 : VLD2D<0b1000, 0b0000, "8">;
269 def VLD2d16 : VLD2D<0b1000, 0b0100, "16">;
270 def VLD2d32 : VLD2D<0b1000, 0b1000, "32">;
272 def VLD2q8 : VLD2Q<0b0000, "8">;
273 def VLD2q16 : VLD2Q<0b0100, "16">;
274 def VLD2q32 : VLD2Q<0b1000, "32">;
276 // ...with address register writeback:
277 class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
278 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
279 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2,
280 "vld2", Dt, "\\{$dst1, $dst2\\}, $addr$offset",
281 "$addr.addr = $wb", []>;
282 class VLD2QWB<bits<4> op7_4, string Dt>
283 : NLdSt<0, 0b10, 0b0011, op7_4,
284 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
285 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2,
286 "vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset",
287 "$addr.addr = $wb", []>;
289 def VLD2d8_UPD : VLD2DWB<0b1000, 0b0000, "8">;
290 def VLD2d16_UPD : VLD2DWB<0b1000, 0b0100, "16">;
291 def VLD2d32_UPD : VLD2DWB<0b1000, 0b1000, "32">;
293 def VLD2q8_UPD : VLD2QWB<0b0000, "8">;
294 def VLD2q16_UPD : VLD2QWB<0b0100, "16">;
295 def VLD2q32_UPD : VLD2QWB<0b1000, "32">;
297 // ...with double-spaced registers (for disassembly only):
298 def VLD2b8 : VLD2D<0b1001, 0b0000, "8">;
299 def VLD2b16 : VLD2D<0b1001, 0b0100, "16">;
300 def VLD2b32 : VLD2D<0b1001, 0b1000, "32">;
301 def VLD2b8_UPD : VLD2DWB<0b1001, 0b0000, "8">;
302 def VLD2b16_UPD : VLD2DWB<0b1001, 0b0100, "16">;
303 def VLD2b32_UPD : VLD2DWB<0b1001, 0b1000, "32">;
305 // VLD3 : Vector Load (multiple 3-element structures)
306 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
307 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
308 (ins addrmode6:$addr), IIC_VLD3,
309 "vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
311 def VLD3d8 : VLD3D<0b0100, 0b0000, "8">;
312 def VLD3d16 : VLD3D<0b0100, 0b0100, "16">;
313 def VLD3d32 : VLD3D<0b0100, 0b1000, "32">;
315 // ...with address register writeback:
316 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
317 : NLdSt<0, 0b10, op11_8, op7_4,
318 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
319 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD3,
320 "vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr$offset",
321 "$addr.addr = $wb", []>;
323 def VLD3d8_UPD : VLD3DWB<0b0100, 0b0000, "8">;
324 def VLD3d16_UPD : VLD3DWB<0b0100, 0b0100, "16">;
325 def VLD3d32_UPD : VLD3DWB<0b0100, 0b1000, "32">;
327 // ...with double-spaced registers (non-updating versions for disassembly only):
328 def VLD3q8 : VLD3D<0b0101, 0b0000, "8">;
329 def VLD3q16 : VLD3D<0b0101, 0b0100, "16">;
330 def VLD3q32 : VLD3D<0b0101, 0b1000, "32">;
331 def VLD3q8_UPD : VLD3DWB<0b0101, 0b0000, "8">;
332 def VLD3q16_UPD : VLD3DWB<0b0101, 0b0100, "16">;
333 def VLD3q32_UPD : VLD3DWB<0b0101, 0b1000, "32">;
335 // ...alternate versions to be allocated odd register numbers:
336 def VLD3q8odd_UPD : VLD3DWB<0b0101, 0b0000, "8">;
337 def VLD3q16odd_UPD : VLD3DWB<0b0101, 0b0100, "16">;
338 def VLD3q32odd_UPD : VLD3DWB<0b0101, 0b1000, "32">;
340 // VLD4 : Vector Load (multiple 4-element structures)
341 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
342 : NLdSt<0, 0b10, op11_8, op7_4,
343 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
344 (ins addrmode6:$addr), IIC_VLD4,
345 "vld4", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
347 def VLD4d8 : VLD4D<0b0000, 0b0000, "8">;
348 def VLD4d16 : VLD4D<0b0000, 0b0100, "16">;
349 def VLD4d32 : VLD4D<0b0000, 0b1000, "32">;
351 // ...with address register writeback:
352 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
353 : NLdSt<0, 0b10, op11_8, op7_4,
354 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
355 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD4,
356 "vld4", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset",
357 "$addr.addr = $wb", []>;
359 def VLD4d8_UPD : VLD4DWB<0b0000, 0b0000, "8">;
360 def VLD4d16_UPD : VLD4DWB<0b0000, 0b0100, "16">;
361 def VLD4d32_UPD : VLD4DWB<0b0000, 0b1000, "32">;
363 // ...with double-spaced registers (non-updating versions for disassembly only):
364 def VLD4q8 : VLD4D<0b0001, 0b0000, "8">;
365 def VLD4q16 : VLD4D<0b0001, 0b0100, "16">;
366 def VLD4q32 : VLD4D<0b0001, 0b1000, "32">;
367 def VLD4q8_UPD : VLD4DWB<0b0001, 0b0000, "8">;
368 def VLD4q16_UPD : VLD4DWB<0b0001, 0b0100, "16">;
369 def VLD4q32_UPD : VLD4DWB<0b0001, 0b1000, "32">;
371 // ...alternate versions to be allocated odd register numbers:
372 def VLD4q8odd_UPD : VLD4DWB<0b0001, 0b0000, "8">;
373 def VLD4q16odd_UPD : VLD4DWB<0b0001, 0b0100, "16">;
374 def VLD4q32odd_UPD : VLD4DWB<0b0001, 0b1000, "32">;
376 // VLD1LN : Vector Load (single element to one lane)
377 // FIXME: Not yet implemented.
379 // VLD2LN : Vector Load (single 2-element structure to one lane)
380 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
381 : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2),
382 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
383 IIC_VLD2, "vld2", Dt, "\\{$dst1[$lane], $dst2[$lane]\\}, $addr",
384 "$src1 = $dst1, $src2 = $dst2", []>;
386 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8">;
387 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16">;
388 def VLD2LNd32 : VLD2LN<0b1001, {?,0,?,?}, "32">;
390 // ...with double-spaced registers:
391 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16">;
392 def VLD2LNq32 : VLD2LN<0b1001, {?,1,?,?}, "32">;
394 // ...alternate versions to be allocated odd register numbers:
395 def VLD2LNq16odd : VLD2LN<0b0101, {?,?,1,?}, "16">;
396 def VLD2LNq32odd : VLD2LN<0b1001, {?,1,?,?}, "32">;
398 // ...with address register writeback:
399 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
400 : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
401 (ins addrmode6:$addr, am6offset:$offset,
402 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2, "vld2", Dt,
403 "\\{$dst1[$lane], $dst2[$lane]\\}, $addr$offset",
404 "$src1 = $dst1, $src2 = $dst2, $addr.addr = $wb", []>;
406 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8">;
407 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16">;
408 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,?,?}, "32">;
410 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16">;
411 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,?,?}, "32">;
413 // VLD3LN : Vector Load (single 3-element structure to one lane)
414 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
415 : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
416 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
417 nohash_imm:$lane), IIC_VLD3, "vld3", Dt,
418 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr",
419 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
421 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8">;
422 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16">;
423 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32">;
425 // ...with double-spaced registers:
426 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16">;
427 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32">;
429 // ...alternate versions to be allocated odd register numbers:
430 def VLD3LNq16odd : VLD3LN<0b0110, {?,?,1,0}, "16">;
431 def VLD3LNq32odd : VLD3LN<0b1010, {?,1,0,0}, "32">;
433 // ...with address register writeback:
434 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
435 : NLdSt<1, 0b10, op11_8, op7_4,
436 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
437 (ins addrmode6:$addr, am6offset:$offset,
438 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
439 IIC_VLD3, "vld3", Dt,
440 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr$offset",
441 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $addr.addr = $wb",
444 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8">;
445 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16">;
446 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32">;
448 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16">;
449 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32">;
451 // VLD4LN : Vector Load (single 4-element structure to one lane)
452 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
453 : NLdSt<1, 0b10, op11_8, op7_4,
454 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
455 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
456 nohash_imm:$lane), IIC_VLD4, "vld4", Dt,
457 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr",
458 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
460 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8">;
461 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16">;
462 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32">;
464 // ...with double-spaced registers:
465 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16">;
466 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32">;
468 // ...alternate versions to be allocated odd register numbers:
469 def VLD4LNq16odd : VLD4LN<0b0111, {?,?,1,?}, "16">;
470 def VLD4LNq32odd : VLD4LN<0b1011, {?,1,?,?}, "32">;
472 // ...with address register writeback:
473 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
474 : NLdSt<1, 0b10, op11_8, op7_4,
475 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
476 (ins addrmode6:$addr, am6offset:$offset,
477 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
478 IIC_VLD4, "vld4", Dt,
479 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr$offset",
480 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $addr.addr = $wb",
483 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8">;
484 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16">;
485 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32">;
487 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16">;
488 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32">;
490 // VLD1DUP : Vector Load (single element to all lanes)
491 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
492 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
493 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
494 // FIXME: Not yet implemented.
495 } // mayLoad = 1, hasExtraDefRegAllocReq = 1
497 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
499 // VST1 : Vector Store (multiple single elements)
500 class VST1D<bits<4> op7_4, string Dt>
501 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src), IIC_VST,
502 "vst1", Dt, "\\{$src\\}, $addr", "", []>;
503 class VST1Q<bits<4> op7_4, string Dt>
504 : NLdSt<0,0b00,0b1010,op7_4, (outs),
505 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
506 "vst1", Dt, "\\{$src1, $src2\\}, $addr", "", []>;
508 def VST1d8 : VST1D<0b0000, "8">;
509 def VST1d16 : VST1D<0b0100, "16">;
510 def VST1d32 : VST1D<0b1000, "32">;
511 def VST1d64 : VST1D<0b1100, "64">;
513 def VST1q8 : VST1Q<0b0000, "8">;
514 def VST1q16 : VST1Q<0b0100, "16">;
515 def VST1q32 : VST1Q<0b1000, "32">;
516 def VST1q64 : VST1Q<0b1100, "64">;
518 // ...with address register writeback:
519 class VST1DWB<bits<4> op7_4, string Dt>
520 : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
521 (ins addrmode6:$addr, am6offset:$offset, DPR:$src), IIC_VST,
522 "vst1", Dt, "\\{$src\\}, $addr$offset", "$addr.addr = $wb", []>;
523 class VST1QWB<bits<4> op7_4, string Dt>
524 : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),
525 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), IIC_VST,
526 "vst1", Dt, "${src:dregpair}, $addr$offset", "$addr.addr = $wb", []>;
528 def VST1d8_UPD : VST1DWB<0b0000, "8">;
529 def VST1d16_UPD : VST1DWB<0b0100, "16">;
530 def VST1d32_UPD : VST1DWB<0b1000, "32">;
531 def VST1d64_UPD : VST1DWB<0b1100, "64">;
533 def VST1q8_UPD : VST1QWB<0b0000, "8">;
534 def VST1q16_UPD : VST1QWB<0b0100, "16">;
535 def VST1q32_UPD : VST1QWB<0b1000, "32">;
536 def VST1q64_UPD : VST1QWB<0b1100, "64">;
538 // ...with 3 registers (some of these are only for the disassembler):
539 class VST1D3<bits<4> op7_4, string Dt>
540 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
541 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
542 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>;
543 class VST1D3WB<bits<4> op7_4, string Dt>
544 : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
545 (ins addrmode6:$addr, am6offset:$offset,
546 DPR:$src1, DPR:$src2, DPR:$src3),
547 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr$offset",
548 "$addr.addr = $wb", []>;
550 def VST1d8T : VST1D3<0b0000, "8">;
551 def VST1d16T : VST1D3<0b0100, "16">;
552 def VST1d32T : VST1D3<0b1000, "32">;
553 def VST1d64T : VST1D3<0b1100, "64">;
555 def VST1d8T_UPD : VST1D3WB<0b0000, "8">;
556 def VST1d16T_UPD : VST1D3WB<0b0100, "16">;
557 def VST1d32T_UPD : VST1D3WB<0b1000, "32">;
558 def VST1d64T_UPD : VST1D3WB<0b1100, "64">;
560 // ...with 4 registers (some of these are only for the disassembler):
561 class VST1D4<bits<4> op7_4, string Dt>
562 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
563 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
564 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr", "",
566 class VST1D4WB<bits<4> op7_4, string Dt>
567 : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
568 (ins addrmode6:$addr, am6offset:$offset,
569 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
570 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
571 "$addr.addr = $wb", []>;
573 def VST1d8Q : VST1D4<0b0000, "8">;
574 def VST1d16Q : VST1D4<0b0100, "16">;
575 def VST1d32Q : VST1D4<0b1000, "32">;
576 def VST1d64Q : VST1D4<0b1100, "64">;
578 def VST1d8Q_UPD : VST1D4WB<0b0000, "8">;
579 def VST1d16Q_UPD : VST1D4WB<0b0100, "16">;
580 def VST1d32Q_UPD : VST1D4WB<0b1000, "32">;
581 def VST1d64Q_UPD : VST1D4WB<0b1100, "64">;
583 // VST2 : Vector Store (multiple 2-element structures)
584 class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
585 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
586 (ins addrmode6:$addr, DPR:$src1, DPR:$src2),
587 IIC_VST, "vst2", Dt, "\\{$src1, $src2\\}, $addr", "", []>;
588 class VST2Q<bits<4> op7_4, string Dt>
589 : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
590 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
591 IIC_VST, "vst2", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
594 def VST2d8 : VST2D<0b1000, 0b0000, "8">;
595 def VST2d16 : VST2D<0b1000, 0b0100, "16">;
596 def VST2d32 : VST2D<0b1000, 0b1000, "32">;
598 def VST2q8 : VST2Q<0b0000, "8">;
599 def VST2q16 : VST2Q<0b0100, "16">;
600 def VST2q32 : VST2Q<0b1000, "32">;
602 // ...with address register writeback:
603 class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
604 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
605 (ins addrmode6:$addr, am6offset:$offset, DPR:$src1, DPR:$src2),
606 IIC_VST, "vst2", Dt, "\\{$src1, $src2\\}, $addr$offset",
607 "$addr.addr = $wb", []>;
608 class VST2QWB<bits<4> op7_4, string Dt>
609 : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
610 (ins addrmode6:$addr, am6offset:$offset,
611 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
612 IIC_VST, "vst2", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
613 "$addr.addr = $wb", []>;
615 def VST2d8_UPD : VST2DWB<0b1000, 0b0000, "8">;
616 def VST2d16_UPD : VST2DWB<0b1000, 0b0100, "16">;
617 def VST2d32_UPD : VST2DWB<0b1000, 0b1000, "32">;
619 def VST2q8_UPD : VST2QWB<0b0000, "8">;
620 def VST2q16_UPD : VST2QWB<0b0100, "16">;
621 def VST2q32_UPD : VST2QWB<0b1000, "32">;
623 // ...with double-spaced registers (for disassembly only):
624 def VST2b8 : VST2D<0b1001, 0b0000, "8">;
625 def VST2b16 : VST2D<0b1001, 0b0100, "16">;
626 def VST2b32 : VST2D<0b1001, 0b1000, "32">;
627 def VST2b8_UPD : VST2DWB<0b1001, 0b0000, "8">;
628 def VST2b16_UPD : VST2DWB<0b1001, 0b0100, "16">;
629 def VST2b32_UPD : VST2DWB<0b1001, 0b1000, "32">;
631 // VST3 : Vector Store (multiple 3-element structures)
632 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
633 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
634 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
635 "vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>;
637 def VST3d8 : VST3D<0b0100, 0b0000, "8">;
638 def VST3d16 : VST3D<0b0100, 0b0100, "16">;
639 def VST3d32 : VST3D<0b0100, 0b1000, "32">;
641 // ...with address register writeback:
642 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
643 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
644 (ins addrmode6:$addr, am6offset:$offset,
645 DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
646 "vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr$offset",
647 "$addr.addr = $wb", []>;
649 def VST3d8_UPD : VST3DWB<0b0100, 0b0000, "8">;
650 def VST3d16_UPD : VST3DWB<0b0100, 0b0100, "16">;
651 def VST3d32_UPD : VST3DWB<0b0100, 0b1000, "32">;
653 // ...with double-spaced registers (non-updating versions for disassembly only):
654 def VST3q8 : VST3D<0b0101, 0b0000, "8">;
655 def VST3q16 : VST3D<0b0101, 0b0100, "16">;
656 def VST3q32 : VST3D<0b0101, 0b1000, "32">;
657 def VST3q8_UPD : VST3DWB<0b0101, 0b0000, "8">;
658 def VST3q16_UPD : VST3DWB<0b0101, 0b0100, "16">;
659 def VST3q32_UPD : VST3DWB<0b0101, 0b1000, "32">;
661 // ...alternate versions to be allocated odd register numbers:
662 def VST3q8odd_UPD : VST3DWB<0b0101, 0b0000, "8">;
663 def VST3q16odd_UPD : VST3DWB<0b0101, 0b0100, "16">;
664 def VST3q32odd_UPD : VST3DWB<0b0101, 0b1000, "32">;
666 // VST4 : Vector Store (multiple 4-element structures)
667 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
668 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
669 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
670 IIC_VST, "vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
673 def VST4d8 : VST4D<0b0000, 0b0000, "8">;
674 def VST4d16 : VST4D<0b0000, 0b0100, "16">;
675 def VST4d32 : VST4D<0b0000, 0b1000, "32">;
677 // ...with address register writeback:
678 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
679 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
680 (ins addrmode6:$addr, am6offset:$offset,
681 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST,
682 "vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
683 "$addr.addr = $wb", []>;
685 def VST4d8_UPD : VST4DWB<0b0000, 0b0000, "8">;
686 def VST4d16_UPD : VST4DWB<0b0000, 0b0100, "16">;
687 def VST4d32_UPD : VST4DWB<0b0000, 0b1000, "32">;
689 // ...with double-spaced registers (non-updating versions for disassembly only):
690 def VST4q8 : VST4D<0b0001, 0b0000, "8">;
691 def VST4q16 : VST4D<0b0001, 0b0100, "16">;
692 def VST4q32 : VST4D<0b0001, 0b1000, "32">;
693 def VST4q8_UPD : VST4DWB<0b0001, 0b0000, "8">;
694 def VST4q16_UPD : VST4DWB<0b0001, 0b0100, "16">;
695 def VST4q32_UPD : VST4DWB<0b0001, 0b1000, "32">;
697 // ...alternate versions to be allocated odd register numbers:
698 def VST4q8odd_UPD : VST4DWB<0b0001, 0b0000, "8">;
699 def VST4q16odd_UPD : VST4DWB<0b0001, 0b0100, "16">;
700 def VST4q32odd_UPD : VST4DWB<0b0001, 0b1000, "32">;
702 // VST1LN : Vector Store (single element from one lane)
703 // FIXME: Not yet implemented.
705 // VST2LN : Vector Store (single 2-element structure from one lane)
706 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
707 : NLdSt<1, 0b00, op11_8, op7_4, (outs),
708 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
709 IIC_VST, "vst2", Dt, "\\{$src1[$lane], $src2[$lane]\\}, $addr",
712 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8">;
713 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16">;
714 def VST2LNd32 : VST2LN<0b1001, {?,0,?,?}, "32">;
716 // ...with double-spaced registers:
717 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16">;
718 def VST2LNq32 : VST2LN<0b1001, {?,1,?,?}, "32">;
720 // ...alternate versions to be allocated odd register numbers:
721 def VST2LNq16odd : VST2LN<0b0101, {?,?,1,?}, "16">;
722 def VST2LNq32odd : VST2LN<0b1001, {?,1,?,?}, "32">;
724 // ...with address register writeback:
725 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
726 : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
727 (ins addrmode6:$addr, am6offset:$offset,
728 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST, "vst2", Dt,
729 "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset",
730 "$addr.addr = $wb", []>;
732 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8">;
733 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16">;
734 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,?,?}, "32">;
736 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16">;
737 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,?,?}, "32">;
739 // VST3LN : Vector Store (single 3-element structure from one lane)
740 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
741 : NLdSt<1, 0b00, op11_8, op7_4, (outs),
742 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
743 nohash_imm:$lane), IIC_VST, "vst3", Dt,
744 "\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr", "", []>;
746 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8">;
747 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16">;
748 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32">;
750 // ...with double-spaced registers:
751 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16">;
752 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32">;
754 // ...alternate versions to be allocated odd register numbers:
755 def VST3LNq16odd : VST3LN<0b0110, {?,?,1,0}, "16">;
756 def VST3LNq32odd : VST3LN<0b1010, {?,1,0,0}, "32">;
758 // ...with address register writeback:
759 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
760 : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
761 (ins addrmode6:$addr, am6offset:$offset,
762 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
764 "\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr$offset",
765 "$addr.addr = $wb", []>;
767 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8">;
768 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16">;
769 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32">;
771 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16">;
772 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32">;
774 // VST4LN : Vector Store (single 4-element structure from one lane)
775 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
776 : NLdSt<1, 0b00, op11_8, op7_4, (outs),
777 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
778 nohash_imm:$lane), IIC_VST, "vst4", Dt,
779 "\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr",
782 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8">;
783 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16">;
784 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32">;
786 // ...with double-spaced registers:
787 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16">;
788 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32">;
790 // ...alternate versions to be allocated odd register numbers:
791 def VST4LNq16odd : VST4LN<0b0111, {?,?,1,?}, "16">;
792 def VST4LNq32odd : VST4LN<0b1011, {?,1,?,?}, "32">;
794 // ...with address register writeback:
795 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
796 : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
797 (ins addrmode6:$addr, am6offset:$offset,
798 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
800 "\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr$offset",
801 "$addr.addr = $wb", []>;
803 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8">;
804 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16">;
805 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32">;
807 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16">;
808 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32">;
810 } // mayStore = 1, hasExtraSrcRegAllocReq = 1
813 //===----------------------------------------------------------------------===//
814 // NEON pattern fragments
815 //===----------------------------------------------------------------------===//
817 // Extract D sub-registers of Q registers.
818 // (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
819 def DSubReg_i8_reg : SDNodeXForm<imm, [{
820 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
822 def DSubReg_i16_reg : SDNodeXForm<imm, [{
823 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
825 def DSubReg_i32_reg : SDNodeXForm<imm, [{
826 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
828 def DSubReg_f64_reg : SDNodeXForm<imm, [{
829 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
831 def DSubReg_f64_other_reg : SDNodeXForm<imm, [{
832 return CurDAG->getTargetConstant(5 + (1 - N->getZExtValue()), MVT::i32);
835 // Extract S sub-registers of Q/D registers.
836 // (arm_ssubreg_0 is 1; arm_ssubreg_1 is 2; etc.)
837 def SSubReg_f32_reg : SDNodeXForm<imm, [{
838 return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32);
841 // Translate lane numbers from Q registers to D subregs.
842 def SubReg_i8_lane : SDNodeXForm<imm, [{
843 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
845 def SubReg_i16_lane : SDNodeXForm<imm, [{
846 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
848 def SubReg_i32_lane : SDNodeXForm<imm, [{
849 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
852 //===----------------------------------------------------------------------===//
853 // Instruction Classes
854 //===----------------------------------------------------------------------===//
856 // Basic 2-register operations: single-, double- and quad-register.
857 class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
858 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
859 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
860 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
861 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
862 IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
863 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
864 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
865 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
866 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
867 (ins DPR:$src), IIC_VUNAD, OpcodeStr, Dt,"$dst, $src", "",
868 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
869 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
870 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
871 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
872 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
873 (ins QPR:$src), IIC_VUNAQ, OpcodeStr, Dt,"$dst, $src", "",
874 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
876 // Basic 2-register intrinsics, both double- and quad-register.
877 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
878 bits<2> op17_16, bits<5> op11_7, bit op4,
879 InstrItinClass itin, string OpcodeStr, string Dt,
880 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
881 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
882 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
883 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
884 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
885 bits<2> op17_16, bits<5> op11_7, bit op4,
886 InstrItinClass itin, string OpcodeStr, string Dt,
887 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
888 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
889 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
890 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
892 // Narrow 2-register intrinsics.
893 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
894 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
895 InstrItinClass itin, string OpcodeStr, string Dt,
896 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
897 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
898 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
899 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
901 // Long 2-register intrinsics (currently only used for VMOVL).
902 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
903 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
904 InstrItinClass itin, string OpcodeStr, string Dt,
905 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
906 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$dst),
907 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
908 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
910 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
911 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
912 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
913 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
914 OpcodeStr, Dt, "$dst1, $dst2",
915 "$src1 = $dst1, $src2 = $dst2", []>;
916 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
917 InstrItinClass itin, string OpcodeStr, string Dt>
918 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
919 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$dst1, $dst2",
920 "$src1 = $dst1, $src2 = $dst2", []>;
922 // Basic 3-register operations: single-, double- and quad-register.
923 class N3VS<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
924 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
925 SDNode OpNode, bit Commutable>
926 : N3V<op24, op23, op21_20, op11_8, 0, op4,
927 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm,
928 IIC_VBIND, OpcodeStr, Dt, "$dst, $src1, $src2", "", []> {
929 let isCommutable = Commutable;
932 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
933 InstrItinClass itin, string OpcodeStr, string Dt,
934 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
935 : N3V<op24, op23, op21_20, op11_8, 0, op4,
936 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
937 OpcodeStr, Dt, "$dst, $src1, $src2", "",
938 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
939 let isCommutable = Commutable;
941 // Same as N3VD but no data type.
942 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
943 InstrItinClass itin, string OpcodeStr,
944 ValueType ResTy, ValueType OpTy,
945 SDNode OpNode, bit Commutable>
946 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
947 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
948 OpcodeStr, "$dst, $src1, $src2", "",
949 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]>{
950 let isCommutable = Commutable;
953 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
954 InstrItinClass itin, string OpcodeStr, string Dt,
955 ValueType Ty, SDNode ShOp>
956 : N3V<0, 1, op21_20, op11_8, 1, 0,
957 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
958 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
960 (Ty (ShOp (Ty DPR:$src1),
961 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),imm:$lane)))))]> {
962 let isCommutable = 0;
964 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
965 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
966 : N3V<0, 1, op21_20, op11_8, 1, 0,
967 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
968 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$dst, $src1, $src2[$lane]","",
970 (Ty (ShOp (Ty DPR:$src1),
971 (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
972 let isCommutable = 0;
975 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
976 InstrItinClass itin, string OpcodeStr, string Dt,
977 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
978 : N3V<op24, op23, op21_20, op11_8, 1, op4,
979 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, itin,
980 OpcodeStr, Dt, "$dst, $src1, $src2", "",
981 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
982 let isCommutable = Commutable;
984 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
985 InstrItinClass itin, string OpcodeStr,
986 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
987 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
988 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, itin,
989 OpcodeStr, "$dst, $src1, $src2", "",
990 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]>{
991 let isCommutable = Commutable;
993 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
994 InstrItinClass itin, string OpcodeStr, string Dt,
995 ValueType ResTy, ValueType OpTy, SDNode ShOp>
996 : N3V<1, 1, op21_20, op11_8, 1, 0,
997 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
998 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
999 [(set (ResTy QPR:$dst),
1000 (ResTy (ShOp (ResTy QPR:$src1),
1001 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1003 let isCommutable = 0;
1005 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
1006 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1007 : N3V<1, 1, op21_20, op11_8, 1, 0,
1008 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1009 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$dst, $src1, $src2[$lane]","",
1010 [(set (ResTy QPR:$dst),
1011 (ResTy (ShOp (ResTy QPR:$src1),
1012 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
1014 let isCommutable = 0;
1017 // Basic 3-register intrinsics, both double- and quad-register.
1018 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1019 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1020 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1021 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1022 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), f, itin,
1023 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1024 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
1025 let isCommutable = Commutable;
1027 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1028 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1029 : N3V<0, 1, op21_20, op11_8, 1, 0,
1030 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1031 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1032 [(set (Ty DPR:$dst),
1033 (Ty (IntOp (Ty DPR:$src1),
1034 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
1036 let isCommutable = 0;
1038 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1039 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1040 : N3V<0, 1, op21_20, op11_8, 1, 0,
1041 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1042 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1043 [(set (Ty DPR:$dst),
1044 (Ty (IntOp (Ty DPR:$src1),
1045 (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
1046 let isCommutable = 0;
1049 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1050 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1051 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1052 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1053 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), f, itin,
1054 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1055 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
1056 let isCommutable = Commutable;
1058 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1059 string OpcodeStr, string Dt,
1060 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1061 : N3V<1, 1, op21_20, op11_8, 1, 0,
1062 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1063 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1064 [(set (ResTy QPR:$dst),
1065 (ResTy (IntOp (ResTy QPR:$src1),
1066 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1068 let isCommutable = 0;
1070 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1071 string OpcodeStr, string Dt,
1072 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1073 : N3V<1, 1, op21_20, op11_8, 1, 0,
1074 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1075 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1076 [(set (ResTy QPR:$dst),
1077 (ResTy (IntOp (ResTy QPR:$src1),
1078 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
1080 let isCommutable = 0;
1083 // Multiply-Add/Sub operations: single-, double- and quad-register.
1084 class N3VSMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1085 InstrItinClass itin, string OpcodeStr, string Dt,
1086 ValueType Ty, SDNode MulOp, SDNode OpNode>
1087 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1088 (outs DPR_VFP2:$dst),
1089 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), N3RegFrm, itin,
1090 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst", []>;
1092 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1093 InstrItinClass itin, string OpcodeStr, string Dt,
1094 ValueType Ty, SDNode MulOp, SDNode OpNode>
1095 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1096 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1097 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1098 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
1099 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
1100 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1101 string OpcodeStr, string Dt,
1102 ValueType Ty, SDNode MulOp, SDNode ShOp>
1103 : N3V<0, 1, op21_20, op11_8, 1, 0,
1105 (ins DPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1107 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1108 [(set (Ty DPR:$dst),
1109 (Ty (ShOp (Ty DPR:$src1),
1110 (Ty (MulOp DPR:$src2,
1111 (Ty (NEONvduplane (Ty DPR_VFP2:$src3),
1113 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1114 string OpcodeStr, string Dt,
1115 ValueType Ty, SDNode MulOp, SDNode ShOp>
1116 : N3V<0, 1, op21_20, op11_8, 1, 0,
1118 (ins DPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1120 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1121 [(set (Ty DPR:$dst),
1122 (Ty (ShOp (Ty DPR:$src1),
1123 (Ty (MulOp DPR:$src2,
1124 (Ty (NEONvduplane (Ty DPR_8:$src3),
1127 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1128 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
1129 SDNode MulOp, SDNode OpNode>
1130 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1131 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), N3RegFrm, itin,
1132 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1133 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
1134 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
1135 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1136 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1137 SDNode MulOp, SDNode ShOp>
1138 : N3V<1, 1, op21_20, op11_8, 1, 0,
1140 (ins QPR:$src1, QPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1142 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1143 [(set (ResTy QPR:$dst),
1144 (ResTy (ShOp (ResTy QPR:$src1),
1145 (ResTy (MulOp QPR:$src2,
1146 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src3),
1148 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1149 string OpcodeStr, string Dt,
1150 ValueType ResTy, ValueType OpTy,
1151 SDNode MulOp, SDNode ShOp>
1152 : N3V<1, 1, op21_20, op11_8, 1, 0,
1154 (ins QPR:$src1, QPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1156 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1157 [(set (ResTy QPR:$dst),
1158 (ResTy (ShOp (ResTy QPR:$src1),
1159 (ResTy (MulOp QPR:$src2,
1160 (ResTy (NEONvduplane (OpTy DPR_8:$src3),
1163 // Neon 3-argument intrinsics, both double- and quad-register.
1164 // The destination register is also used as the first source operand register.
1165 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1166 InstrItinClass itin, string OpcodeStr, string Dt,
1167 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1168 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1169 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1170 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1171 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
1172 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
1173 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1174 InstrItinClass itin, string OpcodeStr, string Dt,
1175 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1176 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1177 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), N3RegFrm, itin,
1178 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1179 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
1180 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
1182 // Neon Long 3-argument intrinsic. The destination register is
1183 // a quad-register and is also used as the first source operand register.
1184 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1185 InstrItinClass itin, string OpcodeStr, string Dt,
1186 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
1187 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1188 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1189 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1191 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
1192 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1193 string OpcodeStr, string Dt,
1194 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1195 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1197 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1199 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1200 [(set (ResTy QPR:$dst),
1201 (ResTy (IntOp (ResTy QPR:$src1),
1203 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src3),
1205 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1206 InstrItinClass itin, string OpcodeStr, string Dt,
1207 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1208 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1210 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1212 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1213 [(set (ResTy QPR:$dst),
1214 (ResTy (IntOp (ResTy QPR:$src1),
1216 (OpTy (NEONvduplane (OpTy DPR_8:$src3),
1219 // Narrowing 3-register intrinsics.
1220 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1221 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
1222 Intrinsic IntOp, bit Commutable>
1223 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1224 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINi4D,
1225 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1226 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
1227 let isCommutable = Commutable;
1230 // Long 3-register intrinsics.
1231 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1232 InstrItinClass itin, string OpcodeStr, string Dt,
1233 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
1234 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1235 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1236 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1237 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
1238 let isCommutable = Commutable;
1240 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1241 string OpcodeStr, string Dt,
1242 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1243 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1244 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1245 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1246 [(set (ResTy QPR:$dst),
1247 (ResTy (IntOp (OpTy DPR:$src1),
1248 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1250 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1251 InstrItinClass itin, string OpcodeStr, string Dt,
1252 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1253 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1254 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1255 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1256 [(set (ResTy QPR:$dst),
1257 (ResTy (IntOp (OpTy DPR:$src1),
1258 (OpTy (NEONvduplane (OpTy DPR_8:$src2),
1261 // Wide 3-register intrinsics.
1262 class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1263 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
1264 Intrinsic IntOp, bit Commutable>
1265 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1266 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), N3RegFrm, IIC_VSUBiD,
1267 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1268 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
1269 let isCommutable = Commutable;
1272 // Pairwise long 2-register intrinsics, both double- and quad-register.
1273 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1274 bits<2> op17_16, bits<5> op11_7, bit op4,
1275 string OpcodeStr, string Dt,
1276 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1277 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1278 (ins DPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
1279 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
1280 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1281 bits<2> op17_16, bits<5> op11_7, bit op4,
1282 string OpcodeStr, string Dt,
1283 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1284 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1285 (ins QPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
1286 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
1288 // Pairwise long 2-register accumulate intrinsics,
1289 // both double- and quad-register.
1290 // The destination register is also used as the first source operand register.
1291 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1292 bits<2> op17_16, bits<5> op11_7, bit op4,
1293 string OpcodeStr, string Dt,
1294 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1295 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
1296 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), IIC_VPALiD,
1297 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
1298 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
1299 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1300 bits<2> op17_16, bits<5> op11_7, bit op4,
1301 string OpcodeStr, string Dt,
1302 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1303 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
1304 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VPALiQ,
1305 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
1306 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
1308 // Shift by immediate,
1309 // both double- and quad-register.
1310 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1311 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1312 ValueType Ty, SDNode OpNode>
1313 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1314 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), f, itin,
1315 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1316 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
1317 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1318 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1319 ValueType Ty, SDNode OpNode>
1320 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1321 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), f, itin,
1322 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1323 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
1325 // Long shift by immediate.
1326 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1327 string OpcodeStr, string Dt,
1328 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1329 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1330 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), N2RegVShLFrm,
1331 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1332 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
1333 (i32 imm:$SIMM))))]>;
1335 // Narrow shift by immediate.
1336 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1337 InstrItinClass itin, string OpcodeStr, string Dt,
1338 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1339 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1340 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), N2RegVShRFrm, itin,
1341 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1342 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
1343 (i32 imm:$SIMM))))]>;
1345 // Shift right by immediate and accumulate,
1346 // both double- and quad-register.
1347 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1348 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1349 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1350 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
1351 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1352 [(set DPR:$dst, (Ty (add DPR:$src1,
1353 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
1354 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1355 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1356 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1357 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
1358 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1359 [(set QPR:$dst, (Ty (add QPR:$src1,
1360 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
1362 // Shift by immediate and insert,
1363 // both double- and quad-register.
1364 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1365 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
1366 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1367 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), f, IIC_VSHLiD,
1368 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1369 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
1370 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1371 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
1372 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1373 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), f, IIC_VSHLiQ,
1374 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1375 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
1377 // Convert, with fractional bits immediate,
1378 // both double- and quad-register.
1379 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1380 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1382 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1383 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NVCVTFrm,
1384 IIC_VUNAD, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1385 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
1386 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1387 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1389 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1390 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NVCVTFrm,
1391 IIC_VUNAQ, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1392 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
1394 //===----------------------------------------------------------------------===//
1396 //===----------------------------------------------------------------------===//
1398 // Abbreviations used in multiclass suffixes:
1399 // Q = quarter int (8 bit) elements
1400 // H = half int (16 bit) elements
1401 // S = single int (32 bit) elements
1402 // D = double int (64 bit) elements
1404 // Neon 2-register vector operations -- for disassembly only.
1406 // First with only element sizes of 8, 16 and 32 bits:
1407 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1408 bits<5> op11_7, bit op4, string opc, string Dt,
1410 // 64-bit vector types.
1411 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
1412 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1413 opc, !strconcat(Dt, "8"), asm, "", []>;
1414 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
1415 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1416 opc, !strconcat(Dt, "16"), asm, "", []>;
1417 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
1418 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1419 opc, !strconcat(Dt, "32"), asm, "", []>;
1420 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
1421 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1422 opc, "f32", asm, "", []> {
1423 let Inst{10} = 1; // overwrite F = 1
1426 // 128-bit vector types.
1427 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
1428 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1429 opc, !strconcat(Dt, "8"), asm, "", []>;
1430 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
1431 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1432 opc, !strconcat(Dt, "16"), asm, "", []>;
1433 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
1434 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1435 opc, !strconcat(Dt, "32"), asm, "", []>;
1436 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
1437 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1438 opc, "f32", asm, "", []> {
1439 let Inst{10} = 1; // overwrite F = 1
1443 // Neon 3-register vector operations.
1445 // First with only element sizes of 8, 16 and 32 bits:
1446 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1447 InstrItinClass itinD16, InstrItinClass itinD32,
1448 InstrItinClass itinQ16, InstrItinClass itinQ32,
1449 string OpcodeStr, string Dt,
1450 SDNode OpNode, bit Commutable = 0> {
1451 // 64-bit vector types.
1452 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
1453 OpcodeStr, !strconcat(Dt, "8"),
1454 v8i8, v8i8, OpNode, Commutable>;
1455 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
1456 OpcodeStr, !strconcat(Dt, "16"),
1457 v4i16, v4i16, OpNode, Commutable>;
1458 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
1459 OpcodeStr, !strconcat(Dt, "32"),
1460 v2i32, v2i32, OpNode, Commutable>;
1462 // 128-bit vector types.
1463 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
1464 OpcodeStr, !strconcat(Dt, "8"),
1465 v16i8, v16i8, OpNode, Commutable>;
1466 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
1467 OpcodeStr, !strconcat(Dt, "16"),
1468 v8i16, v8i16, OpNode, Commutable>;
1469 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
1470 OpcodeStr, !strconcat(Dt, "32"),
1471 v4i32, v4i32, OpNode, Commutable>;
1474 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
1475 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1477 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
1479 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1480 v8i16, v4i16, ShOp>;
1481 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
1482 v4i32, v2i32, ShOp>;
1485 // ....then also with element size 64 bits:
1486 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1487 InstrItinClass itinD, InstrItinClass itinQ,
1488 string OpcodeStr, string Dt,
1489 SDNode OpNode, bit Commutable = 0>
1490 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
1491 OpcodeStr, Dt, OpNode, Commutable> {
1492 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
1493 OpcodeStr, !strconcat(Dt, "64"),
1494 v1i64, v1i64, OpNode, Commutable>;
1495 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
1496 OpcodeStr, !strconcat(Dt, "64"),
1497 v2i64, v2i64, OpNode, Commutable>;
1501 // Neon Narrowing 2-register vector intrinsics,
1502 // source operand element sizes of 16, 32 and 64 bits:
1503 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1504 bits<5> op11_7, bit op6, bit op4,
1505 InstrItinClass itin, string OpcodeStr, string Dt,
1507 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
1508 itin, OpcodeStr, !strconcat(Dt, "16"),
1509 v8i8, v8i16, IntOp>;
1510 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
1511 itin, OpcodeStr, !strconcat(Dt, "32"),
1512 v4i16, v4i32, IntOp>;
1513 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
1514 itin, OpcodeStr, !strconcat(Dt, "64"),
1515 v2i32, v2i64, IntOp>;
1519 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
1520 // source operand element sizes of 16, 32 and 64 bits:
1521 multiclass N2VLInt_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
1522 string OpcodeStr, string Dt, Intrinsic IntOp> {
1523 def v8i16 : N2VLInt<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1524 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
1525 def v4i32 : N2VLInt<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1526 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1527 def v2i64 : N2VLInt<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1528 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1532 // Neon 3-register vector intrinsics.
1534 // First with only element sizes of 16 and 32 bits:
1535 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
1536 InstrItinClass itinD16, InstrItinClass itinD32,
1537 InstrItinClass itinQ16, InstrItinClass itinQ32,
1538 string OpcodeStr, string Dt,
1539 Intrinsic IntOp, bit Commutable = 0> {
1540 // 64-bit vector types.
1541 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
1542 OpcodeStr, !strconcat(Dt, "16"),
1543 v4i16, v4i16, IntOp, Commutable>;
1544 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
1545 OpcodeStr, !strconcat(Dt, "32"),
1546 v2i32, v2i32, IntOp, Commutable>;
1548 // 128-bit vector types.
1549 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
1550 OpcodeStr, !strconcat(Dt, "16"),
1551 v8i16, v8i16, IntOp, Commutable>;
1552 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
1553 OpcodeStr, !strconcat(Dt, "32"),
1554 v4i32, v4i32, IntOp, Commutable>;
1557 multiclass N3VIntSL_HS<bits<4> op11_8,
1558 InstrItinClass itinD16, InstrItinClass itinD32,
1559 InstrItinClass itinQ16, InstrItinClass itinQ32,
1560 string OpcodeStr, string Dt, Intrinsic IntOp> {
1561 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
1562 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
1563 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
1564 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
1565 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
1566 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
1567 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
1568 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
1571 // ....then also with element size of 8 bits:
1572 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
1573 InstrItinClass itinD16, InstrItinClass itinD32,
1574 InstrItinClass itinQ16, InstrItinClass itinQ32,
1575 string OpcodeStr, string Dt,
1576 Intrinsic IntOp, bit Commutable = 0>
1577 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
1578 OpcodeStr, Dt, IntOp, Commutable> {
1579 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
1580 OpcodeStr, !strconcat(Dt, "8"),
1581 v8i8, v8i8, IntOp, Commutable>;
1582 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
1583 OpcodeStr, !strconcat(Dt, "8"),
1584 v16i8, v16i8, IntOp, Commutable>;
1587 // ....then also with element size of 64 bits:
1588 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
1589 InstrItinClass itinD16, InstrItinClass itinD32,
1590 InstrItinClass itinQ16, InstrItinClass itinQ32,
1591 string OpcodeStr, string Dt,
1592 Intrinsic IntOp, bit Commutable = 0>
1593 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
1594 OpcodeStr, Dt, IntOp, Commutable> {
1595 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
1596 OpcodeStr, !strconcat(Dt, "64"),
1597 v1i64, v1i64, IntOp, Commutable>;
1598 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
1599 OpcodeStr, !strconcat(Dt, "64"),
1600 v2i64, v2i64, IntOp, Commutable>;
1603 // Neon Narrowing 3-register vector intrinsics,
1604 // source operand element sizes of 16, 32 and 64 bits:
1605 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1606 string OpcodeStr, string Dt,
1607 Intrinsic IntOp, bit Commutable = 0> {
1608 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
1609 OpcodeStr, !strconcat(Dt, "16"),
1610 v8i8, v8i16, IntOp, Commutable>;
1611 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
1612 OpcodeStr, !strconcat(Dt, "32"),
1613 v4i16, v4i32, IntOp, Commutable>;
1614 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
1615 OpcodeStr, !strconcat(Dt, "64"),
1616 v2i32, v2i64, IntOp, Commutable>;
1620 // Neon Long 3-register vector intrinsics.
1622 // First with only element sizes of 16 and 32 bits:
1623 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1624 InstrItinClass itin, string OpcodeStr, string Dt,
1625 Intrinsic IntOp, bit Commutable = 0> {
1626 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin,
1627 OpcodeStr, !strconcat(Dt, "16"),
1628 v4i32, v4i16, IntOp, Commutable>;
1629 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin,
1630 OpcodeStr, !strconcat(Dt, "32"),
1631 v2i64, v2i32, IntOp, Commutable>;
1634 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
1635 InstrItinClass itin, string OpcodeStr, string Dt,
1637 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
1638 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1639 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
1640 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1643 // ....then also with element size of 8 bits:
1644 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1645 InstrItinClass itin, string OpcodeStr, string Dt,
1646 Intrinsic IntOp, bit Commutable = 0>
1647 : N3VLInt_HS<op24, op23, op11_8, op4, itin, OpcodeStr, Dt,
1648 IntOp, Commutable> {
1649 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin,
1650 OpcodeStr, !strconcat(Dt, "8"),
1651 v8i16, v8i8, IntOp, Commutable>;
1655 // Neon Wide 3-register vector intrinsics,
1656 // source operand element sizes of 8, 16 and 32 bits:
1657 multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1658 string OpcodeStr, string Dt,
1659 Intrinsic IntOp, bit Commutable = 0> {
1660 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4,
1661 OpcodeStr, !strconcat(Dt, "8"),
1662 v8i16, v8i8, IntOp, Commutable>;
1663 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4,
1664 OpcodeStr, !strconcat(Dt, "16"),
1665 v4i32, v4i16, IntOp, Commutable>;
1666 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4,
1667 OpcodeStr, !strconcat(Dt, "32"),
1668 v2i64, v2i32, IntOp, Commutable>;
1672 // Neon Multiply-Op vector operations,
1673 // element sizes of 8, 16 and 32 bits:
1674 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1675 InstrItinClass itinD16, InstrItinClass itinD32,
1676 InstrItinClass itinQ16, InstrItinClass itinQ32,
1677 string OpcodeStr, string Dt, SDNode OpNode> {
1678 // 64-bit vector types.
1679 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
1680 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
1681 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
1682 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
1683 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
1684 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
1686 // 128-bit vector types.
1687 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
1688 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
1689 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
1690 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
1691 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
1692 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
1695 multiclass N3VMulOpSL_HS<bits<4> op11_8,
1696 InstrItinClass itinD16, InstrItinClass itinD32,
1697 InstrItinClass itinQ16, InstrItinClass itinQ32,
1698 string OpcodeStr, string Dt, SDNode ShOp> {
1699 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
1700 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
1701 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
1702 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
1703 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
1704 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
1706 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
1707 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
1711 // Neon 3-argument intrinsics,
1712 // element sizes of 8, 16 and 32 bits:
1713 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1714 string OpcodeStr, string Dt, Intrinsic IntOp> {
1715 // 64-bit vector types.
1716 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16D,
1717 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
1718 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
1719 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
1720 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32D,
1721 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
1723 // 128-bit vector types.
1724 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16Q,
1725 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
1726 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16Q,
1727 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
1728 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32Q,
1729 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
1733 // Neon Long 3-argument intrinsics.
1735 // First with only element sizes of 16 and 32 bits:
1736 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1737 string OpcodeStr, string Dt, Intrinsic IntOp> {
1738 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
1739 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1740 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi16D,
1741 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1744 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
1745 string OpcodeStr, string Dt, Intrinsic IntOp> {
1746 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
1747 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
1748 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
1749 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1752 // ....then also with element size of 8 bits:
1753 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1754 string OpcodeStr, string Dt, Intrinsic IntOp>
1755 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, Dt, IntOp> {
1756 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16D,
1757 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
1761 // Neon 2-register vector intrinsics,
1762 // element sizes of 8, 16 and 32 bits:
1763 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1764 bits<5> op11_7, bit op4,
1765 InstrItinClass itinD, InstrItinClass itinQ,
1766 string OpcodeStr, string Dt, Intrinsic IntOp> {
1767 // 64-bit vector types.
1768 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1769 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
1770 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1771 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
1772 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1773 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
1775 // 128-bit vector types.
1776 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1777 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
1778 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1779 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
1780 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1781 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
1785 // Neon Pairwise long 2-register intrinsics,
1786 // element sizes of 8, 16 and 32 bits:
1787 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1788 bits<5> op11_7, bit op4,
1789 string OpcodeStr, string Dt, Intrinsic IntOp> {
1790 // 64-bit vector types.
1791 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1792 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
1793 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1794 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
1795 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1796 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
1798 // 128-bit vector types.
1799 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1800 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
1801 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1802 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
1803 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1804 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
1808 // Neon Pairwise long 2-register accumulate intrinsics,
1809 // element sizes of 8, 16 and 32 bits:
1810 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1811 bits<5> op11_7, bit op4,
1812 string OpcodeStr, string Dt, Intrinsic IntOp> {
1813 // 64-bit vector types.
1814 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1815 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
1816 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1817 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
1818 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1819 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
1821 // 128-bit vector types.
1822 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1823 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
1824 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1825 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
1826 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1827 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
1831 // Neon 2-register vector shift by immediate,
1832 // with f of either N2RegVShLFrm or N2RegVShRFrm
1833 // element sizes of 8, 16, 32 and 64 bits:
1834 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1835 InstrItinClass itin, string OpcodeStr, string Dt,
1836 SDNode OpNode, Format f> {
1837 // 64-bit vector types.
1838 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
1839 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
1840 let Inst{21-19} = 0b001; // imm6 = 001xxx
1842 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
1843 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
1844 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1846 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
1847 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
1848 let Inst{21} = 0b1; // imm6 = 1xxxxx
1850 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, f, itin,
1851 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
1854 // 128-bit vector types.
1855 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
1856 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
1857 let Inst{21-19} = 0b001; // imm6 = 001xxx
1859 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
1860 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
1861 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1863 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
1864 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
1865 let Inst{21} = 0b1; // imm6 = 1xxxxx
1867 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, f, itin,
1868 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
1872 // Neon Shift-Accumulate vector operations,
1873 // element sizes of 8, 16, 32 and 64 bits:
1874 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1875 string OpcodeStr, string Dt, SDNode ShOp> {
1876 // 64-bit vector types.
1877 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1878 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
1879 let Inst{21-19} = 0b001; // imm6 = 001xxx
1881 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1882 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
1883 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1885 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1886 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
1887 let Inst{21} = 0b1; // imm6 = 1xxxxx
1889 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4,
1890 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
1893 // 128-bit vector types.
1894 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1895 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
1896 let Inst{21-19} = 0b001; // imm6 = 001xxx
1898 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1899 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
1900 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1902 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1903 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
1904 let Inst{21} = 0b1; // imm6 = 1xxxxx
1906 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4,
1907 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
1912 // Neon Shift-Insert vector operations,
1913 // with f of either N2RegVShLFrm or N2RegVShRFrm
1914 // element sizes of 8, 16, 32 and 64 bits:
1915 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1916 string OpcodeStr, SDNode ShOp,
1918 // 64-bit vector types.
1919 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4,
1920 f, OpcodeStr, "8", v8i8, ShOp> {
1921 let Inst{21-19} = 0b001; // imm6 = 001xxx
1923 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4,
1924 f, OpcodeStr, "16", v4i16, ShOp> {
1925 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1927 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4,
1928 f, OpcodeStr, "32", v2i32, ShOp> {
1929 let Inst{21} = 0b1; // imm6 = 1xxxxx
1931 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4,
1932 f, OpcodeStr, "64", v1i64, ShOp>;
1935 // 128-bit vector types.
1936 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4,
1937 f, OpcodeStr, "8", v16i8, ShOp> {
1938 let Inst{21-19} = 0b001; // imm6 = 001xxx
1940 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4,
1941 f, OpcodeStr, "16", v8i16, ShOp> {
1942 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1944 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4,
1945 f, OpcodeStr, "32", v4i32, ShOp> {
1946 let Inst{21} = 0b1; // imm6 = 1xxxxx
1948 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4,
1949 f, OpcodeStr, "64", v2i64, ShOp>;
1953 // Neon Shift Long operations,
1954 // element sizes of 8, 16, 32 bits:
1955 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
1956 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
1957 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1958 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
1959 let Inst{21-19} = 0b001; // imm6 = 001xxx
1961 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1962 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
1963 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1965 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1966 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
1967 let Inst{21} = 0b1; // imm6 = 1xxxxx
1971 // Neon Shift Narrow operations,
1972 // element sizes of 16, 32, 64 bits:
1973 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
1974 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
1976 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1977 OpcodeStr, !strconcat(Dt, "16"), v8i8, v8i16, OpNode> {
1978 let Inst{21-19} = 0b001; // imm6 = 001xxx
1980 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1981 OpcodeStr, !strconcat(Dt, "32"), v4i16, v4i32, OpNode> {
1982 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1984 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1985 OpcodeStr, !strconcat(Dt, "64"), v2i32, v2i64, OpNode> {
1986 let Inst{21} = 0b1; // imm6 = 1xxxxx
1990 //===----------------------------------------------------------------------===//
1991 // Instruction Definitions.
1992 //===----------------------------------------------------------------------===//
1994 // Vector Add Operations.
1996 // VADD : Vector Add (integer and floating-point)
1997 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
1999 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
2000 v2f32, v2f32, fadd, 1>;
2001 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
2002 v4f32, v4f32, fadd, 1>;
2003 // VADDL : Vector Add Long (Q = D + D)
2004 defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, IIC_VSHLiD, "vaddl", "s",
2005 int_arm_neon_vaddls, 1>;
2006 defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, IIC_VSHLiD, "vaddl", "u",
2007 int_arm_neon_vaddlu, 1>;
2008 // VADDW : Vector Add Wide (Q = Q + D)
2009 defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw", "s", int_arm_neon_vaddws, 0>;
2010 defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw", "u", int_arm_neon_vaddwu, 0>;
2011 // VHADD : Vector Halving Add
2012 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
2013 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2014 "vhadd", "s", int_arm_neon_vhadds, 1>;
2015 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
2016 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2017 "vhadd", "u", int_arm_neon_vhaddu, 1>;
2018 // VRHADD : Vector Rounding Halving Add
2019 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
2020 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2021 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
2022 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
2023 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2024 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
2025 // VQADD : Vector Saturating Add
2026 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
2027 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2028 "vqadd", "s", int_arm_neon_vqadds, 1>;
2029 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
2030 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2031 "vqadd", "u", int_arm_neon_vqaddu, 1>;
2032 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
2033 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
2034 int_arm_neon_vaddhn, 1>;
2035 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
2036 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
2037 int_arm_neon_vraddhn, 1>;
2039 // Vector Multiply Operations.
2041 // VMUL : Vector Multiply (integer, polynomial and floating-point)
2042 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
2043 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
2044 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
2045 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
2046 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
2047 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
2048 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VBIND, "vmul", "f32",
2049 v2f32, v2f32, fmul, 1>;
2050 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VBINQ, "vmul", "f32",
2051 v4f32, v4f32, fmul, 1>;
2052 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
2053 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
2054 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
2057 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
2058 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
2059 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
2060 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2061 (DSubReg_i16_reg imm:$lane))),
2062 (SubReg_i16_lane imm:$lane)))>;
2063 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
2064 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
2065 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
2066 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2067 (DSubReg_i32_reg imm:$lane))),
2068 (SubReg_i32_lane imm:$lane)))>;
2069 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
2070 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
2071 (v4f32 (VMULslfq (v4f32 QPR:$src1),
2072 (v2f32 (EXTRACT_SUBREG QPR:$src2,
2073 (DSubReg_i32_reg imm:$lane))),
2074 (SubReg_i32_lane imm:$lane)))>;
2076 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
2077 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
2078 IIC_VMULi16Q, IIC_VMULi32Q,
2079 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
2080 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
2081 IIC_VMULi16Q, IIC_VMULi32Q,
2082 "vqdmulh", "s", int_arm_neon_vqdmulh>;
2083 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
2084 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
2086 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
2087 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2088 (DSubReg_i16_reg imm:$lane))),
2089 (SubReg_i16_lane imm:$lane)))>;
2090 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
2091 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
2093 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
2094 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2095 (DSubReg_i32_reg imm:$lane))),
2096 (SubReg_i32_lane imm:$lane)))>;
2098 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
2099 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
2100 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
2101 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
2102 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
2103 IIC_VMULi16Q, IIC_VMULi32Q,
2104 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
2105 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
2106 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
2108 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
2109 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2110 (DSubReg_i16_reg imm:$lane))),
2111 (SubReg_i16_lane imm:$lane)))>;
2112 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
2113 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
2115 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
2116 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2117 (DSubReg_i32_reg imm:$lane))),
2118 (SubReg_i32_lane imm:$lane)))>;
2120 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
2121 defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, IIC_VMULi16D, "vmull", "s",
2122 int_arm_neon_vmulls, 1>;
2123 defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, IIC_VMULi16D, "vmull", "u",
2124 int_arm_neon_vmullu, 1>;
2125 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
2126 v8i16, v8i8, int_arm_neon_vmullp, 1>;
2127 defm VMULLsls : N3VLIntSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s",
2128 int_arm_neon_vmulls>;
2129 defm VMULLslu : N3VLIntSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u",
2130 int_arm_neon_vmullu>;
2132 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
2133 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, "vqdmull", "s",
2134 int_arm_neon_vqdmull, 1>;
2135 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D, "vqdmull", "s",
2136 int_arm_neon_vqdmull>;
2138 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
2140 // VMLA : Vector Multiply Accumulate (integer and floating-point)
2141 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
2142 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
2143 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
2145 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
2147 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
2148 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
2149 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
2151 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
2152 v4f32, v2f32, fmul, fadd>;
2154 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
2155 (mul (v8i16 QPR:$src2),
2156 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
2157 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
2158 (v4i16 (EXTRACT_SUBREG QPR:$src3,
2159 (DSubReg_i16_reg imm:$lane))),
2160 (SubReg_i16_lane imm:$lane)))>;
2162 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
2163 (mul (v4i32 QPR:$src2),
2164 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
2165 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
2166 (v2i32 (EXTRACT_SUBREG QPR:$src3,
2167 (DSubReg_i32_reg imm:$lane))),
2168 (SubReg_i32_lane imm:$lane)))>;
2170 def : Pat<(v4f32 (fadd (v4f32 QPR:$src1),
2171 (fmul (v4f32 QPR:$src2),
2172 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
2173 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
2175 (v2f32 (EXTRACT_SUBREG QPR:$src3,
2176 (DSubReg_i32_reg imm:$lane))),
2177 (SubReg_i32_lane imm:$lane)))>;
2179 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
2180 defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal", "s", int_arm_neon_vmlals>;
2181 defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal", "u", int_arm_neon_vmlalu>;
2183 defm VMLALsls : N3VLInt3SL_HS<0, 0b0010, "vmlal", "s", int_arm_neon_vmlals>;
2184 defm VMLALslu : N3VLInt3SL_HS<1, 0b0010, "vmlal", "u", int_arm_neon_vmlalu>;
2186 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
2187 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal", "s",
2188 int_arm_neon_vqdmlal>;
2189 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
2191 // VMLS : Vector Multiply Subtract (integer and floating-point)
2192 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
2193 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
2194 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
2196 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
2198 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
2199 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
2200 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
2202 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
2203 v4f32, v2f32, fmul, fsub>;
2205 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
2206 (mul (v8i16 QPR:$src2),
2207 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
2208 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
2209 (v4i16 (EXTRACT_SUBREG QPR:$src3,
2210 (DSubReg_i16_reg imm:$lane))),
2211 (SubReg_i16_lane imm:$lane)))>;
2213 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
2214 (mul (v4i32 QPR:$src2),
2215 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
2216 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
2217 (v2i32 (EXTRACT_SUBREG QPR:$src3,
2218 (DSubReg_i32_reg imm:$lane))),
2219 (SubReg_i32_lane imm:$lane)))>;
2221 def : Pat<(v4f32 (fsub (v4f32 QPR:$src1),
2222 (fmul (v4f32 QPR:$src2),
2223 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
2224 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
2225 (v2f32 (EXTRACT_SUBREG QPR:$src3,
2226 (DSubReg_i32_reg imm:$lane))),
2227 (SubReg_i32_lane imm:$lane)))>;
2229 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
2230 defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl", "s", int_arm_neon_vmlsls>;
2231 defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl", "u", int_arm_neon_vmlslu>;
2233 defm VMLSLsls : N3VLInt3SL_HS<0, 0b0110, "vmlsl", "s", int_arm_neon_vmlsls>;
2234 defm VMLSLslu : N3VLInt3SL_HS<1, 0b0110, "vmlsl", "u", int_arm_neon_vmlslu>;
2236 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
2237 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl", "s",
2238 int_arm_neon_vqdmlsl>;
2239 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
2241 // Vector Subtract Operations.
2243 // VSUB : Vector Subtract (integer and floating-point)
2244 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
2245 "vsub", "i", sub, 0>;
2246 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
2247 v2f32, v2f32, fsub, 0>;
2248 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
2249 v4f32, v4f32, fsub, 0>;
2250 // VSUBL : Vector Subtract Long (Q = D - D)
2251 defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, IIC_VSHLiD, "vsubl", "s",
2252 int_arm_neon_vsubls, 1>;
2253 defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, IIC_VSHLiD, "vsubl", "u",
2254 int_arm_neon_vsublu, 1>;
2255 // VSUBW : Vector Subtract Wide (Q = Q - D)
2256 defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw", "s", int_arm_neon_vsubws, 0>;
2257 defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw", "u", int_arm_neon_vsubwu, 0>;
2258 // VHSUB : Vector Halving Subtract
2259 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
2260 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2261 "vhsub", "s", int_arm_neon_vhsubs, 0>;
2262 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
2263 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2264 "vhsub", "u", int_arm_neon_vhsubu, 0>;
2265 // VQSUB : Vector Saturing Subtract
2266 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
2267 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2268 "vqsub", "s", int_arm_neon_vqsubs, 0>;
2269 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
2270 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2271 "vqsub", "u", int_arm_neon_vqsubu, 0>;
2272 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
2273 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
2274 int_arm_neon_vsubhn, 0>;
2275 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
2276 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
2277 int_arm_neon_vrsubhn, 0>;
2279 // Vector Comparisons.
2281 // VCEQ : Vector Compare Equal
2282 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2283 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
2284 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
2286 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
2288 // For disassembly only.
2289 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
2292 // VCGE : Vector Compare Greater Than or Equal
2293 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2294 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
2295 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2296 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
2297 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
2299 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
2301 // For disassembly only.
2302 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
2304 // For disassembly only.
2305 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
2308 // VCGT : Vector Compare Greater Than
2309 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2310 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
2311 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2312 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
2313 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
2315 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
2317 // For disassembly only.
2318 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
2320 // For disassembly only.
2321 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
2324 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
2325 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
2326 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
2327 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
2328 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
2329 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
2330 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
2331 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
2332 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
2333 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
2334 // VTST : Vector Test Bits
2335 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2336 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
2338 // Vector Bitwise Operations.
2340 def vnot8 : PatFrag<(ops node:$in),
2341 (xor node:$in, (bitconvert (v8i8 immAllOnesV)))>;
2342 def vnot16 : PatFrag<(ops node:$in),
2343 (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>;
2346 // VAND : Vector Bitwise AND
2347 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
2348 v2i32, v2i32, and, 1>;
2349 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
2350 v4i32, v4i32, and, 1>;
2352 // VEOR : Vector Bitwise Exclusive OR
2353 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
2354 v2i32, v2i32, xor, 1>;
2355 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
2356 v4i32, v4i32, xor, 1>;
2358 // VORR : Vector Bitwise OR
2359 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
2360 v2i32, v2i32, or, 1>;
2361 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
2362 v4i32, v4i32, or, 1>;
2364 // VBIC : Vector Bitwise Bit Clear (AND NOT)
2365 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2366 (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD,
2367 "vbic", "$dst, $src1, $src2", "",
2368 [(set DPR:$dst, (v2i32 (and DPR:$src1,
2369 (vnot8 DPR:$src2))))]>;
2370 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2371 (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINiQ,
2372 "vbic", "$dst, $src1, $src2", "",
2373 [(set QPR:$dst, (v4i32 (and QPR:$src1,
2374 (vnot16 QPR:$src2))))]>;
2376 // VORN : Vector Bitwise OR NOT
2377 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
2378 (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD,
2379 "vorn", "$dst, $src1, $src2", "",
2380 [(set DPR:$dst, (v2i32 (or DPR:$src1,
2381 (vnot8 DPR:$src2))))]>;
2382 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
2383 (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINiQ,
2384 "vorn", "$dst, $src1, $src2", "",
2385 [(set QPR:$dst, (v4i32 (or QPR:$src1,
2386 (vnot16 QPR:$src2))))]>;
2388 // VMVN : Vector Bitwise NOT
2389 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
2390 (outs DPR:$dst), (ins DPR:$src), IIC_VSHLiD,
2391 "vmvn", "$dst, $src", "",
2392 [(set DPR:$dst, (v2i32 (vnot8 DPR:$src)))]>;
2393 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
2394 (outs QPR:$dst), (ins QPR:$src), IIC_VSHLiD,
2395 "vmvn", "$dst, $src", "",
2396 [(set QPR:$dst, (v4i32 (vnot16 QPR:$src)))]>;
2397 def : Pat<(v2i32 (vnot8 DPR:$src)), (VMVNd DPR:$src)>;
2398 def : Pat<(v4i32 (vnot16 QPR:$src)), (VMVNq QPR:$src)>;
2400 // VBSL : Vector Bitwise Select
2401 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2402 (ins DPR:$src1, DPR:$src2, DPR:$src3),
2403 N3RegFrm, IIC_VCNTiD,
2404 "vbsl", "$dst, $src2, $src3", "$src1 = $dst",
2406 (v2i32 (or (and DPR:$src2, DPR:$src1),
2407 (and DPR:$src3, (vnot8 DPR:$src1)))))]>;
2408 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2409 (ins QPR:$src1, QPR:$src2, QPR:$src3),
2410 N3RegFrm, IIC_VCNTiQ,
2411 "vbsl", "$dst, $src2, $src3", "$src1 = $dst",
2413 (v4i32 (or (and QPR:$src2, QPR:$src1),
2414 (and QPR:$src3, (vnot16 QPR:$src1)))))]>;
2416 // VBIF : Vector Bitwise Insert if False
2417 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
2418 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
2419 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
2420 N3RegFrm, IIC_VBINiD,
2421 "vbif", "$dst, $src2, $src3", "$src1 = $dst",
2422 [/* For disassembly only; pattern left blank */]>;
2423 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
2424 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
2425 N3RegFrm, IIC_VBINiQ,
2426 "vbif", "$dst, $src2, $src3", "$src1 = $dst",
2427 [/* For disassembly only; pattern left blank */]>;
2429 // VBIT : Vector Bitwise Insert if True
2430 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
2431 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
2432 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
2433 N3RegFrm, IIC_VBINiD,
2434 "vbit", "$dst, $src2, $src3", "$src1 = $dst",
2435 [/* For disassembly only; pattern left blank */]>;
2436 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
2437 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
2438 N3RegFrm, IIC_VBINiQ,
2439 "vbit", "$dst, $src2, $src3", "$src1 = $dst",
2440 [/* For disassembly only; pattern left blank */]>;
2442 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
2443 // for equivalent operations with different register constraints; it just
2446 // Vector Absolute Differences.
2448 // VABD : Vector Absolute Difference
2449 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
2450 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2451 "vabd", "s", int_arm_neon_vabds, 0>;
2452 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
2453 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2454 "vabd", "u", int_arm_neon_vabdu, 0>;
2455 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
2456 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 0>;
2457 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
2458 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 0>;
2460 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
2461 defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
2462 "vabdl", "s", int_arm_neon_vabdls, 0>;
2463 defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
2464 "vabdl", "u", int_arm_neon_vabdlu, 0>;
2466 // VABA : Vector Absolute Difference and Accumulate
2467 defm VABAs : N3VInt3_QHS<0,0,0b0111,1, "vaba", "s", int_arm_neon_vabas>;
2468 defm VABAu : N3VInt3_QHS<1,0,0b0111,1, "vaba", "u", int_arm_neon_vabau>;
2470 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
2471 defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal", "s", int_arm_neon_vabals>;
2472 defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal", "u", int_arm_neon_vabalu>;
2474 // Vector Maximum and Minimum.
2476 // VMAX : Vector Maximum
2477 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
2478 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2479 "vmax", "s", int_arm_neon_vmaxs, 1>;
2480 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
2481 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2482 "vmax", "u", int_arm_neon_vmaxu, 1>;
2483 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
2485 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
2486 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
2488 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
2490 // VMIN : Vector Minimum
2491 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
2492 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2493 "vmin", "s", int_arm_neon_vmins, 1>;
2494 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
2495 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2496 "vmin", "u", int_arm_neon_vminu, 1>;
2497 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
2499 v2f32, v2f32, int_arm_neon_vmins, 1>;
2500 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
2502 v4f32, v4f32, int_arm_neon_vmins, 1>;
2504 // Vector Pairwise Operations.
2506 // VPADD : Vector Pairwise Add
2507 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
2509 v8i8, v8i8, int_arm_neon_vpadd, 0>;
2510 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
2512 v4i16, v4i16, int_arm_neon_vpadd, 0>;
2513 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
2515 v2i32, v2i32, int_arm_neon_vpadd, 0>;
2516 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
2517 IIC_VBIND, "vpadd", "f32",
2518 v2f32, v2f32, int_arm_neon_vpadd, 0>;
2520 // VPADDL : Vector Pairwise Add Long
2521 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
2522 int_arm_neon_vpaddls>;
2523 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
2524 int_arm_neon_vpaddlu>;
2526 // VPADAL : Vector Pairwise Add and Accumulate Long
2527 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
2528 int_arm_neon_vpadals>;
2529 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
2530 int_arm_neon_vpadalu>;
2532 // VPMAX : Vector Pairwise Maximum
2533 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2534 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
2535 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2536 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
2537 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2538 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
2539 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2540 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
2541 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2542 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
2543 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2544 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
2545 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2546 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
2548 // VPMIN : Vector Pairwise Minimum
2549 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2550 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
2551 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2552 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
2553 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2554 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
2555 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2556 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
2557 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2558 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
2559 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2560 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
2561 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VSUBi4D, "vpmin",
2562 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
2564 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
2566 // VRECPE : Vector Reciprocal Estimate
2567 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
2568 IIC_VUNAD, "vrecpe", "u32",
2569 v2i32, v2i32, int_arm_neon_vrecpe>;
2570 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
2571 IIC_VUNAQ, "vrecpe", "u32",
2572 v4i32, v4i32, int_arm_neon_vrecpe>;
2573 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
2574 IIC_VUNAD, "vrecpe", "f32",
2575 v2f32, v2f32, int_arm_neon_vrecpe>;
2576 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
2577 IIC_VUNAQ, "vrecpe", "f32",
2578 v4f32, v4f32, int_arm_neon_vrecpe>;
2580 // VRECPS : Vector Reciprocal Step
2581 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
2582 IIC_VRECSD, "vrecps", "f32",
2583 v2f32, v2f32, int_arm_neon_vrecps, 1>;
2584 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
2585 IIC_VRECSQ, "vrecps", "f32",
2586 v4f32, v4f32, int_arm_neon_vrecps, 1>;
2588 // VRSQRTE : Vector Reciprocal Square Root Estimate
2589 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
2590 IIC_VUNAD, "vrsqrte", "u32",
2591 v2i32, v2i32, int_arm_neon_vrsqrte>;
2592 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
2593 IIC_VUNAQ, "vrsqrte", "u32",
2594 v4i32, v4i32, int_arm_neon_vrsqrte>;
2595 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
2596 IIC_VUNAD, "vrsqrte", "f32",
2597 v2f32, v2f32, int_arm_neon_vrsqrte>;
2598 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
2599 IIC_VUNAQ, "vrsqrte", "f32",
2600 v4f32, v4f32, int_arm_neon_vrsqrte>;
2602 // VRSQRTS : Vector Reciprocal Square Root Step
2603 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
2604 IIC_VRECSD, "vrsqrts", "f32",
2605 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
2606 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
2607 IIC_VRECSQ, "vrsqrts", "f32",
2608 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
2612 // VSHL : Vector Shift
2613 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, N3RegVShFrm,
2614 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
2615 "vshl", "s", int_arm_neon_vshifts, 0>;
2616 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, N3RegVShFrm,
2617 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
2618 "vshl", "u", int_arm_neon_vshiftu, 0>;
2619 // VSHL : Vector Shift Left (Immediate)
2620 defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl,
2622 // VSHR : Vector Shift Right (Immediate)
2623 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", NEONvshrs,
2625 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", NEONvshru,
2628 // VSHLL : Vector Shift Left Long
2629 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
2630 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
2632 // VSHLL : Vector Shift Left Long (with maximum shift count)
2633 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
2634 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
2635 ValueType OpTy, SDNode OpNode>
2636 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
2637 ResTy, OpTy, OpNode> {
2638 let Inst{21-16} = op21_16;
2640 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
2641 v8i16, v8i8, NEONvshlli>;
2642 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
2643 v4i32, v4i16, NEONvshlli>;
2644 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
2645 v2i64, v2i32, NEONvshlli>;
2647 // VSHRN : Vector Shift Right and Narrow
2648 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
2651 // VRSHL : Vector Rounding Shift
2652 defm VRSHLs : N3VInt_QHSD<0, 0, 0b0101, 0, N3RegVShFrm,
2653 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
2654 "vrshl", "s", int_arm_neon_vrshifts, 0>;
2655 defm VRSHLu : N3VInt_QHSD<1, 0, 0b0101, 0, N3RegVShFrm,
2656 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
2657 "vrshl", "u", int_arm_neon_vrshiftu, 0>;
2658 // VRSHR : Vector Rounding Shift Right
2659 defm VRSHRs : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs,
2661 defm VRSHRu : N2VSh_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", NEONvrshru,
2664 // VRSHRN : Vector Rounding Shift Right and Narrow
2665 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
2668 // VQSHL : Vector Saturating Shift
2669 defm VQSHLs : N3VInt_QHSD<0, 0, 0b0100, 1, N3RegVShFrm,
2670 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
2671 "vqshl", "s", int_arm_neon_vqshifts, 0>;
2672 defm VQSHLu : N3VInt_QHSD<1, 0, 0b0100, 1, N3RegVShFrm,
2673 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
2674 "vqshl", "u", int_arm_neon_vqshiftu, 0>;
2675 // VQSHL : Vector Saturating Shift Left (Immediate)
2676 defm VQSHLsi : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls,
2678 defm VQSHLui : N2VSh_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu,
2680 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
2681 defm VQSHLsu : N2VSh_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu,
2684 // VQSHRN : Vector Saturating Shift Right and Narrow
2685 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
2687 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
2690 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
2691 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
2694 // VQRSHL : Vector Saturating Rounding Shift
2695 defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, N3RegVShFrm,
2696 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
2697 "vqrshl", "s", int_arm_neon_vqrshifts, 0>;
2698 defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, N3RegVShFrm,
2699 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
2700 "vqrshl", "u", int_arm_neon_vqrshiftu, 0>;
2702 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
2703 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
2705 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
2708 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
2709 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
2712 // VSRA : Vector Shift Right and Accumulate
2713 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
2714 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
2715 // VRSRA : Vector Rounding Shift Right and Accumulate
2716 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
2717 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
2719 // VSLI : Vector Shift Left and Insert
2720 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli", NEONvsli, N2RegVShLFrm>;
2721 // VSRI : Vector Shift Right and Insert
2722 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri", NEONvsri, N2RegVShRFrm>;
2724 // Vector Absolute and Saturating Absolute.
2726 // VABS : Vector Absolute Value
2727 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
2728 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
2730 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2731 IIC_VUNAD, "vabs", "f32",
2732 v2f32, v2f32, int_arm_neon_vabs>;
2733 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2734 IIC_VUNAQ, "vabs", "f32",
2735 v4f32, v4f32, int_arm_neon_vabs>;
2737 // VQABS : Vector Saturating Absolute Value
2738 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
2739 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
2740 int_arm_neon_vqabs>;
2744 def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
2745 def vneg8 : PatFrag<(ops node:$in),
2746 (sub (bitconvert (v8i8 immAllZerosV)), node:$in)>;
2747 def vneg16 : PatFrag<(ops node:$in),
2748 (sub (bitconvert (v16i8 immAllZerosV)), node:$in)>;
2750 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
2751 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
2752 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
2753 [(set DPR:$dst, (Ty (vneg8 DPR:$src)))]>;
2754 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
2755 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
2756 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
2757 [(set QPR:$dst, (Ty (vneg16 QPR:$src)))]>;
2759 // VNEG : Vector Negate (integer)
2760 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
2761 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
2762 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
2763 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
2764 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
2765 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
2767 // VNEG : Vector Negate (floating-point)
2768 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
2769 (outs DPR:$dst), (ins DPR:$src), IIC_VUNAD,
2770 "vneg", "f32", "$dst, $src", "",
2771 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
2772 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
2773 (outs QPR:$dst), (ins QPR:$src), IIC_VUNAQ,
2774 "vneg", "f32", "$dst, $src", "",
2775 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
2777 def : Pat<(v8i8 (vneg8 DPR:$src)), (VNEGs8d DPR:$src)>;
2778 def : Pat<(v4i16 (vneg8 DPR:$src)), (VNEGs16d DPR:$src)>;
2779 def : Pat<(v2i32 (vneg8 DPR:$src)), (VNEGs32d DPR:$src)>;
2780 def : Pat<(v16i8 (vneg16 QPR:$src)), (VNEGs8q QPR:$src)>;
2781 def : Pat<(v8i16 (vneg16 QPR:$src)), (VNEGs16q QPR:$src)>;
2782 def : Pat<(v4i32 (vneg16 QPR:$src)), (VNEGs32q QPR:$src)>;
2784 // VQNEG : Vector Saturating Negate
2785 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
2786 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
2787 int_arm_neon_vqneg>;
2789 // Vector Bit Counting Operations.
2791 // VCLS : Vector Count Leading Sign Bits
2792 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
2793 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
2795 // VCLZ : Vector Count Leading Zeros
2796 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
2797 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
2799 // VCNT : Vector Count One Bits
2800 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2801 IIC_VCNTiD, "vcnt", "8",
2802 v8i8, v8i8, int_arm_neon_vcnt>;
2803 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2804 IIC_VCNTiQ, "vcnt", "8",
2805 v16i8, v16i8, int_arm_neon_vcnt>;
2807 // Vector Swap -- for disassembly only.
2808 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
2809 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
2810 "vswp", "$dst, $src", "", []>;
2811 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
2812 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
2813 "vswp", "$dst, $src", "", []>;
2815 // Vector Move Operations.
2817 // VMOV : Vector Move (Register)
2819 def VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
2820 N3RegFrm, IIC_VMOVD, "vmov", "$dst, $src", "", []>;
2821 def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
2822 N3RegFrm, IIC_VMOVD, "vmov", "$dst, $src", "", []>;
2824 // VMOV : Vector Move (Immediate)
2826 // VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
2827 def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
2828 return ARM::getVMOVImm(N, 1, *CurDAG);
2830 def vmovImm8 : PatLeaf<(build_vector), [{
2831 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
2834 // VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
2835 def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
2836 return ARM::getVMOVImm(N, 2, *CurDAG);
2838 def vmovImm16 : PatLeaf<(build_vector), [{
2839 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
2840 }], VMOV_get_imm16>;
2842 // VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
2843 def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
2844 return ARM::getVMOVImm(N, 4, *CurDAG);
2846 def vmovImm32 : PatLeaf<(build_vector), [{
2847 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
2848 }], VMOV_get_imm32>;
2850 // VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
2851 def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
2852 return ARM::getVMOVImm(N, 8, *CurDAG);
2854 def vmovImm64 : PatLeaf<(build_vector), [{
2855 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
2856 }], VMOV_get_imm64>;
2858 // Note: Some of the cmode bits in the following VMOV instructions need to
2859 // be encoded based on the immed values.
2861 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
2862 (ins h8imm:$SIMM), IIC_VMOVImm,
2863 "vmov", "i8", "$dst, $SIMM", "",
2864 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
2865 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
2866 (ins h8imm:$SIMM), IIC_VMOVImm,
2867 "vmov", "i8", "$dst, $SIMM", "",
2868 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
2870 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,?}, 0, 0, {?}, 1, (outs DPR:$dst),
2871 (ins h16imm:$SIMM), IIC_VMOVImm,
2872 "vmov", "i16", "$dst, $SIMM", "",
2873 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
2874 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,?}, 0, 1, {?}, 1, (outs QPR:$dst),
2875 (ins h16imm:$SIMM), IIC_VMOVImm,
2876 "vmov", "i16", "$dst, $SIMM", "",
2877 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
2879 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, {?}, 1, (outs DPR:$dst),
2880 (ins h32imm:$SIMM), IIC_VMOVImm,
2881 "vmov", "i32", "$dst, $SIMM", "",
2882 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
2883 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, {?}, 1, (outs QPR:$dst),
2884 (ins h32imm:$SIMM), IIC_VMOVImm,
2885 "vmov", "i32", "$dst, $SIMM", "",
2886 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
2888 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
2889 (ins h64imm:$SIMM), IIC_VMOVImm,
2890 "vmov", "i64", "$dst, $SIMM", "",
2891 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
2892 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
2893 (ins h64imm:$SIMM), IIC_VMOVImm,
2894 "vmov", "i64", "$dst, $SIMM", "",
2895 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
2897 // VMOV : Vector Get Lane (move scalar to ARM core register)
2899 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
2900 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2901 IIC_VMOVSI, "vmov", "s8", "$dst, $src[$lane]",
2902 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
2904 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
2905 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2906 IIC_VMOVSI, "vmov", "s16", "$dst, $src[$lane]",
2907 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
2909 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
2910 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2911 IIC_VMOVSI, "vmov", "u8", "$dst, $src[$lane]",
2912 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
2914 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
2915 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2916 IIC_VMOVSI, "vmov", "u16", "$dst, $src[$lane]",
2917 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
2919 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
2920 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2921 IIC_VMOVSI, "vmov", "32", "$dst, $src[$lane]",
2922 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
2924 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
2925 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
2926 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2927 (DSubReg_i8_reg imm:$lane))),
2928 (SubReg_i8_lane imm:$lane))>;
2929 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
2930 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2931 (DSubReg_i16_reg imm:$lane))),
2932 (SubReg_i16_lane imm:$lane))>;
2933 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
2934 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2935 (DSubReg_i8_reg imm:$lane))),
2936 (SubReg_i8_lane imm:$lane))>;
2937 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
2938 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2939 (DSubReg_i16_reg imm:$lane))),
2940 (SubReg_i16_lane imm:$lane))>;
2941 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
2942 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
2943 (DSubReg_i32_reg imm:$lane))),
2944 (SubReg_i32_lane imm:$lane))>;
2945 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
2946 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
2947 (SSubReg_f32_reg imm:$src2))>;
2948 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
2949 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
2950 (SSubReg_f32_reg imm:$src2))>;
2951 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
2952 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2953 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
2954 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2957 // VMOV : Vector Set Lane (move ARM core register to scalar)
2959 let Constraints = "$src1 = $dst" in {
2960 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$dst),
2961 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2962 IIC_VMOVISL, "vmov", "8", "$dst[$lane], $src2",
2963 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
2964 GPR:$src2, imm:$lane))]>;
2965 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$dst),
2966 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2967 IIC_VMOVISL, "vmov", "16", "$dst[$lane], $src2",
2968 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
2969 GPR:$src2, imm:$lane))]>;
2970 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$dst),
2971 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2972 IIC_VMOVISL, "vmov", "32", "$dst[$lane], $src2",
2973 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
2974 GPR:$src2, imm:$lane))]>;
2976 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
2977 (v16i8 (INSERT_SUBREG QPR:$src1,
2978 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
2979 (DSubReg_i8_reg imm:$lane))),
2980 GPR:$src2, (SubReg_i8_lane imm:$lane))),
2981 (DSubReg_i8_reg imm:$lane)))>;
2982 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
2983 (v8i16 (INSERT_SUBREG QPR:$src1,
2984 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
2985 (DSubReg_i16_reg imm:$lane))),
2986 GPR:$src2, (SubReg_i16_lane imm:$lane))),
2987 (DSubReg_i16_reg imm:$lane)))>;
2988 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
2989 (v4i32 (INSERT_SUBREG QPR:$src1,
2990 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
2991 (DSubReg_i32_reg imm:$lane))),
2992 GPR:$src2, (SubReg_i32_lane imm:$lane))),
2993 (DSubReg_i32_reg imm:$lane)))>;
2995 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
2996 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
2997 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
2998 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
2999 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
3000 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
3002 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
3003 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
3004 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
3005 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
3007 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
3008 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
3009 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
3010 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, arm_dsubreg_0)>;
3011 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
3012 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
3014 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
3015 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
3016 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
3017 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
3018 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
3019 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
3021 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
3022 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3023 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
3025 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
3026 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
3027 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
3029 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
3030 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3031 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
3034 // VDUP : Vector Duplicate (from ARM core register to all elements)
3036 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
3037 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
3038 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
3039 [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
3040 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
3041 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
3042 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
3043 [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
3045 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
3046 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
3047 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
3048 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
3049 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
3050 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
3052 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
3053 IIC_VMOVIS, "vdup", "32", "$dst, $src",
3054 [(set DPR:$dst, (v2f32 (NEONvdup
3055 (f32 (bitconvert GPR:$src)))))]>;
3056 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
3057 IIC_VMOVIS, "vdup", "32", "$dst, $src",
3058 [(set QPR:$dst, (v4f32 (NEONvdup
3059 (f32 (bitconvert GPR:$src)))))]>;
3061 // VDUP : Vector Duplicate Lane (from scalar to all elements)
3063 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
3065 : NVDupLane<op19_16, 0, (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3066 IIC_VMOVD, OpcodeStr, Dt, "$dst, $src[$lane]",
3067 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
3069 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
3070 ValueType ResTy, ValueType OpTy>
3071 : NVDupLane<op19_16, 1, (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3072 IIC_VMOVD, OpcodeStr, Dt, "$dst, $src[$lane]",
3073 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src),
3076 // Inst{19-16} is partially specified depending on the element size.
3078 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8>;
3079 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16>;
3080 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32>;
3081 def VDUPLNfd : VDUPLND<{?,1,0,0}, "vdup", "32", v2f32>;
3082 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8>;
3083 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16>;
3084 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32>;
3085 def VDUPLNfq : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4f32, v2f32>;
3087 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
3088 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
3089 (DSubReg_i8_reg imm:$lane))),
3090 (SubReg_i8_lane imm:$lane)))>;
3091 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
3092 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
3093 (DSubReg_i16_reg imm:$lane))),
3094 (SubReg_i16_lane imm:$lane)))>;
3095 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
3096 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
3097 (DSubReg_i32_reg imm:$lane))),
3098 (SubReg_i32_lane imm:$lane)))>;
3099 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
3100 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
3101 (DSubReg_i32_reg imm:$lane))),
3102 (SubReg_i32_lane imm:$lane)))>;
3104 def VDUPfdf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 0, 0,
3105 (outs DPR:$dst), (ins SPR:$src),
3106 IIC_VMOVD, "vdup", "32", "$dst, ${src:lane}", "",
3107 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
3109 def VDUPfqf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 1, 0,
3110 (outs QPR:$dst), (ins SPR:$src),
3111 IIC_VMOVD, "vdup", "32", "$dst, ${src:lane}", "",
3112 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
3114 def : Pat<(v2i64 (NEONvduplane (v2i64 QPR:$src), imm:$lane)),
3115 (INSERT_SUBREG QPR:$src,
3116 (i64 (EXTRACT_SUBREG QPR:$src,
3117 (DSubReg_f64_reg imm:$lane))),
3118 (DSubReg_f64_other_reg imm:$lane))>;
3119 def : Pat<(v2f64 (NEONvduplane (v2f64 QPR:$src), imm:$lane)),
3120 (INSERT_SUBREG QPR:$src,
3121 (f64 (EXTRACT_SUBREG QPR:$src,
3122 (DSubReg_f64_reg imm:$lane))),
3123 (DSubReg_f64_other_reg imm:$lane))>;
3125 // VMOVN : Vector Narrowing Move
3126 defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVD,
3127 "vmovn", "i", int_arm_neon_vmovn>;
3128 // VQMOVN : Vector Saturating Narrowing Move
3129 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
3130 "vqmovn", "s", int_arm_neon_vqmovns>;
3131 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
3132 "vqmovn", "u", int_arm_neon_vqmovnu>;
3133 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
3134 "vqmovun", "s", int_arm_neon_vqmovnsu>;
3135 // VMOVL : Vector Lengthening Move
3136 defm VMOVLs : N2VLInt_QHS<0b01,0b10100,0,1, "vmovl", "s",
3137 int_arm_neon_vmovls>;
3138 defm VMOVLu : N2VLInt_QHS<0b11,0b10100,0,1, "vmovl", "u",
3139 int_arm_neon_vmovlu>;
3141 // Vector Conversions.
3143 // VCVT : Vector Convert Between Floating-Point and Integers
3144 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3145 v2i32, v2f32, fp_to_sint>;
3146 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3147 v2i32, v2f32, fp_to_uint>;
3148 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3149 v2f32, v2i32, sint_to_fp>;
3150 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3151 v2f32, v2i32, uint_to_fp>;
3153 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3154 v4i32, v4f32, fp_to_sint>;
3155 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3156 v4i32, v4f32, fp_to_uint>;
3157 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3158 v4f32, v4i32, sint_to_fp>;
3159 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3160 v4f32, v4i32, uint_to_fp>;
3162 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
3163 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
3164 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
3165 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
3166 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
3167 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
3168 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
3169 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
3170 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
3172 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
3173 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
3174 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
3175 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
3176 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
3177 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
3178 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
3179 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
3183 // VREV64 : Vector Reverse elements within 64-bit doublewords
3185 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3186 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
3187 (ins DPR:$src), IIC_VMOVD,
3188 OpcodeStr, Dt, "$dst, $src", "",
3189 [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
3190 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3191 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
3192 (ins QPR:$src), IIC_VMOVD,
3193 OpcodeStr, Dt, "$dst, $src", "",
3194 [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
3196 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
3197 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
3198 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
3199 def VREV64df : VREV64D<0b10, "vrev64", "32", v2f32>;
3201 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
3202 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
3203 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
3204 def VREV64qf : VREV64Q<0b10, "vrev64", "32", v4f32>;
3206 // VREV32 : Vector Reverse elements within 32-bit words
3208 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3209 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
3210 (ins DPR:$src), IIC_VMOVD,
3211 OpcodeStr, Dt, "$dst, $src", "",
3212 [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
3213 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3214 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
3215 (ins QPR:$src), IIC_VMOVD,
3216 OpcodeStr, Dt, "$dst, $src", "",
3217 [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
3219 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
3220 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
3222 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
3223 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
3225 // VREV16 : Vector Reverse elements within 16-bit halfwords
3227 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3228 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
3229 (ins DPR:$src), IIC_VMOVD,
3230 OpcodeStr, Dt, "$dst, $src", "",
3231 [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
3232 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3233 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
3234 (ins QPR:$src), IIC_VMOVD,
3235 OpcodeStr, Dt, "$dst, $src", "",
3236 [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
3238 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
3239 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
3241 // Other Vector Shuffles.
3243 // VEXT : Vector Extract
3245 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
3246 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$dst),
3247 (ins DPR:$lhs, DPR:$rhs, i32imm:$index), NVExtFrm,
3248 IIC_VEXTD, OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
3249 [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
3250 (Ty DPR:$rhs), imm:$index)))]>;
3252 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
3253 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$dst),
3254 (ins QPR:$lhs, QPR:$rhs, i32imm:$index), NVExtFrm,
3255 IIC_VEXTQ, OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
3256 [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
3257 (Ty QPR:$rhs), imm:$index)))]>;
3259 def VEXTd8 : VEXTd<"vext", "8", v8i8>;
3260 def VEXTd16 : VEXTd<"vext", "16", v4i16>;
3261 def VEXTd32 : VEXTd<"vext", "32", v2i32>;
3262 def VEXTdf : VEXTd<"vext", "32", v2f32>;
3264 def VEXTq8 : VEXTq<"vext", "8", v16i8>;
3265 def VEXTq16 : VEXTq<"vext", "16", v8i16>;
3266 def VEXTq32 : VEXTq<"vext", "32", v4i32>;
3267 def VEXTqf : VEXTq<"vext", "32", v4f32>;
3269 // VTRN : Vector Transpose
3271 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
3272 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
3273 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
3275 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
3276 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
3277 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
3279 // VUZP : Vector Unzip (Deinterleave)
3281 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
3282 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
3283 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
3285 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
3286 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
3287 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
3289 // VZIP : Vector Zip (Interleave)
3291 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
3292 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
3293 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
3295 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
3296 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
3297 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
3299 // Vector Table Lookup and Table Extension.
3301 // VTBL : Vector Table Lookup
3303 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
3304 (ins DPR:$tbl1, DPR:$src), NVTBLFrm, IIC_VTB1,
3305 "vtbl", "8", "$dst, \\{$tbl1\\}, $src", "",
3306 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
3307 let hasExtraSrcRegAllocReq = 1 in {
3309 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
3310 (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), NVTBLFrm, IIC_VTB2,
3311 "vtbl", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "",
3312 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl2
3313 DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
3315 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
3316 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), NVTBLFrm, IIC_VTB3,
3317 "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src", "",
3318 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl3
3319 DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
3321 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
3322 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src),
3324 "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src", "",
3325 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl4 DPR:$tbl1, DPR:$tbl2,
3326 DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
3327 } // hasExtraSrcRegAllocReq = 1
3329 // VTBX : Vector Table Extension
3331 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
3332 (ins DPR:$orig, DPR:$tbl1, DPR:$src), NVTBLFrm, IIC_VTBX1,
3333 "vtbx", "8", "$dst, \\{$tbl1\\}, $src", "$orig = $dst",
3334 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
3335 DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
3336 let hasExtraSrcRegAllocReq = 1 in {
3338 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
3339 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), NVTBLFrm, IIC_VTBX2,
3340 "vtbx", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "$orig = $dst",
3341 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx2
3342 DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
3344 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
3345 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src),
3346 NVTBLFrm, IIC_VTBX3,
3347 "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src", "$orig = $dst",
3348 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx3 DPR:$orig, DPR:$tbl1,
3349 DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
3351 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
3352 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), NVTBLFrm, IIC_VTBX4,
3353 "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src",
3355 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx4 DPR:$orig, DPR:$tbl1,
3356 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
3357 } // hasExtraSrcRegAllocReq = 1
3359 //===----------------------------------------------------------------------===//
3360 // NEON instructions for single-precision FP math
3361 //===----------------------------------------------------------------------===//
3363 class N2VSPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
3364 : NEONFPPat<(ResTy (OpNode SPR:$a)),
3365 (EXTRACT_SUBREG (OpTy (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)),
3366 SPR:$a, arm_ssubreg_0))),
3369 class N3VSPat<SDNode OpNode, NeonI Inst>
3370 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
3371 (EXTRACT_SUBREG (v2f32
3372 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3373 SPR:$a, arm_ssubreg_0),
3374 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3375 SPR:$b, arm_ssubreg_0))),
3378 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
3379 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
3380 (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3381 SPR:$acc, arm_ssubreg_0),
3382 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3383 SPR:$a, arm_ssubreg_0),
3384 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3385 SPR:$b, arm_ssubreg_0)),
3388 // These need separate instructions because they must use DPR_VFP2 register
3389 // class which have SPR sub-registers.
3391 // Vector Add Operations used for single-precision FP
3392 let neverHasSideEffects = 1 in
3393 def VADDfd_sfp : N3VS<0,0,0b00,0b1101,0, "vadd", "f32", v2f32, v2f32, fadd, 1>;
3394 def : N3VSPat<fadd, VADDfd_sfp>;
3396 // Vector Sub Operations used for single-precision FP
3397 let neverHasSideEffects = 1 in
3398 def VSUBfd_sfp : N3VS<0,0,0b10,0b1101,0, "vsub", "f32", v2f32, v2f32, fsub, 0>;
3399 def : N3VSPat<fsub, VSUBfd_sfp>;
3401 // Vector Multiply Operations used for single-precision FP
3402 let neverHasSideEffects = 1 in
3403 def VMULfd_sfp : N3VS<1,0,0b00,0b1101,1, "vmul", "f32", v2f32, v2f32, fmul, 1>;
3404 def : N3VSPat<fmul, VMULfd_sfp>;
3406 // Vector Multiply-Accumulate/Subtract used for single-precision FP
3407 // vml[as].f32 can cause 4-8 cycle stalls in following ASIMD instructions, so
3408 // we want to avoid them for now. e.g., alternating vmla/vadd instructions.
3410 //let neverHasSideEffects = 1 in
3411 //def VMLAfd_sfp : N3VSMulOp<0,0,0b00,0b1101,1, IIC_VMACD, "vmla", "f32",
3412 // v2f32, fmul, fadd>;
3413 //def : N3VSMulOpPat<fmul, fadd, VMLAfd_sfp>;
3415 //let neverHasSideEffects = 1 in
3416 //def VMLSfd_sfp : N3VSMulOp<0,0,0b10,0b1101,1, IIC_VMACD, "vmls", "f32",
3417 // v2f32, fmul, fsub>;
3418 //def : N3VSMulOpPat<fmul, fsub, VMLSfd_sfp>;
3420 // Vector Absolute used for single-precision FP
3421 let neverHasSideEffects = 1 in
3422 def VABSfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01110, 0, 0,
3423 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
3424 "vabs", "f32", "$dst, $src", "", []>;
3425 def : N2VSPat<fabs, f32, v2f32, VABSfd_sfp>;
3427 // Vector Negate used for single-precision FP
3428 let neverHasSideEffects = 1 in
3429 def VNEGfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
3430 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
3431 "vneg", "f32", "$dst, $src", "", []>;
3432 def : N2VSPat<fneg, f32, v2f32, VNEGfd_sfp>;
3434 // Vector Maximum used for single-precision FP
3435 let neverHasSideEffects = 1 in
3436 def VMAXfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
3437 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm, IIC_VBIND,
3438 "vmax", "f32", "$dst, $src1, $src2", "", []>;
3439 def : N3VSPat<NEONfmax, VMAXfd_sfp>;
3441 // Vector Minimum used for single-precision FP
3442 let neverHasSideEffects = 1 in
3443 def VMINfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
3444 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm, IIC_VBIND,
3445 "vmin", "f32", "$dst, $src1, $src2", "", []>;
3446 def : N3VSPat<NEONfmin, VMINfd_sfp>;
3448 // Vector Convert between single-precision FP and integer
3449 let neverHasSideEffects = 1 in
3450 def VCVTf2sd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3451 v2i32, v2f32, fp_to_sint>;
3452 def : N2VSPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
3454 let neverHasSideEffects = 1 in
3455 def VCVTf2ud_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3456 v2i32, v2f32, fp_to_uint>;
3457 def : N2VSPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
3459 let neverHasSideEffects = 1 in
3460 def VCVTs2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3461 v2f32, v2i32, sint_to_fp>;
3462 def : N2VSPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
3464 let neverHasSideEffects = 1 in
3465 def VCVTu2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3466 v2f32, v2i32, uint_to_fp>;
3467 def : N2VSPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
3469 //===----------------------------------------------------------------------===//
3470 // Non-Instruction Patterns
3471 //===----------------------------------------------------------------------===//
3474 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
3475 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
3476 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
3477 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
3478 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
3479 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
3480 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
3481 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
3482 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
3483 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
3484 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
3485 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
3486 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
3487 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
3488 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
3489 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
3490 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
3491 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
3492 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
3493 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
3494 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
3495 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
3496 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
3497 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
3498 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
3499 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
3500 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
3501 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
3502 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
3503 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
3505 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
3506 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
3507 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
3508 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
3509 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
3510 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
3511 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
3512 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
3513 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
3514 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
3515 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
3516 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
3517 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
3518 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
3519 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
3520 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
3521 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
3522 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
3523 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
3524 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
3525 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
3526 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
3527 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
3528 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
3529 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
3530 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
3531 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
3532 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
3533 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
3534 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;